1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988, 1989, 1991 Free Software Foundation, Inc.
4 This file is part of GDB.
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
21 * 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
26 * The main tables describing the instructions is essentially a copy
27 * of the "Opcode Map" chapter (Appendix A) of the Intel 80386
28 * Programmers Manual. Usually, there is a capital letter, followed
29 * by a small letter. The capital letter tell the addressing mode,
30 * and the small letter tells about the operand size. Refer to
31 * the Intel manual for details.
38 /* For the GDB interface at the bottom of the file... */
41 #define Eb OP_E, b_mode
42 #define indirEb OP_indirE, b_mode
43 #define Gb OP_G, b_mode
44 #define Ev OP_E, v_mode
45 #define indirEv OP_indirE, v_mode
46 #define Ew OP_E, w_mode
47 #define Ma OP_E, v_mode
49 #define Mp OP_E, 0 /* ? */
50 #define Gv OP_G, v_mode
51 #define Gw OP_G, w_mode
52 #define Rw OP_rm, w_mode
53 #define Rd OP_rm, d_mode
54 #define Ib OP_I, b_mode
55 #define sIb OP_sI, b_mode /* sign extened byte */
56 #define Iv OP_I, v_mode
57 #define Iw OP_I, w_mode
58 #define Jb OP_J, b_mode
59 #define Jv OP_J, v_mode
61 #define Cd OP_C, d_mode
62 #define Dd OP_D, d_mode
63 #define Td OP_T, d_mode
65 #define eAX OP_REG, eAX_reg
66 #define eBX OP_REG, eBX_reg
67 #define eCX OP_REG, eCX_reg
68 #define eDX OP_REG, eDX_reg
69 #define eSP OP_REG, eSP_reg
70 #define eBP OP_REG, eBP_reg
71 #define eSI OP_REG, eSI_reg
72 #define eDI OP_REG, eDI_reg
73 #define AL OP_REG, al_reg
74 #define CL OP_REG, cl_reg
75 #define DL OP_REG, dl_reg
76 #define BL OP_REG, bl_reg
77 #define AH OP_REG, ah_reg
78 #define CH OP_REG, ch_reg
79 #define DH OP_REG, dh_reg
80 #define BH OP_REG, bh_reg
81 #define AX OP_REG, ax_reg
82 #define DX OP_REG, dx_reg
83 #define indirDX OP_REG, indir_dx_reg
85 #define Sw OP_SEG, w_mode
86 #define Ap OP_DIR, lptr
87 #define Av OP_DIR, v_mode
88 #define Ob OP_OFF, b_mode
89 #define Ov OP_OFF, v_mode
90 #define Xb OP_DSSI, b_mode
91 #define Xv OP_DSSI, v_mode
92 #define Yb OP_ESDI, b_mode
93 #define Yv OP_ESDI, v_mode
95 #define es OP_REG, es_reg
96 #define ss OP_REG, ss_reg
97 #define cs OP_REG, cs_reg
98 #define ds OP_REG, ds_reg
99 #define fs OP_REG, fs_reg
100 #define gs OP_REG, gs_reg
102 int OP_E(), OP_indirE(), OP_G(), OP_I(), OP_sI(), OP_REG();
103 int OP_J(), OP_SEG();
104 int OP_DIR(), OP_OFF(), OP_DSSI(), OP_ESDI(), OP_ONE(), OP_C();
105 int OP_D(), OP_T(), OP_rm();
148 #define indir_dx_reg 150
150 #define GRP1b NULL, NULL, 0
151 #define GRP1S NULL, NULL, 1
152 #define GRP1Ss NULL, NULL, 2
153 #define GRP2b NULL, NULL, 3
154 #define GRP2S NULL, NULL, 4
155 #define GRP2b_one NULL, NULL, 5
156 #define GRP2S_one NULL, NULL, 6
157 #define GRP2b_cl NULL, NULL, 7
158 #define GRP2S_cl NULL, NULL, 8
159 #define GRP3b NULL, NULL, 9
160 #define GRP3S NULL, NULL, 10
161 #define GRP4 NULL, NULL, 11
162 #define GRP5 NULL, NULL, 12
163 #define GRP6 NULL, NULL, 13
164 #define GRP7 NULL, NULL, 14
165 #define GRP8 NULL, NULL, 15
168 #define FLOAT NULL, NULL, FLOATCODE
180 struct dis386 dis386
[] = {
198 { "(bad)" }, /* 0x0f extended opcode escape */
224 { "(bad)" }, /* SEG ES prefix */
233 { "(bad)" }, /* SEG CS prefix */
242 { "(bad)" }, /* SEG SS prefix */
251 { "(bad)" }, /* SEG DS prefix */
292 { "boundS", Gv
, Ma
},
294 { "(bad)" }, /* seg fs */
295 { "(bad)" }, /* seg gs */
296 { "(bad)" }, /* op size prefix */
297 { "(bad)" }, /* adr size prefix */
299 { "pushS", Iv
}, /* 386 book wrong */
300 { "imulS", Gv
, Ev
, Iv
},
301 { "pushl", sIb
}, /* push of byte really pushes 4 bytes */
302 { "imulS", Gv
, Ev
, Ib
},
303 { "insb", Yb
, indirDX
},
304 { "insS", Yv
, indirDX
},
305 { "outsb", indirDX
, Xb
},
306 { "outsS", indirDX
, Xv
},
345 { "xchgS", eCX
, eAX
},
346 { "xchgS", eDX
, eAX
},
347 { "xchgS", eBX
, eAX
},
348 { "xchgS", eSP
, eAX
},
349 { "xchgS", eBP
, eAX
},
350 { "xchgS", eSI
, eAX
},
351 { "xchgS", eDI
, eAX
},
356 { "(bad)" }, /* fwait */
372 { "testS", eAX
, Iv
},
374 { "stosS", Yv
, eAX
},
376 { "lodsS", eAX
, Xv
},
378 { "scasS", eAX
, Xv
},
447 { "inb", AL
, indirDX
},
448 { "inS", eAX
, indirDX
},
449 { "outb", indirDX
, AL
},
450 { "outS", indirDX
, eAX
},
452 { "(bad)" }, /* lock prefix */
454 { "(bad)" }, /* repne */
455 { "(bad)" }, /* repz */
471 struct dis386 dis386_twobyte
[] = {
482 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
483 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
485 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
486 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
488 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
489 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
491 /* these are all backward in appendix A of the intel book */
501 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
502 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
504 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
505 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
507 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
508 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
510 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
511 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
513 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
514 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
516 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
517 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
519 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
520 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
522 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
523 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
525 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
526 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
528 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
529 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
531 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
532 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
574 { "shldS", Ev
, Gv
, Ib
},
575 { "shldS", Ev
, Gv
, CL
},
583 { "shrdS", Ev
, Gv
, Ib
},
584 { "shrdS", Ev
, Gv
, CL
},
590 { "lssS", Gv
, Mp
}, /* 386 lists only Mp */
592 { "lfsS", Gv
, Mp
}, /* 386 lists only Mp */
593 { "lgsS", Gv
, Mp
}, /* 386 lists only Mp */
594 { "movzbS", Gv
, Eb
},
595 { "movzwS", Gv
, Ew
},
603 { "movsbS", Gv
, Eb
},
604 { "movswS", Gv
, Ew
},
606 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
607 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
609 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
610 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
612 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
613 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
615 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
616 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
618 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
619 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
621 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
622 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
624 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
625 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
627 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
628 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
631 static char obuf
[100];
633 static char scratchbuf
[100];
634 static unsigned char *start_codep
;
635 static unsigned char *codep
;
639 static void oappend ();
641 static char *names32
[]={
642 "%eax","%ecx","%edx","%ebx", "%esp","%ebp","%esi","%edi",
644 static char *names16
[] = {
645 "%ax","%cx","%dx","%bx","%sp","%bp","%si","%di",
647 static char *names8
[] = {
648 "%al","%cl","%dl","%bl","%ah","%ch","%dh","%bh",
650 static char *names_seg
[] = {
651 "%es","%cs","%ss","%ds","%fs","%gs","%?","%?",
654 struct dis386 grps
[][8] = {
772 { "imulS", eAX
, Ev
},
774 { "idivS", eAX
, Ev
},
792 { "lcall", indirEv
},
833 #define PREFIX_REPZ 1
834 #define PREFIX_REPNZ 2
835 #define PREFIX_LOCK 4
837 #define PREFIX_SS 0x10
838 #define PREFIX_DS 0x20
839 #define PREFIX_ES 0x40
840 #define PREFIX_FS 0x80
841 #define PREFIX_GS 0x100
842 #define PREFIX_DATA 0x200
843 #define PREFIX_ADR 0x400
844 #define PREFIX_FWAIT 0x800
856 prefixes
|= PREFIX_REPZ
;
859 prefixes
|= PREFIX_REPNZ
;
862 prefixes
|= PREFIX_LOCK
;
865 prefixes
|= PREFIX_CS
;
868 prefixes
|= PREFIX_SS
;
871 prefixes
|= PREFIX_DS
;
874 prefixes
|= PREFIX_ES
;
877 prefixes
|= PREFIX_FS
;
880 prefixes
|= PREFIX_GS
;
883 prefixes
|= PREFIX_DATA
;
886 prefixes
|= PREFIX_ADR
;
889 prefixes
|= PREFIX_FWAIT
;
901 static char op1out
[100], op2out
[100], op3out
[100];
902 static int op_address
[3], op_ad
, op_index
[3];
904 extern void fputs_filtered ();
907 * disassemble the first instruction in 'inbuf'. You have to make
908 * sure all of the bytes of the instruction are filled in.
909 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
910 * (see topic "Redundant prefixes" in the "Differences from 8086"
911 * section of the "Virtual 8086 Mode" chapter.)
912 * 'pc' should be the address of this instruction, it will
913 * be used to print the target address if this is a relative jump or call
914 * 'outbuf' gets filled in with the disassembled instruction. it should
915 * be long enough to hold the longest disassembled instruction.
916 * 100 bytes is certainly enough, unless symbol printing is added later
917 * The function returns the length of this instruction in bytes.
919 i386dis (pc
, inbuf
, stream
)
921 unsigned char *inbuf
;
927 int enter_instruction
;
928 char *first
, *second
, *third
;
936 op_index
[0] = op_index
[1] = op_index
[2] = -1;
945 enter_instruction
= 1;
947 enter_instruction
= 0;
951 if (prefixes
& PREFIX_REPZ
)
953 if (prefixes
& PREFIX_REPNZ
)
955 if (prefixes
& PREFIX_LOCK
)
958 if ((prefixes
& PREFIX_FWAIT
)
959 && ((*codep
< 0xd8) || (*codep
> 0xdf)))
961 /* fwait not followed by floating point instruction */
962 fputs_filtered ("fwait", stream
);
966 /* these would be initialized to 0 if disassembling for 8086 or 286 */
970 if (prefixes
& PREFIX_DATA
)
973 if (prefixes
& PREFIX_ADR
)
980 dp
= &dis386_twobyte
[*++codep
];
982 dp
= &dis386
[*codep
];
984 mod
= (*codep
>> 6) & 3;
985 reg
= (*codep
>> 3) & 7;
988 if (dp
->name
== NULL
&& dp
->bytemode1
== FLOATCODE
)
994 if (dp
->name
== NULL
)
995 dp
= &grps
[dp
->bytemode1
][reg
];
1002 (*dp
->op1
)(dp
->bytemode1
);
1007 (*dp
->op2
)(dp
->bytemode2
);
1012 (*dp
->op3
)(dp
->bytemode3
);
1015 obufp
= obuf
+ strlen (obuf
);
1016 for (i
= strlen (obuf
); i
< 6; i
++)
1019 fputs_filtered (obuf
, stream
);
1021 /* enter instruction is printed with operands in the
1022 * same order as the intel book; everything else
1023 * is printed in reverse order
1025 if (enter_instruction
)
1030 op_ad
= op_index
[0];
1031 op_index
[0] = op_index
[2];
1032 op_index
[2] = op_ad
;
1043 if (op_index
[0] != -1)
1044 print_address (op_address
[op_index
[0]], stream
);
1046 fputs_filtered (first
, stream
);
1052 fputs_filtered (",", stream
);
1053 if (op_index
[1] != -1)
1054 print_address (op_address
[op_index
[1]], stream
);
1056 fputs_filtered (second
, stream
);
1062 fputs_filtered (",", stream
);
1063 if (op_index
[2] != -1)
1064 print_address (op_address
[op_index
[2]], stream
);
1066 fputs_filtered (third
, stream
);
1068 return (codep
- inbuf
);
1071 char *float_mem
[] = {
1147 #define STi OP_STi, 0
1148 int OP_ST(), OP_STi();
1150 #define FGRPd9_2 NULL, NULL, 0
1151 #define FGRPd9_4 NULL, NULL, 1
1152 #define FGRPd9_5 NULL, NULL, 2
1153 #define FGRPd9_6 NULL, NULL, 3
1154 #define FGRPd9_7 NULL, NULL, 4
1155 #define FGRPda_5 NULL, NULL, 5
1156 #define FGRPdb_4 NULL, NULL, 6
1157 #define FGRPde_3 NULL, NULL, 7
1158 #define FGRPdf_4 NULL, NULL, 8
1160 struct dis386 float_reg
[][8] = {
1163 { "fadd", ST
, STi
},
1164 { "fmul", ST
, STi
},
1167 { "fsub", ST
, STi
},
1168 { "fsubr", ST
, STi
},
1169 { "fdiv", ST
, STi
},
1170 { "fdivr", ST
, STi
},
1207 { "fadd", STi
, ST
},
1208 { "fmul", STi
, ST
},
1211 { "fsub", STi
, ST
},
1212 { "fsubr", STi
, ST
},
1213 { "fdiv", STi
, ST
},
1214 { "fdivr", STi
, ST
},
1229 { "faddp", STi
, ST
},
1230 { "fmulp", STi
, ST
},
1233 { "fsubp", STi
, ST
},
1234 { "fsubrp", STi
, ST
},
1235 { "fdivp", STi
, ST
},
1236 { "fdivrp", STi
, ST
},
1252 char *fgrps
[][8] = {
1255 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
1260 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
1265 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
1270 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
1275 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
1280 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
1285 "feni(287 only)","fdisi(287 only)","fNclex","fNinit",
1286 "fNsetpm(287 only)","(bad)","(bad)","(bad)",
1291 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
1296 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
1304 unsigned char floatop
;
1306 floatop
= codep
[-1];
1310 putop (float_mem
[(floatop
- 0xd8) * 8 + reg
]);
1317 dp
= &float_reg
[floatop
- 0xd8][reg
];
1318 if (dp
->name
== NULL
)
1320 putop (fgrps
[dp
->bytemode1
][rm
]);
1321 /* instruction fnstsw is only one with strange arg */
1322 if (floatop
== 0xdf && *codep
== 0xe0)
1323 strcpy (op1out
, "%eax");
1330 (*dp
->op1
)(dp
->bytemode1
);
1333 (*dp
->op2
)(dp
->bytemode2
);
1346 sprintf (scratchbuf
, "%%st(%d)", rm
);
1347 oappend (scratchbuf
);
1351 /* capital letters in template are macros */
1357 for (p
= template; *p
; p
++)
1364 case 'C': /* For jcxz/jecxz */
1369 if ((prefixes
& PREFIX_FWAIT
) == 0)
1373 /* operand size flag */
1389 obufp
+= strlen (s
);
1395 if (prefixes
& PREFIX_CS
)
1397 if (prefixes
& PREFIX_DS
)
1399 if (prefixes
& PREFIX_SS
)
1401 if (prefixes
& PREFIX_ES
)
1403 if (prefixes
& PREFIX_FS
)
1405 if (prefixes
& PREFIX_GS
)
1409 OP_indirE (bytemode
)
1425 /* skip mod/rm byte */
1437 oappend (names8
[rm
]);
1440 oappend (names16
[rm
]);
1444 oappend (names32
[rm
]);
1446 oappend (names16
[rm
]);
1449 oappend ("<bad dis table>");
1460 scale
= (*codep
>> 6) & 3;
1461 index
= (*codep
>> 3) & 7;
1472 /* implies havesib and havebase */
1488 disp
= *(char *)codep
++;
1505 if (mod
!= 0 || rm
== 5 || (havesib
&& base
== 5))
1507 sprintf (scratchbuf
, "0x%x", disp
);
1508 oappend (scratchbuf
);
1511 if (havebase
|| havesib
)
1515 oappend (names32
[base
]);
1520 sprintf (scratchbuf
, ",%s", names32
[index
]);
1521 oappend (scratchbuf
);
1523 sprintf (scratchbuf
, ",%d", 1 << scale
);
1524 oappend (scratchbuf
);
1535 oappend (names8
[reg
]);
1538 oappend (names16
[reg
]);
1541 oappend (names32
[reg
]);
1545 oappend (names32
[reg
]);
1547 oappend (names16
[reg
]);
1550 oappend ("<internal disassembler error>");
1559 x
= *codep
++ & 0xff;
1560 x
|= (*codep
++ & 0xff) << 8;
1561 x
|= (*codep
++ & 0xff) << 16;
1562 x
|= (*codep
++ & 0xff) << 24;
1570 x
= *codep
++ & 0xff;
1571 x
|= (*codep
++ & 0xff) << 8;
1578 op_index
[op_ad
] = op_ad
;
1579 op_address
[op_ad
] = op
;
1588 case indir_dx_reg
: s
= "(%dx)"; break;
1589 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
1590 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
1591 s
= names16
[code
- ax_reg
];
1593 case es_reg
: case ss_reg
: case cs_reg
:
1594 case ds_reg
: case fs_reg
: case gs_reg
:
1595 s
= names_seg
[code
- es_reg
];
1597 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
1598 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
1599 s
= names8
[code
- al_reg
];
1601 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
1602 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
1604 s
= names32
[code
- eAX_reg
];
1606 s
= names16
[code
- eAX_reg
];
1609 s
= "<internal disassembler error>";
1622 op
= *codep
++ & 0xff;
1634 oappend ("<internal disassembler error>");
1637 sprintf (scratchbuf
, "$0x%x", op
);
1638 oappend (scratchbuf
);
1648 op
= *(char *)codep
++;
1654 op
= (short)get16();
1657 op
= (short)get16 ();
1660 oappend ("<internal disassembler error>");
1663 sprintf (scratchbuf
, "$0x%x", op
);
1664 oappend (scratchbuf
);
1675 disp
= *(char *)codep
++;
1682 disp
= (short)get16 ();
1683 /* for some reason, a data16 prefix on a jump instruction
1684 means that the pc is masked to 16 bits after the
1685 displacement is added! */
1690 oappend ("<internal disassembler error>");
1693 disp
= (start_pc
+ codep
- start_codep
+ disp
) & mask
;
1695 sprintf (scratchbuf
, "0x%x", disp
);
1696 oappend (scratchbuf
);
1702 static char *sreg
[] = {
1703 "%es","%cs","%ss","%ds","%fs","%gs","%?","%?",
1706 oappend (sreg
[reg
]);
1726 sprintf (scratchbuf
, "0x%x,0x%x", seg
, offset
);
1727 oappend (scratchbuf
);
1733 offset
= (short)get16 ();
1735 offset
= start_pc
+ codep
- start_codep
+ offset
;
1737 sprintf (scratchbuf
, "0x%x", offset
);
1738 oappend (scratchbuf
);
1741 oappend ("<internal disassembler error>");
1756 sprintf (scratchbuf
, "0x%x", off
);
1757 oappend (scratchbuf
);
1764 oappend (aflag
? "%edi" : "%di");
1772 oappend (aflag
? "%esi" : "%si");
1785 codep
++; /* skip mod/rm */
1786 sprintf (scratchbuf
, "%%cr%d", reg
);
1787 oappend (scratchbuf
);
1793 codep
++; /* skip mod/rm */
1794 sprintf (scratchbuf
, "%%db%d", reg
);
1795 oappend (scratchbuf
);
1801 codep
++; /* skip mod/rm */
1802 sprintf (scratchbuf
, "%%tr%d", reg
);
1803 oappend (scratchbuf
);
1811 oappend (names32
[rm
]);
1814 oappend (names16
[rm
]);
1820 print_insn (memaddr
, stream
)
1824 unsigned char buffer
[MAXLEN
];
1826 read_memory (memaddr
, buffer
, MAXLEN
);
1828 return (i386dis ((int)memaddr
, buffer
, stream
));
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