1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988, 1989, 1991 Free Software Foundation, Inc.
4 This file is part of GDB.
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
21 * 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
26 * The main tables describing the instructions is essentially a copy
27 * of the "Opcode Map" chapter (Appendix A) of the Intel 80386
28 * Programmers Manual. Usually, there is a capital letter, followed
29 * by a small letter. The capital letter tell the addressing mode,
30 * and the small letter tells about the operand size. Refer to
31 * the Intel manual for details.
38 /* For the GDB interface at the bottom of the file... */
41 #define Eb OP_E, b_mode
42 #define indirEb OP_indirE, b_mode
43 #define Gb OP_G, b_mode
44 #define Ev OP_E, v_mode
45 #define indirEv OP_indirE, v_mode
46 #define Ew OP_E, w_mode
47 #define Ma OP_E, v_mode
49 #define Mp OP_E, 0 /* ? */
50 #define Gv OP_G, v_mode
51 #define Gw OP_G, w_mode
52 #define Rw OP_rm, w_mode
53 #define Rd OP_rm, d_mode
54 #define Ib OP_I, b_mode
55 #define sIb OP_sI, b_mode /* sign extened byte */
56 #define Iv OP_I, v_mode
57 #define Iw OP_I, w_mode
58 #define Jb OP_J, b_mode
59 #define Jv OP_J, v_mode
61 #define Cd OP_C, d_mode
62 #define Dd OP_D, d_mode
63 #define Td OP_T, d_mode
65 #define eAX OP_REG, eAX_reg
66 #define eBX OP_REG, eBX_reg
67 #define eCX OP_REG, eCX_reg
68 #define eDX OP_REG, eDX_reg
69 #define eSP OP_REG, eSP_reg
70 #define eBP OP_REG, eBP_reg
71 #define eSI OP_REG, eSI_reg
72 #define eDI OP_REG, eDI_reg
73 #define AL OP_REG, al_reg
74 #define CL OP_REG, cl_reg
75 #define DL OP_REG, dl_reg
76 #define BL OP_REG, bl_reg
77 #define AH OP_REG, ah_reg
78 #define CH OP_REG, ch_reg
79 #define DH OP_REG, dh_reg
80 #define BH OP_REG, bh_reg
81 #define AX OP_REG, ax_reg
82 #define DX OP_REG, dx_reg
83 #define indirDX OP_REG, indir_dx_reg
85 #define Sw OP_SEG, w_mode
86 #define Ap OP_DIR, lptr
87 #define Av OP_DIR, v_mode
88 #define Ob OP_OFF, b_mode
89 #define Ov OP_OFF, v_mode
90 #define Xb OP_DSSI, b_mode
91 #define Xv OP_DSSI, v_mode
92 #define Yb OP_ESDI, b_mode
93 #define Yv OP_ESDI, v_mode
95 #define es OP_REG, es_reg
96 #define ss OP_REG, ss_reg
97 #define cs OP_REG, cs_reg
98 #define ds OP_REG, ds_reg
99 #define fs OP_REG, fs_reg
100 #define gs OP_REG, gs_reg
102 int OP_E(), OP_indirE(), OP_G(), OP_I(), OP_sI(), OP_REG();
103 int OP_J(), OP_SEG();
104 int OP_DIR(), OP_OFF(), OP_DSSI(), OP_ESDI(), OP_ONE(), OP_C();
105 int OP_D(), OP_T(), OP_rm();
107 static void dofloat (), putop (), append_prefix (), set_op ();
108 static int get16 (), get32 ();
150 #define indir_dx_reg 150
152 #define GRP1b NULL, NULL, 0
153 #define GRP1S NULL, NULL, 1
154 #define GRP1Ss NULL, NULL, 2
155 #define GRP2b NULL, NULL, 3
156 #define GRP2S NULL, NULL, 4
157 #define GRP2b_one NULL, NULL, 5
158 #define GRP2S_one NULL, NULL, 6
159 #define GRP2b_cl NULL, NULL, 7
160 #define GRP2S_cl NULL, NULL, 8
161 #define GRP3b NULL, NULL, 9
162 #define GRP3S NULL, NULL, 10
163 #define GRP4 NULL, NULL, 11
164 #define GRP5 NULL, NULL, 12
165 #define GRP6 NULL, NULL, 13
166 #define GRP7 NULL, NULL, 14
167 #define GRP8 NULL, NULL, 15
170 #define FLOAT NULL, NULL, FLOATCODE
182 struct dis386 dis386
[] = {
200 { "(bad)" }, /* 0x0f extended opcode escape */
226 { "(bad)" }, /* SEG ES prefix */
235 { "(bad)" }, /* SEG CS prefix */
244 { "(bad)" }, /* SEG SS prefix */
253 { "(bad)" }, /* SEG DS prefix */
294 { "boundS", Gv
, Ma
},
296 { "(bad)" }, /* seg fs */
297 { "(bad)" }, /* seg gs */
298 { "(bad)" }, /* op size prefix */
299 { "(bad)" }, /* adr size prefix */
301 { "pushS", Iv
}, /* 386 book wrong */
302 { "imulS", Gv
, Ev
, Iv
},
303 { "pushl", sIb
}, /* push of byte really pushes 4 bytes */
304 { "imulS", Gv
, Ev
, Ib
},
305 { "insb", Yb
, indirDX
},
306 { "insS", Yv
, indirDX
},
307 { "outsb", indirDX
, Xb
},
308 { "outsS", indirDX
, Xv
},
347 { "xchgS", eCX
, eAX
},
348 { "xchgS", eDX
, eAX
},
349 { "xchgS", eBX
, eAX
},
350 { "xchgS", eSP
, eAX
},
351 { "xchgS", eBP
, eAX
},
352 { "xchgS", eSI
, eAX
},
353 { "xchgS", eDI
, eAX
},
358 { "(bad)" }, /* fwait */
374 { "testS", eAX
, Iv
},
376 { "stosS", Yv
, eAX
},
378 { "lodsS", eAX
, Xv
},
380 { "scasS", eAX
, Xv
},
449 { "inb", AL
, indirDX
},
450 { "inS", eAX
, indirDX
},
451 { "outb", indirDX
, AL
},
452 { "outS", indirDX
, eAX
},
454 { "(bad)" }, /* lock prefix */
456 { "(bad)" }, /* repne */
457 { "(bad)" }, /* repz */
473 struct dis386 dis386_twobyte
[] = {
484 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
485 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
487 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
488 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
490 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
491 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
493 /* these are all backward in appendix A of the intel book */
503 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
504 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
506 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
507 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
509 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
510 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
512 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
513 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
515 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
516 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
518 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
519 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
521 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
522 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
524 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
525 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
527 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
528 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
530 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
531 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
533 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
534 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
576 { "shldS", Ev
, Gv
, Ib
},
577 { "shldS", Ev
, Gv
, CL
},
585 { "shrdS", Ev
, Gv
, Ib
},
586 { "shrdS", Ev
, Gv
, CL
},
592 { "lssS", Gv
, Mp
}, /* 386 lists only Mp */
594 { "lfsS", Gv
, Mp
}, /* 386 lists only Mp */
595 { "lgsS", Gv
, Mp
}, /* 386 lists only Mp */
596 { "movzbS", Gv
, Eb
},
597 { "movzwS", Gv
, Ew
},
605 { "movsbS", Gv
, Eb
},
606 { "movswS", Gv
, Ew
},
608 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
609 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
611 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
612 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
614 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
615 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
617 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
618 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
620 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
621 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
623 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
624 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
626 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
627 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
629 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
630 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
633 static char obuf
[100];
635 static char scratchbuf
[100];
636 static unsigned char *start_codep
;
637 static unsigned char *codep
;
641 static void oappend ();
643 static char *names32
[]={
644 "%eax","%ecx","%edx","%ebx", "%esp","%ebp","%esi","%edi",
646 static char *names16
[] = {
647 "%ax","%cx","%dx","%bx","%sp","%bp","%si","%di",
649 static char *names8
[] = {
650 "%al","%cl","%dl","%bl","%ah","%ch","%dh","%bh",
652 static char *names_seg
[] = {
653 "%es","%cs","%ss","%ds","%fs","%gs","%?","%?",
656 struct dis386 grps
[][8] = {
774 { "imulS", eAX
, Ev
},
776 { "idivS", eAX
, Ev
},
794 { "lcall", indirEv
},
835 #define PREFIX_REPZ 1
836 #define PREFIX_REPNZ 2
837 #define PREFIX_LOCK 4
839 #define PREFIX_SS 0x10
840 #define PREFIX_DS 0x20
841 #define PREFIX_ES 0x40
842 #define PREFIX_FS 0x80
843 #define PREFIX_GS 0x100
844 #define PREFIX_DATA 0x200
845 #define PREFIX_ADR 0x400
846 #define PREFIX_FWAIT 0x800
859 prefixes
|= PREFIX_REPZ
;
862 prefixes
|= PREFIX_REPNZ
;
865 prefixes
|= PREFIX_LOCK
;
868 prefixes
|= PREFIX_CS
;
871 prefixes
|= PREFIX_SS
;
874 prefixes
|= PREFIX_DS
;
877 prefixes
|= PREFIX_ES
;
880 prefixes
|= PREFIX_FS
;
883 prefixes
|= PREFIX_GS
;
886 prefixes
|= PREFIX_DATA
;
889 prefixes
|= PREFIX_ADR
;
892 prefixes
|= PREFIX_FWAIT
;
904 static char op1out
[100], op2out
[100], op3out
[100];
905 static int op_address
[3], op_ad
, op_index
[3];
907 extern void fputs_filtered ();
910 * disassemble the first instruction in 'inbuf'. You have to make
911 * sure all of the bytes of the instruction are filled in.
912 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
913 * (see topic "Redundant prefixes" in the "Differences from 8086"
914 * section of the "Virtual 8086 Mode" chapter.)
915 * 'pc' should be the address of this instruction, it will
916 * be used to print the target address if this is a relative jump or call
917 * 'outbuf' gets filled in with the disassembled instruction. it should
918 * be long enough to hold the longest disassembled instruction.
919 * 100 bytes is certainly enough, unless symbol printing is added later
920 * The function returns the length of this instruction in bytes.
924 i386dis (pc
, inbuf
, stream
)
926 unsigned char *inbuf
;
931 int enter_instruction
;
932 char *first
, *second
, *third
;
940 op_index
[0] = op_index
[1] = op_index
[2] = -1;
949 enter_instruction
= 1;
951 enter_instruction
= 0;
955 if (prefixes
& PREFIX_REPZ
)
957 if (prefixes
& PREFIX_REPNZ
)
959 if (prefixes
& PREFIX_LOCK
)
962 if ((prefixes
& PREFIX_FWAIT
)
963 && ((*codep
< 0xd8) || (*codep
> 0xdf)))
965 /* fwait not followed by floating point instruction */
966 fputs_filtered ("fwait", stream
);
970 /* these would be initialized to 0 if disassembling for 8086 or 286 */
974 if (prefixes
& PREFIX_DATA
)
977 if (prefixes
& PREFIX_ADR
)
984 dp
= &dis386_twobyte
[*++codep
];
986 dp
= &dis386
[*codep
];
988 mod
= (*codep
>> 6) & 3;
989 reg
= (*codep
>> 3) & 7;
992 if (dp
->name
== NULL
&& dp
->bytemode1
== FLOATCODE
)
998 if (dp
->name
== NULL
)
999 dp
= &grps
[dp
->bytemode1
][reg
];
1006 (*dp
->op1
)(dp
->bytemode1
);
1011 (*dp
->op2
)(dp
->bytemode2
);
1016 (*dp
->op3
)(dp
->bytemode3
);
1019 obufp
= obuf
+ strlen (obuf
);
1020 for (i
= strlen (obuf
); i
< 6; i
++)
1023 fputs_filtered (obuf
, stream
);
1025 /* enter instruction is printed with operands in the
1026 * same order as the intel book; everything else
1027 * is printed in reverse order
1029 if (enter_instruction
)
1034 op_ad
= op_index
[0];
1035 op_index
[0] = op_index
[2];
1036 op_index
[2] = op_ad
;
1047 if (op_index
[0] != -1)
1048 print_address (op_address
[op_index
[0]], stream
);
1050 fputs_filtered (first
, stream
);
1056 fputs_filtered (",", stream
);
1057 if (op_index
[1] != -1)
1058 print_address (op_address
[op_index
[1]], stream
);
1060 fputs_filtered (second
, stream
);
1066 fputs_filtered (",", stream
);
1067 if (op_index
[2] != -1)
1068 print_address (op_address
[op_index
[2]], stream
);
1070 fputs_filtered (third
, stream
);
1072 return (codep
- inbuf
);
1075 char *float_mem
[] = {
1151 #define STi OP_STi, 0
1152 int OP_ST(), OP_STi();
1154 #define FGRPd9_2 NULL, NULL, 0
1155 #define FGRPd9_4 NULL, NULL, 1
1156 #define FGRPd9_5 NULL, NULL, 2
1157 #define FGRPd9_6 NULL, NULL, 3
1158 #define FGRPd9_7 NULL, NULL, 4
1159 #define FGRPda_5 NULL, NULL, 5
1160 #define FGRPdb_4 NULL, NULL, 6
1161 #define FGRPde_3 NULL, NULL, 7
1162 #define FGRPdf_4 NULL, NULL, 8
1164 struct dis386 float_reg
[][8] = {
1167 { "fadd", ST
, STi
},
1168 { "fmul", ST
, STi
},
1171 { "fsub", ST
, STi
},
1172 { "fsubr", ST
, STi
},
1173 { "fdiv", ST
, STi
},
1174 { "fdivr", ST
, STi
},
1211 { "fadd", STi
, ST
},
1212 { "fmul", STi
, ST
},
1215 { "fsub", STi
, ST
},
1216 { "fsubr", STi
, ST
},
1217 { "fdiv", STi
, ST
},
1218 { "fdivr", STi
, ST
},
1233 { "faddp", STi
, ST
},
1234 { "fmulp", STi
, ST
},
1237 { "fsubp", STi
, ST
},
1238 { "fsubrp", STi
, ST
},
1239 { "fdivp", STi
, ST
},
1240 { "fdivrp", STi
, ST
},
1256 char *fgrps
[][8] = {
1259 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
1264 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
1269 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
1274 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
1279 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
1284 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
1289 "feni(287 only)","fdisi(287 only)","fNclex","fNinit",
1290 "fNsetpm(287 only)","(bad)","(bad)","(bad)",
1295 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
1300 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
1308 unsigned char floatop
;
1310 floatop
= codep
[-1];
1314 putop (float_mem
[(floatop
- 0xd8) * 8 + reg
]);
1321 dp
= &float_reg
[floatop
- 0xd8][reg
];
1322 if (dp
->name
== NULL
)
1324 putop (fgrps
[dp
->bytemode1
][rm
]);
1325 /* instruction fnstsw is only one with strange arg */
1326 if (floatop
== 0xdf && *codep
== 0xe0)
1327 strcpy (op1out
, "%eax");
1334 (*dp
->op1
)(dp
->bytemode1
);
1337 (*dp
->op2
)(dp
->bytemode2
);
1355 sprintf (scratchbuf
, "%%st(%d)", rm
);
1356 oappend (scratchbuf
);
1361 /* capital letters in template are macros */
1368 for (p
= template; *p
; p
++)
1375 case 'C': /* For jcxz/jecxz */
1380 if ((prefixes
& PREFIX_FWAIT
) == 0)
1384 /* operand size flag */
1400 obufp
+= strlen (s
);
1407 if (prefixes
& PREFIX_CS
)
1409 if (prefixes
& PREFIX_DS
)
1411 if (prefixes
& PREFIX_SS
)
1413 if (prefixes
& PREFIX_ES
)
1415 if (prefixes
& PREFIX_FS
)
1417 if (prefixes
& PREFIX_GS
)
1422 OP_indirE (bytemode
)
1441 /* skip mod/rm byte */
1453 oappend (names8
[rm
]);
1456 oappend (names16
[rm
]);
1460 oappend (names32
[rm
]);
1462 oappend (names16
[rm
]);
1465 oappend ("<bad dis table>");
1476 scale
= (*codep
>> 6) & 3;
1477 index
= (*codep
>> 3) & 7;
1488 /* implies havesib and havebase */
1504 disp
= *(char *)codep
++;
1521 if (mod
!= 0 || rm
== 5 || (havesib
&& base
== 5))
1523 sprintf (scratchbuf
, "0x%x", disp
);
1524 oappend (scratchbuf
);
1527 if (havebase
|| havesib
)
1531 oappend (names32
[base
]);
1536 sprintf (scratchbuf
, ",%s", names32
[index
]);
1537 oappend (scratchbuf
);
1539 sprintf (scratchbuf
, ",%d", 1 << scale
);
1540 oappend (scratchbuf
);
1554 oappend (names8
[reg
]);
1557 oappend (names16
[reg
]);
1560 oappend (names32
[reg
]);
1564 oappend (names32
[reg
]);
1566 oappend (names16
[reg
]);
1569 oappend ("<internal disassembler error>");
1580 x
= *codep
++ & 0xff;
1581 x
|= (*codep
++ & 0xff) << 8;
1582 x
|= (*codep
++ & 0xff) << 16;
1583 x
|= (*codep
++ & 0xff) << 24;
1592 x
= *codep
++ & 0xff;
1593 x
|= (*codep
++ & 0xff) << 8;
1601 op_index
[op_ad
] = op_ad
;
1602 op_address
[op_ad
] = op
;
1613 case indir_dx_reg
: s
= "(%dx)"; break;
1614 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
1615 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
1616 s
= names16
[code
- ax_reg
];
1618 case es_reg
: case ss_reg
: case cs_reg
:
1619 case ds_reg
: case fs_reg
: case gs_reg
:
1620 s
= names_seg
[code
- es_reg
];
1622 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
1623 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
1624 s
= names8
[code
- al_reg
];
1626 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
1627 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
1629 s
= names32
[code
- eAX_reg
];
1631 s
= names16
[code
- eAX_reg
];
1634 s
= "<internal disassembler error>";
1650 op
= *codep
++ & 0xff;
1662 oappend ("<internal disassembler error>");
1665 sprintf (scratchbuf
, "$0x%x", op
);
1666 oappend (scratchbuf
);
1679 op
= *(char *)codep
++;
1685 op
= (short)get16();
1688 op
= (short)get16 ();
1691 oappend ("<internal disassembler error>");
1694 sprintf (scratchbuf
, "$0x%x", op
);
1695 oappend (scratchbuf
);
1709 disp
= *(char *)codep
++;
1716 disp
= (short)get16 ();
1717 /* for some reason, a data16 prefix on a jump instruction
1718 means that the pc is masked to 16 bits after the
1719 displacement is added! */
1724 oappend ("<internal disassembler error>");
1727 disp
= (start_pc
+ codep
- start_codep
+ disp
) & mask
;
1729 sprintf (scratchbuf
, "0x%x", disp
);
1730 oappend (scratchbuf
);
1739 static char *sreg
[] = {
1740 "%es","%cs","%ss","%ds","%fs","%gs","%?","%?",
1743 oappend (sreg
[reg
]);
1766 sprintf (scratchbuf
, "0x%x,0x%x", seg
, offset
);
1767 oappend (scratchbuf
);
1773 offset
= (short)get16 ();
1775 offset
= start_pc
+ codep
- start_codep
+ offset
;
1777 sprintf (scratchbuf
, "0x%x", offset
);
1778 oappend (scratchbuf
);
1781 oappend ("<internal disassembler error>");
1799 sprintf (scratchbuf
, "0x%x", off
);
1800 oappend (scratchbuf
);
1810 oappend (aflag
? "%edi" : "%di");
1821 oappend (aflag
? "%esi" : "%si");
1840 codep
++; /* skip mod/rm */
1841 sprintf (scratchbuf
, "%%cr%d", reg
);
1842 oappend (scratchbuf
);
1851 codep
++; /* skip mod/rm */
1852 sprintf (scratchbuf
, "%%db%d", reg
);
1853 oappend (scratchbuf
);
1862 codep
++; /* skip mod/rm */
1863 sprintf (scratchbuf
, "%%tr%d", reg
);
1864 oappend (scratchbuf
);
1875 oappend (names32
[rm
]);
1878 oappend (names16
[rm
]);
1887 print_insn (memaddr
, stream
)
1891 unsigned char buffer
[MAXLEN
];
1893 read_memory (memaddr
, (char *) buffer
, MAXLEN
);
1895 return (i386dis ((int)memaddr
, buffer
, stream
));
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