1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988, 1989, 1991 Free Software Foundation, Inc.
4 This file is part of GDB.
6 GDB is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 1, or (at your option)
11 GDB is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GDB; see the file COPYING. If not, write to
18 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
21 * 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
26 * The main tables describing the instructions is essentially a copy
27 * of the "Opcode Map" chapter (Appendix A) of the Intel 80386
28 * Programmers Manual. Usually, there is a capital letter, followed
29 * by a small letter. The capital letter tell the addressing mode,
30 * and the small letter tells about the operand size. Refer to
31 * the Intel manual for details.
37 /* For the GDB interface at the bottom of the file... */
42 #define Eb OP_E, b_mode
43 #define indirEb OP_indirE, b_mode
44 #define Gb OP_G, b_mode
45 #define Ev OP_E, v_mode
46 #define indirEv OP_indirE, v_mode
47 #define Ew OP_E, w_mode
48 #define Ma OP_E, v_mode
50 #define Mp OP_E, 0 /* ? */
51 #define Gv OP_G, v_mode
52 #define Gw OP_G, w_mode
53 #define Rw OP_rm, w_mode
54 #define Rd OP_rm, d_mode
55 #define Ib OP_I, b_mode
56 #define sIb OP_sI, b_mode /* sign extened byte */
57 #define Iv OP_I, v_mode
58 #define Iw OP_I, w_mode
59 #define Jb OP_J, b_mode
60 #define Jv OP_J, v_mode
62 #define Cd OP_C, d_mode
63 #define Dd OP_D, d_mode
64 #define Td OP_T, d_mode
66 #define eAX OP_REG, eAX_reg
67 #define eBX OP_REG, eBX_reg
68 #define eCX OP_REG, eCX_reg
69 #define eDX OP_REG, eDX_reg
70 #define eSP OP_REG, eSP_reg
71 #define eBP OP_REG, eBP_reg
72 #define eSI OP_REG, eSI_reg
73 #define eDI OP_REG, eDI_reg
74 #define AL OP_REG, al_reg
75 #define CL OP_REG, cl_reg
76 #define DL OP_REG, dl_reg
77 #define BL OP_REG, bl_reg
78 #define AH OP_REG, ah_reg
79 #define CH OP_REG, ch_reg
80 #define DH OP_REG, dh_reg
81 #define BH OP_REG, bh_reg
82 #define AX OP_REG, ax_reg
83 #define DX OP_REG, dx_reg
84 #define indirDX OP_REG, indir_dx_reg
86 #define Sw OP_SEG, w_mode
87 #define Ap OP_DIR, lptr
88 #define Av OP_DIR, v_mode
89 #define Ob OP_OFF, b_mode
90 #define Ov OP_OFF, v_mode
91 #define Xb OP_DSSI, b_mode
92 #define Xv OP_DSSI, v_mode
93 #define Yb OP_ESDI, b_mode
94 #define Yv OP_ESDI, v_mode
96 #define es OP_REG, es_reg
97 #define ss OP_REG, ss_reg
98 #define cs OP_REG, cs_reg
99 #define ds OP_REG, ds_reg
100 #define fs OP_REG, fs_reg
101 #define gs OP_REG, gs_reg
103 int OP_E(), OP_indirE(), OP_G(), OP_I(), OP_sI(), OP_REG();
104 int OP_J(), OP_SEG();
105 int OP_DIR(), OP_OFF(), OP_DSSI(), OP_ESDI(), OP_ONE(), OP_C();
106 int OP_D(), OP_T(), OP_rm();
149 #define indir_dx_reg 150
151 #define GRP1b NULL, NULL, 0
152 #define GRP1S NULL, NULL, 1
153 #define GRP1Ss NULL, NULL, 2
154 #define GRP2b NULL, NULL, 3
155 #define GRP2S NULL, NULL, 4
156 #define GRP2b_one NULL, NULL, 5
157 #define GRP2S_one NULL, NULL, 6
158 #define GRP2b_cl NULL, NULL, 7
159 #define GRP2S_cl NULL, NULL, 8
160 #define GRP3b NULL, NULL, 9
161 #define GRP3S NULL, NULL, 10
162 #define GRP4 NULL, NULL, 11
163 #define GRP5 NULL, NULL, 12
164 #define GRP6 NULL, NULL, 13
165 #define GRP7 NULL, NULL, 14
166 #define GRP8 NULL, NULL, 15
169 #define FLOAT NULL, NULL, FLOATCODE
181 struct dis386 dis386
[] = {
199 { "(bad)" }, /* 0x0f extended opcode escape */
225 { "(bad)" }, /* SEG ES prefix */
234 { "(bad)" }, /* SEG CS prefix */
243 { "(bad)" }, /* SEG SS prefix */
252 { "(bad)" }, /* SEG DS prefix */
293 { "boundS", Gv
, Ma
},
295 { "(bad)" }, /* seg fs */
296 { "(bad)" }, /* seg gs */
297 { "(bad)" }, /* op size prefix */
298 { "(bad)" }, /* adr size prefix */
300 { "pushS", Iv
}, /* 386 book wrong */
301 { "imulS", Gv
, Ev
, Iv
},
302 { "pushl", sIb
}, /* push of byte really pushes 4 bytes */
303 { "imulS", Gv
, Ev
, Ib
},
304 { "insb", Yb
, indirDX
},
305 { "insS", Yv
, indirDX
},
306 { "outsb", indirDX
, Xb
},
307 { "outsS", indirDX
, Xv
},
346 { "xchgS", eCX
, eAX
},
347 { "xchgS", eDX
, eAX
},
348 { "xchgS", eBX
, eAX
},
349 { "xchgS", eSP
, eAX
},
350 { "xchgS", eBP
, eAX
},
351 { "xchgS", eSI
, eAX
},
352 { "xchgS", eDI
, eAX
},
357 { "(bad)" }, /* fwait */
373 { "testS", eAX
, Iv
},
375 { "stosS", Yv
, eAX
},
377 { "lodsS", eAX
, Xv
},
379 { "scasS", eAX
, Xv
},
448 { "inb", AL
, indirDX
},
449 { "inS", eAX
, indirDX
},
450 { "outb", indirDX
, AL
},
451 { "outS", indirDX
, eAX
},
453 { "(bad)" }, /* lock prefix */
455 { "(bad)" }, /* repne */
456 { "(bad)" }, /* repz */
472 struct dis386 dis386_twobyte
[] = {
483 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
484 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
486 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
487 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
489 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
490 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
492 /* these are all backward in appendix A of the intel book */
502 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
503 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
505 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
506 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
508 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
509 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
511 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
512 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
514 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
515 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
517 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
518 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
520 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
521 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
523 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
524 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
526 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
527 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
529 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
530 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
532 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
533 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
575 { "shldS", Ev
, Gv
, Ib
},
576 { "shldS", Ev
, Gv
, CL
},
584 { "shrdS", Ev
, Gv
, Ib
},
585 { "shrdS", Ev
, Gv
, CL
},
591 { "lssS", Gv
, Mp
}, /* 386 lists only Mp */
593 { "lfsS", Gv
, Mp
}, /* 386 lists only Mp */
594 { "lgsS", Gv
, Mp
}, /* 386 lists only Mp */
595 { "movzbS", Gv
, Eb
},
596 { "movzwS", Gv
, Ew
},
604 { "movsbS", Gv
, Eb
},
605 { "movswS", Gv
, Ew
},
607 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
608 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
610 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
611 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
613 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
614 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
616 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
617 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
619 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
620 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
622 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
623 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
625 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
626 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
628 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
629 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
632 static char obuf
[100];
634 static char scratchbuf
[100];
635 static unsigned char *start_codep
;
636 static unsigned char *codep
;
640 static void oappend ();
642 static char *names32
[]={
643 "%eax","%ecx","%edx","%ebx", "%esp","%ebp","%esi","%edi",
645 static char *names16
[] = {
646 "%ax","%cx","%dx","%bx","%sp","%bp","%si","%di",
648 static char *names8
[] = {
649 "%al","%cl","%dl","%bl","%ah","%ch","%dh","%bh",
651 static char *names_seg
[] = {
652 "%es","%cs","%ss","%ds","%fs","%gs","%?","%?",
655 struct dis386 grps
[][8] = {
773 { "imulS", eAX
, Ev
},
775 { "idivS", eAX
, Ev
},
793 { "lcall", indirEv
},
834 #define PREFIX_REPZ 1
835 #define PREFIX_REPNZ 2
836 #define PREFIX_LOCK 4
838 #define PREFIX_SS 0x10
839 #define PREFIX_DS 0x20
840 #define PREFIX_ES 0x40
841 #define PREFIX_FS 0x80
842 #define PREFIX_GS 0x100
843 #define PREFIX_DATA 0x200
844 #define PREFIX_ADR 0x400
845 #define PREFIX_FWAIT 0x800
857 prefixes
|= PREFIX_REPZ
;
860 prefixes
|= PREFIX_REPNZ
;
863 prefixes
|= PREFIX_LOCK
;
866 prefixes
|= PREFIX_CS
;
869 prefixes
|= PREFIX_SS
;
872 prefixes
|= PREFIX_DS
;
875 prefixes
|= PREFIX_ES
;
878 prefixes
|= PREFIX_FS
;
881 prefixes
|= PREFIX_GS
;
884 prefixes
|= PREFIX_DATA
;
887 prefixes
|= PREFIX_ADR
;
890 prefixes
|= PREFIX_FWAIT
;
902 static char op1out
[100], op2out
[100], op3out
[100];
903 static int op_address
[3], op_ad
, op_index
[3];
905 extern void fputs_filtered ();
908 * disassemble the first instruction in 'inbuf'. You have to make
909 * sure all of the bytes of the instruction are filled in.
910 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
911 * (see topic "Redundant prefixes" in the "Differences from 8086"
912 * section of the "Virtual 8086 Mode" chapter.)
913 * 'pc' should be the address of this instruction, it will
914 * be used to print the target address if this is a relative jump or call
915 * 'outbuf' gets filled in with the disassembled instruction. it should
916 * be long enough to hold the longest disassembled instruction.
917 * 100 bytes is certainly enough, unless symbol printing is added later
918 * The function returns the length of this instruction in bytes.
920 i386dis (pc
, inbuf
, stream
)
922 unsigned char *inbuf
;
928 int enter_instruction
;
929 char *first
, *second
, *third
;
937 op_index
[0] = op_index
[1] = op_index
[2] = -1;
946 enter_instruction
= 1;
948 enter_instruction
= 0;
952 if (prefixes
& PREFIX_REPZ
)
954 if (prefixes
& PREFIX_REPNZ
)
956 if (prefixes
& PREFIX_LOCK
)
959 if ((prefixes
& PREFIX_FWAIT
)
960 && ((*codep
< 0xd8) || (*codep
> 0xdf)))
962 /* fwait not followed by floating point instruction */
963 fputs_filtered ("fwait", stream
);
967 /* these would be initialized to 0 if disassembling for 8086 or 286 */
971 if (prefixes
& PREFIX_DATA
)
974 if (prefixes
& PREFIX_ADR
)
981 dp
= &dis386_twobyte
[*++codep
];
983 dp
= &dis386
[*codep
];
985 mod
= (*codep
>> 6) & 3;
986 reg
= (*codep
>> 3) & 7;
989 if (dp
->name
== NULL
&& dp
->bytemode1
== FLOATCODE
)
995 if (dp
->name
== NULL
)
996 dp
= &grps
[dp
->bytemode1
][reg
];
1003 (*dp
->op1
)(dp
->bytemode1
);
1008 (*dp
->op2
)(dp
->bytemode2
);
1013 (*dp
->op3
)(dp
->bytemode3
);
1016 obufp
= obuf
+ strlen (obuf
);
1017 for (i
= strlen (obuf
); i
< 6; i
++)
1020 fputs_filtered (obuf
, stream
);
1022 /* enter instruction is printed with operands in the
1023 * same order as the intel book; everything else
1024 * is printed in reverse order
1026 if (enter_instruction
)
1031 op_ad
= op_index
[0];
1032 op_index
[0] = op_index
[2];
1033 op_index
[2] = op_ad
;
1044 if (op_index
[0] != -1)
1045 print_address (op_address
[op_index
[0]], stream
);
1047 fputs_filtered (first
, stream
);
1053 fputs_filtered (",", stream
);
1054 if (op_index
[1] != -1)
1055 print_address (op_address
[op_index
[1]], stream
);
1057 fputs_filtered (second
, stream
);
1063 fputs_filtered (",", stream
);
1064 if (op_index
[2] != -1)
1065 print_address (op_address
[op_index
[2]], stream
);
1067 fputs_filtered (third
, stream
);
1069 return (codep
- inbuf
);
1072 char *float_mem
[] = {
1148 #define STi OP_STi, 0
1149 int OP_ST(), OP_STi();
1151 #define FGRPd9_2 NULL, NULL, 0
1152 #define FGRPd9_4 NULL, NULL, 1
1153 #define FGRPd9_5 NULL, NULL, 2
1154 #define FGRPd9_6 NULL, NULL, 3
1155 #define FGRPd9_7 NULL, NULL, 4
1156 #define FGRPda_5 NULL, NULL, 5
1157 #define FGRPdb_4 NULL, NULL, 6
1158 #define FGRPde_3 NULL, NULL, 7
1159 #define FGRPdf_4 NULL, NULL, 8
1161 struct dis386 float_reg
[][8] = {
1164 { "fadd", ST
, STi
},
1165 { "fmul", ST
, STi
},
1168 { "fsub", ST
, STi
},
1169 { "fsubr", ST
, STi
},
1170 { "fdiv", ST
, STi
},
1171 { "fdivr", ST
, STi
},
1208 { "fadd", STi
, ST
},
1209 { "fmul", STi
, ST
},
1212 { "fsub", STi
, ST
},
1213 { "fsubr", STi
, ST
},
1214 { "fdiv", STi
, ST
},
1215 { "fdivr", STi
, ST
},
1230 { "faddp", STi
, ST
},
1231 { "fmulp", STi
, ST
},
1234 { "fsubp", STi
, ST
},
1235 { "fsubrp", STi
, ST
},
1236 { "fdivp", STi
, ST
},
1237 { "fdivrp", STi
, ST
},
1253 char *fgrps
[][8] = {
1256 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
1261 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
1266 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
1271 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
1276 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
1281 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
1286 "feni(287 only)","fdisi(287 only)","fNclex","fNinit",
1287 "fNsetpm(287 only)","(bad)","(bad)","(bad)",
1292 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
1297 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
1305 unsigned char floatop
;
1307 floatop
= codep
[-1];
1311 putop (float_mem
[(floatop
- 0xd8) * 8 + reg
]);
1318 dp
= &float_reg
[floatop
- 0xd8][reg
];
1319 if (dp
->name
== NULL
)
1321 putop (fgrps
[dp
->bytemode1
][rm
]);
1322 /* instruction fnstsw is only one with strange arg */
1323 if (floatop
== 0xdf && *codep
== 0xe0)
1324 strcpy (op1out
, "%eax");
1331 (*dp
->op1
)(dp
->bytemode1
);
1334 (*dp
->op2
)(dp
->bytemode2
);
1347 sprintf (scratchbuf
, "%%st(%d)", rm
);
1348 oappend (scratchbuf
);
1352 /* capital letters in template are macros */
1358 for (p
= template; *p
; p
++)
1365 case 'C': /* For jcxz/jecxz */
1370 if ((prefixes
& PREFIX_FWAIT
) == 0)
1374 /* operand size flag */
1390 obufp
+= strlen (s
);
1396 if (prefixes
& PREFIX_CS
)
1398 if (prefixes
& PREFIX_DS
)
1400 if (prefixes
& PREFIX_SS
)
1402 if (prefixes
& PREFIX_ES
)
1404 if (prefixes
& PREFIX_FS
)
1406 if (prefixes
& PREFIX_GS
)
1410 OP_indirE (bytemode
)
1426 /* skip mod/rm byte */
1438 oappend (names8
[rm
]);
1441 oappend (names16
[rm
]);
1445 oappend (names32
[rm
]);
1447 oappend (names16
[rm
]);
1450 oappend ("<bad dis table>");
1461 scale
= (*codep
>> 6) & 3;
1462 index
= (*codep
>> 3) & 7;
1473 /* implies havesib and havebase */
1489 disp
= *(char *)codep
++;
1506 if (mod
!= 0 || rm
== 5 || (havesib
&& base
== 5))
1508 sprintf (scratchbuf
, "0x%x", disp
);
1509 oappend (scratchbuf
);
1512 if (havebase
|| havesib
)
1516 oappend (names32
[base
]);
1521 sprintf (scratchbuf
, ",%s", names32
[index
]);
1522 oappend (scratchbuf
);
1524 sprintf (scratchbuf
, ",%d", 1 << scale
);
1525 oappend (scratchbuf
);
1536 oappend (names8
[reg
]);
1539 oappend (names16
[reg
]);
1542 oappend (names32
[reg
]);
1546 oappend (names32
[reg
]);
1548 oappend (names16
[reg
]);
1551 oappend ("<internal disassembler error>");
1560 x
= *codep
++ & 0xff;
1561 x
|= (*codep
++ & 0xff) << 8;
1562 x
|= (*codep
++ & 0xff) << 16;
1563 x
|= (*codep
++ & 0xff) << 24;
1571 x
= *codep
++ & 0xff;
1572 x
|= (*codep
++ & 0xff) << 8;
1579 op_index
[op_ad
] = op_ad
;
1580 op_address
[op_ad
] = op
;
1589 case indir_dx_reg
: s
= "(%dx)"; break;
1590 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
1591 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
1592 s
= names16
[code
- ax_reg
];
1594 case es_reg
: case ss_reg
: case cs_reg
:
1595 case ds_reg
: case fs_reg
: case gs_reg
:
1596 s
= names_seg
[code
- es_reg
];
1598 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
1599 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
1600 s
= names8
[code
- al_reg
];
1602 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
1603 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
1605 s
= names32
[code
- eAX_reg
];
1607 s
= names16
[code
- eAX_reg
];
1610 s
= "<internal disassembler error>";
1623 op
= *codep
++ & 0xff;
1635 oappend ("<internal disassembler error>");
1638 sprintf (scratchbuf
, "$0x%x", op
);
1639 oappend (scratchbuf
);
1649 op
= *(char *)codep
++;
1655 op
= (short)get16();
1658 op
= (short)get16 ();
1661 oappend ("<internal disassembler error>");
1664 sprintf (scratchbuf
, "$0x%x", op
);
1665 oappend (scratchbuf
);
1676 disp
= *(char *)codep
++;
1683 disp
= (short)get16 ();
1684 /* for some reason, a data16 prefix on a jump instruction
1685 means that the pc is masked to 16 bits after the
1686 displacement is added! */
1691 oappend ("<internal disassembler error>");
1694 disp
= (start_pc
+ codep
- start_codep
+ disp
) & mask
;
1696 sprintf (scratchbuf
, "0x%x", disp
);
1697 oappend (scratchbuf
);
1703 static char *sreg
[] = {
1704 "%es","%cs","%ss","%ds","%fs","%gs","%?","%?",
1707 oappend (sreg
[reg
]);
1727 sprintf (scratchbuf
, "0x%x,0x%x", seg
, offset
);
1728 oappend (scratchbuf
);
1734 offset
= (short)get16 ();
1736 offset
= start_pc
+ codep
- start_codep
+ offset
;
1738 sprintf (scratchbuf
, "0x%x", offset
);
1739 oappend (scratchbuf
);
1742 oappend ("<internal disassembler error>");
1757 sprintf (scratchbuf
, "0x%x", off
);
1758 oappend (scratchbuf
);
1765 oappend (aflag
? "%edi" : "%di");
1773 oappend (aflag
? "%esi" : "%si");
1786 codep
++; /* skip mod/rm */
1787 sprintf (scratchbuf
, "%%cr%d", reg
);
1788 oappend (scratchbuf
);
1794 codep
++; /* skip mod/rm */
1795 sprintf (scratchbuf
, "%%db%d", reg
);
1796 oappend (scratchbuf
);
1802 codep
++; /* skip mod/rm */
1803 sprintf (scratchbuf
, "%%tr%d", reg
);
1804 oappend (scratchbuf
);
1812 oappend (names32
[rm
]);
1815 oappend (names16
[rm
]);
1821 print_insn (memaddr
, stream
)
1825 unsigned char buffer
[MAXLEN
];
1827 read_memory (memaddr
, buffer
, MAXLEN
);
1829 return (i386dis ((int)memaddr
, buffer
, stream
));
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