1 /* Intel 386 target-dependent stuff.
3 Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009,
5 2010, 2011 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "opcode/i386.h"
24 #include "arch-utils.h"
26 #include "dummy-frame.h"
27 #include "dwarf2-frame.h"
30 #include "frame-base.h"
31 #include "frame-unwind.h"
39 #include "reggroups.h"
48 #include "exceptions.h"
49 #include "gdb_assert.h"
50 #include "gdb_string.h"
52 #include "i386-tdep.h"
53 #include "i387-tdep.h"
54 #include "i386-xstate.h"
59 #include "features/i386/i386.c"
60 #include "features/i386/i386-avx.c"
61 #include "features/i386/i386-mmx.c"
65 static const char *i386_register_names
[] =
67 "eax", "ecx", "edx", "ebx",
68 "esp", "ebp", "esi", "edi",
69 "eip", "eflags", "cs", "ss",
70 "ds", "es", "fs", "gs",
71 "st0", "st1", "st2", "st3",
72 "st4", "st5", "st6", "st7",
73 "fctrl", "fstat", "ftag", "fiseg",
74 "fioff", "foseg", "fooff", "fop",
75 "xmm0", "xmm1", "xmm2", "xmm3",
76 "xmm4", "xmm5", "xmm6", "xmm7",
80 static const char *i386_ymm_names
[] =
82 "ymm0", "ymm1", "ymm2", "ymm3",
83 "ymm4", "ymm5", "ymm6", "ymm7",
86 static const char *i386_ymmh_names
[] =
88 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
89 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
92 /* Register names for MMX pseudo-registers. */
94 static const char *i386_mmx_names
[] =
96 "mm0", "mm1", "mm2", "mm3",
97 "mm4", "mm5", "mm6", "mm7"
100 /* Register names for byte pseudo-registers. */
102 static const char *i386_byte_names
[] =
104 "al", "cl", "dl", "bl",
105 "ah", "ch", "dh", "bh"
108 /* Register names for word pseudo-registers. */
110 static const char *i386_word_names
[] =
112 "ax", "cx", "dx", "bx",
119 i386_mmx_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
121 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
122 int mm0_regnum
= tdep
->mm0_regnum
;
127 regnum
-= mm0_regnum
;
128 return regnum
>= 0 && regnum
< tdep
->num_mmx_regs
;
134 i386_byte_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
136 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
138 regnum
-= tdep
->al_regnum
;
139 return regnum
>= 0 && regnum
< tdep
->num_byte_regs
;
145 i386_word_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
147 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
149 regnum
-= tdep
->ax_regnum
;
150 return regnum
>= 0 && regnum
< tdep
->num_word_regs
;
153 /* Dword register? */
156 i386_dword_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
158 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
159 int eax_regnum
= tdep
->eax_regnum
;
164 regnum
-= eax_regnum
;
165 return regnum
>= 0 && regnum
< tdep
->num_dword_regs
;
169 i386_ymmh_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
171 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
172 int ymm0h_regnum
= tdep
->ymm0h_regnum
;
174 if (ymm0h_regnum
< 0)
177 regnum
-= ymm0h_regnum
;
178 return regnum
>= 0 && regnum
< tdep
->num_ymm_regs
;
184 i386_ymm_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
186 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
187 int ymm0_regnum
= tdep
->ymm0_regnum
;
192 regnum
-= ymm0_regnum
;
193 return regnum
>= 0 && regnum
< tdep
->num_ymm_regs
;
199 i386_xmm_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
201 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
202 int num_xmm_regs
= I387_NUM_XMM_REGS (tdep
);
204 if (num_xmm_regs
== 0)
207 regnum
-= I387_XMM0_REGNUM (tdep
);
208 return regnum
>= 0 && regnum
< num_xmm_regs
;
212 i386_mxcsr_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
214 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
216 if (I387_NUM_XMM_REGS (tdep
) == 0)
219 return (regnum
== I387_MXCSR_REGNUM (tdep
));
225 i386_fp_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
227 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
229 if (I387_ST0_REGNUM (tdep
) < 0)
232 return (I387_ST0_REGNUM (tdep
) <= regnum
233 && regnum
< I387_FCTRL_REGNUM (tdep
));
237 i386_fpc_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
239 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
241 if (I387_ST0_REGNUM (tdep
) < 0)
244 return (I387_FCTRL_REGNUM (tdep
) <= regnum
245 && regnum
< I387_XMM0_REGNUM (tdep
));
248 /* Return the name of register REGNUM, or the empty string if it is
249 an anonymous register. */
252 i386_register_name (struct gdbarch
*gdbarch
, int regnum
)
254 /* Hide the upper YMM registers. */
255 if (i386_ymmh_regnum_p (gdbarch
, regnum
))
258 return tdesc_register_name (gdbarch
, regnum
);
261 /* Return the name of register REGNUM. */
264 i386_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
266 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
267 if (i386_mmx_regnum_p (gdbarch
, regnum
))
268 return i386_mmx_names
[regnum
- I387_MM0_REGNUM (tdep
)];
269 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
270 return i386_ymm_names
[regnum
- tdep
->ymm0_regnum
];
271 else if (i386_byte_regnum_p (gdbarch
, regnum
))
272 return i386_byte_names
[regnum
- tdep
->al_regnum
];
273 else if (i386_word_regnum_p (gdbarch
, regnum
))
274 return i386_word_names
[regnum
- tdep
->ax_regnum
];
276 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
279 /* Convert a dbx register number REG to the appropriate register
280 number used by GDB. */
283 i386_dbx_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
285 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
287 /* This implements what GCC calls the "default" register map
288 (dbx_register_map[]). */
290 if (reg
>= 0 && reg
<= 7)
292 /* General-purpose registers. The debug info calls %ebp
293 register 4, and %esp register 5. */
300 else if (reg
>= 12 && reg
<= 19)
302 /* Floating-point registers. */
303 return reg
- 12 + I387_ST0_REGNUM (tdep
);
305 else if (reg
>= 21 && reg
<= 28)
308 int ymm0_regnum
= tdep
->ymm0_regnum
;
311 && i386_xmm_regnum_p (gdbarch
, reg
))
312 return reg
- 21 + ymm0_regnum
;
314 return reg
- 21 + I387_XMM0_REGNUM (tdep
);
316 else if (reg
>= 29 && reg
<= 36)
319 return reg
- 29 + I387_MM0_REGNUM (tdep
);
322 /* This will hopefully provoke a warning. */
323 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
326 /* Convert SVR4 register number REG to the appropriate register number
330 i386_svr4_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
332 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
334 /* This implements the GCC register map that tries to be compatible
335 with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */
337 /* The SVR4 register numbering includes %eip and %eflags, and
338 numbers the floating point registers differently. */
339 if (reg
>= 0 && reg
<= 9)
341 /* General-purpose registers. */
344 else if (reg
>= 11 && reg
<= 18)
346 /* Floating-point registers. */
347 return reg
- 11 + I387_ST0_REGNUM (tdep
);
349 else if (reg
>= 21 && reg
<= 36)
351 /* The SSE and MMX registers have the same numbers as with dbx. */
352 return i386_dbx_reg_to_regnum (gdbarch
, reg
);
357 case 37: return I387_FCTRL_REGNUM (tdep
);
358 case 38: return I387_FSTAT_REGNUM (tdep
);
359 case 39: return I387_MXCSR_REGNUM (tdep
);
360 case 40: return I386_ES_REGNUM
;
361 case 41: return I386_CS_REGNUM
;
362 case 42: return I386_SS_REGNUM
;
363 case 43: return I386_DS_REGNUM
;
364 case 44: return I386_FS_REGNUM
;
365 case 45: return I386_GS_REGNUM
;
368 /* This will hopefully provoke a warning. */
369 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
374 /* This is the variable that is set with "set disassembly-flavor", and
375 its legitimate values. */
376 static const char att_flavor
[] = "att";
377 static const char intel_flavor
[] = "intel";
378 static const char *valid_flavors
[] =
384 static const char *disassembly_flavor
= att_flavor
;
387 /* Use the program counter to determine the contents and size of a
388 breakpoint instruction. Return a pointer to a string of bytes that
389 encode a breakpoint instruction, store the length of the string in
390 *LEN and optionally adjust *PC to point to the correct memory
391 location for inserting the breakpoint.
393 On the i386 we have a single breakpoint that fits in a single byte
394 and can be inserted anywhere.
396 This function is 64-bit safe. */
398 static const gdb_byte
*
399 i386_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pc
, int *len
)
401 static gdb_byte break_insn
[] = { 0xcc }; /* int 3 */
403 *len
= sizeof (break_insn
);
407 /* Displaced instruction handling. */
409 /* Skip the legacy instruction prefixes in INSN.
410 Not all prefixes are valid for any particular insn
411 but we needn't care, the insn will fault if it's invalid.
412 The result is a pointer to the first opcode byte,
413 or NULL if we run off the end of the buffer. */
416 i386_skip_prefixes (gdb_byte
*insn
, size_t max_len
)
418 gdb_byte
*end
= insn
+ max_len
;
424 case DATA_PREFIX_OPCODE
:
425 case ADDR_PREFIX_OPCODE
:
426 case CS_PREFIX_OPCODE
:
427 case DS_PREFIX_OPCODE
:
428 case ES_PREFIX_OPCODE
:
429 case FS_PREFIX_OPCODE
:
430 case GS_PREFIX_OPCODE
:
431 case SS_PREFIX_OPCODE
:
432 case LOCK_PREFIX_OPCODE
:
433 case REPE_PREFIX_OPCODE
:
434 case REPNE_PREFIX_OPCODE
:
446 i386_absolute_jmp_p (const gdb_byte
*insn
)
448 /* jmp far (absolute address in operand). */
454 /* jump near, absolute indirect (/4). */
455 if ((insn
[1] & 0x38) == 0x20)
458 /* jump far, absolute indirect (/5). */
459 if ((insn
[1] & 0x38) == 0x28)
467 i386_absolute_call_p (const gdb_byte
*insn
)
469 /* call far, absolute. */
475 /* Call near, absolute indirect (/2). */
476 if ((insn
[1] & 0x38) == 0x10)
479 /* Call far, absolute indirect (/3). */
480 if ((insn
[1] & 0x38) == 0x18)
488 i386_ret_p (const gdb_byte
*insn
)
492 case 0xc2: /* ret near, pop N bytes. */
493 case 0xc3: /* ret near */
494 case 0xca: /* ret far, pop N bytes. */
495 case 0xcb: /* ret far */
496 case 0xcf: /* iret */
505 i386_call_p (const gdb_byte
*insn
)
507 if (i386_absolute_call_p (insn
))
510 /* call near, relative. */
517 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
518 length in bytes. Otherwise, return zero. */
521 i386_syscall_p (const gdb_byte
*insn
, int *lengthp
)
532 /* Some kernels may run one past a syscall insn, so we have to cope.
533 Otherwise this is just simple_displaced_step_copy_insn. */
535 struct displaced_step_closure
*
536 i386_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
537 CORE_ADDR from
, CORE_ADDR to
,
538 struct regcache
*regs
)
540 size_t len
= gdbarch_max_insn_length (gdbarch
);
541 gdb_byte
*buf
= xmalloc (len
);
543 read_memory (from
, buf
, len
);
545 /* GDB may get control back after the insn after the syscall.
546 Presumably this is a kernel bug.
547 If this is a syscall, make sure there's a nop afterwards. */
552 insn
= i386_skip_prefixes (buf
, len
);
553 if (insn
!= NULL
&& i386_syscall_p (insn
, &syscall_length
))
554 insn
[syscall_length
] = NOP_OPCODE
;
557 write_memory (to
, buf
, len
);
561 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
562 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
563 displaced_step_dump_bytes (gdb_stdlog
, buf
, len
);
566 return (struct displaced_step_closure
*) buf
;
569 /* Fix up the state of registers and memory after having single-stepped
570 a displaced instruction. */
573 i386_displaced_step_fixup (struct gdbarch
*gdbarch
,
574 struct displaced_step_closure
*closure
,
575 CORE_ADDR from
, CORE_ADDR to
,
576 struct regcache
*regs
)
578 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
580 /* The offset we applied to the instruction's address.
581 This could well be negative (when viewed as a signed 32-bit
582 value), but ULONGEST won't reflect that, so take care when
584 ULONGEST insn_offset
= to
- from
;
586 /* Since we use simple_displaced_step_copy_insn, our closure is a
587 copy of the instruction. */
588 gdb_byte
*insn
= (gdb_byte
*) closure
;
589 /* The start of the insn, needed in case we see some prefixes. */
590 gdb_byte
*insn_start
= insn
;
593 fprintf_unfiltered (gdb_stdlog
,
594 "displaced: fixup (%s, %s), "
595 "insn = 0x%02x 0x%02x ...\n",
596 paddress (gdbarch
, from
), paddress (gdbarch
, to
),
599 /* The list of issues to contend with here is taken from
600 resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20.
601 Yay for Free Software! */
603 /* Relocate the %eip, if necessary. */
605 /* The instruction recognizers we use assume any leading prefixes
606 have been skipped. */
608 /* This is the size of the buffer in closure. */
609 size_t max_insn_len
= gdbarch_max_insn_length (gdbarch
);
610 gdb_byte
*opcode
= i386_skip_prefixes (insn
, max_insn_len
);
611 /* If there are too many prefixes, just ignore the insn.
612 It will fault when run. */
617 /* Except in the case of absolute or indirect jump or call
618 instructions, or a return instruction, the new eip is relative to
619 the displaced instruction; make it relative. Well, signal
620 handler returns don't need relocation either, but we use the
621 value of %eip to recognize those; see below. */
622 if (! i386_absolute_jmp_p (insn
)
623 && ! i386_absolute_call_p (insn
)
624 && ! i386_ret_p (insn
))
629 regcache_cooked_read_unsigned (regs
, I386_EIP_REGNUM
, &orig_eip
);
631 /* A signal trampoline system call changes the %eip, resuming
632 execution of the main program after the signal handler has
633 returned. That makes them like 'return' instructions; we
634 shouldn't relocate %eip.
636 But most system calls don't, and we do need to relocate %eip.
638 Our heuristic for distinguishing these cases: if stepping
639 over the system call instruction left control directly after
640 the instruction, the we relocate --- control almost certainly
641 doesn't belong in the displaced copy. Otherwise, we assume
642 the instruction has put control where it belongs, and leave
643 it unrelocated. Goodness help us if there are PC-relative
645 if (i386_syscall_p (insn
, &insn_len
)
646 && orig_eip
!= to
+ (insn
- insn_start
) + insn_len
647 /* GDB can get control back after the insn after the syscall.
648 Presumably this is a kernel bug.
649 i386_displaced_step_copy_insn ensures its a nop,
650 we add one to the length for it. */
651 && orig_eip
!= to
+ (insn
- insn_start
) + insn_len
+ 1)
654 fprintf_unfiltered (gdb_stdlog
,
655 "displaced: syscall changed %%eip; "
660 ULONGEST eip
= (orig_eip
- insn_offset
) & 0xffffffffUL
;
662 /* If we just stepped over a breakpoint insn, we don't backup
663 the pc on purpose; this is to match behaviour without
666 regcache_cooked_write_unsigned (regs
, I386_EIP_REGNUM
, eip
);
669 fprintf_unfiltered (gdb_stdlog
,
671 "relocated %%eip from %s to %s\n",
672 paddress (gdbarch
, orig_eip
),
673 paddress (gdbarch
, eip
));
677 /* If the instruction was PUSHFL, then the TF bit will be set in the
678 pushed value, and should be cleared. We'll leave this for later,
679 since GDB already messes up the TF flag when stepping over a
682 /* If the instruction was a call, the return address now atop the
683 stack is the address following the copied instruction. We need
684 to make it the address following the original instruction. */
685 if (i386_call_p (insn
))
689 const ULONGEST retaddr_len
= 4;
691 regcache_cooked_read_unsigned (regs
, I386_ESP_REGNUM
, &esp
);
692 retaddr
= read_memory_unsigned_integer (esp
, retaddr_len
, byte_order
);
693 retaddr
= (retaddr
- insn_offset
) & 0xffffffffUL
;
694 write_memory_unsigned_integer (esp
, retaddr_len
, byte_order
, retaddr
);
697 fprintf_unfiltered (gdb_stdlog
,
698 "displaced: relocated return addr at %s to %s\n",
699 paddress (gdbarch
, esp
),
700 paddress (gdbarch
, retaddr
));
705 append_insns (CORE_ADDR
*to
, ULONGEST len
, const gdb_byte
*buf
)
707 target_write_memory (*to
, buf
, len
);
712 i386_relocate_instruction (struct gdbarch
*gdbarch
,
713 CORE_ADDR
*to
, CORE_ADDR oldloc
)
715 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
716 gdb_byte buf
[I386_MAX_INSN_LEN
];
717 int offset
= 0, rel32
, newrel
;
719 gdb_byte
*insn
= buf
;
721 read_memory (oldloc
, buf
, I386_MAX_INSN_LEN
);
723 insn_length
= gdb_buffered_insn_length (gdbarch
, insn
,
724 I386_MAX_INSN_LEN
, oldloc
);
726 /* Get past the prefixes. */
727 insn
= i386_skip_prefixes (insn
, I386_MAX_INSN_LEN
);
729 /* Adjust calls with 32-bit relative addresses as push/jump, with
730 the address pushed being the location where the original call in
731 the user program would return to. */
734 gdb_byte push_buf
[16];
735 unsigned int ret_addr
;
737 /* Where "ret" in the original code will return to. */
738 ret_addr
= oldloc
+ insn_length
;
739 push_buf
[0] = 0x68; /* pushq $... */
740 memcpy (&push_buf
[1], &ret_addr
, 4);
742 append_insns (to
, 5, push_buf
);
744 /* Convert the relative call to a relative jump. */
747 /* Adjust the destination offset. */
748 rel32
= extract_signed_integer (insn
+ 1, 4, byte_order
);
749 newrel
= (oldloc
- *to
) + rel32
;
750 store_signed_integer (insn
+ 1, 4, byte_order
, newrel
);
753 fprintf_unfiltered (gdb_stdlog
,
754 "Adjusted insn rel32=%s at %s to"
756 hex_string (rel32
), paddress (gdbarch
, oldloc
),
757 hex_string (newrel
), paddress (gdbarch
, *to
));
759 /* Write the adjusted jump into its displaced location. */
760 append_insns (to
, 5, insn
);
764 /* Adjust jumps with 32-bit relative addresses. Calls are already
768 /* Adjust conditional jumps. */
769 else if (insn
[0] == 0x0f && (insn
[1] & 0xf0) == 0x80)
774 rel32
= extract_signed_integer (insn
+ offset
, 4, byte_order
);
775 newrel
= (oldloc
- *to
) + rel32
;
776 store_signed_integer (insn
+ offset
, 4, byte_order
, newrel
);
778 fprintf_unfiltered (gdb_stdlog
,
779 "Adjusted insn rel32=%s at %s to"
781 hex_string (rel32
), paddress (gdbarch
, oldloc
),
782 hex_string (newrel
), paddress (gdbarch
, *to
));
785 /* Write the adjusted instructions into their displaced
787 append_insns (to
, insn_length
, buf
);
791 #ifdef I386_REGNO_TO_SYMMETRY
792 #error "The Sequent Symmetry is no longer supported."
795 /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi
796 and %esp "belong" to the calling function. Therefore these
797 registers should be saved if they're going to be modified. */
799 /* The maximum number of saved registers. This should include all
800 registers mentioned above, and %eip. */
801 #define I386_NUM_SAVED_REGS I386_NUM_GREGS
803 struct i386_frame_cache
811 /* Saved registers. */
812 CORE_ADDR saved_regs
[I386_NUM_SAVED_REGS
];
817 /* Stack space reserved for local variables. */
821 /* Allocate and initialize a frame cache. */
823 static struct i386_frame_cache
*
824 i386_alloc_frame_cache (void)
826 struct i386_frame_cache
*cache
;
829 cache
= FRAME_OBSTACK_ZALLOC (struct i386_frame_cache
);
834 cache
->sp_offset
= -4;
837 /* Saved registers. We initialize these to -1 since zero is a valid
838 offset (that's where %ebp is supposed to be stored). */
839 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
840 cache
->saved_regs
[i
] = -1;
842 cache
->saved_sp_reg
= -1;
843 cache
->pc_in_eax
= 0;
845 /* Frameless until proven otherwise. */
851 /* If the instruction at PC is a jump, return the address of its
852 target. Otherwise, return PC. */
855 i386_follow_jump (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
857 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
862 if (target_read_memory (pc
, &op
, 1))
868 op
= read_memory_unsigned_integer (pc
+ 1, 1, byte_order
);
874 /* Relative jump: if data16 == 0, disp32, else disp16. */
877 delta
= read_memory_integer (pc
+ 2, 2, byte_order
);
879 /* Include the size of the jmp instruction (including the
885 delta
= read_memory_integer (pc
+ 1, 4, byte_order
);
887 /* Include the size of the jmp instruction. */
892 /* Relative jump, disp8 (ignore data16). */
893 delta
= read_memory_integer (pc
+ data16
+ 1, 1, byte_order
);
902 /* Check whether PC points at a prologue for a function returning a
903 structure or union. If so, it updates CACHE and returns the
904 address of the first instruction after the code sequence that
905 removes the "hidden" argument from the stack or CURRENT_PC,
906 whichever is smaller. Otherwise, return PC. */
909 i386_analyze_struct_return (CORE_ADDR pc
, CORE_ADDR current_pc
,
910 struct i386_frame_cache
*cache
)
912 /* Functions that return a structure or union start with:
915 xchgl %eax, (%esp) 0x87 0x04 0x24
916 or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00
918 (the System V compiler puts out the second `xchg' instruction,
919 and the assembler doesn't try to optimize it, so the 'sib' form
920 gets generated). This sequence is used to get the address of the
921 return buffer for a function that returns a structure. */
922 static gdb_byte proto1
[3] = { 0x87, 0x04, 0x24 };
923 static gdb_byte proto2
[4] = { 0x87, 0x44, 0x24, 0x00 };
927 if (current_pc
<= pc
)
930 if (target_read_memory (pc
, &op
, 1))
933 if (op
!= 0x58) /* popl %eax */
936 if (target_read_memory (pc
+ 1, buf
, 4))
939 if (memcmp (buf
, proto1
, 3) != 0 && memcmp (buf
, proto2
, 4) != 0)
942 if (current_pc
== pc
)
944 cache
->sp_offset
+= 4;
948 if (current_pc
== pc
+ 1)
950 cache
->pc_in_eax
= 1;
954 if (buf
[1] == proto1
[1])
961 i386_skip_probe (CORE_ADDR pc
)
963 /* A function may start with
977 if (target_read_memory (pc
, &op
, 1))
980 if (op
== 0x68 || op
== 0x6a)
984 /* Skip past the `pushl' instruction; it has either a one-byte or a
985 four-byte operand, depending on the opcode. */
991 /* Read the following 8 bytes, which should be `call _probe' (6
992 bytes) followed by `addl $4,%esp' (2 bytes). */
993 read_memory (pc
+ delta
, buf
, sizeof (buf
));
994 if (buf
[0] == 0xe8 && buf
[6] == 0xc4 && buf
[7] == 0x4)
995 pc
+= delta
+ sizeof (buf
);
1001 /* GCC 4.1 and later, can put code in the prologue to realign the
1002 stack pointer. Check whether PC points to such code, and update
1003 CACHE accordingly. Return the first instruction after the code
1004 sequence or CURRENT_PC, whichever is smaller. If we don't
1005 recognize the code, return PC. */
1008 i386_analyze_stack_align (CORE_ADDR pc
, CORE_ADDR current_pc
,
1009 struct i386_frame_cache
*cache
)
1011 /* There are 2 code sequences to re-align stack before the frame
1014 1. Use a caller-saved saved register:
1020 2. Use a callee-saved saved register:
1027 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
1029 0x83 0xe4 0xf0 andl $-16, %esp
1030 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
1035 int offset
, offset_and
;
1036 static int regnums
[8] = {
1037 I386_EAX_REGNUM
, /* %eax */
1038 I386_ECX_REGNUM
, /* %ecx */
1039 I386_EDX_REGNUM
, /* %edx */
1040 I386_EBX_REGNUM
, /* %ebx */
1041 I386_ESP_REGNUM
, /* %esp */
1042 I386_EBP_REGNUM
, /* %ebp */
1043 I386_ESI_REGNUM
, /* %esi */
1044 I386_EDI_REGNUM
/* %edi */
1047 if (target_read_memory (pc
, buf
, sizeof buf
))
1050 /* Check caller-saved saved register. The first instruction has
1051 to be "leal 4(%esp), %reg". */
1052 if (buf
[0] == 0x8d && buf
[2] == 0x24 && buf
[3] == 0x4)
1054 /* MOD must be binary 10 and R/M must be binary 100. */
1055 if ((buf
[1] & 0xc7) != 0x44)
1058 /* REG has register number. */
1059 reg
= (buf
[1] >> 3) & 7;
1064 /* Check callee-saved saved register. The first instruction
1065 has to be "pushl %reg". */
1066 if ((buf
[0] & 0xf8) != 0x50)
1072 /* The next instruction has to be "leal 8(%esp), %reg". */
1073 if (buf
[1] != 0x8d || buf
[3] != 0x24 || buf
[4] != 0x8)
1076 /* MOD must be binary 10 and R/M must be binary 100. */
1077 if ((buf
[2] & 0xc7) != 0x44)
1080 /* REG has register number. Registers in pushl and leal have to
1082 if (reg
!= ((buf
[2] >> 3) & 7))
1088 /* Rigister can't be %esp nor %ebp. */
1089 if (reg
== 4 || reg
== 5)
1092 /* The next instruction has to be "andl $-XXX, %esp". */
1093 if (buf
[offset
+ 1] != 0xe4
1094 || (buf
[offset
] != 0x81 && buf
[offset
] != 0x83))
1097 offset_and
= offset
;
1098 offset
+= buf
[offset
] == 0x81 ? 6 : 3;
1100 /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is
1101 0xfc. REG must be binary 110 and MOD must be binary 01. */
1102 if (buf
[offset
] != 0xff
1103 || buf
[offset
+ 2] != 0xfc
1104 || (buf
[offset
+ 1] & 0xf8) != 0x70)
1107 /* R/M has register. Registers in leal and pushl have to be the
1109 if (reg
!= (buf
[offset
+ 1] & 7))
1112 if (current_pc
> pc
+ offset_and
)
1113 cache
->saved_sp_reg
= regnums
[reg
];
1115 return min (pc
+ offset
+ 3, current_pc
);
1118 /* Maximum instruction length we need to handle. */
1119 #define I386_MAX_MATCHED_INSN_LEN 6
1121 /* Instruction description. */
1125 gdb_byte insn
[I386_MAX_MATCHED_INSN_LEN
];
1126 gdb_byte mask
[I386_MAX_MATCHED_INSN_LEN
];
1129 /* Return whether instruction at PC matches PATTERN. */
1132 i386_match_pattern (CORE_ADDR pc
, struct i386_insn pattern
)
1136 if (target_read_memory (pc
, &op
, 1))
1139 if ((op
& pattern
.mask
[0]) == pattern
.insn
[0])
1141 gdb_byte buf
[I386_MAX_MATCHED_INSN_LEN
- 1];
1142 int insn_matched
= 1;
1145 gdb_assert (pattern
.len
> 1);
1146 gdb_assert (pattern
.len
<= I386_MAX_MATCHED_INSN_LEN
);
1148 if (target_read_memory (pc
+ 1, buf
, pattern
.len
- 1))
1151 for (i
= 1; i
< pattern
.len
; i
++)
1153 if ((buf
[i
- 1] & pattern
.mask
[i
]) != pattern
.insn
[i
])
1156 return insn_matched
;
1161 /* Search for the instruction at PC in the list INSN_PATTERNS. Return
1162 the first instruction description that matches. Otherwise, return
1165 static struct i386_insn
*
1166 i386_match_insn (CORE_ADDR pc
, struct i386_insn
*insn_patterns
)
1168 struct i386_insn
*pattern
;
1170 for (pattern
= insn_patterns
; pattern
->len
> 0; pattern
++)
1172 if (i386_match_pattern (pc
, *pattern
))
1179 /* Return whether PC points inside a sequence of instructions that
1180 matches INSN_PATTERNS. */
1183 i386_match_insn_block (CORE_ADDR pc
, struct i386_insn
*insn_patterns
)
1185 CORE_ADDR current_pc
;
1188 struct i386_insn
*insn
;
1190 insn
= i386_match_insn (pc
, insn_patterns
);
1195 ix
= insn
- insn_patterns
;
1196 for (i
= ix
- 1; i
>= 0; i
--)
1198 current_pc
-= insn_patterns
[i
].len
;
1200 if (!i386_match_pattern (current_pc
, insn_patterns
[i
]))
1204 current_pc
= pc
+ insn
->len
;
1205 for (insn
= insn_patterns
+ ix
+ 1; insn
->len
> 0; insn
++)
1207 if (!i386_match_pattern (current_pc
, *insn
))
1210 current_pc
+= insn
->len
;
1216 /* Some special instructions that might be migrated by GCC into the
1217 part of the prologue that sets up the new stack frame. Because the
1218 stack frame hasn't been setup yet, no registers have been saved
1219 yet, and only the scratch registers %eax, %ecx and %edx can be
1222 struct i386_insn i386_frame_setup_skip_insns
[] =
1224 /* Check for `movb imm8, r' and `movl imm32, r'.
1226 ??? Should we handle 16-bit operand-sizes here? */
1228 /* `movb imm8, %al' and `movb imm8, %ah' */
1229 /* `movb imm8, %cl' and `movb imm8, %ch' */
1230 { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } },
1231 /* `movb imm8, %dl' and `movb imm8, %dh' */
1232 { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } },
1233 /* `movl imm32, %eax' and `movl imm32, %ecx' */
1234 { 5, { 0xb8 }, { 0xfe } },
1235 /* `movl imm32, %edx' */
1236 { 5, { 0xba }, { 0xff } },
1238 /* Check for `mov imm32, r32'. Note that there is an alternative
1239 encoding for `mov m32, %eax'.
1241 ??? Should we handle SIB adressing here?
1242 ??? Should we handle 16-bit operand-sizes here? */
1244 /* `movl m32, %eax' */
1245 { 5, { 0xa1 }, { 0xff } },
1246 /* `movl m32, %eax' and `mov; m32, %ecx' */
1247 { 6, { 0x89, 0x05 }, {0xff, 0xf7 } },
1248 /* `movl m32, %edx' */
1249 { 6, { 0x89, 0x15 }, {0xff, 0xff } },
1251 /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'.
1252 Because of the symmetry, there are actually two ways to encode
1253 these instructions; opcode bytes 0x29 and 0x2b for `subl' and
1254 opcode bytes 0x31 and 0x33 for `xorl'. */
1256 /* `subl %eax, %eax' */
1257 { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } },
1258 /* `subl %ecx, %ecx' */
1259 { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } },
1260 /* `subl %edx, %edx' */
1261 { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } },
1262 /* `xorl %eax, %eax' */
1263 { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } },
1264 /* `xorl %ecx, %ecx' */
1265 { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } },
1266 /* `xorl %edx, %edx' */
1267 { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } },
1272 /* Check whether PC points to a no-op instruction. */
1274 i386_skip_noop (CORE_ADDR pc
)
1279 if (target_read_memory (pc
, &op
, 1))
1285 /* Ignore `nop' instruction. */
1289 if (target_read_memory (pc
, &op
, 1))
1293 /* Ignore no-op instruction `mov %edi, %edi'.
1294 Microsoft system dlls often start with
1295 a `mov %edi,%edi' instruction.
1296 The 5 bytes before the function start are
1297 filled with `nop' instructions.
1298 This pattern can be used for hot-patching:
1299 The `mov %edi, %edi' instruction can be replaced by a
1300 near jump to the location of the 5 `nop' instructions
1301 which can be replaced by a 32-bit jump to anywhere
1302 in the 32-bit address space. */
1304 else if (op
== 0x8b)
1306 if (target_read_memory (pc
+ 1, &op
, 1))
1312 if (target_read_memory (pc
, &op
, 1))
1322 /* Check whether PC points at a code that sets up a new stack frame.
1323 If so, it updates CACHE and returns the address of the first
1324 instruction after the sequence that sets up the frame or LIMIT,
1325 whichever is smaller. If we don't recognize the code, return PC. */
1328 i386_analyze_frame_setup (struct gdbarch
*gdbarch
,
1329 CORE_ADDR pc
, CORE_ADDR limit
,
1330 struct i386_frame_cache
*cache
)
1332 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1333 struct i386_insn
*insn
;
1340 if (target_read_memory (pc
, &op
, 1))
1343 if (op
== 0x55) /* pushl %ebp */
1345 /* Take into account that we've executed the `pushl %ebp' that
1346 starts this instruction sequence. */
1347 cache
->saved_regs
[I386_EBP_REGNUM
] = 0;
1348 cache
->sp_offset
+= 4;
1351 /* If that's all, return now. */
1355 /* Check for some special instructions that might be migrated by
1356 GCC into the prologue and skip them. At this point in the
1357 prologue, code should only touch the scratch registers %eax,
1358 %ecx and %edx, so while the number of posibilities is sheer,
1361 Make sure we only skip these instructions if we later see the
1362 `movl %esp, %ebp' that actually sets up the frame. */
1363 while (pc
+ skip
< limit
)
1365 insn
= i386_match_insn (pc
+ skip
, i386_frame_setup_skip_insns
);
1372 /* If that's all, return now. */
1373 if (limit
<= pc
+ skip
)
1376 if (target_read_memory (pc
+ skip
, &op
, 1))
1379 /* Check for `movl %esp, %ebp' -- can be written in two ways. */
1383 if (read_memory_unsigned_integer (pc
+ skip
+ 1, 1, byte_order
)
1388 if (read_memory_unsigned_integer (pc
+ skip
+ 1, 1, byte_order
)
1396 /* OK, we actually have a frame. We just don't know how large
1397 it is yet. Set its size to zero. We'll adjust it if
1398 necessary. We also now commit to skipping the special
1399 instructions mentioned before. */
1403 /* If that's all, return now. */
1407 /* Check for stack adjustment
1411 NOTE: You can't subtract a 16-bit immediate from a 32-bit
1412 reg, so we don't have to worry about a data16 prefix. */
1413 if (target_read_memory (pc
, &op
, 1))
1417 /* `subl' with 8-bit immediate. */
1418 if (read_memory_unsigned_integer (pc
+ 1, 1, byte_order
) != 0xec)
1419 /* Some instruction starting with 0x83 other than `subl'. */
1422 /* `subl' with signed 8-bit immediate (though it wouldn't
1423 make sense to be negative). */
1424 cache
->locals
= read_memory_integer (pc
+ 2, 1, byte_order
);
1427 else if (op
== 0x81)
1429 /* Maybe it is `subl' with a 32-bit immediate. */
1430 if (read_memory_unsigned_integer (pc
+ 1, 1, byte_order
) != 0xec)
1431 /* Some instruction starting with 0x81 other than `subl'. */
1434 /* It is `subl' with a 32-bit immediate. */
1435 cache
->locals
= read_memory_integer (pc
+ 2, 4, byte_order
);
1440 /* Some instruction other than `subl'. */
1444 else if (op
== 0xc8) /* enter */
1446 cache
->locals
= read_memory_unsigned_integer (pc
+ 1, 2, byte_order
);
1453 /* Check whether PC points at code that saves registers on the stack.
1454 If so, it updates CACHE and returns the address of the first
1455 instruction after the register saves or CURRENT_PC, whichever is
1456 smaller. Otherwise, return PC. */
1459 i386_analyze_register_saves (CORE_ADDR pc
, CORE_ADDR current_pc
,
1460 struct i386_frame_cache
*cache
)
1462 CORE_ADDR offset
= 0;
1466 if (cache
->locals
> 0)
1467 offset
-= cache
->locals
;
1468 for (i
= 0; i
< 8 && pc
< current_pc
; i
++)
1470 if (target_read_memory (pc
, &op
, 1))
1472 if (op
< 0x50 || op
> 0x57)
1476 cache
->saved_regs
[op
- 0x50] = offset
;
1477 cache
->sp_offset
+= 4;
1484 /* Do a full analysis of the prologue at PC and update CACHE
1485 accordingly. Bail out early if CURRENT_PC is reached. Return the
1486 address where the analysis stopped.
1488 We handle these cases:
1490 The startup sequence can be at the start of the function, or the
1491 function can start with a branch to startup code at the end.
1493 %ebp can be set up with either the 'enter' instruction, or "pushl
1494 %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was
1495 once used in the System V compiler).
1497 Local space is allocated just below the saved %ebp by either the
1498 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a
1499 16-bit unsigned argument for space to allocate, and the 'addl'
1500 instruction could have either a signed byte, or 32-bit immediate.
1502 Next, the registers used by this function are pushed. With the
1503 System V compiler they will always be in the order: %edi, %esi,
1504 %ebx (and sometimes a harmless bug causes it to also save but not
1505 restore %eax); however, the code below is willing to see the pushes
1506 in any order, and will handle up to 8 of them.
1508 If the setup sequence is at the end of the function, then the next
1509 instruction will be a branch back to the start. */
1512 i386_analyze_prologue (struct gdbarch
*gdbarch
,
1513 CORE_ADDR pc
, CORE_ADDR current_pc
,
1514 struct i386_frame_cache
*cache
)
1516 pc
= i386_skip_noop (pc
);
1517 pc
= i386_follow_jump (gdbarch
, pc
);
1518 pc
= i386_analyze_struct_return (pc
, current_pc
, cache
);
1519 pc
= i386_skip_probe (pc
);
1520 pc
= i386_analyze_stack_align (pc
, current_pc
, cache
);
1521 pc
= i386_analyze_frame_setup (gdbarch
, pc
, current_pc
, cache
);
1522 return i386_analyze_register_saves (pc
, current_pc
, cache
);
1525 /* Return PC of first real instruction. */
1528 i386_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
1530 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1532 static gdb_byte pic_pat
[6] =
1534 0xe8, 0, 0, 0, 0, /* call 0x0 */
1535 0x5b, /* popl %ebx */
1537 struct i386_frame_cache cache
;
1543 pc
= i386_analyze_prologue (gdbarch
, start_pc
, 0xffffffff, &cache
);
1544 if (cache
.locals
< 0)
1547 /* Found valid frame setup. */
1549 /* The native cc on SVR4 in -K PIC mode inserts the following code
1550 to get the address of the global offset table (GOT) into register
1555 movl %ebx,x(%ebp) (optional)
1558 This code is with the rest of the prologue (at the end of the
1559 function), so we have to skip it to get to the first real
1560 instruction at the start of the function. */
1562 for (i
= 0; i
< 6; i
++)
1564 if (target_read_memory (pc
+ i
, &op
, 1))
1567 if (pic_pat
[i
] != op
)
1574 if (target_read_memory (pc
+ delta
, &op
, 1))
1577 if (op
== 0x89) /* movl %ebx, x(%ebp) */
1579 op
= read_memory_unsigned_integer (pc
+ delta
+ 1, 1, byte_order
);
1581 if (op
== 0x5d) /* One byte offset from %ebp. */
1583 else if (op
== 0x9d) /* Four byte offset from %ebp. */
1585 else /* Unexpected instruction. */
1588 if (target_read_memory (pc
+ delta
, &op
, 1))
1593 if (delta
> 0 && op
== 0x81
1594 && read_memory_unsigned_integer (pc
+ delta
+ 1, 1, byte_order
)
1601 /* If the function starts with a branch (to startup code at the end)
1602 the last instruction should bring us back to the first
1603 instruction of the real code. */
1604 if (i386_follow_jump (gdbarch
, start_pc
) != start_pc
)
1605 pc
= i386_follow_jump (gdbarch
, pc
);
1610 /* Check that the code pointed to by PC corresponds to a call to
1611 __main, skip it if so. Return PC otherwise. */
1614 i386_skip_main_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1616 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1619 if (target_read_memory (pc
, &op
, 1))
1625 if (target_read_memory (pc
+ 1, buf
, sizeof buf
) == 0)
1627 /* Make sure address is computed correctly as a 32bit
1628 integer even if CORE_ADDR is 64 bit wide. */
1629 struct minimal_symbol
*s
;
1630 CORE_ADDR call_dest
;
1632 call_dest
= pc
+ 5 + extract_signed_integer (buf
, 4, byte_order
);
1633 call_dest
= call_dest
& 0xffffffffU
;
1634 s
= lookup_minimal_symbol_by_pc (call_dest
);
1636 && SYMBOL_LINKAGE_NAME (s
) != NULL
1637 && strcmp (SYMBOL_LINKAGE_NAME (s
), "__main") == 0)
1645 /* This function is 64-bit safe. */
1648 i386_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1652 frame_unwind_register (next_frame
, gdbarch_pc_regnum (gdbarch
), buf
);
1653 return extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
1657 /* Normal frames. */
1660 i386_frame_cache_1 (struct frame_info
*this_frame
,
1661 struct i386_frame_cache
*cache
)
1663 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1664 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1668 cache
->pc
= get_frame_func (this_frame
);
1670 /* In principle, for normal frames, %ebp holds the frame pointer,
1671 which holds the base address for the current stack frame.
1672 However, for functions that don't need it, the frame pointer is
1673 optional. For these "frameless" functions the frame pointer is
1674 actually the frame pointer of the calling frame. Signal
1675 trampolines are just a special case of a "frameless" function.
1676 They (usually) share their frame pointer with the frame that was
1677 in progress when the signal occurred. */
1679 get_frame_register (this_frame
, I386_EBP_REGNUM
, buf
);
1680 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
);
1681 if (cache
->base
== 0)
1684 /* For normal frames, %eip is stored at 4(%ebp). */
1685 cache
->saved_regs
[I386_EIP_REGNUM
] = 4;
1688 i386_analyze_prologue (gdbarch
, cache
->pc
, get_frame_pc (this_frame
),
1691 if (cache
->locals
< 0)
1693 /* We didn't find a valid frame, which means that CACHE->base
1694 currently holds the frame pointer for our calling frame. If
1695 we're at the start of a function, or somewhere half-way its
1696 prologue, the function's frame probably hasn't been fully
1697 setup yet. Try to reconstruct the base address for the stack
1698 frame by looking at the stack pointer. For truly "frameless"
1699 functions this might work too. */
1701 if (cache
->saved_sp_reg
!= -1)
1703 /* Saved stack pointer has been saved. */
1704 get_frame_register (this_frame
, cache
->saved_sp_reg
, buf
);
1705 cache
->saved_sp
= extract_unsigned_integer (buf
, 4, byte_order
);
1707 /* We're halfway aligning the stack. */
1708 cache
->base
= ((cache
->saved_sp
- 4) & 0xfffffff0) - 4;
1709 cache
->saved_regs
[I386_EIP_REGNUM
] = cache
->saved_sp
- 4;
1711 /* This will be added back below. */
1712 cache
->saved_regs
[I386_EIP_REGNUM
] -= cache
->base
;
1714 else if (cache
->pc
!= 0
1715 || target_read_memory (get_frame_pc (this_frame
), buf
, 1))
1717 /* We're in a known function, but did not find a frame
1718 setup. Assume that the function does not use %ebp.
1719 Alternatively, we may have jumped to an invalid
1720 address; in that case there is definitely no new
1722 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
1723 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
)
1727 /* We're in an unknown function. We could not find the start
1728 of the function to analyze the prologue; our best option is
1729 to assume a typical frame layout with the caller's %ebp
1731 cache
->saved_regs
[I386_EBP_REGNUM
] = 0;
1734 if (cache
->saved_sp_reg
!= -1)
1736 /* Saved stack pointer has been saved (but the SAVED_SP_REG
1737 register may be unavailable). */
1738 if (cache
->saved_sp
== 0
1739 && frame_register_read (this_frame
, cache
->saved_sp_reg
, buf
))
1740 cache
->saved_sp
= extract_unsigned_integer (buf
, 4, byte_order
);
1742 /* Now that we have the base address for the stack frame we can
1743 calculate the value of %esp in the calling frame. */
1744 else if (cache
->saved_sp
== 0)
1745 cache
->saved_sp
= cache
->base
+ 8;
1747 /* Adjust all the saved registers such that they contain addresses
1748 instead of offsets. */
1749 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
1750 if (cache
->saved_regs
[i
] != -1)
1751 cache
->saved_regs
[i
] += cache
->base
;
1756 static struct i386_frame_cache
*
1757 i386_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1759 volatile struct gdb_exception ex
;
1760 struct i386_frame_cache
*cache
;
1765 cache
= i386_alloc_frame_cache ();
1766 *this_cache
= cache
;
1768 TRY_CATCH (ex
, RETURN_MASK_ERROR
)
1770 i386_frame_cache_1 (this_frame
, cache
);
1772 if (ex
.reason
< 0 && ex
.error
!= NOT_AVAILABLE_ERROR
)
1773 throw_exception (ex
);
1779 i386_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
1780 struct frame_id
*this_id
)
1782 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1784 /* This marks the outermost frame. */
1785 if (cache
->base
== 0)
1788 /* See the end of i386_push_dummy_call. */
1789 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
1792 static enum unwind_stop_reason
1793 i386_frame_unwind_stop_reason (struct frame_info
*this_frame
,
1796 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1799 return UNWIND_UNAVAILABLE
;
1801 /* This marks the outermost frame. */
1802 if (cache
->base
== 0)
1803 return UNWIND_OUTERMOST
;
1805 return UNWIND_NO_REASON
;
1808 static struct value
*
1809 i386_frame_prev_register (struct frame_info
*this_frame
, void **this_cache
,
1812 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1814 gdb_assert (regnum
>= 0);
1816 /* The System V ABI says that:
1818 "The flags register contains the system flags, such as the
1819 direction flag and the carry flag. The direction flag must be
1820 set to the forward (that is, zero) direction before entry and
1821 upon exit from a function. Other user flags have no specified
1822 role in the standard calling sequence and are not preserved."
1824 To guarantee the "upon exit" part of that statement we fake a
1825 saved flags register that has its direction flag cleared.
1827 Note that GCC doesn't seem to rely on the fact that the direction
1828 flag is cleared after a function return; it always explicitly
1829 clears the flag before operations where it matters.
1831 FIXME: kettenis/20030316: I'm not quite sure whether this is the
1832 right thing to do. The way we fake the flags register here makes
1833 it impossible to change it. */
1835 if (regnum
== I386_EFLAGS_REGNUM
)
1839 val
= get_frame_register_unsigned (this_frame
, regnum
);
1841 return frame_unwind_got_constant (this_frame
, regnum
, val
);
1844 if (regnum
== I386_EIP_REGNUM
&& cache
->pc_in_eax
)
1845 return frame_unwind_got_register (this_frame
, regnum
, I386_EAX_REGNUM
);
1847 if (regnum
== I386_ESP_REGNUM
1848 && (cache
->saved_sp
!= 0 || cache
->saved_sp_reg
!= -1))
1850 /* If the SP has been saved, but we don't know where, then this
1851 means that SAVED_SP_REG register was found unavailable back
1852 when we built the cache. */
1853 if (cache
->saved_sp
== 0)
1854 return frame_unwind_got_register (this_frame
, regnum
,
1855 cache
->saved_sp_reg
);
1857 return frame_unwind_got_constant (this_frame
, regnum
,
1861 if (regnum
< I386_NUM_SAVED_REGS
&& cache
->saved_regs
[regnum
] != -1)
1862 return frame_unwind_got_memory (this_frame
, regnum
,
1863 cache
->saved_regs
[regnum
]);
1865 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
1868 static const struct frame_unwind i386_frame_unwind
=
1871 i386_frame_unwind_stop_reason
,
1873 i386_frame_prev_register
,
1875 default_frame_sniffer
1878 /* Normal frames, but in a function epilogue. */
1880 /* The epilogue is defined here as the 'ret' instruction, which will
1881 follow any instruction such as 'leave' or 'pop %ebp' that destroys
1882 the function's stack frame. */
1885 i386_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1888 struct symtab
*symtab
;
1890 symtab
= find_pc_symtab (pc
);
1891 if (symtab
&& symtab
->epilogue_unwind_valid
)
1894 if (target_read_memory (pc
, &insn
, 1))
1895 return 0; /* Can't read memory at pc. */
1897 if (insn
!= 0xc3) /* 'ret' instruction. */
1904 i386_epilogue_frame_sniffer (const struct frame_unwind
*self
,
1905 struct frame_info
*this_frame
,
1906 void **this_prologue_cache
)
1908 if (frame_relative_level (this_frame
) == 0)
1909 return i386_in_function_epilogue_p (get_frame_arch (this_frame
),
1910 get_frame_pc (this_frame
));
1915 static struct i386_frame_cache
*
1916 i386_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1918 volatile struct gdb_exception ex
;
1919 struct i386_frame_cache
*cache
;
1925 cache
= i386_alloc_frame_cache ();
1926 *this_cache
= cache
;
1928 TRY_CATCH (ex
, RETURN_MASK_ERROR
)
1930 cache
->pc
= get_frame_func (this_frame
);
1932 /* At this point the stack looks as if we just entered the
1933 function, with the return address at the top of the
1935 sp
= get_frame_register_unsigned (this_frame
, I386_ESP_REGNUM
);
1936 cache
->base
= sp
+ cache
->sp_offset
;
1937 cache
->saved_sp
= cache
->base
+ 8;
1938 cache
->saved_regs
[I386_EIP_REGNUM
] = cache
->base
+ 4;
1942 if (ex
.reason
< 0 && ex
.error
!= NOT_AVAILABLE_ERROR
)
1943 throw_exception (ex
);
1948 static enum unwind_stop_reason
1949 i386_epilogue_frame_unwind_stop_reason (struct frame_info
*this_frame
,
1952 struct i386_frame_cache
*cache
=
1953 i386_epilogue_frame_cache (this_frame
, this_cache
);
1956 return UNWIND_UNAVAILABLE
;
1958 return UNWIND_NO_REASON
;
1962 i386_epilogue_frame_this_id (struct frame_info
*this_frame
,
1964 struct frame_id
*this_id
)
1966 struct i386_frame_cache
*cache
=
1967 i386_epilogue_frame_cache (this_frame
, this_cache
);
1972 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
1975 static struct value
*
1976 i386_epilogue_frame_prev_register (struct frame_info
*this_frame
,
1977 void **this_cache
, int regnum
)
1979 /* Make sure we've initialized the cache. */
1980 i386_epilogue_frame_cache (this_frame
, this_cache
);
1982 return i386_frame_prev_register (this_frame
, this_cache
, regnum
);
1985 static const struct frame_unwind i386_epilogue_frame_unwind
=
1988 i386_epilogue_frame_unwind_stop_reason
,
1989 i386_epilogue_frame_this_id
,
1990 i386_epilogue_frame_prev_register
,
1992 i386_epilogue_frame_sniffer
1996 /* Stack-based trampolines. */
1998 /* These trampolines are used on cross x86 targets, when taking the
1999 address of a nested function. When executing these trampolines,
2000 no stack frame is set up, so we are in a similar situation as in
2001 epilogues and i386_epilogue_frame_this_id can be re-used. */
2003 /* Static chain passed in register. */
2005 struct i386_insn i386_tramp_chain_in_reg_insns
[] =
2007 /* `movl imm32, %eax' and `movl imm32, %ecx' */
2008 { 5, { 0xb8 }, { 0xfe } },
2011 { 5, { 0xe9 }, { 0xff } },
2016 /* Static chain passed on stack (when regparm=3). */
2018 struct i386_insn i386_tramp_chain_on_stack_insns
[] =
2021 { 5, { 0x68 }, { 0xff } },
2024 { 5, { 0xe9 }, { 0xff } },
2029 /* Return whether PC points inside a stack trampoline. */
2032 i386_in_stack_tramp_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2037 /* A stack trampoline is detected if no name is associated
2038 to the current pc and if it points inside a trampoline
2041 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
2045 if (target_read_memory (pc
, &insn
, 1))
2048 if (!i386_match_insn_block (pc
, i386_tramp_chain_in_reg_insns
)
2049 && !i386_match_insn_block (pc
, i386_tramp_chain_on_stack_insns
))
2056 i386_stack_tramp_frame_sniffer (const struct frame_unwind
*self
,
2057 struct frame_info
*this_frame
,
2060 if (frame_relative_level (this_frame
) == 0)
2061 return i386_in_stack_tramp_p (get_frame_arch (this_frame
),
2062 get_frame_pc (this_frame
));
2067 static const struct frame_unwind i386_stack_tramp_frame_unwind
=
2070 i386_epilogue_frame_unwind_stop_reason
,
2071 i386_epilogue_frame_this_id
,
2072 i386_epilogue_frame_prev_register
,
2074 i386_stack_tramp_frame_sniffer
2078 /* Signal trampolines. */
2080 static struct i386_frame_cache
*
2081 i386_sigtramp_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2083 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2084 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2085 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2086 volatile struct gdb_exception ex
;
2087 struct i386_frame_cache
*cache
;
2094 cache
= i386_alloc_frame_cache ();
2096 TRY_CATCH (ex
, RETURN_MASK_ERROR
)
2098 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
2099 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
) - 4;
2101 addr
= tdep
->sigcontext_addr (this_frame
);
2102 if (tdep
->sc_reg_offset
)
2106 gdb_assert (tdep
->sc_num_regs
<= I386_NUM_SAVED_REGS
);
2108 for (i
= 0; i
< tdep
->sc_num_regs
; i
++)
2109 if (tdep
->sc_reg_offset
[i
] != -1)
2110 cache
->saved_regs
[i
] = addr
+ tdep
->sc_reg_offset
[i
];
2114 cache
->saved_regs
[I386_EIP_REGNUM
] = addr
+ tdep
->sc_pc_offset
;
2115 cache
->saved_regs
[I386_ESP_REGNUM
] = addr
+ tdep
->sc_sp_offset
;
2120 if (ex
.reason
< 0 && ex
.error
!= NOT_AVAILABLE_ERROR
)
2121 throw_exception (ex
);
2123 *this_cache
= cache
;
2127 static enum unwind_stop_reason
2128 i386_sigtramp_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2131 struct i386_frame_cache
*cache
=
2132 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2135 return UNWIND_UNAVAILABLE
;
2137 return UNWIND_NO_REASON
;
2141 i386_sigtramp_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2142 struct frame_id
*this_id
)
2144 struct i386_frame_cache
*cache
=
2145 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2150 /* See the end of i386_push_dummy_call. */
2151 (*this_id
) = frame_id_build (cache
->base
+ 8, get_frame_pc (this_frame
));
2154 static struct value
*
2155 i386_sigtramp_frame_prev_register (struct frame_info
*this_frame
,
2156 void **this_cache
, int regnum
)
2158 /* Make sure we've initialized the cache. */
2159 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2161 return i386_frame_prev_register (this_frame
, this_cache
, regnum
);
2165 i386_sigtramp_frame_sniffer (const struct frame_unwind
*self
,
2166 struct frame_info
*this_frame
,
2167 void **this_prologue_cache
)
2169 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (this_frame
));
2171 /* We shouldn't even bother if we don't have a sigcontext_addr
2173 if (tdep
->sigcontext_addr
== NULL
)
2176 if (tdep
->sigtramp_p
!= NULL
)
2178 if (tdep
->sigtramp_p (this_frame
))
2182 if (tdep
->sigtramp_start
!= 0)
2184 CORE_ADDR pc
= get_frame_pc (this_frame
);
2186 gdb_assert (tdep
->sigtramp_end
!= 0);
2187 if (pc
>= tdep
->sigtramp_start
&& pc
< tdep
->sigtramp_end
)
2194 static const struct frame_unwind i386_sigtramp_frame_unwind
=
2197 i386_sigtramp_frame_unwind_stop_reason
,
2198 i386_sigtramp_frame_this_id
,
2199 i386_sigtramp_frame_prev_register
,
2201 i386_sigtramp_frame_sniffer
2206 i386_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
2208 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
2213 static const struct frame_base i386_frame_base
=
2216 i386_frame_base_address
,
2217 i386_frame_base_address
,
2218 i386_frame_base_address
2221 static struct frame_id
2222 i386_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
2226 fp
= get_frame_register_unsigned (this_frame
, I386_EBP_REGNUM
);
2228 /* See the end of i386_push_dummy_call. */
2229 return frame_id_build (fp
+ 8, get_frame_pc (this_frame
));
2233 /* Figure out where the longjmp will land. Slurp the args out of the
2234 stack. We expect the first arg to be a pointer to the jmp_buf
2235 structure from which we extract the address that we will land at.
2236 This address is copied into PC. This routine returns non-zero on
2240 i386_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
2243 CORE_ADDR sp
, jb_addr
;
2244 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2245 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2246 int jb_pc_offset
= gdbarch_tdep (gdbarch
)->jb_pc_offset
;
2248 /* If JB_PC_OFFSET is -1, we have no way to find out where the
2249 longjmp will land. */
2250 if (jb_pc_offset
== -1)
2253 get_frame_register (frame
, I386_ESP_REGNUM
, buf
);
2254 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
2255 if (target_read_memory (sp
+ 4, buf
, 4))
2258 jb_addr
= extract_unsigned_integer (buf
, 4, byte_order
);
2259 if (target_read_memory (jb_addr
+ jb_pc_offset
, buf
, 4))
2262 *pc
= extract_unsigned_integer (buf
, 4, byte_order
);
2267 /* Check whether TYPE must be 16-byte-aligned when passed as a
2268 function argument. 16-byte vectors, _Decimal128 and structures or
2269 unions containing such types must be 16-byte-aligned; other
2270 arguments are 4-byte-aligned. */
2273 i386_16_byte_align_p (struct type
*type
)
2275 type
= check_typedef (type
);
2276 if ((TYPE_CODE (type
) == TYPE_CODE_DECFLOAT
2277 || (TYPE_CODE (type
) == TYPE_CODE_ARRAY
&& TYPE_VECTOR (type
)))
2278 && TYPE_LENGTH (type
) == 16)
2280 if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
2281 return i386_16_byte_align_p (TYPE_TARGET_TYPE (type
));
2282 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
2283 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
2286 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
2288 if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type
, i
)))
2296 i386_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2297 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
2298 struct value
**args
, CORE_ADDR sp
, int struct_return
,
2299 CORE_ADDR struct_addr
)
2301 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2307 /* Determine the total space required for arguments and struct
2308 return address in a first pass (allowing for 16-byte-aligned
2309 arguments), then push arguments in a second pass. */
2311 for (write_pass
= 0; write_pass
< 2; write_pass
++)
2313 int args_space_used
= 0;
2314 int have_16_byte_aligned_arg
= 0;
2320 /* Push value address. */
2321 store_unsigned_integer (buf
, 4, byte_order
, struct_addr
);
2322 write_memory (sp
, buf
, 4);
2323 args_space_used
+= 4;
2329 for (i
= 0; i
< nargs
; i
++)
2331 int len
= TYPE_LENGTH (value_enclosing_type (args
[i
]));
2335 if (i386_16_byte_align_p (value_enclosing_type (args
[i
])))
2336 args_space_used
= align_up (args_space_used
, 16);
2338 write_memory (sp
+ args_space_used
,
2339 value_contents_all (args
[i
]), len
);
2340 /* The System V ABI says that:
2342 "An argument's size is increased, if necessary, to make it a
2343 multiple of [32-bit] words. This may require tail padding,
2344 depending on the size of the argument."
2346 This makes sure the stack stays word-aligned. */
2347 args_space_used
+= align_up (len
, 4);
2351 if (i386_16_byte_align_p (value_enclosing_type (args
[i
])))
2353 args_space
= align_up (args_space
, 16);
2354 have_16_byte_aligned_arg
= 1;
2356 args_space
+= align_up (len
, 4);
2362 if (have_16_byte_aligned_arg
)
2363 args_space
= align_up (args_space
, 16);
2368 /* Store return address. */
2370 store_unsigned_integer (buf
, 4, byte_order
, bp_addr
);
2371 write_memory (sp
, buf
, 4);
2373 /* Finally, update the stack pointer... */
2374 store_unsigned_integer (buf
, 4, byte_order
, sp
);
2375 regcache_cooked_write (regcache
, I386_ESP_REGNUM
, buf
);
2377 /* ...and fake a frame pointer. */
2378 regcache_cooked_write (regcache
, I386_EBP_REGNUM
, buf
);
2380 /* MarkK wrote: This "+ 8" is all over the place:
2381 (i386_frame_this_id, i386_sigtramp_frame_this_id,
2382 i386_dummy_id). It's there, since all frame unwinders for
2383 a given target have to agree (within a certain margin) on the
2384 definition of the stack address of a frame. Otherwise frame id
2385 comparison might not work correctly. Since DWARF2/GCC uses the
2386 stack address *before* the function call as a frame's CFA. On
2387 the i386, when %ebp is used as a frame pointer, the offset
2388 between the contents %ebp and the CFA as defined by GCC. */
2392 /* These registers are used for returning integers (and on some
2393 targets also for returning `struct' and `union' values when their
2394 size and alignment match an integer type). */
2395 #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */
2396 #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */
2398 /* Read, for architecture GDBARCH, a function return value of TYPE
2399 from REGCACHE, and copy that into VALBUF. */
2402 i386_extract_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
2403 struct regcache
*regcache
, gdb_byte
*valbuf
)
2405 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2406 int len
= TYPE_LENGTH (type
);
2407 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
2409 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2411 if (tdep
->st0_regnum
< 0)
2413 warning (_("Cannot find floating-point return value."));
2414 memset (valbuf
, 0, len
);
2418 /* Floating-point return values can be found in %st(0). Convert
2419 its contents to the desired type. This is probably not
2420 exactly how it would happen on the target itself, but it is
2421 the best we can do. */
2422 regcache_raw_read (regcache
, I386_ST0_REGNUM
, buf
);
2423 convert_typed_floating (buf
, i387_ext_type (gdbarch
), valbuf
, type
);
2427 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
2428 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
2430 if (len
<= low_size
)
2432 regcache_raw_read (regcache
, LOW_RETURN_REGNUM
, buf
);
2433 memcpy (valbuf
, buf
, len
);
2435 else if (len
<= (low_size
+ high_size
))
2437 regcache_raw_read (regcache
, LOW_RETURN_REGNUM
, buf
);
2438 memcpy (valbuf
, buf
, low_size
);
2439 regcache_raw_read (regcache
, HIGH_RETURN_REGNUM
, buf
);
2440 memcpy (valbuf
+ low_size
, buf
, len
- low_size
);
2443 internal_error (__FILE__
, __LINE__
,
2444 _("Cannot extract return value of %d bytes long."),
2449 /* Write, for architecture GDBARCH, a function return value of TYPE
2450 from VALBUF into REGCACHE. */
2453 i386_store_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
2454 struct regcache
*regcache
, const gdb_byte
*valbuf
)
2456 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2457 int len
= TYPE_LENGTH (type
);
2459 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2462 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
2464 if (tdep
->st0_regnum
< 0)
2466 warning (_("Cannot set floating-point return value."));
2470 /* Returning floating-point values is a bit tricky. Apart from
2471 storing the return value in %st(0), we have to simulate the
2472 state of the FPU at function return point. */
2474 /* Convert the value found in VALBUF to the extended
2475 floating-point format used by the FPU. This is probably
2476 not exactly how it would happen on the target itself, but
2477 it is the best we can do. */
2478 convert_typed_floating (valbuf
, type
, buf
, i387_ext_type (gdbarch
));
2479 regcache_raw_write (regcache
, I386_ST0_REGNUM
, buf
);
2481 /* Set the top of the floating-point register stack to 7. The
2482 actual value doesn't really matter, but 7 is what a normal
2483 function return would end up with if the program started out
2484 with a freshly initialized FPU. */
2485 regcache_raw_read_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), &fstat
);
2487 regcache_raw_write_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), fstat
);
2489 /* Mark %st(1) through %st(7) as empty. Since we set the top of
2490 the floating-point register stack to 7, the appropriate value
2491 for the tag word is 0x3fff. */
2492 regcache_raw_write_unsigned (regcache
, I387_FTAG_REGNUM (tdep
), 0x3fff);
2496 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
2497 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
2499 if (len
<= low_size
)
2500 regcache_raw_write_part (regcache
, LOW_RETURN_REGNUM
, 0, len
, valbuf
);
2501 else if (len
<= (low_size
+ high_size
))
2503 regcache_raw_write (regcache
, LOW_RETURN_REGNUM
, valbuf
);
2504 regcache_raw_write_part (regcache
, HIGH_RETURN_REGNUM
, 0,
2505 len
- low_size
, valbuf
+ low_size
);
2508 internal_error (__FILE__
, __LINE__
,
2509 _("Cannot store return value of %d bytes long."), len
);
2514 /* This is the variable that is set with "set struct-convention", and
2515 its legitimate values. */
2516 static const char default_struct_convention
[] = "default";
2517 static const char pcc_struct_convention
[] = "pcc";
2518 static const char reg_struct_convention
[] = "reg";
2519 static const char *valid_conventions
[] =
2521 default_struct_convention
,
2522 pcc_struct_convention
,
2523 reg_struct_convention
,
2526 static const char *struct_convention
= default_struct_convention
;
2528 /* Return non-zero if TYPE, which is assumed to be a structure,
2529 a union type, or an array type, should be returned in registers
2530 for architecture GDBARCH. */
2533 i386_reg_struct_return_p (struct gdbarch
*gdbarch
, struct type
*type
)
2535 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2536 enum type_code code
= TYPE_CODE (type
);
2537 int len
= TYPE_LENGTH (type
);
2539 gdb_assert (code
== TYPE_CODE_STRUCT
2540 || code
== TYPE_CODE_UNION
2541 || code
== TYPE_CODE_ARRAY
);
2543 if (struct_convention
== pcc_struct_convention
2544 || (struct_convention
== default_struct_convention
2545 && tdep
->struct_return
== pcc_struct_return
))
2548 /* Structures consisting of a single `float', `double' or 'long
2549 double' member are returned in %st(0). */
2550 if (code
== TYPE_CODE_STRUCT
&& TYPE_NFIELDS (type
) == 1)
2552 type
= check_typedef (TYPE_FIELD_TYPE (type
, 0));
2553 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2554 return (len
== 4 || len
== 8 || len
== 12);
2557 return (len
== 1 || len
== 2 || len
== 4 || len
== 8);
2560 /* Determine, for architecture GDBARCH, how a return value of TYPE
2561 should be returned. If it is supposed to be returned in registers,
2562 and READBUF is non-zero, read the appropriate value from REGCACHE,
2563 and copy it into READBUF. If WRITEBUF is non-zero, write the value
2564 from WRITEBUF into REGCACHE. */
2566 static enum return_value_convention
2567 i386_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
2568 struct type
*type
, struct regcache
*regcache
,
2569 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2571 enum type_code code
= TYPE_CODE (type
);
2573 if (((code
== TYPE_CODE_STRUCT
2574 || code
== TYPE_CODE_UNION
2575 || code
== TYPE_CODE_ARRAY
)
2576 && !i386_reg_struct_return_p (gdbarch
, type
))
2577 /* 128-bit decimal float uses the struct return convention. */
2578 || (code
== TYPE_CODE_DECFLOAT
&& TYPE_LENGTH (type
) == 16))
2580 /* The System V ABI says that:
2582 "A function that returns a structure or union also sets %eax
2583 to the value of the original address of the caller's area
2584 before it returns. Thus when the caller receives control
2585 again, the address of the returned object resides in register
2586 %eax and can be used to access the object."
2588 So the ABI guarantees that we can always find the return
2589 value just after the function has returned. */
2591 /* Note that the ABI doesn't mention functions returning arrays,
2592 which is something possible in certain languages such as Ada.
2593 In this case, the value is returned as if it was wrapped in
2594 a record, so the convention applied to records also applies
2601 regcache_raw_read_unsigned (regcache
, I386_EAX_REGNUM
, &addr
);
2602 read_memory (addr
, readbuf
, TYPE_LENGTH (type
));
2605 return RETURN_VALUE_ABI_RETURNS_ADDRESS
;
2608 /* This special case is for structures consisting of a single
2609 `float', `double' or 'long double' member. These structures are
2610 returned in %st(0). For these structures, we call ourselves
2611 recursively, changing TYPE into the type of the first member of
2612 the structure. Since that should work for all structures that
2613 have only one member, we don't bother to check the member's type
2615 if (code
== TYPE_CODE_STRUCT
&& TYPE_NFIELDS (type
) == 1)
2617 type
= check_typedef (TYPE_FIELD_TYPE (type
, 0));
2618 return i386_return_value (gdbarch
, func_type
, type
, regcache
,
2623 i386_extract_return_value (gdbarch
, type
, regcache
, readbuf
);
2625 i386_store_return_value (gdbarch
, type
, regcache
, writebuf
);
2627 return RETURN_VALUE_REGISTER_CONVENTION
;
2632 i387_ext_type (struct gdbarch
*gdbarch
)
2634 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2636 if (!tdep
->i387_ext_type
)
2638 tdep
->i387_ext_type
= tdesc_find_type (gdbarch
, "i387_ext");
2639 gdb_assert (tdep
->i387_ext_type
!= NULL
);
2642 return tdep
->i387_ext_type
;
2645 /* Construct vector type for pseudo YMM registers. We can't use
2646 tdesc_find_type since YMM isn't described in target description. */
2648 static struct type
*
2649 i386_ymm_type (struct gdbarch
*gdbarch
)
2651 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2653 if (!tdep
->i386_ymm_type
)
2655 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2657 /* The type we're building is this: */
2659 union __gdb_builtin_type_vec256i
2661 int128_t uint128
[2];
2662 int64_t v2_int64
[4];
2663 int32_t v4_int32
[8];
2664 int16_t v8_int16
[16];
2665 int8_t v16_int8
[32];
2666 double v2_double
[4];
2673 t
= arch_composite_type (gdbarch
,
2674 "__gdb_builtin_type_vec256i", TYPE_CODE_UNION
);
2675 append_composite_type_field (t
, "v8_float",
2676 init_vector_type (bt
->builtin_float
, 8));
2677 append_composite_type_field (t
, "v4_double",
2678 init_vector_type (bt
->builtin_double
, 4));
2679 append_composite_type_field (t
, "v32_int8",
2680 init_vector_type (bt
->builtin_int8
, 32));
2681 append_composite_type_field (t
, "v16_int16",
2682 init_vector_type (bt
->builtin_int16
, 16));
2683 append_composite_type_field (t
, "v8_int32",
2684 init_vector_type (bt
->builtin_int32
, 8));
2685 append_composite_type_field (t
, "v4_int64",
2686 init_vector_type (bt
->builtin_int64
, 4));
2687 append_composite_type_field (t
, "v2_int128",
2688 init_vector_type (bt
->builtin_int128
, 2));
2690 TYPE_VECTOR (t
) = 1;
2691 TYPE_NAME (t
) = "builtin_type_vec256i";
2692 tdep
->i386_ymm_type
= t
;
2695 return tdep
->i386_ymm_type
;
2698 /* Construct vector type for MMX registers. */
2699 static struct type
*
2700 i386_mmx_type (struct gdbarch
*gdbarch
)
2702 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2704 if (!tdep
->i386_mmx_type
)
2706 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2708 /* The type we're building is this: */
2710 union __gdb_builtin_type_vec64i
2713 int32_t v2_int32
[2];
2714 int16_t v4_int16
[4];
2721 t
= arch_composite_type (gdbarch
,
2722 "__gdb_builtin_type_vec64i", TYPE_CODE_UNION
);
2724 append_composite_type_field (t
, "uint64", bt
->builtin_int64
);
2725 append_composite_type_field (t
, "v2_int32",
2726 init_vector_type (bt
->builtin_int32
, 2));
2727 append_composite_type_field (t
, "v4_int16",
2728 init_vector_type (bt
->builtin_int16
, 4));
2729 append_composite_type_field (t
, "v8_int8",
2730 init_vector_type (bt
->builtin_int8
, 8));
2732 TYPE_VECTOR (t
) = 1;
2733 TYPE_NAME (t
) = "builtin_type_vec64i";
2734 tdep
->i386_mmx_type
= t
;
2737 return tdep
->i386_mmx_type
;
2740 /* Return the GDB type object for the "standard" data type of data in
2743 static struct type
*
2744 i386_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
2746 if (i386_mmx_regnum_p (gdbarch
, regnum
))
2747 return i386_mmx_type (gdbarch
);
2748 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
2749 return i386_ymm_type (gdbarch
);
2752 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2753 if (i386_byte_regnum_p (gdbarch
, regnum
))
2754 return bt
->builtin_int8
;
2755 else if (i386_word_regnum_p (gdbarch
, regnum
))
2756 return bt
->builtin_int16
;
2757 else if (i386_dword_regnum_p (gdbarch
, regnum
))
2758 return bt
->builtin_int32
;
2761 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
2764 /* Map a cooked register onto a raw register or memory. For the i386,
2765 the MMX registers need to be mapped onto floating point registers. */
2768 i386_mmx_regnum_to_fp_regnum (struct regcache
*regcache
, int regnum
)
2770 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_regcache_arch (regcache
));
2775 mmxreg
= regnum
- tdep
->mm0_regnum
;
2776 regcache_raw_read_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), &fstat
);
2777 tos
= (fstat
>> 11) & 0x7;
2778 fpreg
= (mmxreg
+ tos
) % 8;
2780 return (I387_ST0_REGNUM (tdep
) + fpreg
);
2783 enum register_status
2784 i386_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2785 int regnum
, gdb_byte
*buf
)
2787 gdb_byte raw_buf
[MAX_REGISTER_SIZE
];
2788 enum register_status status
;
2790 if (i386_mmx_regnum_p (gdbarch
, regnum
))
2792 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
2794 /* Extract (always little endian). */
2795 status
= regcache_raw_read (regcache
, fpnum
, raw_buf
);
2796 if (status
!= REG_VALID
)
2798 memcpy (buf
, raw_buf
, register_size (gdbarch
, regnum
));
2802 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2804 if (i386_ymm_regnum_p (gdbarch
, regnum
))
2806 regnum
-= tdep
->ymm0_regnum
;
2808 /* Extract (always little endian). Read lower 128bits. */
2809 status
= regcache_raw_read (regcache
,
2810 I387_XMM0_REGNUM (tdep
) + regnum
,
2812 if (status
!= REG_VALID
)
2814 memcpy (buf
, raw_buf
, 16);
2815 /* Read upper 128bits. */
2816 status
= regcache_raw_read (regcache
,
2817 tdep
->ymm0h_regnum
+ regnum
,
2819 if (status
!= REG_VALID
)
2821 memcpy (buf
+ 16, raw_buf
, 16);
2823 else if (i386_word_regnum_p (gdbarch
, regnum
))
2825 int gpnum
= regnum
- tdep
->ax_regnum
;
2827 /* Extract (always little endian). */
2828 status
= regcache_raw_read (regcache
, gpnum
, raw_buf
);
2829 if (status
!= REG_VALID
)
2831 memcpy (buf
, raw_buf
, 2);
2833 else if (i386_byte_regnum_p (gdbarch
, regnum
))
2835 /* Check byte pseudo registers last since this function will
2836 be called from amd64_pseudo_register_read, which handles
2837 byte pseudo registers differently. */
2838 int gpnum
= regnum
- tdep
->al_regnum
;
2840 /* Extract (always little endian). We read both lower and
2842 status
= regcache_raw_read (regcache
, gpnum
% 4, raw_buf
);
2843 if (status
!= REG_VALID
)
2846 memcpy (buf
, raw_buf
+ 1, 1);
2848 memcpy (buf
, raw_buf
, 1);
2851 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
2858 i386_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2859 int regnum
, const gdb_byte
*buf
)
2861 gdb_byte raw_buf
[MAX_REGISTER_SIZE
];
2863 if (i386_mmx_regnum_p (gdbarch
, regnum
))
2865 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
2868 regcache_raw_read (regcache
, fpnum
, raw_buf
);
2869 /* ... Modify ... (always little endian). */
2870 memcpy (raw_buf
, buf
, register_size (gdbarch
, regnum
));
2872 regcache_raw_write (regcache
, fpnum
, raw_buf
);
2876 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2878 if (i386_ymm_regnum_p (gdbarch
, regnum
))
2880 regnum
-= tdep
->ymm0_regnum
;
2882 /* ... Write lower 128bits. */
2883 regcache_raw_write (regcache
,
2884 I387_XMM0_REGNUM (tdep
) + regnum
,
2886 /* ... Write upper 128bits. */
2887 regcache_raw_write (regcache
,
2888 tdep
->ymm0h_regnum
+ regnum
,
2891 else if (i386_word_regnum_p (gdbarch
, regnum
))
2893 int gpnum
= regnum
- tdep
->ax_regnum
;
2896 regcache_raw_read (regcache
, gpnum
, raw_buf
);
2897 /* ... Modify ... (always little endian). */
2898 memcpy (raw_buf
, buf
, 2);
2900 regcache_raw_write (regcache
, gpnum
, raw_buf
);
2902 else if (i386_byte_regnum_p (gdbarch
, regnum
))
2904 /* Check byte pseudo registers last since this function will
2905 be called from amd64_pseudo_register_read, which handles
2906 byte pseudo registers differently. */
2907 int gpnum
= regnum
- tdep
->al_regnum
;
2909 /* Read ... We read both lower and upper registers. */
2910 regcache_raw_read (regcache
, gpnum
% 4, raw_buf
);
2911 /* ... Modify ... (always little endian). */
2913 memcpy (raw_buf
+ 1, buf
, 1);
2915 memcpy (raw_buf
, buf
, 1);
2917 regcache_raw_write (regcache
, gpnum
% 4, raw_buf
);
2920 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
2925 /* Return the register number of the register allocated by GCC after
2926 REGNUM, or -1 if there is no such register. */
2929 i386_next_regnum (int regnum
)
2931 /* GCC allocates the registers in the order:
2933 %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ...
2935 Since storing a variable in %esp doesn't make any sense we return
2936 -1 for %ebp and for %esp itself. */
2937 static int next_regnum
[] =
2939 I386_EDX_REGNUM
, /* Slot for %eax. */
2940 I386_EBX_REGNUM
, /* Slot for %ecx. */
2941 I386_ECX_REGNUM
, /* Slot for %edx. */
2942 I386_ESI_REGNUM
, /* Slot for %ebx. */
2943 -1, -1, /* Slots for %esp and %ebp. */
2944 I386_EDI_REGNUM
, /* Slot for %esi. */
2945 I386_EBP_REGNUM
/* Slot for %edi. */
2948 if (regnum
>= 0 && regnum
< sizeof (next_regnum
) / sizeof (next_regnum
[0]))
2949 return next_regnum
[regnum
];
2954 /* Return nonzero if a value of type TYPE stored in register REGNUM
2955 needs any special handling. */
2958 i386_convert_register_p (struct gdbarch
*gdbarch
,
2959 int regnum
, struct type
*type
)
2961 int len
= TYPE_LENGTH (type
);
2963 /* Values may be spread across multiple registers. Most debugging
2964 formats aren't expressive enough to specify the locations, so
2965 some heuristics is involved. Right now we only handle types that
2966 have a length that is a multiple of the word size, since GCC
2967 doesn't seem to put any other types into registers. */
2968 if (len
> 4 && len
% 4 == 0)
2970 int last_regnum
= regnum
;
2974 last_regnum
= i386_next_regnum (last_regnum
);
2978 if (last_regnum
!= -1)
2982 return i387_convert_register_p (gdbarch
, regnum
, type
);
2985 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
2986 return its contents in TO. */
2989 i386_register_to_value (struct frame_info
*frame
, int regnum
,
2990 struct type
*type
, gdb_byte
*to
,
2991 int *optimizedp
, int *unavailablep
)
2993 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2994 int len
= TYPE_LENGTH (type
);
2996 if (i386_fp_regnum_p (gdbarch
, regnum
))
2997 return i387_register_to_value (frame
, regnum
, type
, to
,
2998 optimizedp
, unavailablep
);
3000 /* Read a value spread across multiple registers. */
3002 gdb_assert (len
> 4 && len
% 4 == 0);
3006 gdb_assert (regnum
!= -1);
3007 gdb_assert (register_size (gdbarch
, regnum
) == 4);
3009 if (!get_frame_register_bytes (frame
, regnum
, 0,
3010 register_size (gdbarch
, regnum
),
3011 to
, optimizedp
, unavailablep
))
3014 regnum
= i386_next_regnum (regnum
);
3019 *optimizedp
= *unavailablep
= 0;
3023 /* Write the contents FROM of a value of type TYPE into register
3024 REGNUM in frame FRAME. */
3027 i386_value_to_register (struct frame_info
*frame
, int regnum
,
3028 struct type
*type
, const gdb_byte
*from
)
3030 int len
= TYPE_LENGTH (type
);
3032 if (i386_fp_regnum_p (get_frame_arch (frame
), regnum
))
3034 i387_value_to_register (frame
, regnum
, type
, from
);
3038 /* Write a value spread across multiple registers. */
3040 gdb_assert (len
> 4 && len
% 4 == 0);
3044 gdb_assert (regnum
!= -1);
3045 gdb_assert (register_size (get_frame_arch (frame
), regnum
) == 4);
3047 put_frame_register (frame
, regnum
, from
);
3048 regnum
= i386_next_regnum (regnum
);
3054 /* Supply register REGNUM from the buffer specified by GREGS and LEN
3055 in the general-purpose register set REGSET to register cache
3056 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3059 i386_supply_gregset (const struct regset
*regset
, struct regcache
*regcache
,
3060 int regnum
, const void *gregs
, size_t len
)
3062 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
3063 const gdb_byte
*regs
= gregs
;
3066 gdb_assert (len
== tdep
->sizeof_gregset
);
3068 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
3070 if ((regnum
== i
|| regnum
== -1)
3071 && tdep
->gregset_reg_offset
[i
] != -1)
3072 regcache_raw_supply (regcache
, i
, regs
+ tdep
->gregset_reg_offset
[i
]);
3076 /* Collect register REGNUM from the register cache REGCACHE and store
3077 it in the buffer specified by GREGS and LEN as described by the
3078 general-purpose register set REGSET. If REGNUM is -1, do this for
3079 all registers in REGSET. */
3082 i386_collect_gregset (const struct regset
*regset
,
3083 const struct regcache
*regcache
,
3084 int regnum
, void *gregs
, size_t len
)
3086 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
3087 gdb_byte
*regs
= gregs
;
3090 gdb_assert (len
== tdep
->sizeof_gregset
);
3092 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
3094 if ((regnum
== i
|| regnum
== -1)
3095 && tdep
->gregset_reg_offset
[i
] != -1)
3096 regcache_raw_collect (regcache
, i
, regs
+ tdep
->gregset_reg_offset
[i
]);
3100 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
3101 in the floating-point register set REGSET to register cache
3102 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3105 i386_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
3106 int regnum
, const void *fpregs
, size_t len
)
3108 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
3110 if (len
== I387_SIZEOF_FXSAVE
)
3112 i387_supply_fxsave (regcache
, regnum
, fpregs
);
3116 gdb_assert (len
== tdep
->sizeof_fpregset
);
3117 i387_supply_fsave (regcache
, regnum
, fpregs
);
3120 /* Collect register REGNUM from the register cache REGCACHE and store
3121 it in the buffer specified by FPREGS and LEN as described by the
3122 floating-point register set REGSET. If REGNUM is -1, do this for
3123 all registers in REGSET. */
3126 i386_collect_fpregset (const struct regset
*regset
,
3127 const struct regcache
*regcache
,
3128 int regnum
, void *fpregs
, size_t len
)
3130 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
3132 if (len
== I387_SIZEOF_FXSAVE
)
3134 i387_collect_fxsave (regcache
, regnum
, fpregs
);
3138 gdb_assert (len
== tdep
->sizeof_fpregset
);
3139 i387_collect_fsave (regcache
, regnum
, fpregs
);
3142 /* Similar to i386_supply_fpregset, but use XSAVE extended state. */
3145 i386_supply_xstateregset (const struct regset
*regset
,
3146 struct regcache
*regcache
, int regnum
,
3147 const void *xstateregs
, size_t len
)
3149 i387_supply_xsave (regcache
, regnum
, xstateregs
);
3152 /* Similar to i386_collect_fpregset , but use XSAVE extended state. */
3155 i386_collect_xstateregset (const struct regset
*regset
,
3156 const struct regcache
*regcache
,
3157 int regnum
, void *xstateregs
, size_t len
)
3159 i387_collect_xsave (regcache
, regnum
, xstateregs
, 1);
3162 /* Return the appropriate register set for the core section identified
3163 by SECT_NAME and SECT_SIZE. */
3165 const struct regset
*
3166 i386_regset_from_core_section (struct gdbarch
*gdbarch
,
3167 const char *sect_name
, size_t sect_size
)
3169 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3171 if (strcmp (sect_name
, ".reg") == 0 && sect_size
== tdep
->sizeof_gregset
)
3173 if (tdep
->gregset
== NULL
)
3174 tdep
->gregset
= regset_alloc (gdbarch
, i386_supply_gregset
,
3175 i386_collect_gregset
);
3176 return tdep
->gregset
;
3179 if ((strcmp (sect_name
, ".reg2") == 0 && sect_size
== tdep
->sizeof_fpregset
)
3180 || (strcmp (sect_name
, ".reg-xfp") == 0
3181 && sect_size
== I387_SIZEOF_FXSAVE
))
3183 if (tdep
->fpregset
== NULL
)
3184 tdep
->fpregset
= regset_alloc (gdbarch
, i386_supply_fpregset
,
3185 i386_collect_fpregset
);
3186 return tdep
->fpregset
;
3189 if (strcmp (sect_name
, ".reg-xstate") == 0)
3191 if (tdep
->xstateregset
== NULL
)
3192 tdep
->xstateregset
= regset_alloc (gdbarch
,
3193 i386_supply_xstateregset
,
3194 i386_collect_xstateregset
);
3196 return tdep
->xstateregset
;
3203 /* Stuff for WIN32 PE style DLL's but is pretty generic really. */
3206 i386_pe_skip_trampoline_code (struct frame_info
*frame
,
3207 CORE_ADDR pc
, char *name
)
3209 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3210 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3213 if (pc
&& read_memory_unsigned_integer (pc
, 2, byte_order
) == 0x25ff)
3215 unsigned long indirect
=
3216 read_memory_unsigned_integer (pc
+ 2, 4, byte_order
);
3217 struct minimal_symbol
*indsym
=
3218 indirect
? lookup_minimal_symbol_by_pc (indirect
) : 0;
3219 char *symname
= indsym
? SYMBOL_LINKAGE_NAME (indsym
) : 0;
3223 if (strncmp (symname
, "__imp_", 6) == 0
3224 || strncmp (symname
, "_imp_", 5) == 0)
3226 read_memory_unsigned_integer (indirect
, 4, byte_order
);
3229 return 0; /* Not a trampoline. */
3233 /* Return whether the THIS_FRAME corresponds to a sigtramp
3237 i386_sigtramp_p (struct frame_info
*this_frame
)
3239 CORE_ADDR pc
= get_frame_pc (this_frame
);
3242 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
3243 return (name
&& strcmp ("_sigtramp", name
) == 0);
3247 /* We have two flavours of disassembly. The machinery on this page
3248 deals with switching between those. */
3251 i386_print_insn (bfd_vma pc
, struct disassemble_info
*info
)
3253 gdb_assert (disassembly_flavor
== att_flavor
3254 || disassembly_flavor
== intel_flavor
);
3256 /* FIXME: kettenis/20020915: Until disassembler_options is properly
3257 constified, cast to prevent a compiler warning. */
3258 info
->disassembler_options
= (char *) disassembly_flavor
;
3260 return print_insn_i386 (pc
, info
);
3264 /* There are a few i386 architecture variants that differ only
3265 slightly from the generic i386 target. For now, we don't give them
3266 their own source file, but include them here. As a consequence,
3267 they'll always be included. */
3269 /* System V Release 4 (SVR4). */
3271 /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp
3275 i386_svr4_sigtramp_p (struct frame_info
*this_frame
)
3277 CORE_ADDR pc
= get_frame_pc (this_frame
);
3280 /* UnixWare uses _sigacthandler. The origin of the other symbols is
3281 currently unknown. */
3282 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
3283 return (name
&& (strcmp ("_sigreturn", name
) == 0
3284 || strcmp ("_sigacthandler", name
) == 0
3285 || strcmp ("sigvechandler", name
) == 0));
3288 /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the
3289 address of the associated sigcontext (ucontext) structure. */
3292 i386_svr4_sigcontext_addr (struct frame_info
*this_frame
)
3294 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3295 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3299 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
3300 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
3302 return read_memory_unsigned_integer (sp
+ 8, 4, byte_order
);
3309 i386_elf_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
3311 /* We typically use stabs-in-ELF with the SVR4 register numbering. */
3312 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
3315 /* System V Release 4 (SVR4). */
3318 i386_svr4_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
3320 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3322 /* System V Release 4 uses ELF. */
3323 i386_elf_init_abi (info
, gdbarch
);
3325 /* System V Release 4 has shared libraries. */
3326 set_gdbarch_skip_trampoline_code (gdbarch
, find_solib_trampoline_target
);
3328 tdep
->sigtramp_p
= i386_svr4_sigtramp_p
;
3329 tdep
->sigcontext_addr
= i386_svr4_sigcontext_addr
;
3330 tdep
->sc_pc_offset
= 36 + 14 * 4;
3331 tdep
->sc_sp_offset
= 36 + 17 * 4;
3333 tdep
->jb_pc_offset
= 20;
3339 i386_go32_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
3341 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3343 /* DJGPP doesn't have any special frames for signal handlers. */
3344 tdep
->sigtramp_p
= NULL
;
3346 tdep
->jb_pc_offset
= 36;
3348 /* DJGPP does not support the SSE registers. */
3349 if (! tdesc_has_registers (info
.target_desc
))
3350 tdep
->tdesc
= tdesc_i386_mmx
;
3352 /* Native compiler is GCC, which uses the SVR4 register numbering
3353 even in COFF and STABS. See the comment in i386_gdbarch_init,
3354 before the calls to set_gdbarch_stab_reg_to_regnum and
3355 set_gdbarch_sdb_reg_to_regnum. */
3356 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
3357 set_gdbarch_sdb_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
3359 set_gdbarch_has_dos_based_file_system (gdbarch
, 1);
3363 /* i386 register groups. In addition to the normal groups, add "mmx"
3366 static struct reggroup
*i386_sse_reggroup
;
3367 static struct reggroup
*i386_mmx_reggroup
;
3370 i386_init_reggroups (void)
3372 i386_sse_reggroup
= reggroup_new ("sse", USER_REGGROUP
);
3373 i386_mmx_reggroup
= reggroup_new ("mmx", USER_REGGROUP
);
3377 i386_add_reggroups (struct gdbarch
*gdbarch
)
3379 reggroup_add (gdbarch
, i386_sse_reggroup
);
3380 reggroup_add (gdbarch
, i386_mmx_reggroup
);
3381 reggroup_add (gdbarch
, general_reggroup
);
3382 reggroup_add (gdbarch
, float_reggroup
);
3383 reggroup_add (gdbarch
, all_reggroup
);
3384 reggroup_add (gdbarch
, save_reggroup
);
3385 reggroup_add (gdbarch
, restore_reggroup
);
3386 reggroup_add (gdbarch
, vector_reggroup
);
3387 reggroup_add (gdbarch
, system_reggroup
);
3391 i386_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
3392 struct reggroup
*group
)
3394 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3395 int fp_regnum_p
, mmx_regnum_p
, xmm_regnum_p
, mxcsr_regnum_p
,
3396 ymm_regnum_p
, ymmh_regnum_p
;
3398 /* Don't include pseudo registers, except for MMX, in any register
3400 if (i386_byte_regnum_p (gdbarch
, regnum
))
3403 if (i386_word_regnum_p (gdbarch
, regnum
))
3406 if (i386_dword_regnum_p (gdbarch
, regnum
))
3409 mmx_regnum_p
= i386_mmx_regnum_p (gdbarch
, regnum
);
3410 if (group
== i386_mmx_reggroup
)
3411 return mmx_regnum_p
;
3413 xmm_regnum_p
= i386_xmm_regnum_p (gdbarch
, regnum
);
3414 mxcsr_regnum_p
= i386_mxcsr_regnum_p (gdbarch
, regnum
);
3415 if (group
== i386_sse_reggroup
)
3416 return xmm_regnum_p
|| mxcsr_regnum_p
;
3418 ymm_regnum_p
= i386_ymm_regnum_p (gdbarch
, regnum
);
3419 if (group
== vector_reggroup
)
3420 return (mmx_regnum_p
3424 && ((tdep
->xcr0
& I386_XSTATE_AVX_MASK
)
3425 == I386_XSTATE_SSE_MASK
)));
3427 fp_regnum_p
= (i386_fp_regnum_p (gdbarch
, regnum
)
3428 || i386_fpc_regnum_p (gdbarch
, regnum
));
3429 if (group
== float_reggroup
)
3432 /* For "info reg all", don't include upper YMM registers nor XMM
3433 registers when AVX is supported. */
3434 ymmh_regnum_p
= i386_ymmh_regnum_p (gdbarch
, regnum
);
3435 if (group
== all_reggroup
3437 && (tdep
->xcr0
& I386_XSTATE_AVX
))
3441 if (group
== general_reggroup
)
3442 return (!fp_regnum_p
3449 return default_register_reggroup_p (gdbarch
, regnum
, group
);
3453 /* Get the ARGIth function argument for the current function. */
3456 i386_fetch_pointer_argument (struct frame_info
*frame
, int argi
,
3459 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3460 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3461 CORE_ADDR sp
= get_frame_register_unsigned (frame
, I386_ESP_REGNUM
);
3462 return read_memory_unsigned_integer (sp
+ (4 * (argi
+ 1)), 4, byte_order
);
3466 i386_skip_permanent_breakpoint (struct regcache
*regcache
)
3468 CORE_ADDR current_pc
= regcache_read_pc (regcache
);
3470 /* On i386, breakpoint is exactly 1 byte long, so we just
3471 adjust the PC in the regcache. */
3473 regcache_write_pc (regcache
, current_pc
);
3477 #define PREFIX_REPZ 0x01
3478 #define PREFIX_REPNZ 0x02
3479 #define PREFIX_LOCK 0x04
3480 #define PREFIX_DATA 0x08
3481 #define PREFIX_ADDR 0x10
3493 /* i386 arith/logic operations */
3506 struct i386_record_s
3508 struct gdbarch
*gdbarch
;
3509 struct regcache
*regcache
;
3510 CORE_ADDR orig_addr
;
3516 uint8_t mod
, reg
, rm
;
3525 /* Parse "modrm" part in current memory address that irp->addr point to
3526 Return -1 if something wrong. */
3529 i386_record_modrm (struct i386_record_s
*irp
)
3531 struct gdbarch
*gdbarch
= irp
->gdbarch
;
3533 if (target_read_memory (irp
->addr
, &irp
->modrm
, 1))
3536 printf_unfiltered (_("Process record: error reading memory at "
3537 "addr %s len = 1.\n"),
3538 paddress (gdbarch
, irp
->addr
));
3542 irp
->mod
= (irp
->modrm
>> 6) & 3;
3543 irp
->reg
= (irp
->modrm
>> 3) & 7;
3544 irp
->rm
= irp
->modrm
& 7;
3549 /* Get the memory address that current instruction write to and set it to
3550 the argument "addr".
3551 Return -1 if something wrong. */
3554 i386_record_lea_modrm_addr (struct i386_record_s
*irp
, uint64_t *addr
)
3556 struct gdbarch
*gdbarch
= irp
->gdbarch
;
3557 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3569 uint8_t base
= irp
->rm
;
3574 if (target_read_memory (irp
->addr
, &byte
, 1))
3577 printf_unfiltered (_("Process record: error reading memory "
3578 "at addr %s len = 1.\n"),
3579 paddress (gdbarch
, irp
->addr
));
3583 scale
= (byte
>> 6) & 3;
3584 index
= ((byte
>> 3) & 7) | irp
->rex_x
;
3592 if ((base
& 7) == 5)
3595 if (target_read_memory (irp
->addr
, buf
, 4))
3598 printf_unfiltered (_("Process record: error reading "
3599 "memory at addr %s len = 4.\n"),
3600 paddress (gdbarch
, irp
->addr
));
3604 *addr
= extract_signed_integer (buf
, 4, byte_order
);
3605 if (irp
->regmap
[X86_RECORD_R8_REGNUM
] && !havesib
)
3606 *addr
+= irp
->addr
+ irp
->rip_offset
;
3610 if (target_read_memory (irp
->addr
, buf
, 1))
3613 printf_unfiltered (_("Process record: error reading memory "
3614 "at addr %s len = 1.\n"),
3615 paddress (gdbarch
, irp
->addr
));
3619 *addr
= (int8_t) buf
[0];
3622 if (target_read_memory (irp
->addr
, buf
, 4))
3625 printf_unfiltered (_("Process record: error reading memory "
3626 "at addr %s len = 4.\n"),
3627 paddress (gdbarch
, irp
->addr
));
3630 *addr
= extract_signed_integer (buf
, 4, byte_order
);
3638 if (base
== 4 && irp
->popl_esp_hack
)
3639 *addr
+= irp
->popl_esp_hack
;
3640 regcache_raw_read_unsigned (irp
->regcache
, irp
->regmap
[base
],
3643 if (irp
->aflag
== 2)
3648 *addr
= (uint32_t) (offset64
+ *addr
);
3650 if (havesib
&& (index
!= 4 || scale
!= 0))
3652 regcache_raw_read_unsigned (irp
->regcache
, irp
->regmap
[index
],
3654 if (irp
->aflag
== 2)
3655 *addr
+= offset64
<< scale
;
3657 *addr
= (uint32_t) (*addr
+ (offset64
<< scale
));
3668 if (target_read_memory (irp
->addr
, buf
, 2))
3671 printf_unfiltered (_("Process record: error reading "
3672 "memory at addr %s len = 2.\n"),
3673 paddress (gdbarch
, irp
->addr
));
3677 *addr
= extract_signed_integer (buf
, 2, byte_order
);
3683 if (target_read_memory (irp
->addr
, buf
, 1))
3686 printf_unfiltered (_("Process record: error reading memory "
3687 "at addr %s len = 1.\n"),
3688 paddress (gdbarch
, irp
->addr
));
3692 *addr
= (int8_t) buf
[0];
3695 if (target_read_memory (irp
->addr
, buf
, 2))
3698 printf_unfiltered (_("Process record: error reading memory "
3699 "at addr %s len = 2.\n"),
3700 paddress (gdbarch
, irp
->addr
));
3704 *addr
= extract_signed_integer (buf
, 2, byte_order
);
3711 regcache_raw_read_unsigned (irp
->regcache
,
3712 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
3714 *addr
= (uint32_t) (*addr
+ offset64
);
3715 regcache_raw_read_unsigned (irp
->regcache
,
3716 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
3718 *addr
= (uint32_t) (*addr
+ offset64
);
3721 regcache_raw_read_unsigned (irp
->regcache
,
3722 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
3724 *addr
= (uint32_t) (*addr
+ offset64
);
3725 regcache_raw_read_unsigned (irp
->regcache
,
3726 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
3728 *addr
= (uint32_t) (*addr
+ offset64
);
3731 regcache_raw_read_unsigned (irp
->regcache
,
3732 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
3734 *addr
= (uint32_t) (*addr
+ offset64
);
3735 regcache_raw_read_unsigned (irp
->regcache
,
3736 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
3738 *addr
= (uint32_t) (*addr
+ offset64
);
3741 regcache_raw_read_unsigned (irp
->regcache
,
3742 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
3744 *addr
= (uint32_t) (*addr
+ offset64
);
3745 regcache_raw_read_unsigned (irp
->regcache
,
3746 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
3748 *addr
= (uint32_t) (*addr
+ offset64
);
3751 regcache_raw_read_unsigned (irp
->regcache
,
3752 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
3754 *addr
= (uint32_t) (*addr
+ offset64
);
3757 regcache_raw_read_unsigned (irp
->regcache
,
3758 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
3760 *addr
= (uint32_t) (*addr
+ offset64
);
3763 regcache_raw_read_unsigned (irp
->regcache
,
3764 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
3766 *addr
= (uint32_t) (*addr
+ offset64
);
3769 regcache_raw_read_unsigned (irp
->regcache
,
3770 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
3772 *addr
= (uint32_t) (*addr
+ offset64
);
3782 /* Record the value of the memory that willbe changed in current instruction
3783 to "record_arch_list".
3784 Return -1 if something wrong. */
3787 i386_record_lea_modrm (struct i386_record_s
*irp
)
3789 struct gdbarch
*gdbarch
= irp
->gdbarch
;
3792 if (irp
->override
>= 0)
3794 if (record_memory_query
)
3798 target_terminal_ours ();
3800 Process record ignores the memory change of instruction at address %s\n\
3801 because it can't get the value of the segment register.\n\
3802 Do you want to stop the program?"),
3803 paddress (gdbarch
, irp
->orig_addr
));
3804 target_terminal_inferior ();
3812 if (i386_record_lea_modrm_addr (irp
, &addr
))
3815 if (record_arch_list_add_mem (addr
, 1 << irp
->ot
))
3821 /* Record the push operation to "record_arch_list".
3822 Return -1 if something wrong. */
3825 i386_record_push (struct i386_record_s
*irp
, int size
)
3829 if (record_arch_list_add_reg (irp
->regcache
,
3830 irp
->regmap
[X86_RECORD_RESP_REGNUM
]))
3832 regcache_raw_read_unsigned (irp
->regcache
,
3833 irp
->regmap
[X86_RECORD_RESP_REGNUM
],
3835 if (record_arch_list_add_mem ((CORE_ADDR
) addr
- size
, size
))
3842 /* Defines contents to record. */
3843 #define I386_SAVE_FPU_REGS 0xfffd
3844 #define I386_SAVE_FPU_ENV 0xfffe
3845 #define I386_SAVE_FPU_ENV_REG_STACK 0xffff
3847 /* Record the value of floating point registers which will be changed
3848 by the current instruction to "record_arch_list". Return -1 if
3849 something is wrong. */
3851 static int i386_record_floats (struct gdbarch
*gdbarch
,
3852 struct i386_record_s
*ir
,
3855 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3858 /* Oza: Because of floating point insn push/pop of fpu stack is going to
3859 happen. Currently we store st0-st7 registers, but we need not store all
3860 registers all the time, in future we use ftag register and record only
3861 those who are not marked as an empty. */
3863 if (I386_SAVE_FPU_REGS
== iregnum
)
3865 for (i
= I387_ST0_REGNUM (tdep
); i
<= I387_ST0_REGNUM (tdep
) + 7; i
++)
3867 if (record_arch_list_add_reg (ir
->regcache
, i
))
3871 else if (I386_SAVE_FPU_ENV
== iregnum
)
3873 for (i
= I387_FCTRL_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
3875 if (record_arch_list_add_reg (ir
->regcache
, i
))
3879 else if (I386_SAVE_FPU_ENV_REG_STACK
== iregnum
)
3881 for (i
= I387_ST0_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
3883 if (record_arch_list_add_reg (ir
->regcache
, i
))
3887 else if ((iregnum
>= I387_ST0_REGNUM (tdep
)) &&
3888 (iregnum
<= I387_FOP_REGNUM (tdep
)))
3890 if (record_arch_list_add_reg (ir
->regcache
,iregnum
))
3895 /* Parameter error. */
3898 if(I386_SAVE_FPU_ENV
!= iregnum
)
3900 for (i
= I387_FCTRL_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
3902 if (record_arch_list_add_reg (ir
->regcache
, i
))
3909 /* Parse the current instruction and record the values of the registers and
3910 memory that will be changed in current instruction to "record_arch_list".
3911 Return -1 if something wrong. */
3913 #define I386_RECORD_ARCH_LIST_ADD_REG(regnum) \
3914 record_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)])
3917 i386_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
3918 CORE_ADDR input_addr
)
3920 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3926 gdb_byte buf
[MAX_REGISTER_SIZE
];
3927 struct i386_record_s ir
;
3928 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3933 memset (&ir
, 0, sizeof (struct i386_record_s
));
3934 ir
.regcache
= regcache
;
3935 ir
.addr
= input_addr
;
3936 ir
.orig_addr
= input_addr
;
3940 ir
.popl_esp_hack
= 0;
3941 ir
.regmap
= tdep
->record_regmap
;
3942 ir
.gdbarch
= gdbarch
;
3944 if (record_debug
> 1)
3945 fprintf_unfiltered (gdb_stdlog
, "Process record: i386_process_record "
3947 paddress (gdbarch
, ir
.addr
));
3952 if (target_read_memory (ir
.addr
, &opcode8
, 1))
3955 printf_unfiltered (_("Process record: error reading memory at "
3956 "addr %s len = 1.\n"),
3957 paddress (gdbarch
, ir
.addr
));
3961 switch (opcode8
) /* Instruction prefixes */
3963 case REPE_PREFIX_OPCODE
:
3964 prefixes
|= PREFIX_REPZ
;
3966 case REPNE_PREFIX_OPCODE
:
3967 prefixes
|= PREFIX_REPNZ
;
3969 case LOCK_PREFIX_OPCODE
:
3970 prefixes
|= PREFIX_LOCK
;
3972 case CS_PREFIX_OPCODE
:
3973 ir
.override
= X86_RECORD_CS_REGNUM
;
3975 case SS_PREFIX_OPCODE
:
3976 ir
.override
= X86_RECORD_SS_REGNUM
;
3978 case DS_PREFIX_OPCODE
:
3979 ir
.override
= X86_RECORD_DS_REGNUM
;
3981 case ES_PREFIX_OPCODE
:
3982 ir
.override
= X86_RECORD_ES_REGNUM
;
3984 case FS_PREFIX_OPCODE
:
3985 ir
.override
= X86_RECORD_FS_REGNUM
;
3987 case GS_PREFIX_OPCODE
:
3988 ir
.override
= X86_RECORD_GS_REGNUM
;
3990 case DATA_PREFIX_OPCODE
:
3991 prefixes
|= PREFIX_DATA
;
3993 case ADDR_PREFIX_OPCODE
:
3994 prefixes
|= PREFIX_ADDR
;
3996 case 0x40: /* i386 inc %eax */
3997 case 0x41: /* i386 inc %ecx */
3998 case 0x42: /* i386 inc %edx */
3999 case 0x43: /* i386 inc %ebx */
4000 case 0x44: /* i386 inc %esp */
4001 case 0x45: /* i386 inc %ebp */
4002 case 0x46: /* i386 inc %esi */
4003 case 0x47: /* i386 inc %edi */
4004 case 0x48: /* i386 dec %eax */
4005 case 0x49: /* i386 dec %ecx */
4006 case 0x4a: /* i386 dec %edx */
4007 case 0x4b: /* i386 dec %ebx */
4008 case 0x4c: /* i386 dec %esp */
4009 case 0x4d: /* i386 dec %ebp */
4010 case 0x4e: /* i386 dec %esi */
4011 case 0x4f: /* i386 dec %edi */
4012 if (ir
.regmap
[X86_RECORD_R8_REGNUM
]) /* 64 bit target */
4016 rex_w
= (opcode8
>> 3) & 1;
4017 rex_r
= (opcode8
& 0x4) << 1;
4018 ir
.rex_x
= (opcode8
& 0x2) << 2;
4019 ir
.rex_b
= (opcode8
& 0x1) << 3;
4021 else /* 32 bit target */
4030 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && rex_w
== 1)
4036 if (prefixes
& PREFIX_DATA
)
4039 if (prefixes
& PREFIX_ADDR
)
4041 else if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4044 /* Now check op code. */
4045 opcode
= (uint32_t) opcode8
;
4050 if (target_read_memory (ir
.addr
, &opcode8
, 1))
4053 printf_unfiltered (_("Process record: error reading memory at "
4054 "addr %s len = 1.\n"),
4055 paddress (gdbarch
, ir
.addr
));
4059 opcode
= (uint32_t) opcode8
| 0x0f00;
4063 case 0x00: /* arith & logic */
4111 if (((opcode
>> 3) & 7) != OP_CMPL
)
4113 if ((opcode
& 1) == 0)
4116 ir
.ot
= ir
.dflag
+ OT_WORD
;
4118 switch ((opcode
>> 1) & 3)
4120 case 0: /* OP Ev, Gv */
4121 if (i386_record_modrm (&ir
))
4125 if (i386_record_lea_modrm (&ir
))
4131 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4133 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4136 case 1: /* OP Gv, Ev */
4137 if (i386_record_modrm (&ir
))
4140 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4142 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4144 case 2: /* OP A, Iv */
4145 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4149 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4152 case 0x80: /* GRP1 */
4156 if (i386_record_modrm (&ir
))
4159 if (ir
.reg
!= OP_CMPL
)
4161 if ((opcode
& 1) == 0)
4164 ir
.ot
= ir
.dflag
+ OT_WORD
;
4171 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
4172 if (i386_record_lea_modrm (&ir
))
4176 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
4178 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4181 case 0x40: /* inc */
4190 case 0x48: /* dec */
4199 I386_RECORD_ARCH_LIST_ADD_REG (opcode
& 7);
4200 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4203 case 0xf6: /* GRP3 */
4205 if ((opcode
& 1) == 0)
4208 ir
.ot
= ir
.dflag
+ OT_WORD
;
4209 if (i386_record_modrm (&ir
))
4212 if (ir
.mod
!= 3 && ir
.reg
== 0)
4213 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
4218 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4224 if (i386_record_lea_modrm (&ir
))
4230 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4232 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4234 if (ir
.reg
== 3) /* neg */
4235 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4241 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4242 if (ir
.ot
!= OT_BYTE
)
4243 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
4244 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4248 opcode
= opcode
<< 8 | ir
.modrm
;
4254 case 0xfe: /* GRP4 */
4255 case 0xff: /* GRP5 */
4256 if (i386_record_modrm (&ir
))
4258 if (ir
.reg
>= 2 && opcode
== 0xfe)
4261 opcode
= opcode
<< 8 | ir
.modrm
;
4268 if ((opcode
& 1) == 0)
4271 ir
.ot
= ir
.dflag
+ OT_WORD
;
4274 if (i386_record_lea_modrm (&ir
))
4280 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4282 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4284 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4287 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4289 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4291 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4294 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
4295 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4297 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4301 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4304 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4306 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4311 opcode
= opcode
<< 8 | ir
.modrm
;
4317 case 0x84: /* test */
4321 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4324 case 0x98: /* CWDE/CBW */
4325 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4328 case 0x99: /* CDQ/CWD */
4329 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4330 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
4333 case 0x0faf: /* imul */
4336 ir
.ot
= ir
.dflag
+ OT_WORD
;
4337 if (i386_record_modrm (&ir
))
4340 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
4341 else if (opcode
== 0x6b)
4344 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4346 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4347 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4350 case 0x0fc0: /* xadd */
4352 if ((opcode
& 1) == 0)
4355 ir
.ot
= ir
.dflag
+ OT_WORD
;
4356 if (i386_record_modrm (&ir
))
4361 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4363 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4364 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4366 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4370 if (i386_record_lea_modrm (&ir
))
4372 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4374 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4376 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4379 case 0x0fb0: /* cmpxchg */
4381 if ((opcode
& 1) == 0)
4384 ir
.ot
= ir
.dflag
+ OT_WORD
;
4385 if (i386_record_modrm (&ir
))
4390 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4391 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4393 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4397 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4398 if (i386_record_lea_modrm (&ir
))
4401 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4404 case 0x0fc7: /* cmpxchg8b */
4405 if (i386_record_modrm (&ir
))
4410 opcode
= opcode
<< 8 | ir
.modrm
;
4413 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4414 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
4415 if (i386_record_lea_modrm (&ir
))
4417 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4420 case 0x50: /* push */
4430 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4432 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4436 case 0x06: /* push es */
4437 case 0x0e: /* push cs */
4438 case 0x16: /* push ss */
4439 case 0x1e: /* push ds */
4440 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4445 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4449 case 0x0fa0: /* push fs */
4450 case 0x0fa8: /* push gs */
4451 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4456 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4460 case 0x60: /* pusha */
4461 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4466 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 4)))
4470 case 0x58: /* pop */
4478 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4479 I386_RECORD_ARCH_LIST_ADD_REG ((opcode
& 0x7) | ir
.rex_b
);
4482 case 0x61: /* popa */
4483 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4488 for (regnum
= X86_RECORD_REAX_REGNUM
;
4489 regnum
<= X86_RECORD_REDI_REGNUM
;
4491 I386_RECORD_ARCH_LIST_ADD_REG (regnum
);
4494 case 0x8f: /* pop */
4495 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4496 ir
.ot
= ir
.dflag
? OT_QUAD
: OT_WORD
;
4498 ir
.ot
= ir
.dflag
+ OT_WORD
;
4499 if (i386_record_modrm (&ir
))
4502 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
4505 ir
.popl_esp_hack
= 1 << ir
.ot
;
4506 if (i386_record_lea_modrm (&ir
))
4509 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4512 case 0xc8: /* enter */
4513 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
4514 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4516 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4520 case 0xc9: /* leave */
4521 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4522 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
4525 case 0x07: /* pop es */
4526 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4531 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4532 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM
);
4533 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4536 case 0x17: /* pop ss */
4537 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4542 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4543 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM
);
4544 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4547 case 0x1f: /* pop ds */
4548 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4553 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4554 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM
);
4555 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4558 case 0x0fa1: /* pop fs */
4559 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4560 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM
);
4561 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4564 case 0x0fa9: /* pop gs */
4565 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4566 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM
);
4567 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4570 case 0x88: /* mov */
4574 if ((opcode
& 1) == 0)
4577 ir
.ot
= ir
.dflag
+ OT_WORD
;
4579 if (i386_record_modrm (&ir
))
4584 if (opcode
== 0xc6 || opcode
== 0xc7)
4585 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
4586 if (i386_record_lea_modrm (&ir
))
4591 if (opcode
== 0xc6 || opcode
== 0xc7)
4593 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4595 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4599 case 0x8a: /* mov */
4601 if ((opcode
& 1) == 0)
4604 ir
.ot
= ir
.dflag
+ OT_WORD
;
4605 if (i386_record_modrm (&ir
))
4608 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4610 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4613 case 0x8c: /* mov seg */
4614 if (i386_record_modrm (&ir
))
4619 opcode
= opcode
<< 8 | ir
.modrm
;
4624 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4628 if (i386_record_lea_modrm (&ir
))
4633 case 0x8e: /* mov seg */
4634 if (i386_record_modrm (&ir
))
4639 regnum
= X86_RECORD_ES_REGNUM
;
4642 regnum
= X86_RECORD_SS_REGNUM
;
4645 regnum
= X86_RECORD_DS_REGNUM
;
4648 regnum
= X86_RECORD_FS_REGNUM
;
4651 regnum
= X86_RECORD_GS_REGNUM
;
4655 opcode
= opcode
<< 8 | ir
.modrm
;
4659 I386_RECORD_ARCH_LIST_ADD_REG (regnum
);
4660 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4663 case 0x0fb6: /* movzbS */
4664 case 0x0fb7: /* movzwS */
4665 case 0x0fbe: /* movsbS */
4666 case 0x0fbf: /* movswS */
4667 if (i386_record_modrm (&ir
))
4669 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
4672 case 0x8d: /* lea */
4673 if (i386_record_modrm (&ir
))
4678 opcode
= opcode
<< 8 | ir
.modrm
;
4683 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4685 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4688 case 0xa0: /* mov EAX */
4691 case 0xd7: /* xlat */
4692 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4695 case 0xa2: /* mov EAX */
4697 if (ir
.override
>= 0)
4699 if (record_memory_query
)
4703 target_terminal_ours ();
4705 Process record ignores the memory change of instruction at address %s\n\
4706 because it can't get the value of the segment register.\n\
4707 Do you want to stop the program?"),
4708 paddress (gdbarch
, ir
.orig_addr
));
4709 target_terminal_inferior ();
4716 if ((opcode
& 1) == 0)
4719 ir
.ot
= ir
.dflag
+ OT_WORD
;
4722 if (target_read_memory (ir
.addr
, buf
, 8))
4725 printf_unfiltered (_("Process record: error reading "
4726 "memory at addr 0x%s len = 8.\n"),
4727 paddress (gdbarch
, ir
.addr
));
4731 addr
= extract_unsigned_integer (buf
, 8, byte_order
);
4735 if (target_read_memory (ir
.addr
, buf
, 4))
4738 printf_unfiltered (_("Process record: error reading "
4739 "memory at addr 0x%s len = 4.\n"),
4740 paddress (gdbarch
, ir
.addr
));
4744 addr
= extract_unsigned_integer (buf
, 4, byte_order
);
4748 if (target_read_memory (ir
.addr
, buf
, 2))
4751 printf_unfiltered (_("Process record: error reading "
4752 "memory at addr 0x%s len = 2.\n"),
4753 paddress (gdbarch
, ir
.addr
));
4757 addr
= extract_unsigned_integer (buf
, 2, byte_order
);
4759 if (record_arch_list_add_mem (addr
, 1 << ir
.ot
))
4764 case 0xb0: /* mov R, Ib */
4772 I386_RECORD_ARCH_LIST_ADD_REG ((ir
.regmap
[X86_RECORD_R8_REGNUM
])
4773 ? ((opcode
& 0x7) | ir
.rex_b
)
4774 : ((opcode
& 0x7) & 0x3));
4777 case 0xb8: /* mov R, Iv */
4785 I386_RECORD_ARCH_LIST_ADD_REG ((opcode
& 0x7) | ir
.rex_b
);
4788 case 0x91: /* xchg R, EAX */
4795 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4796 I386_RECORD_ARCH_LIST_ADD_REG (opcode
& 0x7);
4799 case 0x86: /* xchg Ev, Gv */
4801 if ((opcode
& 1) == 0)
4804 ir
.ot
= ir
.dflag
+ OT_WORD
;
4805 if (i386_record_modrm (&ir
))
4810 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4812 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4816 if (i386_record_lea_modrm (&ir
))
4820 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4822 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4825 case 0xc4: /* les Gv */
4826 case 0xc5: /* lds Gv */
4827 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4833 case 0x0fb2: /* lss Gv */
4834 case 0x0fb4: /* lfs Gv */
4835 case 0x0fb5: /* lgs Gv */
4836 if (i386_record_modrm (&ir
))
4844 opcode
= opcode
<< 8 | ir
.modrm
;
4849 case 0xc4: /* les Gv */
4850 regnum
= X86_RECORD_ES_REGNUM
;
4852 case 0xc5: /* lds Gv */
4853 regnum
= X86_RECORD_DS_REGNUM
;
4855 case 0x0fb2: /* lss Gv */
4856 regnum
= X86_RECORD_SS_REGNUM
;
4858 case 0x0fb4: /* lfs Gv */
4859 regnum
= X86_RECORD_FS_REGNUM
;
4861 case 0x0fb5: /* lgs Gv */
4862 regnum
= X86_RECORD_GS_REGNUM
;
4865 I386_RECORD_ARCH_LIST_ADD_REG (regnum
);
4866 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
4867 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4870 case 0xc0: /* shifts */
4876 if ((opcode
& 1) == 0)
4879 ir
.ot
= ir
.dflag
+ OT_WORD
;
4880 if (i386_record_modrm (&ir
))
4882 if (ir
.mod
!= 3 && (opcode
== 0xd2 || opcode
== 0xd3))
4884 if (i386_record_lea_modrm (&ir
))
4890 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4892 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4894 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4901 if (i386_record_modrm (&ir
))
4905 if (record_arch_list_add_reg (ir
.regcache
, ir
.rm
))
4910 if (i386_record_lea_modrm (&ir
))
4915 case 0xd8: /* Floats. */
4923 if (i386_record_modrm (&ir
))
4925 ir
.reg
|= ((opcode
& 7) << 3);
4931 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
4939 /* For fcom, ficom nothing to do. */
4945 /* For fcomp, ficomp pop FPU stack, store all. */
4946 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
4973 /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul,
4974 fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension
4975 of code, always affects st(0) register. */
4976 if (i386_record_floats (gdbarch
, &ir
, I387_ST0_REGNUM (tdep
)))
5000 /* Handling fld, fild. */
5001 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5005 switch (ir
.reg
>> 4)
5008 if (record_arch_list_add_mem (addr64
, 4))
5012 if (record_arch_list_add_mem (addr64
, 8))
5018 if (record_arch_list_add_mem (addr64
, 2))
5024 switch (ir
.reg
>> 4)
5027 if (record_arch_list_add_mem (addr64
, 4))
5029 if (3 == (ir
.reg
& 7))
5031 /* For fstp m32fp. */
5032 if (i386_record_floats (gdbarch
, &ir
,
5033 I386_SAVE_FPU_REGS
))
5038 if (record_arch_list_add_mem (addr64
, 4))
5040 if ((3 == (ir
.reg
& 7))
5041 || (5 == (ir
.reg
& 7))
5042 || (7 == (ir
.reg
& 7)))
5044 /* For fstp insn. */
5045 if (i386_record_floats (gdbarch
, &ir
,
5046 I386_SAVE_FPU_REGS
))
5051 if (record_arch_list_add_mem (addr64
, 8))
5053 if (3 == (ir
.reg
& 7))
5055 /* For fstp m64fp. */
5056 if (i386_record_floats (gdbarch
, &ir
,
5057 I386_SAVE_FPU_REGS
))
5062 if ((3 <= (ir
.reg
& 7)) && (6 <= (ir
.reg
& 7)))
5064 /* For fistp, fbld, fild, fbstp. */
5065 if (i386_record_floats (gdbarch
, &ir
,
5066 I386_SAVE_FPU_REGS
))
5071 if (record_arch_list_add_mem (addr64
, 2))
5080 if (i386_record_floats (gdbarch
, &ir
,
5081 I386_SAVE_FPU_ENV_REG_STACK
))
5086 if (i386_record_floats (gdbarch
, &ir
, I387_FCTRL_REGNUM (tdep
)))
5091 if (i386_record_floats (gdbarch
, &ir
,
5092 I386_SAVE_FPU_ENV_REG_STACK
))
5098 if (record_arch_list_add_mem (addr64
, 28))
5103 if (record_arch_list_add_mem (addr64
, 14))
5109 if (record_arch_list_add_mem (addr64
, 2))
5111 /* Insn fstp, fbstp. */
5112 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5117 if (record_arch_list_add_mem (addr64
, 10))
5123 if (record_arch_list_add_mem (addr64
, 28))
5129 if (record_arch_list_add_mem (addr64
, 14))
5133 if (record_arch_list_add_mem (addr64
, 80))
5136 if (i386_record_floats (gdbarch
, &ir
,
5137 I386_SAVE_FPU_ENV_REG_STACK
))
5141 if (record_arch_list_add_mem (addr64
, 8))
5144 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5149 opcode
= opcode
<< 8 | ir
.modrm
;
5154 /* Opcode is an extension of modR/M byte. */
5160 if (i386_record_floats (gdbarch
, &ir
, I387_ST0_REGNUM (tdep
)))
5164 if (0x0c == (ir
.modrm
>> 4))
5166 if ((ir
.modrm
& 0x0f) <= 7)
5168 if (i386_record_floats (gdbarch
, &ir
,
5169 I386_SAVE_FPU_REGS
))
5174 if (i386_record_floats (gdbarch
, &ir
,
5175 I387_ST0_REGNUM (tdep
)))
5177 /* If only st(0) is changing, then we have already
5179 if ((ir
.modrm
& 0x0f) - 0x08)
5181 if (i386_record_floats (gdbarch
, &ir
,
5182 I387_ST0_REGNUM (tdep
) +
5183 ((ir
.modrm
& 0x0f) - 0x08)))
5201 if (i386_record_floats (gdbarch
, &ir
,
5202 I387_ST0_REGNUM (tdep
)))
5220 if (i386_record_floats (gdbarch
, &ir
,
5221 I386_SAVE_FPU_REGS
))
5225 if (i386_record_floats (gdbarch
, &ir
,
5226 I387_ST0_REGNUM (tdep
)))
5228 if (i386_record_floats (gdbarch
, &ir
,
5229 I387_ST0_REGNUM (tdep
) + 1))
5236 if (0xe9 == ir
.modrm
)
5238 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5241 else if ((0x0c == ir
.modrm
>> 4) || (0x0d == ir
.modrm
>> 4))
5243 if (i386_record_floats (gdbarch
, &ir
,
5244 I387_ST0_REGNUM (tdep
)))
5246 if (((ir
.modrm
& 0x0f) > 0) && ((ir
.modrm
& 0x0f) <= 7))
5248 if (i386_record_floats (gdbarch
, &ir
,
5249 I387_ST0_REGNUM (tdep
) +
5253 else if ((ir
.modrm
& 0x0f) - 0x08)
5255 if (i386_record_floats (gdbarch
, &ir
,
5256 I387_ST0_REGNUM (tdep
) +
5257 ((ir
.modrm
& 0x0f) - 0x08)))
5263 if (0xe3 == ir
.modrm
)
5265 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_ENV
))
5268 else if ((0x0c == ir
.modrm
>> 4) || (0x0d == ir
.modrm
>> 4))
5270 if (i386_record_floats (gdbarch
, &ir
,
5271 I387_ST0_REGNUM (tdep
)))
5273 if (((ir
.modrm
& 0x0f) > 0) && ((ir
.modrm
& 0x0f) <= 7))
5275 if (i386_record_floats (gdbarch
, &ir
,
5276 I387_ST0_REGNUM (tdep
) +
5280 else if ((ir
.modrm
& 0x0f) - 0x08)
5282 if (i386_record_floats (gdbarch
, &ir
,
5283 I387_ST0_REGNUM (tdep
) +
5284 ((ir
.modrm
& 0x0f) - 0x08)))
5290 if ((0x0c == ir
.modrm
>> 4)
5291 || (0x0d == ir
.modrm
>> 4)
5292 || (0x0f == ir
.modrm
>> 4))
5294 if ((ir
.modrm
& 0x0f) <= 7)
5296 if (i386_record_floats (gdbarch
, &ir
,
5297 I387_ST0_REGNUM (tdep
) +
5303 if (i386_record_floats (gdbarch
, &ir
,
5304 I387_ST0_REGNUM (tdep
) +
5305 ((ir
.modrm
& 0x0f) - 0x08)))
5311 if (0x0c == ir
.modrm
>> 4)
5313 if (i386_record_floats (gdbarch
, &ir
,
5314 I387_FTAG_REGNUM (tdep
)))
5317 else if ((0x0d == ir
.modrm
>> 4) || (0x0e == ir
.modrm
>> 4))
5319 if ((ir
.modrm
& 0x0f) <= 7)
5321 if (i386_record_floats (gdbarch
, &ir
,
5322 I387_ST0_REGNUM (tdep
) +
5328 if (i386_record_floats (gdbarch
, &ir
,
5329 I386_SAVE_FPU_REGS
))
5335 if ((0x0c == ir
.modrm
>> 4)
5336 || (0x0e == ir
.modrm
>> 4)
5337 || (0x0f == ir
.modrm
>> 4)
5338 || (0xd9 == ir
.modrm
))
5340 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5345 if (0xe0 == ir
.modrm
)
5347 if (record_arch_list_add_reg (ir
.regcache
, I386_EAX_REGNUM
))
5350 else if ((0x0f == ir
.modrm
>> 4) || (0x0e == ir
.modrm
>> 4))
5352 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5360 case 0xa4: /* movsS */
5362 case 0xaa: /* stosS */
5364 case 0x6c: /* insS */
5366 regcache_raw_read_unsigned (ir
.regcache
,
5367 ir
.regmap
[X86_RECORD_RECX_REGNUM
],
5373 if ((opcode
& 1) == 0)
5376 ir
.ot
= ir
.dflag
+ OT_WORD
;
5377 regcache_raw_read_unsigned (ir
.regcache
,
5378 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
5381 regcache_raw_read_unsigned (ir
.regcache
,
5382 ir
.regmap
[X86_RECORD_ES_REGNUM
],
5384 regcache_raw_read_unsigned (ir
.regcache
,
5385 ir
.regmap
[X86_RECORD_DS_REGNUM
],
5387 if (ir
.aflag
&& (es
!= ds
))
5389 /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */
5390 if (record_memory_query
)
5394 target_terminal_ours ();
5396 Process record ignores the memory change of instruction at address %s\n\
5397 because it can't get the value of the segment register.\n\
5398 Do you want to stop the program?"),
5399 paddress (gdbarch
, ir
.orig_addr
));
5400 target_terminal_inferior ();
5407 if (record_arch_list_add_mem (addr
, 1 << ir
.ot
))
5411 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5412 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5413 if (opcode
== 0xa4 || opcode
== 0xa5)
5414 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
5415 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
5416 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5420 case 0xa6: /* cmpsS */
5422 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
5423 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
5424 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5425 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5426 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5429 case 0xac: /* lodsS */
5431 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5432 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
5433 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5434 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5435 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5438 case 0xae: /* scasS */
5440 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
5441 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5442 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5443 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5446 case 0x6e: /* outsS */
5448 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
5449 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5450 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5451 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5454 case 0xe4: /* port I/O */
5458 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5459 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5469 case 0xc2: /* ret im */
5470 case 0xc3: /* ret */
5471 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5472 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5475 case 0xca: /* lret im */
5476 case 0xcb: /* lret */
5477 case 0xcf: /* iret */
5478 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
5479 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5480 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5483 case 0xe8: /* call im */
5484 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5486 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5490 case 0x9a: /* lcall im */
5491 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5496 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
5497 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5501 case 0xe9: /* jmp im */
5502 case 0xea: /* ljmp im */
5503 case 0xeb: /* jmp Jb */
5504 case 0x70: /* jcc Jb */
5520 case 0x0f80: /* jcc Jv */
5538 case 0x0f90: /* setcc Gv */
5554 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5556 if (i386_record_modrm (&ir
))
5559 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rex_b
? (ir
.rm
| ir
.rex_b
)
5563 if (i386_record_lea_modrm (&ir
))
5568 case 0x0f40: /* cmov Gv, Ev */
5584 if (i386_record_modrm (&ir
))
5587 if (ir
.dflag
== OT_BYTE
)
5589 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
5593 case 0x9c: /* pushf */
5594 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5595 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5597 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5601 case 0x9d: /* popf */
5602 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5603 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5606 case 0x9e: /* sahf */
5607 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5613 case 0xf5: /* cmc */
5614 case 0xf8: /* clc */
5615 case 0xf9: /* stc */
5616 case 0xfc: /* cld */
5617 case 0xfd: /* std */
5618 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5621 case 0x9f: /* lahf */
5622 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5627 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5628 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5631 /* bit operations */
5632 case 0x0fba: /* bt/bts/btr/btc Gv, im */
5633 ir
.ot
= ir
.dflag
+ OT_WORD
;
5634 if (i386_record_modrm (&ir
))
5639 opcode
= opcode
<< 8 | ir
.modrm
;
5645 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5648 if (i386_record_lea_modrm (&ir
))
5652 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5655 case 0x0fa3: /* bt Gv, Ev */
5656 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5659 case 0x0fab: /* bts */
5660 case 0x0fb3: /* btr */
5661 case 0x0fbb: /* btc */
5662 ir
.ot
= ir
.dflag
+ OT_WORD
;
5663 if (i386_record_modrm (&ir
))
5666 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5670 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
5672 regcache_raw_read_unsigned (ir
.regcache
,
5673 ir
.regmap
[ir
.reg
| rex_r
],
5678 addr64
+= ((int16_t) addr
>> 4) << 4;
5681 addr64
+= ((int32_t) addr
>> 5) << 5;
5684 addr64
+= ((int64_t) addr
>> 6) << 6;
5687 if (record_arch_list_add_mem (addr64
, 1 << ir
.ot
))
5689 if (i386_record_lea_modrm (&ir
))
5692 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5695 case 0x0fbc: /* bsf */
5696 case 0x0fbd: /* bsr */
5697 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
5698 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5702 case 0x27: /* daa */
5703 case 0x2f: /* das */
5704 case 0x37: /* aaa */
5705 case 0x3f: /* aas */
5706 case 0xd4: /* aam */
5707 case 0xd5: /* aad */
5708 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5713 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5714 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5718 case 0x90: /* nop */
5719 if (prefixes
& PREFIX_LOCK
)
5726 case 0x9b: /* fwait */
5727 if (target_read_memory (ir
.addr
, &opcode8
, 1))
5730 printf_unfiltered (_("Process record: error reading memory at "
5731 "addr 0x%s len = 1.\n"),
5732 paddress (gdbarch
, ir
.addr
));
5735 opcode
= (uint32_t) opcode8
;
5741 case 0xcc: /* int3 */
5742 printf_unfiltered (_("Process record does not support instruction "
5749 case 0xcd: /* int */
5753 if (target_read_memory (ir
.addr
, &interrupt
, 1))
5756 printf_unfiltered (_("Process record: error reading memory "
5757 "at addr %s len = 1.\n"),
5758 paddress (gdbarch
, ir
.addr
));
5762 if (interrupt
!= 0x80
5763 || tdep
->i386_intx80_record
== NULL
)
5765 printf_unfiltered (_("Process record does not support "
5766 "instruction int 0x%02x.\n"),
5771 ret
= tdep
->i386_intx80_record (ir
.regcache
);
5778 case 0xce: /* into */
5779 printf_unfiltered (_("Process record does not support "
5780 "instruction into.\n"));
5785 case 0xfa: /* cli */
5786 case 0xfb: /* sti */
5789 case 0x62: /* bound */
5790 printf_unfiltered (_("Process record does not support "
5791 "instruction bound.\n"));
5796 case 0x0fc8: /* bswap reg */
5804 I386_RECORD_ARCH_LIST_ADD_REG ((opcode
& 7) | ir
.rex_b
);
5807 case 0xd6: /* salc */
5808 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5813 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5814 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5817 case 0xe0: /* loopnz */
5818 case 0xe1: /* loopz */
5819 case 0xe2: /* loop */
5820 case 0xe3: /* jecxz */
5821 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5822 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5825 case 0x0f30: /* wrmsr */
5826 printf_unfiltered (_("Process record does not support "
5827 "instruction wrmsr.\n"));
5832 case 0x0f32: /* rdmsr */
5833 printf_unfiltered (_("Process record does not support "
5834 "instruction rdmsr.\n"));
5839 case 0x0f31: /* rdtsc */
5840 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5841 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5844 case 0x0f34: /* sysenter */
5847 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5852 if (tdep
->i386_sysenter_record
== NULL
)
5854 printf_unfiltered (_("Process record does not support "
5855 "instruction sysenter.\n"));
5859 ret
= tdep
->i386_sysenter_record (ir
.regcache
);
5865 case 0x0f35: /* sysexit */
5866 printf_unfiltered (_("Process record does not support "
5867 "instruction sysexit.\n"));
5872 case 0x0f05: /* syscall */
5875 if (tdep
->i386_syscall_record
== NULL
)
5877 printf_unfiltered (_("Process record does not support "
5878 "instruction syscall.\n"));
5882 ret
= tdep
->i386_syscall_record (ir
.regcache
);
5888 case 0x0f07: /* sysret */
5889 printf_unfiltered (_("Process record does not support "
5890 "instruction sysret.\n"));
5895 case 0x0fa2: /* cpuid */
5896 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5897 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5898 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5899 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM
);
5902 case 0xf4: /* hlt */
5903 printf_unfiltered (_("Process record does not support "
5904 "instruction hlt.\n"));
5910 if (i386_record_modrm (&ir
))
5917 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5921 if (i386_record_lea_modrm (&ir
))
5930 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5934 opcode
= opcode
<< 8 | ir
.modrm
;
5941 if (i386_record_modrm (&ir
))
5952 opcode
= opcode
<< 8 | ir
.modrm
;
5955 if (ir
.override
>= 0)
5957 if (record_memory_query
)
5961 target_terminal_ours ();
5963 Process record ignores the memory change of instruction at address %s\n\
5964 because it can't get the value of the segment register.\n\
5965 Do you want to stop the program?"),
5966 paddress (gdbarch
, ir
.orig_addr
));
5967 target_terminal_inferior ();
5974 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
5976 if (record_arch_list_add_mem (addr64
, 2))
5979 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5981 if (record_arch_list_add_mem (addr64
, 8))
5986 if (record_arch_list_add_mem (addr64
, 4))
5997 case 0: /* monitor */
6000 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6004 opcode
= opcode
<< 8 | ir
.modrm
;
6012 if (ir
.override
>= 0)
6014 if (record_memory_query
)
6018 target_terminal_ours ();
6020 Process record ignores the memory change of instruction at address %s\n\
6021 because it can't get the value of the segment register.\n\
6022 Do you want to stop the program?"),
6023 paddress (gdbarch
, ir
.orig_addr
));
6024 target_terminal_inferior ();
6033 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
6035 if (record_arch_list_add_mem (addr64
, 2))
6038 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6040 if (record_arch_list_add_mem (addr64
, 8))
6045 if (record_arch_list_add_mem (addr64
, 4))
6057 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6058 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
6062 else if (ir
.rm
== 1)
6069 opcode
= opcode
<< 8 | ir
.modrm
;
6076 if (record_arch_list_add_reg (ir
.regcache
, ir
.rm
| ir
.rex_b
))
6082 if (i386_record_lea_modrm (&ir
))
6085 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6088 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6090 case 7: /* invlpg */
6093 if (ir
.rm
== 0 && ir
.regmap
[X86_RECORD_R8_REGNUM
])
6094 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM
);
6098 opcode
= opcode
<< 8 | ir
.modrm
;
6103 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6107 opcode
= opcode
<< 8 | ir
.modrm
;
6113 case 0x0f08: /* invd */
6114 case 0x0f09: /* wbinvd */
6117 case 0x63: /* arpl */
6118 if (i386_record_modrm (&ir
))
6120 if (ir
.mod
== 3 || ir
.regmap
[X86_RECORD_R8_REGNUM
])
6122 I386_RECORD_ARCH_LIST_ADD_REG (ir
.regmap
[X86_RECORD_R8_REGNUM
]
6123 ? (ir
.reg
| rex_r
) : ir
.rm
);
6127 ir
.ot
= ir
.dflag
? OT_LONG
: OT_WORD
;
6128 if (i386_record_lea_modrm (&ir
))
6131 if (!ir
.regmap
[X86_RECORD_R8_REGNUM
])
6132 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6135 case 0x0f02: /* lar */
6136 case 0x0f03: /* lsl */
6137 if (i386_record_modrm (&ir
))
6139 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
6140 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6144 if (i386_record_modrm (&ir
))
6146 if (ir
.mod
== 3 && ir
.reg
== 3)
6149 opcode
= opcode
<< 8 | ir
.modrm
;
6161 /* nop (multi byte) */
6164 case 0x0f20: /* mov reg, crN */
6165 case 0x0f22: /* mov crN, reg */
6166 if (i386_record_modrm (&ir
))
6168 if ((ir
.modrm
& 0xc0) != 0xc0)
6171 opcode
= opcode
<< 8 | ir
.modrm
;
6182 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6184 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6188 opcode
= opcode
<< 8 | ir
.modrm
;
6194 case 0x0f21: /* mov reg, drN */
6195 case 0x0f23: /* mov drN, reg */
6196 if (i386_record_modrm (&ir
))
6198 if ((ir
.modrm
& 0xc0) != 0xc0 || ir
.reg
== 4
6199 || ir
.reg
== 5 || ir
.reg
>= 8)
6202 opcode
= opcode
<< 8 | ir
.modrm
;
6206 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6208 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6211 case 0x0f06: /* clts */
6212 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6215 /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */
6217 case 0x0f0d: /* 3DNow! prefetch */
6220 case 0x0f0e: /* 3DNow! femms */
6221 case 0x0f77: /* emms */
6222 if (i386_fpc_regnum_p (gdbarch
, I387_FTAG_REGNUM(tdep
)))
6224 record_arch_list_add_reg (ir
.regcache
, I387_FTAG_REGNUM(tdep
));
6227 case 0x0f0f: /* 3DNow! data */
6228 if (i386_record_modrm (&ir
))
6230 if (target_read_memory (ir
.addr
, &opcode8
, 1))
6232 printf_unfiltered (_("Process record: error reading memory at "
6233 "addr %s len = 1.\n"),
6234 paddress (gdbarch
, ir
.addr
));
6240 case 0x0c: /* 3DNow! pi2fw */
6241 case 0x0d: /* 3DNow! pi2fd */
6242 case 0x1c: /* 3DNow! pf2iw */
6243 case 0x1d: /* 3DNow! pf2id */
6244 case 0x8a: /* 3DNow! pfnacc */
6245 case 0x8e: /* 3DNow! pfpnacc */
6246 case 0x90: /* 3DNow! pfcmpge */
6247 case 0x94: /* 3DNow! pfmin */
6248 case 0x96: /* 3DNow! pfrcp */
6249 case 0x97: /* 3DNow! pfrsqrt */
6250 case 0x9a: /* 3DNow! pfsub */
6251 case 0x9e: /* 3DNow! pfadd */
6252 case 0xa0: /* 3DNow! pfcmpgt */
6253 case 0xa4: /* 3DNow! pfmax */
6254 case 0xa6: /* 3DNow! pfrcpit1 */
6255 case 0xa7: /* 3DNow! pfrsqit1 */
6256 case 0xaa: /* 3DNow! pfsubr */
6257 case 0xae: /* 3DNow! pfacc */
6258 case 0xb0: /* 3DNow! pfcmpeq */
6259 case 0xb4: /* 3DNow! pfmul */
6260 case 0xb6: /* 3DNow! pfrcpit2 */
6261 case 0xb7: /* 3DNow! pmulhrw */
6262 case 0xbb: /* 3DNow! pswapd */
6263 case 0xbf: /* 3DNow! pavgusb */
6264 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.reg
))
6265 goto no_support_3dnow_data
;
6266 record_arch_list_add_reg (ir
.regcache
, ir
.reg
);
6270 no_support_3dnow_data
:
6271 opcode
= (opcode
<< 8) | opcode8
;
6277 case 0x0faa: /* rsm */
6278 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6279 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6280 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6281 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
6282 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM
);
6283 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
6284 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
6285 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
6286 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
6290 if (i386_record_modrm (&ir
))
6294 case 0: /* fxsave */
6298 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6299 if (i386_record_lea_modrm_addr (&ir
, &tmpu64
))
6301 if (record_arch_list_add_mem (tmpu64
, 512))
6306 case 1: /* fxrstor */
6310 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6312 for (i
= I387_MM0_REGNUM (tdep
);
6313 i386_mmx_regnum_p (gdbarch
, i
); i
++)
6314 record_arch_list_add_reg (ir
.regcache
, i
);
6316 for (i
= I387_XMM0_REGNUM (tdep
);
6317 i386_xmm_regnum_p (gdbarch
, i
); i
++)
6318 record_arch_list_add_reg (ir
.regcache
, i
);
6320 if (i386_mxcsr_regnum_p (gdbarch
, I387_MXCSR_REGNUM(tdep
)))
6321 record_arch_list_add_reg (ir
.regcache
, I387_MXCSR_REGNUM(tdep
));
6323 for (i
= I387_ST0_REGNUM (tdep
);
6324 i386_fp_regnum_p (gdbarch
, i
); i
++)
6325 record_arch_list_add_reg (ir
.regcache
, i
);
6327 for (i
= I387_FCTRL_REGNUM (tdep
);
6328 i386_fpc_regnum_p (gdbarch
, i
); i
++)
6329 record_arch_list_add_reg (ir
.regcache
, i
);
6333 case 2: /* ldmxcsr */
6334 if (!i386_mxcsr_regnum_p (gdbarch
, I387_MXCSR_REGNUM(tdep
)))
6336 record_arch_list_add_reg (ir
.regcache
, I387_MXCSR_REGNUM(tdep
));
6339 case 3: /* stmxcsr */
6341 if (i386_record_lea_modrm (&ir
))
6345 case 5: /* lfence */
6346 case 6: /* mfence */
6347 case 7: /* sfence clflush */
6351 opcode
= (opcode
<< 8) | ir
.modrm
;
6357 case 0x0fc3: /* movnti */
6358 ir
.ot
= (ir
.dflag
== 2) ? OT_QUAD
: OT_LONG
;
6359 if (i386_record_modrm (&ir
))
6364 if (i386_record_lea_modrm (&ir
))
6368 /* Add prefix to opcode. */
6495 reswitch_prefix_add
:
6503 if (target_read_memory (ir
.addr
, &opcode8
, 1))
6505 printf_unfiltered (_("Process record: error reading memory at "
6506 "addr %s len = 1.\n"),
6507 paddress (gdbarch
, ir
.addr
));
6511 opcode
= (uint32_t) opcode8
| opcode
<< 8;
6512 goto reswitch_prefix_add
;
6515 case 0x0f10: /* movups */
6516 case 0x660f10: /* movupd */
6517 case 0xf30f10: /* movss */
6518 case 0xf20f10: /* movsd */
6519 case 0x0f12: /* movlps */
6520 case 0x660f12: /* movlpd */
6521 case 0xf30f12: /* movsldup */
6522 case 0xf20f12: /* movddup */
6523 case 0x0f14: /* unpcklps */
6524 case 0x660f14: /* unpcklpd */
6525 case 0x0f15: /* unpckhps */
6526 case 0x660f15: /* unpckhpd */
6527 case 0x0f16: /* movhps */
6528 case 0x660f16: /* movhpd */
6529 case 0xf30f16: /* movshdup */
6530 case 0x0f28: /* movaps */
6531 case 0x660f28: /* movapd */
6532 case 0x0f2a: /* cvtpi2ps */
6533 case 0x660f2a: /* cvtpi2pd */
6534 case 0xf30f2a: /* cvtsi2ss */
6535 case 0xf20f2a: /* cvtsi2sd */
6536 case 0x0f2c: /* cvttps2pi */
6537 case 0x660f2c: /* cvttpd2pi */
6538 case 0x0f2d: /* cvtps2pi */
6539 case 0x660f2d: /* cvtpd2pi */
6540 case 0x660f3800: /* pshufb */
6541 case 0x660f3801: /* phaddw */
6542 case 0x660f3802: /* phaddd */
6543 case 0x660f3803: /* phaddsw */
6544 case 0x660f3804: /* pmaddubsw */
6545 case 0x660f3805: /* phsubw */
6546 case 0x660f3806: /* phsubd */
6547 case 0x660f3807: /* phsubsw */
6548 case 0x660f3808: /* psignb */
6549 case 0x660f3809: /* psignw */
6550 case 0x660f380a: /* psignd */
6551 case 0x660f380b: /* pmulhrsw */
6552 case 0x660f3810: /* pblendvb */
6553 case 0x660f3814: /* blendvps */
6554 case 0x660f3815: /* blendvpd */
6555 case 0x660f381c: /* pabsb */
6556 case 0x660f381d: /* pabsw */
6557 case 0x660f381e: /* pabsd */
6558 case 0x660f3820: /* pmovsxbw */
6559 case 0x660f3821: /* pmovsxbd */
6560 case 0x660f3822: /* pmovsxbq */
6561 case 0x660f3823: /* pmovsxwd */
6562 case 0x660f3824: /* pmovsxwq */
6563 case 0x660f3825: /* pmovsxdq */
6564 case 0x660f3828: /* pmuldq */
6565 case 0x660f3829: /* pcmpeqq */
6566 case 0x660f382a: /* movntdqa */
6567 case 0x660f3a08: /* roundps */
6568 case 0x660f3a09: /* roundpd */
6569 case 0x660f3a0a: /* roundss */
6570 case 0x660f3a0b: /* roundsd */
6571 case 0x660f3a0c: /* blendps */
6572 case 0x660f3a0d: /* blendpd */
6573 case 0x660f3a0e: /* pblendw */
6574 case 0x660f3a0f: /* palignr */
6575 case 0x660f3a20: /* pinsrb */
6576 case 0x660f3a21: /* insertps */
6577 case 0x660f3a22: /* pinsrd pinsrq */
6578 case 0x660f3a40: /* dpps */
6579 case 0x660f3a41: /* dppd */
6580 case 0x660f3a42: /* mpsadbw */
6581 case 0x660f3a60: /* pcmpestrm */
6582 case 0x660f3a61: /* pcmpestri */
6583 case 0x660f3a62: /* pcmpistrm */
6584 case 0x660f3a63: /* pcmpistri */
6585 case 0x0f51: /* sqrtps */
6586 case 0x660f51: /* sqrtpd */
6587 case 0xf20f51: /* sqrtsd */
6588 case 0xf30f51: /* sqrtss */
6589 case 0x0f52: /* rsqrtps */
6590 case 0xf30f52: /* rsqrtss */
6591 case 0x0f53: /* rcpps */
6592 case 0xf30f53: /* rcpss */
6593 case 0x0f54: /* andps */
6594 case 0x660f54: /* andpd */
6595 case 0x0f55: /* andnps */
6596 case 0x660f55: /* andnpd */
6597 case 0x0f56: /* orps */
6598 case 0x660f56: /* orpd */
6599 case 0x0f57: /* xorps */
6600 case 0x660f57: /* xorpd */
6601 case 0x0f58: /* addps */
6602 case 0x660f58: /* addpd */
6603 case 0xf20f58: /* addsd */
6604 case 0xf30f58: /* addss */
6605 case 0x0f59: /* mulps */
6606 case 0x660f59: /* mulpd */
6607 case 0xf20f59: /* mulsd */
6608 case 0xf30f59: /* mulss */
6609 case 0x0f5a: /* cvtps2pd */
6610 case 0x660f5a: /* cvtpd2ps */
6611 case 0xf20f5a: /* cvtsd2ss */
6612 case 0xf30f5a: /* cvtss2sd */
6613 case 0x0f5b: /* cvtdq2ps */
6614 case 0x660f5b: /* cvtps2dq */
6615 case 0xf30f5b: /* cvttps2dq */
6616 case 0x0f5c: /* subps */
6617 case 0x660f5c: /* subpd */
6618 case 0xf20f5c: /* subsd */
6619 case 0xf30f5c: /* subss */
6620 case 0x0f5d: /* minps */
6621 case 0x660f5d: /* minpd */
6622 case 0xf20f5d: /* minsd */
6623 case 0xf30f5d: /* minss */
6624 case 0x0f5e: /* divps */
6625 case 0x660f5e: /* divpd */
6626 case 0xf20f5e: /* divsd */
6627 case 0xf30f5e: /* divss */
6628 case 0x0f5f: /* maxps */
6629 case 0x660f5f: /* maxpd */
6630 case 0xf20f5f: /* maxsd */
6631 case 0xf30f5f: /* maxss */
6632 case 0x660f60: /* punpcklbw */
6633 case 0x660f61: /* punpcklwd */
6634 case 0x660f62: /* punpckldq */
6635 case 0x660f63: /* packsswb */
6636 case 0x660f64: /* pcmpgtb */
6637 case 0x660f65: /* pcmpgtw */
6638 case 0x660f66: /* pcmpgtd */
6639 case 0x660f67: /* packuswb */
6640 case 0x660f68: /* punpckhbw */
6641 case 0x660f69: /* punpckhwd */
6642 case 0x660f6a: /* punpckhdq */
6643 case 0x660f6b: /* packssdw */
6644 case 0x660f6c: /* punpcklqdq */
6645 case 0x660f6d: /* punpckhqdq */
6646 case 0x660f6e: /* movd */
6647 case 0x660f6f: /* movdqa */
6648 case 0xf30f6f: /* movdqu */
6649 case 0x660f70: /* pshufd */
6650 case 0xf20f70: /* pshuflw */
6651 case 0xf30f70: /* pshufhw */
6652 case 0x660f74: /* pcmpeqb */
6653 case 0x660f75: /* pcmpeqw */
6654 case 0x660f76: /* pcmpeqd */
6655 case 0x660f7c: /* haddpd */
6656 case 0xf20f7c: /* haddps */
6657 case 0x660f7d: /* hsubpd */
6658 case 0xf20f7d: /* hsubps */
6659 case 0xf30f7e: /* movq */
6660 case 0x0fc2: /* cmpps */
6661 case 0x660fc2: /* cmppd */
6662 case 0xf20fc2: /* cmpsd */
6663 case 0xf30fc2: /* cmpss */
6664 case 0x660fc4: /* pinsrw */
6665 case 0x0fc6: /* shufps */
6666 case 0x660fc6: /* shufpd */
6667 case 0x660fd0: /* addsubpd */
6668 case 0xf20fd0: /* addsubps */
6669 case 0x660fd1: /* psrlw */
6670 case 0x660fd2: /* psrld */
6671 case 0x660fd3: /* psrlq */
6672 case 0x660fd4: /* paddq */
6673 case 0x660fd5: /* pmullw */
6674 case 0xf30fd6: /* movq2dq */
6675 case 0x660fd8: /* psubusb */
6676 case 0x660fd9: /* psubusw */
6677 case 0x660fda: /* pminub */
6678 case 0x660fdb: /* pand */
6679 case 0x660fdc: /* paddusb */
6680 case 0x660fdd: /* paddusw */
6681 case 0x660fde: /* pmaxub */
6682 case 0x660fdf: /* pandn */
6683 case 0x660fe0: /* pavgb */
6684 case 0x660fe1: /* psraw */
6685 case 0x660fe2: /* psrad */
6686 case 0x660fe3: /* pavgw */
6687 case 0x660fe4: /* pmulhuw */
6688 case 0x660fe5: /* pmulhw */
6689 case 0x660fe6: /* cvttpd2dq */
6690 case 0xf20fe6: /* cvtpd2dq */
6691 case 0xf30fe6: /* cvtdq2pd */
6692 case 0x660fe8: /* psubsb */
6693 case 0x660fe9: /* psubsw */
6694 case 0x660fea: /* pminsw */
6695 case 0x660feb: /* por */
6696 case 0x660fec: /* paddsb */
6697 case 0x660fed: /* paddsw */
6698 case 0x660fee: /* pmaxsw */
6699 case 0x660fef: /* pxor */
6700 case 0xf20ff0: /* lddqu */
6701 case 0x660ff1: /* psllw */
6702 case 0x660ff2: /* pslld */
6703 case 0x660ff3: /* psllq */
6704 case 0x660ff4: /* pmuludq */
6705 case 0x660ff5: /* pmaddwd */
6706 case 0x660ff6: /* psadbw */
6707 case 0x660ff8: /* psubb */
6708 case 0x660ff9: /* psubw */
6709 case 0x660ffa: /* psubd */
6710 case 0x660ffb: /* psubq */
6711 case 0x660ffc: /* paddb */
6712 case 0x660ffd: /* paddw */
6713 case 0x660ffe: /* paddd */
6714 if (i386_record_modrm (&ir
))
6717 if (!i386_xmm_regnum_p (gdbarch
, I387_XMM0_REGNUM (tdep
) + ir
.reg
))
6719 record_arch_list_add_reg (ir
.regcache
,
6720 I387_XMM0_REGNUM (tdep
) + ir
.reg
);
6721 if ((opcode
& 0xfffffffc) == 0x660f3a60)
6722 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6725 case 0x0f11: /* movups */
6726 case 0x660f11: /* movupd */
6727 case 0xf30f11: /* movss */
6728 case 0xf20f11: /* movsd */
6729 case 0x0f13: /* movlps */
6730 case 0x660f13: /* movlpd */
6731 case 0x0f17: /* movhps */
6732 case 0x660f17: /* movhpd */
6733 case 0x0f29: /* movaps */
6734 case 0x660f29: /* movapd */
6735 case 0x660f3a14: /* pextrb */
6736 case 0x660f3a15: /* pextrw */
6737 case 0x660f3a16: /* pextrd pextrq */
6738 case 0x660f3a17: /* extractps */
6739 case 0x660f7f: /* movdqa */
6740 case 0xf30f7f: /* movdqu */
6741 if (i386_record_modrm (&ir
))
6745 if (opcode
== 0x0f13 || opcode
== 0x660f13
6746 || opcode
== 0x0f17 || opcode
== 0x660f17)
6749 if (!i386_xmm_regnum_p (gdbarch
,
6750 I387_XMM0_REGNUM (tdep
) + ir
.rm
))
6752 record_arch_list_add_reg (ir
.regcache
,
6753 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
6775 if (i386_record_lea_modrm (&ir
))
6780 case 0x0f2b: /* movntps */
6781 case 0x660f2b: /* movntpd */
6782 case 0x0fe7: /* movntq */
6783 case 0x660fe7: /* movntdq */
6786 if (opcode
== 0x0fe7)
6790 if (i386_record_lea_modrm (&ir
))
6794 case 0xf30f2c: /* cvttss2si */
6795 case 0xf20f2c: /* cvttsd2si */
6796 case 0xf30f2d: /* cvtss2si */
6797 case 0xf20f2d: /* cvtsd2si */
6798 case 0xf20f38f0: /* crc32 */
6799 case 0xf20f38f1: /* crc32 */
6800 case 0x0f50: /* movmskps */
6801 case 0x660f50: /* movmskpd */
6802 case 0x0fc5: /* pextrw */
6803 case 0x660fc5: /* pextrw */
6804 case 0x0fd7: /* pmovmskb */
6805 case 0x660fd7: /* pmovmskb */
6806 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
6809 case 0x0f3800: /* pshufb */
6810 case 0x0f3801: /* phaddw */
6811 case 0x0f3802: /* phaddd */
6812 case 0x0f3803: /* phaddsw */
6813 case 0x0f3804: /* pmaddubsw */
6814 case 0x0f3805: /* phsubw */
6815 case 0x0f3806: /* phsubd */
6816 case 0x0f3807: /* phsubsw */
6817 case 0x0f3808: /* psignb */
6818 case 0x0f3809: /* psignw */
6819 case 0x0f380a: /* psignd */
6820 case 0x0f380b: /* pmulhrsw */
6821 case 0x0f381c: /* pabsb */
6822 case 0x0f381d: /* pabsw */
6823 case 0x0f381e: /* pabsd */
6824 case 0x0f382b: /* packusdw */
6825 case 0x0f3830: /* pmovzxbw */
6826 case 0x0f3831: /* pmovzxbd */
6827 case 0x0f3832: /* pmovzxbq */
6828 case 0x0f3833: /* pmovzxwd */
6829 case 0x0f3834: /* pmovzxwq */
6830 case 0x0f3835: /* pmovzxdq */
6831 case 0x0f3837: /* pcmpgtq */
6832 case 0x0f3838: /* pminsb */
6833 case 0x0f3839: /* pminsd */
6834 case 0x0f383a: /* pminuw */
6835 case 0x0f383b: /* pminud */
6836 case 0x0f383c: /* pmaxsb */
6837 case 0x0f383d: /* pmaxsd */
6838 case 0x0f383e: /* pmaxuw */
6839 case 0x0f383f: /* pmaxud */
6840 case 0x0f3840: /* pmulld */
6841 case 0x0f3841: /* phminposuw */
6842 case 0x0f3a0f: /* palignr */
6843 case 0x0f60: /* punpcklbw */
6844 case 0x0f61: /* punpcklwd */
6845 case 0x0f62: /* punpckldq */
6846 case 0x0f63: /* packsswb */
6847 case 0x0f64: /* pcmpgtb */
6848 case 0x0f65: /* pcmpgtw */
6849 case 0x0f66: /* pcmpgtd */
6850 case 0x0f67: /* packuswb */
6851 case 0x0f68: /* punpckhbw */
6852 case 0x0f69: /* punpckhwd */
6853 case 0x0f6a: /* punpckhdq */
6854 case 0x0f6b: /* packssdw */
6855 case 0x0f6e: /* movd */
6856 case 0x0f6f: /* movq */
6857 case 0x0f70: /* pshufw */
6858 case 0x0f74: /* pcmpeqb */
6859 case 0x0f75: /* pcmpeqw */
6860 case 0x0f76: /* pcmpeqd */
6861 case 0x0fc4: /* pinsrw */
6862 case 0x0fd1: /* psrlw */
6863 case 0x0fd2: /* psrld */
6864 case 0x0fd3: /* psrlq */
6865 case 0x0fd4: /* paddq */
6866 case 0x0fd5: /* pmullw */
6867 case 0xf20fd6: /* movdq2q */
6868 case 0x0fd8: /* psubusb */
6869 case 0x0fd9: /* psubusw */
6870 case 0x0fda: /* pminub */
6871 case 0x0fdb: /* pand */
6872 case 0x0fdc: /* paddusb */
6873 case 0x0fdd: /* paddusw */
6874 case 0x0fde: /* pmaxub */
6875 case 0x0fdf: /* pandn */
6876 case 0x0fe0: /* pavgb */
6877 case 0x0fe1: /* psraw */
6878 case 0x0fe2: /* psrad */
6879 case 0x0fe3: /* pavgw */
6880 case 0x0fe4: /* pmulhuw */
6881 case 0x0fe5: /* pmulhw */
6882 case 0x0fe8: /* psubsb */
6883 case 0x0fe9: /* psubsw */
6884 case 0x0fea: /* pminsw */
6885 case 0x0feb: /* por */
6886 case 0x0fec: /* paddsb */
6887 case 0x0fed: /* paddsw */
6888 case 0x0fee: /* pmaxsw */
6889 case 0x0fef: /* pxor */
6890 case 0x0ff1: /* psllw */
6891 case 0x0ff2: /* pslld */
6892 case 0x0ff3: /* psllq */
6893 case 0x0ff4: /* pmuludq */
6894 case 0x0ff5: /* pmaddwd */
6895 case 0x0ff6: /* psadbw */
6896 case 0x0ff8: /* psubb */
6897 case 0x0ff9: /* psubw */
6898 case 0x0ffa: /* psubd */
6899 case 0x0ffb: /* psubq */
6900 case 0x0ffc: /* paddb */
6901 case 0x0ffd: /* paddw */
6902 case 0x0ffe: /* paddd */
6903 if (i386_record_modrm (&ir
))
6905 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.reg
))
6907 record_arch_list_add_reg (ir
.regcache
,
6908 I387_MM0_REGNUM (tdep
) + ir
.reg
);
6911 case 0x0f71: /* psllw */
6912 case 0x0f72: /* pslld */
6913 case 0x0f73: /* psllq */
6914 if (i386_record_modrm (&ir
))
6916 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.rm
))
6918 record_arch_list_add_reg (ir
.regcache
,
6919 I387_MM0_REGNUM (tdep
) + ir
.rm
);
6922 case 0x660f71: /* psllw */
6923 case 0x660f72: /* pslld */
6924 case 0x660f73: /* psllq */
6925 if (i386_record_modrm (&ir
))
6928 if (!i386_xmm_regnum_p (gdbarch
, I387_XMM0_REGNUM (tdep
) + ir
.rm
))
6930 record_arch_list_add_reg (ir
.regcache
,
6931 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
6934 case 0x0f7e: /* movd */
6935 case 0x660f7e: /* movd */
6936 if (i386_record_modrm (&ir
))
6939 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6946 if (i386_record_lea_modrm (&ir
))
6951 case 0x0f7f: /* movq */
6952 if (i386_record_modrm (&ir
))
6956 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.rm
))
6958 record_arch_list_add_reg (ir
.regcache
,
6959 I387_MM0_REGNUM (tdep
) + ir
.rm
);
6964 if (i386_record_lea_modrm (&ir
))
6969 case 0xf30fb8: /* popcnt */
6970 if (i386_record_modrm (&ir
))
6972 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
6973 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6976 case 0x660fd6: /* movq */
6977 if (i386_record_modrm (&ir
))
6982 if (!i386_xmm_regnum_p (gdbarch
,
6983 I387_XMM0_REGNUM (tdep
) + ir
.rm
))
6985 record_arch_list_add_reg (ir
.regcache
,
6986 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
6991 if (i386_record_lea_modrm (&ir
))
6996 case 0x660f3817: /* ptest */
6997 case 0x0f2e: /* ucomiss */
6998 case 0x660f2e: /* ucomisd */
6999 case 0x0f2f: /* comiss */
7000 case 0x660f2f: /* comisd */
7001 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7004 case 0x0ff7: /* maskmovq */
7005 regcache_raw_read_unsigned (ir
.regcache
,
7006 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
7008 if (record_arch_list_add_mem (addr
, 64))
7012 case 0x660ff7: /* maskmovdqu */
7013 regcache_raw_read_unsigned (ir
.regcache
,
7014 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
7016 if (record_arch_list_add_mem (addr
, 128))
7031 /* In the future, maybe still need to deal with need_dasm. */
7032 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM
);
7033 if (record_arch_list_add_end ())
7039 printf_unfiltered (_("Process record does not support instruction 0x%02x "
7040 "at address %s.\n"),
7041 (unsigned int) (opcode
),
7042 paddress (gdbarch
, ir
.orig_addr
));
7046 static const int i386_record_regmap
[] =
7048 I386_EAX_REGNUM
, I386_ECX_REGNUM
, I386_EDX_REGNUM
, I386_EBX_REGNUM
,
7049 I386_ESP_REGNUM
, I386_EBP_REGNUM
, I386_ESI_REGNUM
, I386_EDI_REGNUM
,
7050 0, 0, 0, 0, 0, 0, 0, 0,
7051 I386_EIP_REGNUM
, I386_EFLAGS_REGNUM
, I386_CS_REGNUM
, I386_SS_REGNUM
,
7052 I386_DS_REGNUM
, I386_ES_REGNUM
, I386_FS_REGNUM
, I386_GS_REGNUM
7055 /* Check that the given address appears suitable for a fast
7056 tracepoint, which on x86 means that we need an instruction of at
7057 least 5 bytes, so that we can overwrite it with a 4-byte-offset
7058 jump and not have to worry about program jumps to an address in the
7059 middle of the tracepoint jump. Returns 1 if OK, and writes a size
7060 of instruction to replace, and 0 if not, plus an explanatory
7064 i386_fast_tracepoint_valid_at (struct gdbarch
*gdbarch
,
7065 CORE_ADDR addr
, int *isize
, char **msg
)
7068 static struct ui_file
*gdb_null
= NULL
;
7070 /* This is based on the target agent using a 4-byte relative jump.
7071 Alternate future possibilities include 8-byte offset for x86-84,
7072 or 3-byte jumps if the program has trampoline space close by. */
7075 /* Dummy file descriptor for the disassembler. */
7077 gdb_null
= ui_file_new ();
7079 /* Check for fit. */
7080 len
= gdb_print_insn (gdbarch
, addr
, gdb_null
, NULL
);
7083 /* Return a bit of target-specific detail to add to the caller's
7084 generic failure message. */
7086 *msg
= xstrprintf (_("; instruction is only %d bytes long, "
7087 "need at least %d bytes for the jump"),
7100 i386_validate_tdesc_p (struct gdbarch_tdep
*tdep
,
7101 struct tdesc_arch_data
*tdesc_data
)
7103 const struct target_desc
*tdesc
= tdep
->tdesc
;
7104 const struct tdesc_feature
*feature_core
;
7105 const struct tdesc_feature
*feature_sse
, *feature_avx
;
7106 int i
, num_regs
, valid_p
;
7108 if (! tdesc_has_registers (tdesc
))
7111 /* Get core registers. */
7112 feature_core
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.core");
7113 if (feature_core
== NULL
)
7116 /* Get SSE registers. */
7117 feature_sse
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.sse");
7119 /* Try AVX registers. */
7120 feature_avx
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx");
7124 /* The XCR0 bits. */
7127 /* AVX register description requires SSE register description. */
7131 tdep
->xcr0
= I386_XSTATE_AVX_MASK
;
7133 /* It may have been set by OSABI initialization function. */
7134 if (tdep
->num_ymm_regs
== 0)
7136 tdep
->ymmh_register_names
= i386_ymmh_names
;
7137 tdep
->num_ymm_regs
= 8;
7138 tdep
->ymm0h_regnum
= I386_YMM0H_REGNUM
;
7141 for (i
= 0; i
< tdep
->num_ymm_regs
; i
++)
7142 valid_p
&= tdesc_numbered_register (feature_avx
, tdesc_data
,
7143 tdep
->ymm0h_regnum
+ i
,
7144 tdep
->ymmh_register_names
[i
]);
7146 else if (feature_sse
)
7147 tdep
->xcr0
= I386_XSTATE_SSE_MASK
;
7150 tdep
->xcr0
= I386_XSTATE_X87_MASK
;
7151 tdep
->num_xmm_regs
= 0;
7154 num_regs
= tdep
->num_core_regs
;
7155 for (i
= 0; i
< num_regs
; i
++)
7156 valid_p
&= tdesc_numbered_register (feature_core
, tdesc_data
, i
,
7157 tdep
->register_names
[i
]);
7161 /* Need to include %mxcsr, so add one. */
7162 num_regs
+= tdep
->num_xmm_regs
+ 1;
7163 for (; i
< num_regs
; i
++)
7164 valid_p
&= tdesc_numbered_register (feature_sse
, tdesc_data
, i
,
7165 tdep
->register_names
[i
]);
7172 static struct gdbarch
*
7173 i386_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
7175 struct gdbarch_tdep
*tdep
;
7176 struct gdbarch
*gdbarch
;
7177 struct tdesc_arch_data
*tdesc_data
;
7178 const struct target_desc
*tdesc
;
7182 /* If there is already a candidate, use it. */
7183 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
7185 return arches
->gdbarch
;
7187 /* Allocate space for the new architecture. */
7188 tdep
= XCALLOC (1, struct gdbarch_tdep
);
7189 gdbarch
= gdbarch_alloc (&info
, tdep
);
7191 /* General-purpose registers. */
7192 tdep
->gregset
= NULL
;
7193 tdep
->gregset_reg_offset
= NULL
;
7194 tdep
->gregset_num_regs
= I386_NUM_GREGS
;
7195 tdep
->sizeof_gregset
= 0;
7197 /* Floating-point registers. */
7198 tdep
->fpregset
= NULL
;
7199 tdep
->sizeof_fpregset
= I387_SIZEOF_FSAVE
;
7201 tdep
->xstateregset
= NULL
;
7203 /* The default settings include the FPU registers, the MMX registers
7204 and the SSE registers. This can be overridden for a specific ABI
7205 by adjusting the members `st0_regnum', `mm0_regnum' and
7206 `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers
7207 will show up in the output of "info all-registers". */
7209 tdep
->st0_regnum
= I386_ST0_REGNUM
;
7211 /* I386_NUM_XREGS includes %mxcsr, so substract one. */
7212 tdep
->num_xmm_regs
= I386_NUM_XREGS
- 1;
7214 tdep
->jb_pc_offset
= -1;
7215 tdep
->struct_return
= pcc_struct_return
;
7216 tdep
->sigtramp_start
= 0;
7217 tdep
->sigtramp_end
= 0;
7218 tdep
->sigtramp_p
= i386_sigtramp_p
;
7219 tdep
->sigcontext_addr
= NULL
;
7220 tdep
->sc_reg_offset
= NULL
;
7221 tdep
->sc_pc_offset
= -1;
7222 tdep
->sc_sp_offset
= -1;
7224 tdep
->xsave_xcr0_offset
= -1;
7226 tdep
->record_regmap
= i386_record_regmap
;
7228 /* The format used for `long double' on almost all i386 targets is
7229 the i387 extended floating-point format. In fact, of all targets
7230 in the GCC 2.95 tree, only OSF/1 does it different, and insists
7231 on having a `long double' that's not `long' at all. */
7232 set_gdbarch_long_double_format (gdbarch
, floatformats_i387_ext
);
7234 /* Although the i387 extended floating-point has only 80 significant
7235 bits, a `long double' actually takes up 96, probably to enforce
7237 set_gdbarch_long_double_bit (gdbarch
, 96);
7239 /* Register numbers of various important registers. */
7240 set_gdbarch_sp_regnum (gdbarch
, I386_ESP_REGNUM
); /* %esp */
7241 set_gdbarch_pc_regnum (gdbarch
, I386_EIP_REGNUM
); /* %eip */
7242 set_gdbarch_ps_regnum (gdbarch
, I386_EFLAGS_REGNUM
); /* %eflags */
7243 set_gdbarch_fp0_regnum (gdbarch
, I386_ST0_REGNUM
); /* %st(0) */
7245 /* NOTE: kettenis/20040418: GCC does have two possible register
7246 numbering schemes on the i386: dbx and SVR4. These schemes
7247 differ in how they number %ebp, %esp, %eflags, and the
7248 floating-point registers, and are implemented by the arrays
7249 dbx_register_map[] and svr4_dbx_register_map in
7250 gcc/config/i386.c. GCC also defines a third numbering scheme in
7251 gcc/config/i386.c, which it designates as the "default" register
7252 map used in 64bit mode. This last register numbering scheme is
7253 implemented in dbx64_register_map, and is used for AMD64; see
7256 Currently, each GCC i386 target always uses the same register
7257 numbering scheme across all its supported debugging formats
7258 i.e. SDB (COFF), stabs and DWARF 2. This is because
7259 gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the
7260 DBX_REGISTER_NUMBER macro which is defined by each target's
7261 respective config header in a manner independent of the requested
7262 output debugging format.
7264 This does not match the arrangement below, which presumes that
7265 the SDB and stabs numbering schemes differ from the DWARF and
7266 DWARF 2 ones. The reason for this arrangement is that it is
7267 likely to get the numbering scheme for the target's
7268 default/native debug format right. For targets where GCC is the
7269 native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for
7270 targets where the native toolchain uses a different numbering
7271 scheme for a particular debug format (stabs-in-ELF on Solaris)
7272 the defaults below will have to be overridden, like
7273 i386_elf_init_abi() does. */
7275 /* Use the dbx register numbering scheme for stabs and COFF. */
7276 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
7277 set_gdbarch_sdb_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
7279 /* Use the SVR4 register numbering scheme for DWARF 2. */
7280 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
7282 /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to
7283 be in use on any of the supported i386 targets. */
7285 set_gdbarch_print_float_info (gdbarch
, i387_print_float_info
);
7287 set_gdbarch_get_longjmp_target (gdbarch
, i386_get_longjmp_target
);
7289 /* Call dummy code. */
7290 set_gdbarch_push_dummy_call (gdbarch
, i386_push_dummy_call
);
7292 set_gdbarch_convert_register_p (gdbarch
, i386_convert_register_p
);
7293 set_gdbarch_register_to_value (gdbarch
, i386_register_to_value
);
7294 set_gdbarch_value_to_register (gdbarch
, i386_value_to_register
);
7296 set_gdbarch_return_value (gdbarch
, i386_return_value
);
7298 set_gdbarch_skip_prologue (gdbarch
, i386_skip_prologue
);
7300 /* Stack grows downward. */
7301 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
7303 set_gdbarch_breakpoint_from_pc (gdbarch
, i386_breakpoint_from_pc
);
7304 set_gdbarch_decr_pc_after_break (gdbarch
, 1);
7305 set_gdbarch_max_insn_length (gdbarch
, I386_MAX_INSN_LEN
);
7307 set_gdbarch_frame_args_skip (gdbarch
, 8);
7309 set_gdbarch_print_insn (gdbarch
, i386_print_insn
);
7311 set_gdbarch_dummy_id (gdbarch
, i386_dummy_id
);
7313 set_gdbarch_unwind_pc (gdbarch
, i386_unwind_pc
);
7315 /* Add the i386 register groups. */
7316 i386_add_reggroups (gdbarch
);
7317 tdep
->register_reggroup_p
= i386_register_reggroup_p
;
7319 /* Helper for function argument information. */
7320 set_gdbarch_fetch_pointer_argument (gdbarch
, i386_fetch_pointer_argument
);
7322 /* Hook the function epilogue frame unwinder. This unwinder is
7323 appended to the list first, so that it supercedes the DWARF
7324 unwinder in function epilogues (where the DWARF unwinder
7325 currently fails). */
7326 frame_unwind_append_unwinder (gdbarch
, &i386_epilogue_frame_unwind
);
7328 /* Hook in the DWARF CFI frame unwinder. This unwinder is appended
7329 to the list before the prologue-based unwinders, so that DWARF
7330 CFI info will be used if it is available. */
7331 dwarf2_append_unwinders (gdbarch
);
7333 frame_base_set_default (gdbarch
, &i386_frame_base
);
7335 /* Pseudo registers may be changed by amd64_init_abi. */
7336 set_gdbarch_pseudo_register_read (gdbarch
, i386_pseudo_register_read
);
7337 set_gdbarch_pseudo_register_write (gdbarch
, i386_pseudo_register_write
);
7339 set_tdesc_pseudo_register_type (gdbarch
, i386_pseudo_register_type
);
7340 set_tdesc_pseudo_register_name (gdbarch
, i386_pseudo_register_name
);
7342 /* Override the normal target description method to make the AVX
7343 upper halves anonymous. */
7344 set_gdbarch_register_name (gdbarch
, i386_register_name
);
7346 /* Even though the default ABI only includes general-purpose registers,
7347 floating-point registers and the SSE registers, we have to leave a
7348 gap for the upper AVX registers. */
7349 set_gdbarch_num_regs (gdbarch
, I386_AVX_NUM_REGS
);
7351 /* Get the x86 target description from INFO. */
7352 tdesc
= info
.target_desc
;
7353 if (! tdesc_has_registers (tdesc
))
7355 tdep
->tdesc
= tdesc
;
7357 tdep
->num_core_regs
= I386_NUM_GREGS
+ I387_NUM_REGS
;
7358 tdep
->register_names
= i386_register_names
;
7360 /* No upper YMM registers. */
7361 tdep
->ymmh_register_names
= NULL
;
7362 tdep
->ymm0h_regnum
= -1;
7364 tdep
->num_byte_regs
= 8;
7365 tdep
->num_word_regs
= 8;
7366 tdep
->num_dword_regs
= 0;
7367 tdep
->num_mmx_regs
= 8;
7368 tdep
->num_ymm_regs
= 0;
7370 tdesc_data
= tdesc_data_alloc ();
7372 set_gdbarch_relocate_instruction (gdbarch
, i386_relocate_instruction
);
7374 /* Hook in ABI-specific overrides, if they have been registered. */
7375 info
.tdep_info
= (void *) tdesc_data
;
7376 gdbarch_init_osabi (info
, gdbarch
);
7378 if (!i386_validate_tdesc_p (tdep
, tdesc_data
))
7380 tdesc_data_cleanup (tdesc_data
);
7382 gdbarch_free (gdbarch
);
7386 /* Wire in pseudo registers. Number of pseudo registers may be
7388 set_gdbarch_num_pseudo_regs (gdbarch
, (tdep
->num_byte_regs
7389 + tdep
->num_word_regs
7390 + tdep
->num_dword_regs
7391 + tdep
->num_mmx_regs
7392 + tdep
->num_ymm_regs
));
7394 /* Target description may be changed. */
7395 tdesc
= tdep
->tdesc
;
7397 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
7399 /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */
7400 set_gdbarch_register_reggroup_p (gdbarch
, tdep
->register_reggroup_p
);
7402 /* Make %al the first pseudo-register. */
7403 tdep
->al_regnum
= gdbarch_num_regs (gdbarch
);
7404 tdep
->ax_regnum
= tdep
->al_regnum
+ tdep
->num_byte_regs
;
7406 ymm0_regnum
= tdep
->ax_regnum
+ tdep
->num_word_regs
;
7407 if (tdep
->num_dword_regs
)
7409 /* Support dword pseudo-register if it hasn't been disabled. */
7410 tdep
->eax_regnum
= ymm0_regnum
;
7411 ymm0_regnum
+= tdep
->num_dword_regs
;
7414 tdep
->eax_regnum
= -1;
7416 mm0_regnum
= ymm0_regnum
;
7417 if (tdep
->num_ymm_regs
)
7419 /* Support YMM pseudo-register if it is available. */
7420 tdep
->ymm0_regnum
= ymm0_regnum
;
7421 mm0_regnum
+= tdep
->num_ymm_regs
;
7424 tdep
->ymm0_regnum
= -1;
7426 if (tdep
->num_mmx_regs
!= 0)
7428 /* Support MMX pseudo-register if MMX hasn't been disabled. */
7429 tdep
->mm0_regnum
= mm0_regnum
;
7432 tdep
->mm0_regnum
= -1;
7434 /* Hook in the legacy prologue-based unwinders last (fallback). */
7435 frame_unwind_append_unwinder (gdbarch
, &i386_stack_tramp_frame_unwind
);
7436 frame_unwind_append_unwinder (gdbarch
, &i386_sigtramp_frame_unwind
);
7437 frame_unwind_append_unwinder (gdbarch
, &i386_frame_unwind
);
7439 /* If we have a register mapping, enable the generic core file
7440 support, unless it has already been enabled. */
7441 if (tdep
->gregset_reg_offset
7442 && !gdbarch_regset_from_core_section_p (gdbarch
))
7443 set_gdbarch_regset_from_core_section (gdbarch
,
7444 i386_regset_from_core_section
);
7446 set_gdbarch_skip_permanent_breakpoint (gdbarch
,
7447 i386_skip_permanent_breakpoint
);
7449 set_gdbarch_fast_tracepoint_valid_at (gdbarch
,
7450 i386_fast_tracepoint_valid_at
);
7455 static enum gdb_osabi
7456 i386_coff_osabi_sniffer (bfd
*abfd
)
7458 if (strcmp (bfd_get_target (abfd
), "coff-go32-exe") == 0
7459 || strcmp (bfd_get_target (abfd
), "coff-go32") == 0)
7460 return GDB_OSABI_GO32
;
7462 return GDB_OSABI_UNKNOWN
;
7466 /* Provide a prototype to silence -Wmissing-prototypes. */
7467 void _initialize_i386_tdep (void);
7470 _initialize_i386_tdep (void)
7472 register_gdbarch_init (bfd_arch_i386
, i386_gdbarch_init
);
7474 /* Add the variable that controls the disassembly flavor. */
7475 add_setshow_enum_cmd ("disassembly-flavor", no_class
, valid_flavors
,
7476 &disassembly_flavor
, _("\
7477 Set the disassembly flavor."), _("\
7478 Show the disassembly flavor."), _("\
7479 The valid values are \"att\" and \"intel\", and the default value is \"att\"."),
7481 NULL
, /* FIXME: i18n: */
7482 &setlist
, &showlist
);
7484 /* Add the variable that controls the convention for returning
7486 add_setshow_enum_cmd ("struct-convention", no_class
, valid_conventions
,
7487 &struct_convention
, _("\
7488 Set the convention for returning small structs."), _("\
7489 Show the convention for returning small structs."), _("\
7490 Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\
7493 NULL
, /* FIXME: i18n: */
7494 &setlist
, &showlist
);
7496 gdbarch_register_osabi_sniffer (bfd_arch_i386
, bfd_target_coff_flavour
,
7497 i386_coff_osabi_sniffer
);
7499 gdbarch_register_osabi (bfd_arch_i386
, 0, GDB_OSABI_SVR4
,
7500 i386_svr4_init_abi
);
7501 gdbarch_register_osabi (bfd_arch_i386
, 0, GDB_OSABI_GO32
,
7502 i386_go32_init_abi
);
7504 /* Initialize the i386-specific register groups. */
7505 i386_init_reggroups ();
7507 /* Initialize the standard target descriptions. */
7508 initialize_tdesc_i386 ();
7509 initialize_tdesc_i386_mmx ();
7510 initialize_tdesc_i386_avx ();
7512 /* Tell remote stub that we support XML target description. */
7513 register_remote_support_xml ("i386");