1 /* Intel 386 target-dependent stuff.
3 Copyright (C) 1988-2017 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "opcode/i386.h"
22 #include "arch-utils.h"
24 #include "dummy-frame.h"
25 #include "dwarf2-frame.h"
28 #include "frame-base.h"
29 #include "frame-unwind.h"
38 #include "reggroups.h"
47 #include "i386-tdep.h"
48 #include "i387-tdep.h"
49 #include "x86-xstate.h"
52 #include "record-full.h"
53 #include "target-descriptions.h"
54 #include "arch/i386.h"
59 #include "stap-probe.h"
60 #include "user-regs.h"
61 #include "cli/cli-utils.h"
62 #include "expression.h"
63 #include "parser-defs.h"
69 static const char *i386_register_names
[] =
71 "eax", "ecx", "edx", "ebx",
72 "esp", "ebp", "esi", "edi",
73 "eip", "eflags", "cs", "ss",
74 "ds", "es", "fs", "gs",
75 "st0", "st1", "st2", "st3",
76 "st4", "st5", "st6", "st7",
77 "fctrl", "fstat", "ftag", "fiseg",
78 "fioff", "foseg", "fooff", "fop",
79 "xmm0", "xmm1", "xmm2", "xmm3",
80 "xmm4", "xmm5", "xmm6", "xmm7",
84 static const char *i386_zmm_names
[] =
86 "zmm0", "zmm1", "zmm2", "zmm3",
87 "zmm4", "zmm5", "zmm6", "zmm7"
90 static const char *i386_zmmh_names
[] =
92 "zmm0h", "zmm1h", "zmm2h", "zmm3h",
93 "zmm4h", "zmm5h", "zmm6h", "zmm7h"
96 static const char *i386_k_names
[] =
98 "k0", "k1", "k2", "k3",
99 "k4", "k5", "k6", "k7"
102 static const char *i386_ymm_names
[] =
104 "ymm0", "ymm1", "ymm2", "ymm3",
105 "ymm4", "ymm5", "ymm6", "ymm7",
108 static const char *i386_ymmh_names
[] =
110 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
111 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
114 static const char *i386_mpx_names
[] =
116 "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus"
119 static const char* i386_pkeys_names
[] =
124 /* Register names for MPX pseudo-registers. */
126 static const char *i386_bnd_names
[] =
128 "bnd0", "bnd1", "bnd2", "bnd3"
131 /* Register names for MMX pseudo-registers. */
133 static const char *i386_mmx_names
[] =
135 "mm0", "mm1", "mm2", "mm3",
136 "mm4", "mm5", "mm6", "mm7"
139 /* Register names for byte pseudo-registers. */
141 static const char *i386_byte_names
[] =
143 "al", "cl", "dl", "bl",
144 "ah", "ch", "dh", "bh"
147 /* Register names for word pseudo-registers. */
149 static const char *i386_word_names
[] =
151 "ax", "cx", "dx", "bx",
155 /* Constant used for reading/writing pseudo registers. In 64-bit mode, we have
156 16 lower ZMM regs that extend corresponding xmm/ymm registers. In addition,
157 we have 16 upper ZMM regs that have to be handled differently. */
159 const int num_lower_zmm_regs
= 16;
164 i386_mmx_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
166 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
167 int mm0_regnum
= tdep
->mm0_regnum
;
172 regnum
-= mm0_regnum
;
173 return regnum
>= 0 && regnum
< tdep
->num_mmx_regs
;
179 i386_byte_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
181 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
183 regnum
-= tdep
->al_regnum
;
184 return regnum
>= 0 && regnum
< tdep
->num_byte_regs
;
190 i386_word_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
192 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
194 regnum
-= tdep
->ax_regnum
;
195 return regnum
>= 0 && regnum
< tdep
->num_word_regs
;
198 /* Dword register? */
201 i386_dword_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
203 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
204 int eax_regnum
= tdep
->eax_regnum
;
209 regnum
-= eax_regnum
;
210 return regnum
>= 0 && regnum
< tdep
->num_dword_regs
;
213 /* AVX512 register? */
216 i386_zmmh_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
218 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
219 int zmm0h_regnum
= tdep
->zmm0h_regnum
;
221 if (zmm0h_regnum
< 0)
224 regnum
-= zmm0h_regnum
;
225 return regnum
>= 0 && regnum
< tdep
->num_zmm_regs
;
229 i386_zmm_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
231 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
232 int zmm0_regnum
= tdep
->zmm0_regnum
;
237 regnum
-= zmm0_regnum
;
238 return regnum
>= 0 && regnum
< tdep
->num_zmm_regs
;
242 i386_k_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
244 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
245 int k0_regnum
= tdep
->k0_regnum
;
251 return regnum
>= 0 && regnum
< I387_NUM_K_REGS
;
255 i386_ymmh_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
257 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
258 int ymm0h_regnum
= tdep
->ymm0h_regnum
;
260 if (ymm0h_regnum
< 0)
263 regnum
-= ymm0h_regnum
;
264 return regnum
>= 0 && regnum
< tdep
->num_ymm_regs
;
270 i386_ymm_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
272 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
273 int ymm0_regnum
= tdep
->ymm0_regnum
;
278 regnum
-= ymm0_regnum
;
279 return regnum
>= 0 && regnum
< tdep
->num_ymm_regs
;
283 i386_ymmh_avx512_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
285 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
286 int ymm16h_regnum
= tdep
->ymm16h_regnum
;
288 if (ymm16h_regnum
< 0)
291 regnum
-= ymm16h_regnum
;
292 return regnum
>= 0 && regnum
< tdep
->num_ymm_avx512_regs
;
296 i386_ymm_avx512_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
298 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
299 int ymm16_regnum
= tdep
->ymm16_regnum
;
301 if (ymm16_regnum
< 0)
304 regnum
-= ymm16_regnum
;
305 return regnum
>= 0 && regnum
< tdep
->num_ymm_avx512_regs
;
311 i386_bnd_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
313 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
314 int bnd0_regnum
= tdep
->bnd0_regnum
;
319 regnum
-= bnd0_regnum
;
320 return regnum
>= 0 && regnum
< I387_NUM_BND_REGS
;
326 i386_xmm_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
328 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
329 int num_xmm_regs
= I387_NUM_XMM_REGS (tdep
);
331 if (num_xmm_regs
== 0)
334 regnum
-= I387_XMM0_REGNUM (tdep
);
335 return regnum
>= 0 && regnum
< num_xmm_regs
;
338 /* XMM_512 register? */
341 i386_xmm_avx512_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
343 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
344 int num_xmm_avx512_regs
= I387_NUM_XMM_AVX512_REGS (tdep
);
346 if (num_xmm_avx512_regs
== 0)
349 regnum
-= I387_XMM16_REGNUM (tdep
);
350 return regnum
>= 0 && regnum
< num_xmm_avx512_regs
;
354 i386_mxcsr_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
356 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
358 if (I387_NUM_XMM_REGS (tdep
) == 0)
361 return (regnum
== I387_MXCSR_REGNUM (tdep
));
367 i386_fp_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
369 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
371 if (I387_ST0_REGNUM (tdep
) < 0)
374 return (I387_ST0_REGNUM (tdep
) <= regnum
375 && regnum
< I387_FCTRL_REGNUM (tdep
));
379 i386_fpc_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
381 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
383 if (I387_ST0_REGNUM (tdep
) < 0)
386 return (I387_FCTRL_REGNUM (tdep
) <= regnum
387 && regnum
< I387_XMM0_REGNUM (tdep
));
390 /* BNDr (raw) register? */
393 i386_bndr_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
395 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
397 if (I387_BND0R_REGNUM (tdep
) < 0)
400 regnum
-= tdep
->bnd0r_regnum
;
401 return regnum
>= 0 && regnum
< I387_NUM_BND_REGS
;
404 /* BND control register? */
407 i386_mpx_ctrl_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
409 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
411 if (I387_BNDCFGU_REGNUM (tdep
) < 0)
414 regnum
-= I387_BNDCFGU_REGNUM (tdep
);
415 return regnum
>= 0 && regnum
< I387_NUM_MPX_CTRL_REGS
;
421 i386_pkru_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
423 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
424 int pkru_regnum
= tdep
->pkru_regnum
;
429 regnum
-= pkru_regnum
;
430 return regnum
>= 0 && regnum
< I387_NUM_PKEYS_REGS
;
433 /* Return the name of register REGNUM, or the empty string if it is
434 an anonymous register. */
437 i386_register_name (struct gdbarch
*gdbarch
, int regnum
)
439 /* Hide the upper YMM registers. */
440 if (i386_ymmh_regnum_p (gdbarch
, regnum
))
443 /* Hide the upper YMM16-31 registers. */
444 if (i386_ymmh_avx512_regnum_p (gdbarch
, regnum
))
447 /* Hide the upper ZMM registers. */
448 if (i386_zmmh_regnum_p (gdbarch
, regnum
))
451 return tdesc_register_name (gdbarch
, regnum
);
454 /* Return the name of register REGNUM. */
457 i386_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
459 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
460 if (i386_bnd_regnum_p (gdbarch
, regnum
))
461 return i386_bnd_names
[regnum
- tdep
->bnd0_regnum
];
462 if (i386_mmx_regnum_p (gdbarch
, regnum
))
463 return i386_mmx_names
[regnum
- I387_MM0_REGNUM (tdep
)];
464 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
465 return i386_ymm_names
[regnum
- tdep
->ymm0_regnum
];
466 else if (i386_zmm_regnum_p (gdbarch
, regnum
))
467 return i386_zmm_names
[regnum
- tdep
->zmm0_regnum
];
468 else if (i386_byte_regnum_p (gdbarch
, regnum
))
469 return i386_byte_names
[regnum
- tdep
->al_regnum
];
470 else if (i386_word_regnum_p (gdbarch
, regnum
))
471 return i386_word_names
[regnum
- tdep
->ax_regnum
];
473 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
476 /* Convert a dbx register number REG to the appropriate register
477 number used by GDB. */
480 i386_dbx_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
482 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
484 /* This implements what GCC calls the "default" register map
485 (dbx_register_map[]). */
487 if (reg
>= 0 && reg
<= 7)
489 /* General-purpose registers. The debug info calls %ebp
490 register 4, and %esp register 5. */
497 else if (reg
>= 12 && reg
<= 19)
499 /* Floating-point registers. */
500 return reg
- 12 + I387_ST0_REGNUM (tdep
);
502 else if (reg
>= 21 && reg
<= 28)
505 int ymm0_regnum
= tdep
->ymm0_regnum
;
508 && i386_xmm_regnum_p (gdbarch
, reg
))
509 return reg
- 21 + ymm0_regnum
;
511 return reg
- 21 + I387_XMM0_REGNUM (tdep
);
513 else if (reg
>= 29 && reg
<= 36)
516 return reg
- 29 + I387_MM0_REGNUM (tdep
);
519 /* This will hopefully provoke a warning. */
520 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
523 /* Convert SVR4 DWARF register number REG to the appropriate register number
527 i386_svr4_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
529 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
531 /* This implements the GCC register map that tries to be compatible
532 with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */
534 /* The SVR4 register numbering includes %eip and %eflags, and
535 numbers the floating point registers differently. */
536 if (reg
>= 0 && reg
<= 9)
538 /* General-purpose registers. */
541 else if (reg
>= 11 && reg
<= 18)
543 /* Floating-point registers. */
544 return reg
- 11 + I387_ST0_REGNUM (tdep
);
546 else if (reg
>= 21 && reg
<= 36)
548 /* The SSE and MMX registers have the same numbers as with dbx. */
549 return i386_dbx_reg_to_regnum (gdbarch
, reg
);
554 case 37: return I387_FCTRL_REGNUM (tdep
);
555 case 38: return I387_FSTAT_REGNUM (tdep
);
556 case 39: return I387_MXCSR_REGNUM (tdep
);
557 case 40: return I386_ES_REGNUM
;
558 case 41: return I386_CS_REGNUM
;
559 case 42: return I386_SS_REGNUM
;
560 case 43: return I386_DS_REGNUM
;
561 case 44: return I386_FS_REGNUM
;
562 case 45: return I386_GS_REGNUM
;
568 /* Wrapper on i386_svr4_dwarf_reg_to_regnum to return
569 num_regs + num_pseudo_regs for other debug formats. */
572 i386_svr4_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
574 int regnum
= i386_svr4_dwarf_reg_to_regnum (gdbarch
, reg
);
577 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
583 /* This is the variable that is set with "set disassembly-flavor", and
584 its legitimate values. */
585 static const char att_flavor
[] = "att";
586 static const char intel_flavor
[] = "intel";
587 static const char *const valid_flavors
[] =
593 static const char *disassembly_flavor
= att_flavor
;
596 /* Use the program counter to determine the contents and size of a
597 breakpoint instruction. Return a pointer to a string of bytes that
598 encode a breakpoint instruction, store the length of the string in
599 *LEN and optionally adjust *PC to point to the correct memory
600 location for inserting the breakpoint.
602 On the i386 we have a single breakpoint that fits in a single byte
603 and can be inserted anywhere.
605 This function is 64-bit safe. */
607 constexpr gdb_byte i386_break_insn
[] = { 0xcc }; /* int 3 */
609 typedef BP_MANIPULATION (i386_break_insn
) i386_breakpoint
;
612 /* Displaced instruction handling. */
614 /* Skip the legacy instruction prefixes in INSN.
615 Not all prefixes are valid for any particular insn
616 but we needn't care, the insn will fault if it's invalid.
617 The result is a pointer to the first opcode byte,
618 or NULL if we run off the end of the buffer. */
621 i386_skip_prefixes (gdb_byte
*insn
, size_t max_len
)
623 gdb_byte
*end
= insn
+ max_len
;
629 case DATA_PREFIX_OPCODE
:
630 case ADDR_PREFIX_OPCODE
:
631 case CS_PREFIX_OPCODE
:
632 case DS_PREFIX_OPCODE
:
633 case ES_PREFIX_OPCODE
:
634 case FS_PREFIX_OPCODE
:
635 case GS_PREFIX_OPCODE
:
636 case SS_PREFIX_OPCODE
:
637 case LOCK_PREFIX_OPCODE
:
638 case REPE_PREFIX_OPCODE
:
639 case REPNE_PREFIX_OPCODE
:
651 i386_absolute_jmp_p (const gdb_byte
*insn
)
653 /* jmp far (absolute address in operand). */
659 /* jump near, absolute indirect (/4). */
660 if ((insn
[1] & 0x38) == 0x20)
663 /* jump far, absolute indirect (/5). */
664 if ((insn
[1] & 0x38) == 0x28)
671 /* Return non-zero if INSN is a jump, zero otherwise. */
674 i386_jmp_p (const gdb_byte
*insn
)
676 /* jump short, relative. */
680 /* jump near, relative. */
684 return i386_absolute_jmp_p (insn
);
688 i386_absolute_call_p (const gdb_byte
*insn
)
690 /* call far, absolute. */
696 /* Call near, absolute indirect (/2). */
697 if ((insn
[1] & 0x38) == 0x10)
700 /* Call far, absolute indirect (/3). */
701 if ((insn
[1] & 0x38) == 0x18)
709 i386_ret_p (const gdb_byte
*insn
)
713 case 0xc2: /* ret near, pop N bytes. */
714 case 0xc3: /* ret near */
715 case 0xca: /* ret far, pop N bytes. */
716 case 0xcb: /* ret far */
717 case 0xcf: /* iret */
726 i386_call_p (const gdb_byte
*insn
)
728 if (i386_absolute_call_p (insn
))
731 /* call near, relative. */
738 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
739 length in bytes. Otherwise, return zero. */
742 i386_syscall_p (const gdb_byte
*insn
, int *lengthp
)
744 /* Is it 'int $0x80'? */
745 if ((insn
[0] == 0xcd && insn
[1] == 0x80)
746 /* Or is it 'sysenter'? */
747 || (insn
[0] == 0x0f && insn
[1] == 0x34)
748 /* Or is it 'syscall'? */
749 || (insn
[0] == 0x0f && insn
[1] == 0x05))
758 /* The gdbarch insn_is_call method. */
761 i386_insn_is_call (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
763 gdb_byte buf
[I386_MAX_INSN_LEN
], *insn
;
765 read_code (addr
, buf
, I386_MAX_INSN_LEN
);
766 insn
= i386_skip_prefixes (buf
, I386_MAX_INSN_LEN
);
768 return i386_call_p (insn
);
771 /* The gdbarch insn_is_ret method. */
774 i386_insn_is_ret (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
776 gdb_byte buf
[I386_MAX_INSN_LEN
], *insn
;
778 read_code (addr
, buf
, I386_MAX_INSN_LEN
);
779 insn
= i386_skip_prefixes (buf
, I386_MAX_INSN_LEN
);
781 return i386_ret_p (insn
);
784 /* The gdbarch insn_is_jump method. */
787 i386_insn_is_jump (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
789 gdb_byte buf
[I386_MAX_INSN_LEN
], *insn
;
791 read_code (addr
, buf
, I386_MAX_INSN_LEN
);
792 insn
= i386_skip_prefixes (buf
, I386_MAX_INSN_LEN
);
794 return i386_jmp_p (insn
);
797 /* Some kernels may run one past a syscall insn, so we have to cope. */
799 struct displaced_step_closure
*
800 i386_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
801 CORE_ADDR from
, CORE_ADDR to
,
802 struct regcache
*regs
)
804 size_t len
= gdbarch_max_insn_length (gdbarch
);
805 gdb_byte
*buf
= (gdb_byte
*) xmalloc (len
);
807 read_memory (from
, buf
, len
);
809 /* GDB may get control back after the insn after the syscall.
810 Presumably this is a kernel bug.
811 If this is a syscall, make sure there's a nop afterwards. */
816 insn
= i386_skip_prefixes (buf
, len
);
817 if (insn
!= NULL
&& i386_syscall_p (insn
, &syscall_length
))
818 insn
[syscall_length
] = NOP_OPCODE
;
821 write_memory (to
, buf
, len
);
825 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
826 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
827 displaced_step_dump_bytes (gdb_stdlog
, buf
, len
);
830 return (struct displaced_step_closure
*) buf
;
833 /* Fix up the state of registers and memory after having single-stepped
834 a displaced instruction. */
837 i386_displaced_step_fixup (struct gdbarch
*gdbarch
,
838 struct displaced_step_closure
*closure
,
839 CORE_ADDR from
, CORE_ADDR to
,
840 struct regcache
*regs
)
842 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
844 /* The offset we applied to the instruction's address.
845 This could well be negative (when viewed as a signed 32-bit
846 value), but ULONGEST won't reflect that, so take care when
848 ULONGEST insn_offset
= to
- from
;
850 /* Our closure is a copy of the instruction. */
851 gdb_byte
*insn
= (gdb_byte
*) closure
;
852 /* The start of the insn, needed in case we see some prefixes. */
853 gdb_byte
*insn_start
= insn
;
856 fprintf_unfiltered (gdb_stdlog
,
857 "displaced: fixup (%s, %s), "
858 "insn = 0x%02x 0x%02x ...\n",
859 paddress (gdbarch
, from
), paddress (gdbarch
, to
),
862 /* The list of issues to contend with here is taken from
863 resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20.
864 Yay for Free Software! */
866 /* Relocate the %eip, if necessary. */
868 /* The instruction recognizers we use assume any leading prefixes
869 have been skipped. */
871 /* This is the size of the buffer in closure. */
872 size_t max_insn_len
= gdbarch_max_insn_length (gdbarch
);
873 gdb_byte
*opcode
= i386_skip_prefixes (insn
, max_insn_len
);
874 /* If there are too many prefixes, just ignore the insn.
875 It will fault when run. */
880 /* Except in the case of absolute or indirect jump or call
881 instructions, or a return instruction, the new eip is relative to
882 the displaced instruction; make it relative. Well, signal
883 handler returns don't need relocation either, but we use the
884 value of %eip to recognize those; see below. */
885 if (! i386_absolute_jmp_p (insn
)
886 && ! i386_absolute_call_p (insn
)
887 && ! i386_ret_p (insn
))
892 regcache_cooked_read_unsigned (regs
, I386_EIP_REGNUM
, &orig_eip
);
894 /* A signal trampoline system call changes the %eip, resuming
895 execution of the main program after the signal handler has
896 returned. That makes them like 'return' instructions; we
897 shouldn't relocate %eip.
899 But most system calls don't, and we do need to relocate %eip.
901 Our heuristic for distinguishing these cases: if stepping
902 over the system call instruction left control directly after
903 the instruction, the we relocate --- control almost certainly
904 doesn't belong in the displaced copy. Otherwise, we assume
905 the instruction has put control where it belongs, and leave
906 it unrelocated. Goodness help us if there are PC-relative
908 if (i386_syscall_p (insn
, &insn_len
)
909 && orig_eip
!= to
+ (insn
- insn_start
) + insn_len
910 /* GDB can get control back after the insn after the syscall.
911 Presumably this is a kernel bug.
912 i386_displaced_step_copy_insn ensures its a nop,
913 we add one to the length for it. */
914 && orig_eip
!= to
+ (insn
- insn_start
) + insn_len
+ 1)
917 fprintf_unfiltered (gdb_stdlog
,
918 "displaced: syscall changed %%eip; "
923 ULONGEST eip
= (orig_eip
- insn_offset
) & 0xffffffffUL
;
925 /* If we just stepped over a breakpoint insn, we don't backup
926 the pc on purpose; this is to match behaviour without
929 regcache_cooked_write_unsigned (regs
, I386_EIP_REGNUM
, eip
);
932 fprintf_unfiltered (gdb_stdlog
,
934 "relocated %%eip from %s to %s\n",
935 paddress (gdbarch
, orig_eip
),
936 paddress (gdbarch
, eip
));
940 /* If the instruction was PUSHFL, then the TF bit will be set in the
941 pushed value, and should be cleared. We'll leave this for later,
942 since GDB already messes up the TF flag when stepping over a
945 /* If the instruction was a call, the return address now atop the
946 stack is the address following the copied instruction. We need
947 to make it the address following the original instruction. */
948 if (i386_call_p (insn
))
952 const ULONGEST retaddr_len
= 4;
954 regcache_cooked_read_unsigned (regs
, I386_ESP_REGNUM
, &esp
);
955 retaddr
= read_memory_unsigned_integer (esp
, retaddr_len
, byte_order
);
956 retaddr
= (retaddr
- insn_offset
) & 0xffffffffUL
;
957 write_memory_unsigned_integer (esp
, retaddr_len
, byte_order
, retaddr
);
960 fprintf_unfiltered (gdb_stdlog
,
961 "displaced: relocated return addr at %s to %s\n",
962 paddress (gdbarch
, esp
),
963 paddress (gdbarch
, retaddr
));
968 append_insns (CORE_ADDR
*to
, ULONGEST len
, const gdb_byte
*buf
)
970 target_write_memory (*to
, buf
, len
);
975 i386_relocate_instruction (struct gdbarch
*gdbarch
,
976 CORE_ADDR
*to
, CORE_ADDR oldloc
)
978 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
979 gdb_byte buf
[I386_MAX_INSN_LEN
];
980 int offset
= 0, rel32
, newrel
;
982 gdb_byte
*insn
= buf
;
984 read_memory (oldloc
, buf
, I386_MAX_INSN_LEN
);
986 insn_length
= gdb_buffered_insn_length (gdbarch
, insn
,
987 I386_MAX_INSN_LEN
, oldloc
);
989 /* Get past the prefixes. */
990 insn
= i386_skip_prefixes (insn
, I386_MAX_INSN_LEN
);
992 /* Adjust calls with 32-bit relative addresses as push/jump, with
993 the address pushed being the location where the original call in
994 the user program would return to. */
997 gdb_byte push_buf
[16];
998 unsigned int ret_addr
;
1000 /* Where "ret" in the original code will return to. */
1001 ret_addr
= oldloc
+ insn_length
;
1002 push_buf
[0] = 0x68; /* pushq $... */
1003 store_unsigned_integer (&push_buf
[1], 4, byte_order
, ret_addr
);
1004 /* Push the push. */
1005 append_insns (to
, 5, push_buf
);
1007 /* Convert the relative call to a relative jump. */
1010 /* Adjust the destination offset. */
1011 rel32
= extract_signed_integer (insn
+ 1, 4, byte_order
);
1012 newrel
= (oldloc
- *to
) + rel32
;
1013 store_signed_integer (insn
+ 1, 4, byte_order
, newrel
);
1015 if (debug_displaced
)
1016 fprintf_unfiltered (gdb_stdlog
,
1017 "Adjusted insn rel32=%s at %s to"
1018 " rel32=%s at %s\n",
1019 hex_string (rel32
), paddress (gdbarch
, oldloc
),
1020 hex_string (newrel
), paddress (gdbarch
, *to
));
1022 /* Write the adjusted jump into its displaced location. */
1023 append_insns (to
, 5, insn
);
1027 /* Adjust jumps with 32-bit relative addresses. Calls are already
1029 if (insn
[0] == 0xe9)
1031 /* Adjust conditional jumps. */
1032 else if (insn
[0] == 0x0f && (insn
[1] & 0xf0) == 0x80)
1037 rel32
= extract_signed_integer (insn
+ offset
, 4, byte_order
);
1038 newrel
= (oldloc
- *to
) + rel32
;
1039 store_signed_integer (insn
+ offset
, 4, byte_order
, newrel
);
1040 if (debug_displaced
)
1041 fprintf_unfiltered (gdb_stdlog
,
1042 "Adjusted insn rel32=%s at %s to"
1043 " rel32=%s at %s\n",
1044 hex_string (rel32
), paddress (gdbarch
, oldloc
),
1045 hex_string (newrel
), paddress (gdbarch
, *to
));
1048 /* Write the adjusted instructions into their displaced
1050 append_insns (to
, insn_length
, buf
);
1054 #ifdef I386_REGNO_TO_SYMMETRY
1055 #error "The Sequent Symmetry is no longer supported."
1058 /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi
1059 and %esp "belong" to the calling function. Therefore these
1060 registers should be saved if they're going to be modified. */
1062 /* The maximum number of saved registers. This should include all
1063 registers mentioned above, and %eip. */
1064 #define I386_NUM_SAVED_REGS I386_NUM_GREGS
1066 struct i386_frame_cache
1074 /* Saved registers. */
1075 CORE_ADDR saved_regs
[I386_NUM_SAVED_REGS
];
1080 /* Stack space reserved for local variables. */
1084 /* Allocate and initialize a frame cache. */
1086 static struct i386_frame_cache
*
1087 i386_alloc_frame_cache (void)
1089 struct i386_frame_cache
*cache
;
1092 cache
= FRAME_OBSTACK_ZALLOC (struct i386_frame_cache
);
1097 cache
->sp_offset
= -4;
1100 /* Saved registers. We initialize these to -1 since zero is a valid
1101 offset (that's where %ebp is supposed to be stored). */
1102 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
1103 cache
->saved_regs
[i
] = -1;
1104 cache
->saved_sp
= 0;
1105 cache
->saved_sp_reg
= -1;
1106 cache
->pc_in_eax
= 0;
1108 /* Frameless until proven otherwise. */
1114 /* If the instruction at PC is a jump, return the address of its
1115 target. Otherwise, return PC. */
1118 i386_follow_jump (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1120 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1125 if (target_read_code (pc
, &op
, 1))
1132 op
= read_code_unsigned_integer (pc
+ 1, 1, byte_order
);
1138 /* Relative jump: if data16 == 0, disp32, else disp16. */
1141 delta
= read_memory_integer (pc
+ 2, 2, byte_order
);
1143 /* Include the size of the jmp instruction (including the
1149 delta
= read_memory_integer (pc
+ 1, 4, byte_order
);
1151 /* Include the size of the jmp instruction. */
1156 /* Relative jump, disp8 (ignore data16). */
1157 delta
= read_memory_integer (pc
+ data16
+ 1, 1, byte_order
);
1159 delta
+= data16
+ 2;
1166 /* Check whether PC points at a prologue for a function returning a
1167 structure or union. If so, it updates CACHE and returns the
1168 address of the first instruction after the code sequence that
1169 removes the "hidden" argument from the stack or CURRENT_PC,
1170 whichever is smaller. Otherwise, return PC. */
1173 i386_analyze_struct_return (CORE_ADDR pc
, CORE_ADDR current_pc
,
1174 struct i386_frame_cache
*cache
)
1176 /* Functions that return a structure or union start with:
1179 xchgl %eax, (%esp) 0x87 0x04 0x24
1180 or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00
1182 (the System V compiler puts out the second `xchg' instruction,
1183 and the assembler doesn't try to optimize it, so the 'sib' form
1184 gets generated). This sequence is used to get the address of the
1185 return buffer for a function that returns a structure. */
1186 static gdb_byte proto1
[3] = { 0x87, 0x04, 0x24 };
1187 static gdb_byte proto2
[4] = { 0x87, 0x44, 0x24, 0x00 };
1191 if (current_pc
<= pc
)
1194 if (target_read_code (pc
, &op
, 1))
1197 if (op
!= 0x58) /* popl %eax */
1200 if (target_read_code (pc
+ 1, buf
, 4))
1203 if (memcmp (buf
, proto1
, 3) != 0 && memcmp (buf
, proto2
, 4) != 0)
1206 if (current_pc
== pc
)
1208 cache
->sp_offset
+= 4;
1212 if (current_pc
== pc
+ 1)
1214 cache
->pc_in_eax
= 1;
1218 if (buf
[1] == proto1
[1])
1225 i386_skip_probe (CORE_ADDR pc
)
1227 /* A function may start with
1241 if (target_read_code (pc
, &op
, 1))
1244 if (op
== 0x68 || op
== 0x6a)
1248 /* Skip past the `pushl' instruction; it has either a one-byte or a
1249 four-byte operand, depending on the opcode. */
1255 /* Read the following 8 bytes, which should be `call _probe' (6
1256 bytes) followed by `addl $4,%esp' (2 bytes). */
1257 read_memory (pc
+ delta
, buf
, sizeof (buf
));
1258 if (buf
[0] == 0xe8 && buf
[6] == 0xc4 && buf
[7] == 0x4)
1259 pc
+= delta
+ sizeof (buf
);
1265 /* GCC 4.1 and later, can put code in the prologue to realign the
1266 stack pointer. Check whether PC points to such code, and update
1267 CACHE accordingly. Return the first instruction after the code
1268 sequence or CURRENT_PC, whichever is smaller. If we don't
1269 recognize the code, return PC. */
1272 i386_analyze_stack_align (CORE_ADDR pc
, CORE_ADDR current_pc
,
1273 struct i386_frame_cache
*cache
)
1275 /* There are 2 code sequences to re-align stack before the frame
1278 1. Use a caller-saved saved register:
1284 2. Use a callee-saved saved register:
1291 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
1293 0x83 0xe4 0xf0 andl $-16, %esp
1294 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
1299 int offset
, offset_and
;
1300 static int regnums
[8] = {
1301 I386_EAX_REGNUM
, /* %eax */
1302 I386_ECX_REGNUM
, /* %ecx */
1303 I386_EDX_REGNUM
, /* %edx */
1304 I386_EBX_REGNUM
, /* %ebx */
1305 I386_ESP_REGNUM
, /* %esp */
1306 I386_EBP_REGNUM
, /* %ebp */
1307 I386_ESI_REGNUM
, /* %esi */
1308 I386_EDI_REGNUM
/* %edi */
1311 if (target_read_code (pc
, buf
, sizeof buf
))
1314 /* Check caller-saved saved register. The first instruction has
1315 to be "leal 4(%esp), %reg". */
1316 if (buf
[0] == 0x8d && buf
[2] == 0x24 && buf
[3] == 0x4)
1318 /* MOD must be binary 10 and R/M must be binary 100. */
1319 if ((buf
[1] & 0xc7) != 0x44)
1322 /* REG has register number. */
1323 reg
= (buf
[1] >> 3) & 7;
1328 /* Check callee-saved saved register. The first instruction
1329 has to be "pushl %reg". */
1330 if ((buf
[0] & 0xf8) != 0x50)
1336 /* The next instruction has to be "leal 8(%esp), %reg". */
1337 if (buf
[1] != 0x8d || buf
[3] != 0x24 || buf
[4] != 0x8)
1340 /* MOD must be binary 10 and R/M must be binary 100. */
1341 if ((buf
[2] & 0xc7) != 0x44)
1344 /* REG has register number. Registers in pushl and leal have to
1346 if (reg
!= ((buf
[2] >> 3) & 7))
1352 /* Rigister can't be %esp nor %ebp. */
1353 if (reg
== 4 || reg
== 5)
1356 /* The next instruction has to be "andl $-XXX, %esp". */
1357 if (buf
[offset
+ 1] != 0xe4
1358 || (buf
[offset
] != 0x81 && buf
[offset
] != 0x83))
1361 offset_and
= offset
;
1362 offset
+= buf
[offset
] == 0x81 ? 6 : 3;
1364 /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is
1365 0xfc. REG must be binary 110 and MOD must be binary 01. */
1366 if (buf
[offset
] != 0xff
1367 || buf
[offset
+ 2] != 0xfc
1368 || (buf
[offset
+ 1] & 0xf8) != 0x70)
1371 /* R/M has register. Registers in leal and pushl have to be the
1373 if (reg
!= (buf
[offset
+ 1] & 7))
1376 if (current_pc
> pc
+ offset_and
)
1377 cache
->saved_sp_reg
= regnums
[reg
];
1379 return std::min (pc
+ offset
+ 3, current_pc
);
1382 /* Maximum instruction length we need to handle. */
1383 #define I386_MAX_MATCHED_INSN_LEN 6
1385 /* Instruction description. */
1389 gdb_byte insn
[I386_MAX_MATCHED_INSN_LEN
];
1390 gdb_byte mask
[I386_MAX_MATCHED_INSN_LEN
];
1393 /* Return whether instruction at PC matches PATTERN. */
1396 i386_match_pattern (CORE_ADDR pc
, struct i386_insn pattern
)
1400 if (target_read_code (pc
, &op
, 1))
1403 if ((op
& pattern
.mask
[0]) == pattern
.insn
[0])
1405 gdb_byte buf
[I386_MAX_MATCHED_INSN_LEN
- 1];
1406 int insn_matched
= 1;
1409 gdb_assert (pattern
.len
> 1);
1410 gdb_assert (pattern
.len
<= I386_MAX_MATCHED_INSN_LEN
);
1412 if (target_read_code (pc
+ 1, buf
, pattern
.len
- 1))
1415 for (i
= 1; i
< pattern
.len
; i
++)
1417 if ((buf
[i
- 1] & pattern
.mask
[i
]) != pattern
.insn
[i
])
1420 return insn_matched
;
1425 /* Search for the instruction at PC in the list INSN_PATTERNS. Return
1426 the first instruction description that matches. Otherwise, return
1429 static struct i386_insn
*
1430 i386_match_insn (CORE_ADDR pc
, struct i386_insn
*insn_patterns
)
1432 struct i386_insn
*pattern
;
1434 for (pattern
= insn_patterns
; pattern
->len
> 0; pattern
++)
1436 if (i386_match_pattern (pc
, *pattern
))
1443 /* Return whether PC points inside a sequence of instructions that
1444 matches INSN_PATTERNS. */
1447 i386_match_insn_block (CORE_ADDR pc
, struct i386_insn
*insn_patterns
)
1449 CORE_ADDR current_pc
;
1451 struct i386_insn
*insn
;
1453 insn
= i386_match_insn (pc
, insn_patterns
);
1458 ix
= insn
- insn_patterns
;
1459 for (i
= ix
- 1; i
>= 0; i
--)
1461 current_pc
-= insn_patterns
[i
].len
;
1463 if (!i386_match_pattern (current_pc
, insn_patterns
[i
]))
1467 current_pc
= pc
+ insn
->len
;
1468 for (insn
= insn_patterns
+ ix
+ 1; insn
->len
> 0; insn
++)
1470 if (!i386_match_pattern (current_pc
, *insn
))
1473 current_pc
+= insn
->len
;
1479 /* Some special instructions that might be migrated by GCC into the
1480 part of the prologue that sets up the new stack frame. Because the
1481 stack frame hasn't been setup yet, no registers have been saved
1482 yet, and only the scratch registers %eax, %ecx and %edx can be
1485 struct i386_insn i386_frame_setup_skip_insns
[] =
1487 /* Check for `movb imm8, r' and `movl imm32, r'.
1489 ??? Should we handle 16-bit operand-sizes here? */
1491 /* `movb imm8, %al' and `movb imm8, %ah' */
1492 /* `movb imm8, %cl' and `movb imm8, %ch' */
1493 { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } },
1494 /* `movb imm8, %dl' and `movb imm8, %dh' */
1495 { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } },
1496 /* `movl imm32, %eax' and `movl imm32, %ecx' */
1497 { 5, { 0xb8 }, { 0xfe } },
1498 /* `movl imm32, %edx' */
1499 { 5, { 0xba }, { 0xff } },
1501 /* Check for `mov imm32, r32'. Note that there is an alternative
1502 encoding for `mov m32, %eax'.
1504 ??? Should we handle SIB adressing here?
1505 ??? Should we handle 16-bit operand-sizes here? */
1507 /* `movl m32, %eax' */
1508 { 5, { 0xa1 }, { 0xff } },
1509 /* `movl m32, %eax' and `mov; m32, %ecx' */
1510 { 6, { 0x89, 0x05 }, {0xff, 0xf7 } },
1511 /* `movl m32, %edx' */
1512 { 6, { 0x89, 0x15 }, {0xff, 0xff } },
1514 /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'.
1515 Because of the symmetry, there are actually two ways to encode
1516 these instructions; opcode bytes 0x29 and 0x2b for `subl' and
1517 opcode bytes 0x31 and 0x33 for `xorl'. */
1519 /* `subl %eax, %eax' */
1520 { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } },
1521 /* `subl %ecx, %ecx' */
1522 { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } },
1523 /* `subl %edx, %edx' */
1524 { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } },
1525 /* `xorl %eax, %eax' */
1526 { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } },
1527 /* `xorl %ecx, %ecx' */
1528 { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } },
1529 /* `xorl %edx, %edx' */
1530 { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } },
1535 /* Check whether PC points to a no-op instruction. */
1537 i386_skip_noop (CORE_ADDR pc
)
1542 if (target_read_code (pc
, &op
, 1))
1548 /* Ignore `nop' instruction. */
1552 if (target_read_code (pc
, &op
, 1))
1556 /* Ignore no-op instruction `mov %edi, %edi'.
1557 Microsoft system dlls often start with
1558 a `mov %edi,%edi' instruction.
1559 The 5 bytes before the function start are
1560 filled with `nop' instructions.
1561 This pattern can be used for hot-patching:
1562 The `mov %edi, %edi' instruction can be replaced by a
1563 near jump to the location of the 5 `nop' instructions
1564 which can be replaced by a 32-bit jump to anywhere
1565 in the 32-bit address space. */
1567 else if (op
== 0x8b)
1569 if (target_read_code (pc
+ 1, &op
, 1))
1575 if (target_read_code (pc
, &op
, 1))
1585 /* Check whether PC points at a code that sets up a new stack frame.
1586 If so, it updates CACHE and returns the address of the first
1587 instruction after the sequence that sets up the frame or LIMIT,
1588 whichever is smaller. If we don't recognize the code, return PC. */
1591 i386_analyze_frame_setup (struct gdbarch
*gdbarch
,
1592 CORE_ADDR pc
, CORE_ADDR limit
,
1593 struct i386_frame_cache
*cache
)
1595 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1596 struct i386_insn
*insn
;
1603 if (target_read_code (pc
, &op
, 1))
1606 if (op
== 0x55) /* pushl %ebp */
1608 /* Take into account that we've executed the `pushl %ebp' that
1609 starts this instruction sequence. */
1610 cache
->saved_regs
[I386_EBP_REGNUM
] = 0;
1611 cache
->sp_offset
+= 4;
1614 /* If that's all, return now. */
1618 /* Check for some special instructions that might be migrated by
1619 GCC into the prologue and skip them. At this point in the
1620 prologue, code should only touch the scratch registers %eax,
1621 %ecx and %edx, so while the number of posibilities is sheer,
1624 Make sure we only skip these instructions if we later see the
1625 `movl %esp, %ebp' that actually sets up the frame. */
1626 while (pc
+ skip
< limit
)
1628 insn
= i386_match_insn (pc
+ skip
, i386_frame_setup_skip_insns
);
1635 /* If that's all, return now. */
1636 if (limit
<= pc
+ skip
)
1639 if (target_read_code (pc
+ skip
, &op
, 1))
1642 /* The i386 prologue looks like
1648 and a different prologue can be generated for atom.
1652 lea -0x10(%esp),%esp
1654 We handle both of them here. */
1658 /* Check for `movl %esp, %ebp' -- can be written in two ways. */
1660 if (read_code_unsigned_integer (pc
+ skip
+ 1, 1, byte_order
)
1666 if (read_code_unsigned_integer (pc
+ skip
+ 1, 1, byte_order
)
1671 case 0x8d: /* Check for 'lea (%ebp), %ebp'. */
1672 if (read_code_unsigned_integer (pc
+ skip
+ 1, 2, byte_order
)
1681 /* OK, we actually have a frame. We just don't know how large
1682 it is yet. Set its size to zero. We'll adjust it if
1683 necessary. We also now commit to skipping the special
1684 instructions mentioned before. */
1687 /* If that's all, return now. */
1691 /* Check for stack adjustment
1697 NOTE: You can't subtract a 16-bit immediate from a 32-bit
1698 reg, so we don't have to worry about a data16 prefix. */
1699 if (target_read_code (pc
, &op
, 1))
1703 /* `subl' with 8-bit immediate. */
1704 if (read_code_unsigned_integer (pc
+ 1, 1, byte_order
) != 0xec)
1705 /* Some instruction starting with 0x83 other than `subl'. */
1708 /* `subl' with signed 8-bit immediate (though it wouldn't
1709 make sense to be negative). */
1710 cache
->locals
= read_code_integer (pc
+ 2, 1, byte_order
);
1713 else if (op
== 0x81)
1715 /* Maybe it is `subl' with a 32-bit immediate. */
1716 if (read_code_unsigned_integer (pc
+ 1, 1, byte_order
) != 0xec)
1717 /* Some instruction starting with 0x81 other than `subl'. */
1720 /* It is `subl' with a 32-bit immediate. */
1721 cache
->locals
= read_code_integer (pc
+ 2, 4, byte_order
);
1724 else if (op
== 0x8d)
1726 /* The ModR/M byte is 0x64. */
1727 if (read_code_unsigned_integer (pc
+ 1, 1, byte_order
) != 0x64)
1729 /* 'lea' with 8-bit displacement. */
1730 cache
->locals
= -1 * read_code_integer (pc
+ 3, 1, byte_order
);
1735 /* Some instruction other than `subl' nor 'lea'. */
1739 else if (op
== 0xc8) /* enter */
1741 cache
->locals
= read_code_unsigned_integer (pc
+ 1, 2, byte_order
);
1748 /* Check whether PC points at code that saves registers on the stack.
1749 If so, it updates CACHE and returns the address of the first
1750 instruction after the register saves or CURRENT_PC, whichever is
1751 smaller. Otherwise, return PC. */
1754 i386_analyze_register_saves (CORE_ADDR pc
, CORE_ADDR current_pc
,
1755 struct i386_frame_cache
*cache
)
1757 CORE_ADDR offset
= 0;
1761 if (cache
->locals
> 0)
1762 offset
-= cache
->locals
;
1763 for (i
= 0; i
< 8 && pc
< current_pc
; i
++)
1765 if (target_read_code (pc
, &op
, 1))
1767 if (op
< 0x50 || op
> 0x57)
1771 cache
->saved_regs
[op
- 0x50] = offset
;
1772 cache
->sp_offset
+= 4;
1779 /* Do a full analysis of the prologue at PC and update CACHE
1780 accordingly. Bail out early if CURRENT_PC is reached. Return the
1781 address where the analysis stopped.
1783 We handle these cases:
1785 The startup sequence can be at the start of the function, or the
1786 function can start with a branch to startup code at the end.
1788 %ebp can be set up with either the 'enter' instruction, or "pushl
1789 %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was
1790 once used in the System V compiler).
1792 Local space is allocated just below the saved %ebp by either the
1793 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a
1794 16-bit unsigned argument for space to allocate, and the 'addl'
1795 instruction could have either a signed byte, or 32-bit immediate.
1797 Next, the registers used by this function are pushed. With the
1798 System V compiler they will always be in the order: %edi, %esi,
1799 %ebx (and sometimes a harmless bug causes it to also save but not
1800 restore %eax); however, the code below is willing to see the pushes
1801 in any order, and will handle up to 8 of them.
1803 If the setup sequence is at the end of the function, then the next
1804 instruction will be a branch back to the start. */
1807 i386_analyze_prologue (struct gdbarch
*gdbarch
,
1808 CORE_ADDR pc
, CORE_ADDR current_pc
,
1809 struct i386_frame_cache
*cache
)
1811 pc
= i386_skip_noop (pc
);
1812 pc
= i386_follow_jump (gdbarch
, pc
);
1813 pc
= i386_analyze_struct_return (pc
, current_pc
, cache
);
1814 pc
= i386_skip_probe (pc
);
1815 pc
= i386_analyze_stack_align (pc
, current_pc
, cache
);
1816 pc
= i386_analyze_frame_setup (gdbarch
, pc
, current_pc
, cache
);
1817 return i386_analyze_register_saves (pc
, current_pc
, cache
);
1820 /* Return PC of first real instruction. */
1823 i386_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
1825 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1827 static gdb_byte pic_pat
[6] =
1829 0xe8, 0, 0, 0, 0, /* call 0x0 */
1830 0x5b, /* popl %ebx */
1832 struct i386_frame_cache cache
;
1836 CORE_ADDR func_addr
;
1838 if (find_pc_partial_function (start_pc
, NULL
, &func_addr
, NULL
))
1840 CORE_ADDR post_prologue_pc
1841 = skip_prologue_using_sal (gdbarch
, func_addr
);
1842 struct compunit_symtab
*cust
= find_pc_compunit_symtab (func_addr
);
1844 /* Clang always emits a line note before the prologue and another
1845 one after. We trust clang to emit usable line notes. */
1846 if (post_prologue_pc
1848 && COMPUNIT_PRODUCER (cust
) != NULL
1849 && startswith (COMPUNIT_PRODUCER (cust
), "clang ")))
1850 return std::max (start_pc
, post_prologue_pc
);
1854 pc
= i386_analyze_prologue (gdbarch
, start_pc
, 0xffffffff, &cache
);
1855 if (cache
.locals
< 0)
1858 /* Found valid frame setup. */
1860 /* The native cc on SVR4 in -K PIC mode inserts the following code
1861 to get the address of the global offset table (GOT) into register
1866 movl %ebx,x(%ebp) (optional)
1869 This code is with the rest of the prologue (at the end of the
1870 function), so we have to skip it to get to the first real
1871 instruction at the start of the function. */
1873 for (i
= 0; i
< 6; i
++)
1875 if (target_read_code (pc
+ i
, &op
, 1))
1878 if (pic_pat
[i
] != op
)
1885 if (target_read_code (pc
+ delta
, &op
, 1))
1888 if (op
== 0x89) /* movl %ebx, x(%ebp) */
1890 op
= read_code_unsigned_integer (pc
+ delta
+ 1, 1, byte_order
);
1892 if (op
== 0x5d) /* One byte offset from %ebp. */
1894 else if (op
== 0x9d) /* Four byte offset from %ebp. */
1896 else /* Unexpected instruction. */
1899 if (target_read_code (pc
+ delta
, &op
, 1))
1904 if (delta
> 0 && op
== 0x81
1905 && read_code_unsigned_integer (pc
+ delta
+ 1, 1, byte_order
)
1912 /* If the function starts with a branch (to startup code at the end)
1913 the last instruction should bring us back to the first
1914 instruction of the real code. */
1915 if (i386_follow_jump (gdbarch
, start_pc
) != start_pc
)
1916 pc
= i386_follow_jump (gdbarch
, pc
);
1921 /* Check that the code pointed to by PC corresponds to a call to
1922 __main, skip it if so. Return PC otherwise. */
1925 i386_skip_main_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1927 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1930 if (target_read_code (pc
, &op
, 1))
1936 if (target_read_code (pc
+ 1, buf
, sizeof buf
) == 0)
1938 /* Make sure address is computed correctly as a 32bit
1939 integer even if CORE_ADDR is 64 bit wide. */
1940 struct bound_minimal_symbol s
;
1941 CORE_ADDR call_dest
;
1943 call_dest
= pc
+ 5 + extract_signed_integer (buf
, 4, byte_order
);
1944 call_dest
= call_dest
& 0xffffffffU
;
1945 s
= lookup_minimal_symbol_by_pc (call_dest
);
1946 if (s
.minsym
!= NULL
1947 && MSYMBOL_LINKAGE_NAME (s
.minsym
) != NULL
1948 && strcmp (MSYMBOL_LINKAGE_NAME (s
.minsym
), "__main") == 0)
1956 /* This function is 64-bit safe. */
1959 i386_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1963 frame_unwind_register (next_frame
, gdbarch_pc_regnum (gdbarch
), buf
);
1964 return extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
1968 /* Normal frames. */
1971 i386_frame_cache_1 (struct frame_info
*this_frame
,
1972 struct i386_frame_cache
*cache
)
1974 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1975 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1979 cache
->pc
= get_frame_func (this_frame
);
1981 /* In principle, for normal frames, %ebp holds the frame pointer,
1982 which holds the base address for the current stack frame.
1983 However, for functions that don't need it, the frame pointer is
1984 optional. For these "frameless" functions the frame pointer is
1985 actually the frame pointer of the calling frame. Signal
1986 trampolines are just a special case of a "frameless" function.
1987 They (usually) share their frame pointer with the frame that was
1988 in progress when the signal occurred. */
1990 get_frame_register (this_frame
, I386_EBP_REGNUM
, buf
);
1991 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
);
1992 if (cache
->base
== 0)
1998 /* For normal frames, %eip is stored at 4(%ebp). */
1999 cache
->saved_regs
[I386_EIP_REGNUM
] = 4;
2002 i386_analyze_prologue (gdbarch
, cache
->pc
, get_frame_pc (this_frame
),
2005 if (cache
->locals
< 0)
2007 /* We didn't find a valid frame, which means that CACHE->base
2008 currently holds the frame pointer for our calling frame. If
2009 we're at the start of a function, or somewhere half-way its
2010 prologue, the function's frame probably hasn't been fully
2011 setup yet. Try to reconstruct the base address for the stack
2012 frame by looking at the stack pointer. For truly "frameless"
2013 functions this might work too. */
2015 if (cache
->saved_sp_reg
!= -1)
2017 /* Saved stack pointer has been saved. */
2018 get_frame_register (this_frame
, cache
->saved_sp_reg
, buf
);
2019 cache
->saved_sp
= extract_unsigned_integer (buf
, 4, byte_order
);
2021 /* We're halfway aligning the stack. */
2022 cache
->base
= ((cache
->saved_sp
- 4) & 0xfffffff0) - 4;
2023 cache
->saved_regs
[I386_EIP_REGNUM
] = cache
->saved_sp
- 4;
2025 /* This will be added back below. */
2026 cache
->saved_regs
[I386_EIP_REGNUM
] -= cache
->base
;
2028 else if (cache
->pc
!= 0
2029 || target_read_code (get_frame_pc (this_frame
), buf
, 1))
2031 /* We're in a known function, but did not find a frame
2032 setup. Assume that the function does not use %ebp.
2033 Alternatively, we may have jumped to an invalid
2034 address; in that case there is definitely no new
2036 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
2037 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
)
2041 /* We're in an unknown function. We could not find the start
2042 of the function to analyze the prologue; our best option is
2043 to assume a typical frame layout with the caller's %ebp
2045 cache
->saved_regs
[I386_EBP_REGNUM
] = 0;
2048 if (cache
->saved_sp_reg
!= -1)
2050 /* Saved stack pointer has been saved (but the SAVED_SP_REG
2051 register may be unavailable). */
2052 if (cache
->saved_sp
== 0
2053 && deprecated_frame_register_read (this_frame
,
2054 cache
->saved_sp_reg
, buf
))
2055 cache
->saved_sp
= extract_unsigned_integer (buf
, 4, byte_order
);
2057 /* Now that we have the base address for the stack frame we can
2058 calculate the value of %esp in the calling frame. */
2059 else if (cache
->saved_sp
== 0)
2060 cache
->saved_sp
= cache
->base
+ 8;
2062 /* Adjust all the saved registers such that they contain addresses
2063 instead of offsets. */
2064 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
2065 if (cache
->saved_regs
[i
] != -1)
2066 cache
->saved_regs
[i
] += cache
->base
;
2071 static struct i386_frame_cache
*
2072 i386_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2074 struct i386_frame_cache
*cache
;
2077 return (struct i386_frame_cache
*) *this_cache
;
2079 cache
= i386_alloc_frame_cache ();
2080 *this_cache
= cache
;
2084 i386_frame_cache_1 (this_frame
, cache
);
2086 CATCH (ex
, RETURN_MASK_ERROR
)
2088 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
2089 throw_exception (ex
);
2097 i386_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2098 struct frame_id
*this_id
)
2100 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
2103 (*this_id
) = frame_id_build_unavailable_stack (cache
->pc
);
2104 else if (cache
->base
== 0)
2106 /* This marks the outermost frame. */
2110 /* See the end of i386_push_dummy_call. */
2111 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
2115 static enum unwind_stop_reason
2116 i386_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2119 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
2122 return UNWIND_UNAVAILABLE
;
2124 /* This marks the outermost frame. */
2125 if (cache
->base
== 0)
2126 return UNWIND_OUTERMOST
;
2128 return UNWIND_NO_REASON
;
2131 static struct value
*
2132 i386_frame_prev_register (struct frame_info
*this_frame
, void **this_cache
,
2135 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
2137 gdb_assert (regnum
>= 0);
2139 /* The System V ABI says that:
2141 "The flags register contains the system flags, such as the
2142 direction flag and the carry flag. The direction flag must be
2143 set to the forward (that is, zero) direction before entry and
2144 upon exit from a function. Other user flags have no specified
2145 role in the standard calling sequence and are not preserved."
2147 To guarantee the "upon exit" part of that statement we fake a
2148 saved flags register that has its direction flag cleared.
2150 Note that GCC doesn't seem to rely on the fact that the direction
2151 flag is cleared after a function return; it always explicitly
2152 clears the flag before operations where it matters.
2154 FIXME: kettenis/20030316: I'm not quite sure whether this is the
2155 right thing to do. The way we fake the flags register here makes
2156 it impossible to change it. */
2158 if (regnum
== I386_EFLAGS_REGNUM
)
2162 val
= get_frame_register_unsigned (this_frame
, regnum
);
2164 return frame_unwind_got_constant (this_frame
, regnum
, val
);
2167 if (regnum
== I386_EIP_REGNUM
&& cache
->pc_in_eax
)
2168 return frame_unwind_got_register (this_frame
, regnum
, I386_EAX_REGNUM
);
2170 if (regnum
== I386_ESP_REGNUM
2171 && (cache
->saved_sp
!= 0 || cache
->saved_sp_reg
!= -1))
2173 /* If the SP has been saved, but we don't know where, then this
2174 means that SAVED_SP_REG register was found unavailable back
2175 when we built the cache. */
2176 if (cache
->saved_sp
== 0)
2177 return frame_unwind_got_register (this_frame
, regnum
,
2178 cache
->saved_sp_reg
);
2180 return frame_unwind_got_constant (this_frame
, regnum
,
2184 if (regnum
< I386_NUM_SAVED_REGS
&& cache
->saved_regs
[regnum
] != -1)
2185 return frame_unwind_got_memory (this_frame
, regnum
,
2186 cache
->saved_regs
[regnum
]);
2188 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
2191 static const struct frame_unwind i386_frame_unwind
=
2194 i386_frame_unwind_stop_reason
,
2196 i386_frame_prev_register
,
2198 default_frame_sniffer
2201 /* Normal frames, but in a function epilogue. */
2203 /* Implement the stack_frame_destroyed_p gdbarch method.
2205 The epilogue is defined here as the 'ret' instruction, which will
2206 follow any instruction such as 'leave' or 'pop %ebp' that destroys
2207 the function's stack frame. */
2210 i386_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2213 struct compunit_symtab
*cust
;
2215 cust
= find_pc_compunit_symtab (pc
);
2216 if (cust
!= NULL
&& COMPUNIT_EPILOGUE_UNWIND_VALID (cust
))
2219 if (target_read_memory (pc
, &insn
, 1))
2220 return 0; /* Can't read memory at pc. */
2222 if (insn
!= 0xc3) /* 'ret' instruction. */
2229 i386_epilogue_frame_sniffer (const struct frame_unwind
*self
,
2230 struct frame_info
*this_frame
,
2231 void **this_prologue_cache
)
2233 if (frame_relative_level (this_frame
) == 0)
2234 return i386_stack_frame_destroyed_p (get_frame_arch (this_frame
),
2235 get_frame_pc (this_frame
));
2240 static struct i386_frame_cache
*
2241 i386_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2243 struct i386_frame_cache
*cache
;
2247 return (struct i386_frame_cache
*) *this_cache
;
2249 cache
= i386_alloc_frame_cache ();
2250 *this_cache
= cache
;
2254 cache
->pc
= get_frame_func (this_frame
);
2256 /* At this point the stack looks as if we just entered the
2257 function, with the return address at the top of the
2259 sp
= get_frame_register_unsigned (this_frame
, I386_ESP_REGNUM
);
2260 cache
->base
= sp
+ cache
->sp_offset
;
2261 cache
->saved_sp
= cache
->base
+ 8;
2262 cache
->saved_regs
[I386_EIP_REGNUM
] = cache
->base
+ 4;
2266 CATCH (ex
, RETURN_MASK_ERROR
)
2268 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
2269 throw_exception (ex
);
2276 static enum unwind_stop_reason
2277 i386_epilogue_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2280 struct i386_frame_cache
*cache
=
2281 i386_epilogue_frame_cache (this_frame
, this_cache
);
2284 return UNWIND_UNAVAILABLE
;
2286 return UNWIND_NO_REASON
;
2290 i386_epilogue_frame_this_id (struct frame_info
*this_frame
,
2292 struct frame_id
*this_id
)
2294 struct i386_frame_cache
*cache
=
2295 i386_epilogue_frame_cache (this_frame
, this_cache
);
2298 (*this_id
) = frame_id_build_unavailable_stack (cache
->pc
);
2300 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
2303 static struct value
*
2304 i386_epilogue_frame_prev_register (struct frame_info
*this_frame
,
2305 void **this_cache
, int regnum
)
2307 /* Make sure we've initialized the cache. */
2308 i386_epilogue_frame_cache (this_frame
, this_cache
);
2310 return i386_frame_prev_register (this_frame
, this_cache
, regnum
);
2313 static const struct frame_unwind i386_epilogue_frame_unwind
=
2316 i386_epilogue_frame_unwind_stop_reason
,
2317 i386_epilogue_frame_this_id
,
2318 i386_epilogue_frame_prev_register
,
2320 i386_epilogue_frame_sniffer
2324 /* Stack-based trampolines. */
2326 /* These trampolines are used on cross x86 targets, when taking the
2327 address of a nested function. When executing these trampolines,
2328 no stack frame is set up, so we are in a similar situation as in
2329 epilogues and i386_epilogue_frame_this_id can be re-used. */
2331 /* Static chain passed in register. */
2333 struct i386_insn i386_tramp_chain_in_reg_insns
[] =
2335 /* `movl imm32, %eax' and `movl imm32, %ecx' */
2336 { 5, { 0xb8 }, { 0xfe } },
2339 { 5, { 0xe9 }, { 0xff } },
2344 /* Static chain passed on stack (when regparm=3). */
2346 struct i386_insn i386_tramp_chain_on_stack_insns
[] =
2349 { 5, { 0x68 }, { 0xff } },
2352 { 5, { 0xe9 }, { 0xff } },
2357 /* Return whether PC points inside a stack trampoline. */
2360 i386_in_stack_tramp_p (CORE_ADDR pc
)
2365 /* A stack trampoline is detected if no name is associated
2366 to the current pc and if it points inside a trampoline
2369 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
2373 if (target_read_memory (pc
, &insn
, 1))
2376 if (!i386_match_insn_block (pc
, i386_tramp_chain_in_reg_insns
)
2377 && !i386_match_insn_block (pc
, i386_tramp_chain_on_stack_insns
))
2384 i386_stack_tramp_frame_sniffer (const struct frame_unwind
*self
,
2385 struct frame_info
*this_frame
,
2388 if (frame_relative_level (this_frame
) == 0)
2389 return i386_in_stack_tramp_p (get_frame_pc (this_frame
));
2394 static const struct frame_unwind i386_stack_tramp_frame_unwind
=
2397 i386_epilogue_frame_unwind_stop_reason
,
2398 i386_epilogue_frame_this_id
,
2399 i386_epilogue_frame_prev_register
,
2401 i386_stack_tramp_frame_sniffer
2404 /* Generate a bytecode expression to get the value of the saved PC. */
2407 i386_gen_return_address (struct gdbarch
*gdbarch
,
2408 struct agent_expr
*ax
, struct axs_value
*value
,
2411 /* The following sequence assumes the traditional use of the base
2413 ax_reg (ax
, I386_EBP_REGNUM
);
2415 ax_simple (ax
, aop_add
);
2416 value
->type
= register_type (gdbarch
, I386_EIP_REGNUM
);
2417 value
->kind
= axs_lvalue_memory
;
2421 /* Signal trampolines. */
2423 static struct i386_frame_cache
*
2424 i386_sigtramp_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2426 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2427 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2428 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2429 struct i386_frame_cache
*cache
;
2434 return (struct i386_frame_cache
*) *this_cache
;
2436 cache
= i386_alloc_frame_cache ();
2440 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
2441 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
) - 4;
2443 addr
= tdep
->sigcontext_addr (this_frame
);
2444 if (tdep
->sc_reg_offset
)
2448 gdb_assert (tdep
->sc_num_regs
<= I386_NUM_SAVED_REGS
);
2450 for (i
= 0; i
< tdep
->sc_num_regs
; i
++)
2451 if (tdep
->sc_reg_offset
[i
] != -1)
2452 cache
->saved_regs
[i
] = addr
+ tdep
->sc_reg_offset
[i
];
2456 cache
->saved_regs
[I386_EIP_REGNUM
] = addr
+ tdep
->sc_pc_offset
;
2457 cache
->saved_regs
[I386_ESP_REGNUM
] = addr
+ tdep
->sc_sp_offset
;
2462 CATCH (ex
, RETURN_MASK_ERROR
)
2464 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
2465 throw_exception (ex
);
2469 *this_cache
= cache
;
2473 static enum unwind_stop_reason
2474 i386_sigtramp_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2477 struct i386_frame_cache
*cache
=
2478 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2481 return UNWIND_UNAVAILABLE
;
2483 return UNWIND_NO_REASON
;
2487 i386_sigtramp_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2488 struct frame_id
*this_id
)
2490 struct i386_frame_cache
*cache
=
2491 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2494 (*this_id
) = frame_id_build_unavailable_stack (get_frame_pc (this_frame
));
2497 /* See the end of i386_push_dummy_call. */
2498 (*this_id
) = frame_id_build (cache
->base
+ 8, get_frame_pc (this_frame
));
2502 static struct value
*
2503 i386_sigtramp_frame_prev_register (struct frame_info
*this_frame
,
2504 void **this_cache
, int regnum
)
2506 /* Make sure we've initialized the cache. */
2507 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2509 return i386_frame_prev_register (this_frame
, this_cache
, regnum
);
2513 i386_sigtramp_frame_sniffer (const struct frame_unwind
*self
,
2514 struct frame_info
*this_frame
,
2515 void **this_prologue_cache
)
2517 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (this_frame
));
2519 /* We shouldn't even bother if we don't have a sigcontext_addr
2521 if (tdep
->sigcontext_addr
== NULL
)
2524 if (tdep
->sigtramp_p
!= NULL
)
2526 if (tdep
->sigtramp_p (this_frame
))
2530 if (tdep
->sigtramp_start
!= 0)
2532 CORE_ADDR pc
= get_frame_pc (this_frame
);
2534 gdb_assert (tdep
->sigtramp_end
!= 0);
2535 if (pc
>= tdep
->sigtramp_start
&& pc
< tdep
->sigtramp_end
)
2542 static const struct frame_unwind i386_sigtramp_frame_unwind
=
2545 i386_sigtramp_frame_unwind_stop_reason
,
2546 i386_sigtramp_frame_this_id
,
2547 i386_sigtramp_frame_prev_register
,
2549 i386_sigtramp_frame_sniffer
2554 i386_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
2556 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
2561 static const struct frame_base i386_frame_base
=
2564 i386_frame_base_address
,
2565 i386_frame_base_address
,
2566 i386_frame_base_address
2569 static struct frame_id
2570 i386_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
2574 fp
= get_frame_register_unsigned (this_frame
, I386_EBP_REGNUM
);
2576 /* See the end of i386_push_dummy_call. */
2577 return frame_id_build (fp
+ 8, get_frame_pc (this_frame
));
2580 /* _Decimal128 function return values need 16-byte alignment on the
2584 i386_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
2586 return sp
& -(CORE_ADDR
)16;
2590 /* Figure out where the longjmp will land. Slurp the args out of the
2591 stack. We expect the first arg to be a pointer to the jmp_buf
2592 structure from which we extract the address that we will land at.
2593 This address is copied into PC. This routine returns non-zero on
2597 i386_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
2600 CORE_ADDR sp
, jb_addr
;
2601 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2602 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2603 int jb_pc_offset
= gdbarch_tdep (gdbarch
)->jb_pc_offset
;
2605 /* If JB_PC_OFFSET is -1, we have no way to find out where the
2606 longjmp will land. */
2607 if (jb_pc_offset
== -1)
2610 get_frame_register (frame
, I386_ESP_REGNUM
, buf
);
2611 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
2612 if (target_read_memory (sp
+ 4, buf
, 4))
2615 jb_addr
= extract_unsigned_integer (buf
, 4, byte_order
);
2616 if (target_read_memory (jb_addr
+ jb_pc_offset
, buf
, 4))
2619 *pc
= extract_unsigned_integer (buf
, 4, byte_order
);
2624 /* Check whether TYPE must be 16-byte-aligned when passed as a
2625 function argument. 16-byte vectors, _Decimal128 and structures or
2626 unions containing such types must be 16-byte-aligned; other
2627 arguments are 4-byte-aligned. */
2630 i386_16_byte_align_p (struct type
*type
)
2632 type
= check_typedef (type
);
2633 if ((TYPE_CODE (type
) == TYPE_CODE_DECFLOAT
2634 || (TYPE_CODE (type
) == TYPE_CODE_ARRAY
&& TYPE_VECTOR (type
)))
2635 && TYPE_LENGTH (type
) == 16)
2637 if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
2638 return i386_16_byte_align_p (TYPE_TARGET_TYPE (type
));
2639 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
2640 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
2643 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
2645 if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type
, i
)))
2652 /* Implementation for set_gdbarch_push_dummy_code. */
2655 i386_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
, CORE_ADDR funaddr
,
2656 struct value
**args
, int nargs
, struct type
*value_type
,
2657 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
,
2658 struct regcache
*regcache
)
2660 /* Use 0xcc breakpoint - 1 byte. */
2664 /* Keep the stack aligned. */
2669 i386_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2670 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
2671 struct value
**args
, CORE_ADDR sp
, int struct_return
,
2672 CORE_ADDR struct_addr
)
2674 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2680 /* BND registers can be in arbitrary values at the moment of the
2681 inferior call. This can cause boundary violations that are not
2682 due to a real bug or even desired by the user. The best to be done
2683 is set the BND registers to allow access to the whole memory, INIT
2684 state, before pushing the inferior call. */
2685 i387_reset_bnd_regs (gdbarch
, regcache
);
2687 /* Determine the total space required for arguments and struct
2688 return address in a first pass (allowing for 16-byte-aligned
2689 arguments), then push arguments in a second pass. */
2691 for (write_pass
= 0; write_pass
< 2; write_pass
++)
2693 int args_space_used
= 0;
2699 /* Push value address. */
2700 store_unsigned_integer (buf
, 4, byte_order
, struct_addr
);
2701 write_memory (sp
, buf
, 4);
2702 args_space_used
+= 4;
2708 for (i
= 0; i
< nargs
; i
++)
2710 int len
= TYPE_LENGTH (value_enclosing_type (args
[i
]));
2714 if (i386_16_byte_align_p (value_enclosing_type (args
[i
])))
2715 args_space_used
= align_up (args_space_used
, 16);
2717 write_memory (sp
+ args_space_used
,
2718 value_contents_all (args
[i
]), len
);
2719 /* The System V ABI says that:
2721 "An argument's size is increased, if necessary, to make it a
2722 multiple of [32-bit] words. This may require tail padding,
2723 depending on the size of the argument."
2725 This makes sure the stack stays word-aligned. */
2726 args_space_used
+= align_up (len
, 4);
2730 if (i386_16_byte_align_p (value_enclosing_type (args
[i
])))
2731 args_space
= align_up (args_space
, 16);
2732 args_space
+= align_up (len
, 4);
2740 /* The original System V ABI only requires word alignment,
2741 but modern incarnations need 16-byte alignment in order
2742 to support SSE. Since wasting a few bytes here isn't
2743 harmful we unconditionally enforce 16-byte alignment. */
2748 /* Store return address. */
2750 store_unsigned_integer (buf
, 4, byte_order
, bp_addr
);
2751 write_memory (sp
, buf
, 4);
2753 /* Finally, update the stack pointer... */
2754 store_unsigned_integer (buf
, 4, byte_order
, sp
);
2755 regcache_cooked_write (regcache
, I386_ESP_REGNUM
, buf
);
2757 /* ...and fake a frame pointer. */
2758 regcache_cooked_write (regcache
, I386_EBP_REGNUM
, buf
);
2760 /* MarkK wrote: This "+ 8" is all over the place:
2761 (i386_frame_this_id, i386_sigtramp_frame_this_id,
2762 i386_dummy_id). It's there, since all frame unwinders for
2763 a given target have to agree (within a certain margin) on the
2764 definition of the stack address of a frame. Otherwise frame id
2765 comparison might not work correctly. Since DWARF2/GCC uses the
2766 stack address *before* the function call as a frame's CFA. On
2767 the i386, when %ebp is used as a frame pointer, the offset
2768 between the contents %ebp and the CFA as defined by GCC. */
2772 /* These registers are used for returning integers (and on some
2773 targets also for returning `struct' and `union' values when their
2774 size and alignment match an integer type). */
2775 #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */
2776 #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */
2778 /* Read, for architecture GDBARCH, a function return value of TYPE
2779 from REGCACHE, and copy that into VALBUF. */
2782 i386_extract_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
2783 struct regcache
*regcache
, gdb_byte
*valbuf
)
2785 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2786 int len
= TYPE_LENGTH (type
);
2787 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
2789 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2791 if (tdep
->st0_regnum
< 0)
2793 warning (_("Cannot find floating-point return value."));
2794 memset (valbuf
, 0, len
);
2798 /* Floating-point return values can be found in %st(0). Convert
2799 its contents to the desired type. This is probably not
2800 exactly how it would happen on the target itself, but it is
2801 the best we can do. */
2802 regcache_raw_read (regcache
, I386_ST0_REGNUM
, buf
);
2803 convert_typed_floating (buf
, i387_ext_type (gdbarch
), valbuf
, type
);
2807 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
2808 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
2810 if (len
<= low_size
)
2812 regcache_raw_read (regcache
, LOW_RETURN_REGNUM
, buf
);
2813 memcpy (valbuf
, buf
, len
);
2815 else if (len
<= (low_size
+ high_size
))
2817 regcache_raw_read (regcache
, LOW_RETURN_REGNUM
, buf
);
2818 memcpy (valbuf
, buf
, low_size
);
2819 regcache_raw_read (regcache
, HIGH_RETURN_REGNUM
, buf
);
2820 memcpy (valbuf
+ low_size
, buf
, len
- low_size
);
2823 internal_error (__FILE__
, __LINE__
,
2824 _("Cannot extract return value of %d bytes long."),
2829 /* Write, for architecture GDBARCH, a function return value of TYPE
2830 from VALBUF into REGCACHE. */
2833 i386_store_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
2834 struct regcache
*regcache
, const gdb_byte
*valbuf
)
2836 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2837 int len
= TYPE_LENGTH (type
);
2839 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2842 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
2844 if (tdep
->st0_regnum
< 0)
2846 warning (_("Cannot set floating-point return value."));
2850 /* Returning floating-point values is a bit tricky. Apart from
2851 storing the return value in %st(0), we have to simulate the
2852 state of the FPU at function return point. */
2854 /* Convert the value found in VALBUF to the extended
2855 floating-point format used by the FPU. This is probably
2856 not exactly how it would happen on the target itself, but
2857 it is the best we can do. */
2858 convert_typed_floating (valbuf
, type
, buf
, i387_ext_type (gdbarch
));
2859 regcache_raw_write (regcache
, I386_ST0_REGNUM
, buf
);
2861 /* Set the top of the floating-point register stack to 7. The
2862 actual value doesn't really matter, but 7 is what a normal
2863 function return would end up with if the program started out
2864 with a freshly initialized FPU. */
2865 regcache_raw_read_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), &fstat
);
2867 regcache_raw_write_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), fstat
);
2869 /* Mark %st(1) through %st(7) as empty. Since we set the top of
2870 the floating-point register stack to 7, the appropriate value
2871 for the tag word is 0x3fff. */
2872 regcache_raw_write_unsigned (regcache
, I387_FTAG_REGNUM (tdep
), 0x3fff);
2876 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
2877 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
2879 if (len
<= low_size
)
2880 regcache_raw_write_part (regcache
, LOW_RETURN_REGNUM
, 0, len
, valbuf
);
2881 else if (len
<= (low_size
+ high_size
))
2883 regcache_raw_write (regcache
, LOW_RETURN_REGNUM
, valbuf
);
2884 regcache_raw_write_part (regcache
, HIGH_RETURN_REGNUM
, 0,
2885 len
- low_size
, valbuf
+ low_size
);
2888 internal_error (__FILE__
, __LINE__
,
2889 _("Cannot store return value of %d bytes long."), len
);
2894 /* This is the variable that is set with "set struct-convention", and
2895 its legitimate values. */
2896 static const char default_struct_convention
[] = "default";
2897 static const char pcc_struct_convention
[] = "pcc";
2898 static const char reg_struct_convention
[] = "reg";
2899 static const char *const valid_conventions
[] =
2901 default_struct_convention
,
2902 pcc_struct_convention
,
2903 reg_struct_convention
,
2906 static const char *struct_convention
= default_struct_convention
;
2908 /* Return non-zero if TYPE, which is assumed to be a structure,
2909 a union type, or an array type, should be returned in registers
2910 for architecture GDBARCH. */
2913 i386_reg_struct_return_p (struct gdbarch
*gdbarch
, struct type
*type
)
2915 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2916 enum type_code code
= TYPE_CODE (type
);
2917 int len
= TYPE_LENGTH (type
);
2919 gdb_assert (code
== TYPE_CODE_STRUCT
2920 || code
== TYPE_CODE_UNION
2921 || code
== TYPE_CODE_ARRAY
);
2923 if (struct_convention
== pcc_struct_convention
2924 || (struct_convention
== default_struct_convention
2925 && tdep
->struct_return
== pcc_struct_return
))
2928 /* Structures consisting of a single `float', `double' or 'long
2929 double' member are returned in %st(0). */
2930 if (code
== TYPE_CODE_STRUCT
&& TYPE_NFIELDS (type
) == 1)
2932 type
= check_typedef (TYPE_FIELD_TYPE (type
, 0));
2933 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2934 return (len
== 4 || len
== 8 || len
== 12);
2937 return (len
== 1 || len
== 2 || len
== 4 || len
== 8);
2940 /* Determine, for architecture GDBARCH, how a return value of TYPE
2941 should be returned. If it is supposed to be returned in registers,
2942 and READBUF is non-zero, read the appropriate value from REGCACHE,
2943 and copy it into READBUF. If WRITEBUF is non-zero, write the value
2944 from WRITEBUF into REGCACHE. */
2946 static enum return_value_convention
2947 i386_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
2948 struct type
*type
, struct regcache
*regcache
,
2949 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2951 enum type_code code
= TYPE_CODE (type
);
2953 if (((code
== TYPE_CODE_STRUCT
2954 || code
== TYPE_CODE_UNION
2955 || code
== TYPE_CODE_ARRAY
)
2956 && !i386_reg_struct_return_p (gdbarch
, type
))
2957 /* Complex double and long double uses the struct return covention. */
2958 || (code
== TYPE_CODE_COMPLEX
&& TYPE_LENGTH (type
) == 16)
2959 || (code
== TYPE_CODE_COMPLEX
&& TYPE_LENGTH (type
) == 24)
2960 /* 128-bit decimal float uses the struct return convention. */
2961 || (code
== TYPE_CODE_DECFLOAT
&& TYPE_LENGTH (type
) == 16))
2963 /* The System V ABI says that:
2965 "A function that returns a structure or union also sets %eax
2966 to the value of the original address of the caller's area
2967 before it returns. Thus when the caller receives control
2968 again, the address of the returned object resides in register
2969 %eax and can be used to access the object."
2971 So the ABI guarantees that we can always find the return
2972 value just after the function has returned. */
2974 /* Note that the ABI doesn't mention functions returning arrays,
2975 which is something possible in certain languages such as Ada.
2976 In this case, the value is returned as if it was wrapped in
2977 a record, so the convention applied to records also applies
2984 regcache_raw_read_unsigned (regcache
, I386_EAX_REGNUM
, &addr
);
2985 read_memory (addr
, readbuf
, TYPE_LENGTH (type
));
2988 return RETURN_VALUE_ABI_RETURNS_ADDRESS
;
2991 /* This special case is for structures consisting of a single
2992 `float', `double' or 'long double' member. These structures are
2993 returned in %st(0). For these structures, we call ourselves
2994 recursively, changing TYPE into the type of the first member of
2995 the structure. Since that should work for all structures that
2996 have only one member, we don't bother to check the member's type
2998 if (code
== TYPE_CODE_STRUCT
&& TYPE_NFIELDS (type
) == 1)
3000 type
= check_typedef (TYPE_FIELD_TYPE (type
, 0));
3001 return i386_return_value (gdbarch
, function
, type
, regcache
,
3006 i386_extract_return_value (gdbarch
, type
, regcache
, readbuf
);
3008 i386_store_return_value (gdbarch
, type
, regcache
, writebuf
);
3010 return RETURN_VALUE_REGISTER_CONVENTION
;
3015 i387_ext_type (struct gdbarch
*gdbarch
)
3017 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3019 if (!tdep
->i387_ext_type
)
3021 tdep
->i387_ext_type
= tdesc_find_type (gdbarch
, "i387_ext");
3022 gdb_assert (tdep
->i387_ext_type
!= NULL
);
3025 return tdep
->i387_ext_type
;
3028 /* Construct type for pseudo BND registers. We can't use
3029 tdesc_find_type since a complement of one value has to be used
3030 to describe the upper bound. */
3032 static struct type
*
3033 i386_bnd_type (struct gdbarch
*gdbarch
)
3035 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3038 if (!tdep
->i386_bnd_type
)
3041 const struct builtin_type
*bt
= builtin_type (gdbarch
);
3043 /* The type we're building is described bellow: */
3048 void *ubound
; /* One complement of raw ubound field. */
3052 t
= arch_composite_type (gdbarch
,
3053 "__gdb_builtin_type_bound128", TYPE_CODE_STRUCT
);
3055 append_composite_type_field (t
, "lbound", bt
->builtin_data_ptr
);
3056 append_composite_type_field (t
, "ubound", bt
->builtin_data_ptr
);
3058 TYPE_NAME (t
) = "builtin_type_bound128";
3059 tdep
->i386_bnd_type
= t
;
3062 return tdep
->i386_bnd_type
;
3065 /* Construct vector type for pseudo ZMM registers. We can't use
3066 tdesc_find_type since ZMM isn't described in target description. */
3068 static struct type
*
3069 i386_zmm_type (struct gdbarch
*gdbarch
)
3071 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3073 if (!tdep
->i386_zmm_type
)
3075 const struct builtin_type
*bt
= builtin_type (gdbarch
);
3077 /* The type we're building is this: */
3079 union __gdb_builtin_type_vec512i
3081 int128_t uint128
[4];
3082 int64_t v4_int64
[8];
3083 int32_t v8_int32
[16];
3084 int16_t v16_int16
[32];
3085 int8_t v32_int8
[64];
3086 double v4_double
[8];
3093 t
= arch_composite_type (gdbarch
,
3094 "__gdb_builtin_type_vec512i", TYPE_CODE_UNION
);
3095 append_composite_type_field (t
, "v16_float",
3096 init_vector_type (bt
->builtin_float
, 16));
3097 append_composite_type_field (t
, "v8_double",
3098 init_vector_type (bt
->builtin_double
, 8));
3099 append_composite_type_field (t
, "v64_int8",
3100 init_vector_type (bt
->builtin_int8
, 64));
3101 append_composite_type_field (t
, "v32_int16",
3102 init_vector_type (bt
->builtin_int16
, 32));
3103 append_composite_type_field (t
, "v16_int32",
3104 init_vector_type (bt
->builtin_int32
, 16));
3105 append_composite_type_field (t
, "v8_int64",
3106 init_vector_type (bt
->builtin_int64
, 8));
3107 append_composite_type_field (t
, "v4_int128",
3108 init_vector_type (bt
->builtin_int128
, 4));
3110 TYPE_VECTOR (t
) = 1;
3111 TYPE_NAME (t
) = "builtin_type_vec512i";
3112 tdep
->i386_zmm_type
= t
;
3115 return tdep
->i386_zmm_type
;
3118 /* Construct vector type for pseudo YMM registers. We can't use
3119 tdesc_find_type since YMM isn't described in target description. */
3121 static struct type
*
3122 i386_ymm_type (struct gdbarch
*gdbarch
)
3124 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3126 if (!tdep
->i386_ymm_type
)
3128 const struct builtin_type
*bt
= builtin_type (gdbarch
);
3130 /* The type we're building is this: */
3132 union __gdb_builtin_type_vec256i
3134 int128_t uint128
[2];
3135 int64_t v2_int64
[4];
3136 int32_t v4_int32
[8];
3137 int16_t v8_int16
[16];
3138 int8_t v16_int8
[32];
3139 double v2_double
[4];
3146 t
= arch_composite_type (gdbarch
,
3147 "__gdb_builtin_type_vec256i", TYPE_CODE_UNION
);
3148 append_composite_type_field (t
, "v8_float",
3149 init_vector_type (bt
->builtin_float
, 8));
3150 append_composite_type_field (t
, "v4_double",
3151 init_vector_type (bt
->builtin_double
, 4));
3152 append_composite_type_field (t
, "v32_int8",
3153 init_vector_type (bt
->builtin_int8
, 32));
3154 append_composite_type_field (t
, "v16_int16",
3155 init_vector_type (bt
->builtin_int16
, 16));
3156 append_composite_type_field (t
, "v8_int32",
3157 init_vector_type (bt
->builtin_int32
, 8));
3158 append_composite_type_field (t
, "v4_int64",
3159 init_vector_type (bt
->builtin_int64
, 4));
3160 append_composite_type_field (t
, "v2_int128",
3161 init_vector_type (bt
->builtin_int128
, 2));
3163 TYPE_VECTOR (t
) = 1;
3164 TYPE_NAME (t
) = "builtin_type_vec256i";
3165 tdep
->i386_ymm_type
= t
;
3168 return tdep
->i386_ymm_type
;
3171 /* Construct vector type for MMX registers. */
3172 static struct type
*
3173 i386_mmx_type (struct gdbarch
*gdbarch
)
3175 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3177 if (!tdep
->i386_mmx_type
)
3179 const struct builtin_type
*bt
= builtin_type (gdbarch
);
3181 /* The type we're building is this: */
3183 union __gdb_builtin_type_vec64i
3186 int32_t v2_int32
[2];
3187 int16_t v4_int16
[4];
3194 t
= arch_composite_type (gdbarch
,
3195 "__gdb_builtin_type_vec64i", TYPE_CODE_UNION
);
3197 append_composite_type_field (t
, "uint64", bt
->builtin_int64
);
3198 append_composite_type_field (t
, "v2_int32",
3199 init_vector_type (bt
->builtin_int32
, 2));
3200 append_composite_type_field (t
, "v4_int16",
3201 init_vector_type (bt
->builtin_int16
, 4));
3202 append_composite_type_field (t
, "v8_int8",
3203 init_vector_type (bt
->builtin_int8
, 8));
3205 TYPE_VECTOR (t
) = 1;
3206 TYPE_NAME (t
) = "builtin_type_vec64i";
3207 tdep
->i386_mmx_type
= t
;
3210 return tdep
->i386_mmx_type
;
3213 /* Return the GDB type object for the "standard" data type of data in
3217 i386_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
3219 if (i386_bnd_regnum_p (gdbarch
, regnum
))
3220 return i386_bnd_type (gdbarch
);
3221 if (i386_mmx_regnum_p (gdbarch
, regnum
))
3222 return i386_mmx_type (gdbarch
);
3223 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
3224 return i386_ymm_type (gdbarch
);
3225 else if (i386_ymm_avx512_regnum_p (gdbarch
, regnum
))
3226 return i386_ymm_type (gdbarch
);
3227 else if (i386_zmm_regnum_p (gdbarch
, regnum
))
3228 return i386_zmm_type (gdbarch
);
3231 const struct builtin_type
*bt
= builtin_type (gdbarch
);
3232 if (i386_byte_regnum_p (gdbarch
, regnum
))
3233 return bt
->builtin_int8
;
3234 else if (i386_word_regnum_p (gdbarch
, regnum
))
3235 return bt
->builtin_int16
;
3236 else if (i386_dword_regnum_p (gdbarch
, regnum
))
3237 return bt
->builtin_int32
;
3238 else if (i386_k_regnum_p (gdbarch
, regnum
))
3239 return bt
->builtin_int64
;
3242 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
3245 /* Map a cooked register onto a raw register or memory. For the i386,
3246 the MMX registers need to be mapped onto floating point registers. */
3249 i386_mmx_regnum_to_fp_regnum (struct regcache
*regcache
, int regnum
)
3251 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_regcache_arch (regcache
));
3256 mmxreg
= regnum
- tdep
->mm0_regnum
;
3257 regcache_raw_read_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), &fstat
);
3258 tos
= (fstat
>> 11) & 0x7;
3259 fpreg
= (mmxreg
+ tos
) % 8;
3261 return (I387_ST0_REGNUM (tdep
) + fpreg
);
3264 /* A helper function for us by i386_pseudo_register_read_value and
3265 amd64_pseudo_register_read_value. It does all the work but reads
3266 the data into an already-allocated value. */
3269 i386_pseudo_register_read_into_value (struct gdbarch
*gdbarch
,
3270 struct regcache
*regcache
,
3272 struct value
*result_value
)
3274 gdb_byte raw_buf
[I386_MAX_REGISTER_SIZE
];
3275 enum register_status status
;
3276 gdb_byte
*buf
= value_contents_raw (result_value
);
3278 if (i386_mmx_regnum_p (gdbarch
, regnum
))
3280 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
3282 /* Extract (always little endian). */
3283 status
= regcache_raw_read (regcache
, fpnum
, raw_buf
);
3284 if (status
!= REG_VALID
)
3285 mark_value_bytes_unavailable (result_value
, 0,
3286 TYPE_LENGTH (value_type (result_value
)));
3288 memcpy (buf
, raw_buf
, register_size (gdbarch
, regnum
));
3292 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3293 if (i386_bnd_regnum_p (gdbarch
, regnum
))
3295 regnum
-= tdep
->bnd0_regnum
;
3297 /* Extract (always little endian). Read lower 128bits. */
3298 status
= regcache_raw_read (regcache
,
3299 I387_BND0R_REGNUM (tdep
) + regnum
,
3301 if (status
!= REG_VALID
)
3302 mark_value_bytes_unavailable (result_value
, 0, 16);
3305 enum bfd_endian byte_order
= gdbarch_byte_order (target_gdbarch ());
3306 LONGEST upper
, lower
;
3307 int size
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_data_ptr
);
3309 lower
= extract_unsigned_integer (raw_buf
, 8, byte_order
);
3310 upper
= extract_unsigned_integer (raw_buf
+ 8, 8, byte_order
);
3313 memcpy (buf
, &lower
, size
);
3314 memcpy (buf
+ size
, &upper
, size
);
3317 else if (i386_k_regnum_p (gdbarch
, regnum
))
3319 regnum
-= tdep
->k0_regnum
;
3321 /* Extract (always little endian). */
3322 status
= regcache_raw_read (regcache
,
3323 tdep
->k0_regnum
+ regnum
,
3325 if (status
!= REG_VALID
)
3326 mark_value_bytes_unavailable (result_value
, 0, 8);
3328 memcpy (buf
, raw_buf
, 8);
3330 else if (i386_zmm_regnum_p (gdbarch
, regnum
))
3332 regnum
-= tdep
->zmm0_regnum
;
3334 if (regnum
< num_lower_zmm_regs
)
3336 /* Extract (always little endian). Read lower 128bits. */
3337 status
= regcache_raw_read (regcache
,
3338 I387_XMM0_REGNUM (tdep
) + regnum
,
3340 if (status
!= REG_VALID
)
3341 mark_value_bytes_unavailable (result_value
, 0, 16);
3343 memcpy (buf
, raw_buf
, 16);
3345 /* Extract (always little endian). Read upper 128bits. */
3346 status
= regcache_raw_read (regcache
,
3347 tdep
->ymm0h_regnum
+ regnum
,
3349 if (status
!= REG_VALID
)
3350 mark_value_bytes_unavailable (result_value
, 16, 16);
3352 memcpy (buf
+ 16, raw_buf
, 16);
3356 /* Extract (always little endian). Read lower 128bits. */
3357 status
= regcache_raw_read (regcache
,
3358 I387_XMM16_REGNUM (tdep
) + regnum
3359 - num_lower_zmm_regs
,
3361 if (status
!= REG_VALID
)
3362 mark_value_bytes_unavailable (result_value
, 0, 16);
3364 memcpy (buf
, raw_buf
, 16);
3366 /* Extract (always little endian). Read upper 128bits. */
3367 status
= regcache_raw_read (regcache
,
3368 I387_YMM16H_REGNUM (tdep
) + regnum
3369 - num_lower_zmm_regs
,
3371 if (status
!= REG_VALID
)
3372 mark_value_bytes_unavailable (result_value
, 16, 16);
3374 memcpy (buf
+ 16, raw_buf
, 16);
3377 /* Read upper 256bits. */
3378 status
= regcache_raw_read (regcache
,
3379 tdep
->zmm0h_regnum
+ regnum
,
3381 if (status
!= REG_VALID
)
3382 mark_value_bytes_unavailable (result_value
, 32, 32);
3384 memcpy (buf
+ 32, raw_buf
, 32);
3386 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
3388 regnum
-= tdep
->ymm0_regnum
;
3390 /* Extract (always little endian). Read lower 128bits. */
3391 status
= regcache_raw_read (regcache
,
3392 I387_XMM0_REGNUM (tdep
) + regnum
,
3394 if (status
!= REG_VALID
)
3395 mark_value_bytes_unavailable (result_value
, 0, 16);
3397 memcpy (buf
, raw_buf
, 16);
3398 /* Read upper 128bits. */
3399 status
= regcache_raw_read (regcache
,
3400 tdep
->ymm0h_regnum
+ regnum
,
3402 if (status
!= REG_VALID
)
3403 mark_value_bytes_unavailable (result_value
, 16, 32);
3405 memcpy (buf
+ 16, raw_buf
, 16);
3407 else if (i386_ymm_avx512_regnum_p (gdbarch
, regnum
))
3409 regnum
-= tdep
->ymm16_regnum
;
3410 /* Extract (always little endian). Read lower 128bits. */
3411 status
= regcache_raw_read (regcache
,
3412 I387_XMM16_REGNUM (tdep
) + regnum
,
3414 if (status
!= REG_VALID
)
3415 mark_value_bytes_unavailable (result_value
, 0, 16);
3417 memcpy (buf
, raw_buf
, 16);
3418 /* Read upper 128bits. */
3419 status
= regcache_raw_read (regcache
,
3420 tdep
->ymm16h_regnum
+ regnum
,
3422 if (status
!= REG_VALID
)
3423 mark_value_bytes_unavailable (result_value
, 16, 16);
3425 memcpy (buf
+ 16, raw_buf
, 16);
3427 else if (i386_word_regnum_p (gdbarch
, regnum
))
3429 int gpnum
= regnum
- tdep
->ax_regnum
;
3431 /* Extract (always little endian). */
3432 status
= regcache_raw_read (regcache
, gpnum
, raw_buf
);
3433 if (status
!= REG_VALID
)
3434 mark_value_bytes_unavailable (result_value
, 0,
3435 TYPE_LENGTH (value_type (result_value
)));
3437 memcpy (buf
, raw_buf
, 2);
3439 else if (i386_byte_regnum_p (gdbarch
, regnum
))
3441 int gpnum
= regnum
- tdep
->al_regnum
;
3443 /* Extract (always little endian). We read both lower and
3445 status
= regcache_raw_read (regcache
, gpnum
% 4, raw_buf
);
3446 if (status
!= REG_VALID
)
3447 mark_value_bytes_unavailable (result_value
, 0,
3448 TYPE_LENGTH (value_type (result_value
)));
3449 else if (gpnum
>= 4)
3450 memcpy (buf
, raw_buf
+ 1, 1);
3452 memcpy (buf
, raw_buf
, 1);
3455 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
3459 static struct value
*
3460 i386_pseudo_register_read_value (struct gdbarch
*gdbarch
,
3461 struct regcache
*regcache
,
3464 struct value
*result
;
3466 result
= allocate_value (register_type (gdbarch
, regnum
));
3467 VALUE_LVAL (result
) = lval_register
;
3468 VALUE_REGNUM (result
) = regnum
;
3470 i386_pseudo_register_read_into_value (gdbarch
, regcache
, regnum
, result
);
3476 i386_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
3477 int regnum
, const gdb_byte
*buf
)
3479 gdb_byte raw_buf
[I386_MAX_REGISTER_SIZE
];
3481 if (i386_mmx_regnum_p (gdbarch
, regnum
))
3483 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
3486 regcache_raw_read (regcache
, fpnum
, raw_buf
);
3487 /* ... Modify ... (always little endian). */
3488 memcpy (raw_buf
, buf
, register_size (gdbarch
, regnum
));
3490 regcache_raw_write (regcache
, fpnum
, raw_buf
);
3494 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3496 if (i386_bnd_regnum_p (gdbarch
, regnum
))
3498 ULONGEST upper
, lower
;
3499 int size
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_data_ptr
);
3500 enum bfd_endian byte_order
= gdbarch_byte_order (target_gdbarch ());
3502 /* New values from input value. */
3503 regnum
-= tdep
->bnd0_regnum
;
3504 lower
= extract_unsigned_integer (buf
, size
, byte_order
);
3505 upper
= extract_unsigned_integer (buf
+ size
, size
, byte_order
);
3507 /* Fetching register buffer. */
3508 regcache_raw_read (regcache
,
3509 I387_BND0R_REGNUM (tdep
) + regnum
,
3514 /* Set register bits. */
3515 memcpy (raw_buf
, &lower
, 8);
3516 memcpy (raw_buf
+ 8, &upper
, 8);
3519 regcache_raw_write (regcache
,
3520 I387_BND0R_REGNUM (tdep
) + regnum
,
3523 else if (i386_k_regnum_p (gdbarch
, regnum
))
3525 regnum
-= tdep
->k0_regnum
;
3527 regcache_raw_write (regcache
,
3528 tdep
->k0_regnum
+ regnum
,
3531 else if (i386_zmm_regnum_p (gdbarch
, regnum
))
3533 regnum
-= tdep
->zmm0_regnum
;
3535 if (regnum
< num_lower_zmm_regs
)
3537 /* Write lower 128bits. */
3538 regcache_raw_write (regcache
,
3539 I387_XMM0_REGNUM (tdep
) + regnum
,
3541 /* Write upper 128bits. */
3542 regcache_raw_write (regcache
,
3543 I387_YMM0_REGNUM (tdep
) + regnum
,
3548 /* Write lower 128bits. */
3549 regcache_raw_write (regcache
,
3550 I387_XMM16_REGNUM (tdep
) + regnum
3551 - num_lower_zmm_regs
,
3553 /* Write upper 128bits. */
3554 regcache_raw_write (regcache
,
3555 I387_YMM16H_REGNUM (tdep
) + regnum
3556 - num_lower_zmm_regs
,
3559 /* Write upper 256bits. */
3560 regcache_raw_write (regcache
,
3561 tdep
->zmm0h_regnum
+ regnum
,
3564 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
3566 regnum
-= tdep
->ymm0_regnum
;
3568 /* ... Write lower 128bits. */
3569 regcache_raw_write (regcache
,
3570 I387_XMM0_REGNUM (tdep
) + regnum
,
3572 /* ... Write upper 128bits. */
3573 regcache_raw_write (regcache
,
3574 tdep
->ymm0h_regnum
+ regnum
,
3577 else if (i386_ymm_avx512_regnum_p (gdbarch
, regnum
))
3579 regnum
-= tdep
->ymm16_regnum
;
3581 /* ... Write lower 128bits. */
3582 regcache_raw_write (regcache
,
3583 I387_XMM16_REGNUM (tdep
) + regnum
,
3585 /* ... Write upper 128bits. */
3586 regcache_raw_write (regcache
,
3587 tdep
->ymm16h_regnum
+ regnum
,
3590 else if (i386_word_regnum_p (gdbarch
, regnum
))
3592 int gpnum
= regnum
- tdep
->ax_regnum
;
3595 regcache_raw_read (regcache
, gpnum
, raw_buf
);
3596 /* ... Modify ... (always little endian). */
3597 memcpy (raw_buf
, buf
, 2);
3599 regcache_raw_write (regcache
, gpnum
, raw_buf
);
3601 else if (i386_byte_regnum_p (gdbarch
, regnum
))
3603 int gpnum
= regnum
- tdep
->al_regnum
;
3605 /* Read ... We read both lower and upper registers. */
3606 regcache_raw_read (regcache
, gpnum
% 4, raw_buf
);
3607 /* ... Modify ... (always little endian). */
3609 memcpy (raw_buf
+ 1, buf
, 1);
3611 memcpy (raw_buf
, buf
, 1);
3613 regcache_raw_write (regcache
, gpnum
% 4, raw_buf
);
3616 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
3620 /* Implement the 'ax_pseudo_register_collect' gdbarch method. */
3623 i386_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
3624 struct agent_expr
*ax
, int regnum
)
3626 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3628 if (i386_mmx_regnum_p (gdbarch
, regnum
))
3630 /* MMX to FPU register mapping depends on current TOS. Let's just
3631 not care and collect everything... */
3634 ax_reg_mask (ax
, I387_FSTAT_REGNUM (tdep
));
3635 for (i
= 0; i
< 8; i
++)
3636 ax_reg_mask (ax
, I387_ST0_REGNUM (tdep
) + i
);
3639 else if (i386_bnd_regnum_p (gdbarch
, regnum
))
3641 regnum
-= tdep
->bnd0_regnum
;
3642 ax_reg_mask (ax
, I387_BND0R_REGNUM (tdep
) + regnum
);
3645 else if (i386_k_regnum_p (gdbarch
, regnum
))
3647 regnum
-= tdep
->k0_regnum
;
3648 ax_reg_mask (ax
, tdep
->k0_regnum
+ regnum
);
3651 else if (i386_zmm_regnum_p (gdbarch
, regnum
))
3653 regnum
-= tdep
->zmm0_regnum
;
3654 if (regnum
< num_lower_zmm_regs
)
3656 ax_reg_mask (ax
, I387_XMM0_REGNUM (tdep
) + regnum
);
3657 ax_reg_mask (ax
, tdep
->ymm0h_regnum
+ regnum
);
3661 ax_reg_mask (ax
, I387_XMM16_REGNUM (tdep
) + regnum
3662 - num_lower_zmm_regs
);
3663 ax_reg_mask (ax
, I387_YMM16H_REGNUM (tdep
) + regnum
3664 - num_lower_zmm_regs
);
3666 ax_reg_mask (ax
, tdep
->zmm0h_regnum
+ regnum
);
3669 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
3671 regnum
-= tdep
->ymm0_regnum
;
3672 ax_reg_mask (ax
, I387_XMM0_REGNUM (tdep
) + regnum
);
3673 ax_reg_mask (ax
, tdep
->ymm0h_regnum
+ regnum
);
3676 else if (i386_ymm_avx512_regnum_p (gdbarch
, regnum
))
3678 regnum
-= tdep
->ymm16_regnum
;
3679 ax_reg_mask (ax
, I387_XMM16_REGNUM (tdep
) + regnum
);
3680 ax_reg_mask (ax
, tdep
->ymm16h_regnum
+ regnum
);
3683 else if (i386_word_regnum_p (gdbarch
, regnum
))
3685 int gpnum
= regnum
- tdep
->ax_regnum
;
3687 ax_reg_mask (ax
, gpnum
);
3690 else if (i386_byte_regnum_p (gdbarch
, regnum
))
3692 int gpnum
= regnum
- tdep
->al_regnum
;
3694 ax_reg_mask (ax
, gpnum
% 4);
3698 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
3703 /* Return the register number of the register allocated by GCC after
3704 REGNUM, or -1 if there is no such register. */
3707 i386_next_regnum (int regnum
)
3709 /* GCC allocates the registers in the order:
3711 %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ...
3713 Since storing a variable in %esp doesn't make any sense we return
3714 -1 for %ebp and for %esp itself. */
3715 static int next_regnum
[] =
3717 I386_EDX_REGNUM
, /* Slot for %eax. */
3718 I386_EBX_REGNUM
, /* Slot for %ecx. */
3719 I386_ECX_REGNUM
, /* Slot for %edx. */
3720 I386_ESI_REGNUM
, /* Slot for %ebx. */
3721 -1, -1, /* Slots for %esp and %ebp. */
3722 I386_EDI_REGNUM
, /* Slot for %esi. */
3723 I386_EBP_REGNUM
/* Slot for %edi. */
3726 if (regnum
>= 0 && regnum
< sizeof (next_regnum
) / sizeof (next_regnum
[0]))
3727 return next_regnum
[regnum
];
3732 /* Return nonzero if a value of type TYPE stored in register REGNUM
3733 needs any special handling. */
3736 i386_convert_register_p (struct gdbarch
*gdbarch
,
3737 int regnum
, struct type
*type
)
3739 int len
= TYPE_LENGTH (type
);
3741 /* Values may be spread across multiple registers. Most debugging
3742 formats aren't expressive enough to specify the locations, so
3743 some heuristics is involved. Right now we only handle types that
3744 have a length that is a multiple of the word size, since GCC
3745 doesn't seem to put any other types into registers. */
3746 if (len
> 4 && len
% 4 == 0)
3748 int last_regnum
= regnum
;
3752 last_regnum
= i386_next_regnum (last_regnum
);
3756 if (last_regnum
!= -1)
3760 return i387_convert_register_p (gdbarch
, regnum
, type
);
3763 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
3764 return its contents in TO. */
3767 i386_register_to_value (struct frame_info
*frame
, int regnum
,
3768 struct type
*type
, gdb_byte
*to
,
3769 int *optimizedp
, int *unavailablep
)
3771 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3772 int len
= TYPE_LENGTH (type
);
3774 if (i386_fp_regnum_p (gdbarch
, regnum
))
3775 return i387_register_to_value (frame
, regnum
, type
, to
,
3776 optimizedp
, unavailablep
);
3778 /* Read a value spread across multiple registers. */
3780 gdb_assert (len
> 4 && len
% 4 == 0);
3784 gdb_assert (regnum
!= -1);
3785 gdb_assert (register_size (gdbarch
, regnum
) == 4);
3787 if (!get_frame_register_bytes (frame
, regnum
, 0,
3788 register_size (gdbarch
, regnum
),
3789 to
, optimizedp
, unavailablep
))
3792 regnum
= i386_next_regnum (regnum
);
3797 *optimizedp
= *unavailablep
= 0;
3801 /* Write the contents FROM of a value of type TYPE into register
3802 REGNUM in frame FRAME. */
3805 i386_value_to_register (struct frame_info
*frame
, int regnum
,
3806 struct type
*type
, const gdb_byte
*from
)
3808 int len
= TYPE_LENGTH (type
);
3810 if (i386_fp_regnum_p (get_frame_arch (frame
), regnum
))
3812 i387_value_to_register (frame
, regnum
, type
, from
);
3816 /* Write a value spread across multiple registers. */
3818 gdb_assert (len
> 4 && len
% 4 == 0);
3822 gdb_assert (regnum
!= -1);
3823 gdb_assert (register_size (get_frame_arch (frame
), regnum
) == 4);
3825 put_frame_register (frame
, regnum
, from
);
3826 regnum
= i386_next_regnum (regnum
);
3832 /* Supply register REGNUM from the buffer specified by GREGS and LEN
3833 in the general-purpose register set REGSET to register cache
3834 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3837 i386_supply_gregset (const struct regset
*regset
, struct regcache
*regcache
,
3838 int regnum
, const void *gregs
, size_t len
)
3840 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
3841 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3842 const gdb_byte
*regs
= (const gdb_byte
*) gregs
;
3845 gdb_assert (len
>= tdep
->sizeof_gregset
);
3847 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
3849 if ((regnum
== i
|| regnum
== -1)
3850 && tdep
->gregset_reg_offset
[i
] != -1)
3851 regcache_raw_supply (regcache
, i
, regs
+ tdep
->gregset_reg_offset
[i
]);
3855 /* Collect register REGNUM from the register cache REGCACHE and store
3856 it in the buffer specified by GREGS and LEN as described by the
3857 general-purpose register set REGSET. If REGNUM is -1, do this for
3858 all registers in REGSET. */
3861 i386_collect_gregset (const struct regset
*regset
,
3862 const struct regcache
*regcache
,
3863 int regnum
, void *gregs
, size_t len
)
3865 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
3866 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3867 gdb_byte
*regs
= (gdb_byte
*) gregs
;
3870 gdb_assert (len
>= tdep
->sizeof_gregset
);
3872 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
3874 if ((regnum
== i
|| regnum
== -1)
3875 && tdep
->gregset_reg_offset
[i
] != -1)
3876 regcache_raw_collect (regcache
, i
, regs
+ tdep
->gregset_reg_offset
[i
]);
3880 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
3881 in the floating-point register set REGSET to register cache
3882 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3885 i386_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
3886 int regnum
, const void *fpregs
, size_t len
)
3888 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
3889 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3891 if (len
== I387_SIZEOF_FXSAVE
)
3893 i387_supply_fxsave (regcache
, regnum
, fpregs
);
3897 gdb_assert (len
>= tdep
->sizeof_fpregset
);
3898 i387_supply_fsave (regcache
, regnum
, fpregs
);
3901 /* Collect register REGNUM from the register cache REGCACHE and store
3902 it in the buffer specified by FPREGS and LEN as described by the
3903 floating-point register set REGSET. If REGNUM is -1, do this for
3904 all registers in REGSET. */
3907 i386_collect_fpregset (const struct regset
*regset
,
3908 const struct regcache
*regcache
,
3909 int regnum
, void *fpregs
, size_t len
)
3911 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
3912 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3914 if (len
== I387_SIZEOF_FXSAVE
)
3916 i387_collect_fxsave (regcache
, regnum
, fpregs
);
3920 gdb_assert (len
>= tdep
->sizeof_fpregset
);
3921 i387_collect_fsave (regcache
, regnum
, fpregs
);
3924 /* Register set definitions. */
3926 const struct regset i386_gregset
=
3928 NULL
, i386_supply_gregset
, i386_collect_gregset
3931 const struct regset i386_fpregset
=
3933 NULL
, i386_supply_fpregset
, i386_collect_fpregset
3936 /* Default iterator over core file register note sections. */
3939 i386_iterate_over_regset_sections (struct gdbarch
*gdbarch
,
3940 iterate_over_regset_sections_cb
*cb
,
3942 const struct regcache
*regcache
)
3944 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3946 cb (".reg", tdep
->sizeof_gregset
, &i386_gregset
, NULL
, cb_data
);
3947 if (tdep
->sizeof_fpregset
)
3948 cb (".reg2", tdep
->sizeof_fpregset
, tdep
->fpregset
, NULL
, cb_data
);
3952 /* Stuff for WIN32 PE style DLL's but is pretty generic really. */
3955 i386_pe_skip_trampoline_code (struct frame_info
*frame
,
3956 CORE_ADDR pc
, char *name
)
3958 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3959 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3962 if (pc
&& read_memory_unsigned_integer (pc
, 2, byte_order
) == 0x25ff)
3964 unsigned long indirect
=
3965 read_memory_unsigned_integer (pc
+ 2, 4, byte_order
);
3966 struct minimal_symbol
*indsym
=
3967 indirect
? lookup_minimal_symbol_by_pc (indirect
).minsym
: 0;
3968 const char *symname
= indsym
? MSYMBOL_LINKAGE_NAME (indsym
) : 0;
3972 if (startswith (symname
, "__imp_")
3973 || startswith (symname
, "_imp_"))
3975 read_memory_unsigned_integer (indirect
, 4, byte_order
);
3978 return 0; /* Not a trampoline. */
3982 /* Return whether the THIS_FRAME corresponds to a sigtramp
3986 i386_sigtramp_p (struct frame_info
*this_frame
)
3988 CORE_ADDR pc
= get_frame_pc (this_frame
);
3991 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
3992 return (name
&& strcmp ("_sigtramp", name
) == 0);
3996 /* We have two flavours of disassembly. The machinery on this page
3997 deals with switching between those. */
4000 i386_print_insn (bfd_vma pc
, struct disassemble_info
*info
)
4002 gdb_assert (disassembly_flavor
== att_flavor
4003 || disassembly_flavor
== intel_flavor
);
4005 info
->disassembler_options
= disassembly_flavor
;
4007 return default_print_insn (pc
, info
);
4011 /* There are a few i386 architecture variants that differ only
4012 slightly from the generic i386 target. For now, we don't give them
4013 their own source file, but include them here. As a consequence,
4014 they'll always be included. */
4016 /* System V Release 4 (SVR4). */
4018 /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp
4022 i386_svr4_sigtramp_p (struct frame_info
*this_frame
)
4024 CORE_ADDR pc
= get_frame_pc (this_frame
);
4027 /* The origin of these symbols is currently unknown. */
4028 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
4029 return (name
&& (strcmp ("_sigreturn", name
) == 0
4030 || strcmp ("sigvechandler", name
) == 0));
4033 /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the
4034 address of the associated sigcontext (ucontext) structure. */
4037 i386_svr4_sigcontext_addr (struct frame_info
*this_frame
)
4039 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
4040 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4044 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
4045 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
4047 return read_memory_unsigned_integer (sp
+ 8, 4, byte_order
);
4052 /* Implementation of `gdbarch_stap_is_single_operand', as defined in
4056 i386_stap_is_single_operand (struct gdbarch
*gdbarch
, const char *s
)
4058 return (*s
== '$' /* Literal number. */
4059 || (isdigit (*s
) && s
[1] == '(' && s
[2] == '%') /* Displacement. */
4060 || (*s
== '(' && s
[1] == '%') /* Register indirection. */
4061 || (*s
== '%' && isalpha (s
[1]))); /* Register access. */
4064 /* Helper function for i386_stap_parse_special_token.
4066 This function parses operands of the form `-8+3+1(%rbp)', which
4067 must be interpreted as `*(-8 + 3 - 1 + (void *) $eax)'.
4069 Return 1 if the operand was parsed successfully, zero
4073 i386_stap_parse_special_token_triplet (struct gdbarch
*gdbarch
,
4074 struct stap_parse_info
*p
)
4076 const char *s
= p
->arg
;
4078 if (isdigit (*s
) || *s
== '-' || *s
== '+')
4082 long displacements
[3];
4098 if (!isdigit ((unsigned char) *s
))
4101 displacements
[0] = strtol (s
, &endp
, 10);
4104 if (*s
!= '+' && *s
!= '-')
4106 /* We are not dealing with a triplet. */
4119 if (!isdigit ((unsigned char) *s
))
4122 displacements
[1] = strtol (s
, &endp
, 10);
4125 if (*s
!= '+' && *s
!= '-')
4127 /* We are not dealing with a triplet. */
4140 if (!isdigit ((unsigned char) *s
))
4143 displacements
[2] = strtol (s
, &endp
, 10);
4146 if (*s
!= '(' || s
[1] != '%')
4152 while (isalnum (*s
))
4158 len
= s
- start
- 1;
4159 regname
= (char *) alloca (len
+ 1);
4161 strncpy (regname
, start
, len
);
4162 regname
[len
] = '\0';
4164 if (user_reg_map_name_to_regnum (gdbarch
, regname
, len
) == -1)
4165 error (_("Invalid register name `%s' on expression `%s'."),
4166 regname
, p
->saved_arg
);
4168 for (i
= 0; i
< 3; i
++)
4170 write_exp_elt_opcode (&p
->pstate
, OP_LONG
);
4172 (&p
->pstate
, builtin_type (gdbarch
)->builtin_long
);
4173 write_exp_elt_longcst (&p
->pstate
, displacements
[i
]);
4174 write_exp_elt_opcode (&p
->pstate
, OP_LONG
);
4176 write_exp_elt_opcode (&p
->pstate
, UNOP_NEG
);
4179 write_exp_elt_opcode (&p
->pstate
, OP_REGISTER
);
4182 write_exp_string (&p
->pstate
, str
);
4183 write_exp_elt_opcode (&p
->pstate
, OP_REGISTER
);
4185 write_exp_elt_opcode (&p
->pstate
, UNOP_CAST
);
4186 write_exp_elt_type (&p
->pstate
,
4187 builtin_type (gdbarch
)->builtin_data_ptr
);
4188 write_exp_elt_opcode (&p
->pstate
, UNOP_CAST
);
4190 write_exp_elt_opcode (&p
->pstate
, BINOP_ADD
);
4191 write_exp_elt_opcode (&p
->pstate
, BINOP_ADD
);
4192 write_exp_elt_opcode (&p
->pstate
, BINOP_ADD
);
4194 write_exp_elt_opcode (&p
->pstate
, UNOP_CAST
);
4195 write_exp_elt_type (&p
->pstate
,
4196 lookup_pointer_type (p
->arg_type
));
4197 write_exp_elt_opcode (&p
->pstate
, UNOP_CAST
);
4199 write_exp_elt_opcode (&p
->pstate
, UNOP_IND
);
4209 /* Helper function for i386_stap_parse_special_token.
4211 This function parses operands of the form `register base +
4212 (register index * size) + offset', as represented in
4213 `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'.
4215 Return 1 if the operand was parsed successfully, zero
4219 i386_stap_parse_special_token_three_arg_disp (struct gdbarch
*gdbarch
,
4220 struct stap_parse_info
*p
)
4222 const char *s
= p
->arg
;
4224 if (isdigit (*s
) || *s
== '(' || *s
== '-' || *s
== '+')
4226 int offset_minus
= 0;
4235 struct stoken base_token
, index_token
;
4245 if (offset_minus
&& !isdigit (*s
))
4252 offset
= strtol (s
, &endp
, 10);
4256 if (*s
!= '(' || s
[1] != '%')
4262 while (isalnum (*s
))
4265 if (*s
!= ',' || s
[1] != '%')
4268 len_base
= s
- start
;
4269 base
= (char *) alloca (len_base
+ 1);
4270 strncpy (base
, start
, len_base
);
4271 base
[len_base
] = '\0';
4273 if (user_reg_map_name_to_regnum (gdbarch
, base
, len_base
) == -1)
4274 error (_("Invalid register name `%s' on expression `%s'."),
4275 base
, p
->saved_arg
);
4280 while (isalnum (*s
))
4283 len_index
= s
- start
;
4284 index
= (char *) alloca (len_index
+ 1);
4285 strncpy (index
, start
, len_index
);
4286 index
[len_index
] = '\0';
4288 if (user_reg_map_name_to_regnum (gdbarch
, index
, len_index
) == -1)
4289 error (_("Invalid register name `%s' on expression `%s'."),
4290 index
, p
->saved_arg
);
4292 if (*s
!= ',' && *s
!= ')')
4308 size
= strtol (s
, &endp
, 10);
4319 write_exp_elt_opcode (&p
->pstate
, OP_LONG
);
4320 write_exp_elt_type (&p
->pstate
,
4321 builtin_type (gdbarch
)->builtin_long
);
4322 write_exp_elt_longcst (&p
->pstate
, offset
);
4323 write_exp_elt_opcode (&p
->pstate
, OP_LONG
);
4325 write_exp_elt_opcode (&p
->pstate
, UNOP_NEG
);
4328 write_exp_elt_opcode (&p
->pstate
, OP_REGISTER
);
4329 base_token
.ptr
= base
;
4330 base_token
.length
= len_base
;
4331 write_exp_string (&p
->pstate
, base_token
);
4332 write_exp_elt_opcode (&p
->pstate
, OP_REGISTER
);
4335 write_exp_elt_opcode (&p
->pstate
, BINOP_ADD
);
4337 write_exp_elt_opcode (&p
->pstate
, OP_REGISTER
);
4338 index_token
.ptr
= index
;
4339 index_token
.length
= len_index
;
4340 write_exp_string (&p
->pstate
, index_token
);
4341 write_exp_elt_opcode (&p
->pstate
, OP_REGISTER
);
4345 write_exp_elt_opcode (&p
->pstate
, OP_LONG
);
4346 write_exp_elt_type (&p
->pstate
,
4347 builtin_type (gdbarch
)->builtin_long
);
4348 write_exp_elt_longcst (&p
->pstate
, size
);
4349 write_exp_elt_opcode (&p
->pstate
, OP_LONG
);
4351 write_exp_elt_opcode (&p
->pstate
, UNOP_NEG
);
4352 write_exp_elt_opcode (&p
->pstate
, BINOP_MUL
);
4355 write_exp_elt_opcode (&p
->pstate
, BINOP_ADD
);
4357 write_exp_elt_opcode (&p
->pstate
, UNOP_CAST
);
4358 write_exp_elt_type (&p
->pstate
,
4359 lookup_pointer_type (p
->arg_type
));
4360 write_exp_elt_opcode (&p
->pstate
, UNOP_CAST
);
4362 write_exp_elt_opcode (&p
->pstate
, UNOP_IND
);
4372 /* Implementation of `gdbarch_stap_parse_special_token', as defined in
4376 i386_stap_parse_special_token (struct gdbarch
*gdbarch
,
4377 struct stap_parse_info
*p
)
4379 /* In order to parse special tokens, we use a state-machine that go
4380 through every known token and try to get a match. */
4384 THREE_ARG_DISPLACEMENT
,
4389 current_state
= TRIPLET
;
4391 /* The special tokens to be parsed here are:
4393 - `register base + (register index * size) + offset', as represented
4394 in `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'.
4396 - Operands of the form `-8+3+1(%rbp)', which must be interpreted as
4397 `*(-8 + 3 - 1 + (void *) $eax)'. */
4399 while (current_state
!= DONE
)
4401 switch (current_state
)
4404 if (i386_stap_parse_special_token_triplet (gdbarch
, p
))
4408 case THREE_ARG_DISPLACEMENT
:
4409 if (i386_stap_parse_special_token_three_arg_disp (gdbarch
, p
))
4414 /* Advancing to the next state. */
4423 /* gdbarch gnu_triplet_regexp method. Both arches are acceptable as GDB always
4424 also supplies -m64 or -m32 by gdbarch_gcc_target_options. */
4427 i386_gnu_triplet_regexp (struct gdbarch
*gdbarch
)
4429 return "(x86_64|i.86)";
4437 i386_elf_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
4439 static const char *const stap_integer_prefixes
[] = { "$", NULL
};
4440 static const char *const stap_register_prefixes
[] = { "%", NULL
};
4441 static const char *const stap_register_indirection_prefixes
[] = { "(",
4443 static const char *const stap_register_indirection_suffixes
[] = { ")",
4446 /* We typically use stabs-in-ELF with the SVR4 register numbering. */
4447 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
4449 /* Registering SystemTap handlers. */
4450 set_gdbarch_stap_integer_prefixes (gdbarch
, stap_integer_prefixes
);
4451 set_gdbarch_stap_register_prefixes (gdbarch
, stap_register_prefixes
);
4452 set_gdbarch_stap_register_indirection_prefixes (gdbarch
,
4453 stap_register_indirection_prefixes
);
4454 set_gdbarch_stap_register_indirection_suffixes (gdbarch
,
4455 stap_register_indirection_suffixes
);
4456 set_gdbarch_stap_is_single_operand (gdbarch
,
4457 i386_stap_is_single_operand
);
4458 set_gdbarch_stap_parse_special_token (gdbarch
,
4459 i386_stap_parse_special_token
);
4462 /* System V Release 4 (SVR4). */
4465 i386_svr4_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
4467 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4469 /* System V Release 4 uses ELF. */
4470 i386_elf_init_abi (info
, gdbarch
);
4472 /* System V Release 4 has shared libraries. */
4473 set_gdbarch_skip_trampoline_code (gdbarch
, find_solib_trampoline_target
);
4475 tdep
->sigtramp_p
= i386_svr4_sigtramp_p
;
4476 tdep
->sigcontext_addr
= i386_svr4_sigcontext_addr
;
4477 tdep
->sc_pc_offset
= 36 + 14 * 4;
4478 tdep
->sc_sp_offset
= 36 + 17 * 4;
4480 tdep
->jb_pc_offset
= 20;
4485 /* i386 register groups. In addition to the normal groups, add "mmx"
4488 static struct reggroup
*i386_sse_reggroup
;
4489 static struct reggroup
*i386_mmx_reggroup
;
4492 i386_init_reggroups (void)
4494 i386_sse_reggroup
= reggroup_new ("sse", USER_REGGROUP
);
4495 i386_mmx_reggroup
= reggroup_new ("mmx", USER_REGGROUP
);
4499 i386_add_reggroups (struct gdbarch
*gdbarch
)
4501 reggroup_add (gdbarch
, i386_sse_reggroup
);
4502 reggroup_add (gdbarch
, i386_mmx_reggroup
);
4503 reggroup_add (gdbarch
, general_reggroup
);
4504 reggroup_add (gdbarch
, float_reggroup
);
4505 reggroup_add (gdbarch
, all_reggroup
);
4506 reggroup_add (gdbarch
, save_reggroup
);
4507 reggroup_add (gdbarch
, restore_reggroup
);
4508 reggroup_add (gdbarch
, vector_reggroup
);
4509 reggroup_add (gdbarch
, system_reggroup
);
4513 i386_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
4514 struct reggroup
*group
)
4516 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4517 int fp_regnum_p
, mmx_regnum_p
, xmm_regnum_p
, mxcsr_regnum_p
,
4518 ymm_regnum_p
, ymmh_regnum_p
, ymm_avx512_regnum_p
, ymmh_avx512_regnum_p
,
4519 bndr_regnum_p
, bnd_regnum_p
, k_regnum_p
, zmm_regnum_p
, zmmh_regnum_p
,
4520 zmm_avx512_regnum_p
, mpx_ctrl_regnum_p
, xmm_avx512_regnum_p
,
4521 avx512_p
, avx_p
, sse_p
, pkru_regnum_p
;
4523 /* Don't include pseudo registers, except for MMX, in any register
4525 if (i386_byte_regnum_p (gdbarch
, regnum
))
4528 if (i386_word_regnum_p (gdbarch
, regnum
))
4531 if (i386_dword_regnum_p (gdbarch
, regnum
))
4534 mmx_regnum_p
= i386_mmx_regnum_p (gdbarch
, regnum
);
4535 if (group
== i386_mmx_reggroup
)
4536 return mmx_regnum_p
;
4538 pkru_regnum_p
= i386_pkru_regnum_p(gdbarch
, regnum
);
4539 xmm_regnum_p
= i386_xmm_regnum_p (gdbarch
, regnum
);
4540 xmm_avx512_regnum_p
= i386_xmm_avx512_regnum_p (gdbarch
, regnum
);
4541 mxcsr_regnum_p
= i386_mxcsr_regnum_p (gdbarch
, regnum
);
4542 if (group
== i386_sse_reggroup
)
4543 return xmm_regnum_p
|| xmm_avx512_regnum_p
|| mxcsr_regnum_p
;
4545 ymm_regnum_p
= i386_ymm_regnum_p (gdbarch
, regnum
);
4546 ymm_avx512_regnum_p
= i386_ymm_avx512_regnum_p (gdbarch
, regnum
);
4547 zmm_regnum_p
= i386_zmm_regnum_p (gdbarch
, regnum
);
4549 avx512_p
= ((tdep
->xcr0
& X86_XSTATE_AVX_AVX512_MASK
)
4550 == X86_XSTATE_AVX_AVX512_MASK
);
4551 avx_p
= ((tdep
->xcr0
& X86_XSTATE_AVX_AVX512_MASK
)
4552 == X86_XSTATE_AVX_MASK
) && !avx512_p
;
4553 sse_p
= ((tdep
->xcr0
& X86_XSTATE_AVX_AVX512_MASK
)
4554 == X86_XSTATE_SSE_MASK
) && !avx512_p
&& ! avx_p
;
4556 if (group
== vector_reggroup
)
4557 return (mmx_regnum_p
4558 || (zmm_regnum_p
&& avx512_p
)
4559 || ((ymm_regnum_p
|| ymm_avx512_regnum_p
) && avx_p
)
4560 || ((xmm_regnum_p
|| xmm_avx512_regnum_p
) && sse_p
)
4563 fp_regnum_p
= (i386_fp_regnum_p (gdbarch
, regnum
)
4564 || i386_fpc_regnum_p (gdbarch
, regnum
));
4565 if (group
== float_reggroup
)
4568 /* For "info reg all", don't include upper YMM registers nor XMM
4569 registers when AVX is supported. */
4570 ymmh_regnum_p
= i386_ymmh_regnum_p (gdbarch
, regnum
);
4571 ymmh_avx512_regnum_p
= i386_ymmh_avx512_regnum_p (gdbarch
, regnum
);
4572 zmmh_regnum_p
= i386_zmmh_regnum_p (gdbarch
, regnum
);
4573 if (group
== all_reggroup
4574 && (((xmm_regnum_p
|| xmm_avx512_regnum_p
) && !sse_p
)
4575 || ((ymm_regnum_p
|| ymm_avx512_regnum_p
) && !avx_p
)
4577 || ymmh_avx512_regnum_p
4581 bnd_regnum_p
= i386_bnd_regnum_p (gdbarch
, regnum
);
4582 if (group
== all_reggroup
4583 && ((bnd_regnum_p
&& (tdep
->xcr0
& X86_XSTATE_MPX_MASK
))))
4584 return bnd_regnum_p
;
4586 bndr_regnum_p
= i386_bndr_regnum_p (gdbarch
, regnum
);
4587 if (group
== all_reggroup
4588 && ((bndr_regnum_p
&& (tdep
->xcr0
& X86_XSTATE_MPX_MASK
))))
4591 mpx_ctrl_regnum_p
= i386_mpx_ctrl_regnum_p (gdbarch
, regnum
);
4592 if (group
== all_reggroup
4593 && ((mpx_ctrl_regnum_p
&& (tdep
->xcr0
& X86_XSTATE_MPX_MASK
))))
4594 return mpx_ctrl_regnum_p
;
4596 if (group
== general_reggroup
)
4597 return (!fp_regnum_p
4601 && !xmm_avx512_regnum_p
4604 && !ymm_avx512_regnum_p
4605 && !ymmh_avx512_regnum_p
4608 && !mpx_ctrl_regnum_p
4613 return default_register_reggroup_p (gdbarch
, regnum
, group
);
4617 /* Get the ARGIth function argument for the current function. */
4620 i386_fetch_pointer_argument (struct frame_info
*frame
, int argi
,
4623 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4624 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4625 CORE_ADDR sp
= get_frame_register_unsigned (frame
, I386_ESP_REGNUM
);
4626 return read_memory_unsigned_integer (sp
+ (4 * (argi
+ 1)), 4, byte_order
);
4629 #define PREFIX_REPZ 0x01
4630 #define PREFIX_REPNZ 0x02
4631 #define PREFIX_LOCK 0x04
4632 #define PREFIX_DATA 0x08
4633 #define PREFIX_ADDR 0x10
4645 /* i386 arith/logic operations */
4658 struct i386_record_s
4660 struct gdbarch
*gdbarch
;
4661 struct regcache
*regcache
;
4662 CORE_ADDR orig_addr
;
4668 uint8_t mod
, reg
, rm
;
4677 /* Parse the "modrm" part of the memory address irp->addr points at.
4678 Returns -1 if something goes wrong, 0 otherwise. */
4681 i386_record_modrm (struct i386_record_s
*irp
)
4683 struct gdbarch
*gdbarch
= irp
->gdbarch
;
4685 if (record_read_memory (gdbarch
, irp
->addr
, &irp
->modrm
, 1))
4689 irp
->mod
= (irp
->modrm
>> 6) & 3;
4690 irp
->reg
= (irp
->modrm
>> 3) & 7;
4691 irp
->rm
= irp
->modrm
& 7;
4696 /* Extract the memory address that the current instruction writes to,
4697 and return it in *ADDR. Return -1 if something goes wrong. */
4700 i386_record_lea_modrm_addr (struct i386_record_s
*irp
, uint64_t *addr
)
4702 struct gdbarch
*gdbarch
= irp
->gdbarch
;
4703 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4708 if (irp
->aflag
|| irp
->regmap
[X86_RECORD_R8_REGNUM
])
4715 uint8_t base
= irp
->rm
;
4720 if (record_read_memory (gdbarch
, irp
->addr
, &byte
, 1))
4723 scale
= (byte
>> 6) & 3;
4724 index
= ((byte
>> 3) & 7) | irp
->rex_x
;
4732 if ((base
& 7) == 5)
4735 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 4))
4738 *addr
= extract_signed_integer (buf
, 4, byte_order
);
4739 if (irp
->regmap
[X86_RECORD_R8_REGNUM
] && !havesib
)
4740 *addr
+= irp
->addr
+ irp
->rip_offset
;
4744 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 1))
4747 *addr
= (int8_t) buf
[0];
4750 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 4))
4752 *addr
= extract_signed_integer (buf
, 4, byte_order
);
4760 if (base
== 4 && irp
->popl_esp_hack
)
4761 *addr
+= irp
->popl_esp_hack
;
4762 regcache_raw_read_unsigned (irp
->regcache
, irp
->regmap
[base
],
4765 if (irp
->aflag
== 2)
4770 *addr
= (uint32_t) (offset64
+ *addr
);
4772 if (havesib
&& (index
!= 4 || scale
!= 0))
4774 regcache_raw_read_unsigned (irp
->regcache
, irp
->regmap
[index
],
4776 if (irp
->aflag
== 2)
4777 *addr
+= offset64
<< scale
;
4779 *addr
= (uint32_t) (*addr
+ (offset64
<< scale
));
4784 /* Since we are in 64-bit mode with ADDR32 prefix, zero-extend
4785 address from 32-bit to 64-bit. */
4786 *addr
= (uint32_t) *addr
;
4797 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 2))
4800 *addr
= extract_signed_integer (buf
, 2, byte_order
);
4806 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 1))
4809 *addr
= (int8_t) buf
[0];
4812 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 2))
4815 *addr
= extract_signed_integer (buf
, 2, byte_order
);
4822 regcache_raw_read_unsigned (irp
->regcache
,
4823 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
4825 *addr
= (uint32_t) (*addr
+ offset64
);
4826 regcache_raw_read_unsigned (irp
->regcache
,
4827 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
4829 *addr
= (uint32_t) (*addr
+ offset64
);
4832 regcache_raw_read_unsigned (irp
->regcache
,
4833 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
4835 *addr
= (uint32_t) (*addr
+ offset64
);
4836 regcache_raw_read_unsigned (irp
->regcache
,
4837 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
4839 *addr
= (uint32_t) (*addr
+ offset64
);
4842 regcache_raw_read_unsigned (irp
->regcache
,
4843 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
4845 *addr
= (uint32_t) (*addr
+ offset64
);
4846 regcache_raw_read_unsigned (irp
->regcache
,
4847 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
4849 *addr
= (uint32_t) (*addr
+ offset64
);
4852 regcache_raw_read_unsigned (irp
->regcache
,
4853 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
4855 *addr
= (uint32_t) (*addr
+ offset64
);
4856 regcache_raw_read_unsigned (irp
->regcache
,
4857 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
4859 *addr
= (uint32_t) (*addr
+ offset64
);
4862 regcache_raw_read_unsigned (irp
->regcache
,
4863 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
4865 *addr
= (uint32_t) (*addr
+ offset64
);
4868 regcache_raw_read_unsigned (irp
->regcache
,
4869 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
4871 *addr
= (uint32_t) (*addr
+ offset64
);
4874 regcache_raw_read_unsigned (irp
->regcache
,
4875 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
4877 *addr
= (uint32_t) (*addr
+ offset64
);
4880 regcache_raw_read_unsigned (irp
->regcache
,
4881 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
4883 *addr
= (uint32_t) (*addr
+ offset64
);
4893 /* Record the address and contents of the memory that will be changed
4894 by the current instruction. Return -1 if something goes wrong, 0
4898 i386_record_lea_modrm (struct i386_record_s
*irp
)
4900 struct gdbarch
*gdbarch
= irp
->gdbarch
;
4903 if (irp
->override
>= 0)
4905 if (record_full_memory_query
)
4908 Process record ignores the memory change of instruction at address %s\n\
4909 because it can't get the value of the segment register.\n\
4910 Do you want to stop the program?"),
4911 paddress (gdbarch
, irp
->orig_addr
)))
4918 if (i386_record_lea_modrm_addr (irp
, &addr
))
4921 if (record_full_arch_list_add_mem (addr
, 1 << irp
->ot
))
4927 /* Record the effects of a push operation. Return -1 if something
4928 goes wrong, 0 otherwise. */
4931 i386_record_push (struct i386_record_s
*irp
, int size
)
4935 if (record_full_arch_list_add_reg (irp
->regcache
,
4936 irp
->regmap
[X86_RECORD_RESP_REGNUM
]))
4938 regcache_raw_read_unsigned (irp
->regcache
,
4939 irp
->regmap
[X86_RECORD_RESP_REGNUM
],
4941 if (record_full_arch_list_add_mem ((CORE_ADDR
) addr
- size
, size
))
4948 /* Defines contents to record. */
4949 #define I386_SAVE_FPU_REGS 0xfffd
4950 #define I386_SAVE_FPU_ENV 0xfffe
4951 #define I386_SAVE_FPU_ENV_REG_STACK 0xffff
4953 /* Record the values of the floating point registers which will be
4954 changed by the current instruction. Returns -1 if something is
4955 wrong, 0 otherwise. */
4957 static int i386_record_floats (struct gdbarch
*gdbarch
,
4958 struct i386_record_s
*ir
,
4961 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4964 /* Oza: Because of floating point insn push/pop of fpu stack is going to
4965 happen. Currently we store st0-st7 registers, but we need not store all
4966 registers all the time, in future we use ftag register and record only
4967 those who are not marked as an empty. */
4969 if (I386_SAVE_FPU_REGS
== iregnum
)
4971 for (i
= I387_ST0_REGNUM (tdep
); i
<= I387_ST0_REGNUM (tdep
) + 7; i
++)
4973 if (record_full_arch_list_add_reg (ir
->regcache
, i
))
4977 else if (I386_SAVE_FPU_ENV
== iregnum
)
4979 for (i
= I387_FCTRL_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
4981 if (record_full_arch_list_add_reg (ir
->regcache
, i
))
4985 else if (I386_SAVE_FPU_ENV_REG_STACK
== iregnum
)
4987 for (i
= I387_ST0_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
4989 if (record_full_arch_list_add_reg (ir
->regcache
, i
))
4993 else if ((iregnum
>= I387_ST0_REGNUM (tdep
)) &&
4994 (iregnum
<= I387_FOP_REGNUM (tdep
)))
4996 if (record_full_arch_list_add_reg (ir
->regcache
,iregnum
))
5001 /* Parameter error. */
5004 if(I386_SAVE_FPU_ENV
!= iregnum
)
5006 for (i
= I387_FCTRL_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
5008 if (record_full_arch_list_add_reg (ir
->regcache
, i
))
5015 /* Parse the current instruction, and record the values of the
5016 registers and memory that will be changed by the current
5017 instruction. Returns -1 if something goes wrong, 0 otherwise. */
5019 #define I386_RECORD_FULL_ARCH_LIST_ADD_REG(regnum) \
5020 record_full_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)])
5023 i386_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5024 CORE_ADDR input_addr
)
5026 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5032 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
5033 struct i386_record_s ir
;
5034 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5038 memset (&ir
, 0, sizeof (struct i386_record_s
));
5039 ir
.regcache
= regcache
;
5040 ir
.addr
= input_addr
;
5041 ir
.orig_addr
= input_addr
;
5045 ir
.popl_esp_hack
= 0;
5046 ir
.regmap
= tdep
->record_regmap
;
5047 ir
.gdbarch
= gdbarch
;
5049 if (record_debug
> 1)
5050 fprintf_unfiltered (gdb_stdlog
, "Process record: i386_process_record "
5052 paddress (gdbarch
, ir
.addr
));
5057 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
5060 switch (opcode8
) /* Instruction prefixes */
5062 case REPE_PREFIX_OPCODE
:
5063 prefixes
|= PREFIX_REPZ
;
5065 case REPNE_PREFIX_OPCODE
:
5066 prefixes
|= PREFIX_REPNZ
;
5068 case LOCK_PREFIX_OPCODE
:
5069 prefixes
|= PREFIX_LOCK
;
5071 case CS_PREFIX_OPCODE
:
5072 ir
.override
= X86_RECORD_CS_REGNUM
;
5074 case SS_PREFIX_OPCODE
:
5075 ir
.override
= X86_RECORD_SS_REGNUM
;
5077 case DS_PREFIX_OPCODE
:
5078 ir
.override
= X86_RECORD_DS_REGNUM
;
5080 case ES_PREFIX_OPCODE
:
5081 ir
.override
= X86_RECORD_ES_REGNUM
;
5083 case FS_PREFIX_OPCODE
:
5084 ir
.override
= X86_RECORD_FS_REGNUM
;
5086 case GS_PREFIX_OPCODE
:
5087 ir
.override
= X86_RECORD_GS_REGNUM
;
5089 case DATA_PREFIX_OPCODE
:
5090 prefixes
|= PREFIX_DATA
;
5092 case ADDR_PREFIX_OPCODE
:
5093 prefixes
|= PREFIX_ADDR
;
5095 case 0x40: /* i386 inc %eax */
5096 case 0x41: /* i386 inc %ecx */
5097 case 0x42: /* i386 inc %edx */
5098 case 0x43: /* i386 inc %ebx */
5099 case 0x44: /* i386 inc %esp */
5100 case 0x45: /* i386 inc %ebp */
5101 case 0x46: /* i386 inc %esi */
5102 case 0x47: /* i386 inc %edi */
5103 case 0x48: /* i386 dec %eax */
5104 case 0x49: /* i386 dec %ecx */
5105 case 0x4a: /* i386 dec %edx */
5106 case 0x4b: /* i386 dec %ebx */
5107 case 0x4c: /* i386 dec %esp */
5108 case 0x4d: /* i386 dec %ebp */
5109 case 0x4e: /* i386 dec %esi */
5110 case 0x4f: /* i386 dec %edi */
5111 if (ir
.regmap
[X86_RECORD_R8_REGNUM
]) /* 64 bit target */
5114 rex_w
= (opcode8
>> 3) & 1;
5115 rex_r
= (opcode8
& 0x4) << 1;
5116 ir
.rex_x
= (opcode8
& 0x2) << 2;
5117 ir
.rex_b
= (opcode8
& 0x1) << 3;
5119 else /* 32 bit target */
5128 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && rex_w
== 1)
5134 if (prefixes
& PREFIX_DATA
)
5137 if (prefixes
& PREFIX_ADDR
)
5139 else if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5142 /* Now check op code. */
5143 opcode
= (uint32_t) opcode8
;
5148 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
5151 opcode
= (uint32_t) opcode8
| 0x0f00;
5155 case 0x00: /* arith & logic */
5203 if (((opcode
>> 3) & 7) != OP_CMPL
)
5205 if ((opcode
& 1) == 0)
5208 ir
.ot
= ir
.dflag
+ OT_WORD
;
5210 switch ((opcode
>> 1) & 3)
5212 case 0: /* OP Ev, Gv */
5213 if (i386_record_modrm (&ir
))
5217 if (i386_record_lea_modrm (&ir
))
5223 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5225 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5228 case 1: /* OP Gv, Ev */
5229 if (i386_record_modrm (&ir
))
5232 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5234 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5236 case 2: /* OP A, Iv */
5237 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5241 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5244 case 0x80: /* GRP1 */
5248 if (i386_record_modrm (&ir
))
5251 if (ir
.reg
!= OP_CMPL
)
5253 if ((opcode
& 1) == 0)
5256 ir
.ot
= ir
.dflag
+ OT_WORD
;
5263 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
5264 if (i386_record_lea_modrm (&ir
))
5268 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5270 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5273 case 0x40: /* inc */
5282 case 0x48: /* dec */
5291 I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode
& 7);
5292 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5295 case 0xf6: /* GRP3 */
5297 if ((opcode
& 1) == 0)
5300 ir
.ot
= ir
.dflag
+ OT_WORD
;
5301 if (i386_record_modrm (&ir
))
5304 if (ir
.mod
!= 3 && ir
.reg
== 0)
5305 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
5310 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5316 if (i386_record_lea_modrm (&ir
))
5322 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5324 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5326 if (ir
.reg
== 3) /* neg */
5327 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5333 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5334 if (ir
.ot
!= OT_BYTE
)
5335 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5336 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5340 opcode
= opcode
<< 8 | ir
.modrm
;
5346 case 0xfe: /* GRP4 */
5347 case 0xff: /* GRP5 */
5348 if (i386_record_modrm (&ir
))
5350 if (ir
.reg
>= 2 && opcode
== 0xfe)
5353 opcode
= opcode
<< 8 | ir
.modrm
;
5360 if ((opcode
& 1) == 0)
5363 ir
.ot
= ir
.dflag
+ OT_WORD
;
5366 if (i386_record_lea_modrm (&ir
))
5372 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5374 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5376 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5379 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5381 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5383 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5386 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
5387 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5389 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5393 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5396 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5398 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5403 opcode
= opcode
<< 8 | ir
.modrm
;
5409 case 0x84: /* test */
5413 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5416 case 0x98: /* CWDE/CBW */
5417 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5420 case 0x99: /* CDQ/CWD */
5421 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5422 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5425 case 0x0faf: /* imul */
5428 ir
.ot
= ir
.dflag
+ OT_WORD
;
5429 if (i386_record_modrm (&ir
))
5432 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
5433 else if (opcode
== 0x6b)
5436 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5438 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5439 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5442 case 0x0fc0: /* xadd */
5444 if ((opcode
& 1) == 0)
5447 ir
.ot
= ir
.dflag
+ OT_WORD
;
5448 if (i386_record_modrm (&ir
))
5453 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5455 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5456 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5458 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5462 if (i386_record_lea_modrm (&ir
))
5464 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5466 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5468 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5471 case 0x0fb0: /* cmpxchg */
5473 if ((opcode
& 1) == 0)
5476 ir
.ot
= ir
.dflag
+ OT_WORD
;
5477 if (i386_record_modrm (&ir
))
5482 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5483 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5485 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5489 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5490 if (i386_record_lea_modrm (&ir
))
5493 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5496 case 0x0fc7: /* cmpxchg8b / rdrand / rdseed */
5497 if (i386_record_modrm (&ir
))
5501 /* rdrand and rdseed use the 3 bits of the REG field of ModR/M as
5502 an extended opcode. rdrand has bits 110 (/6) and rdseed
5503 has bits 111 (/7). */
5504 if (ir
.reg
== 6 || ir
.reg
== 7)
5506 /* The storage register is described by the 3 R/M bits, but the
5507 REX.B prefix may be used to give access to registers
5508 R8~R15. In this case ir.rex_b + R/M will give us the register
5509 in the range R8~R15.
5511 REX.W may also be used to access 64-bit registers, but we
5512 already record entire registers and not just partial bits
5514 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rex_b
+ ir
.rm
);
5515 /* These instructions also set conditional bits. */
5516 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5521 /* We don't handle this particular instruction yet. */
5523 opcode
= opcode
<< 8 | ir
.modrm
;
5527 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5528 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5529 if (i386_record_lea_modrm (&ir
))
5531 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5534 case 0x50: /* push */
5544 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5546 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5550 case 0x06: /* push es */
5551 case 0x0e: /* push cs */
5552 case 0x16: /* push ss */
5553 case 0x1e: /* push ds */
5554 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5559 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5563 case 0x0fa0: /* push fs */
5564 case 0x0fa8: /* push gs */
5565 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5570 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5574 case 0x60: /* pusha */
5575 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5580 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 4)))
5584 case 0x58: /* pop */
5592 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5593 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode
& 0x7) | ir
.rex_b
);
5596 case 0x61: /* popa */
5597 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5602 for (regnum
= X86_RECORD_REAX_REGNUM
;
5603 regnum
<= X86_RECORD_REDI_REGNUM
;
5605 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum
);
5608 case 0x8f: /* pop */
5609 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5610 ir
.ot
= ir
.dflag
? OT_QUAD
: OT_WORD
;
5612 ir
.ot
= ir
.dflag
+ OT_WORD
;
5613 if (i386_record_modrm (&ir
))
5616 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5619 ir
.popl_esp_hack
= 1 << ir
.ot
;
5620 if (i386_record_lea_modrm (&ir
))
5623 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5626 case 0xc8: /* enter */
5627 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
5628 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5630 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5634 case 0xc9: /* leave */
5635 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5636 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
5639 case 0x07: /* pop es */
5640 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5645 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5646 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM
);
5647 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5650 case 0x17: /* pop ss */
5651 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5656 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5657 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM
);
5658 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5661 case 0x1f: /* pop ds */
5662 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5667 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5668 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM
);
5669 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5672 case 0x0fa1: /* pop fs */
5673 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5674 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM
);
5675 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5678 case 0x0fa9: /* pop gs */
5679 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5680 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM
);
5681 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5684 case 0x88: /* mov */
5688 if ((opcode
& 1) == 0)
5691 ir
.ot
= ir
.dflag
+ OT_WORD
;
5693 if (i386_record_modrm (&ir
))
5698 if (opcode
== 0xc6 || opcode
== 0xc7)
5699 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
5700 if (i386_record_lea_modrm (&ir
))
5705 if (opcode
== 0xc6 || opcode
== 0xc7)
5707 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5709 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5713 case 0x8a: /* mov */
5715 if ((opcode
& 1) == 0)
5718 ir
.ot
= ir
.dflag
+ OT_WORD
;
5719 if (i386_record_modrm (&ir
))
5722 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5724 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5727 case 0x8c: /* mov seg */
5728 if (i386_record_modrm (&ir
))
5733 opcode
= opcode
<< 8 | ir
.modrm
;
5738 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5742 if (i386_record_lea_modrm (&ir
))
5747 case 0x8e: /* mov seg */
5748 if (i386_record_modrm (&ir
))
5753 regnum
= X86_RECORD_ES_REGNUM
;
5756 regnum
= X86_RECORD_SS_REGNUM
;
5759 regnum
= X86_RECORD_DS_REGNUM
;
5762 regnum
= X86_RECORD_FS_REGNUM
;
5765 regnum
= X86_RECORD_GS_REGNUM
;
5769 opcode
= opcode
<< 8 | ir
.modrm
;
5773 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum
);
5774 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5777 case 0x0fb6: /* movzbS */
5778 case 0x0fb7: /* movzwS */
5779 case 0x0fbe: /* movsbS */
5780 case 0x0fbf: /* movswS */
5781 if (i386_record_modrm (&ir
))
5783 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
5786 case 0x8d: /* lea */
5787 if (i386_record_modrm (&ir
))
5792 opcode
= opcode
<< 8 | ir
.modrm
;
5797 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5799 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5802 case 0xa0: /* mov EAX */
5805 case 0xd7: /* xlat */
5806 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5809 case 0xa2: /* mov EAX */
5811 if (ir
.override
>= 0)
5813 if (record_full_memory_query
)
5816 Process record ignores the memory change of instruction at address %s\n\
5817 because it can't get the value of the segment register.\n\
5818 Do you want to stop the program?"),
5819 paddress (gdbarch
, ir
.orig_addr
)))
5825 if ((opcode
& 1) == 0)
5828 ir
.ot
= ir
.dflag
+ OT_WORD
;
5831 if (record_read_memory (gdbarch
, ir
.addr
, buf
, 8))
5834 addr
= extract_unsigned_integer (buf
, 8, byte_order
);
5838 if (record_read_memory (gdbarch
, ir
.addr
, buf
, 4))
5841 addr
= extract_unsigned_integer (buf
, 4, byte_order
);
5845 if (record_read_memory (gdbarch
, ir
.addr
, buf
, 2))
5848 addr
= extract_unsigned_integer (buf
, 2, byte_order
);
5850 if (record_full_arch_list_add_mem (addr
, 1 << ir
.ot
))
5855 case 0xb0: /* mov R, Ib */
5863 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((ir
.regmap
[X86_RECORD_R8_REGNUM
])
5864 ? ((opcode
& 0x7) | ir
.rex_b
)
5865 : ((opcode
& 0x7) & 0x3));
5868 case 0xb8: /* mov R, Iv */
5876 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode
& 0x7) | ir
.rex_b
);
5879 case 0x91: /* xchg R, EAX */
5886 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5887 I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode
& 0x7);
5890 case 0x86: /* xchg Ev, Gv */
5892 if ((opcode
& 1) == 0)
5895 ir
.ot
= ir
.dflag
+ OT_WORD
;
5896 if (i386_record_modrm (&ir
))
5901 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5903 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5907 if (i386_record_lea_modrm (&ir
))
5911 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5913 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5916 case 0xc4: /* les Gv */
5917 case 0xc5: /* lds Gv */
5918 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5924 case 0x0fb2: /* lss Gv */
5925 case 0x0fb4: /* lfs Gv */
5926 case 0x0fb5: /* lgs Gv */
5927 if (i386_record_modrm (&ir
))
5935 opcode
= opcode
<< 8 | ir
.modrm
;
5940 case 0xc4: /* les Gv */
5941 regnum
= X86_RECORD_ES_REGNUM
;
5943 case 0xc5: /* lds Gv */
5944 regnum
= X86_RECORD_DS_REGNUM
;
5946 case 0x0fb2: /* lss Gv */
5947 regnum
= X86_RECORD_SS_REGNUM
;
5949 case 0x0fb4: /* lfs Gv */
5950 regnum
= X86_RECORD_FS_REGNUM
;
5952 case 0x0fb5: /* lgs Gv */
5953 regnum
= X86_RECORD_GS_REGNUM
;
5956 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum
);
5957 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
5958 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5961 case 0xc0: /* shifts */
5967 if ((opcode
& 1) == 0)
5970 ir
.ot
= ir
.dflag
+ OT_WORD
;
5971 if (i386_record_modrm (&ir
))
5973 if (ir
.mod
!= 3 && (opcode
== 0xd2 || opcode
== 0xd3))
5975 if (i386_record_lea_modrm (&ir
))
5981 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5983 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5985 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5992 if (i386_record_modrm (&ir
))
5996 if (record_full_arch_list_add_reg (ir
.regcache
, ir
.rm
))
6001 if (i386_record_lea_modrm (&ir
))
6006 case 0xd8: /* Floats. */
6014 if (i386_record_modrm (&ir
))
6016 ir
.reg
|= ((opcode
& 7) << 3);
6022 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
6030 /* For fcom, ficom nothing to do. */
6036 /* For fcomp, ficomp pop FPU stack, store all. */
6037 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
6064 /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul,
6065 fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension
6066 of code, always affects st(0) register. */
6067 if (i386_record_floats (gdbarch
, &ir
, I387_ST0_REGNUM (tdep
)))
6091 /* Handling fld, fild. */
6092 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
6096 switch (ir
.reg
>> 4)
6099 if (record_full_arch_list_add_mem (addr64
, 4))
6103 if (record_full_arch_list_add_mem (addr64
, 8))
6109 if (record_full_arch_list_add_mem (addr64
, 2))
6115 switch (ir
.reg
>> 4)
6118 if (record_full_arch_list_add_mem (addr64
, 4))
6120 if (3 == (ir
.reg
& 7))
6122 /* For fstp m32fp. */
6123 if (i386_record_floats (gdbarch
, &ir
,
6124 I386_SAVE_FPU_REGS
))
6129 if (record_full_arch_list_add_mem (addr64
, 4))
6131 if ((3 == (ir
.reg
& 7))
6132 || (5 == (ir
.reg
& 7))
6133 || (7 == (ir
.reg
& 7)))
6135 /* For fstp insn. */
6136 if (i386_record_floats (gdbarch
, &ir
,
6137 I386_SAVE_FPU_REGS
))
6142 if (record_full_arch_list_add_mem (addr64
, 8))
6144 if (3 == (ir
.reg
& 7))
6146 /* For fstp m64fp. */
6147 if (i386_record_floats (gdbarch
, &ir
,
6148 I386_SAVE_FPU_REGS
))
6153 if ((3 <= (ir
.reg
& 7)) && (6 <= (ir
.reg
& 7)))
6155 /* For fistp, fbld, fild, fbstp. */
6156 if (i386_record_floats (gdbarch
, &ir
,
6157 I386_SAVE_FPU_REGS
))
6162 if (record_full_arch_list_add_mem (addr64
, 2))
6171 if (i386_record_floats (gdbarch
, &ir
,
6172 I386_SAVE_FPU_ENV_REG_STACK
))
6177 if (i386_record_floats (gdbarch
, &ir
, I387_FCTRL_REGNUM (tdep
)))
6182 if (i386_record_floats (gdbarch
, &ir
,
6183 I386_SAVE_FPU_ENV_REG_STACK
))
6189 if (record_full_arch_list_add_mem (addr64
, 28))
6194 if (record_full_arch_list_add_mem (addr64
, 14))
6200 if (record_full_arch_list_add_mem (addr64
, 2))
6202 /* Insn fstp, fbstp. */
6203 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
6208 if (record_full_arch_list_add_mem (addr64
, 10))
6214 if (record_full_arch_list_add_mem (addr64
, 28))
6220 if (record_full_arch_list_add_mem (addr64
, 14))
6224 if (record_full_arch_list_add_mem (addr64
, 80))
6227 if (i386_record_floats (gdbarch
, &ir
,
6228 I386_SAVE_FPU_ENV_REG_STACK
))
6232 if (record_full_arch_list_add_mem (addr64
, 8))
6235 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
6240 opcode
= opcode
<< 8 | ir
.modrm
;
6245 /* Opcode is an extension of modR/M byte. */
6251 if (i386_record_floats (gdbarch
, &ir
, I387_ST0_REGNUM (tdep
)))
6255 if (0x0c == (ir
.modrm
>> 4))
6257 if ((ir
.modrm
& 0x0f) <= 7)
6259 if (i386_record_floats (gdbarch
, &ir
,
6260 I386_SAVE_FPU_REGS
))
6265 if (i386_record_floats (gdbarch
, &ir
,
6266 I387_ST0_REGNUM (tdep
)))
6268 /* If only st(0) is changing, then we have already
6270 if ((ir
.modrm
& 0x0f) - 0x08)
6272 if (i386_record_floats (gdbarch
, &ir
,
6273 I387_ST0_REGNUM (tdep
) +
6274 ((ir
.modrm
& 0x0f) - 0x08)))
6292 if (i386_record_floats (gdbarch
, &ir
,
6293 I387_ST0_REGNUM (tdep
)))
6311 if (i386_record_floats (gdbarch
, &ir
,
6312 I386_SAVE_FPU_REGS
))
6316 if (i386_record_floats (gdbarch
, &ir
,
6317 I387_ST0_REGNUM (tdep
)))
6319 if (i386_record_floats (gdbarch
, &ir
,
6320 I387_ST0_REGNUM (tdep
) + 1))
6327 if (0xe9 == ir
.modrm
)
6329 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
6332 else if ((0x0c == ir
.modrm
>> 4) || (0x0d == ir
.modrm
>> 4))
6334 if (i386_record_floats (gdbarch
, &ir
,
6335 I387_ST0_REGNUM (tdep
)))
6337 if (((ir
.modrm
& 0x0f) > 0) && ((ir
.modrm
& 0x0f) <= 7))
6339 if (i386_record_floats (gdbarch
, &ir
,
6340 I387_ST0_REGNUM (tdep
) +
6344 else if ((ir
.modrm
& 0x0f) - 0x08)
6346 if (i386_record_floats (gdbarch
, &ir
,
6347 I387_ST0_REGNUM (tdep
) +
6348 ((ir
.modrm
& 0x0f) - 0x08)))
6354 if (0xe3 == ir
.modrm
)
6356 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_ENV
))
6359 else if ((0x0c == ir
.modrm
>> 4) || (0x0d == ir
.modrm
>> 4))
6361 if (i386_record_floats (gdbarch
, &ir
,
6362 I387_ST0_REGNUM (tdep
)))
6364 if (((ir
.modrm
& 0x0f) > 0) && ((ir
.modrm
& 0x0f) <= 7))
6366 if (i386_record_floats (gdbarch
, &ir
,
6367 I387_ST0_REGNUM (tdep
) +
6371 else if ((ir
.modrm
& 0x0f) - 0x08)
6373 if (i386_record_floats (gdbarch
, &ir
,
6374 I387_ST0_REGNUM (tdep
) +
6375 ((ir
.modrm
& 0x0f) - 0x08)))
6381 if ((0x0c == ir
.modrm
>> 4)
6382 || (0x0d == ir
.modrm
>> 4)
6383 || (0x0f == ir
.modrm
>> 4))
6385 if ((ir
.modrm
& 0x0f) <= 7)
6387 if (i386_record_floats (gdbarch
, &ir
,
6388 I387_ST0_REGNUM (tdep
) +
6394 if (i386_record_floats (gdbarch
, &ir
,
6395 I387_ST0_REGNUM (tdep
) +
6396 ((ir
.modrm
& 0x0f) - 0x08)))
6402 if (0x0c == ir
.modrm
>> 4)
6404 if (i386_record_floats (gdbarch
, &ir
,
6405 I387_FTAG_REGNUM (tdep
)))
6408 else if ((0x0d == ir
.modrm
>> 4) || (0x0e == ir
.modrm
>> 4))
6410 if ((ir
.modrm
& 0x0f) <= 7)
6412 if (i386_record_floats (gdbarch
, &ir
,
6413 I387_ST0_REGNUM (tdep
) +
6419 if (i386_record_floats (gdbarch
, &ir
,
6420 I386_SAVE_FPU_REGS
))
6426 if ((0x0c == ir
.modrm
>> 4)
6427 || (0x0e == ir
.modrm
>> 4)
6428 || (0x0f == ir
.modrm
>> 4)
6429 || (0xd9 == ir
.modrm
))
6431 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
6436 if (0xe0 == ir
.modrm
)
6438 if (record_full_arch_list_add_reg (ir
.regcache
,
6442 else if ((0x0f == ir
.modrm
>> 4) || (0x0e == ir
.modrm
>> 4))
6444 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
6452 case 0xa4: /* movsS */
6454 case 0xaa: /* stosS */
6456 case 0x6c: /* insS */
6458 regcache_raw_read_unsigned (ir
.regcache
,
6459 ir
.regmap
[X86_RECORD_RECX_REGNUM
],
6465 if ((opcode
& 1) == 0)
6468 ir
.ot
= ir
.dflag
+ OT_WORD
;
6469 regcache_raw_read_unsigned (ir
.regcache
,
6470 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
6473 regcache_raw_read_unsigned (ir
.regcache
,
6474 ir
.regmap
[X86_RECORD_ES_REGNUM
],
6476 regcache_raw_read_unsigned (ir
.regcache
,
6477 ir
.regmap
[X86_RECORD_DS_REGNUM
],
6479 if (ir
.aflag
&& (es
!= ds
))
6481 /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */
6482 if (record_full_memory_query
)
6485 Process record ignores the memory change of instruction at address %s\n\
6486 because it can't get the value of the segment register.\n\
6487 Do you want to stop the program?"),
6488 paddress (gdbarch
, ir
.orig_addr
)))
6494 if (record_full_arch_list_add_mem (addr
, 1 << ir
.ot
))
6498 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
6499 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6500 if (opcode
== 0xa4 || opcode
== 0xa5)
6501 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
6502 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
6503 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6507 case 0xa6: /* cmpsS */
6509 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
6510 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
6511 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
6512 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6513 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6516 case 0xac: /* lodsS */
6518 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6519 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
6520 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
6521 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6522 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6525 case 0xae: /* scasS */
6527 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
6528 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
6529 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6530 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6533 case 0x6e: /* outsS */
6535 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
6536 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
6537 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6538 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6541 case 0xe4: /* port I/O */
6545 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6546 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6556 case 0xc2: /* ret im */
6557 case 0xc3: /* ret */
6558 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
6559 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6562 case 0xca: /* lret im */
6563 case 0xcb: /* lret */
6564 case 0xcf: /* iret */
6565 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
6566 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
6567 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6570 case 0xe8: /* call im */
6571 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
6573 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
6577 case 0x9a: /* lcall im */
6578 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6583 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
6584 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
6588 case 0xe9: /* jmp im */
6589 case 0xea: /* ljmp im */
6590 case 0xeb: /* jmp Jb */
6591 case 0x70: /* jcc Jb */
6607 case 0x0f80: /* jcc Jv */
6625 case 0x0f90: /* setcc Gv */
6641 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6643 if (i386_record_modrm (&ir
))
6646 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rex_b
? (ir
.rm
| ir
.rex_b
)
6650 if (i386_record_lea_modrm (&ir
))
6655 case 0x0f40: /* cmov Gv, Ev */
6671 if (i386_record_modrm (&ir
))
6674 if (ir
.dflag
== OT_BYTE
)
6676 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
6680 case 0x9c: /* pushf */
6681 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6682 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
6684 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
6688 case 0x9d: /* popf */
6689 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
6690 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6693 case 0x9e: /* sahf */
6694 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6700 case 0xf5: /* cmc */
6701 case 0xf8: /* clc */
6702 case 0xf9: /* stc */
6703 case 0xfc: /* cld */
6704 case 0xfd: /* std */
6705 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6708 case 0x9f: /* lahf */
6709 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6714 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6715 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6718 /* bit operations */
6719 case 0x0fba: /* bt/bts/btr/btc Gv, im */
6720 ir
.ot
= ir
.dflag
+ OT_WORD
;
6721 if (i386_record_modrm (&ir
))
6726 opcode
= opcode
<< 8 | ir
.modrm
;
6732 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6735 if (i386_record_lea_modrm (&ir
))
6739 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6742 case 0x0fa3: /* bt Gv, Ev */
6743 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6746 case 0x0fab: /* bts */
6747 case 0x0fb3: /* btr */
6748 case 0x0fbb: /* btc */
6749 ir
.ot
= ir
.dflag
+ OT_WORD
;
6750 if (i386_record_modrm (&ir
))
6753 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6757 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
6759 regcache_raw_read_unsigned (ir
.regcache
,
6760 ir
.regmap
[ir
.reg
| rex_r
],
6765 addr64
+= ((int16_t) addr
>> 4) << 4;
6768 addr64
+= ((int32_t) addr
>> 5) << 5;
6771 addr64
+= ((int64_t) addr
>> 6) << 6;
6774 if (record_full_arch_list_add_mem (addr64
, 1 << ir
.ot
))
6776 if (i386_record_lea_modrm (&ir
))
6779 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6782 case 0x0fbc: /* bsf */
6783 case 0x0fbd: /* bsr */
6784 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
6785 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6789 case 0x27: /* daa */
6790 case 0x2f: /* das */
6791 case 0x37: /* aaa */
6792 case 0x3f: /* aas */
6793 case 0xd4: /* aam */
6794 case 0xd5: /* aad */
6795 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6800 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6801 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6805 case 0x90: /* nop */
6806 if (prefixes
& PREFIX_LOCK
)
6813 case 0x9b: /* fwait */
6814 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
6816 opcode
= (uint32_t) opcode8
;
6822 case 0xcc: /* int3 */
6823 printf_unfiltered (_("Process record does not support instruction "
6830 case 0xcd: /* int */
6834 if (record_read_memory (gdbarch
, ir
.addr
, &interrupt
, 1))
6837 if (interrupt
!= 0x80
6838 || tdep
->i386_intx80_record
== NULL
)
6840 printf_unfiltered (_("Process record does not support "
6841 "instruction int 0x%02x.\n"),
6846 ret
= tdep
->i386_intx80_record (ir
.regcache
);
6853 case 0xce: /* into */
6854 printf_unfiltered (_("Process record does not support "
6855 "instruction into.\n"));
6860 case 0xfa: /* cli */
6861 case 0xfb: /* sti */
6864 case 0x62: /* bound */
6865 printf_unfiltered (_("Process record does not support "
6866 "instruction bound.\n"));
6871 case 0x0fc8: /* bswap reg */
6879 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode
& 7) | ir
.rex_b
);
6882 case 0xd6: /* salc */
6883 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6888 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6889 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6892 case 0xe0: /* loopnz */
6893 case 0xe1: /* loopz */
6894 case 0xe2: /* loop */
6895 case 0xe3: /* jecxz */
6896 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6897 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6900 case 0x0f30: /* wrmsr */
6901 printf_unfiltered (_("Process record does not support "
6902 "instruction wrmsr.\n"));
6907 case 0x0f32: /* rdmsr */
6908 printf_unfiltered (_("Process record does not support "
6909 "instruction rdmsr.\n"));
6914 case 0x0f31: /* rdtsc */
6915 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6916 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
6919 case 0x0f34: /* sysenter */
6922 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6927 if (tdep
->i386_sysenter_record
== NULL
)
6929 printf_unfiltered (_("Process record does not support "
6930 "instruction sysenter.\n"));
6934 ret
= tdep
->i386_sysenter_record (ir
.regcache
);
6940 case 0x0f35: /* sysexit */
6941 printf_unfiltered (_("Process record does not support "
6942 "instruction sysexit.\n"));
6947 case 0x0f05: /* syscall */
6950 if (tdep
->i386_syscall_record
== NULL
)
6952 printf_unfiltered (_("Process record does not support "
6953 "instruction syscall.\n"));
6957 ret
= tdep
->i386_syscall_record (ir
.regcache
);
6963 case 0x0f07: /* sysret */
6964 printf_unfiltered (_("Process record does not support "
6965 "instruction sysret.\n"));
6970 case 0x0fa2: /* cpuid */
6971 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6972 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6973 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
6974 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM
);
6977 case 0xf4: /* hlt */
6978 printf_unfiltered (_("Process record does not support "
6979 "instruction hlt.\n"));
6985 if (i386_record_modrm (&ir
))
6992 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6996 if (i386_record_lea_modrm (&ir
))
7005 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7009 opcode
= opcode
<< 8 | ir
.modrm
;
7016 if (i386_record_modrm (&ir
))
7027 opcode
= opcode
<< 8 | ir
.modrm
;
7030 if (ir
.override
>= 0)
7032 if (record_full_memory_query
)
7035 Process record ignores the memory change of instruction at address %s\n\
7036 because it can't get the value of the segment register.\n\
7037 Do you want to stop the program?"),
7038 paddress (gdbarch
, ir
.orig_addr
)))
7044 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
7046 if (record_full_arch_list_add_mem (addr64
, 2))
7049 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
7051 if (record_full_arch_list_add_mem (addr64
, 8))
7056 if (record_full_arch_list_add_mem (addr64
, 4))
7067 case 0: /* monitor */
7070 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7074 opcode
= opcode
<< 8 | ir
.modrm
;
7082 if (ir
.override
>= 0)
7084 if (record_full_memory_query
)
7087 Process record ignores the memory change of instruction at address %s\n\
7088 because it can't get the value of the segment register.\n\
7089 Do you want to stop the program?"),
7090 paddress (gdbarch
, ir
.orig_addr
)))
7098 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
7100 if (record_full_arch_list_add_mem (addr64
, 2))
7103 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
7105 if (record_full_arch_list_add_mem (addr64
, 8))
7110 if (record_full_arch_list_add_mem (addr64
, 4))
7122 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
7123 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
7127 else if (ir
.rm
== 1)
7134 opcode
= opcode
<< 8 | ir
.modrm
;
7141 if (record_full_arch_list_add_reg (ir
.regcache
, ir
.rm
| ir
.rex_b
))
7147 if (i386_record_lea_modrm (&ir
))
7150 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7153 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7155 case 7: /* invlpg */
7158 if (ir
.rm
== 0 && ir
.regmap
[X86_RECORD_R8_REGNUM
])
7159 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM
);
7163 opcode
= opcode
<< 8 | ir
.modrm
;
7168 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7172 opcode
= opcode
<< 8 | ir
.modrm
;
7178 case 0x0f08: /* invd */
7179 case 0x0f09: /* wbinvd */
7182 case 0x63: /* arpl */
7183 if (i386_record_modrm (&ir
))
7185 if (ir
.mod
== 3 || ir
.regmap
[X86_RECORD_R8_REGNUM
])
7187 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.regmap
[X86_RECORD_R8_REGNUM
]
7188 ? (ir
.reg
| rex_r
) : ir
.rm
);
7192 ir
.ot
= ir
.dflag
? OT_LONG
: OT_WORD
;
7193 if (i386_record_lea_modrm (&ir
))
7196 if (!ir
.regmap
[X86_RECORD_R8_REGNUM
])
7197 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7200 case 0x0f02: /* lar */
7201 case 0x0f03: /* lsl */
7202 if (i386_record_modrm (&ir
))
7204 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
7205 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7209 if (i386_record_modrm (&ir
))
7211 if (ir
.mod
== 3 && ir
.reg
== 3)
7214 opcode
= opcode
<< 8 | ir
.modrm
;
7226 /* nop (multi byte) */
7229 case 0x0f20: /* mov reg, crN */
7230 case 0x0f22: /* mov crN, reg */
7231 if (i386_record_modrm (&ir
))
7233 if ((ir
.modrm
& 0xc0) != 0xc0)
7236 opcode
= opcode
<< 8 | ir
.modrm
;
7247 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7249 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
7253 opcode
= opcode
<< 8 | ir
.modrm
;
7259 case 0x0f21: /* mov reg, drN */
7260 case 0x0f23: /* mov drN, reg */
7261 if (i386_record_modrm (&ir
))
7263 if ((ir
.modrm
& 0xc0) != 0xc0 || ir
.reg
== 4
7264 || ir
.reg
== 5 || ir
.reg
>= 8)
7267 opcode
= opcode
<< 8 | ir
.modrm
;
7271 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7273 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
7276 case 0x0f06: /* clts */
7277 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7280 /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */
7282 case 0x0f0d: /* 3DNow! prefetch */
7285 case 0x0f0e: /* 3DNow! femms */
7286 case 0x0f77: /* emms */
7287 if (i386_fpc_regnum_p (gdbarch
, I387_FTAG_REGNUM(tdep
)))
7289 record_full_arch_list_add_reg (ir
.regcache
, I387_FTAG_REGNUM(tdep
));
7292 case 0x0f0f: /* 3DNow! data */
7293 if (i386_record_modrm (&ir
))
7295 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
7300 case 0x0c: /* 3DNow! pi2fw */
7301 case 0x0d: /* 3DNow! pi2fd */
7302 case 0x1c: /* 3DNow! pf2iw */
7303 case 0x1d: /* 3DNow! pf2id */
7304 case 0x8a: /* 3DNow! pfnacc */
7305 case 0x8e: /* 3DNow! pfpnacc */
7306 case 0x90: /* 3DNow! pfcmpge */
7307 case 0x94: /* 3DNow! pfmin */
7308 case 0x96: /* 3DNow! pfrcp */
7309 case 0x97: /* 3DNow! pfrsqrt */
7310 case 0x9a: /* 3DNow! pfsub */
7311 case 0x9e: /* 3DNow! pfadd */
7312 case 0xa0: /* 3DNow! pfcmpgt */
7313 case 0xa4: /* 3DNow! pfmax */
7314 case 0xa6: /* 3DNow! pfrcpit1 */
7315 case 0xa7: /* 3DNow! pfrsqit1 */
7316 case 0xaa: /* 3DNow! pfsubr */
7317 case 0xae: /* 3DNow! pfacc */
7318 case 0xb0: /* 3DNow! pfcmpeq */
7319 case 0xb4: /* 3DNow! pfmul */
7320 case 0xb6: /* 3DNow! pfrcpit2 */
7321 case 0xb7: /* 3DNow! pmulhrw */
7322 case 0xbb: /* 3DNow! pswapd */
7323 case 0xbf: /* 3DNow! pavgusb */
7324 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.reg
))
7325 goto no_support_3dnow_data
;
7326 record_full_arch_list_add_reg (ir
.regcache
, ir
.reg
);
7330 no_support_3dnow_data
:
7331 opcode
= (opcode
<< 8) | opcode8
;
7337 case 0x0faa: /* rsm */
7338 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7339 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
7340 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
7341 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
7342 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM
);
7343 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
7344 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
7345 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
7346 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
7350 if (i386_record_modrm (&ir
))
7354 case 0: /* fxsave */
7358 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7359 if (i386_record_lea_modrm_addr (&ir
, &tmpu64
))
7361 if (record_full_arch_list_add_mem (tmpu64
, 512))
7366 case 1: /* fxrstor */
7370 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7372 for (i
= I387_MM0_REGNUM (tdep
);
7373 i386_mmx_regnum_p (gdbarch
, i
); i
++)
7374 record_full_arch_list_add_reg (ir
.regcache
, i
);
7376 for (i
= I387_XMM0_REGNUM (tdep
);
7377 i386_xmm_regnum_p (gdbarch
, i
); i
++)
7378 record_full_arch_list_add_reg (ir
.regcache
, i
);
7380 if (i386_mxcsr_regnum_p (gdbarch
, I387_MXCSR_REGNUM(tdep
)))
7381 record_full_arch_list_add_reg (ir
.regcache
,
7382 I387_MXCSR_REGNUM(tdep
));
7384 for (i
= I387_ST0_REGNUM (tdep
);
7385 i386_fp_regnum_p (gdbarch
, i
); i
++)
7386 record_full_arch_list_add_reg (ir
.regcache
, i
);
7388 for (i
= I387_FCTRL_REGNUM (tdep
);
7389 i386_fpc_regnum_p (gdbarch
, i
); i
++)
7390 record_full_arch_list_add_reg (ir
.regcache
, i
);
7394 case 2: /* ldmxcsr */
7395 if (!i386_mxcsr_regnum_p (gdbarch
, I387_MXCSR_REGNUM(tdep
)))
7397 record_full_arch_list_add_reg (ir
.regcache
, I387_MXCSR_REGNUM(tdep
));
7400 case 3: /* stmxcsr */
7402 if (i386_record_lea_modrm (&ir
))
7406 case 5: /* lfence */
7407 case 6: /* mfence */
7408 case 7: /* sfence clflush */
7412 opcode
= (opcode
<< 8) | ir
.modrm
;
7418 case 0x0fc3: /* movnti */
7419 ir
.ot
= (ir
.dflag
== 2) ? OT_QUAD
: OT_LONG
;
7420 if (i386_record_modrm (&ir
))
7425 if (i386_record_lea_modrm (&ir
))
7429 /* Add prefix to opcode. */
7544 /* Mask out PREFIX_ADDR. */
7545 switch ((prefixes
& ~PREFIX_ADDR
))
7557 reswitch_prefix_add
:
7565 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
7568 opcode
= (uint32_t) opcode8
| opcode
<< 8;
7569 goto reswitch_prefix_add
;
7572 case 0x0f10: /* movups */
7573 case 0x660f10: /* movupd */
7574 case 0xf30f10: /* movss */
7575 case 0xf20f10: /* movsd */
7576 case 0x0f12: /* movlps */
7577 case 0x660f12: /* movlpd */
7578 case 0xf30f12: /* movsldup */
7579 case 0xf20f12: /* movddup */
7580 case 0x0f14: /* unpcklps */
7581 case 0x660f14: /* unpcklpd */
7582 case 0x0f15: /* unpckhps */
7583 case 0x660f15: /* unpckhpd */
7584 case 0x0f16: /* movhps */
7585 case 0x660f16: /* movhpd */
7586 case 0xf30f16: /* movshdup */
7587 case 0x0f28: /* movaps */
7588 case 0x660f28: /* movapd */
7589 case 0x0f2a: /* cvtpi2ps */
7590 case 0x660f2a: /* cvtpi2pd */
7591 case 0xf30f2a: /* cvtsi2ss */
7592 case 0xf20f2a: /* cvtsi2sd */
7593 case 0x0f2c: /* cvttps2pi */
7594 case 0x660f2c: /* cvttpd2pi */
7595 case 0x0f2d: /* cvtps2pi */
7596 case 0x660f2d: /* cvtpd2pi */
7597 case 0x660f3800: /* pshufb */
7598 case 0x660f3801: /* phaddw */
7599 case 0x660f3802: /* phaddd */
7600 case 0x660f3803: /* phaddsw */
7601 case 0x660f3804: /* pmaddubsw */
7602 case 0x660f3805: /* phsubw */
7603 case 0x660f3806: /* phsubd */
7604 case 0x660f3807: /* phsubsw */
7605 case 0x660f3808: /* psignb */
7606 case 0x660f3809: /* psignw */
7607 case 0x660f380a: /* psignd */
7608 case 0x660f380b: /* pmulhrsw */
7609 case 0x660f3810: /* pblendvb */
7610 case 0x660f3814: /* blendvps */
7611 case 0x660f3815: /* blendvpd */
7612 case 0x660f381c: /* pabsb */
7613 case 0x660f381d: /* pabsw */
7614 case 0x660f381e: /* pabsd */
7615 case 0x660f3820: /* pmovsxbw */
7616 case 0x660f3821: /* pmovsxbd */
7617 case 0x660f3822: /* pmovsxbq */
7618 case 0x660f3823: /* pmovsxwd */
7619 case 0x660f3824: /* pmovsxwq */
7620 case 0x660f3825: /* pmovsxdq */
7621 case 0x660f3828: /* pmuldq */
7622 case 0x660f3829: /* pcmpeqq */
7623 case 0x660f382a: /* movntdqa */
7624 case 0x660f3a08: /* roundps */
7625 case 0x660f3a09: /* roundpd */
7626 case 0x660f3a0a: /* roundss */
7627 case 0x660f3a0b: /* roundsd */
7628 case 0x660f3a0c: /* blendps */
7629 case 0x660f3a0d: /* blendpd */
7630 case 0x660f3a0e: /* pblendw */
7631 case 0x660f3a0f: /* palignr */
7632 case 0x660f3a20: /* pinsrb */
7633 case 0x660f3a21: /* insertps */
7634 case 0x660f3a22: /* pinsrd pinsrq */
7635 case 0x660f3a40: /* dpps */
7636 case 0x660f3a41: /* dppd */
7637 case 0x660f3a42: /* mpsadbw */
7638 case 0x660f3a60: /* pcmpestrm */
7639 case 0x660f3a61: /* pcmpestri */
7640 case 0x660f3a62: /* pcmpistrm */
7641 case 0x660f3a63: /* pcmpistri */
7642 case 0x0f51: /* sqrtps */
7643 case 0x660f51: /* sqrtpd */
7644 case 0xf20f51: /* sqrtsd */
7645 case 0xf30f51: /* sqrtss */
7646 case 0x0f52: /* rsqrtps */
7647 case 0xf30f52: /* rsqrtss */
7648 case 0x0f53: /* rcpps */
7649 case 0xf30f53: /* rcpss */
7650 case 0x0f54: /* andps */
7651 case 0x660f54: /* andpd */
7652 case 0x0f55: /* andnps */
7653 case 0x660f55: /* andnpd */
7654 case 0x0f56: /* orps */
7655 case 0x660f56: /* orpd */
7656 case 0x0f57: /* xorps */
7657 case 0x660f57: /* xorpd */
7658 case 0x0f58: /* addps */
7659 case 0x660f58: /* addpd */
7660 case 0xf20f58: /* addsd */
7661 case 0xf30f58: /* addss */
7662 case 0x0f59: /* mulps */
7663 case 0x660f59: /* mulpd */
7664 case 0xf20f59: /* mulsd */
7665 case 0xf30f59: /* mulss */
7666 case 0x0f5a: /* cvtps2pd */
7667 case 0x660f5a: /* cvtpd2ps */
7668 case 0xf20f5a: /* cvtsd2ss */
7669 case 0xf30f5a: /* cvtss2sd */
7670 case 0x0f5b: /* cvtdq2ps */
7671 case 0x660f5b: /* cvtps2dq */
7672 case 0xf30f5b: /* cvttps2dq */
7673 case 0x0f5c: /* subps */
7674 case 0x660f5c: /* subpd */
7675 case 0xf20f5c: /* subsd */
7676 case 0xf30f5c: /* subss */
7677 case 0x0f5d: /* minps */
7678 case 0x660f5d: /* minpd */
7679 case 0xf20f5d: /* minsd */
7680 case 0xf30f5d: /* minss */
7681 case 0x0f5e: /* divps */
7682 case 0x660f5e: /* divpd */
7683 case 0xf20f5e: /* divsd */
7684 case 0xf30f5e: /* divss */
7685 case 0x0f5f: /* maxps */
7686 case 0x660f5f: /* maxpd */
7687 case 0xf20f5f: /* maxsd */
7688 case 0xf30f5f: /* maxss */
7689 case 0x660f60: /* punpcklbw */
7690 case 0x660f61: /* punpcklwd */
7691 case 0x660f62: /* punpckldq */
7692 case 0x660f63: /* packsswb */
7693 case 0x660f64: /* pcmpgtb */
7694 case 0x660f65: /* pcmpgtw */
7695 case 0x660f66: /* pcmpgtd */
7696 case 0x660f67: /* packuswb */
7697 case 0x660f68: /* punpckhbw */
7698 case 0x660f69: /* punpckhwd */
7699 case 0x660f6a: /* punpckhdq */
7700 case 0x660f6b: /* packssdw */
7701 case 0x660f6c: /* punpcklqdq */
7702 case 0x660f6d: /* punpckhqdq */
7703 case 0x660f6e: /* movd */
7704 case 0x660f6f: /* movdqa */
7705 case 0xf30f6f: /* movdqu */
7706 case 0x660f70: /* pshufd */
7707 case 0xf20f70: /* pshuflw */
7708 case 0xf30f70: /* pshufhw */
7709 case 0x660f74: /* pcmpeqb */
7710 case 0x660f75: /* pcmpeqw */
7711 case 0x660f76: /* pcmpeqd */
7712 case 0x660f7c: /* haddpd */
7713 case 0xf20f7c: /* haddps */
7714 case 0x660f7d: /* hsubpd */
7715 case 0xf20f7d: /* hsubps */
7716 case 0xf30f7e: /* movq */
7717 case 0x0fc2: /* cmpps */
7718 case 0x660fc2: /* cmppd */
7719 case 0xf20fc2: /* cmpsd */
7720 case 0xf30fc2: /* cmpss */
7721 case 0x660fc4: /* pinsrw */
7722 case 0x0fc6: /* shufps */
7723 case 0x660fc6: /* shufpd */
7724 case 0x660fd0: /* addsubpd */
7725 case 0xf20fd0: /* addsubps */
7726 case 0x660fd1: /* psrlw */
7727 case 0x660fd2: /* psrld */
7728 case 0x660fd3: /* psrlq */
7729 case 0x660fd4: /* paddq */
7730 case 0x660fd5: /* pmullw */
7731 case 0xf30fd6: /* movq2dq */
7732 case 0x660fd8: /* psubusb */
7733 case 0x660fd9: /* psubusw */
7734 case 0x660fda: /* pminub */
7735 case 0x660fdb: /* pand */
7736 case 0x660fdc: /* paddusb */
7737 case 0x660fdd: /* paddusw */
7738 case 0x660fde: /* pmaxub */
7739 case 0x660fdf: /* pandn */
7740 case 0x660fe0: /* pavgb */
7741 case 0x660fe1: /* psraw */
7742 case 0x660fe2: /* psrad */
7743 case 0x660fe3: /* pavgw */
7744 case 0x660fe4: /* pmulhuw */
7745 case 0x660fe5: /* pmulhw */
7746 case 0x660fe6: /* cvttpd2dq */
7747 case 0xf20fe6: /* cvtpd2dq */
7748 case 0xf30fe6: /* cvtdq2pd */
7749 case 0x660fe8: /* psubsb */
7750 case 0x660fe9: /* psubsw */
7751 case 0x660fea: /* pminsw */
7752 case 0x660feb: /* por */
7753 case 0x660fec: /* paddsb */
7754 case 0x660fed: /* paddsw */
7755 case 0x660fee: /* pmaxsw */
7756 case 0x660fef: /* pxor */
7757 case 0xf20ff0: /* lddqu */
7758 case 0x660ff1: /* psllw */
7759 case 0x660ff2: /* pslld */
7760 case 0x660ff3: /* psllq */
7761 case 0x660ff4: /* pmuludq */
7762 case 0x660ff5: /* pmaddwd */
7763 case 0x660ff6: /* psadbw */
7764 case 0x660ff8: /* psubb */
7765 case 0x660ff9: /* psubw */
7766 case 0x660ffa: /* psubd */
7767 case 0x660ffb: /* psubq */
7768 case 0x660ffc: /* paddb */
7769 case 0x660ffd: /* paddw */
7770 case 0x660ffe: /* paddd */
7771 if (i386_record_modrm (&ir
))
7774 if (!i386_xmm_regnum_p (gdbarch
, I387_XMM0_REGNUM (tdep
) + ir
.reg
))
7776 record_full_arch_list_add_reg (ir
.regcache
,
7777 I387_XMM0_REGNUM (tdep
) + ir
.reg
);
7778 if ((opcode
& 0xfffffffc) == 0x660f3a60)
7779 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7782 case 0x0f11: /* movups */
7783 case 0x660f11: /* movupd */
7784 case 0xf30f11: /* movss */
7785 case 0xf20f11: /* movsd */
7786 case 0x0f13: /* movlps */
7787 case 0x660f13: /* movlpd */
7788 case 0x0f17: /* movhps */
7789 case 0x660f17: /* movhpd */
7790 case 0x0f29: /* movaps */
7791 case 0x660f29: /* movapd */
7792 case 0x660f3a14: /* pextrb */
7793 case 0x660f3a15: /* pextrw */
7794 case 0x660f3a16: /* pextrd pextrq */
7795 case 0x660f3a17: /* extractps */
7796 case 0x660f7f: /* movdqa */
7797 case 0xf30f7f: /* movdqu */
7798 if (i386_record_modrm (&ir
))
7802 if (opcode
== 0x0f13 || opcode
== 0x660f13
7803 || opcode
== 0x0f17 || opcode
== 0x660f17)
7806 if (!i386_xmm_regnum_p (gdbarch
,
7807 I387_XMM0_REGNUM (tdep
) + ir
.rm
))
7809 record_full_arch_list_add_reg (ir
.regcache
,
7810 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
7832 if (i386_record_lea_modrm (&ir
))
7837 case 0x0f2b: /* movntps */
7838 case 0x660f2b: /* movntpd */
7839 case 0x0fe7: /* movntq */
7840 case 0x660fe7: /* movntdq */
7843 if (opcode
== 0x0fe7)
7847 if (i386_record_lea_modrm (&ir
))
7851 case 0xf30f2c: /* cvttss2si */
7852 case 0xf20f2c: /* cvttsd2si */
7853 case 0xf30f2d: /* cvtss2si */
7854 case 0xf20f2d: /* cvtsd2si */
7855 case 0xf20f38f0: /* crc32 */
7856 case 0xf20f38f1: /* crc32 */
7857 case 0x0f50: /* movmskps */
7858 case 0x660f50: /* movmskpd */
7859 case 0x0fc5: /* pextrw */
7860 case 0x660fc5: /* pextrw */
7861 case 0x0fd7: /* pmovmskb */
7862 case 0x660fd7: /* pmovmskb */
7863 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
7866 case 0x0f3800: /* pshufb */
7867 case 0x0f3801: /* phaddw */
7868 case 0x0f3802: /* phaddd */
7869 case 0x0f3803: /* phaddsw */
7870 case 0x0f3804: /* pmaddubsw */
7871 case 0x0f3805: /* phsubw */
7872 case 0x0f3806: /* phsubd */
7873 case 0x0f3807: /* phsubsw */
7874 case 0x0f3808: /* psignb */
7875 case 0x0f3809: /* psignw */
7876 case 0x0f380a: /* psignd */
7877 case 0x0f380b: /* pmulhrsw */
7878 case 0x0f381c: /* pabsb */
7879 case 0x0f381d: /* pabsw */
7880 case 0x0f381e: /* pabsd */
7881 case 0x0f382b: /* packusdw */
7882 case 0x0f3830: /* pmovzxbw */
7883 case 0x0f3831: /* pmovzxbd */
7884 case 0x0f3832: /* pmovzxbq */
7885 case 0x0f3833: /* pmovzxwd */
7886 case 0x0f3834: /* pmovzxwq */
7887 case 0x0f3835: /* pmovzxdq */
7888 case 0x0f3837: /* pcmpgtq */
7889 case 0x0f3838: /* pminsb */
7890 case 0x0f3839: /* pminsd */
7891 case 0x0f383a: /* pminuw */
7892 case 0x0f383b: /* pminud */
7893 case 0x0f383c: /* pmaxsb */
7894 case 0x0f383d: /* pmaxsd */
7895 case 0x0f383e: /* pmaxuw */
7896 case 0x0f383f: /* pmaxud */
7897 case 0x0f3840: /* pmulld */
7898 case 0x0f3841: /* phminposuw */
7899 case 0x0f3a0f: /* palignr */
7900 case 0x0f60: /* punpcklbw */
7901 case 0x0f61: /* punpcklwd */
7902 case 0x0f62: /* punpckldq */
7903 case 0x0f63: /* packsswb */
7904 case 0x0f64: /* pcmpgtb */
7905 case 0x0f65: /* pcmpgtw */
7906 case 0x0f66: /* pcmpgtd */
7907 case 0x0f67: /* packuswb */
7908 case 0x0f68: /* punpckhbw */
7909 case 0x0f69: /* punpckhwd */
7910 case 0x0f6a: /* punpckhdq */
7911 case 0x0f6b: /* packssdw */
7912 case 0x0f6e: /* movd */
7913 case 0x0f6f: /* movq */
7914 case 0x0f70: /* pshufw */
7915 case 0x0f74: /* pcmpeqb */
7916 case 0x0f75: /* pcmpeqw */
7917 case 0x0f76: /* pcmpeqd */
7918 case 0x0fc4: /* pinsrw */
7919 case 0x0fd1: /* psrlw */
7920 case 0x0fd2: /* psrld */
7921 case 0x0fd3: /* psrlq */
7922 case 0x0fd4: /* paddq */
7923 case 0x0fd5: /* pmullw */
7924 case 0xf20fd6: /* movdq2q */
7925 case 0x0fd8: /* psubusb */
7926 case 0x0fd9: /* psubusw */
7927 case 0x0fda: /* pminub */
7928 case 0x0fdb: /* pand */
7929 case 0x0fdc: /* paddusb */
7930 case 0x0fdd: /* paddusw */
7931 case 0x0fde: /* pmaxub */
7932 case 0x0fdf: /* pandn */
7933 case 0x0fe0: /* pavgb */
7934 case 0x0fe1: /* psraw */
7935 case 0x0fe2: /* psrad */
7936 case 0x0fe3: /* pavgw */
7937 case 0x0fe4: /* pmulhuw */
7938 case 0x0fe5: /* pmulhw */
7939 case 0x0fe8: /* psubsb */
7940 case 0x0fe9: /* psubsw */
7941 case 0x0fea: /* pminsw */
7942 case 0x0feb: /* por */
7943 case 0x0fec: /* paddsb */
7944 case 0x0fed: /* paddsw */
7945 case 0x0fee: /* pmaxsw */
7946 case 0x0fef: /* pxor */
7947 case 0x0ff1: /* psllw */
7948 case 0x0ff2: /* pslld */
7949 case 0x0ff3: /* psllq */
7950 case 0x0ff4: /* pmuludq */
7951 case 0x0ff5: /* pmaddwd */
7952 case 0x0ff6: /* psadbw */
7953 case 0x0ff8: /* psubb */
7954 case 0x0ff9: /* psubw */
7955 case 0x0ffa: /* psubd */
7956 case 0x0ffb: /* psubq */
7957 case 0x0ffc: /* paddb */
7958 case 0x0ffd: /* paddw */
7959 case 0x0ffe: /* paddd */
7960 if (i386_record_modrm (&ir
))
7962 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.reg
))
7964 record_full_arch_list_add_reg (ir
.regcache
,
7965 I387_MM0_REGNUM (tdep
) + ir
.reg
);
7968 case 0x0f71: /* psllw */
7969 case 0x0f72: /* pslld */
7970 case 0x0f73: /* psllq */
7971 if (i386_record_modrm (&ir
))
7973 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.rm
))
7975 record_full_arch_list_add_reg (ir
.regcache
,
7976 I387_MM0_REGNUM (tdep
) + ir
.rm
);
7979 case 0x660f71: /* psllw */
7980 case 0x660f72: /* pslld */
7981 case 0x660f73: /* psllq */
7982 if (i386_record_modrm (&ir
))
7985 if (!i386_xmm_regnum_p (gdbarch
, I387_XMM0_REGNUM (tdep
) + ir
.rm
))
7987 record_full_arch_list_add_reg (ir
.regcache
,
7988 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
7991 case 0x0f7e: /* movd */
7992 case 0x660f7e: /* movd */
7993 if (i386_record_modrm (&ir
))
7996 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
8003 if (i386_record_lea_modrm (&ir
))
8008 case 0x0f7f: /* movq */
8009 if (i386_record_modrm (&ir
))
8013 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.rm
))
8015 record_full_arch_list_add_reg (ir
.regcache
,
8016 I387_MM0_REGNUM (tdep
) + ir
.rm
);
8021 if (i386_record_lea_modrm (&ir
))
8026 case 0xf30fb8: /* popcnt */
8027 if (i386_record_modrm (&ir
))
8029 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
8030 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
8033 case 0x660fd6: /* movq */
8034 if (i386_record_modrm (&ir
))
8039 if (!i386_xmm_regnum_p (gdbarch
,
8040 I387_XMM0_REGNUM (tdep
) + ir
.rm
))
8042 record_full_arch_list_add_reg (ir
.regcache
,
8043 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
8048 if (i386_record_lea_modrm (&ir
))
8053 case 0x660f3817: /* ptest */
8054 case 0x0f2e: /* ucomiss */
8055 case 0x660f2e: /* ucomisd */
8056 case 0x0f2f: /* comiss */
8057 case 0x660f2f: /* comisd */
8058 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
8061 case 0x0ff7: /* maskmovq */
8062 regcache_raw_read_unsigned (ir
.regcache
,
8063 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
8065 if (record_full_arch_list_add_mem (addr
, 64))
8069 case 0x660ff7: /* maskmovdqu */
8070 regcache_raw_read_unsigned (ir
.regcache
,
8071 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
8073 if (record_full_arch_list_add_mem (addr
, 128))
8088 /* In the future, maybe still need to deal with need_dasm. */
8089 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM
);
8090 if (record_full_arch_list_add_end ())
8096 printf_unfiltered (_("Process record does not support instruction 0x%02x "
8097 "at address %s.\n"),
8098 (unsigned int) (opcode
),
8099 paddress (gdbarch
, ir
.orig_addr
));
8103 static const int i386_record_regmap
[] =
8105 I386_EAX_REGNUM
, I386_ECX_REGNUM
, I386_EDX_REGNUM
, I386_EBX_REGNUM
,
8106 I386_ESP_REGNUM
, I386_EBP_REGNUM
, I386_ESI_REGNUM
, I386_EDI_REGNUM
,
8107 0, 0, 0, 0, 0, 0, 0, 0,
8108 I386_EIP_REGNUM
, I386_EFLAGS_REGNUM
, I386_CS_REGNUM
, I386_SS_REGNUM
,
8109 I386_DS_REGNUM
, I386_ES_REGNUM
, I386_FS_REGNUM
, I386_GS_REGNUM
8112 /* Check that the given address appears suitable for a fast
8113 tracepoint, which on x86-64 means that we need an instruction of at
8114 least 5 bytes, so that we can overwrite it with a 4-byte-offset
8115 jump and not have to worry about program jumps to an address in the
8116 middle of the tracepoint jump. On x86, it may be possible to use
8117 4-byte jumps with a 2-byte offset to a trampoline located in the
8118 bottom 64 KiB of memory. Returns 1 if OK, and writes a size
8119 of instruction to replace, and 0 if not, plus an explanatory
8123 i386_fast_tracepoint_valid_at (struct gdbarch
*gdbarch
, CORE_ADDR addr
,
8128 /* Ask the target for the minimum instruction length supported. */
8129 jumplen
= target_get_min_fast_tracepoint_insn_len ();
8133 /* If the target does not support the get_min_fast_tracepoint_insn_len
8134 operation, assume that fast tracepoints will always be implemented
8135 using 4-byte relative jumps on both x86 and x86-64. */
8138 else if (jumplen
== 0)
8140 /* If the target does support get_min_fast_tracepoint_insn_len but
8141 returns zero, then the IPA has not loaded yet. In this case,
8142 we optimistically assume that truncated 2-byte relative jumps
8143 will be available on x86, and compensate later if this assumption
8144 turns out to be incorrect. On x86-64 architectures, 4-byte relative
8145 jumps will always be used. */
8146 jumplen
= (register_size (gdbarch
, 0) == 8) ? 5 : 4;
8149 /* Check for fit. */
8150 len
= gdb_insn_length (gdbarch
, addr
);
8154 /* Return a bit of target-specific detail to add to the caller's
8155 generic failure message. */
8157 *msg
= xstrprintf (_("; instruction is only %d bytes long, "
8158 "need at least %d bytes for the jump"),
8170 /* Return a floating-point format for a floating-point variable of
8171 length LEN in bits. If non-NULL, NAME is the name of its type.
8172 If no suitable type is found, return NULL. */
8174 const struct floatformat
**
8175 i386_floatformat_for_type (struct gdbarch
*gdbarch
,
8176 const char *name
, int len
)
8178 if (len
== 128 && name
)
8179 if (strcmp (name
, "__float128") == 0
8180 || strcmp (name
, "_Float128") == 0
8181 || strcmp (name
, "complex _Float128") == 0)
8182 return floatformats_ia64_quad
;
8184 return default_floatformat_for_type (gdbarch
, name
, len
);
8188 i386_validate_tdesc_p (struct gdbarch_tdep
*tdep
,
8189 struct tdesc_arch_data
*tdesc_data
)
8191 const struct target_desc
*tdesc
= tdep
->tdesc
;
8192 const struct tdesc_feature
*feature_core
;
8194 const struct tdesc_feature
*feature_sse
, *feature_avx
, *feature_mpx
,
8195 *feature_avx512
, *feature_pkeys
;
8196 int i
, num_regs
, valid_p
;
8198 if (! tdesc_has_registers (tdesc
))
8201 /* Get core registers. */
8202 feature_core
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.core");
8203 if (feature_core
== NULL
)
8206 /* Get SSE registers. */
8207 feature_sse
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.sse");
8209 /* Try AVX registers. */
8210 feature_avx
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx");
8212 /* Try MPX registers. */
8213 feature_mpx
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.mpx");
8215 /* Try AVX512 registers. */
8216 feature_avx512
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx512");
8219 feature_pkeys
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.pkeys");
8223 /* The XCR0 bits. */
8226 /* AVX512 register description requires AVX register description. */
8230 tdep
->xcr0
= X86_XSTATE_AVX_AVX512_MASK
;
8232 /* It may have been set by OSABI initialization function. */
8233 if (tdep
->k0_regnum
< 0)
8235 tdep
->k_register_names
= i386_k_names
;
8236 tdep
->k0_regnum
= I386_K0_REGNUM
;
8239 for (i
= 0; i
< I387_NUM_K_REGS
; i
++)
8240 valid_p
&= tdesc_numbered_register (feature_avx512
, tdesc_data
,
8241 tdep
->k0_regnum
+ i
,
8244 if (tdep
->num_zmm_regs
== 0)
8246 tdep
->zmmh_register_names
= i386_zmmh_names
;
8247 tdep
->num_zmm_regs
= 8;
8248 tdep
->zmm0h_regnum
= I386_ZMM0H_REGNUM
;
8251 for (i
= 0; i
< tdep
->num_zmm_regs
; i
++)
8252 valid_p
&= tdesc_numbered_register (feature_avx512
, tdesc_data
,
8253 tdep
->zmm0h_regnum
+ i
,
8254 tdep
->zmmh_register_names
[i
]);
8256 for (i
= 0; i
< tdep
->num_xmm_avx512_regs
; i
++)
8257 valid_p
&= tdesc_numbered_register (feature_avx512
, tdesc_data
,
8258 tdep
->xmm16_regnum
+ i
,
8259 tdep
->xmm_avx512_register_names
[i
]);
8261 for (i
= 0; i
< tdep
->num_ymm_avx512_regs
; i
++)
8262 valid_p
&= tdesc_numbered_register (feature_avx512
, tdesc_data
,
8263 tdep
->ymm16h_regnum
+ i
,
8264 tdep
->ymm16h_register_names
[i
]);
8268 /* AVX register description requires SSE register description. */
8272 if (!feature_avx512
)
8273 tdep
->xcr0
= X86_XSTATE_AVX_MASK
;
8275 /* It may have been set by OSABI initialization function. */
8276 if (tdep
->num_ymm_regs
== 0)
8278 tdep
->ymmh_register_names
= i386_ymmh_names
;
8279 tdep
->num_ymm_regs
= 8;
8280 tdep
->ymm0h_regnum
= I386_YMM0H_REGNUM
;
8283 for (i
= 0; i
< tdep
->num_ymm_regs
; i
++)
8284 valid_p
&= tdesc_numbered_register (feature_avx
, tdesc_data
,
8285 tdep
->ymm0h_regnum
+ i
,
8286 tdep
->ymmh_register_names
[i
]);
8288 else if (feature_sse
)
8289 tdep
->xcr0
= X86_XSTATE_SSE_MASK
;
8292 tdep
->xcr0
= X86_XSTATE_X87_MASK
;
8293 tdep
->num_xmm_regs
= 0;
8296 num_regs
= tdep
->num_core_regs
;
8297 for (i
= 0; i
< num_regs
; i
++)
8298 valid_p
&= tdesc_numbered_register (feature_core
, tdesc_data
, i
,
8299 tdep
->register_names
[i
]);
8303 /* Need to include %mxcsr, so add one. */
8304 num_regs
+= tdep
->num_xmm_regs
+ 1;
8305 for (; i
< num_regs
; i
++)
8306 valid_p
&= tdesc_numbered_register (feature_sse
, tdesc_data
, i
,
8307 tdep
->register_names
[i
]);
8312 tdep
->xcr0
|= X86_XSTATE_MPX_MASK
;
8314 if (tdep
->bnd0r_regnum
< 0)
8316 tdep
->mpx_register_names
= i386_mpx_names
;
8317 tdep
->bnd0r_regnum
= I386_BND0R_REGNUM
;
8318 tdep
->bndcfgu_regnum
= I386_BNDCFGU_REGNUM
;
8321 for (i
= 0; i
< I387_NUM_MPX_REGS
; i
++)
8322 valid_p
&= tdesc_numbered_register (feature_mpx
, tdesc_data
,
8323 I387_BND0R_REGNUM (tdep
) + i
,
8324 tdep
->mpx_register_names
[i
]);
8329 tdep
->xcr0
|= X86_XSTATE_PKRU
;
8330 if (tdep
->pkru_regnum
< 0)
8332 tdep
->pkeys_register_names
= i386_pkeys_names
;
8333 tdep
->pkru_regnum
= I386_PKRU_REGNUM
;
8334 tdep
->num_pkeys_regs
= 1;
8337 for (i
= 0; i
< I387_NUM_PKEYS_REGS
; i
++)
8338 valid_p
&= tdesc_numbered_register (feature_pkeys
, tdesc_data
,
8339 I387_PKRU_REGNUM (tdep
) + i
,
8340 tdep
->pkeys_register_names
[i
]);
8347 /* Note: This is called for both i386 and amd64. */
8349 static struct gdbarch
*
8350 i386_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
8352 struct gdbarch_tdep
*tdep
;
8353 struct gdbarch
*gdbarch
;
8354 struct tdesc_arch_data
*tdesc_data
;
8355 const struct target_desc
*tdesc
;
8361 /* If there is already a candidate, use it. */
8362 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
8364 return arches
->gdbarch
;
8366 /* Allocate space for the new architecture. Assume i386 for now. */
8367 tdep
= XCNEW (struct gdbarch_tdep
);
8368 gdbarch
= gdbarch_alloc (&info
, tdep
);
8370 /* General-purpose registers. */
8371 tdep
->gregset_reg_offset
= NULL
;
8372 tdep
->gregset_num_regs
= I386_NUM_GREGS
;
8373 tdep
->sizeof_gregset
= 0;
8375 /* Floating-point registers. */
8376 tdep
->sizeof_fpregset
= I387_SIZEOF_FSAVE
;
8377 tdep
->fpregset
= &i386_fpregset
;
8379 /* The default settings include the FPU registers, the MMX registers
8380 and the SSE registers. This can be overridden for a specific ABI
8381 by adjusting the members `st0_regnum', `mm0_regnum' and
8382 `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers
8383 will show up in the output of "info all-registers". */
8385 tdep
->st0_regnum
= I386_ST0_REGNUM
;
8387 /* I386_NUM_XREGS includes %mxcsr, so substract one. */
8388 tdep
->num_xmm_regs
= I386_NUM_XREGS
- 1;
8390 tdep
->jb_pc_offset
= -1;
8391 tdep
->struct_return
= pcc_struct_return
;
8392 tdep
->sigtramp_start
= 0;
8393 tdep
->sigtramp_end
= 0;
8394 tdep
->sigtramp_p
= i386_sigtramp_p
;
8395 tdep
->sigcontext_addr
= NULL
;
8396 tdep
->sc_reg_offset
= NULL
;
8397 tdep
->sc_pc_offset
= -1;
8398 tdep
->sc_sp_offset
= -1;
8400 tdep
->xsave_xcr0_offset
= -1;
8402 tdep
->record_regmap
= i386_record_regmap
;
8404 set_gdbarch_long_long_align_bit (gdbarch
, 32);
8406 /* The format used for `long double' on almost all i386 targets is
8407 the i387 extended floating-point format. In fact, of all targets
8408 in the GCC 2.95 tree, only OSF/1 does it different, and insists
8409 on having a `long double' that's not `long' at all. */
8410 set_gdbarch_long_double_format (gdbarch
, floatformats_i387_ext
);
8412 /* Although the i387 extended floating-point has only 80 significant
8413 bits, a `long double' actually takes up 96, probably to enforce
8415 set_gdbarch_long_double_bit (gdbarch
, 96);
8417 /* Support for floating-point data type variants. */
8418 set_gdbarch_floatformat_for_type (gdbarch
, i386_floatformat_for_type
);
8420 /* Register numbers of various important registers. */
8421 set_gdbarch_sp_regnum (gdbarch
, I386_ESP_REGNUM
); /* %esp */
8422 set_gdbarch_pc_regnum (gdbarch
, I386_EIP_REGNUM
); /* %eip */
8423 set_gdbarch_ps_regnum (gdbarch
, I386_EFLAGS_REGNUM
); /* %eflags */
8424 set_gdbarch_fp0_regnum (gdbarch
, I386_ST0_REGNUM
); /* %st(0) */
8426 /* NOTE: kettenis/20040418: GCC does have two possible register
8427 numbering schemes on the i386: dbx and SVR4. These schemes
8428 differ in how they number %ebp, %esp, %eflags, and the
8429 floating-point registers, and are implemented by the arrays
8430 dbx_register_map[] and svr4_dbx_register_map in
8431 gcc/config/i386.c. GCC also defines a third numbering scheme in
8432 gcc/config/i386.c, which it designates as the "default" register
8433 map used in 64bit mode. This last register numbering scheme is
8434 implemented in dbx64_register_map, and is used for AMD64; see
8437 Currently, each GCC i386 target always uses the same register
8438 numbering scheme across all its supported debugging formats
8439 i.e. SDB (COFF), stabs and DWARF 2. This is because
8440 gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the
8441 DBX_REGISTER_NUMBER macro which is defined by each target's
8442 respective config header in a manner independent of the requested
8443 output debugging format.
8445 This does not match the arrangement below, which presumes that
8446 the SDB and stabs numbering schemes differ from the DWARF and
8447 DWARF 2 ones. The reason for this arrangement is that it is
8448 likely to get the numbering scheme for the target's
8449 default/native debug format right. For targets where GCC is the
8450 native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for
8451 targets where the native toolchain uses a different numbering
8452 scheme for a particular debug format (stabs-in-ELF on Solaris)
8453 the defaults below will have to be overridden, like
8454 i386_elf_init_abi() does. */
8456 /* Use the dbx register numbering scheme for stabs and COFF. */
8457 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
8458 set_gdbarch_sdb_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
8460 /* Use the SVR4 register numbering scheme for DWARF 2. */
8461 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, i386_svr4_dwarf_reg_to_regnum
);
8463 /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to
8464 be in use on any of the supported i386 targets. */
8466 set_gdbarch_print_float_info (gdbarch
, i387_print_float_info
);
8468 set_gdbarch_get_longjmp_target (gdbarch
, i386_get_longjmp_target
);
8470 /* Call dummy code. */
8471 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
8472 set_gdbarch_push_dummy_code (gdbarch
, i386_push_dummy_code
);
8473 set_gdbarch_push_dummy_call (gdbarch
, i386_push_dummy_call
);
8474 set_gdbarch_frame_align (gdbarch
, i386_frame_align
);
8476 set_gdbarch_convert_register_p (gdbarch
, i386_convert_register_p
);
8477 set_gdbarch_register_to_value (gdbarch
, i386_register_to_value
);
8478 set_gdbarch_value_to_register (gdbarch
, i386_value_to_register
);
8480 set_gdbarch_return_value (gdbarch
, i386_return_value
);
8482 set_gdbarch_skip_prologue (gdbarch
, i386_skip_prologue
);
8484 /* Stack grows downward. */
8485 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
8487 set_gdbarch_breakpoint_kind_from_pc (gdbarch
, i386_breakpoint::kind_from_pc
);
8488 set_gdbarch_sw_breakpoint_from_kind (gdbarch
, i386_breakpoint::bp_from_kind
);
8490 set_gdbarch_decr_pc_after_break (gdbarch
, 1);
8491 set_gdbarch_max_insn_length (gdbarch
, I386_MAX_INSN_LEN
);
8493 set_gdbarch_frame_args_skip (gdbarch
, 8);
8495 set_gdbarch_print_insn (gdbarch
, i386_print_insn
);
8497 set_gdbarch_dummy_id (gdbarch
, i386_dummy_id
);
8499 set_gdbarch_unwind_pc (gdbarch
, i386_unwind_pc
);
8501 /* Add the i386 register groups. */
8502 i386_add_reggroups (gdbarch
);
8503 tdep
->register_reggroup_p
= i386_register_reggroup_p
;
8505 /* Helper for function argument information. */
8506 set_gdbarch_fetch_pointer_argument (gdbarch
, i386_fetch_pointer_argument
);
8508 /* Hook the function epilogue frame unwinder. This unwinder is
8509 appended to the list first, so that it supercedes the DWARF
8510 unwinder in function epilogues (where the DWARF unwinder
8511 currently fails). */
8512 frame_unwind_append_unwinder (gdbarch
, &i386_epilogue_frame_unwind
);
8514 /* Hook in the DWARF CFI frame unwinder. This unwinder is appended
8515 to the list before the prologue-based unwinders, so that DWARF
8516 CFI info will be used if it is available. */
8517 dwarf2_append_unwinders (gdbarch
);
8519 frame_base_set_default (gdbarch
, &i386_frame_base
);
8521 /* Pseudo registers may be changed by amd64_init_abi. */
8522 set_gdbarch_pseudo_register_read_value (gdbarch
,
8523 i386_pseudo_register_read_value
);
8524 set_gdbarch_pseudo_register_write (gdbarch
, i386_pseudo_register_write
);
8525 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
8526 i386_ax_pseudo_register_collect
);
8528 set_tdesc_pseudo_register_type (gdbarch
, i386_pseudo_register_type
);
8529 set_tdesc_pseudo_register_name (gdbarch
, i386_pseudo_register_name
);
8531 /* Override the normal target description method to make the AVX
8532 upper halves anonymous. */
8533 set_gdbarch_register_name (gdbarch
, i386_register_name
);
8535 /* Even though the default ABI only includes general-purpose registers,
8536 floating-point registers and the SSE registers, we have to leave a
8537 gap for the upper AVX, MPX and AVX512 registers. */
8538 set_gdbarch_num_regs (gdbarch
, I386_PKEYS_NUM_REGS
);
8540 set_gdbarch_gnu_triplet_regexp (gdbarch
, i386_gnu_triplet_regexp
);
8542 /* Get the x86 target description from INFO. */
8543 tdesc
= info
.target_desc
;
8544 if (! tdesc_has_registers (tdesc
))
8545 tdesc
= i386_target_description (X86_XSTATE_SSE_MASK
);
8546 tdep
->tdesc
= tdesc
;
8548 tdep
->num_core_regs
= I386_NUM_GREGS
+ I387_NUM_REGS
;
8549 tdep
->register_names
= i386_register_names
;
8551 /* No upper YMM registers. */
8552 tdep
->ymmh_register_names
= NULL
;
8553 tdep
->ymm0h_regnum
= -1;
8555 /* No upper ZMM registers. */
8556 tdep
->zmmh_register_names
= NULL
;
8557 tdep
->zmm0h_regnum
= -1;
8559 /* No high XMM registers. */
8560 tdep
->xmm_avx512_register_names
= NULL
;
8561 tdep
->xmm16_regnum
= -1;
8563 /* No upper YMM16-31 registers. */
8564 tdep
->ymm16h_register_names
= NULL
;
8565 tdep
->ymm16h_regnum
= -1;
8567 tdep
->num_byte_regs
= 8;
8568 tdep
->num_word_regs
= 8;
8569 tdep
->num_dword_regs
= 0;
8570 tdep
->num_mmx_regs
= 8;
8571 tdep
->num_ymm_regs
= 0;
8573 /* No MPX registers. */
8574 tdep
->bnd0r_regnum
= -1;
8575 tdep
->bndcfgu_regnum
= -1;
8577 /* No AVX512 registers. */
8578 tdep
->k0_regnum
= -1;
8579 tdep
->num_zmm_regs
= 0;
8580 tdep
->num_ymm_avx512_regs
= 0;
8581 tdep
->num_xmm_avx512_regs
= 0;
8583 /* No PKEYS registers */
8584 tdep
->pkru_regnum
= -1;
8585 tdep
->num_pkeys_regs
= 0;
8587 tdesc_data
= tdesc_data_alloc ();
8589 set_gdbarch_relocate_instruction (gdbarch
, i386_relocate_instruction
);
8591 set_gdbarch_gen_return_address (gdbarch
, i386_gen_return_address
);
8593 set_gdbarch_insn_is_call (gdbarch
, i386_insn_is_call
);
8594 set_gdbarch_insn_is_ret (gdbarch
, i386_insn_is_ret
);
8595 set_gdbarch_insn_is_jump (gdbarch
, i386_insn_is_jump
);
8597 /* Hook in ABI-specific overrides, if they have been registered.
8598 Note: If INFO specifies a 64 bit arch, this is where we turn
8599 a 32-bit i386 into a 64-bit amd64. */
8600 info
.tdesc_data
= tdesc_data
;
8601 gdbarch_init_osabi (info
, gdbarch
);
8603 if (!i386_validate_tdesc_p (tdep
, tdesc_data
))
8605 tdesc_data_cleanup (tdesc_data
);
8607 gdbarch_free (gdbarch
);
8611 num_bnd_cooked
= (tdep
->bnd0r_regnum
> 0 ? I387_NUM_BND_REGS
: 0);
8613 /* Wire in pseudo registers. Number of pseudo registers may be
8615 set_gdbarch_num_pseudo_regs (gdbarch
, (tdep
->num_byte_regs
8616 + tdep
->num_word_regs
8617 + tdep
->num_dword_regs
8618 + tdep
->num_mmx_regs
8619 + tdep
->num_ymm_regs
8621 + tdep
->num_ymm_avx512_regs
8622 + tdep
->num_zmm_regs
));
8624 /* Target description may be changed. */
8625 tdesc
= tdep
->tdesc
;
8627 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
8629 /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */
8630 set_gdbarch_register_reggroup_p (gdbarch
, tdep
->register_reggroup_p
);
8632 /* Make %al the first pseudo-register. */
8633 tdep
->al_regnum
= gdbarch_num_regs (gdbarch
);
8634 tdep
->ax_regnum
= tdep
->al_regnum
+ tdep
->num_byte_regs
;
8636 ymm0_regnum
= tdep
->ax_regnum
+ tdep
->num_word_regs
;
8637 if (tdep
->num_dword_regs
)
8639 /* Support dword pseudo-register if it hasn't been disabled. */
8640 tdep
->eax_regnum
= ymm0_regnum
;
8641 ymm0_regnum
+= tdep
->num_dword_regs
;
8644 tdep
->eax_regnum
= -1;
8646 mm0_regnum
= ymm0_regnum
;
8647 if (tdep
->num_ymm_regs
)
8649 /* Support YMM pseudo-register if it is available. */
8650 tdep
->ymm0_regnum
= ymm0_regnum
;
8651 mm0_regnum
+= tdep
->num_ymm_regs
;
8654 tdep
->ymm0_regnum
= -1;
8656 if (tdep
->num_ymm_avx512_regs
)
8658 /* Support YMM16-31 pseudo registers if available. */
8659 tdep
->ymm16_regnum
= mm0_regnum
;
8660 mm0_regnum
+= tdep
->num_ymm_avx512_regs
;
8663 tdep
->ymm16_regnum
= -1;
8665 if (tdep
->num_zmm_regs
)
8667 /* Support ZMM pseudo-register if it is available. */
8668 tdep
->zmm0_regnum
= mm0_regnum
;
8669 mm0_regnum
+= tdep
->num_zmm_regs
;
8672 tdep
->zmm0_regnum
= -1;
8674 bnd0_regnum
= mm0_regnum
;
8675 if (tdep
->num_mmx_regs
!= 0)
8677 /* Support MMX pseudo-register if MMX hasn't been disabled. */
8678 tdep
->mm0_regnum
= mm0_regnum
;
8679 bnd0_regnum
+= tdep
->num_mmx_regs
;
8682 tdep
->mm0_regnum
= -1;
8684 if (tdep
->bnd0r_regnum
> 0)
8685 tdep
->bnd0_regnum
= bnd0_regnum
;
8687 tdep
-> bnd0_regnum
= -1;
8689 /* Hook in the legacy prologue-based unwinders last (fallback). */
8690 frame_unwind_append_unwinder (gdbarch
, &i386_stack_tramp_frame_unwind
);
8691 frame_unwind_append_unwinder (gdbarch
, &i386_sigtramp_frame_unwind
);
8692 frame_unwind_append_unwinder (gdbarch
, &i386_frame_unwind
);
8694 /* If we have a register mapping, enable the generic core file
8695 support, unless it has already been enabled. */
8696 if (tdep
->gregset_reg_offset
8697 && !gdbarch_iterate_over_regset_sections_p (gdbarch
))
8698 set_gdbarch_iterate_over_regset_sections
8699 (gdbarch
, i386_iterate_over_regset_sections
);
8701 set_gdbarch_fast_tracepoint_valid_at (gdbarch
,
8702 i386_fast_tracepoint_valid_at
);
8709 /* Return the target description for a specified XSAVE feature mask. */
8711 const struct target_desc
*
8712 i386_target_description (uint64_t xcr0
)
8714 static target_desc
*i386_tdescs \
8715 [2/*SSE*/][2/*AVX*/][2/*MPX*/][2/*AVX512*/][2/*PKRU*/] = {};
8716 target_desc
**tdesc
;
8718 tdesc
= &i386_tdescs
[(xcr0
& X86_XSTATE_SSE
) ? 1 : 0]
8719 [(xcr0
& X86_XSTATE_AVX
) ? 1 : 0]
8720 [(xcr0
& X86_XSTATE_MPX
) ? 1 : 0]
8721 [(xcr0
& X86_XSTATE_AVX512
) ? 1 : 0]
8722 [(xcr0
& X86_XSTATE_PKRU
) ? 1 : 0];
8725 *tdesc
= i386_create_target_description (xcr0
, false);
8730 #define MPX_BASE_MASK (~(ULONGEST) 0xfff)
8732 /* Find the bound directory base address. */
8734 static unsigned long
8735 i386_mpx_bd_base (void)
8737 struct regcache
*rcache
;
8738 struct gdbarch_tdep
*tdep
;
8740 enum register_status regstatus
;
8742 rcache
= get_current_regcache ();
8743 tdep
= gdbarch_tdep (get_regcache_arch (rcache
));
8745 regstatus
= regcache_raw_read_unsigned (rcache
, tdep
->bndcfgu_regnum
, &ret
);
8747 if (regstatus
!= REG_VALID
)
8748 error (_("BNDCFGU register invalid, read status %d."), regstatus
);
8750 return ret
& MPX_BASE_MASK
;
8754 i386_mpx_enabled (void)
8756 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_current_arch ());
8757 const struct target_desc
*tdesc
= tdep
->tdesc
;
8759 return (tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.mpx") != NULL
);
8762 #define MPX_BD_MASK 0xfffffff00000ULL /* select bits [47:20] */
8763 #define MPX_BT_MASK 0x0000000ffff8 /* select bits [19:3] */
8764 #define MPX_BD_MASK_32 0xfffff000 /* select bits [31:12] */
8765 #define MPX_BT_MASK_32 0x00000ffc /* select bits [11:2] */
8767 /* Find the bound table entry given the pointer location and the base
8768 address of the table. */
8771 i386_mpx_get_bt_entry (CORE_ADDR ptr
, CORE_ADDR bd_base
)
8775 CORE_ADDR mpx_bd_mask
, bd_ptr_r_shift
, bd_ptr_l_shift
;
8776 CORE_ADDR bt_mask
, bt_select_r_shift
, bt_select_l_shift
;
8777 CORE_ADDR bd_entry_addr
;
8780 struct gdbarch
*gdbarch
= get_current_arch ();
8781 struct type
*data_ptr_type
= builtin_type (gdbarch
)->builtin_data_ptr
;
8784 if (gdbarch_ptr_bit (gdbarch
) == 64)
8786 mpx_bd_mask
= (CORE_ADDR
) MPX_BD_MASK
;
8787 bd_ptr_r_shift
= 20;
8789 bt_select_r_shift
= 3;
8790 bt_select_l_shift
= 5;
8791 bt_mask
= (CORE_ADDR
) MPX_BT_MASK
;
8793 if ( sizeof (CORE_ADDR
) == 4)
8794 error (_("bound table examination not supported\
8795 for 64-bit process with 32-bit GDB"));
8799 mpx_bd_mask
= MPX_BD_MASK_32
;
8800 bd_ptr_r_shift
= 12;
8802 bt_select_r_shift
= 2;
8803 bt_select_l_shift
= 4;
8804 bt_mask
= MPX_BT_MASK_32
;
8807 offset1
= ((ptr
& mpx_bd_mask
) >> bd_ptr_r_shift
) << bd_ptr_l_shift
;
8808 bd_entry_addr
= bd_base
+ offset1
;
8809 bd_entry
= read_memory_typed_address (bd_entry_addr
, data_ptr_type
);
8811 if ((bd_entry
& 0x1) == 0)
8812 error (_("Invalid bounds directory entry at %s."),
8813 paddress (get_current_arch (), bd_entry_addr
));
8815 /* Clearing status bit. */
8817 bt_addr
= bd_entry
& ~bt_select_r_shift
;
8818 offset2
= ((ptr
& bt_mask
) >> bt_select_r_shift
) << bt_select_l_shift
;
8820 return bt_addr
+ offset2
;
8823 /* Print routine for the mpx bounds. */
8826 i386_mpx_print_bounds (const CORE_ADDR bt_entry
[4])
8828 struct ui_out
*uiout
= current_uiout
;
8830 struct gdbarch
*gdbarch
= get_current_arch ();
8831 CORE_ADDR onecompl
= ~((CORE_ADDR
) 0);
8832 int bounds_in_map
= ((~bt_entry
[1] == 0 && bt_entry
[0] == onecompl
) ? 1 : 0);
8834 if (bounds_in_map
== 1)
8836 uiout
->text ("Null bounds on map:");
8837 uiout
->text (" pointer value = ");
8838 uiout
->field_core_addr ("pointer-value", gdbarch
, bt_entry
[2]);
8844 uiout
->text ("{lbound = ");
8845 uiout
->field_core_addr ("lower-bound", gdbarch
, bt_entry
[0]);
8846 uiout
->text (", ubound = ");
8848 /* The upper bound is stored in 1's complement. */
8849 uiout
->field_core_addr ("upper-bound", gdbarch
, ~bt_entry
[1]);
8850 uiout
->text ("}: pointer value = ");
8851 uiout
->field_core_addr ("pointer-value", gdbarch
, bt_entry
[2]);
8853 if (gdbarch_ptr_bit (gdbarch
) == 64)
8854 size
= ( (~(int64_t) bt_entry
[1]) - (int64_t) bt_entry
[0]);
8856 size
= ( ~((int32_t) bt_entry
[1]) - (int32_t) bt_entry
[0]);
8858 /* In case the bounds are 0x0 and 0xffff... the difference will be -1.
8859 -1 represents in this sense full memory access, and there is no need
8862 size
= (size
> -1 ? size
+ 1 : size
);
8863 uiout
->text (", size = ");
8864 uiout
->field_fmt ("size", "%s", plongest (size
));
8866 uiout
->text (", metadata = ");
8867 uiout
->field_core_addr ("metadata", gdbarch
, bt_entry
[3]);
8872 /* Implement the command "show mpx bound". */
8875 i386_mpx_info_bounds (const char *args
, int from_tty
)
8877 CORE_ADDR bd_base
= 0;
8879 CORE_ADDR bt_entry_addr
= 0;
8880 CORE_ADDR bt_entry
[4];
8882 struct gdbarch
*gdbarch
= get_current_arch ();
8883 struct type
*data_ptr_type
= builtin_type (gdbarch
)->builtin_data_ptr
;
8885 if (gdbarch_bfd_arch_info (gdbarch
)->arch
!= bfd_arch_i386
8886 || !i386_mpx_enabled ())
8888 printf_unfiltered (_("Intel Memory Protection Extensions not "
8889 "supported on this target.\n"));
8895 printf_unfiltered (_("Address of pointer variable expected.\n"));
8899 addr
= parse_and_eval_address (args
);
8901 bd_base
= i386_mpx_bd_base ();
8902 bt_entry_addr
= i386_mpx_get_bt_entry (addr
, bd_base
);
8904 memset (bt_entry
, 0, sizeof (bt_entry
));
8906 for (i
= 0; i
< 4; i
++)
8907 bt_entry
[i
] = read_memory_typed_address (bt_entry_addr
8908 + i
* TYPE_LENGTH (data_ptr_type
),
8911 i386_mpx_print_bounds (bt_entry
);
8914 /* Implement the command "set mpx bound". */
8917 i386_mpx_set_bounds (const char *args
, int from_tty
)
8919 CORE_ADDR bd_base
= 0;
8920 CORE_ADDR addr
, lower
, upper
;
8921 CORE_ADDR bt_entry_addr
= 0;
8922 CORE_ADDR bt_entry
[2];
8923 const char *input
= args
;
8925 struct gdbarch
*gdbarch
= get_current_arch ();
8926 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
8927 struct type
*data_ptr_type
= builtin_type (gdbarch
)->builtin_data_ptr
;
8929 if (gdbarch_bfd_arch_info (gdbarch
)->arch
!= bfd_arch_i386
8930 || !i386_mpx_enabled ())
8931 error (_("Intel Memory Protection Extensions not supported\
8935 error (_("Pointer value expected."));
8937 addr
= value_as_address (parse_to_comma_and_eval (&input
));
8939 if (input
[0] == ',')
8941 if (input
[0] == '\0')
8942 error (_("wrong number of arguments: missing lower and upper bound."));
8943 lower
= value_as_address (parse_to_comma_and_eval (&input
));
8945 if (input
[0] == ',')
8947 if (input
[0] == '\0')
8948 error (_("Wrong number of arguments; Missing upper bound."));
8949 upper
= value_as_address (parse_to_comma_and_eval (&input
));
8951 bd_base
= i386_mpx_bd_base ();
8952 bt_entry_addr
= i386_mpx_get_bt_entry (addr
, bd_base
);
8953 for (i
= 0; i
< 2; i
++)
8954 bt_entry
[i
] = read_memory_typed_address (bt_entry_addr
8955 + i
* TYPE_LENGTH (data_ptr_type
),
8957 bt_entry
[0] = (uint64_t) lower
;
8958 bt_entry
[1] = ~(uint64_t) upper
;
8960 for (i
= 0; i
< 2; i
++)
8961 write_memory_unsigned_integer (bt_entry_addr
8962 + i
* TYPE_LENGTH (data_ptr_type
),
8963 TYPE_LENGTH (data_ptr_type
), byte_order
,
8967 static struct cmd_list_element
*mpx_set_cmdlist
, *mpx_show_cmdlist
;
8969 /* Helper function for the CLI commands. */
8972 set_mpx_cmd (const char *args
, int from_tty
)
8974 help_list (mpx_set_cmdlist
, "set mpx ", all_commands
, gdb_stdout
);
8977 /* Helper function for the CLI commands. */
8980 show_mpx_cmd (const char *args
, int from_tty
)
8982 cmd_show_list (mpx_show_cmdlist
, from_tty
, "");
8986 _initialize_i386_tdep (void)
8988 register_gdbarch_init (bfd_arch_i386
, i386_gdbarch_init
);
8990 /* Add the variable that controls the disassembly flavor. */
8991 add_setshow_enum_cmd ("disassembly-flavor", no_class
, valid_flavors
,
8992 &disassembly_flavor
, _("\
8993 Set the disassembly flavor."), _("\
8994 Show the disassembly flavor."), _("\
8995 The valid values are \"att\" and \"intel\", and the default value is \"att\"."),
8997 NULL
, /* FIXME: i18n: */
8998 &setlist
, &showlist
);
9000 /* Add the variable that controls the convention for returning
9002 add_setshow_enum_cmd ("struct-convention", no_class
, valid_conventions
,
9003 &struct_convention
, _("\
9004 Set the convention for returning small structs."), _("\
9005 Show the convention for returning small structs."), _("\
9006 Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\
9009 NULL
, /* FIXME: i18n: */
9010 &setlist
, &showlist
);
9012 /* Add "mpx" prefix for the set commands. */
9014 add_prefix_cmd ("mpx", class_support
, set_mpx_cmd
, _("\
9015 Set Intel Memory Protection Extensions specific variables."),
9016 &mpx_set_cmdlist
, "set mpx ",
9017 0 /* allow-unknown */, &setlist
);
9019 /* Add "mpx" prefix for the show commands. */
9021 add_prefix_cmd ("mpx", class_support
, show_mpx_cmd
, _("\
9022 Show Intel Memory Protection Extensions specific variables."),
9023 &mpx_show_cmdlist
, "show mpx ",
9024 0 /* allow-unknown */, &showlist
);
9026 /* Add "bound" command for the show mpx commands list. */
9028 add_cmd ("bound", no_class
, i386_mpx_info_bounds
,
9029 "Show the memory bounds for a given array/pointer storage\
9030 in the bound table.",
9033 /* Add "bound" command for the set mpx commands list. */
9035 add_cmd ("bound", no_class
, i386_mpx_set_bounds
,
9036 "Set the memory bounds for a given array/pointer storage\
9037 in the bound table.",
9040 gdbarch_register_osabi (bfd_arch_i386
, 0, GDB_OSABI_SVR4
,
9041 i386_svr4_init_abi
);
9043 /* Initialize the i386-specific register groups. */
9044 i386_init_reggroups ();
9046 /* Tell remote stub that we support XML target description. */
9047 register_remote_support_xml ("i386");
9055 { "i386/i386.xml", X86_XSTATE_SSE_MASK
},
9056 { "i386/i386-mmx.xml", X86_XSTATE_X87_MASK
},
9057 { "i386/i386-avx.xml", X86_XSTATE_AVX_MASK
},
9058 { "i386/i386-mpx.xml", X86_XSTATE_MPX_MASK
},
9059 { "i386/i386-avx-mpx.xml", X86_XSTATE_AVX_MPX_MASK
},
9060 { "i386/i386-avx-avx512.xml", X86_XSTATE_AVX_AVX512_MASK
},
9061 { "i386/i386-avx-mpx-avx512-pku.xml",
9062 X86_XSTATE_AVX_MPX_AVX512_PKU_MASK
},
9065 for (auto &a
: xml_masks
)
9067 auto tdesc
= i386_target_description (a
.mask
);
9069 selftests::record_xml_tdesc (a
.xml
, tdesc
);
9071 #endif /* GDB_SELF_TEST */