1 /* Intel 386 target-dependent stuff.
3 Copyright (C) 1988-2012 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "opcode/i386.h"
22 #include "arch-utils.h"
24 #include "dummy-frame.h"
25 #include "dwarf2-frame.h"
28 #include "frame-base.h"
29 #include "frame-unwind.h"
37 #include "reggroups.h"
46 #include "exceptions.h"
47 #include "gdb_assert.h"
48 #include "gdb_string.h"
50 #include "i386-tdep.h"
51 #include "i387-tdep.h"
52 #include "i386-xstate.h"
57 #include "features/i386/i386.c"
58 #include "features/i386/i386-avx.c"
59 #include "features/i386/i386-mmx.c"
64 #include "stap-probe.h"
65 #include "user-regs.h"
66 #include "cli/cli-utils.h"
67 #include "expression.h"
68 #include "parser-defs.h"
73 static const char *i386_register_names
[] =
75 "eax", "ecx", "edx", "ebx",
76 "esp", "ebp", "esi", "edi",
77 "eip", "eflags", "cs", "ss",
78 "ds", "es", "fs", "gs",
79 "st0", "st1", "st2", "st3",
80 "st4", "st5", "st6", "st7",
81 "fctrl", "fstat", "ftag", "fiseg",
82 "fioff", "foseg", "fooff", "fop",
83 "xmm0", "xmm1", "xmm2", "xmm3",
84 "xmm4", "xmm5", "xmm6", "xmm7",
88 static const char *i386_ymm_names
[] =
90 "ymm0", "ymm1", "ymm2", "ymm3",
91 "ymm4", "ymm5", "ymm6", "ymm7",
94 static const char *i386_ymmh_names
[] =
96 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
97 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
100 /* Register names for MMX pseudo-registers. */
102 static const char *i386_mmx_names
[] =
104 "mm0", "mm1", "mm2", "mm3",
105 "mm4", "mm5", "mm6", "mm7"
108 /* Register names for byte pseudo-registers. */
110 static const char *i386_byte_names
[] =
112 "al", "cl", "dl", "bl",
113 "ah", "ch", "dh", "bh"
116 /* Register names for word pseudo-registers. */
118 static const char *i386_word_names
[] =
120 "ax", "cx", "dx", "bx",
127 i386_mmx_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
129 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
130 int mm0_regnum
= tdep
->mm0_regnum
;
135 regnum
-= mm0_regnum
;
136 return regnum
>= 0 && regnum
< tdep
->num_mmx_regs
;
142 i386_byte_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
144 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
146 regnum
-= tdep
->al_regnum
;
147 return regnum
>= 0 && regnum
< tdep
->num_byte_regs
;
153 i386_word_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
155 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
157 regnum
-= tdep
->ax_regnum
;
158 return regnum
>= 0 && regnum
< tdep
->num_word_regs
;
161 /* Dword register? */
164 i386_dword_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
166 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
167 int eax_regnum
= tdep
->eax_regnum
;
172 regnum
-= eax_regnum
;
173 return regnum
>= 0 && regnum
< tdep
->num_dword_regs
;
177 i386_ymmh_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
179 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
180 int ymm0h_regnum
= tdep
->ymm0h_regnum
;
182 if (ymm0h_regnum
< 0)
185 regnum
-= ymm0h_regnum
;
186 return regnum
>= 0 && regnum
< tdep
->num_ymm_regs
;
192 i386_ymm_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
194 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
195 int ymm0_regnum
= tdep
->ymm0_regnum
;
200 regnum
-= ymm0_regnum
;
201 return regnum
>= 0 && regnum
< tdep
->num_ymm_regs
;
207 i386_xmm_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
209 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
210 int num_xmm_regs
= I387_NUM_XMM_REGS (tdep
);
212 if (num_xmm_regs
== 0)
215 regnum
-= I387_XMM0_REGNUM (tdep
);
216 return regnum
>= 0 && regnum
< num_xmm_regs
;
220 i386_mxcsr_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
222 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
224 if (I387_NUM_XMM_REGS (tdep
) == 0)
227 return (regnum
== I387_MXCSR_REGNUM (tdep
));
233 i386_fp_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
235 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
237 if (I387_ST0_REGNUM (tdep
) < 0)
240 return (I387_ST0_REGNUM (tdep
) <= regnum
241 && regnum
< I387_FCTRL_REGNUM (tdep
));
245 i386_fpc_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
247 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
249 if (I387_ST0_REGNUM (tdep
) < 0)
252 return (I387_FCTRL_REGNUM (tdep
) <= regnum
253 && regnum
< I387_XMM0_REGNUM (tdep
));
256 /* Return the name of register REGNUM, or the empty string if it is
257 an anonymous register. */
260 i386_register_name (struct gdbarch
*gdbarch
, int regnum
)
262 /* Hide the upper YMM registers. */
263 if (i386_ymmh_regnum_p (gdbarch
, regnum
))
266 return tdesc_register_name (gdbarch
, regnum
);
269 /* Return the name of register REGNUM. */
272 i386_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
274 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
275 if (i386_mmx_regnum_p (gdbarch
, regnum
))
276 return i386_mmx_names
[regnum
- I387_MM0_REGNUM (tdep
)];
277 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
278 return i386_ymm_names
[regnum
- tdep
->ymm0_regnum
];
279 else if (i386_byte_regnum_p (gdbarch
, regnum
))
280 return i386_byte_names
[regnum
- tdep
->al_regnum
];
281 else if (i386_word_regnum_p (gdbarch
, regnum
))
282 return i386_word_names
[regnum
- tdep
->ax_regnum
];
284 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
287 /* Convert a dbx register number REG to the appropriate register
288 number used by GDB. */
291 i386_dbx_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
293 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
295 /* This implements what GCC calls the "default" register map
296 (dbx_register_map[]). */
298 if (reg
>= 0 && reg
<= 7)
300 /* General-purpose registers. The debug info calls %ebp
301 register 4, and %esp register 5. */
308 else if (reg
>= 12 && reg
<= 19)
310 /* Floating-point registers. */
311 return reg
- 12 + I387_ST0_REGNUM (tdep
);
313 else if (reg
>= 21 && reg
<= 28)
316 int ymm0_regnum
= tdep
->ymm0_regnum
;
319 && i386_xmm_regnum_p (gdbarch
, reg
))
320 return reg
- 21 + ymm0_regnum
;
322 return reg
- 21 + I387_XMM0_REGNUM (tdep
);
324 else if (reg
>= 29 && reg
<= 36)
327 return reg
- 29 + I387_MM0_REGNUM (tdep
);
330 /* This will hopefully provoke a warning. */
331 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
334 /* Convert SVR4 register number REG to the appropriate register number
338 i386_svr4_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
340 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
342 /* This implements the GCC register map that tries to be compatible
343 with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */
345 /* The SVR4 register numbering includes %eip and %eflags, and
346 numbers the floating point registers differently. */
347 if (reg
>= 0 && reg
<= 9)
349 /* General-purpose registers. */
352 else if (reg
>= 11 && reg
<= 18)
354 /* Floating-point registers. */
355 return reg
- 11 + I387_ST0_REGNUM (tdep
);
357 else if (reg
>= 21 && reg
<= 36)
359 /* The SSE and MMX registers have the same numbers as with dbx. */
360 return i386_dbx_reg_to_regnum (gdbarch
, reg
);
365 case 37: return I387_FCTRL_REGNUM (tdep
);
366 case 38: return I387_FSTAT_REGNUM (tdep
);
367 case 39: return I387_MXCSR_REGNUM (tdep
);
368 case 40: return I386_ES_REGNUM
;
369 case 41: return I386_CS_REGNUM
;
370 case 42: return I386_SS_REGNUM
;
371 case 43: return I386_DS_REGNUM
;
372 case 44: return I386_FS_REGNUM
;
373 case 45: return I386_GS_REGNUM
;
376 /* This will hopefully provoke a warning. */
377 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
382 /* This is the variable that is set with "set disassembly-flavor", and
383 its legitimate values. */
384 static const char att_flavor
[] = "att";
385 static const char intel_flavor
[] = "intel";
386 static const char *const valid_flavors
[] =
392 static const char *disassembly_flavor
= att_flavor
;
395 /* Use the program counter to determine the contents and size of a
396 breakpoint instruction. Return a pointer to a string of bytes that
397 encode a breakpoint instruction, store the length of the string in
398 *LEN and optionally adjust *PC to point to the correct memory
399 location for inserting the breakpoint.
401 On the i386 we have a single breakpoint that fits in a single byte
402 and can be inserted anywhere.
404 This function is 64-bit safe. */
406 static const gdb_byte
*
407 i386_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pc
, int *len
)
409 static gdb_byte break_insn
[] = { 0xcc }; /* int 3 */
411 *len
= sizeof (break_insn
);
415 /* Displaced instruction handling. */
417 /* Skip the legacy instruction prefixes in INSN.
418 Not all prefixes are valid for any particular insn
419 but we needn't care, the insn will fault if it's invalid.
420 The result is a pointer to the first opcode byte,
421 or NULL if we run off the end of the buffer. */
424 i386_skip_prefixes (gdb_byte
*insn
, size_t max_len
)
426 gdb_byte
*end
= insn
+ max_len
;
432 case DATA_PREFIX_OPCODE
:
433 case ADDR_PREFIX_OPCODE
:
434 case CS_PREFIX_OPCODE
:
435 case DS_PREFIX_OPCODE
:
436 case ES_PREFIX_OPCODE
:
437 case FS_PREFIX_OPCODE
:
438 case GS_PREFIX_OPCODE
:
439 case SS_PREFIX_OPCODE
:
440 case LOCK_PREFIX_OPCODE
:
441 case REPE_PREFIX_OPCODE
:
442 case REPNE_PREFIX_OPCODE
:
454 i386_absolute_jmp_p (const gdb_byte
*insn
)
456 /* jmp far (absolute address in operand). */
462 /* jump near, absolute indirect (/4). */
463 if ((insn
[1] & 0x38) == 0x20)
466 /* jump far, absolute indirect (/5). */
467 if ((insn
[1] & 0x38) == 0x28)
475 i386_absolute_call_p (const gdb_byte
*insn
)
477 /* call far, absolute. */
483 /* Call near, absolute indirect (/2). */
484 if ((insn
[1] & 0x38) == 0x10)
487 /* Call far, absolute indirect (/3). */
488 if ((insn
[1] & 0x38) == 0x18)
496 i386_ret_p (const gdb_byte
*insn
)
500 case 0xc2: /* ret near, pop N bytes. */
501 case 0xc3: /* ret near */
502 case 0xca: /* ret far, pop N bytes. */
503 case 0xcb: /* ret far */
504 case 0xcf: /* iret */
513 i386_call_p (const gdb_byte
*insn
)
515 if (i386_absolute_call_p (insn
))
518 /* call near, relative. */
525 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
526 length in bytes. Otherwise, return zero. */
529 i386_syscall_p (const gdb_byte
*insn
, int *lengthp
)
531 /* Is it 'int $0x80'? */
532 if ((insn
[0] == 0xcd && insn
[1] == 0x80)
533 /* Or is it 'sysenter'? */
534 || (insn
[0] == 0x0f && insn
[1] == 0x34)
535 /* Or is it 'syscall'? */
536 || (insn
[0] == 0x0f && insn
[1] == 0x05))
545 /* Some kernels may run one past a syscall insn, so we have to cope.
546 Otherwise this is just simple_displaced_step_copy_insn. */
548 struct displaced_step_closure
*
549 i386_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
550 CORE_ADDR from
, CORE_ADDR to
,
551 struct regcache
*regs
)
553 size_t len
= gdbarch_max_insn_length (gdbarch
);
554 gdb_byte
*buf
= xmalloc (len
);
556 read_memory (from
, buf
, len
);
558 /* GDB may get control back after the insn after the syscall.
559 Presumably this is a kernel bug.
560 If this is a syscall, make sure there's a nop afterwards. */
565 insn
= i386_skip_prefixes (buf
, len
);
566 if (insn
!= NULL
&& i386_syscall_p (insn
, &syscall_length
))
567 insn
[syscall_length
] = NOP_OPCODE
;
570 write_memory (to
, buf
, len
);
574 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
575 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
576 displaced_step_dump_bytes (gdb_stdlog
, buf
, len
);
579 return (struct displaced_step_closure
*) buf
;
582 /* Fix up the state of registers and memory after having single-stepped
583 a displaced instruction. */
586 i386_displaced_step_fixup (struct gdbarch
*gdbarch
,
587 struct displaced_step_closure
*closure
,
588 CORE_ADDR from
, CORE_ADDR to
,
589 struct regcache
*regs
)
591 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
593 /* The offset we applied to the instruction's address.
594 This could well be negative (when viewed as a signed 32-bit
595 value), but ULONGEST won't reflect that, so take care when
597 ULONGEST insn_offset
= to
- from
;
599 /* Since we use simple_displaced_step_copy_insn, our closure is a
600 copy of the instruction. */
601 gdb_byte
*insn
= (gdb_byte
*) closure
;
602 /* The start of the insn, needed in case we see some prefixes. */
603 gdb_byte
*insn_start
= insn
;
606 fprintf_unfiltered (gdb_stdlog
,
607 "displaced: fixup (%s, %s), "
608 "insn = 0x%02x 0x%02x ...\n",
609 paddress (gdbarch
, from
), paddress (gdbarch
, to
),
612 /* The list of issues to contend with here is taken from
613 resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20.
614 Yay for Free Software! */
616 /* Relocate the %eip, if necessary. */
618 /* The instruction recognizers we use assume any leading prefixes
619 have been skipped. */
621 /* This is the size of the buffer in closure. */
622 size_t max_insn_len
= gdbarch_max_insn_length (gdbarch
);
623 gdb_byte
*opcode
= i386_skip_prefixes (insn
, max_insn_len
);
624 /* If there are too many prefixes, just ignore the insn.
625 It will fault when run. */
630 /* Except in the case of absolute or indirect jump or call
631 instructions, or a return instruction, the new eip is relative to
632 the displaced instruction; make it relative. Well, signal
633 handler returns don't need relocation either, but we use the
634 value of %eip to recognize those; see below. */
635 if (! i386_absolute_jmp_p (insn
)
636 && ! i386_absolute_call_p (insn
)
637 && ! i386_ret_p (insn
))
642 regcache_cooked_read_unsigned (regs
, I386_EIP_REGNUM
, &orig_eip
);
644 /* A signal trampoline system call changes the %eip, resuming
645 execution of the main program after the signal handler has
646 returned. That makes them like 'return' instructions; we
647 shouldn't relocate %eip.
649 But most system calls don't, and we do need to relocate %eip.
651 Our heuristic for distinguishing these cases: if stepping
652 over the system call instruction left control directly after
653 the instruction, the we relocate --- control almost certainly
654 doesn't belong in the displaced copy. Otherwise, we assume
655 the instruction has put control where it belongs, and leave
656 it unrelocated. Goodness help us if there are PC-relative
658 if (i386_syscall_p (insn
, &insn_len
)
659 && orig_eip
!= to
+ (insn
- insn_start
) + insn_len
660 /* GDB can get control back after the insn after the syscall.
661 Presumably this is a kernel bug.
662 i386_displaced_step_copy_insn ensures its a nop,
663 we add one to the length for it. */
664 && orig_eip
!= to
+ (insn
- insn_start
) + insn_len
+ 1)
667 fprintf_unfiltered (gdb_stdlog
,
668 "displaced: syscall changed %%eip; "
673 ULONGEST eip
= (orig_eip
- insn_offset
) & 0xffffffffUL
;
675 /* If we just stepped over a breakpoint insn, we don't backup
676 the pc on purpose; this is to match behaviour without
679 regcache_cooked_write_unsigned (regs
, I386_EIP_REGNUM
, eip
);
682 fprintf_unfiltered (gdb_stdlog
,
684 "relocated %%eip from %s to %s\n",
685 paddress (gdbarch
, orig_eip
),
686 paddress (gdbarch
, eip
));
690 /* If the instruction was PUSHFL, then the TF bit will be set in the
691 pushed value, and should be cleared. We'll leave this for later,
692 since GDB already messes up the TF flag when stepping over a
695 /* If the instruction was a call, the return address now atop the
696 stack is the address following the copied instruction. We need
697 to make it the address following the original instruction. */
698 if (i386_call_p (insn
))
702 const ULONGEST retaddr_len
= 4;
704 regcache_cooked_read_unsigned (regs
, I386_ESP_REGNUM
, &esp
);
705 retaddr
= read_memory_unsigned_integer (esp
, retaddr_len
, byte_order
);
706 retaddr
= (retaddr
- insn_offset
) & 0xffffffffUL
;
707 write_memory_unsigned_integer (esp
, retaddr_len
, byte_order
, retaddr
);
710 fprintf_unfiltered (gdb_stdlog
,
711 "displaced: relocated return addr at %s to %s\n",
712 paddress (gdbarch
, esp
),
713 paddress (gdbarch
, retaddr
));
718 append_insns (CORE_ADDR
*to
, ULONGEST len
, const gdb_byte
*buf
)
720 target_write_memory (*to
, buf
, len
);
725 i386_relocate_instruction (struct gdbarch
*gdbarch
,
726 CORE_ADDR
*to
, CORE_ADDR oldloc
)
728 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
729 gdb_byte buf
[I386_MAX_INSN_LEN
];
730 int offset
= 0, rel32
, newrel
;
732 gdb_byte
*insn
= buf
;
734 read_memory (oldloc
, buf
, I386_MAX_INSN_LEN
);
736 insn_length
= gdb_buffered_insn_length (gdbarch
, insn
,
737 I386_MAX_INSN_LEN
, oldloc
);
739 /* Get past the prefixes. */
740 insn
= i386_skip_prefixes (insn
, I386_MAX_INSN_LEN
);
742 /* Adjust calls with 32-bit relative addresses as push/jump, with
743 the address pushed being the location where the original call in
744 the user program would return to. */
747 gdb_byte push_buf
[16];
748 unsigned int ret_addr
;
750 /* Where "ret" in the original code will return to. */
751 ret_addr
= oldloc
+ insn_length
;
752 push_buf
[0] = 0x68; /* pushq $... */
753 store_unsigned_integer (&push_buf
[1], 4, byte_order
, ret_addr
);
755 append_insns (to
, 5, push_buf
);
757 /* Convert the relative call to a relative jump. */
760 /* Adjust the destination offset. */
761 rel32
= extract_signed_integer (insn
+ 1, 4, byte_order
);
762 newrel
= (oldloc
- *to
) + rel32
;
763 store_signed_integer (insn
+ 1, 4, byte_order
, newrel
);
766 fprintf_unfiltered (gdb_stdlog
,
767 "Adjusted insn rel32=%s at %s to"
769 hex_string (rel32
), paddress (gdbarch
, oldloc
),
770 hex_string (newrel
), paddress (gdbarch
, *to
));
772 /* Write the adjusted jump into its displaced location. */
773 append_insns (to
, 5, insn
);
777 /* Adjust jumps with 32-bit relative addresses. Calls are already
781 /* Adjust conditional jumps. */
782 else if (insn
[0] == 0x0f && (insn
[1] & 0xf0) == 0x80)
787 rel32
= extract_signed_integer (insn
+ offset
, 4, byte_order
);
788 newrel
= (oldloc
- *to
) + rel32
;
789 store_signed_integer (insn
+ offset
, 4, byte_order
, newrel
);
791 fprintf_unfiltered (gdb_stdlog
,
792 "Adjusted insn rel32=%s at %s to"
794 hex_string (rel32
), paddress (gdbarch
, oldloc
),
795 hex_string (newrel
), paddress (gdbarch
, *to
));
798 /* Write the adjusted instructions into their displaced
800 append_insns (to
, insn_length
, buf
);
804 #ifdef I386_REGNO_TO_SYMMETRY
805 #error "The Sequent Symmetry is no longer supported."
808 /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi
809 and %esp "belong" to the calling function. Therefore these
810 registers should be saved if they're going to be modified. */
812 /* The maximum number of saved registers. This should include all
813 registers mentioned above, and %eip. */
814 #define I386_NUM_SAVED_REGS I386_NUM_GREGS
816 struct i386_frame_cache
824 /* Saved registers. */
825 CORE_ADDR saved_regs
[I386_NUM_SAVED_REGS
];
830 /* Stack space reserved for local variables. */
834 /* Allocate and initialize a frame cache. */
836 static struct i386_frame_cache
*
837 i386_alloc_frame_cache (void)
839 struct i386_frame_cache
*cache
;
842 cache
= FRAME_OBSTACK_ZALLOC (struct i386_frame_cache
);
847 cache
->sp_offset
= -4;
850 /* Saved registers. We initialize these to -1 since zero is a valid
851 offset (that's where %ebp is supposed to be stored). */
852 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
853 cache
->saved_regs
[i
] = -1;
855 cache
->saved_sp_reg
= -1;
856 cache
->pc_in_eax
= 0;
858 /* Frameless until proven otherwise. */
864 /* If the instruction at PC is a jump, return the address of its
865 target. Otherwise, return PC. */
868 i386_follow_jump (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
870 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
875 if (target_read_memory (pc
, &op
, 1))
881 op
= read_memory_unsigned_integer (pc
+ 1, 1, byte_order
);
887 /* Relative jump: if data16 == 0, disp32, else disp16. */
890 delta
= read_memory_integer (pc
+ 2, 2, byte_order
);
892 /* Include the size of the jmp instruction (including the
898 delta
= read_memory_integer (pc
+ 1, 4, byte_order
);
900 /* Include the size of the jmp instruction. */
905 /* Relative jump, disp8 (ignore data16). */
906 delta
= read_memory_integer (pc
+ data16
+ 1, 1, byte_order
);
915 /* Check whether PC points at a prologue for a function returning a
916 structure or union. If so, it updates CACHE and returns the
917 address of the first instruction after the code sequence that
918 removes the "hidden" argument from the stack or CURRENT_PC,
919 whichever is smaller. Otherwise, return PC. */
922 i386_analyze_struct_return (CORE_ADDR pc
, CORE_ADDR current_pc
,
923 struct i386_frame_cache
*cache
)
925 /* Functions that return a structure or union start with:
928 xchgl %eax, (%esp) 0x87 0x04 0x24
929 or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00
931 (the System V compiler puts out the second `xchg' instruction,
932 and the assembler doesn't try to optimize it, so the 'sib' form
933 gets generated). This sequence is used to get the address of the
934 return buffer for a function that returns a structure. */
935 static gdb_byte proto1
[3] = { 0x87, 0x04, 0x24 };
936 static gdb_byte proto2
[4] = { 0x87, 0x44, 0x24, 0x00 };
940 if (current_pc
<= pc
)
943 if (target_read_memory (pc
, &op
, 1))
946 if (op
!= 0x58) /* popl %eax */
949 if (target_read_memory (pc
+ 1, buf
, 4))
952 if (memcmp (buf
, proto1
, 3) != 0 && memcmp (buf
, proto2
, 4) != 0)
955 if (current_pc
== pc
)
957 cache
->sp_offset
+= 4;
961 if (current_pc
== pc
+ 1)
963 cache
->pc_in_eax
= 1;
967 if (buf
[1] == proto1
[1])
974 i386_skip_probe (CORE_ADDR pc
)
976 /* A function may start with
990 if (target_read_memory (pc
, &op
, 1))
993 if (op
== 0x68 || op
== 0x6a)
997 /* Skip past the `pushl' instruction; it has either a one-byte or a
998 four-byte operand, depending on the opcode. */
1004 /* Read the following 8 bytes, which should be `call _probe' (6
1005 bytes) followed by `addl $4,%esp' (2 bytes). */
1006 read_memory (pc
+ delta
, buf
, sizeof (buf
));
1007 if (buf
[0] == 0xe8 && buf
[6] == 0xc4 && buf
[7] == 0x4)
1008 pc
+= delta
+ sizeof (buf
);
1014 /* GCC 4.1 and later, can put code in the prologue to realign the
1015 stack pointer. Check whether PC points to such code, and update
1016 CACHE accordingly. Return the first instruction after the code
1017 sequence or CURRENT_PC, whichever is smaller. If we don't
1018 recognize the code, return PC. */
1021 i386_analyze_stack_align (CORE_ADDR pc
, CORE_ADDR current_pc
,
1022 struct i386_frame_cache
*cache
)
1024 /* There are 2 code sequences to re-align stack before the frame
1027 1. Use a caller-saved saved register:
1033 2. Use a callee-saved saved register:
1040 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
1042 0x83 0xe4 0xf0 andl $-16, %esp
1043 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
1048 int offset
, offset_and
;
1049 static int regnums
[8] = {
1050 I386_EAX_REGNUM
, /* %eax */
1051 I386_ECX_REGNUM
, /* %ecx */
1052 I386_EDX_REGNUM
, /* %edx */
1053 I386_EBX_REGNUM
, /* %ebx */
1054 I386_ESP_REGNUM
, /* %esp */
1055 I386_EBP_REGNUM
, /* %ebp */
1056 I386_ESI_REGNUM
, /* %esi */
1057 I386_EDI_REGNUM
/* %edi */
1060 if (target_read_memory (pc
, buf
, sizeof buf
))
1063 /* Check caller-saved saved register. The first instruction has
1064 to be "leal 4(%esp), %reg". */
1065 if (buf
[0] == 0x8d && buf
[2] == 0x24 && buf
[3] == 0x4)
1067 /* MOD must be binary 10 and R/M must be binary 100. */
1068 if ((buf
[1] & 0xc7) != 0x44)
1071 /* REG has register number. */
1072 reg
= (buf
[1] >> 3) & 7;
1077 /* Check callee-saved saved register. The first instruction
1078 has to be "pushl %reg". */
1079 if ((buf
[0] & 0xf8) != 0x50)
1085 /* The next instruction has to be "leal 8(%esp), %reg". */
1086 if (buf
[1] != 0x8d || buf
[3] != 0x24 || buf
[4] != 0x8)
1089 /* MOD must be binary 10 and R/M must be binary 100. */
1090 if ((buf
[2] & 0xc7) != 0x44)
1093 /* REG has register number. Registers in pushl and leal have to
1095 if (reg
!= ((buf
[2] >> 3) & 7))
1101 /* Rigister can't be %esp nor %ebp. */
1102 if (reg
== 4 || reg
== 5)
1105 /* The next instruction has to be "andl $-XXX, %esp". */
1106 if (buf
[offset
+ 1] != 0xe4
1107 || (buf
[offset
] != 0x81 && buf
[offset
] != 0x83))
1110 offset_and
= offset
;
1111 offset
+= buf
[offset
] == 0x81 ? 6 : 3;
1113 /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is
1114 0xfc. REG must be binary 110 and MOD must be binary 01. */
1115 if (buf
[offset
] != 0xff
1116 || buf
[offset
+ 2] != 0xfc
1117 || (buf
[offset
+ 1] & 0xf8) != 0x70)
1120 /* R/M has register. Registers in leal and pushl have to be the
1122 if (reg
!= (buf
[offset
+ 1] & 7))
1125 if (current_pc
> pc
+ offset_and
)
1126 cache
->saved_sp_reg
= regnums
[reg
];
1128 return min (pc
+ offset
+ 3, current_pc
);
1131 /* Maximum instruction length we need to handle. */
1132 #define I386_MAX_MATCHED_INSN_LEN 6
1134 /* Instruction description. */
1138 gdb_byte insn
[I386_MAX_MATCHED_INSN_LEN
];
1139 gdb_byte mask
[I386_MAX_MATCHED_INSN_LEN
];
1142 /* Return whether instruction at PC matches PATTERN. */
1145 i386_match_pattern (CORE_ADDR pc
, struct i386_insn pattern
)
1149 if (target_read_memory (pc
, &op
, 1))
1152 if ((op
& pattern
.mask
[0]) == pattern
.insn
[0])
1154 gdb_byte buf
[I386_MAX_MATCHED_INSN_LEN
- 1];
1155 int insn_matched
= 1;
1158 gdb_assert (pattern
.len
> 1);
1159 gdb_assert (pattern
.len
<= I386_MAX_MATCHED_INSN_LEN
);
1161 if (target_read_memory (pc
+ 1, buf
, pattern
.len
- 1))
1164 for (i
= 1; i
< pattern
.len
; i
++)
1166 if ((buf
[i
- 1] & pattern
.mask
[i
]) != pattern
.insn
[i
])
1169 return insn_matched
;
1174 /* Search for the instruction at PC in the list INSN_PATTERNS. Return
1175 the first instruction description that matches. Otherwise, return
1178 static struct i386_insn
*
1179 i386_match_insn (CORE_ADDR pc
, struct i386_insn
*insn_patterns
)
1181 struct i386_insn
*pattern
;
1183 for (pattern
= insn_patterns
; pattern
->len
> 0; pattern
++)
1185 if (i386_match_pattern (pc
, *pattern
))
1192 /* Return whether PC points inside a sequence of instructions that
1193 matches INSN_PATTERNS. */
1196 i386_match_insn_block (CORE_ADDR pc
, struct i386_insn
*insn_patterns
)
1198 CORE_ADDR current_pc
;
1200 struct i386_insn
*insn
;
1202 insn
= i386_match_insn (pc
, insn_patterns
);
1207 ix
= insn
- insn_patterns
;
1208 for (i
= ix
- 1; i
>= 0; i
--)
1210 current_pc
-= insn_patterns
[i
].len
;
1212 if (!i386_match_pattern (current_pc
, insn_patterns
[i
]))
1216 current_pc
= pc
+ insn
->len
;
1217 for (insn
= insn_patterns
+ ix
+ 1; insn
->len
> 0; insn
++)
1219 if (!i386_match_pattern (current_pc
, *insn
))
1222 current_pc
+= insn
->len
;
1228 /* Some special instructions that might be migrated by GCC into the
1229 part of the prologue that sets up the new stack frame. Because the
1230 stack frame hasn't been setup yet, no registers have been saved
1231 yet, and only the scratch registers %eax, %ecx and %edx can be
1234 struct i386_insn i386_frame_setup_skip_insns
[] =
1236 /* Check for `movb imm8, r' and `movl imm32, r'.
1238 ??? Should we handle 16-bit operand-sizes here? */
1240 /* `movb imm8, %al' and `movb imm8, %ah' */
1241 /* `movb imm8, %cl' and `movb imm8, %ch' */
1242 { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } },
1243 /* `movb imm8, %dl' and `movb imm8, %dh' */
1244 { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } },
1245 /* `movl imm32, %eax' and `movl imm32, %ecx' */
1246 { 5, { 0xb8 }, { 0xfe } },
1247 /* `movl imm32, %edx' */
1248 { 5, { 0xba }, { 0xff } },
1250 /* Check for `mov imm32, r32'. Note that there is an alternative
1251 encoding for `mov m32, %eax'.
1253 ??? Should we handle SIB adressing here?
1254 ??? Should we handle 16-bit operand-sizes here? */
1256 /* `movl m32, %eax' */
1257 { 5, { 0xa1 }, { 0xff } },
1258 /* `movl m32, %eax' and `mov; m32, %ecx' */
1259 { 6, { 0x89, 0x05 }, {0xff, 0xf7 } },
1260 /* `movl m32, %edx' */
1261 { 6, { 0x89, 0x15 }, {0xff, 0xff } },
1263 /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'.
1264 Because of the symmetry, there are actually two ways to encode
1265 these instructions; opcode bytes 0x29 and 0x2b for `subl' and
1266 opcode bytes 0x31 and 0x33 for `xorl'. */
1268 /* `subl %eax, %eax' */
1269 { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } },
1270 /* `subl %ecx, %ecx' */
1271 { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } },
1272 /* `subl %edx, %edx' */
1273 { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } },
1274 /* `xorl %eax, %eax' */
1275 { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } },
1276 /* `xorl %ecx, %ecx' */
1277 { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } },
1278 /* `xorl %edx, %edx' */
1279 { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } },
1284 /* Check whether PC points to a no-op instruction. */
1286 i386_skip_noop (CORE_ADDR pc
)
1291 if (target_read_memory (pc
, &op
, 1))
1297 /* Ignore `nop' instruction. */
1301 if (target_read_memory (pc
, &op
, 1))
1305 /* Ignore no-op instruction `mov %edi, %edi'.
1306 Microsoft system dlls often start with
1307 a `mov %edi,%edi' instruction.
1308 The 5 bytes before the function start are
1309 filled with `nop' instructions.
1310 This pattern can be used for hot-patching:
1311 The `mov %edi, %edi' instruction can be replaced by a
1312 near jump to the location of the 5 `nop' instructions
1313 which can be replaced by a 32-bit jump to anywhere
1314 in the 32-bit address space. */
1316 else if (op
== 0x8b)
1318 if (target_read_memory (pc
+ 1, &op
, 1))
1324 if (target_read_memory (pc
, &op
, 1))
1334 /* Check whether PC points at a code that sets up a new stack frame.
1335 If so, it updates CACHE and returns the address of the first
1336 instruction after the sequence that sets up the frame or LIMIT,
1337 whichever is smaller. If we don't recognize the code, return PC. */
1340 i386_analyze_frame_setup (struct gdbarch
*gdbarch
,
1341 CORE_ADDR pc
, CORE_ADDR limit
,
1342 struct i386_frame_cache
*cache
)
1344 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1345 struct i386_insn
*insn
;
1352 if (target_read_memory (pc
, &op
, 1))
1355 if (op
== 0x55) /* pushl %ebp */
1357 /* Take into account that we've executed the `pushl %ebp' that
1358 starts this instruction sequence. */
1359 cache
->saved_regs
[I386_EBP_REGNUM
] = 0;
1360 cache
->sp_offset
+= 4;
1363 /* If that's all, return now. */
1367 /* Check for some special instructions that might be migrated by
1368 GCC into the prologue and skip them. At this point in the
1369 prologue, code should only touch the scratch registers %eax,
1370 %ecx and %edx, so while the number of posibilities is sheer,
1373 Make sure we only skip these instructions if we later see the
1374 `movl %esp, %ebp' that actually sets up the frame. */
1375 while (pc
+ skip
< limit
)
1377 insn
= i386_match_insn (pc
+ skip
, i386_frame_setup_skip_insns
);
1384 /* If that's all, return now. */
1385 if (limit
<= pc
+ skip
)
1388 if (target_read_memory (pc
+ skip
, &op
, 1))
1391 /* The i386 prologue looks like
1397 and a different prologue can be generated for atom.
1401 lea -0x10(%esp),%esp
1403 We handle both of them here. */
1407 /* Check for `movl %esp, %ebp' -- can be written in two ways. */
1409 if (read_memory_unsigned_integer (pc
+ skip
+ 1, 1, byte_order
)
1415 if (read_memory_unsigned_integer (pc
+ skip
+ 1, 1, byte_order
)
1420 case 0x8d: /* Check for 'lea (%ebp), %ebp'. */
1421 if (read_memory_unsigned_integer (pc
+ skip
+ 1, 2, byte_order
)
1430 /* OK, we actually have a frame. We just don't know how large
1431 it is yet. Set its size to zero. We'll adjust it if
1432 necessary. We also now commit to skipping the special
1433 instructions mentioned before. */
1436 /* If that's all, return now. */
1440 /* Check for stack adjustment
1446 NOTE: You can't subtract a 16-bit immediate from a 32-bit
1447 reg, so we don't have to worry about a data16 prefix. */
1448 if (target_read_memory (pc
, &op
, 1))
1452 /* `subl' with 8-bit immediate. */
1453 if (read_memory_unsigned_integer (pc
+ 1, 1, byte_order
) != 0xec)
1454 /* Some instruction starting with 0x83 other than `subl'. */
1457 /* `subl' with signed 8-bit immediate (though it wouldn't
1458 make sense to be negative). */
1459 cache
->locals
= read_memory_integer (pc
+ 2, 1, byte_order
);
1462 else if (op
== 0x81)
1464 /* Maybe it is `subl' with a 32-bit immediate. */
1465 if (read_memory_unsigned_integer (pc
+ 1, 1, byte_order
) != 0xec)
1466 /* Some instruction starting with 0x81 other than `subl'. */
1469 /* It is `subl' with a 32-bit immediate. */
1470 cache
->locals
= read_memory_integer (pc
+ 2, 4, byte_order
);
1473 else if (op
== 0x8d)
1475 /* The ModR/M byte is 0x64. */
1476 if (read_memory_unsigned_integer (pc
+ 1, 1, byte_order
) != 0x64)
1478 /* 'lea' with 8-bit displacement. */
1479 cache
->locals
= -1 * read_memory_integer (pc
+ 3, 1, byte_order
);
1484 /* Some instruction other than `subl' nor 'lea'. */
1488 else if (op
== 0xc8) /* enter */
1490 cache
->locals
= read_memory_unsigned_integer (pc
+ 1, 2, byte_order
);
1497 /* Check whether PC points at code that saves registers on the stack.
1498 If so, it updates CACHE and returns the address of the first
1499 instruction after the register saves or CURRENT_PC, whichever is
1500 smaller. Otherwise, return PC. */
1503 i386_analyze_register_saves (CORE_ADDR pc
, CORE_ADDR current_pc
,
1504 struct i386_frame_cache
*cache
)
1506 CORE_ADDR offset
= 0;
1510 if (cache
->locals
> 0)
1511 offset
-= cache
->locals
;
1512 for (i
= 0; i
< 8 && pc
< current_pc
; i
++)
1514 if (target_read_memory (pc
, &op
, 1))
1516 if (op
< 0x50 || op
> 0x57)
1520 cache
->saved_regs
[op
- 0x50] = offset
;
1521 cache
->sp_offset
+= 4;
1528 /* Do a full analysis of the prologue at PC and update CACHE
1529 accordingly. Bail out early if CURRENT_PC is reached. Return the
1530 address where the analysis stopped.
1532 We handle these cases:
1534 The startup sequence can be at the start of the function, or the
1535 function can start with a branch to startup code at the end.
1537 %ebp can be set up with either the 'enter' instruction, or "pushl
1538 %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was
1539 once used in the System V compiler).
1541 Local space is allocated just below the saved %ebp by either the
1542 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a
1543 16-bit unsigned argument for space to allocate, and the 'addl'
1544 instruction could have either a signed byte, or 32-bit immediate.
1546 Next, the registers used by this function are pushed. With the
1547 System V compiler they will always be in the order: %edi, %esi,
1548 %ebx (and sometimes a harmless bug causes it to also save but not
1549 restore %eax); however, the code below is willing to see the pushes
1550 in any order, and will handle up to 8 of them.
1552 If the setup sequence is at the end of the function, then the next
1553 instruction will be a branch back to the start. */
1556 i386_analyze_prologue (struct gdbarch
*gdbarch
,
1557 CORE_ADDR pc
, CORE_ADDR current_pc
,
1558 struct i386_frame_cache
*cache
)
1560 pc
= i386_skip_noop (pc
);
1561 pc
= i386_follow_jump (gdbarch
, pc
);
1562 pc
= i386_analyze_struct_return (pc
, current_pc
, cache
);
1563 pc
= i386_skip_probe (pc
);
1564 pc
= i386_analyze_stack_align (pc
, current_pc
, cache
);
1565 pc
= i386_analyze_frame_setup (gdbarch
, pc
, current_pc
, cache
);
1566 return i386_analyze_register_saves (pc
, current_pc
, cache
);
1569 /* Return PC of first real instruction. */
1572 i386_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
1574 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1576 static gdb_byte pic_pat
[6] =
1578 0xe8, 0, 0, 0, 0, /* call 0x0 */
1579 0x5b, /* popl %ebx */
1581 struct i386_frame_cache cache
;
1585 CORE_ADDR func_addr
;
1587 if (find_pc_partial_function (start_pc
, NULL
, &func_addr
, NULL
))
1589 CORE_ADDR post_prologue_pc
1590 = skip_prologue_using_sal (gdbarch
, func_addr
);
1591 struct symtab
*s
= find_pc_symtab (func_addr
);
1593 /* Clang always emits a line note before the prologue and another
1594 one after. We trust clang to emit usable line notes. */
1595 if (post_prologue_pc
1597 && s
->producer
!= NULL
1598 && strncmp (s
->producer
, "clang ", sizeof ("clang ") - 1) == 0))
1599 return max (start_pc
, post_prologue_pc
);
1603 pc
= i386_analyze_prologue (gdbarch
, start_pc
, 0xffffffff, &cache
);
1604 if (cache
.locals
< 0)
1607 /* Found valid frame setup. */
1609 /* The native cc on SVR4 in -K PIC mode inserts the following code
1610 to get the address of the global offset table (GOT) into register
1615 movl %ebx,x(%ebp) (optional)
1618 This code is with the rest of the prologue (at the end of the
1619 function), so we have to skip it to get to the first real
1620 instruction at the start of the function. */
1622 for (i
= 0; i
< 6; i
++)
1624 if (target_read_memory (pc
+ i
, &op
, 1))
1627 if (pic_pat
[i
] != op
)
1634 if (target_read_memory (pc
+ delta
, &op
, 1))
1637 if (op
== 0x89) /* movl %ebx, x(%ebp) */
1639 op
= read_memory_unsigned_integer (pc
+ delta
+ 1, 1, byte_order
);
1641 if (op
== 0x5d) /* One byte offset from %ebp. */
1643 else if (op
== 0x9d) /* Four byte offset from %ebp. */
1645 else /* Unexpected instruction. */
1648 if (target_read_memory (pc
+ delta
, &op
, 1))
1653 if (delta
> 0 && op
== 0x81
1654 && read_memory_unsigned_integer (pc
+ delta
+ 1, 1, byte_order
)
1661 /* If the function starts with a branch (to startup code at the end)
1662 the last instruction should bring us back to the first
1663 instruction of the real code. */
1664 if (i386_follow_jump (gdbarch
, start_pc
) != start_pc
)
1665 pc
= i386_follow_jump (gdbarch
, pc
);
1670 /* Check that the code pointed to by PC corresponds to a call to
1671 __main, skip it if so. Return PC otherwise. */
1674 i386_skip_main_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1676 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1679 if (target_read_memory (pc
, &op
, 1))
1685 if (target_read_memory (pc
+ 1, buf
, sizeof buf
) == 0)
1687 /* Make sure address is computed correctly as a 32bit
1688 integer even if CORE_ADDR is 64 bit wide. */
1689 struct minimal_symbol
*s
;
1690 CORE_ADDR call_dest
;
1692 call_dest
= pc
+ 5 + extract_signed_integer (buf
, 4, byte_order
);
1693 call_dest
= call_dest
& 0xffffffffU
;
1694 s
= lookup_minimal_symbol_by_pc (call_dest
);
1696 && SYMBOL_LINKAGE_NAME (s
) != NULL
1697 && strcmp (SYMBOL_LINKAGE_NAME (s
), "__main") == 0)
1705 /* This function is 64-bit safe. */
1708 i386_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1712 frame_unwind_register (next_frame
, gdbarch_pc_regnum (gdbarch
), buf
);
1713 return extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
1717 /* Normal frames. */
1720 i386_frame_cache_1 (struct frame_info
*this_frame
,
1721 struct i386_frame_cache
*cache
)
1723 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1724 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1728 cache
->pc
= get_frame_func (this_frame
);
1730 /* In principle, for normal frames, %ebp holds the frame pointer,
1731 which holds the base address for the current stack frame.
1732 However, for functions that don't need it, the frame pointer is
1733 optional. For these "frameless" functions the frame pointer is
1734 actually the frame pointer of the calling frame. Signal
1735 trampolines are just a special case of a "frameless" function.
1736 They (usually) share their frame pointer with the frame that was
1737 in progress when the signal occurred. */
1739 get_frame_register (this_frame
, I386_EBP_REGNUM
, buf
);
1740 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
);
1741 if (cache
->base
== 0)
1747 /* For normal frames, %eip is stored at 4(%ebp). */
1748 cache
->saved_regs
[I386_EIP_REGNUM
] = 4;
1751 i386_analyze_prologue (gdbarch
, cache
->pc
, get_frame_pc (this_frame
),
1754 if (cache
->locals
< 0)
1756 /* We didn't find a valid frame, which means that CACHE->base
1757 currently holds the frame pointer for our calling frame. If
1758 we're at the start of a function, or somewhere half-way its
1759 prologue, the function's frame probably hasn't been fully
1760 setup yet. Try to reconstruct the base address for the stack
1761 frame by looking at the stack pointer. For truly "frameless"
1762 functions this might work too. */
1764 if (cache
->saved_sp_reg
!= -1)
1766 /* Saved stack pointer has been saved. */
1767 get_frame_register (this_frame
, cache
->saved_sp_reg
, buf
);
1768 cache
->saved_sp
= extract_unsigned_integer (buf
, 4, byte_order
);
1770 /* We're halfway aligning the stack. */
1771 cache
->base
= ((cache
->saved_sp
- 4) & 0xfffffff0) - 4;
1772 cache
->saved_regs
[I386_EIP_REGNUM
] = cache
->saved_sp
- 4;
1774 /* This will be added back below. */
1775 cache
->saved_regs
[I386_EIP_REGNUM
] -= cache
->base
;
1777 else if (cache
->pc
!= 0
1778 || target_read_memory (get_frame_pc (this_frame
), buf
, 1))
1780 /* We're in a known function, but did not find a frame
1781 setup. Assume that the function does not use %ebp.
1782 Alternatively, we may have jumped to an invalid
1783 address; in that case there is definitely no new
1785 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
1786 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
)
1790 /* We're in an unknown function. We could not find the start
1791 of the function to analyze the prologue; our best option is
1792 to assume a typical frame layout with the caller's %ebp
1794 cache
->saved_regs
[I386_EBP_REGNUM
] = 0;
1797 if (cache
->saved_sp_reg
!= -1)
1799 /* Saved stack pointer has been saved (but the SAVED_SP_REG
1800 register may be unavailable). */
1801 if (cache
->saved_sp
== 0
1802 && deprecated_frame_register_read (this_frame
,
1803 cache
->saved_sp_reg
, buf
))
1804 cache
->saved_sp
= extract_unsigned_integer (buf
, 4, byte_order
);
1806 /* Now that we have the base address for the stack frame we can
1807 calculate the value of %esp in the calling frame. */
1808 else if (cache
->saved_sp
== 0)
1809 cache
->saved_sp
= cache
->base
+ 8;
1811 /* Adjust all the saved registers such that they contain addresses
1812 instead of offsets. */
1813 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
1814 if (cache
->saved_regs
[i
] != -1)
1815 cache
->saved_regs
[i
] += cache
->base
;
1820 static struct i386_frame_cache
*
1821 i386_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1823 volatile struct gdb_exception ex
;
1824 struct i386_frame_cache
*cache
;
1829 cache
= i386_alloc_frame_cache ();
1830 *this_cache
= cache
;
1832 TRY_CATCH (ex
, RETURN_MASK_ERROR
)
1834 i386_frame_cache_1 (this_frame
, cache
);
1836 if (ex
.reason
< 0 && ex
.error
!= NOT_AVAILABLE_ERROR
)
1837 throw_exception (ex
);
1843 i386_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
1844 struct frame_id
*this_id
)
1846 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1848 /* This marks the outermost frame. */
1849 if (cache
->base
== 0)
1852 /* See the end of i386_push_dummy_call. */
1853 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
1856 static enum unwind_stop_reason
1857 i386_frame_unwind_stop_reason (struct frame_info
*this_frame
,
1860 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1863 return UNWIND_UNAVAILABLE
;
1865 /* This marks the outermost frame. */
1866 if (cache
->base
== 0)
1867 return UNWIND_OUTERMOST
;
1869 return UNWIND_NO_REASON
;
1872 static struct value
*
1873 i386_frame_prev_register (struct frame_info
*this_frame
, void **this_cache
,
1876 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1878 gdb_assert (regnum
>= 0);
1880 /* The System V ABI says that:
1882 "The flags register contains the system flags, such as the
1883 direction flag and the carry flag. The direction flag must be
1884 set to the forward (that is, zero) direction before entry and
1885 upon exit from a function. Other user flags have no specified
1886 role in the standard calling sequence and are not preserved."
1888 To guarantee the "upon exit" part of that statement we fake a
1889 saved flags register that has its direction flag cleared.
1891 Note that GCC doesn't seem to rely on the fact that the direction
1892 flag is cleared after a function return; it always explicitly
1893 clears the flag before operations where it matters.
1895 FIXME: kettenis/20030316: I'm not quite sure whether this is the
1896 right thing to do. The way we fake the flags register here makes
1897 it impossible to change it. */
1899 if (regnum
== I386_EFLAGS_REGNUM
)
1903 val
= get_frame_register_unsigned (this_frame
, regnum
);
1905 return frame_unwind_got_constant (this_frame
, regnum
, val
);
1908 if (regnum
== I386_EIP_REGNUM
&& cache
->pc_in_eax
)
1909 return frame_unwind_got_register (this_frame
, regnum
, I386_EAX_REGNUM
);
1911 if (regnum
== I386_ESP_REGNUM
1912 && (cache
->saved_sp
!= 0 || cache
->saved_sp_reg
!= -1))
1914 /* If the SP has been saved, but we don't know where, then this
1915 means that SAVED_SP_REG register was found unavailable back
1916 when we built the cache. */
1917 if (cache
->saved_sp
== 0)
1918 return frame_unwind_got_register (this_frame
, regnum
,
1919 cache
->saved_sp_reg
);
1921 return frame_unwind_got_constant (this_frame
, regnum
,
1925 if (regnum
< I386_NUM_SAVED_REGS
&& cache
->saved_regs
[regnum
] != -1)
1926 return frame_unwind_got_memory (this_frame
, regnum
,
1927 cache
->saved_regs
[regnum
]);
1929 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
1932 static const struct frame_unwind i386_frame_unwind
=
1935 i386_frame_unwind_stop_reason
,
1937 i386_frame_prev_register
,
1939 default_frame_sniffer
1942 /* Normal frames, but in a function epilogue. */
1944 /* The epilogue is defined here as the 'ret' instruction, which will
1945 follow any instruction such as 'leave' or 'pop %ebp' that destroys
1946 the function's stack frame. */
1949 i386_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1952 struct symtab
*symtab
;
1954 symtab
= find_pc_symtab (pc
);
1955 if (symtab
&& symtab
->epilogue_unwind_valid
)
1958 if (target_read_memory (pc
, &insn
, 1))
1959 return 0; /* Can't read memory at pc. */
1961 if (insn
!= 0xc3) /* 'ret' instruction. */
1968 i386_epilogue_frame_sniffer (const struct frame_unwind
*self
,
1969 struct frame_info
*this_frame
,
1970 void **this_prologue_cache
)
1972 if (frame_relative_level (this_frame
) == 0)
1973 return i386_in_function_epilogue_p (get_frame_arch (this_frame
),
1974 get_frame_pc (this_frame
));
1979 static struct i386_frame_cache
*
1980 i386_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1982 volatile struct gdb_exception ex
;
1983 struct i386_frame_cache
*cache
;
1989 cache
= i386_alloc_frame_cache ();
1990 *this_cache
= cache
;
1992 TRY_CATCH (ex
, RETURN_MASK_ERROR
)
1994 cache
->pc
= get_frame_func (this_frame
);
1996 /* At this point the stack looks as if we just entered the
1997 function, with the return address at the top of the
1999 sp
= get_frame_register_unsigned (this_frame
, I386_ESP_REGNUM
);
2000 cache
->base
= sp
+ cache
->sp_offset
;
2001 cache
->saved_sp
= cache
->base
+ 8;
2002 cache
->saved_regs
[I386_EIP_REGNUM
] = cache
->base
+ 4;
2006 if (ex
.reason
< 0 && ex
.error
!= NOT_AVAILABLE_ERROR
)
2007 throw_exception (ex
);
2012 static enum unwind_stop_reason
2013 i386_epilogue_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2016 struct i386_frame_cache
*cache
=
2017 i386_epilogue_frame_cache (this_frame
, this_cache
);
2020 return UNWIND_UNAVAILABLE
;
2022 return UNWIND_NO_REASON
;
2026 i386_epilogue_frame_this_id (struct frame_info
*this_frame
,
2028 struct frame_id
*this_id
)
2030 struct i386_frame_cache
*cache
=
2031 i386_epilogue_frame_cache (this_frame
, this_cache
);
2036 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
2039 static struct value
*
2040 i386_epilogue_frame_prev_register (struct frame_info
*this_frame
,
2041 void **this_cache
, int regnum
)
2043 /* Make sure we've initialized the cache. */
2044 i386_epilogue_frame_cache (this_frame
, this_cache
);
2046 return i386_frame_prev_register (this_frame
, this_cache
, regnum
);
2049 static const struct frame_unwind i386_epilogue_frame_unwind
=
2052 i386_epilogue_frame_unwind_stop_reason
,
2053 i386_epilogue_frame_this_id
,
2054 i386_epilogue_frame_prev_register
,
2056 i386_epilogue_frame_sniffer
2060 /* Stack-based trampolines. */
2062 /* These trampolines are used on cross x86 targets, when taking the
2063 address of a nested function. When executing these trampolines,
2064 no stack frame is set up, so we are in a similar situation as in
2065 epilogues and i386_epilogue_frame_this_id can be re-used. */
2067 /* Static chain passed in register. */
2069 struct i386_insn i386_tramp_chain_in_reg_insns
[] =
2071 /* `movl imm32, %eax' and `movl imm32, %ecx' */
2072 { 5, { 0xb8 }, { 0xfe } },
2075 { 5, { 0xe9 }, { 0xff } },
2080 /* Static chain passed on stack (when regparm=3). */
2082 struct i386_insn i386_tramp_chain_on_stack_insns
[] =
2085 { 5, { 0x68 }, { 0xff } },
2088 { 5, { 0xe9 }, { 0xff } },
2093 /* Return whether PC points inside a stack trampoline. */
2096 i386_in_stack_tramp_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2101 /* A stack trampoline is detected if no name is associated
2102 to the current pc and if it points inside a trampoline
2105 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
2109 if (target_read_memory (pc
, &insn
, 1))
2112 if (!i386_match_insn_block (pc
, i386_tramp_chain_in_reg_insns
)
2113 && !i386_match_insn_block (pc
, i386_tramp_chain_on_stack_insns
))
2120 i386_stack_tramp_frame_sniffer (const struct frame_unwind
*self
,
2121 struct frame_info
*this_frame
,
2124 if (frame_relative_level (this_frame
) == 0)
2125 return i386_in_stack_tramp_p (get_frame_arch (this_frame
),
2126 get_frame_pc (this_frame
));
2131 static const struct frame_unwind i386_stack_tramp_frame_unwind
=
2134 i386_epilogue_frame_unwind_stop_reason
,
2135 i386_epilogue_frame_this_id
,
2136 i386_epilogue_frame_prev_register
,
2138 i386_stack_tramp_frame_sniffer
2141 /* Generate a bytecode expression to get the value of the saved PC. */
2144 i386_gen_return_address (struct gdbarch
*gdbarch
,
2145 struct agent_expr
*ax
, struct axs_value
*value
,
2148 /* The following sequence assumes the traditional use of the base
2150 ax_reg (ax
, I386_EBP_REGNUM
);
2152 ax_simple (ax
, aop_add
);
2153 value
->type
= register_type (gdbarch
, I386_EIP_REGNUM
);
2154 value
->kind
= axs_lvalue_memory
;
2158 /* Signal trampolines. */
2160 static struct i386_frame_cache
*
2161 i386_sigtramp_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2163 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2164 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2165 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2166 volatile struct gdb_exception ex
;
2167 struct i386_frame_cache
*cache
;
2174 cache
= i386_alloc_frame_cache ();
2176 TRY_CATCH (ex
, RETURN_MASK_ERROR
)
2178 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
2179 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
) - 4;
2181 addr
= tdep
->sigcontext_addr (this_frame
);
2182 if (tdep
->sc_reg_offset
)
2186 gdb_assert (tdep
->sc_num_regs
<= I386_NUM_SAVED_REGS
);
2188 for (i
= 0; i
< tdep
->sc_num_regs
; i
++)
2189 if (tdep
->sc_reg_offset
[i
] != -1)
2190 cache
->saved_regs
[i
] = addr
+ tdep
->sc_reg_offset
[i
];
2194 cache
->saved_regs
[I386_EIP_REGNUM
] = addr
+ tdep
->sc_pc_offset
;
2195 cache
->saved_regs
[I386_ESP_REGNUM
] = addr
+ tdep
->sc_sp_offset
;
2200 if (ex
.reason
< 0 && ex
.error
!= NOT_AVAILABLE_ERROR
)
2201 throw_exception (ex
);
2203 *this_cache
= cache
;
2207 static enum unwind_stop_reason
2208 i386_sigtramp_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2211 struct i386_frame_cache
*cache
=
2212 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2215 return UNWIND_UNAVAILABLE
;
2217 return UNWIND_NO_REASON
;
2221 i386_sigtramp_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2222 struct frame_id
*this_id
)
2224 struct i386_frame_cache
*cache
=
2225 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2230 /* See the end of i386_push_dummy_call. */
2231 (*this_id
) = frame_id_build (cache
->base
+ 8, get_frame_pc (this_frame
));
2234 static struct value
*
2235 i386_sigtramp_frame_prev_register (struct frame_info
*this_frame
,
2236 void **this_cache
, int regnum
)
2238 /* Make sure we've initialized the cache. */
2239 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2241 return i386_frame_prev_register (this_frame
, this_cache
, regnum
);
2245 i386_sigtramp_frame_sniffer (const struct frame_unwind
*self
,
2246 struct frame_info
*this_frame
,
2247 void **this_prologue_cache
)
2249 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (this_frame
));
2251 /* We shouldn't even bother if we don't have a sigcontext_addr
2253 if (tdep
->sigcontext_addr
== NULL
)
2256 if (tdep
->sigtramp_p
!= NULL
)
2258 if (tdep
->sigtramp_p (this_frame
))
2262 if (tdep
->sigtramp_start
!= 0)
2264 CORE_ADDR pc
= get_frame_pc (this_frame
);
2266 gdb_assert (tdep
->sigtramp_end
!= 0);
2267 if (pc
>= tdep
->sigtramp_start
&& pc
< tdep
->sigtramp_end
)
2274 static const struct frame_unwind i386_sigtramp_frame_unwind
=
2277 i386_sigtramp_frame_unwind_stop_reason
,
2278 i386_sigtramp_frame_this_id
,
2279 i386_sigtramp_frame_prev_register
,
2281 i386_sigtramp_frame_sniffer
2286 i386_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
2288 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
2293 static const struct frame_base i386_frame_base
=
2296 i386_frame_base_address
,
2297 i386_frame_base_address
,
2298 i386_frame_base_address
2301 static struct frame_id
2302 i386_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
2306 fp
= get_frame_register_unsigned (this_frame
, I386_EBP_REGNUM
);
2308 /* See the end of i386_push_dummy_call. */
2309 return frame_id_build (fp
+ 8, get_frame_pc (this_frame
));
2312 /* _Decimal128 function return values need 16-byte alignment on the
2316 i386_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
2318 return sp
& -(CORE_ADDR
)16;
2322 /* Figure out where the longjmp will land. Slurp the args out of the
2323 stack. We expect the first arg to be a pointer to the jmp_buf
2324 structure from which we extract the address that we will land at.
2325 This address is copied into PC. This routine returns non-zero on
2329 i386_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
2332 CORE_ADDR sp
, jb_addr
;
2333 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2334 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2335 int jb_pc_offset
= gdbarch_tdep (gdbarch
)->jb_pc_offset
;
2337 /* If JB_PC_OFFSET is -1, we have no way to find out where the
2338 longjmp will land. */
2339 if (jb_pc_offset
== -1)
2342 get_frame_register (frame
, I386_ESP_REGNUM
, buf
);
2343 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
2344 if (target_read_memory (sp
+ 4, buf
, 4))
2347 jb_addr
= extract_unsigned_integer (buf
, 4, byte_order
);
2348 if (target_read_memory (jb_addr
+ jb_pc_offset
, buf
, 4))
2351 *pc
= extract_unsigned_integer (buf
, 4, byte_order
);
2356 /* Check whether TYPE must be 16-byte-aligned when passed as a
2357 function argument. 16-byte vectors, _Decimal128 and structures or
2358 unions containing such types must be 16-byte-aligned; other
2359 arguments are 4-byte-aligned. */
2362 i386_16_byte_align_p (struct type
*type
)
2364 type
= check_typedef (type
);
2365 if ((TYPE_CODE (type
) == TYPE_CODE_DECFLOAT
2366 || (TYPE_CODE (type
) == TYPE_CODE_ARRAY
&& TYPE_VECTOR (type
)))
2367 && TYPE_LENGTH (type
) == 16)
2369 if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
2370 return i386_16_byte_align_p (TYPE_TARGET_TYPE (type
));
2371 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
2372 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
2375 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
2377 if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type
, i
)))
2384 /* Implementation for set_gdbarch_push_dummy_code. */
2387 i386_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
, CORE_ADDR funaddr
,
2388 struct value
**args
, int nargs
, struct type
*value_type
,
2389 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
,
2390 struct regcache
*regcache
)
2392 /* Use 0xcc breakpoint - 1 byte. */
2396 /* Keep the stack aligned. */
2401 i386_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2402 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
2403 struct value
**args
, CORE_ADDR sp
, int struct_return
,
2404 CORE_ADDR struct_addr
)
2406 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2412 /* Determine the total space required for arguments and struct
2413 return address in a first pass (allowing for 16-byte-aligned
2414 arguments), then push arguments in a second pass. */
2416 for (write_pass
= 0; write_pass
< 2; write_pass
++)
2418 int args_space_used
= 0;
2424 /* Push value address. */
2425 store_unsigned_integer (buf
, 4, byte_order
, struct_addr
);
2426 write_memory (sp
, buf
, 4);
2427 args_space_used
+= 4;
2433 for (i
= 0; i
< nargs
; i
++)
2435 int len
= TYPE_LENGTH (value_enclosing_type (args
[i
]));
2439 if (i386_16_byte_align_p (value_enclosing_type (args
[i
])))
2440 args_space_used
= align_up (args_space_used
, 16);
2442 write_memory (sp
+ args_space_used
,
2443 value_contents_all (args
[i
]), len
);
2444 /* The System V ABI says that:
2446 "An argument's size is increased, if necessary, to make it a
2447 multiple of [32-bit] words. This may require tail padding,
2448 depending on the size of the argument."
2450 This makes sure the stack stays word-aligned. */
2451 args_space_used
+= align_up (len
, 4);
2455 if (i386_16_byte_align_p (value_enclosing_type (args
[i
])))
2456 args_space
= align_up (args_space
, 16);
2457 args_space
+= align_up (len
, 4);
2465 /* The original System V ABI only requires word alignment,
2466 but modern incarnations need 16-byte alignment in order
2467 to support SSE. Since wasting a few bytes here isn't
2468 harmful we unconditionally enforce 16-byte alignment. */
2473 /* Store return address. */
2475 store_unsigned_integer (buf
, 4, byte_order
, bp_addr
);
2476 write_memory (sp
, buf
, 4);
2478 /* Finally, update the stack pointer... */
2479 store_unsigned_integer (buf
, 4, byte_order
, sp
);
2480 regcache_cooked_write (regcache
, I386_ESP_REGNUM
, buf
);
2482 /* ...and fake a frame pointer. */
2483 regcache_cooked_write (regcache
, I386_EBP_REGNUM
, buf
);
2485 /* MarkK wrote: This "+ 8" is all over the place:
2486 (i386_frame_this_id, i386_sigtramp_frame_this_id,
2487 i386_dummy_id). It's there, since all frame unwinders for
2488 a given target have to agree (within a certain margin) on the
2489 definition of the stack address of a frame. Otherwise frame id
2490 comparison might not work correctly. Since DWARF2/GCC uses the
2491 stack address *before* the function call as a frame's CFA. On
2492 the i386, when %ebp is used as a frame pointer, the offset
2493 between the contents %ebp and the CFA as defined by GCC. */
2497 /* These registers are used for returning integers (and on some
2498 targets also for returning `struct' and `union' values when their
2499 size and alignment match an integer type). */
2500 #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */
2501 #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */
2503 /* Read, for architecture GDBARCH, a function return value of TYPE
2504 from REGCACHE, and copy that into VALBUF. */
2507 i386_extract_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
2508 struct regcache
*regcache
, gdb_byte
*valbuf
)
2510 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2511 int len
= TYPE_LENGTH (type
);
2512 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
2514 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2516 if (tdep
->st0_regnum
< 0)
2518 warning (_("Cannot find floating-point return value."));
2519 memset (valbuf
, 0, len
);
2523 /* Floating-point return values can be found in %st(0). Convert
2524 its contents to the desired type. This is probably not
2525 exactly how it would happen on the target itself, but it is
2526 the best we can do. */
2527 regcache_raw_read (regcache
, I386_ST0_REGNUM
, buf
);
2528 convert_typed_floating (buf
, i387_ext_type (gdbarch
), valbuf
, type
);
2532 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
2533 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
2535 if (len
<= low_size
)
2537 regcache_raw_read (regcache
, LOW_RETURN_REGNUM
, buf
);
2538 memcpy (valbuf
, buf
, len
);
2540 else if (len
<= (low_size
+ high_size
))
2542 regcache_raw_read (regcache
, LOW_RETURN_REGNUM
, buf
);
2543 memcpy (valbuf
, buf
, low_size
);
2544 regcache_raw_read (regcache
, HIGH_RETURN_REGNUM
, buf
);
2545 memcpy (valbuf
+ low_size
, buf
, len
- low_size
);
2548 internal_error (__FILE__
, __LINE__
,
2549 _("Cannot extract return value of %d bytes long."),
2554 /* Write, for architecture GDBARCH, a function return value of TYPE
2555 from VALBUF into REGCACHE. */
2558 i386_store_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
2559 struct regcache
*regcache
, const gdb_byte
*valbuf
)
2561 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2562 int len
= TYPE_LENGTH (type
);
2564 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2567 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
2569 if (tdep
->st0_regnum
< 0)
2571 warning (_("Cannot set floating-point return value."));
2575 /* Returning floating-point values is a bit tricky. Apart from
2576 storing the return value in %st(0), we have to simulate the
2577 state of the FPU at function return point. */
2579 /* Convert the value found in VALBUF to the extended
2580 floating-point format used by the FPU. This is probably
2581 not exactly how it would happen on the target itself, but
2582 it is the best we can do. */
2583 convert_typed_floating (valbuf
, type
, buf
, i387_ext_type (gdbarch
));
2584 regcache_raw_write (regcache
, I386_ST0_REGNUM
, buf
);
2586 /* Set the top of the floating-point register stack to 7. The
2587 actual value doesn't really matter, but 7 is what a normal
2588 function return would end up with if the program started out
2589 with a freshly initialized FPU. */
2590 regcache_raw_read_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), &fstat
);
2592 regcache_raw_write_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), fstat
);
2594 /* Mark %st(1) through %st(7) as empty. Since we set the top of
2595 the floating-point register stack to 7, the appropriate value
2596 for the tag word is 0x3fff. */
2597 regcache_raw_write_unsigned (regcache
, I387_FTAG_REGNUM (tdep
), 0x3fff);
2601 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
2602 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
2604 if (len
<= low_size
)
2605 regcache_raw_write_part (regcache
, LOW_RETURN_REGNUM
, 0, len
, valbuf
);
2606 else if (len
<= (low_size
+ high_size
))
2608 regcache_raw_write (regcache
, LOW_RETURN_REGNUM
, valbuf
);
2609 regcache_raw_write_part (regcache
, HIGH_RETURN_REGNUM
, 0,
2610 len
- low_size
, valbuf
+ low_size
);
2613 internal_error (__FILE__
, __LINE__
,
2614 _("Cannot store return value of %d bytes long."), len
);
2619 /* This is the variable that is set with "set struct-convention", and
2620 its legitimate values. */
2621 static const char default_struct_convention
[] = "default";
2622 static const char pcc_struct_convention
[] = "pcc";
2623 static const char reg_struct_convention
[] = "reg";
2624 static const char *const valid_conventions
[] =
2626 default_struct_convention
,
2627 pcc_struct_convention
,
2628 reg_struct_convention
,
2631 static const char *struct_convention
= default_struct_convention
;
2633 /* Return non-zero if TYPE, which is assumed to be a structure,
2634 a union type, or an array type, should be returned in registers
2635 for architecture GDBARCH. */
2638 i386_reg_struct_return_p (struct gdbarch
*gdbarch
, struct type
*type
)
2640 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2641 enum type_code code
= TYPE_CODE (type
);
2642 int len
= TYPE_LENGTH (type
);
2644 gdb_assert (code
== TYPE_CODE_STRUCT
2645 || code
== TYPE_CODE_UNION
2646 || code
== TYPE_CODE_ARRAY
);
2648 if (struct_convention
== pcc_struct_convention
2649 || (struct_convention
== default_struct_convention
2650 && tdep
->struct_return
== pcc_struct_return
))
2653 /* Structures consisting of a single `float', `double' or 'long
2654 double' member are returned in %st(0). */
2655 if (code
== TYPE_CODE_STRUCT
&& TYPE_NFIELDS (type
) == 1)
2657 type
= check_typedef (TYPE_FIELD_TYPE (type
, 0));
2658 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2659 return (len
== 4 || len
== 8 || len
== 12);
2662 return (len
== 1 || len
== 2 || len
== 4 || len
== 8);
2665 /* Determine, for architecture GDBARCH, how a return value of TYPE
2666 should be returned. If it is supposed to be returned in registers,
2667 and READBUF is non-zero, read the appropriate value from REGCACHE,
2668 and copy it into READBUF. If WRITEBUF is non-zero, write the value
2669 from WRITEBUF into REGCACHE. */
2671 static enum return_value_convention
2672 i386_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
2673 struct type
*type
, struct regcache
*regcache
,
2674 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2676 enum type_code code
= TYPE_CODE (type
);
2678 if (((code
== TYPE_CODE_STRUCT
2679 || code
== TYPE_CODE_UNION
2680 || code
== TYPE_CODE_ARRAY
)
2681 && !i386_reg_struct_return_p (gdbarch
, type
))
2682 /* Complex double and long double uses the struct return covention. */
2683 || (code
== TYPE_CODE_COMPLEX
&& TYPE_LENGTH (type
) == 16)
2684 || (code
== TYPE_CODE_COMPLEX
&& TYPE_LENGTH (type
) == 24)
2685 /* 128-bit decimal float uses the struct return convention. */
2686 || (code
== TYPE_CODE_DECFLOAT
&& TYPE_LENGTH (type
) == 16))
2688 /* The System V ABI says that:
2690 "A function that returns a structure or union also sets %eax
2691 to the value of the original address of the caller's area
2692 before it returns. Thus when the caller receives control
2693 again, the address of the returned object resides in register
2694 %eax and can be used to access the object."
2696 So the ABI guarantees that we can always find the return
2697 value just after the function has returned. */
2699 /* Note that the ABI doesn't mention functions returning arrays,
2700 which is something possible in certain languages such as Ada.
2701 In this case, the value is returned as if it was wrapped in
2702 a record, so the convention applied to records also applies
2709 regcache_raw_read_unsigned (regcache
, I386_EAX_REGNUM
, &addr
);
2710 read_memory (addr
, readbuf
, TYPE_LENGTH (type
));
2713 return RETURN_VALUE_ABI_RETURNS_ADDRESS
;
2716 /* This special case is for structures consisting of a single
2717 `float', `double' or 'long double' member. These structures are
2718 returned in %st(0). For these structures, we call ourselves
2719 recursively, changing TYPE into the type of the first member of
2720 the structure. Since that should work for all structures that
2721 have only one member, we don't bother to check the member's type
2723 if (code
== TYPE_CODE_STRUCT
&& TYPE_NFIELDS (type
) == 1)
2725 type
= check_typedef (TYPE_FIELD_TYPE (type
, 0));
2726 return i386_return_value (gdbarch
, function
, type
, regcache
,
2731 i386_extract_return_value (gdbarch
, type
, regcache
, readbuf
);
2733 i386_store_return_value (gdbarch
, type
, regcache
, writebuf
);
2735 return RETURN_VALUE_REGISTER_CONVENTION
;
2740 i387_ext_type (struct gdbarch
*gdbarch
)
2742 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2744 if (!tdep
->i387_ext_type
)
2746 tdep
->i387_ext_type
= tdesc_find_type (gdbarch
, "i387_ext");
2747 gdb_assert (tdep
->i387_ext_type
!= NULL
);
2750 return tdep
->i387_ext_type
;
2753 /* Construct vector type for pseudo YMM registers. We can't use
2754 tdesc_find_type since YMM isn't described in target description. */
2756 static struct type
*
2757 i386_ymm_type (struct gdbarch
*gdbarch
)
2759 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2761 if (!tdep
->i386_ymm_type
)
2763 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2765 /* The type we're building is this: */
2767 union __gdb_builtin_type_vec256i
2769 int128_t uint128
[2];
2770 int64_t v2_int64
[4];
2771 int32_t v4_int32
[8];
2772 int16_t v8_int16
[16];
2773 int8_t v16_int8
[32];
2774 double v2_double
[4];
2781 t
= arch_composite_type (gdbarch
,
2782 "__gdb_builtin_type_vec256i", TYPE_CODE_UNION
);
2783 append_composite_type_field (t
, "v8_float",
2784 init_vector_type (bt
->builtin_float
, 8));
2785 append_composite_type_field (t
, "v4_double",
2786 init_vector_type (bt
->builtin_double
, 4));
2787 append_composite_type_field (t
, "v32_int8",
2788 init_vector_type (bt
->builtin_int8
, 32));
2789 append_composite_type_field (t
, "v16_int16",
2790 init_vector_type (bt
->builtin_int16
, 16));
2791 append_composite_type_field (t
, "v8_int32",
2792 init_vector_type (bt
->builtin_int32
, 8));
2793 append_composite_type_field (t
, "v4_int64",
2794 init_vector_type (bt
->builtin_int64
, 4));
2795 append_composite_type_field (t
, "v2_int128",
2796 init_vector_type (bt
->builtin_int128
, 2));
2798 TYPE_VECTOR (t
) = 1;
2799 TYPE_NAME (t
) = "builtin_type_vec256i";
2800 tdep
->i386_ymm_type
= t
;
2803 return tdep
->i386_ymm_type
;
2806 /* Construct vector type for MMX registers. */
2807 static struct type
*
2808 i386_mmx_type (struct gdbarch
*gdbarch
)
2810 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2812 if (!tdep
->i386_mmx_type
)
2814 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2816 /* The type we're building is this: */
2818 union __gdb_builtin_type_vec64i
2821 int32_t v2_int32
[2];
2822 int16_t v4_int16
[4];
2829 t
= arch_composite_type (gdbarch
,
2830 "__gdb_builtin_type_vec64i", TYPE_CODE_UNION
);
2832 append_composite_type_field (t
, "uint64", bt
->builtin_int64
);
2833 append_composite_type_field (t
, "v2_int32",
2834 init_vector_type (bt
->builtin_int32
, 2));
2835 append_composite_type_field (t
, "v4_int16",
2836 init_vector_type (bt
->builtin_int16
, 4));
2837 append_composite_type_field (t
, "v8_int8",
2838 init_vector_type (bt
->builtin_int8
, 8));
2840 TYPE_VECTOR (t
) = 1;
2841 TYPE_NAME (t
) = "builtin_type_vec64i";
2842 tdep
->i386_mmx_type
= t
;
2845 return tdep
->i386_mmx_type
;
2848 /* Return the GDB type object for the "standard" data type of data in
2852 i386_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
2854 if (i386_mmx_regnum_p (gdbarch
, regnum
))
2855 return i386_mmx_type (gdbarch
);
2856 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
2857 return i386_ymm_type (gdbarch
);
2860 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2861 if (i386_byte_regnum_p (gdbarch
, regnum
))
2862 return bt
->builtin_int8
;
2863 else if (i386_word_regnum_p (gdbarch
, regnum
))
2864 return bt
->builtin_int16
;
2865 else if (i386_dword_regnum_p (gdbarch
, regnum
))
2866 return bt
->builtin_int32
;
2869 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
2872 /* Map a cooked register onto a raw register or memory. For the i386,
2873 the MMX registers need to be mapped onto floating point registers. */
2876 i386_mmx_regnum_to_fp_regnum (struct regcache
*regcache
, int regnum
)
2878 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_regcache_arch (regcache
));
2883 mmxreg
= regnum
- tdep
->mm0_regnum
;
2884 regcache_raw_read_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), &fstat
);
2885 tos
= (fstat
>> 11) & 0x7;
2886 fpreg
= (mmxreg
+ tos
) % 8;
2888 return (I387_ST0_REGNUM (tdep
) + fpreg
);
2891 /* A helper function for us by i386_pseudo_register_read_value and
2892 amd64_pseudo_register_read_value. It does all the work but reads
2893 the data into an already-allocated value. */
2896 i386_pseudo_register_read_into_value (struct gdbarch
*gdbarch
,
2897 struct regcache
*regcache
,
2899 struct value
*result_value
)
2901 gdb_byte raw_buf
[MAX_REGISTER_SIZE
];
2902 enum register_status status
;
2903 gdb_byte
*buf
= value_contents_raw (result_value
);
2905 if (i386_mmx_regnum_p (gdbarch
, regnum
))
2907 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
2909 /* Extract (always little endian). */
2910 status
= regcache_raw_read (regcache
, fpnum
, raw_buf
);
2911 if (status
!= REG_VALID
)
2912 mark_value_bytes_unavailable (result_value
, 0,
2913 TYPE_LENGTH (value_type (result_value
)));
2915 memcpy (buf
, raw_buf
, register_size (gdbarch
, regnum
));
2919 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2921 if (i386_ymm_regnum_p (gdbarch
, regnum
))
2923 regnum
-= tdep
->ymm0_regnum
;
2925 /* Extract (always little endian). Read lower 128bits. */
2926 status
= regcache_raw_read (regcache
,
2927 I387_XMM0_REGNUM (tdep
) + regnum
,
2929 if (status
!= REG_VALID
)
2930 mark_value_bytes_unavailable (result_value
, 0, 16);
2932 memcpy (buf
, raw_buf
, 16);
2933 /* Read upper 128bits. */
2934 status
= regcache_raw_read (regcache
,
2935 tdep
->ymm0h_regnum
+ regnum
,
2937 if (status
!= REG_VALID
)
2938 mark_value_bytes_unavailable (result_value
, 16, 32);
2940 memcpy (buf
+ 16, raw_buf
, 16);
2942 else if (i386_word_regnum_p (gdbarch
, regnum
))
2944 int gpnum
= regnum
- tdep
->ax_regnum
;
2946 /* Extract (always little endian). */
2947 status
= regcache_raw_read (regcache
, gpnum
, raw_buf
);
2948 if (status
!= REG_VALID
)
2949 mark_value_bytes_unavailable (result_value
, 0,
2950 TYPE_LENGTH (value_type (result_value
)));
2952 memcpy (buf
, raw_buf
, 2);
2954 else if (i386_byte_regnum_p (gdbarch
, regnum
))
2956 /* Check byte pseudo registers last since this function will
2957 be called from amd64_pseudo_register_read, which handles
2958 byte pseudo registers differently. */
2959 int gpnum
= regnum
- tdep
->al_regnum
;
2961 /* Extract (always little endian). We read both lower and
2963 status
= regcache_raw_read (regcache
, gpnum
% 4, raw_buf
);
2964 if (status
!= REG_VALID
)
2965 mark_value_bytes_unavailable (result_value
, 0,
2966 TYPE_LENGTH (value_type (result_value
)));
2967 else if (gpnum
>= 4)
2968 memcpy (buf
, raw_buf
+ 1, 1);
2970 memcpy (buf
, raw_buf
, 1);
2973 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
2977 static struct value
*
2978 i386_pseudo_register_read_value (struct gdbarch
*gdbarch
,
2979 struct regcache
*regcache
,
2982 struct value
*result
;
2984 result
= allocate_value (register_type (gdbarch
, regnum
));
2985 VALUE_LVAL (result
) = lval_register
;
2986 VALUE_REGNUM (result
) = regnum
;
2988 i386_pseudo_register_read_into_value (gdbarch
, regcache
, regnum
, result
);
2994 i386_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2995 int regnum
, const gdb_byte
*buf
)
2997 gdb_byte raw_buf
[MAX_REGISTER_SIZE
];
2999 if (i386_mmx_regnum_p (gdbarch
, regnum
))
3001 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
3004 regcache_raw_read (regcache
, fpnum
, raw_buf
);
3005 /* ... Modify ... (always little endian). */
3006 memcpy (raw_buf
, buf
, register_size (gdbarch
, regnum
));
3008 regcache_raw_write (regcache
, fpnum
, raw_buf
);
3012 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3014 if (i386_ymm_regnum_p (gdbarch
, regnum
))
3016 regnum
-= tdep
->ymm0_regnum
;
3018 /* ... Write lower 128bits. */
3019 regcache_raw_write (regcache
,
3020 I387_XMM0_REGNUM (tdep
) + regnum
,
3022 /* ... Write upper 128bits. */
3023 regcache_raw_write (regcache
,
3024 tdep
->ymm0h_regnum
+ regnum
,
3027 else if (i386_word_regnum_p (gdbarch
, regnum
))
3029 int gpnum
= regnum
- tdep
->ax_regnum
;
3032 regcache_raw_read (regcache
, gpnum
, raw_buf
);
3033 /* ... Modify ... (always little endian). */
3034 memcpy (raw_buf
, buf
, 2);
3036 regcache_raw_write (regcache
, gpnum
, raw_buf
);
3038 else if (i386_byte_regnum_p (gdbarch
, regnum
))
3040 /* Check byte pseudo registers last since this function will
3041 be called from amd64_pseudo_register_read, which handles
3042 byte pseudo registers differently. */
3043 int gpnum
= regnum
- tdep
->al_regnum
;
3045 /* Read ... We read both lower and upper registers. */
3046 regcache_raw_read (regcache
, gpnum
% 4, raw_buf
);
3047 /* ... Modify ... (always little endian). */
3049 memcpy (raw_buf
+ 1, buf
, 1);
3051 memcpy (raw_buf
, buf
, 1);
3053 regcache_raw_write (regcache
, gpnum
% 4, raw_buf
);
3056 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
3061 /* Return the register number of the register allocated by GCC after
3062 REGNUM, or -1 if there is no such register. */
3065 i386_next_regnum (int regnum
)
3067 /* GCC allocates the registers in the order:
3069 %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ...
3071 Since storing a variable in %esp doesn't make any sense we return
3072 -1 for %ebp and for %esp itself. */
3073 static int next_regnum
[] =
3075 I386_EDX_REGNUM
, /* Slot for %eax. */
3076 I386_EBX_REGNUM
, /* Slot for %ecx. */
3077 I386_ECX_REGNUM
, /* Slot for %edx. */
3078 I386_ESI_REGNUM
, /* Slot for %ebx. */
3079 -1, -1, /* Slots for %esp and %ebp. */
3080 I386_EDI_REGNUM
, /* Slot for %esi. */
3081 I386_EBP_REGNUM
/* Slot for %edi. */
3084 if (regnum
>= 0 && regnum
< sizeof (next_regnum
) / sizeof (next_regnum
[0]))
3085 return next_regnum
[regnum
];
3090 /* Return nonzero if a value of type TYPE stored in register REGNUM
3091 needs any special handling. */
3094 i386_convert_register_p (struct gdbarch
*gdbarch
,
3095 int regnum
, struct type
*type
)
3097 int len
= TYPE_LENGTH (type
);
3099 /* Values may be spread across multiple registers. Most debugging
3100 formats aren't expressive enough to specify the locations, so
3101 some heuristics is involved. Right now we only handle types that
3102 have a length that is a multiple of the word size, since GCC
3103 doesn't seem to put any other types into registers. */
3104 if (len
> 4 && len
% 4 == 0)
3106 int last_regnum
= regnum
;
3110 last_regnum
= i386_next_regnum (last_regnum
);
3114 if (last_regnum
!= -1)
3118 return i387_convert_register_p (gdbarch
, regnum
, type
);
3121 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
3122 return its contents in TO. */
3125 i386_register_to_value (struct frame_info
*frame
, int regnum
,
3126 struct type
*type
, gdb_byte
*to
,
3127 int *optimizedp
, int *unavailablep
)
3129 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3130 int len
= TYPE_LENGTH (type
);
3132 if (i386_fp_regnum_p (gdbarch
, regnum
))
3133 return i387_register_to_value (frame
, regnum
, type
, to
,
3134 optimizedp
, unavailablep
);
3136 /* Read a value spread across multiple registers. */
3138 gdb_assert (len
> 4 && len
% 4 == 0);
3142 gdb_assert (regnum
!= -1);
3143 gdb_assert (register_size (gdbarch
, regnum
) == 4);
3145 if (!get_frame_register_bytes (frame
, regnum
, 0,
3146 register_size (gdbarch
, regnum
),
3147 to
, optimizedp
, unavailablep
))
3150 regnum
= i386_next_regnum (regnum
);
3155 *optimizedp
= *unavailablep
= 0;
3159 /* Write the contents FROM of a value of type TYPE into register
3160 REGNUM in frame FRAME. */
3163 i386_value_to_register (struct frame_info
*frame
, int regnum
,
3164 struct type
*type
, const gdb_byte
*from
)
3166 int len
= TYPE_LENGTH (type
);
3168 if (i386_fp_regnum_p (get_frame_arch (frame
), regnum
))
3170 i387_value_to_register (frame
, regnum
, type
, from
);
3174 /* Write a value spread across multiple registers. */
3176 gdb_assert (len
> 4 && len
% 4 == 0);
3180 gdb_assert (regnum
!= -1);
3181 gdb_assert (register_size (get_frame_arch (frame
), regnum
) == 4);
3183 put_frame_register (frame
, regnum
, from
);
3184 regnum
= i386_next_regnum (regnum
);
3190 /* Supply register REGNUM from the buffer specified by GREGS and LEN
3191 in the general-purpose register set REGSET to register cache
3192 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3195 i386_supply_gregset (const struct regset
*regset
, struct regcache
*regcache
,
3196 int regnum
, const void *gregs
, size_t len
)
3198 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
3199 const gdb_byte
*regs
= gregs
;
3202 gdb_assert (len
== tdep
->sizeof_gregset
);
3204 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
3206 if ((regnum
== i
|| regnum
== -1)
3207 && tdep
->gregset_reg_offset
[i
] != -1)
3208 regcache_raw_supply (regcache
, i
, regs
+ tdep
->gregset_reg_offset
[i
]);
3212 /* Collect register REGNUM from the register cache REGCACHE and store
3213 it in the buffer specified by GREGS and LEN as described by the
3214 general-purpose register set REGSET. If REGNUM is -1, do this for
3215 all registers in REGSET. */
3218 i386_collect_gregset (const struct regset
*regset
,
3219 const struct regcache
*regcache
,
3220 int regnum
, void *gregs
, size_t len
)
3222 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
3223 gdb_byte
*regs
= gregs
;
3226 gdb_assert (len
== tdep
->sizeof_gregset
);
3228 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
3230 if ((regnum
== i
|| regnum
== -1)
3231 && tdep
->gregset_reg_offset
[i
] != -1)
3232 regcache_raw_collect (regcache
, i
, regs
+ tdep
->gregset_reg_offset
[i
]);
3236 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
3237 in the floating-point register set REGSET to register cache
3238 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3241 i386_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
3242 int regnum
, const void *fpregs
, size_t len
)
3244 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
3246 if (len
== I387_SIZEOF_FXSAVE
)
3248 i387_supply_fxsave (regcache
, regnum
, fpregs
);
3252 gdb_assert (len
== tdep
->sizeof_fpregset
);
3253 i387_supply_fsave (regcache
, regnum
, fpregs
);
3256 /* Collect register REGNUM from the register cache REGCACHE and store
3257 it in the buffer specified by FPREGS and LEN as described by the
3258 floating-point register set REGSET. If REGNUM is -1, do this for
3259 all registers in REGSET. */
3262 i386_collect_fpregset (const struct regset
*regset
,
3263 const struct regcache
*regcache
,
3264 int regnum
, void *fpregs
, size_t len
)
3266 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
3268 if (len
== I387_SIZEOF_FXSAVE
)
3270 i387_collect_fxsave (regcache
, regnum
, fpregs
);
3274 gdb_assert (len
== tdep
->sizeof_fpregset
);
3275 i387_collect_fsave (regcache
, regnum
, fpregs
);
3278 /* Similar to i386_supply_fpregset, but use XSAVE extended state. */
3281 i386_supply_xstateregset (const struct regset
*regset
,
3282 struct regcache
*regcache
, int regnum
,
3283 const void *xstateregs
, size_t len
)
3285 i387_supply_xsave (regcache
, regnum
, xstateregs
);
3288 /* Similar to i386_collect_fpregset , but use XSAVE extended state. */
3291 i386_collect_xstateregset (const struct regset
*regset
,
3292 const struct regcache
*regcache
,
3293 int regnum
, void *xstateregs
, size_t len
)
3295 i387_collect_xsave (regcache
, regnum
, xstateregs
, 1);
3298 /* Return the appropriate register set for the core section identified
3299 by SECT_NAME and SECT_SIZE. */
3301 const struct regset
*
3302 i386_regset_from_core_section (struct gdbarch
*gdbarch
,
3303 const char *sect_name
, size_t sect_size
)
3305 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3307 if (strcmp (sect_name
, ".reg") == 0 && sect_size
== tdep
->sizeof_gregset
)
3309 if (tdep
->gregset
== NULL
)
3310 tdep
->gregset
= regset_alloc (gdbarch
, i386_supply_gregset
,
3311 i386_collect_gregset
);
3312 return tdep
->gregset
;
3315 if ((strcmp (sect_name
, ".reg2") == 0 && sect_size
== tdep
->sizeof_fpregset
)
3316 || (strcmp (sect_name
, ".reg-xfp") == 0
3317 && sect_size
== I387_SIZEOF_FXSAVE
))
3319 if (tdep
->fpregset
== NULL
)
3320 tdep
->fpregset
= regset_alloc (gdbarch
, i386_supply_fpregset
,
3321 i386_collect_fpregset
);
3322 return tdep
->fpregset
;
3325 if (strcmp (sect_name
, ".reg-xstate") == 0)
3327 if (tdep
->xstateregset
== NULL
)
3328 tdep
->xstateregset
= regset_alloc (gdbarch
,
3329 i386_supply_xstateregset
,
3330 i386_collect_xstateregset
);
3332 return tdep
->xstateregset
;
3339 /* Stuff for WIN32 PE style DLL's but is pretty generic really. */
3342 i386_pe_skip_trampoline_code (struct frame_info
*frame
,
3343 CORE_ADDR pc
, char *name
)
3345 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3346 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3349 if (pc
&& read_memory_unsigned_integer (pc
, 2, byte_order
) == 0x25ff)
3351 unsigned long indirect
=
3352 read_memory_unsigned_integer (pc
+ 2, 4, byte_order
);
3353 struct minimal_symbol
*indsym
=
3354 indirect
? lookup_minimal_symbol_by_pc (indirect
) : 0;
3355 const char *symname
= indsym
? SYMBOL_LINKAGE_NAME (indsym
) : 0;
3359 if (strncmp (symname
, "__imp_", 6) == 0
3360 || strncmp (symname
, "_imp_", 5) == 0)
3362 read_memory_unsigned_integer (indirect
, 4, byte_order
);
3365 return 0; /* Not a trampoline. */
3369 /* Return whether the THIS_FRAME corresponds to a sigtramp
3373 i386_sigtramp_p (struct frame_info
*this_frame
)
3375 CORE_ADDR pc
= get_frame_pc (this_frame
);
3378 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
3379 return (name
&& strcmp ("_sigtramp", name
) == 0);
3383 /* We have two flavours of disassembly. The machinery on this page
3384 deals with switching between those. */
3387 i386_print_insn (bfd_vma pc
, struct disassemble_info
*info
)
3389 gdb_assert (disassembly_flavor
== att_flavor
3390 || disassembly_flavor
== intel_flavor
);
3392 /* FIXME: kettenis/20020915: Until disassembler_options is properly
3393 constified, cast to prevent a compiler warning. */
3394 info
->disassembler_options
= (char *) disassembly_flavor
;
3396 return print_insn_i386 (pc
, info
);
3400 /* There are a few i386 architecture variants that differ only
3401 slightly from the generic i386 target. For now, we don't give them
3402 their own source file, but include them here. As a consequence,
3403 they'll always be included. */
3405 /* System V Release 4 (SVR4). */
3407 /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp
3411 i386_svr4_sigtramp_p (struct frame_info
*this_frame
)
3413 CORE_ADDR pc
= get_frame_pc (this_frame
);
3416 /* UnixWare uses _sigacthandler. The origin of the other symbols is
3417 currently unknown. */
3418 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
3419 return (name
&& (strcmp ("_sigreturn", name
) == 0
3420 || strcmp ("_sigacthandler", name
) == 0
3421 || strcmp ("sigvechandler", name
) == 0));
3424 /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the
3425 address of the associated sigcontext (ucontext) structure. */
3428 i386_svr4_sigcontext_addr (struct frame_info
*this_frame
)
3430 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3431 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3435 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
3436 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
3438 return read_memory_unsigned_integer (sp
+ 8, 4, byte_order
);
3443 /* Implementation of `gdbarch_stap_is_single_operand', as defined in
3447 i386_stap_is_single_operand (struct gdbarch
*gdbarch
, const char *s
)
3449 return (*s
== '$' /* Literal number. */
3450 || (isdigit (*s
) && s
[1] == '(' && s
[2] == '%') /* Displacement. */
3451 || (*s
== '(' && s
[1] == '%') /* Register indirection. */
3452 || (*s
== '%' && isalpha (s
[1]))); /* Register access. */
3455 /* Implementation of `gdbarch_stap_parse_special_token', as defined in
3459 i386_stap_parse_special_token (struct gdbarch
*gdbarch
,
3460 struct stap_parse_info
*p
)
3462 /* In order to parse special tokens, we use a state-machine that go
3463 through every known token and try to get a match. */
3467 THREE_ARG_DISPLACEMENT
,
3471 current_state
= TRIPLET
;
3473 /* The special tokens to be parsed here are:
3475 - `register base + (register index * size) + offset', as represented
3476 in `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'.
3478 - Operands of the form `-8+3+1(%rbp)', which must be interpreted as
3479 `*(-8 + 3 - 1 + (void *) $eax)'. */
3481 while (current_state
!= DONE
)
3483 const char *s
= p
->arg
;
3485 switch (current_state
)
3489 if (isdigit (*s
) || *s
== '-' || *s
== '+')
3493 long displacements
[3];
3508 displacements
[0] = strtol (s
, (char **) &s
, 10);
3510 if (*s
!= '+' && *s
!= '-')
3512 /* We are not dealing with a triplet. */
3525 displacements
[1] = strtol (s
, (char **) &s
, 10);
3527 if (*s
!= '+' && *s
!= '-')
3529 /* We are not dealing with a triplet. */
3542 displacements
[2] = strtol (s
, (char **) &s
, 10);
3544 if (*s
!= '(' || s
[1] != '%')
3550 while (isalnum (*s
))
3557 regname
= alloca (len
+ 1);
3559 strncpy (regname
, start
, len
);
3560 regname
[len
] = '\0';
3562 if (user_reg_map_name_to_regnum (gdbarch
,
3563 regname
, len
) == -1)
3564 error (_("Invalid register name `%s' "
3565 "on expression `%s'."),
3566 regname
, p
->saved_arg
);
3568 for (i
= 0; i
< 3; i
++)
3570 write_exp_elt_opcode (OP_LONG
);
3572 (builtin_type (gdbarch
)->builtin_long
);
3573 write_exp_elt_longcst (displacements
[i
]);
3574 write_exp_elt_opcode (OP_LONG
);
3576 write_exp_elt_opcode (UNOP_NEG
);
3579 write_exp_elt_opcode (OP_REGISTER
);
3582 write_exp_string (str
);
3583 write_exp_elt_opcode (OP_REGISTER
);
3585 write_exp_elt_opcode (UNOP_CAST
);
3586 write_exp_elt_type (builtin_type (gdbarch
)->builtin_data_ptr
);
3587 write_exp_elt_opcode (UNOP_CAST
);
3589 write_exp_elt_opcode (BINOP_ADD
);
3590 write_exp_elt_opcode (BINOP_ADD
);
3591 write_exp_elt_opcode (BINOP_ADD
);
3593 write_exp_elt_opcode (UNOP_CAST
);
3594 write_exp_elt_type (lookup_pointer_type (p
->arg_type
));
3595 write_exp_elt_opcode (UNOP_CAST
);
3597 write_exp_elt_opcode (UNOP_IND
);
3605 case THREE_ARG_DISPLACEMENT
:
3607 if (isdigit (*s
) || *s
== '(' || *s
== '-' || *s
== '+')
3609 int offset_minus
= 0;
3618 struct stoken base_token
, index_token
;
3628 if (offset_minus
&& !isdigit (*s
))
3632 offset
= strtol (s
, (char **) &s
, 10);
3634 if (*s
!= '(' || s
[1] != '%')
3640 while (isalnum (*s
))
3643 if (*s
!= ',' || s
[1] != '%')
3646 len_base
= s
- start
;
3647 base
= alloca (len_base
+ 1);
3648 strncpy (base
, start
, len_base
);
3649 base
[len_base
] = '\0';
3651 if (user_reg_map_name_to_regnum (gdbarch
,
3652 base
, len_base
) == -1)
3653 error (_("Invalid register name `%s' "
3654 "on expression `%s'."),
3655 base
, p
->saved_arg
);
3660 while (isalnum (*s
))
3663 len_index
= s
- start
;
3664 index
= alloca (len_index
+ 1);
3665 strncpy (index
, start
, len_index
);
3666 index
[len_index
] = '\0';
3668 if (user_reg_map_name_to_regnum (gdbarch
,
3669 index
, len_index
) == -1)
3670 error (_("Invalid register name `%s' "
3671 "on expression `%s'."),
3672 index
, p
->saved_arg
);
3674 if (*s
!= ',' && *s
!= ')')
3688 size
= strtol (s
, (char **) &s
, 10);
3698 write_exp_elt_opcode (OP_LONG
);
3700 (builtin_type (gdbarch
)->builtin_long
);
3701 write_exp_elt_longcst (offset
);
3702 write_exp_elt_opcode (OP_LONG
);
3704 write_exp_elt_opcode (UNOP_NEG
);
3707 write_exp_elt_opcode (OP_REGISTER
);
3708 base_token
.ptr
= base
;
3709 base_token
.length
= len_base
;
3710 write_exp_string (base_token
);
3711 write_exp_elt_opcode (OP_REGISTER
);
3714 write_exp_elt_opcode (BINOP_ADD
);
3716 write_exp_elt_opcode (OP_REGISTER
);
3717 index_token
.ptr
= index
;
3718 index_token
.length
= len_index
;
3719 write_exp_string (index_token
);
3720 write_exp_elt_opcode (OP_REGISTER
);
3724 write_exp_elt_opcode (OP_LONG
);
3726 (builtin_type (gdbarch
)->builtin_long
);
3727 write_exp_elt_longcst (size
);
3728 write_exp_elt_opcode (OP_LONG
);
3730 write_exp_elt_opcode (UNOP_NEG
);
3731 write_exp_elt_opcode (BINOP_MUL
);
3734 write_exp_elt_opcode (BINOP_ADD
);
3736 write_exp_elt_opcode (UNOP_CAST
);
3737 write_exp_elt_type (lookup_pointer_type (p
->arg_type
));
3738 write_exp_elt_opcode (UNOP_CAST
);
3740 write_exp_elt_opcode (UNOP_IND
);
3750 /* Advancing to the next state. */
3762 i386_elf_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
3764 /* We typically use stabs-in-ELF with the SVR4 register numbering. */
3765 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
3767 /* Registering SystemTap handlers. */
3768 set_gdbarch_stap_integer_prefix (gdbarch
, "$");
3769 set_gdbarch_stap_register_prefix (gdbarch
, "%");
3770 set_gdbarch_stap_register_indirection_prefix (gdbarch
, "(");
3771 set_gdbarch_stap_register_indirection_suffix (gdbarch
, ")");
3772 set_gdbarch_stap_is_single_operand (gdbarch
,
3773 i386_stap_is_single_operand
);
3774 set_gdbarch_stap_parse_special_token (gdbarch
,
3775 i386_stap_parse_special_token
);
3778 /* System V Release 4 (SVR4). */
3781 i386_svr4_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
3783 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3785 /* System V Release 4 uses ELF. */
3786 i386_elf_init_abi (info
, gdbarch
);
3788 /* System V Release 4 has shared libraries. */
3789 set_gdbarch_skip_trampoline_code (gdbarch
, find_solib_trampoline_target
);
3791 tdep
->sigtramp_p
= i386_svr4_sigtramp_p
;
3792 tdep
->sigcontext_addr
= i386_svr4_sigcontext_addr
;
3793 tdep
->sc_pc_offset
= 36 + 14 * 4;
3794 tdep
->sc_sp_offset
= 36 + 17 * 4;
3796 tdep
->jb_pc_offset
= 20;
3802 i386_go32_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
3804 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3806 /* DJGPP doesn't have any special frames for signal handlers. */
3807 tdep
->sigtramp_p
= NULL
;
3809 tdep
->jb_pc_offset
= 36;
3811 /* DJGPP does not support the SSE registers. */
3812 if (! tdesc_has_registers (info
.target_desc
))
3813 tdep
->tdesc
= tdesc_i386_mmx
;
3815 /* Native compiler is GCC, which uses the SVR4 register numbering
3816 even in COFF and STABS. See the comment in i386_gdbarch_init,
3817 before the calls to set_gdbarch_stab_reg_to_regnum and
3818 set_gdbarch_sdb_reg_to_regnum. */
3819 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
3820 set_gdbarch_sdb_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
3822 set_gdbarch_has_dos_based_file_system (gdbarch
, 1);
3826 /* i386 register groups. In addition to the normal groups, add "mmx"
3829 static struct reggroup
*i386_sse_reggroup
;
3830 static struct reggroup
*i386_mmx_reggroup
;
3833 i386_init_reggroups (void)
3835 i386_sse_reggroup
= reggroup_new ("sse", USER_REGGROUP
);
3836 i386_mmx_reggroup
= reggroup_new ("mmx", USER_REGGROUP
);
3840 i386_add_reggroups (struct gdbarch
*gdbarch
)
3842 reggroup_add (gdbarch
, i386_sse_reggroup
);
3843 reggroup_add (gdbarch
, i386_mmx_reggroup
);
3844 reggroup_add (gdbarch
, general_reggroup
);
3845 reggroup_add (gdbarch
, float_reggroup
);
3846 reggroup_add (gdbarch
, all_reggroup
);
3847 reggroup_add (gdbarch
, save_reggroup
);
3848 reggroup_add (gdbarch
, restore_reggroup
);
3849 reggroup_add (gdbarch
, vector_reggroup
);
3850 reggroup_add (gdbarch
, system_reggroup
);
3854 i386_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
3855 struct reggroup
*group
)
3857 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3858 int fp_regnum_p
, mmx_regnum_p
, xmm_regnum_p
, mxcsr_regnum_p
,
3859 ymm_regnum_p
, ymmh_regnum_p
;
3861 /* Don't include pseudo registers, except for MMX, in any register
3863 if (i386_byte_regnum_p (gdbarch
, regnum
))
3866 if (i386_word_regnum_p (gdbarch
, regnum
))
3869 if (i386_dword_regnum_p (gdbarch
, regnum
))
3872 mmx_regnum_p
= i386_mmx_regnum_p (gdbarch
, regnum
);
3873 if (group
== i386_mmx_reggroup
)
3874 return mmx_regnum_p
;
3876 xmm_regnum_p
= i386_xmm_regnum_p (gdbarch
, regnum
);
3877 mxcsr_regnum_p
= i386_mxcsr_regnum_p (gdbarch
, regnum
);
3878 if (group
== i386_sse_reggroup
)
3879 return xmm_regnum_p
|| mxcsr_regnum_p
;
3881 ymm_regnum_p
= i386_ymm_regnum_p (gdbarch
, regnum
);
3882 if (group
== vector_reggroup
)
3883 return (mmx_regnum_p
3887 && ((tdep
->xcr0
& I386_XSTATE_AVX_MASK
)
3888 == I386_XSTATE_SSE_MASK
)));
3890 fp_regnum_p
= (i386_fp_regnum_p (gdbarch
, regnum
)
3891 || i386_fpc_regnum_p (gdbarch
, regnum
));
3892 if (group
== float_reggroup
)
3895 /* For "info reg all", don't include upper YMM registers nor XMM
3896 registers when AVX is supported. */
3897 ymmh_regnum_p
= i386_ymmh_regnum_p (gdbarch
, regnum
);
3898 if (group
== all_reggroup
3900 && (tdep
->xcr0
& I386_XSTATE_AVX
))
3904 if (group
== general_reggroup
)
3905 return (!fp_regnum_p
3912 return default_register_reggroup_p (gdbarch
, regnum
, group
);
3916 /* Get the ARGIth function argument for the current function. */
3919 i386_fetch_pointer_argument (struct frame_info
*frame
, int argi
,
3922 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3923 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3924 CORE_ADDR sp
= get_frame_register_unsigned (frame
, I386_ESP_REGNUM
);
3925 return read_memory_unsigned_integer (sp
+ (4 * (argi
+ 1)), 4, byte_order
);
3929 i386_skip_permanent_breakpoint (struct regcache
*regcache
)
3931 CORE_ADDR current_pc
= regcache_read_pc (regcache
);
3933 /* On i386, breakpoint is exactly 1 byte long, so we just
3934 adjust the PC in the regcache. */
3936 regcache_write_pc (regcache
, current_pc
);
3940 #define PREFIX_REPZ 0x01
3941 #define PREFIX_REPNZ 0x02
3942 #define PREFIX_LOCK 0x04
3943 #define PREFIX_DATA 0x08
3944 #define PREFIX_ADDR 0x10
3956 /* i386 arith/logic operations */
3969 struct i386_record_s
3971 struct gdbarch
*gdbarch
;
3972 struct regcache
*regcache
;
3973 CORE_ADDR orig_addr
;
3979 uint8_t mod
, reg
, rm
;
3988 /* Parse the "modrm" part of the memory address irp->addr points at.
3989 Returns -1 if something goes wrong, 0 otherwise. */
3992 i386_record_modrm (struct i386_record_s
*irp
)
3994 struct gdbarch
*gdbarch
= irp
->gdbarch
;
3996 if (record_read_memory (gdbarch
, irp
->addr
, &irp
->modrm
, 1))
4000 irp
->mod
= (irp
->modrm
>> 6) & 3;
4001 irp
->reg
= (irp
->modrm
>> 3) & 7;
4002 irp
->rm
= irp
->modrm
& 7;
4007 /* Extract the memory address that the current instruction writes to,
4008 and return it in *ADDR. Return -1 if something goes wrong. */
4011 i386_record_lea_modrm_addr (struct i386_record_s
*irp
, uint64_t *addr
)
4013 struct gdbarch
*gdbarch
= irp
->gdbarch
;
4014 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4026 uint8_t base
= irp
->rm
;
4031 if (record_read_memory (gdbarch
, irp
->addr
, &byte
, 1))
4034 scale
= (byte
>> 6) & 3;
4035 index
= ((byte
>> 3) & 7) | irp
->rex_x
;
4043 if ((base
& 7) == 5)
4046 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 4))
4049 *addr
= extract_signed_integer (buf
, 4, byte_order
);
4050 if (irp
->regmap
[X86_RECORD_R8_REGNUM
] && !havesib
)
4051 *addr
+= irp
->addr
+ irp
->rip_offset
;
4055 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 1))
4058 *addr
= (int8_t) buf
[0];
4061 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 4))
4063 *addr
= extract_signed_integer (buf
, 4, byte_order
);
4071 if (base
== 4 && irp
->popl_esp_hack
)
4072 *addr
+= irp
->popl_esp_hack
;
4073 regcache_raw_read_unsigned (irp
->regcache
, irp
->regmap
[base
],
4076 if (irp
->aflag
== 2)
4081 *addr
= (uint32_t) (offset64
+ *addr
);
4083 if (havesib
&& (index
!= 4 || scale
!= 0))
4085 regcache_raw_read_unsigned (irp
->regcache
, irp
->regmap
[index
],
4087 if (irp
->aflag
== 2)
4088 *addr
+= offset64
<< scale
;
4090 *addr
= (uint32_t) (*addr
+ (offset64
<< scale
));
4101 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 2))
4104 *addr
= extract_signed_integer (buf
, 2, byte_order
);
4110 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 1))
4113 *addr
= (int8_t) buf
[0];
4116 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 2))
4119 *addr
= extract_signed_integer (buf
, 2, byte_order
);
4126 regcache_raw_read_unsigned (irp
->regcache
,
4127 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
4129 *addr
= (uint32_t) (*addr
+ offset64
);
4130 regcache_raw_read_unsigned (irp
->regcache
,
4131 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
4133 *addr
= (uint32_t) (*addr
+ offset64
);
4136 regcache_raw_read_unsigned (irp
->regcache
,
4137 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
4139 *addr
= (uint32_t) (*addr
+ offset64
);
4140 regcache_raw_read_unsigned (irp
->regcache
,
4141 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
4143 *addr
= (uint32_t) (*addr
+ offset64
);
4146 regcache_raw_read_unsigned (irp
->regcache
,
4147 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
4149 *addr
= (uint32_t) (*addr
+ offset64
);
4150 regcache_raw_read_unsigned (irp
->regcache
,
4151 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
4153 *addr
= (uint32_t) (*addr
+ offset64
);
4156 regcache_raw_read_unsigned (irp
->regcache
,
4157 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
4159 *addr
= (uint32_t) (*addr
+ offset64
);
4160 regcache_raw_read_unsigned (irp
->regcache
,
4161 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
4163 *addr
= (uint32_t) (*addr
+ offset64
);
4166 regcache_raw_read_unsigned (irp
->regcache
,
4167 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
4169 *addr
= (uint32_t) (*addr
+ offset64
);
4172 regcache_raw_read_unsigned (irp
->regcache
,
4173 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
4175 *addr
= (uint32_t) (*addr
+ offset64
);
4178 regcache_raw_read_unsigned (irp
->regcache
,
4179 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
4181 *addr
= (uint32_t) (*addr
+ offset64
);
4184 regcache_raw_read_unsigned (irp
->regcache
,
4185 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
4187 *addr
= (uint32_t) (*addr
+ offset64
);
4197 /* Record the address and contents of the memory that will be changed
4198 by the current instruction. Return -1 if something goes wrong, 0
4202 i386_record_lea_modrm (struct i386_record_s
*irp
)
4204 struct gdbarch
*gdbarch
= irp
->gdbarch
;
4207 if (irp
->override
>= 0)
4209 if (record_memory_query
)
4213 target_terminal_ours ();
4215 Process record ignores the memory change of instruction at address %s\n\
4216 because it can't get the value of the segment register.\n\
4217 Do you want to stop the program?"),
4218 paddress (gdbarch
, irp
->orig_addr
));
4219 target_terminal_inferior ();
4227 if (i386_record_lea_modrm_addr (irp
, &addr
))
4230 if (record_arch_list_add_mem (addr
, 1 << irp
->ot
))
4236 /* Record the effects of a push operation. Return -1 if something
4237 goes wrong, 0 otherwise. */
4240 i386_record_push (struct i386_record_s
*irp
, int size
)
4244 if (record_arch_list_add_reg (irp
->regcache
,
4245 irp
->regmap
[X86_RECORD_RESP_REGNUM
]))
4247 regcache_raw_read_unsigned (irp
->regcache
,
4248 irp
->regmap
[X86_RECORD_RESP_REGNUM
],
4250 if (record_arch_list_add_mem ((CORE_ADDR
) addr
- size
, size
))
4257 /* Defines contents to record. */
4258 #define I386_SAVE_FPU_REGS 0xfffd
4259 #define I386_SAVE_FPU_ENV 0xfffe
4260 #define I386_SAVE_FPU_ENV_REG_STACK 0xffff
4262 /* Record the values of the floating point registers which will be
4263 changed by the current instruction. Returns -1 if something is
4264 wrong, 0 otherwise. */
4266 static int i386_record_floats (struct gdbarch
*gdbarch
,
4267 struct i386_record_s
*ir
,
4270 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4273 /* Oza: Because of floating point insn push/pop of fpu stack is going to
4274 happen. Currently we store st0-st7 registers, but we need not store all
4275 registers all the time, in future we use ftag register and record only
4276 those who are not marked as an empty. */
4278 if (I386_SAVE_FPU_REGS
== iregnum
)
4280 for (i
= I387_ST0_REGNUM (tdep
); i
<= I387_ST0_REGNUM (tdep
) + 7; i
++)
4282 if (record_arch_list_add_reg (ir
->regcache
, i
))
4286 else if (I386_SAVE_FPU_ENV
== iregnum
)
4288 for (i
= I387_FCTRL_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
4290 if (record_arch_list_add_reg (ir
->regcache
, i
))
4294 else if (I386_SAVE_FPU_ENV_REG_STACK
== iregnum
)
4296 for (i
= I387_ST0_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
4298 if (record_arch_list_add_reg (ir
->regcache
, i
))
4302 else if ((iregnum
>= I387_ST0_REGNUM (tdep
)) &&
4303 (iregnum
<= I387_FOP_REGNUM (tdep
)))
4305 if (record_arch_list_add_reg (ir
->regcache
,iregnum
))
4310 /* Parameter error. */
4313 if(I386_SAVE_FPU_ENV
!= iregnum
)
4315 for (i
= I387_FCTRL_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
4317 if (record_arch_list_add_reg (ir
->regcache
, i
))
4324 /* Parse the current instruction, and record the values of the
4325 registers and memory that will be changed by the current
4326 instruction. Returns -1 if something goes wrong, 0 otherwise. */
4328 #define I386_RECORD_ARCH_LIST_ADD_REG(regnum) \
4329 record_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)])
4332 i386_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4333 CORE_ADDR input_addr
)
4335 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4341 gdb_byte buf
[MAX_REGISTER_SIZE
];
4342 struct i386_record_s ir
;
4343 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4348 memset (&ir
, 0, sizeof (struct i386_record_s
));
4349 ir
.regcache
= regcache
;
4350 ir
.addr
= input_addr
;
4351 ir
.orig_addr
= input_addr
;
4355 ir
.popl_esp_hack
= 0;
4356 ir
.regmap
= tdep
->record_regmap
;
4357 ir
.gdbarch
= gdbarch
;
4359 if (record_debug
> 1)
4360 fprintf_unfiltered (gdb_stdlog
, "Process record: i386_process_record "
4362 paddress (gdbarch
, ir
.addr
));
4367 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
4370 switch (opcode8
) /* Instruction prefixes */
4372 case REPE_PREFIX_OPCODE
:
4373 prefixes
|= PREFIX_REPZ
;
4375 case REPNE_PREFIX_OPCODE
:
4376 prefixes
|= PREFIX_REPNZ
;
4378 case LOCK_PREFIX_OPCODE
:
4379 prefixes
|= PREFIX_LOCK
;
4381 case CS_PREFIX_OPCODE
:
4382 ir
.override
= X86_RECORD_CS_REGNUM
;
4384 case SS_PREFIX_OPCODE
:
4385 ir
.override
= X86_RECORD_SS_REGNUM
;
4387 case DS_PREFIX_OPCODE
:
4388 ir
.override
= X86_RECORD_DS_REGNUM
;
4390 case ES_PREFIX_OPCODE
:
4391 ir
.override
= X86_RECORD_ES_REGNUM
;
4393 case FS_PREFIX_OPCODE
:
4394 ir
.override
= X86_RECORD_FS_REGNUM
;
4396 case GS_PREFIX_OPCODE
:
4397 ir
.override
= X86_RECORD_GS_REGNUM
;
4399 case DATA_PREFIX_OPCODE
:
4400 prefixes
|= PREFIX_DATA
;
4402 case ADDR_PREFIX_OPCODE
:
4403 prefixes
|= PREFIX_ADDR
;
4405 case 0x40: /* i386 inc %eax */
4406 case 0x41: /* i386 inc %ecx */
4407 case 0x42: /* i386 inc %edx */
4408 case 0x43: /* i386 inc %ebx */
4409 case 0x44: /* i386 inc %esp */
4410 case 0x45: /* i386 inc %ebp */
4411 case 0x46: /* i386 inc %esi */
4412 case 0x47: /* i386 inc %edi */
4413 case 0x48: /* i386 dec %eax */
4414 case 0x49: /* i386 dec %ecx */
4415 case 0x4a: /* i386 dec %edx */
4416 case 0x4b: /* i386 dec %ebx */
4417 case 0x4c: /* i386 dec %esp */
4418 case 0x4d: /* i386 dec %ebp */
4419 case 0x4e: /* i386 dec %esi */
4420 case 0x4f: /* i386 dec %edi */
4421 if (ir
.regmap
[X86_RECORD_R8_REGNUM
]) /* 64 bit target */
4425 rex_w
= (opcode8
>> 3) & 1;
4426 rex_r
= (opcode8
& 0x4) << 1;
4427 ir
.rex_x
= (opcode8
& 0x2) << 2;
4428 ir
.rex_b
= (opcode8
& 0x1) << 3;
4430 else /* 32 bit target */
4439 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && rex_w
== 1)
4445 if (prefixes
& PREFIX_DATA
)
4448 if (prefixes
& PREFIX_ADDR
)
4450 else if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4453 /* Now check op code. */
4454 opcode
= (uint32_t) opcode8
;
4459 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
4462 opcode
= (uint32_t) opcode8
| 0x0f00;
4466 case 0x00: /* arith & logic */
4514 if (((opcode
>> 3) & 7) != OP_CMPL
)
4516 if ((opcode
& 1) == 0)
4519 ir
.ot
= ir
.dflag
+ OT_WORD
;
4521 switch ((opcode
>> 1) & 3)
4523 case 0: /* OP Ev, Gv */
4524 if (i386_record_modrm (&ir
))
4528 if (i386_record_lea_modrm (&ir
))
4534 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4536 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4539 case 1: /* OP Gv, Ev */
4540 if (i386_record_modrm (&ir
))
4543 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4545 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4547 case 2: /* OP A, Iv */
4548 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4552 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4555 case 0x80: /* GRP1 */
4559 if (i386_record_modrm (&ir
))
4562 if (ir
.reg
!= OP_CMPL
)
4564 if ((opcode
& 1) == 0)
4567 ir
.ot
= ir
.dflag
+ OT_WORD
;
4574 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
4575 if (i386_record_lea_modrm (&ir
))
4579 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
4581 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4584 case 0x40: /* inc */
4593 case 0x48: /* dec */
4602 I386_RECORD_ARCH_LIST_ADD_REG (opcode
& 7);
4603 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4606 case 0xf6: /* GRP3 */
4608 if ((opcode
& 1) == 0)
4611 ir
.ot
= ir
.dflag
+ OT_WORD
;
4612 if (i386_record_modrm (&ir
))
4615 if (ir
.mod
!= 3 && ir
.reg
== 0)
4616 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
4621 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4627 if (i386_record_lea_modrm (&ir
))
4633 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4635 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4637 if (ir
.reg
== 3) /* neg */
4638 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4644 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4645 if (ir
.ot
!= OT_BYTE
)
4646 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
4647 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4651 opcode
= opcode
<< 8 | ir
.modrm
;
4657 case 0xfe: /* GRP4 */
4658 case 0xff: /* GRP5 */
4659 if (i386_record_modrm (&ir
))
4661 if (ir
.reg
>= 2 && opcode
== 0xfe)
4664 opcode
= opcode
<< 8 | ir
.modrm
;
4671 if ((opcode
& 1) == 0)
4674 ir
.ot
= ir
.dflag
+ OT_WORD
;
4677 if (i386_record_lea_modrm (&ir
))
4683 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4685 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4687 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4690 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4692 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4694 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4697 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
4698 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4700 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4704 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4707 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4709 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4714 opcode
= opcode
<< 8 | ir
.modrm
;
4720 case 0x84: /* test */
4724 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4727 case 0x98: /* CWDE/CBW */
4728 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4731 case 0x99: /* CDQ/CWD */
4732 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4733 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
4736 case 0x0faf: /* imul */
4739 ir
.ot
= ir
.dflag
+ OT_WORD
;
4740 if (i386_record_modrm (&ir
))
4743 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
4744 else if (opcode
== 0x6b)
4747 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4749 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4750 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4753 case 0x0fc0: /* xadd */
4755 if ((opcode
& 1) == 0)
4758 ir
.ot
= ir
.dflag
+ OT_WORD
;
4759 if (i386_record_modrm (&ir
))
4764 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4766 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4767 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4769 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4773 if (i386_record_lea_modrm (&ir
))
4775 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4777 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4779 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4782 case 0x0fb0: /* cmpxchg */
4784 if ((opcode
& 1) == 0)
4787 ir
.ot
= ir
.dflag
+ OT_WORD
;
4788 if (i386_record_modrm (&ir
))
4793 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4794 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4796 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4800 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4801 if (i386_record_lea_modrm (&ir
))
4804 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4807 case 0x0fc7: /* cmpxchg8b */
4808 if (i386_record_modrm (&ir
))
4813 opcode
= opcode
<< 8 | ir
.modrm
;
4816 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4817 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
4818 if (i386_record_lea_modrm (&ir
))
4820 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4823 case 0x50: /* push */
4833 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4835 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4839 case 0x06: /* push es */
4840 case 0x0e: /* push cs */
4841 case 0x16: /* push ss */
4842 case 0x1e: /* push ds */
4843 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4848 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4852 case 0x0fa0: /* push fs */
4853 case 0x0fa8: /* push gs */
4854 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4859 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4863 case 0x60: /* pusha */
4864 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4869 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 4)))
4873 case 0x58: /* pop */
4881 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4882 I386_RECORD_ARCH_LIST_ADD_REG ((opcode
& 0x7) | ir
.rex_b
);
4885 case 0x61: /* popa */
4886 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4891 for (regnum
= X86_RECORD_REAX_REGNUM
;
4892 regnum
<= X86_RECORD_REDI_REGNUM
;
4894 I386_RECORD_ARCH_LIST_ADD_REG (regnum
);
4897 case 0x8f: /* pop */
4898 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4899 ir
.ot
= ir
.dflag
? OT_QUAD
: OT_WORD
;
4901 ir
.ot
= ir
.dflag
+ OT_WORD
;
4902 if (i386_record_modrm (&ir
))
4905 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
4908 ir
.popl_esp_hack
= 1 << ir
.ot
;
4909 if (i386_record_lea_modrm (&ir
))
4912 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4915 case 0xc8: /* enter */
4916 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
4917 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4919 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4923 case 0xc9: /* leave */
4924 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4925 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
4928 case 0x07: /* pop es */
4929 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4934 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4935 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM
);
4936 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4939 case 0x17: /* pop ss */
4940 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4945 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4946 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM
);
4947 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4950 case 0x1f: /* pop ds */
4951 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4956 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4957 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM
);
4958 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4961 case 0x0fa1: /* pop fs */
4962 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4963 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM
);
4964 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4967 case 0x0fa9: /* pop gs */
4968 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4969 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM
);
4970 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4973 case 0x88: /* mov */
4977 if ((opcode
& 1) == 0)
4980 ir
.ot
= ir
.dflag
+ OT_WORD
;
4982 if (i386_record_modrm (&ir
))
4987 if (opcode
== 0xc6 || opcode
== 0xc7)
4988 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
4989 if (i386_record_lea_modrm (&ir
))
4994 if (opcode
== 0xc6 || opcode
== 0xc7)
4996 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4998 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
5002 case 0x8a: /* mov */
5004 if ((opcode
& 1) == 0)
5007 ir
.ot
= ir
.dflag
+ OT_WORD
;
5008 if (i386_record_modrm (&ir
))
5011 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5013 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
5016 case 0x8c: /* mov seg */
5017 if (i386_record_modrm (&ir
))
5022 opcode
= opcode
<< 8 | ir
.modrm
;
5027 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
5031 if (i386_record_lea_modrm (&ir
))
5036 case 0x8e: /* mov seg */
5037 if (i386_record_modrm (&ir
))
5042 regnum
= X86_RECORD_ES_REGNUM
;
5045 regnum
= X86_RECORD_SS_REGNUM
;
5048 regnum
= X86_RECORD_DS_REGNUM
;
5051 regnum
= X86_RECORD_FS_REGNUM
;
5054 regnum
= X86_RECORD_GS_REGNUM
;
5058 opcode
= opcode
<< 8 | ir
.modrm
;
5062 I386_RECORD_ARCH_LIST_ADD_REG (regnum
);
5063 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5066 case 0x0fb6: /* movzbS */
5067 case 0x0fb7: /* movzwS */
5068 case 0x0fbe: /* movsbS */
5069 case 0x0fbf: /* movswS */
5070 if (i386_record_modrm (&ir
))
5072 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
5075 case 0x8d: /* lea */
5076 if (i386_record_modrm (&ir
))
5081 opcode
= opcode
<< 8 | ir
.modrm
;
5086 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5088 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
5091 case 0xa0: /* mov EAX */
5094 case 0xd7: /* xlat */
5095 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5098 case 0xa2: /* mov EAX */
5100 if (ir
.override
>= 0)
5102 if (record_memory_query
)
5106 target_terminal_ours ();
5108 Process record ignores the memory change of instruction at address %s\n\
5109 because it can't get the value of the segment register.\n\
5110 Do you want to stop the program?"),
5111 paddress (gdbarch
, ir
.orig_addr
));
5112 target_terminal_inferior ();
5119 if ((opcode
& 1) == 0)
5122 ir
.ot
= ir
.dflag
+ OT_WORD
;
5125 if (record_read_memory (gdbarch
, ir
.addr
, buf
, 8))
5128 addr
= extract_unsigned_integer (buf
, 8, byte_order
);
5132 if (record_read_memory (gdbarch
, ir
.addr
, buf
, 4))
5135 addr
= extract_unsigned_integer (buf
, 4, byte_order
);
5139 if (record_read_memory (gdbarch
, ir
.addr
, buf
, 2))
5142 addr
= extract_unsigned_integer (buf
, 2, byte_order
);
5144 if (record_arch_list_add_mem (addr
, 1 << ir
.ot
))
5149 case 0xb0: /* mov R, Ib */
5157 I386_RECORD_ARCH_LIST_ADD_REG ((ir
.regmap
[X86_RECORD_R8_REGNUM
])
5158 ? ((opcode
& 0x7) | ir
.rex_b
)
5159 : ((opcode
& 0x7) & 0x3));
5162 case 0xb8: /* mov R, Iv */
5170 I386_RECORD_ARCH_LIST_ADD_REG ((opcode
& 0x7) | ir
.rex_b
);
5173 case 0x91: /* xchg R, EAX */
5180 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5181 I386_RECORD_ARCH_LIST_ADD_REG (opcode
& 0x7);
5184 case 0x86: /* xchg Ev, Gv */
5186 if ((opcode
& 1) == 0)
5189 ir
.ot
= ir
.dflag
+ OT_WORD
;
5190 if (i386_record_modrm (&ir
))
5195 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5197 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
5201 if (i386_record_lea_modrm (&ir
))
5205 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5207 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
5210 case 0xc4: /* les Gv */
5211 case 0xc5: /* lds Gv */
5212 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5218 case 0x0fb2: /* lss Gv */
5219 case 0x0fb4: /* lfs Gv */
5220 case 0x0fb5: /* lgs Gv */
5221 if (i386_record_modrm (&ir
))
5229 opcode
= opcode
<< 8 | ir
.modrm
;
5234 case 0xc4: /* les Gv */
5235 regnum
= X86_RECORD_ES_REGNUM
;
5237 case 0xc5: /* lds Gv */
5238 regnum
= X86_RECORD_DS_REGNUM
;
5240 case 0x0fb2: /* lss Gv */
5241 regnum
= X86_RECORD_SS_REGNUM
;
5243 case 0x0fb4: /* lfs Gv */
5244 regnum
= X86_RECORD_FS_REGNUM
;
5246 case 0x0fb5: /* lgs Gv */
5247 regnum
= X86_RECORD_GS_REGNUM
;
5250 I386_RECORD_ARCH_LIST_ADD_REG (regnum
);
5251 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
5252 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5255 case 0xc0: /* shifts */
5261 if ((opcode
& 1) == 0)
5264 ir
.ot
= ir
.dflag
+ OT_WORD
;
5265 if (i386_record_modrm (&ir
))
5267 if (ir
.mod
!= 3 && (opcode
== 0xd2 || opcode
== 0xd3))
5269 if (i386_record_lea_modrm (&ir
))
5275 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5277 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
5279 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5286 if (i386_record_modrm (&ir
))
5290 if (record_arch_list_add_reg (ir
.regcache
, ir
.rm
))
5295 if (i386_record_lea_modrm (&ir
))
5300 case 0xd8: /* Floats. */
5308 if (i386_record_modrm (&ir
))
5310 ir
.reg
|= ((opcode
& 7) << 3);
5316 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
5324 /* For fcom, ficom nothing to do. */
5330 /* For fcomp, ficomp pop FPU stack, store all. */
5331 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5358 /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul,
5359 fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension
5360 of code, always affects st(0) register. */
5361 if (i386_record_floats (gdbarch
, &ir
, I387_ST0_REGNUM (tdep
)))
5385 /* Handling fld, fild. */
5386 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5390 switch (ir
.reg
>> 4)
5393 if (record_arch_list_add_mem (addr64
, 4))
5397 if (record_arch_list_add_mem (addr64
, 8))
5403 if (record_arch_list_add_mem (addr64
, 2))
5409 switch (ir
.reg
>> 4)
5412 if (record_arch_list_add_mem (addr64
, 4))
5414 if (3 == (ir
.reg
& 7))
5416 /* For fstp m32fp. */
5417 if (i386_record_floats (gdbarch
, &ir
,
5418 I386_SAVE_FPU_REGS
))
5423 if (record_arch_list_add_mem (addr64
, 4))
5425 if ((3 == (ir
.reg
& 7))
5426 || (5 == (ir
.reg
& 7))
5427 || (7 == (ir
.reg
& 7)))
5429 /* For fstp insn. */
5430 if (i386_record_floats (gdbarch
, &ir
,
5431 I386_SAVE_FPU_REGS
))
5436 if (record_arch_list_add_mem (addr64
, 8))
5438 if (3 == (ir
.reg
& 7))
5440 /* For fstp m64fp. */
5441 if (i386_record_floats (gdbarch
, &ir
,
5442 I386_SAVE_FPU_REGS
))
5447 if ((3 <= (ir
.reg
& 7)) && (6 <= (ir
.reg
& 7)))
5449 /* For fistp, fbld, fild, fbstp. */
5450 if (i386_record_floats (gdbarch
, &ir
,
5451 I386_SAVE_FPU_REGS
))
5456 if (record_arch_list_add_mem (addr64
, 2))
5465 if (i386_record_floats (gdbarch
, &ir
,
5466 I386_SAVE_FPU_ENV_REG_STACK
))
5471 if (i386_record_floats (gdbarch
, &ir
, I387_FCTRL_REGNUM (tdep
)))
5476 if (i386_record_floats (gdbarch
, &ir
,
5477 I386_SAVE_FPU_ENV_REG_STACK
))
5483 if (record_arch_list_add_mem (addr64
, 28))
5488 if (record_arch_list_add_mem (addr64
, 14))
5494 if (record_arch_list_add_mem (addr64
, 2))
5496 /* Insn fstp, fbstp. */
5497 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5502 if (record_arch_list_add_mem (addr64
, 10))
5508 if (record_arch_list_add_mem (addr64
, 28))
5514 if (record_arch_list_add_mem (addr64
, 14))
5518 if (record_arch_list_add_mem (addr64
, 80))
5521 if (i386_record_floats (gdbarch
, &ir
,
5522 I386_SAVE_FPU_ENV_REG_STACK
))
5526 if (record_arch_list_add_mem (addr64
, 8))
5529 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5534 opcode
= opcode
<< 8 | ir
.modrm
;
5539 /* Opcode is an extension of modR/M byte. */
5545 if (i386_record_floats (gdbarch
, &ir
, I387_ST0_REGNUM (tdep
)))
5549 if (0x0c == (ir
.modrm
>> 4))
5551 if ((ir
.modrm
& 0x0f) <= 7)
5553 if (i386_record_floats (gdbarch
, &ir
,
5554 I386_SAVE_FPU_REGS
))
5559 if (i386_record_floats (gdbarch
, &ir
,
5560 I387_ST0_REGNUM (tdep
)))
5562 /* If only st(0) is changing, then we have already
5564 if ((ir
.modrm
& 0x0f) - 0x08)
5566 if (i386_record_floats (gdbarch
, &ir
,
5567 I387_ST0_REGNUM (tdep
) +
5568 ((ir
.modrm
& 0x0f) - 0x08)))
5586 if (i386_record_floats (gdbarch
, &ir
,
5587 I387_ST0_REGNUM (tdep
)))
5605 if (i386_record_floats (gdbarch
, &ir
,
5606 I386_SAVE_FPU_REGS
))
5610 if (i386_record_floats (gdbarch
, &ir
,
5611 I387_ST0_REGNUM (tdep
)))
5613 if (i386_record_floats (gdbarch
, &ir
,
5614 I387_ST0_REGNUM (tdep
) + 1))
5621 if (0xe9 == ir
.modrm
)
5623 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5626 else if ((0x0c == ir
.modrm
>> 4) || (0x0d == ir
.modrm
>> 4))
5628 if (i386_record_floats (gdbarch
, &ir
,
5629 I387_ST0_REGNUM (tdep
)))
5631 if (((ir
.modrm
& 0x0f) > 0) && ((ir
.modrm
& 0x0f) <= 7))
5633 if (i386_record_floats (gdbarch
, &ir
,
5634 I387_ST0_REGNUM (tdep
) +
5638 else if ((ir
.modrm
& 0x0f) - 0x08)
5640 if (i386_record_floats (gdbarch
, &ir
,
5641 I387_ST0_REGNUM (tdep
) +
5642 ((ir
.modrm
& 0x0f) - 0x08)))
5648 if (0xe3 == ir
.modrm
)
5650 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_ENV
))
5653 else if ((0x0c == ir
.modrm
>> 4) || (0x0d == ir
.modrm
>> 4))
5655 if (i386_record_floats (gdbarch
, &ir
,
5656 I387_ST0_REGNUM (tdep
)))
5658 if (((ir
.modrm
& 0x0f) > 0) && ((ir
.modrm
& 0x0f) <= 7))
5660 if (i386_record_floats (gdbarch
, &ir
,
5661 I387_ST0_REGNUM (tdep
) +
5665 else if ((ir
.modrm
& 0x0f) - 0x08)
5667 if (i386_record_floats (gdbarch
, &ir
,
5668 I387_ST0_REGNUM (tdep
) +
5669 ((ir
.modrm
& 0x0f) - 0x08)))
5675 if ((0x0c == ir
.modrm
>> 4)
5676 || (0x0d == ir
.modrm
>> 4)
5677 || (0x0f == ir
.modrm
>> 4))
5679 if ((ir
.modrm
& 0x0f) <= 7)
5681 if (i386_record_floats (gdbarch
, &ir
,
5682 I387_ST0_REGNUM (tdep
) +
5688 if (i386_record_floats (gdbarch
, &ir
,
5689 I387_ST0_REGNUM (tdep
) +
5690 ((ir
.modrm
& 0x0f) - 0x08)))
5696 if (0x0c == ir
.modrm
>> 4)
5698 if (i386_record_floats (gdbarch
, &ir
,
5699 I387_FTAG_REGNUM (tdep
)))
5702 else if ((0x0d == ir
.modrm
>> 4) || (0x0e == ir
.modrm
>> 4))
5704 if ((ir
.modrm
& 0x0f) <= 7)
5706 if (i386_record_floats (gdbarch
, &ir
,
5707 I387_ST0_REGNUM (tdep
) +
5713 if (i386_record_floats (gdbarch
, &ir
,
5714 I386_SAVE_FPU_REGS
))
5720 if ((0x0c == ir
.modrm
>> 4)
5721 || (0x0e == ir
.modrm
>> 4)
5722 || (0x0f == ir
.modrm
>> 4)
5723 || (0xd9 == ir
.modrm
))
5725 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5730 if (0xe0 == ir
.modrm
)
5732 if (record_arch_list_add_reg (ir
.regcache
, I386_EAX_REGNUM
))
5735 else if ((0x0f == ir
.modrm
>> 4) || (0x0e == ir
.modrm
>> 4))
5737 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5745 case 0xa4: /* movsS */
5747 case 0xaa: /* stosS */
5749 case 0x6c: /* insS */
5751 regcache_raw_read_unsigned (ir
.regcache
,
5752 ir
.regmap
[X86_RECORD_RECX_REGNUM
],
5758 if ((opcode
& 1) == 0)
5761 ir
.ot
= ir
.dflag
+ OT_WORD
;
5762 regcache_raw_read_unsigned (ir
.regcache
,
5763 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
5766 regcache_raw_read_unsigned (ir
.regcache
,
5767 ir
.regmap
[X86_RECORD_ES_REGNUM
],
5769 regcache_raw_read_unsigned (ir
.regcache
,
5770 ir
.regmap
[X86_RECORD_DS_REGNUM
],
5772 if (ir
.aflag
&& (es
!= ds
))
5774 /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */
5775 if (record_memory_query
)
5779 target_terminal_ours ();
5781 Process record ignores the memory change of instruction at address %s\n\
5782 because it can't get the value of the segment register.\n\
5783 Do you want to stop the program?"),
5784 paddress (gdbarch
, ir
.orig_addr
));
5785 target_terminal_inferior ();
5792 if (record_arch_list_add_mem (addr
, 1 << ir
.ot
))
5796 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5797 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5798 if (opcode
== 0xa4 || opcode
== 0xa5)
5799 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
5800 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
5801 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5805 case 0xa6: /* cmpsS */
5807 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
5808 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
5809 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5810 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5811 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5814 case 0xac: /* lodsS */
5816 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5817 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
5818 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5819 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5820 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5823 case 0xae: /* scasS */
5825 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
5826 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5827 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5828 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5831 case 0x6e: /* outsS */
5833 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
5834 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5835 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5836 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5839 case 0xe4: /* port I/O */
5843 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5844 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5854 case 0xc2: /* ret im */
5855 case 0xc3: /* ret */
5856 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5857 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5860 case 0xca: /* lret im */
5861 case 0xcb: /* lret */
5862 case 0xcf: /* iret */
5863 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
5864 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5865 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5868 case 0xe8: /* call im */
5869 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5871 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5875 case 0x9a: /* lcall im */
5876 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5881 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
5882 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5886 case 0xe9: /* jmp im */
5887 case 0xea: /* ljmp im */
5888 case 0xeb: /* jmp Jb */
5889 case 0x70: /* jcc Jb */
5905 case 0x0f80: /* jcc Jv */
5923 case 0x0f90: /* setcc Gv */
5939 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5941 if (i386_record_modrm (&ir
))
5944 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rex_b
? (ir
.rm
| ir
.rex_b
)
5948 if (i386_record_lea_modrm (&ir
))
5953 case 0x0f40: /* cmov Gv, Ev */
5969 if (i386_record_modrm (&ir
))
5972 if (ir
.dflag
== OT_BYTE
)
5974 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
5978 case 0x9c: /* pushf */
5979 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5980 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5982 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5986 case 0x9d: /* popf */
5987 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5988 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5991 case 0x9e: /* sahf */
5992 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5998 case 0xf5: /* cmc */
5999 case 0xf8: /* clc */
6000 case 0xf9: /* stc */
6001 case 0xfc: /* cld */
6002 case 0xfd: /* std */
6003 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6006 case 0x9f: /* lahf */
6007 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6012 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6013 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6016 /* bit operations */
6017 case 0x0fba: /* bt/bts/btr/btc Gv, im */
6018 ir
.ot
= ir
.dflag
+ OT_WORD
;
6019 if (i386_record_modrm (&ir
))
6024 opcode
= opcode
<< 8 | ir
.modrm
;
6030 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6033 if (i386_record_lea_modrm (&ir
))
6037 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6040 case 0x0fa3: /* bt Gv, Ev */
6041 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6044 case 0x0fab: /* bts */
6045 case 0x0fb3: /* btr */
6046 case 0x0fbb: /* btc */
6047 ir
.ot
= ir
.dflag
+ OT_WORD
;
6048 if (i386_record_modrm (&ir
))
6051 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6055 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
6057 regcache_raw_read_unsigned (ir
.regcache
,
6058 ir
.regmap
[ir
.reg
| rex_r
],
6063 addr64
+= ((int16_t) addr
>> 4) << 4;
6066 addr64
+= ((int32_t) addr
>> 5) << 5;
6069 addr64
+= ((int64_t) addr
>> 6) << 6;
6072 if (record_arch_list_add_mem (addr64
, 1 << ir
.ot
))
6074 if (i386_record_lea_modrm (&ir
))
6077 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6080 case 0x0fbc: /* bsf */
6081 case 0x0fbd: /* bsr */
6082 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
6083 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6087 case 0x27: /* daa */
6088 case 0x2f: /* das */
6089 case 0x37: /* aaa */
6090 case 0x3f: /* aas */
6091 case 0xd4: /* aam */
6092 case 0xd5: /* aad */
6093 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6098 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6099 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6103 case 0x90: /* nop */
6104 if (prefixes
& PREFIX_LOCK
)
6111 case 0x9b: /* fwait */
6112 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
6114 opcode
= (uint32_t) opcode8
;
6120 case 0xcc: /* int3 */
6121 printf_unfiltered (_("Process record does not support instruction "
6128 case 0xcd: /* int */
6132 if (record_read_memory (gdbarch
, ir
.addr
, &interrupt
, 1))
6135 if (interrupt
!= 0x80
6136 || tdep
->i386_intx80_record
== NULL
)
6138 printf_unfiltered (_("Process record does not support "
6139 "instruction int 0x%02x.\n"),
6144 ret
= tdep
->i386_intx80_record (ir
.regcache
);
6151 case 0xce: /* into */
6152 printf_unfiltered (_("Process record does not support "
6153 "instruction into.\n"));
6158 case 0xfa: /* cli */
6159 case 0xfb: /* sti */
6162 case 0x62: /* bound */
6163 printf_unfiltered (_("Process record does not support "
6164 "instruction bound.\n"));
6169 case 0x0fc8: /* bswap reg */
6177 I386_RECORD_ARCH_LIST_ADD_REG ((opcode
& 7) | ir
.rex_b
);
6180 case 0xd6: /* salc */
6181 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6186 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6187 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6190 case 0xe0: /* loopnz */
6191 case 0xe1: /* loopz */
6192 case 0xe2: /* loop */
6193 case 0xe3: /* jecxz */
6194 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6195 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6198 case 0x0f30: /* wrmsr */
6199 printf_unfiltered (_("Process record does not support "
6200 "instruction wrmsr.\n"));
6205 case 0x0f32: /* rdmsr */
6206 printf_unfiltered (_("Process record does not support "
6207 "instruction rdmsr.\n"));
6212 case 0x0f31: /* rdtsc */
6213 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6214 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
6217 case 0x0f34: /* sysenter */
6220 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6225 if (tdep
->i386_sysenter_record
== NULL
)
6227 printf_unfiltered (_("Process record does not support "
6228 "instruction sysenter.\n"));
6232 ret
= tdep
->i386_sysenter_record (ir
.regcache
);
6238 case 0x0f35: /* sysexit */
6239 printf_unfiltered (_("Process record does not support "
6240 "instruction sysexit.\n"));
6245 case 0x0f05: /* syscall */
6248 if (tdep
->i386_syscall_record
== NULL
)
6250 printf_unfiltered (_("Process record does not support "
6251 "instruction syscall.\n"));
6255 ret
= tdep
->i386_syscall_record (ir
.regcache
);
6261 case 0x0f07: /* sysret */
6262 printf_unfiltered (_("Process record does not support "
6263 "instruction sysret.\n"));
6268 case 0x0fa2: /* cpuid */
6269 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6270 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6271 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
6272 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM
);
6275 case 0xf4: /* hlt */
6276 printf_unfiltered (_("Process record does not support "
6277 "instruction hlt.\n"));
6283 if (i386_record_modrm (&ir
))
6290 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6294 if (i386_record_lea_modrm (&ir
))
6303 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6307 opcode
= opcode
<< 8 | ir
.modrm
;
6314 if (i386_record_modrm (&ir
))
6325 opcode
= opcode
<< 8 | ir
.modrm
;
6328 if (ir
.override
>= 0)
6330 if (record_memory_query
)
6334 target_terminal_ours ();
6336 Process record ignores the memory change of instruction at address %s\n\
6337 because it can't get the value of the segment register.\n\
6338 Do you want to stop the program?"),
6339 paddress (gdbarch
, ir
.orig_addr
));
6340 target_terminal_inferior ();
6347 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
6349 if (record_arch_list_add_mem (addr64
, 2))
6352 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6354 if (record_arch_list_add_mem (addr64
, 8))
6359 if (record_arch_list_add_mem (addr64
, 4))
6370 case 0: /* monitor */
6373 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6377 opcode
= opcode
<< 8 | ir
.modrm
;
6385 if (ir
.override
>= 0)
6387 if (record_memory_query
)
6391 target_terminal_ours ();
6393 Process record ignores the memory change of instruction at address %s\n\
6394 because it can't get the value of the segment register.\n\
6395 Do you want to stop the program?"),
6396 paddress (gdbarch
, ir
.orig_addr
));
6397 target_terminal_inferior ();
6406 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
6408 if (record_arch_list_add_mem (addr64
, 2))
6411 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6413 if (record_arch_list_add_mem (addr64
, 8))
6418 if (record_arch_list_add_mem (addr64
, 4))
6430 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6431 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
6435 else if (ir
.rm
== 1)
6442 opcode
= opcode
<< 8 | ir
.modrm
;
6449 if (record_arch_list_add_reg (ir
.regcache
, ir
.rm
| ir
.rex_b
))
6455 if (i386_record_lea_modrm (&ir
))
6458 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6461 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6463 case 7: /* invlpg */
6466 if (ir
.rm
== 0 && ir
.regmap
[X86_RECORD_R8_REGNUM
])
6467 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM
);
6471 opcode
= opcode
<< 8 | ir
.modrm
;
6476 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6480 opcode
= opcode
<< 8 | ir
.modrm
;
6486 case 0x0f08: /* invd */
6487 case 0x0f09: /* wbinvd */
6490 case 0x63: /* arpl */
6491 if (i386_record_modrm (&ir
))
6493 if (ir
.mod
== 3 || ir
.regmap
[X86_RECORD_R8_REGNUM
])
6495 I386_RECORD_ARCH_LIST_ADD_REG (ir
.regmap
[X86_RECORD_R8_REGNUM
]
6496 ? (ir
.reg
| rex_r
) : ir
.rm
);
6500 ir
.ot
= ir
.dflag
? OT_LONG
: OT_WORD
;
6501 if (i386_record_lea_modrm (&ir
))
6504 if (!ir
.regmap
[X86_RECORD_R8_REGNUM
])
6505 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6508 case 0x0f02: /* lar */
6509 case 0x0f03: /* lsl */
6510 if (i386_record_modrm (&ir
))
6512 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
6513 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6517 if (i386_record_modrm (&ir
))
6519 if (ir
.mod
== 3 && ir
.reg
== 3)
6522 opcode
= opcode
<< 8 | ir
.modrm
;
6534 /* nop (multi byte) */
6537 case 0x0f20: /* mov reg, crN */
6538 case 0x0f22: /* mov crN, reg */
6539 if (i386_record_modrm (&ir
))
6541 if ((ir
.modrm
& 0xc0) != 0xc0)
6544 opcode
= opcode
<< 8 | ir
.modrm
;
6555 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6557 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6561 opcode
= opcode
<< 8 | ir
.modrm
;
6567 case 0x0f21: /* mov reg, drN */
6568 case 0x0f23: /* mov drN, reg */
6569 if (i386_record_modrm (&ir
))
6571 if ((ir
.modrm
& 0xc0) != 0xc0 || ir
.reg
== 4
6572 || ir
.reg
== 5 || ir
.reg
>= 8)
6575 opcode
= opcode
<< 8 | ir
.modrm
;
6579 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6581 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6584 case 0x0f06: /* clts */
6585 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6588 /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */
6590 case 0x0f0d: /* 3DNow! prefetch */
6593 case 0x0f0e: /* 3DNow! femms */
6594 case 0x0f77: /* emms */
6595 if (i386_fpc_regnum_p (gdbarch
, I387_FTAG_REGNUM(tdep
)))
6597 record_arch_list_add_reg (ir
.regcache
, I387_FTAG_REGNUM(tdep
));
6600 case 0x0f0f: /* 3DNow! data */
6601 if (i386_record_modrm (&ir
))
6603 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
6608 case 0x0c: /* 3DNow! pi2fw */
6609 case 0x0d: /* 3DNow! pi2fd */
6610 case 0x1c: /* 3DNow! pf2iw */
6611 case 0x1d: /* 3DNow! pf2id */
6612 case 0x8a: /* 3DNow! pfnacc */
6613 case 0x8e: /* 3DNow! pfpnacc */
6614 case 0x90: /* 3DNow! pfcmpge */
6615 case 0x94: /* 3DNow! pfmin */
6616 case 0x96: /* 3DNow! pfrcp */
6617 case 0x97: /* 3DNow! pfrsqrt */
6618 case 0x9a: /* 3DNow! pfsub */
6619 case 0x9e: /* 3DNow! pfadd */
6620 case 0xa0: /* 3DNow! pfcmpgt */
6621 case 0xa4: /* 3DNow! pfmax */
6622 case 0xa6: /* 3DNow! pfrcpit1 */
6623 case 0xa7: /* 3DNow! pfrsqit1 */
6624 case 0xaa: /* 3DNow! pfsubr */
6625 case 0xae: /* 3DNow! pfacc */
6626 case 0xb0: /* 3DNow! pfcmpeq */
6627 case 0xb4: /* 3DNow! pfmul */
6628 case 0xb6: /* 3DNow! pfrcpit2 */
6629 case 0xb7: /* 3DNow! pmulhrw */
6630 case 0xbb: /* 3DNow! pswapd */
6631 case 0xbf: /* 3DNow! pavgusb */
6632 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.reg
))
6633 goto no_support_3dnow_data
;
6634 record_arch_list_add_reg (ir
.regcache
, ir
.reg
);
6638 no_support_3dnow_data
:
6639 opcode
= (opcode
<< 8) | opcode8
;
6645 case 0x0faa: /* rsm */
6646 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6647 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6648 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6649 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
6650 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM
);
6651 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
6652 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
6653 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
6654 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
6658 if (i386_record_modrm (&ir
))
6662 case 0: /* fxsave */
6666 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6667 if (i386_record_lea_modrm_addr (&ir
, &tmpu64
))
6669 if (record_arch_list_add_mem (tmpu64
, 512))
6674 case 1: /* fxrstor */
6678 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6680 for (i
= I387_MM0_REGNUM (tdep
);
6681 i386_mmx_regnum_p (gdbarch
, i
); i
++)
6682 record_arch_list_add_reg (ir
.regcache
, i
);
6684 for (i
= I387_XMM0_REGNUM (tdep
);
6685 i386_xmm_regnum_p (gdbarch
, i
); i
++)
6686 record_arch_list_add_reg (ir
.regcache
, i
);
6688 if (i386_mxcsr_regnum_p (gdbarch
, I387_MXCSR_REGNUM(tdep
)))
6689 record_arch_list_add_reg (ir
.regcache
, I387_MXCSR_REGNUM(tdep
));
6691 for (i
= I387_ST0_REGNUM (tdep
);
6692 i386_fp_regnum_p (gdbarch
, i
); i
++)
6693 record_arch_list_add_reg (ir
.regcache
, i
);
6695 for (i
= I387_FCTRL_REGNUM (tdep
);
6696 i386_fpc_regnum_p (gdbarch
, i
); i
++)
6697 record_arch_list_add_reg (ir
.regcache
, i
);
6701 case 2: /* ldmxcsr */
6702 if (!i386_mxcsr_regnum_p (gdbarch
, I387_MXCSR_REGNUM(tdep
)))
6704 record_arch_list_add_reg (ir
.regcache
, I387_MXCSR_REGNUM(tdep
));
6707 case 3: /* stmxcsr */
6709 if (i386_record_lea_modrm (&ir
))
6713 case 5: /* lfence */
6714 case 6: /* mfence */
6715 case 7: /* sfence clflush */
6719 opcode
= (opcode
<< 8) | ir
.modrm
;
6725 case 0x0fc3: /* movnti */
6726 ir
.ot
= (ir
.dflag
== 2) ? OT_QUAD
: OT_LONG
;
6727 if (i386_record_modrm (&ir
))
6732 if (i386_record_lea_modrm (&ir
))
6736 /* Add prefix to opcode. */
6863 reswitch_prefix_add
:
6871 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
6874 opcode
= (uint32_t) opcode8
| opcode
<< 8;
6875 goto reswitch_prefix_add
;
6878 case 0x0f10: /* movups */
6879 case 0x660f10: /* movupd */
6880 case 0xf30f10: /* movss */
6881 case 0xf20f10: /* movsd */
6882 case 0x0f12: /* movlps */
6883 case 0x660f12: /* movlpd */
6884 case 0xf30f12: /* movsldup */
6885 case 0xf20f12: /* movddup */
6886 case 0x0f14: /* unpcklps */
6887 case 0x660f14: /* unpcklpd */
6888 case 0x0f15: /* unpckhps */
6889 case 0x660f15: /* unpckhpd */
6890 case 0x0f16: /* movhps */
6891 case 0x660f16: /* movhpd */
6892 case 0xf30f16: /* movshdup */
6893 case 0x0f28: /* movaps */
6894 case 0x660f28: /* movapd */
6895 case 0x0f2a: /* cvtpi2ps */
6896 case 0x660f2a: /* cvtpi2pd */
6897 case 0xf30f2a: /* cvtsi2ss */
6898 case 0xf20f2a: /* cvtsi2sd */
6899 case 0x0f2c: /* cvttps2pi */
6900 case 0x660f2c: /* cvttpd2pi */
6901 case 0x0f2d: /* cvtps2pi */
6902 case 0x660f2d: /* cvtpd2pi */
6903 case 0x660f3800: /* pshufb */
6904 case 0x660f3801: /* phaddw */
6905 case 0x660f3802: /* phaddd */
6906 case 0x660f3803: /* phaddsw */
6907 case 0x660f3804: /* pmaddubsw */
6908 case 0x660f3805: /* phsubw */
6909 case 0x660f3806: /* phsubd */
6910 case 0x660f3807: /* phsubsw */
6911 case 0x660f3808: /* psignb */
6912 case 0x660f3809: /* psignw */
6913 case 0x660f380a: /* psignd */
6914 case 0x660f380b: /* pmulhrsw */
6915 case 0x660f3810: /* pblendvb */
6916 case 0x660f3814: /* blendvps */
6917 case 0x660f3815: /* blendvpd */
6918 case 0x660f381c: /* pabsb */
6919 case 0x660f381d: /* pabsw */
6920 case 0x660f381e: /* pabsd */
6921 case 0x660f3820: /* pmovsxbw */
6922 case 0x660f3821: /* pmovsxbd */
6923 case 0x660f3822: /* pmovsxbq */
6924 case 0x660f3823: /* pmovsxwd */
6925 case 0x660f3824: /* pmovsxwq */
6926 case 0x660f3825: /* pmovsxdq */
6927 case 0x660f3828: /* pmuldq */
6928 case 0x660f3829: /* pcmpeqq */
6929 case 0x660f382a: /* movntdqa */
6930 case 0x660f3a08: /* roundps */
6931 case 0x660f3a09: /* roundpd */
6932 case 0x660f3a0a: /* roundss */
6933 case 0x660f3a0b: /* roundsd */
6934 case 0x660f3a0c: /* blendps */
6935 case 0x660f3a0d: /* blendpd */
6936 case 0x660f3a0e: /* pblendw */
6937 case 0x660f3a0f: /* palignr */
6938 case 0x660f3a20: /* pinsrb */
6939 case 0x660f3a21: /* insertps */
6940 case 0x660f3a22: /* pinsrd pinsrq */
6941 case 0x660f3a40: /* dpps */
6942 case 0x660f3a41: /* dppd */
6943 case 0x660f3a42: /* mpsadbw */
6944 case 0x660f3a60: /* pcmpestrm */
6945 case 0x660f3a61: /* pcmpestri */
6946 case 0x660f3a62: /* pcmpistrm */
6947 case 0x660f3a63: /* pcmpistri */
6948 case 0x0f51: /* sqrtps */
6949 case 0x660f51: /* sqrtpd */
6950 case 0xf20f51: /* sqrtsd */
6951 case 0xf30f51: /* sqrtss */
6952 case 0x0f52: /* rsqrtps */
6953 case 0xf30f52: /* rsqrtss */
6954 case 0x0f53: /* rcpps */
6955 case 0xf30f53: /* rcpss */
6956 case 0x0f54: /* andps */
6957 case 0x660f54: /* andpd */
6958 case 0x0f55: /* andnps */
6959 case 0x660f55: /* andnpd */
6960 case 0x0f56: /* orps */
6961 case 0x660f56: /* orpd */
6962 case 0x0f57: /* xorps */
6963 case 0x660f57: /* xorpd */
6964 case 0x0f58: /* addps */
6965 case 0x660f58: /* addpd */
6966 case 0xf20f58: /* addsd */
6967 case 0xf30f58: /* addss */
6968 case 0x0f59: /* mulps */
6969 case 0x660f59: /* mulpd */
6970 case 0xf20f59: /* mulsd */
6971 case 0xf30f59: /* mulss */
6972 case 0x0f5a: /* cvtps2pd */
6973 case 0x660f5a: /* cvtpd2ps */
6974 case 0xf20f5a: /* cvtsd2ss */
6975 case 0xf30f5a: /* cvtss2sd */
6976 case 0x0f5b: /* cvtdq2ps */
6977 case 0x660f5b: /* cvtps2dq */
6978 case 0xf30f5b: /* cvttps2dq */
6979 case 0x0f5c: /* subps */
6980 case 0x660f5c: /* subpd */
6981 case 0xf20f5c: /* subsd */
6982 case 0xf30f5c: /* subss */
6983 case 0x0f5d: /* minps */
6984 case 0x660f5d: /* minpd */
6985 case 0xf20f5d: /* minsd */
6986 case 0xf30f5d: /* minss */
6987 case 0x0f5e: /* divps */
6988 case 0x660f5e: /* divpd */
6989 case 0xf20f5e: /* divsd */
6990 case 0xf30f5e: /* divss */
6991 case 0x0f5f: /* maxps */
6992 case 0x660f5f: /* maxpd */
6993 case 0xf20f5f: /* maxsd */
6994 case 0xf30f5f: /* maxss */
6995 case 0x660f60: /* punpcklbw */
6996 case 0x660f61: /* punpcklwd */
6997 case 0x660f62: /* punpckldq */
6998 case 0x660f63: /* packsswb */
6999 case 0x660f64: /* pcmpgtb */
7000 case 0x660f65: /* pcmpgtw */
7001 case 0x660f66: /* pcmpgtd */
7002 case 0x660f67: /* packuswb */
7003 case 0x660f68: /* punpckhbw */
7004 case 0x660f69: /* punpckhwd */
7005 case 0x660f6a: /* punpckhdq */
7006 case 0x660f6b: /* packssdw */
7007 case 0x660f6c: /* punpcklqdq */
7008 case 0x660f6d: /* punpckhqdq */
7009 case 0x660f6e: /* movd */
7010 case 0x660f6f: /* movdqa */
7011 case 0xf30f6f: /* movdqu */
7012 case 0x660f70: /* pshufd */
7013 case 0xf20f70: /* pshuflw */
7014 case 0xf30f70: /* pshufhw */
7015 case 0x660f74: /* pcmpeqb */
7016 case 0x660f75: /* pcmpeqw */
7017 case 0x660f76: /* pcmpeqd */
7018 case 0x660f7c: /* haddpd */
7019 case 0xf20f7c: /* haddps */
7020 case 0x660f7d: /* hsubpd */
7021 case 0xf20f7d: /* hsubps */
7022 case 0xf30f7e: /* movq */
7023 case 0x0fc2: /* cmpps */
7024 case 0x660fc2: /* cmppd */
7025 case 0xf20fc2: /* cmpsd */
7026 case 0xf30fc2: /* cmpss */
7027 case 0x660fc4: /* pinsrw */
7028 case 0x0fc6: /* shufps */
7029 case 0x660fc6: /* shufpd */
7030 case 0x660fd0: /* addsubpd */
7031 case 0xf20fd0: /* addsubps */
7032 case 0x660fd1: /* psrlw */
7033 case 0x660fd2: /* psrld */
7034 case 0x660fd3: /* psrlq */
7035 case 0x660fd4: /* paddq */
7036 case 0x660fd5: /* pmullw */
7037 case 0xf30fd6: /* movq2dq */
7038 case 0x660fd8: /* psubusb */
7039 case 0x660fd9: /* psubusw */
7040 case 0x660fda: /* pminub */
7041 case 0x660fdb: /* pand */
7042 case 0x660fdc: /* paddusb */
7043 case 0x660fdd: /* paddusw */
7044 case 0x660fde: /* pmaxub */
7045 case 0x660fdf: /* pandn */
7046 case 0x660fe0: /* pavgb */
7047 case 0x660fe1: /* psraw */
7048 case 0x660fe2: /* psrad */
7049 case 0x660fe3: /* pavgw */
7050 case 0x660fe4: /* pmulhuw */
7051 case 0x660fe5: /* pmulhw */
7052 case 0x660fe6: /* cvttpd2dq */
7053 case 0xf20fe6: /* cvtpd2dq */
7054 case 0xf30fe6: /* cvtdq2pd */
7055 case 0x660fe8: /* psubsb */
7056 case 0x660fe9: /* psubsw */
7057 case 0x660fea: /* pminsw */
7058 case 0x660feb: /* por */
7059 case 0x660fec: /* paddsb */
7060 case 0x660fed: /* paddsw */
7061 case 0x660fee: /* pmaxsw */
7062 case 0x660fef: /* pxor */
7063 case 0xf20ff0: /* lddqu */
7064 case 0x660ff1: /* psllw */
7065 case 0x660ff2: /* pslld */
7066 case 0x660ff3: /* psllq */
7067 case 0x660ff4: /* pmuludq */
7068 case 0x660ff5: /* pmaddwd */
7069 case 0x660ff6: /* psadbw */
7070 case 0x660ff8: /* psubb */
7071 case 0x660ff9: /* psubw */
7072 case 0x660ffa: /* psubd */
7073 case 0x660ffb: /* psubq */
7074 case 0x660ffc: /* paddb */
7075 case 0x660ffd: /* paddw */
7076 case 0x660ffe: /* paddd */
7077 if (i386_record_modrm (&ir
))
7080 if (!i386_xmm_regnum_p (gdbarch
, I387_XMM0_REGNUM (tdep
) + ir
.reg
))
7082 record_arch_list_add_reg (ir
.regcache
,
7083 I387_XMM0_REGNUM (tdep
) + ir
.reg
);
7084 if ((opcode
& 0xfffffffc) == 0x660f3a60)
7085 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7088 case 0x0f11: /* movups */
7089 case 0x660f11: /* movupd */
7090 case 0xf30f11: /* movss */
7091 case 0xf20f11: /* movsd */
7092 case 0x0f13: /* movlps */
7093 case 0x660f13: /* movlpd */
7094 case 0x0f17: /* movhps */
7095 case 0x660f17: /* movhpd */
7096 case 0x0f29: /* movaps */
7097 case 0x660f29: /* movapd */
7098 case 0x660f3a14: /* pextrb */
7099 case 0x660f3a15: /* pextrw */
7100 case 0x660f3a16: /* pextrd pextrq */
7101 case 0x660f3a17: /* extractps */
7102 case 0x660f7f: /* movdqa */
7103 case 0xf30f7f: /* movdqu */
7104 if (i386_record_modrm (&ir
))
7108 if (opcode
== 0x0f13 || opcode
== 0x660f13
7109 || opcode
== 0x0f17 || opcode
== 0x660f17)
7112 if (!i386_xmm_regnum_p (gdbarch
,
7113 I387_XMM0_REGNUM (tdep
) + ir
.rm
))
7115 record_arch_list_add_reg (ir
.regcache
,
7116 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
7138 if (i386_record_lea_modrm (&ir
))
7143 case 0x0f2b: /* movntps */
7144 case 0x660f2b: /* movntpd */
7145 case 0x0fe7: /* movntq */
7146 case 0x660fe7: /* movntdq */
7149 if (opcode
== 0x0fe7)
7153 if (i386_record_lea_modrm (&ir
))
7157 case 0xf30f2c: /* cvttss2si */
7158 case 0xf20f2c: /* cvttsd2si */
7159 case 0xf30f2d: /* cvtss2si */
7160 case 0xf20f2d: /* cvtsd2si */
7161 case 0xf20f38f0: /* crc32 */
7162 case 0xf20f38f1: /* crc32 */
7163 case 0x0f50: /* movmskps */
7164 case 0x660f50: /* movmskpd */
7165 case 0x0fc5: /* pextrw */
7166 case 0x660fc5: /* pextrw */
7167 case 0x0fd7: /* pmovmskb */
7168 case 0x660fd7: /* pmovmskb */
7169 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
7172 case 0x0f3800: /* pshufb */
7173 case 0x0f3801: /* phaddw */
7174 case 0x0f3802: /* phaddd */
7175 case 0x0f3803: /* phaddsw */
7176 case 0x0f3804: /* pmaddubsw */
7177 case 0x0f3805: /* phsubw */
7178 case 0x0f3806: /* phsubd */
7179 case 0x0f3807: /* phsubsw */
7180 case 0x0f3808: /* psignb */
7181 case 0x0f3809: /* psignw */
7182 case 0x0f380a: /* psignd */
7183 case 0x0f380b: /* pmulhrsw */
7184 case 0x0f381c: /* pabsb */
7185 case 0x0f381d: /* pabsw */
7186 case 0x0f381e: /* pabsd */
7187 case 0x0f382b: /* packusdw */
7188 case 0x0f3830: /* pmovzxbw */
7189 case 0x0f3831: /* pmovzxbd */
7190 case 0x0f3832: /* pmovzxbq */
7191 case 0x0f3833: /* pmovzxwd */
7192 case 0x0f3834: /* pmovzxwq */
7193 case 0x0f3835: /* pmovzxdq */
7194 case 0x0f3837: /* pcmpgtq */
7195 case 0x0f3838: /* pminsb */
7196 case 0x0f3839: /* pminsd */
7197 case 0x0f383a: /* pminuw */
7198 case 0x0f383b: /* pminud */
7199 case 0x0f383c: /* pmaxsb */
7200 case 0x0f383d: /* pmaxsd */
7201 case 0x0f383e: /* pmaxuw */
7202 case 0x0f383f: /* pmaxud */
7203 case 0x0f3840: /* pmulld */
7204 case 0x0f3841: /* phminposuw */
7205 case 0x0f3a0f: /* palignr */
7206 case 0x0f60: /* punpcklbw */
7207 case 0x0f61: /* punpcklwd */
7208 case 0x0f62: /* punpckldq */
7209 case 0x0f63: /* packsswb */
7210 case 0x0f64: /* pcmpgtb */
7211 case 0x0f65: /* pcmpgtw */
7212 case 0x0f66: /* pcmpgtd */
7213 case 0x0f67: /* packuswb */
7214 case 0x0f68: /* punpckhbw */
7215 case 0x0f69: /* punpckhwd */
7216 case 0x0f6a: /* punpckhdq */
7217 case 0x0f6b: /* packssdw */
7218 case 0x0f6e: /* movd */
7219 case 0x0f6f: /* movq */
7220 case 0x0f70: /* pshufw */
7221 case 0x0f74: /* pcmpeqb */
7222 case 0x0f75: /* pcmpeqw */
7223 case 0x0f76: /* pcmpeqd */
7224 case 0x0fc4: /* pinsrw */
7225 case 0x0fd1: /* psrlw */
7226 case 0x0fd2: /* psrld */
7227 case 0x0fd3: /* psrlq */
7228 case 0x0fd4: /* paddq */
7229 case 0x0fd5: /* pmullw */
7230 case 0xf20fd6: /* movdq2q */
7231 case 0x0fd8: /* psubusb */
7232 case 0x0fd9: /* psubusw */
7233 case 0x0fda: /* pminub */
7234 case 0x0fdb: /* pand */
7235 case 0x0fdc: /* paddusb */
7236 case 0x0fdd: /* paddusw */
7237 case 0x0fde: /* pmaxub */
7238 case 0x0fdf: /* pandn */
7239 case 0x0fe0: /* pavgb */
7240 case 0x0fe1: /* psraw */
7241 case 0x0fe2: /* psrad */
7242 case 0x0fe3: /* pavgw */
7243 case 0x0fe4: /* pmulhuw */
7244 case 0x0fe5: /* pmulhw */
7245 case 0x0fe8: /* psubsb */
7246 case 0x0fe9: /* psubsw */
7247 case 0x0fea: /* pminsw */
7248 case 0x0feb: /* por */
7249 case 0x0fec: /* paddsb */
7250 case 0x0fed: /* paddsw */
7251 case 0x0fee: /* pmaxsw */
7252 case 0x0fef: /* pxor */
7253 case 0x0ff1: /* psllw */
7254 case 0x0ff2: /* pslld */
7255 case 0x0ff3: /* psllq */
7256 case 0x0ff4: /* pmuludq */
7257 case 0x0ff5: /* pmaddwd */
7258 case 0x0ff6: /* psadbw */
7259 case 0x0ff8: /* psubb */
7260 case 0x0ff9: /* psubw */
7261 case 0x0ffa: /* psubd */
7262 case 0x0ffb: /* psubq */
7263 case 0x0ffc: /* paddb */
7264 case 0x0ffd: /* paddw */
7265 case 0x0ffe: /* paddd */
7266 if (i386_record_modrm (&ir
))
7268 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.reg
))
7270 record_arch_list_add_reg (ir
.regcache
,
7271 I387_MM0_REGNUM (tdep
) + ir
.reg
);
7274 case 0x0f71: /* psllw */
7275 case 0x0f72: /* pslld */
7276 case 0x0f73: /* psllq */
7277 if (i386_record_modrm (&ir
))
7279 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.rm
))
7281 record_arch_list_add_reg (ir
.regcache
,
7282 I387_MM0_REGNUM (tdep
) + ir
.rm
);
7285 case 0x660f71: /* psllw */
7286 case 0x660f72: /* pslld */
7287 case 0x660f73: /* psllq */
7288 if (i386_record_modrm (&ir
))
7291 if (!i386_xmm_regnum_p (gdbarch
, I387_XMM0_REGNUM (tdep
) + ir
.rm
))
7293 record_arch_list_add_reg (ir
.regcache
,
7294 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
7297 case 0x0f7e: /* movd */
7298 case 0x660f7e: /* movd */
7299 if (i386_record_modrm (&ir
))
7302 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
7309 if (i386_record_lea_modrm (&ir
))
7314 case 0x0f7f: /* movq */
7315 if (i386_record_modrm (&ir
))
7319 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.rm
))
7321 record_arch_list_add_reg (ir
.regcache
,
7322 I387_MM0_REGNUM (tdep
) + ir
.rm
);
7327 if (i386_record_lea_modrm (&ir
))
7332 case 0xf30fb8: /* popcnt */
7333 if (i386_record_modrm (&ir
))
7335 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
7336 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7339 case 0x660fd6: /* movq */
7340 if (i386_record_modrm (&ir
))
7345 if (!i386_xmm_regnum_p (gdbarch
,
7346 I387_XMM0_REGNUM (tdep
) + ir
.rm
))
7348 record_arch_list_add_reg (ir
.regcache
,
7349 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
7354 if (i386_record_lea_modrm (&ir
))
7359 case 0x660f3817: /* ptest */
7360 case 0x0f2e: /* ucomiss */
7361 case 0x660f2e: /* ucomisd */
7362 case 0x0f2f: /* comiss */
7363 case 0x660f2f: /* comisd */
7364 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7367 case 0x0ff7: /* maskmovq */
7368 regcache_raw_read_unsigned (ir
.regcache
,
7369 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
7371 if (record_arch_list_add_mem (addr
, 64))
7375 case 0x660ff7: /* maskmovdqu */
7376 regcache_raw_read_unsigned (ir
.regcache
,
7377 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
7379 if (record_arch_list_add_mem (addr
, 128))
7394 /* In the future, maybe still need to deal with need_dasm. */
7395 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM
);
7396 if (record_arch_list_add_end ())
7402 printf_unfiltered (_("Process record does not support instruction 0x%02x "
7403 "at address %s.\n"),
7404 (unsigned int) (opcode
),
7405 paddress (gdbarch
, ir
.orig_addr
));
7409 static const int i386_record_regmap
[] =
7411 I386_EAX_REGNUM
, I386_ECX_REGNUM
, I386_EDX_REGNUM
, I386_EBX_REGNUM
,
7412 I386_ESP_REGNUM
, I386_EBP_REGNUM
, I386_ESI_REGNUM
, I386_EDI_REGNUM
,
7413 0, 0, 0, 0, 0, 0, 0, 0,
7414 I386_EIP_REGNUM
, I386_EFLAGS_REGNUM
, I386_CS_REGNUM
, I386_SS_REGNUM
,
7415 I386_DS_REGNUM
, I386_ES_REGNUM
, I386_FS_REGNUM
, I386_GS_REGNUM
7418 /* Check that the given address appears suitable for a fast
7419 tracepoint, which on x86-64 means that we need an instruction of at
7420 least 5 bytes, so that we can overwrite it with a 4-byte-offset
7421 jump and not have to worry about program jumps to an address in the
7422 middle of the tracepoint jump. On x86, it may be possible to use
7423 4-byte jumps with a 2-byte offset to a trampoline located in the
7424 bottom 64 KiB of memory. Returns 1 if OK, and writes a size
7425 of instruction to replace, and 0 if not, plus an explanatory
7429 i386_fast_tracepoint_valid_at (struct gdbarch
*gdbarch
,
7430 CORE_ADDR addr
, int *isize
, char **msg
)
7433 static struct ui_file
*gdb_null
= NULL
;
7435 /* Ask the target for the minimum instruction length supported. */
7436 jumplen
= target_get_min_fast_tracepoint_insn_len ();
7440 /* If the target does not support the get_min_fast_tracepoint_insn_len
7441 operation, assume that fast tracepoints will always be implemented
7442 using 4-byte relative jumps on both x86 and x86-64. */
7445 else if (jumplen
== 0)
7447 /* If the target does support get_min_fast_tracepoint_insn_len but
7448 returns zero, then the IPA has not loaded yet. In this case,
7449 we optimistically assume that truncated 2-byte relative jumps
7450 will be available on x86, and compensate later if this assumption
7451 turns out to be incorrect. On x86-64 architectures, 4-byte relative
7452 jumps will always be used. */
7453 jumplen
= (register_size (gdbarch
, 0) == 8) ? 5 : 4;
7456 /* Dummy file descriptor for the disassembler. */
7458 gdb_null
= ui_file_new ();
7460 /* Check for fit. */
7461 len
= gdb_print_insn (gdbarch
, addr
, gdb_null
, NULL
);
7467 /* Return a bit of target-specific detail to add to the caller's
7468 generic failure message. */
7470 *msg
= xstrprintf (_("; instruction is only %d bytes long, "
7471 "need at least %d bytes for the jump"),
7484 i386_validate_tdesc_p (struct gdbarch_tdep
*tdep
,
7485 struct tdesc_arch_data
*tdesc_data
)
7487 const struct target_desc
*tdesc
= tdep
->tdesc
;
7488 const struct tdesc_feature
*feature_core
;
7489 const struct tdesc_feature
*feature_sse
, *feature_avx
;
7490 int i
, num_regs
, valid_p
;
7492 if (! tdesc_has_registers (tdesc
))
7495 /* Get core registers. */
7496 feature_core
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.core");
7497 if (feature_core
== NULL
)
7500 /* Get SSE registers. */
7501 feature_sse
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.sse");
7503 /* Try AVX registers. */
7504 feature_avx
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx");
7508 /* The XCR0 bits. */
7511 /* AVX register description requires SSE register description. */
7515 tdep
->xcr0
= I386_XSTATE_AVX_MASK
;
7517 /* It may have been set by OSABI initialization function. */
7518 if (tdep
->num_ymm_regs
== 0)
7520 tdep
->ymmh_register_names
= i386_ymmh_names
;
7521 tdep
->num_ymm_regs
= 8;
7522 tdep
->ymm0h_regnum
= I386_YMM0H_REGNUM
;
7525 for (i
= 0; i
< tdep
->num_ymm_regs
; i
++)
7526 valid_p
&= tdesc_numbered_register (feature_avx
, tdesc_data
,
7527 tdep
->ymm0h_regnum
+ i
,
7528 tdep
->ymmh_register_names
[i
]);
7530 else if (feature_sse
)
7531 tdep
->xcr0
= I386_XSTATE_SSE_MASK
;
7534 tdep
->xcr0
= I386_XSTATE_X87_MASK
;
7535 tdep
->num_xmm_regs
= 0;
7538 num_regs
= tdep
->num_core_regs
;
7539 for (i
= 0; i
< num_regs
; i
++)
7540 valid_p
&= tdesc_numbered_register (feature_core
, tdesc_data
, i
,
7541 tdep
->register_names
[i
]);
7545 /* Need to include %mxcsr, so add one. */
7546 num_regs
+= tdep
->num_xmm_regs
+ 1;
7547 for (; i
< num_regs
; i
++)
7548 valid_p
&= tdesc_numbered_register (feature_sse
, tdesc_data
, i
,
7549 tdep
->register_names
[i
]);
7556 static struct gdbarch
*
7557 i386_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
7559 struct gdbarch_tdep
*tdep
;
7560 struct gdbarch
*gdbarch
;
7561 struct tdesc_arch_data
*tdesc_data
;
7562 const struct target_desc
*tdesc
;
7566 /* If there is already a candidate, use it. */
7567 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
7569 return arches
->gdbarch
;
7571 /* Allocate space for the new architecture. */
7572 tdep
= XCALLOC (1, struct gdbarch_tdep
);
7573 gdbarch
= gdbarch_alloc (&info
, tdep
);
7575 /* General-purpose registers. */
7576 tdep
->gregset
= NULL
;
7577 tdep
->gregset_reg_offset
= NULL
;
7578 tdep
->gregset_num_regs
= I386_NUM_GREGS
;
7579 tdep
->sizeof_gregset
= 0;
7581 /* Floating-point registers. */
7582 tdep
->fpregset
= NULL
;
7583 tdep
->sizeof_fpregset
= I387_SIZEOF_FSAVE
;
7585 tdep
->xstateregset
= NULL
;
7587 /* The default settings include the FPU registers, the MMX registers
7588 and the SSE registers. This can be overridden for a specific ABI
7589 by adjusting the members `st0_regnum', `mm0_regnum' and
7590 `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers
7591 will show up in the output of "info all-registers". */
7593 tdep
->st0_regnum
= I386_ST0_REGNUM
;
7595 /* I386_NUM_XREGS includes %mxcsr, so substract one. */
7596 tdep
->num_xmm_regs
= I386_NUM_XREGS
- 1;
7598 tdep
->jb_pc_offset
= -1;
7599 tdep
->struct_return
= pcc_struct_return
;
7600 tdep
->sigtramp_start
= 0;
7601 tdep
->sigtramp_end
= 0;
7602 tdep
->sigtramp_p
= i386_sigtramp_p
;
7603 tdep
->sigcontext_addr
= NULL
;
7604 tdep
->sc_reg_offset
= NULL
;
7605 tdep
->sc_pc_offset
= -1;
7606 tdep
->sc_sp_offset
= -1;
7608 tdep
->xsave_xcr0_offset
= -1;
7610 tdep
->record_regmap
= i386_record_regmap
;
7612 set_gdbarch_long_long_align_bit (gdbarch
, 32);
7614 /* The format used for `long double' on almost all i386 targets is
7615 the i387 extended floating-point format. In fact, of all targets
7616 in the GCC 2.95 tree, only OSF/1 does it different, and insists
7617 on having a `long double' that's not `long' at all. */
7618 set_gdbarch_long_double_format (gdbarch
, floatformats_i387_ext
);
7620 /* Although the i387 extended floating-point has only 80 significant
7621 bits, a `long double' actually takes up 96, probably to enforce
7623 set_gdbarch_long_double_bit (gdbarch
, 96);
7625 /* Register numbers of various important registers. */
7626 set_gdbarch_sp_regnum (gdbarch
, I386_ESP_REGNUM
); /* %esp */
7627 set_gdbarch_pc_regnum (gdbarch
, I386_EIP_REGNUM
); /* %eip */
7628 set_gdbarch_ps_regnum (gdbarch
, I386_EFLAGS_REGNUM
); /* %eflags */
7629 set_gdbarch_fp0_regnum (gdbarch
, I386_ST0_REGNUM
); /* %st(0) */
7631 /* NOTE: kettenis/20040418: GCC does have two possible register
7632 numbering schemes on the i386: dbx and SVR4. These schemes
7633 differ in how they number %ebp, %esp, %eflags, and the
7634 floating-point registers, and are implemented by the arrays
7635 dbx_register_map[] and svr4_dbx_register_map in
7636 gcc/config/i386.c. GCC also defines a third numbering scheme in
7637 gcc/config/i386.c, which it designates as the "default" register
7638 map used in 64bit mode. This last register numbering scheme is
7639 implemented in dbx64_register_map, and is used for AMD64; see
7642 Currently, each GCC i386 target always uses the same register
7643 numbering scheme across all its supported debugging formats
7644 i.e. SDB (COFF), stabs and DWARF 2. This is because
7645 gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the
7646 DBX_REGISTER_NUMBER macro which is defined by each target's
7647 respective config header in a manner independent of the requested
7648 output debugging format.
7650 This does not match the arrangement below, which presumes that
7651 the SDB and stabs numbering schemes differ from the DWARF and
7652 DWARF 2 ones. The reason for this arrangement is that it is
7653 likely to get the numbering scheme for the target's
7654 default/native debug format right. For targets where GCC is the
7655 native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for
7656 targets where the native toolchain uses a different numbering
7657 scheme for a particular debug format (stabs-in-ELF on Solaris)
7658 the defaults below will have to be overridden, like
7659 i386_elf_init_abi() does. */
7661 /* Use the dbx register numbering scheme for stabs and COFF. */
7662 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
7663 set_gdbarch_sdb_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
7665 /* Use the SVR4 register numbering scheme for DWARF 2. */
7666 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
7668 /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to
7669 be in use on any of the supported i386 targets. */
7671 set_gdbarch_print_float_info (gdbarch
, i387_print_float_info
);
7673 set_gdbarch_get_longjmp_target (gdbarch
, i386_get_longjmp_target
);
7675 /* Call dummy code. */
7676 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
7677 set_gdbarch_push_dummy_code (gdbarch
, i386_push_dummy_code
);
7678 set_gdbarch_push_dummy_call (gdbarch
, i386_push_dummy_call
);
7679 set_gdbarch_frame_align (gdbarch
, i386_frame_align
);
7681 set_gdbarch_convert_register_p (gdbarch
, i386_convert_register_p
);
7682 set_gdbarch_register_to_value (gdbarch
, i386_register_to_value
);
7683 set_gdbarch_value_to_register (gdbarch
, i386_value_to_register
);
7685 set_gdbarch_return_value (gdbarch
, i386_return_value
);
7687 set_gdbarch_skip_prologue (gdbarch
, i386_skip_prologue
);
7689 /* Stack grows downward. */
7690 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
7692 set_gdbarch_breakpoint_from_pc (gdbarch
, i386_breakpoint_from_pc
);
7693 set_gdbarch_decr_pc_after_break (gdbarch
, 1);
7694 set_gdbarch_max_insn_length (gdbarch
, I386_MAX_INSN_LEN
);
7696 set_gdbarch_frame_args_skip (gdbarch
, 8);
7698 set_gdbarch_print_insn (gdbarch
, i386_print_insn
);
7700 set_gdbarch_dummy_id (gdbarch
, i386_dummy_id
);
7702 set_gdbarch_unwind_pc (gdbarch
, i386_unwind_pc
);
7704 /* Add the i386 register groups. */
7705 i386_add_reggroups (gdbarch
);
7706 tdep
->register_reggroup_p
= i386_register_reggroup_p
;
7708 /* Helper for function argument information. */
7709 set_gdbarch_fetch_pointer_argument (gdbarch
, i386_fetch_pointer_argument
);
7711 /* Hook the function epilogue frame unwinder. This unwinder is
7712 appended to the list first, so that it supercedes the DWARF
7713 unwinder in function epilogues (where the DWARF unwinder
7714 currently fails). */
7715 frame_unwind_append_unwinder (gdbarch
, &i386_epilogue_frame_unwind
);
7717 /* Hook in the DWARF CFI frame unwinder. This unwinder is appended
7718 to the list before the prologue-based unwinders, so that DWARF
7719 CFI info will be used if it is available. */
7720 dwarf2_append_unwinders (gdbarch
);
7722 frame_base_set_default (gdbarch
, &i386_frame_base
);
7724 /* Pseudo registers may be changed by amd64_init_abi. */
7725 set_gdbarch_pseudo_register_read_value (gdbarch
,
7726 i386_pseudo_register_read_value
);
7727 set_gdbarch_pseudo_register_write (gdbarch
, i386_pseudo_register_write
);
7729 set_tdesc_pseudo_register_type (gdbarch
, i386_pseudo_register_type
);
7730 set_tdesc_pseudo_register_name (gdbarch
, i386_pseudo_register_name
);
7732 /* Override the normal target description method to make the AVX
7733 upper halves anonymous. */
7734 set_gdbarch_register_name (gdbarch
, i386_register_name
);
7736 /* Even though the default ABI only includes general-purpose registers,
7737 floating-point registers and the SSE registers, we have to leave a
7738 gap for the upper AVX registers. */
7739 set_gdbarch_num_regs (gdbarch
, I386_AVX_NUM_REGS
);
7741 /* Get the x86 target description from INFO. */
7742 tdesc
= info
.target_desc
;
7743 if (! tdesc_has_registers (tdesc
))
7745 tdep
->tdesc
= tdesc
;
7747 tdep
->num_core_regs
= I386_NUM_GREGS
+ I387_NUM_REGS
;
7748 tdep
->register_names
= i386_register_names
;
7750 /* No upper YMM registers. */
7751 tdep
->ymmh_register_names
= NULL
;
7752 tdep
->ymm0h_regnum
= -1;
7754 tdep
->num_byte_regs
= 8;
7755 tdep
->num_word_regs
= 8;
7756 tdep
->num_dword_regs
= 0;
7757 tdep
->num_mmx_regs
= 8;
7758 tdep
->num_ymm_regs
= 0;
7760 tdesc_data
= tdesc_data_alloc ();
7762 set_gdbarch_relocate_instruction (gdbarch
, i386_relocate_instruction
);
7764 set_gdbarch_gen_return_address (gdbarch
, i386_gen_return_address
);
7766 /* Hook in ABI-specific overrides, if they have been registered. */
7767 info
.tdep_info
= (void *) tdesc_data
;
7768 gdbarch_init_osabi (info
, gdbarch
);
7770 if (!i386_validate_tdesc_p (tdep
, tdesc_data
))
7772 tdesc_data_cleanup (tdesc_data
);
7774 gdbarch_free (gdbarch
);
7778 /* Wire in pseudo registers. Number of pseudo registers may be
7780 set_gdbarch_num_pseudo_regs (gdbarch
, (tdep
->num_byte_regs
7781 + tdep
->num_word_regs
7782 + tdep
->num_dword_regs
7783 + tdep
->num_mmx_regs
7784 + tdep
->num_ymm_regs
));
7786 /* Target description may be changed. */
7787 tdesc
= tdep
->tdesc
;
7789 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
7791 /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */
7792 set_gdbarch_register_reggroup_p (gdbarch
, tdep
->register_reggroup_p
);
7794 /* Make %al the first pseudo-register. */
7795 tdep
->al_regnum
= gdbarch_num_regs (gdbarch
);
7796 tdep
->ax_regnum
= tdep
->al_regnum
+ tdep
->num_byte_regs
;
7798 ymm0_regnum
= tdep
->ax_regnum
+ tdep
->num_word_regs
;
7799 if (tdep
->num_dword_regs
)
7801 /* Support dword pseudo-register if it hasn't been disabled. */
7802 tdep
->eax_regnum
= ymm0_regnum
;
7803 ymm0_regnum
+= tdep
->num_dword_regs
;
7806 tdep
->eax_regnum
= -1;
7808 mm0_regnum
= ymm0_regnum
;
7809 if (tdep
->num_ymm_regs
)
7811 /* Support YMM pseudo-register if it is available. */
7812 tdep
->ymm0_regnum
= ymm0_regnum
;
7813 mm0_regnum
+= tdep
->num_ymm_regs
;
7816 tdep
->ymm0_regnum
= -1;
7818 if (tdep
->num_mmx_regs
!= 0)
7820 /* Support MMX pseudo-register if MMX hasn't been disabled. */
7821 tdep
->mm0_regnum
= mm0_regnum
;
7824 tdep
->mm0_regnum
= -1;
7826 /* Hook in the legacy prologue-based unwinders last (fallback). */
7827 frame_unwind_append_unwinder (gdbarch
, &i386_stack_tramp_frame_unwind
);
7828 frame_unwind_append_unwinder (gdbarch
, &i386_sigtramp_frame_unwind
);
7829 frame_unwind_append_unwinder (gdbarch
, &i386_frame_unwind
);
7831 /* If we have a register mapping, enable the generic core file
7832 support, unless it has already been enabled. */
7833 if (tdep
->gregset_reg_offset
7834 && !gdbarch_regset_from_core_section_p (gdbarch
))
7835 set_gdbarch_regset_from_core_section (gdbarch
,
7836 i386_regset_from_core_section
);
7838 set_gdbarch_skip_permanent_breakpoint (gdbarch
,
7839 i386_skip_permanent_breakpoint
);
7841 set_gdbarch_fast_tracepoint_valid_at (gdbarch
,
7842 i386_fast_tracepoint_valid_at
);
7847 static enum gdb_osabi
7848 i386_coff_osabi_sniffer (bfd
*abfd
)
7850 if (strcmp (bfd_get_target (abfd
), "coff-go32-exe") == 0
7851 || strcmp (bfd_get_target (abfd
), "coff-go32") == 0)
7852 return GDB_OSABI_GO32
;
7854 return GDB_OSABI_UNKNOWN
;
7858 /* Provide a prototype to silence -Wmissing-prototypes. */
7859 void _initialize_i386_tdep (void);
7862 _initialize_i386_tdep (void)
7864 register_gdbarch_init (bfd_arch_i386
, i386_gdbarch_init
);
7866 /* Add the variable that controls the disassembly flavor. */
7867 add_setshow_enum_cmd ("disassembly-flavor", no_class
, valid_flavors
,
7868 &disassembly_flavor
, _("\
7869 Set the disassembly flavor."), _("\
7870 Show the disassembly flavor."), _("\
7871 The valid values are \"att\" and \"intel\", and the default value is \"att\"."),
7873 NULL
, /* FIXME: i18n: */
7874 &setlist
, &showlist
);
7876 /* Add the variable that controls the convention for returning
7878 add_setshow_enum_cmd ("struct-convention", no_class
, valid_conventions
,
7879 &struct_convention
, _("\
7880 Set the convention for returning small structs."), _("\
7881 Show the convention for returning small structs."), _("\
7882 Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\
7885 NULL
, /* FIXME: i18n: */
7886 &setlist
, &showlist
);
7888 gdbarch_register_osabi_sniffer (bfd_arch_i386
, bfd_target_coff_flavour
,
7889 i386_coff_osabi_sniffer
);
7891 gdbarch_register_osabi (bfd_arch_i386
, 0, GDB_OSABI_SVR4
,
7892 i386_svr4_init_abi
);
7893 gdbarch_register_osabi (bfd_arch_i386
, 0, GDB_OSABI_GO32
,
7894 i386_go32_init_abi
);
7896 /* Initialize the i386-specific register groups. */
7897 i386_init_reggroups ();
7899 /* Initialize the standard target descriptions. */
7900 initialize_tdesc_i386 ();
7901 initialize_tdesc_i386_mmx ();
7902 initialize_tdesc_i386_avx ();
7904 /* Tell remote stub that we support XML target description. */
7905 register_remote_support_xml ("i386");