1 /* Intel 386 target-dependent stuff.
3 Copyright (C) 1988-2012 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "opcode/i386.h"
22 #include "arch-utils.h"
24 #include "dummy-frame.h"
25 #include "dwarf2-frame.h"
28 #include "frame-base.h"
29 #include "frame-unwind.h"
37 #include "reggroups.h"
46 #include "exceptions.h"
47 #include "gdb_assert.h"
48 #include "gdb_string.h"
50 #include "i386-tdep.h"
51 #include "i387-tdep.h"
52 #include "i386-xstate.h"
57 #include "features/i386/i386.c"
58 #include "features/i386/i386-avx.c"
59 #include "features/i386/i386-mmx.c"
66 static const char *i386_register_names
[] =
68 "eax", "ecx", "edx", "ebx",
69 "esp", "ebp", "esi", "edi",
70 "eip", "eflags", "cs", "ss",
71 "ds", "es", "fs", "gs",
72 "st0", "st1", "st2", "st3",
73 "st4", "st5", "st6", "st7",
74 "fctrl", "fstat", "ftag", "fiseg",
75 "fioff", "foseg", "fooff", "fop",
76 "xmm0", "xmm1", "xmm2", "xmm3",
77 "xmm4", "xmm5", "xmm6", "xmm7",
81 static const char *i386_ymm_names
[] =
83 "ymm0", "ymm1", "ymm2", "ymm3",
84 "ymm4", "ymm5", "ymm6", "ymm7",
87 static const char *i386_ymmh_names
[] =
89 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
90 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
93 /* Register names for MMX pseudo-registers. */
95 static const char *i386_mmx_names
[] =
97 "mm0", "mm1", "mm2", "mm3",
98 "mm4", "mm5", "mm6", "mm7"
101 /* Register names for byte pseudo-registers. */
103 static const char *i386_byte_names
[] =
105 "al", "cl", "dl", "bl",
106 "ah", "ch", "dh", "bh"
109 /* Register names for word pseudo-registers. */
111 static const char *i386_word_names
[] =
113 "ax", "cx", "dx", "bx",
120 i386_mmx_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
122 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
123 int mm0_regnum
= tdep
->mm0_regnum
;
128 regnum
-= mm0_regnum
;
129 return regnum
>= 0 && regnum
< tdep
->num_mmx_regs
;
135 i386_byte_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
137 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
139 regnum
-= tdep
->al_regnum
;
140 return regnum
>= 0 && regnum
< tdep
->num_byte_regs
;
146 i386_word_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
148 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
150 regnum
-= tdep
->ax_regnum
;
151 return regnum
>= 0 && regnum
< tdep
->num_word_regs
;
154 /* Dword register? */
157 i386_dword_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
159 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
160 int eax_regnum
= tdep
->eax_regnum
;
165 regnum
-= eax_regnum
;
166 return regnum
>= 0 && regnum
< tdep
->num_dword_regs
;
170 i386_ymmh_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
172 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
173 int ymm0h_regnum
= tdep
->ymm0h_regnum
;
175 if (ymm0h_regnum
< 0)
178 regnum
-= ymm0h_regnum
;
179 return regnum
>= 0 && regnum
< tdep
->num_ymm_regs
;
185 i386_ymm_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
187 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
188 int ymm0_regnum
= tdep
->ymm0_regnum
;
193 regnum
-= ymm0_regnum
;
194 return regnum
>= 0 && regnum
< tdep
->num_ymm_regs
;
200 i386_xmm_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
202 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
203 int num_xmm_regs
= I387_NUM_XMM_REGS (tdep
);
205 if (num_xmm_regs
== 0)
208 regnum
-= I387_XMM0_REGNUM (tdep
);
209 return regnum
>= 0 && regnum
< num_xmm_regs
;
213 i386_mxcsr_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
215 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
217 if (I387_NUM_XMM_REGS (tdep
) == 0)
220 return (regnum
== I387_MXCSR_REGNUM (tdep
));
226 i386_fp_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
228 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
230 if (I387_ST0_REGNUM (tdep
) < 0)
233 return (I387_ST0_REGNUM (tdep
) <= regnum
234 && regnum
< I387_FCTRL_REGNUM (tdep
));
238 i386_fpc_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
240 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
242 if (I387_ST0_REGNUM (tdep
) < 0)
245 return (I387_FCTRL_REGNUM (tdep
) <= regnum
246 && regnum
< I387_XMM0_REGNUM (tdep
));
249 /* Return the name of register REGNUM, or the empty string if it is
250 an anonymous register. */
253 i386_register_name (struct gdbarch
*gdbarch
, int regnum
)
255 /* Hide the upper YMM registers. */
256 if (i386_ymmh_regnum_p (gdbarch
, regnum
))
259 return tdesc_register_name (gdbarch
, regnum
);
262 /* Return the name of register REGNUM. */
265 i386_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
267 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
268 if (i386_mmx_regnum_p (gdbarch
, regnum
))
269 return i386_mmx_names
[regnum
- I387_MM0_REGNUM (tdep
)];
270 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
271 return i386_ymm_names
[regnum
- tdep
->ymm0_regnum
];
272 else if (i386_byte_regnum_p (gdbarch
, regnum
))
273 return i386_byte_names
[regnum
- tdep
->al_regnum
];
274 else if (i386_word_regnum_p (gdbarch
, regnum
))
275 return i386_word_names
[regnum
- tdep
->ax_regnum
];
277 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
280 /* Convert a dbx register number REG to the appropriate register
281 number used by GDB. */
284 i386_dbx_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
286 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
288 /* This implements what GCC calls the "default" register map
289 (dbx_register_map[]). */
291 if (reg
>= 0 && reg
<= 7)
293 /* General-purpose registers. The debug info calls %ebp
294 register 4, and %esp register 5. */
301 else if (reg
>= 12 && reg
<= 19)
303 /* Floating-point registers. */
304 return reg
- 12 + I387_ST0_REGNUM (tdep
);
306 else if (reg
>= 21 && reg
<= 28)
309 int ymm0_regnum
= tdep
->ymm0_regnum
;
312 && i386_xmm_regnum_p (gdbarch
, reg
))
313 return reg
- 21 + ymm0_regnum
;
315 return reg
- 21 + I387_XMM0_REGNUM (tdep
);
317 else if (reg
>= 29 && reg
<= 36)
320 return reg
- 29 + I387_MM0_REGNUM (tdep
);
323 /* This will hopefully provoke a warning. */
324 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
327 /* Convert SVR4 register number REG to the appropriate register number
331 i386_svr4_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
333 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
335 /* This implements the GCC register map that tries to be compatible
336 with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */
338 /* The SVR4 register numbering includes %eip and %eflags, and
339 numbers the floating point registers differently. */
340 if (reg
>= 0 && reg
<= 9)
342 /* General-purpose registers. */
345 else if (reg
>= 11 && reg
<= 18)
347 /* Floating-point registers. */
348 return reg
- 11 + I387_ST0_REGNUM (tdep
);
350 else if (reg
>= 21 && reg
<= 36)
352 /* The SSE and MMX registers have the same numbers as with dbx. */
353 return i386_dbx_reg_to_regnum (gdbarch
, reg
);
358 case 37: return I387_FCTRL_REGNUM (tdep
);
359 case 38: return I387_FSTAT_REGNUM (tdep
);
360 case 39: return I387_MXCSR_REGNUM (tdep
);
361 case 40: return I386_ES_REGNUM
;
362 case 41: return I386_CS_REGNUM
;
363 case 42: return I386_SS_REGNUM
;
364 case 43: return I386_DS_REGNUM
;
365 case 44: return I386_FS_REGNUM
;
366 case 45: return I386_GS_REGNUM
;
369 /* This will hopefully provoke a warning. */
370 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
375 /* This is the variable that is set with "set disassembly-flavor", and
376 its legitimate values. */
377 static const char att_flavor
[] = "att";
378 static const char intel_flavor
[] = "intel";
379 static const char *const valid_flavors
[] =
385 static const char *disassembly_flavor
= att_flavor
;
388 /* Use the program counter to determine the contents and size of a
389 breakpoint instruction. Return a pointer to a string of bytes that
390 encode a breakpoint instruction, store the length of the string in
391 *LEN and optionally adjust *PC to point to the correct memory
392 location for inserting the breakpoint.
394 On the i386 we have a single breakpoint that fits in a single byte
395 and can be inserted anywhere.
397 This function is 64-bit safe. */
399 static const gdb_byte
*
400 i386_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pc
, int *len
)
402 static gdb_byte break_insn
[] = { 0xcc }; /* int 3 */
404 *len
= sizeof (break_insn
);
408 /* Displaced instruction handling. */
410 /* Skip the legacy instruction prefixes in INSN.
411 Not all prefixes are valid for any particular insn
412 but we needn't care, the insn will fault if it's invalid.
413 The result is a pointer to the first opcode byte,
414 or NULL if we run off the end of the buffer. */
417 i386_skip_prefixes (gdb_byte
*insn
, size_t max_len
)
419 gdb_byte
*end
= insn
+ max_len
;
425 case DATA_PREFIX_OPCODE
:
426 case ADDR_PREFIX_OPCODE
:
427 case CS_PREFIX_OPCODE
:
428 case DS_PREFIX_OPCODE
:
429 case ES_PREFIX_OPCODE
:
430 case FS_PREFIX_OPCODE
:
431 case GS_PREFIX_OPCODE
:
432 case SS_PREFIX_OPCODE
:
433 case LOCK_PREFIX_OPCODE
:
434 case REPE_PREFIX_OPCODE
:
435 case REPNE_PREFIX_OPCODE
:
447 i386_absolute_jmp_p (const gdb_byte
*insn
)
449 /* jmp far (absolute address in operand). */
455 /* jump near, absolute indirect (/4). */
456 if ((insn
[1] & 0x38) == 0x20)
459 /* jump far, absolute indirect (/5). */
460 if ((insn
[1] & 0x38) == 0x28)
468 i386_absolute_call_p (const gdb_byte
*insn
)
470 /* call far, absolute. */
476 /* Call near, absolute indirect (/2). */
477 if ((insn
[1] & 0x38) == 0x10)
480 /* Call far, absolute indirect (/3). */
481 if ((insn
[1] & 0x38) == 0x18)
489 i386_ret_p (const gdb_byte
*insn
)
493 case 0xc2: /* ret near, pop N bytes. */
494 case 0xc3: /* ret near */
495 case 0xca: /* ret far, pop N bytes. */
496 case 0xcb: /* ret far */
497 case 0xcf: /* iret */
506 i386_call_p (const gdb_byte
*insn
)
508 if (i386_absolute_call_p (insn
))
511 /* call near, relative. */
518 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
519 length in bytes. Otherwise, return zero. */
522 i386_syscall_p (const gdb_byte
*insn
, int *lengthp
)
533 /* Some kernels may run one past a syscall insn, so we have to cope.
534 Otherwise this is just simple_displaced_step_copy_insn. */
536 struct displaced_step_closure
*
537 i386_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
538 CORE_ADDR from
, CORE_ADDR to
,
539 struct regcache
*regs
)
541 size_t len
= gdbarch_max_insn_length (gdbarch
);
542 gdb_byte
*buf
= xmalloc (len
);
544 read_memory (from
, buf
, len
);
546 /* GDB may get control back after the insn after the syscall.
547 Presumably this is a kernel bug.
548 If this is a syscall, make sure there's a nop afterwards. */
553 insn
= i386_skip_prefixes (buf
, len
);
554 if (insn
!= NULL
&& i386_syscall_p (insn
, &syscall_length
))
555 insn
[syscall_length
] = NOP_OPCODE
;
558 write_memory (to
, buf
, len
);
562 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
563 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
564 displaced_step_dump_bytes (gdb_stdlog
, buf
, len
);
567 return (struct displaced_step_closure
*) buf
;
570 /* Fix up the state of registers and memory after having single-stepped
571 a displaced instruction. */
574 i386_displaced_step_fixup (struct gdbarch
*gdbarch
,
575 struct displaced_step_closure
*closure
,
576 CORE_ADDR from
, CORE_ADDR to
,
577 struct regcache
*regs
)
579 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
581 /* The offset we applied to the instruction's address.
582 This could well be negative (when viewed as a signed 32-bit
583 value), but ULONGEST won't reflect that, so take care when
585 ULONGEST insn_offset
= to
- from
;
587 /* Since we use simple_displaced_step_copy_insn, our closure is a
588 copy of the instruction. */
589 gdb_byte
*insn
= (gdb_byte
*) closure
;
590 /* The start of the insn, needed in case we see some prefixes. */
591 gdb_byte
*insn_start
= insn
;
594 fprintf_unfiltered (gdb_stdlog
,
595 "displaced: fixup (%s, %s), "
596 "insn = 0x%02x 0x%02x ...\n",
597 paddress (gdbarch
, from
), paddress (gdbarch
, to
),
600 /* The list of issues to contend with here is taken from
601 resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20.
602 Yay for Free Software! */
604 /* Relocate the %eip, if necessary. */
606 /* The instruction recognizers we use assume any leading prefixes
607 have been skipped. */
609 /* This is the size of the buffer in closure. */
610 size_t max_insn_len
= gdbarch_max_insn_length (gdbarch
);
611 gdb_byte
*opcode
= i386_skip_prefixes (insn
, max_insn_len
);
612 /* If there are too many prefixes, just ignore the insn.
613 It will fault when run. */
618 /* Except in the case of absolute or indirect jump or call
619 instructions, or a return instruction, the new eip is relative to
620 the displaced instruction; make it relative. Well, signal
621 handler returns don't need relocation either, but we use the
622 value of %eip to recognize those; see below. */
623 if (! i386_absolute_jmp_p (insn
)
624 && ! i386_absolute_call_p (insn
)
625 && ! i386_ret_p (insn
))
630 regcache_cooked_read_unsigned (regs
, I386_EIP_REGNUM
, &orig_eip
);
632 /* A signal trampoline system call changes the %eip, resuming
633 execution of the main program after the signal handler has
634 returned. That makes them like 'return' instructions; we
635 shouldn't relocate %eip.
637 But most system calls don't, and we do need to relocate %eip.
639 Our heuristic for distinguishing these cases: if stepping
640 over the system call instruction left control directly after
641 the instruction, the we relocate --- control almost certainly
642 doesn't belong in the displaced copy. Otherwise, we assume
643 the instruction has put control where it belongs, and leave
644 it unrelocated. Goodness help us if there are PC-relative
646 if (i386_syscall_p (insn
, &insn_len
)
647 && orig_eip
!= to
+ (insn
- insn_start
) + insn_len
648 /* GDB can get control back after the insn after the syscall.
649 Presumably this is a kernel bug.
650 i386_displaced_step_copy_insn ensures its a nop,
651 we add one to the length for it. */
652 && orig_eip
!= to
+ (insn
- insn_start
) + insn_len
+ 1)
655 fprintf_unfiltered (gdb_stdlog
,
656 "displaced: syscall changed %%eip; "
661 ULONGEST eip
= (orig_eip
- insn_offset
) & 0xffffffffUL
;
663 /* If we just stepped over a breakpoint insn, we don't backup
664 the pc on purpose; this is to match behaviour without
667 regcache_cooked_write_unsigned (regs
, I386_EIP_REGNUM
, eip
);
670 fprintf_unfiltered (gdb_stdlog
,
672 "relocated %%eip from %s to %s\n",
673 paddress (gdbarch
, orig_eip
),
674 paddress (gdbarch
, eip
));
678 /* If the instruction was PUSHFL, then the TF bit will be set in the
679 pushed value, and should be cleared. We'll leave this for later,
680 since GDB already messes up the TF flag when stepping over a
683 /* If the instruction was a call, the return address now atop the
684 stack is the address following the copied instruction. We need
685 to make it the address following the original instruction. */
686 if (i386_call_p (insn
))
690 const ULONGEST retaddr_len
= 4;
692 regcache_cooked_read_unsigned (regs
, I386_ESP_REGNUM
, &esp
);
693 retaddr
= read_memory_unsigned_integer (esp
, retaddr_len
, byte_order
);
694 retaddr
= (retaddr
- insn_offset
) & 0xffffffffUL
;
695 write_memory_unsigned_integer (esp
, retaddr_len
, byte_order
, retaddr
);
698 fprintf_unfiltered (gdb_stdlog
,
699 "displaced: relocated return addr at %s to %s\n",
700 paddress (gdbarch
, esp
),
701 paddress (gdbarch
, retaddr
));
706 append_insns (CORE_ADDR
*to
, ULONGEST len
, const gdb_byte
*buf
)
708 target_write_memory (*to
, buf
, len
);
713 i386_relocate_instruction (struct gdbarch
*gdbarch
,
714 CORE_ADDR
*to
, CORE_ADDR oldloc
)
716 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
717 gdb_byte buf
[I386_MAX_INSN_LEN
];
718 int offset
= 0, rel32
, newrel
;
720 gdb_byte
*insn
= buf
;
722 read_memory (oldloc
, buf
, I386_MAX_INSN_LEN
);
724 insn_length
= gdb_buffered_insn_length (gdbarch
, insn
,
725 I386_MAX_INSN_LEN
, oldloc
);
727 /* Get past the prefixes. */
728 insn
= i386_skip_prefixes (insn
, I386_MAX_INSN_LEN
);
730 /* Adjust calls with 32-bit relative addresses as push/jump, with
731 the address pushed being the location where the original call in
732 the user program would return to. */
735 gdb_byte push_buf
[16];
736 unsigned int ret_addr
;
738 /* Where "ret" in the original code will return to. */
739 ret_addr
= oldloc
+ insn_length
;
740 push_buf
[0] = 0x68; /* pushq $... */
741 memcpy (&push_buf
[1], &ret_addr
, 4);
743 append_insns (to
, 5, push_buf
);
745 /* Convert the relative call to a relative jump. */
748 /* Adjust the destination offset. */
749 rel32
= extract_signed_integer (insn
+ 1, 4, byte_order
);
750 newrel
= (oldloc
- *to
) + rel32
;
751 store_signed_integer (insn
+ 1, 4, byte_order
, newrel
);
754 fprintf_unfiltered (gdb_stdlog
,
755 "Adjusted insn rel32=%s at %s to"
757 hex_string (rel32
), paddress (gdbarch
, oldloc
),
758 hex_string (newrel
), paddress (gdbarch
, *to
));
760 /* Write the adjusted jump into its displaced location. */
761 append_insns (to
, 5, insn
);
765 /* Adjust jumps with 32-bit relative addresses. Calls are already
769 /* Adjust conditional jumps. */
770 else if (insn
[0] == 0x0f && (insn
[1] & 0xf0) == 0x80)
775 rel32
= extract_signed_integer (insn
+ offset
, 4, byte_order
);
776 newrel
= (oldloc
- *to
) + rel32
;
777 store_signed_integer (insn
+ offset
, 4, byte_order
, newrel
);
779 fprintf_unfiltered (gdb_stdlog
,
780 "Adjusted insn rel32=%s at %s to"
782 hex_string (rel32
), paddress (gdbarch
, oldloc
),
783 hex_string (newrel
), paddress (gdbarch
, *to
));
786 /* Write the adjusted instructions into their displaced
788 append_insns (to
, insn_length
, buf
);
792 #ifdef I386_REGNO_TO_SYMMETRY
793 #error "The Sequent Symmetry is no longer supported."
796 /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi
797 and %esp "belong" to the calling function. Therefore these
798 registers should be saved if they're going to be modified. */
800 /* The maximum number of saved registers. This should include all
801 registers mentioned above, and %eip. */
802 #define I386_NUM_SAVED_REGS I386_NUM_GREGS
804 struct i386_frame_cache
812 /* Saved registers. */
813 CORE_ADDR saved_regs
[I386_NUM_SAVED_REGS
];
818 /* Stack space reserved for local variables. */
822 /* Allocate and initialize a frame cache. */
824 static struct i386_frame_cache
*
825 i386_alloc_frame_cache (void)
827 struct i386_frame_cache
*cache
;
830 cache
= FRAME_OBSTACK_ZALLOC (struct i386_frame_cache
);
835 cache
->sp_offset
= -4;
838 /* Saved registers. We initialize these to -1 since zero is a valid
839 offset (that's where %ebp is supposed to be stored). */
840 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
841 cache
->saved_regs
[i
] = -1;
843 cache
->saved_sp_reg
= -1;
844 cache
->pc_in_eax
= 0;
846 /* Frameless until proven otherwise. */
852 /* If the instruction at PC is a jump, return the address of its
853 target. Otherwise, return PC. */
856 i386_follow_jump (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
858 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
863 if (target_read_memory (pc
, &op
, 1))
869 op
= read_memory_unsigned_integer (pc
+ 1, 1, byte_order
);
875 /* Relative jump: if data16 == 0, disp32, else disp16. */
878 delta
= read_memory_integer (pc
+ 2, 2, byte_order
);
880 /* Include the size of the jmp instruction (including the
886 delta
= read_memory_integer (pc
+ 1, 4, byte_order
);
888 /* Include the size of the jmp instruction. */
893 /* Relative jump, disp8 (ignore data16). */
894 delta
= read_memory_integer (pc
+ data16
+ 1, 1, byte_order
);
903 /* Check whether PC points at a prologue for a function returning a
904 structure or union. If so, it updates CACHE and returns the
905 address of the first instruction after the code sequence that
906 removes the "hidden" argument from the stack or CURRENT_PC,
907 whichever is smaller. Otherwise, return PC. */
910 i386_analyze_struct_return (CORE_ADDR pc
, CORE_ADDR current_pc
,
911 struct i386_frame_cache
*cache
)
913 /* Functions that return a structure or union start with:
916 xchgl %eax, (%esp) 0x87 0x04 0x24
917 or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00
919 (the System V compiler puts out the second `xchg' instruction,
920 and the assembler doesn't try to optimize it, so the 'sib' form
921 gets generated). This sequence is used to get the address of the
922 return buffer for a function that returns a structure. */
923 static gdb_byte proto1
[3] = { 0x87, 0x04, 0x24 };
924 static gdb_byte proto2
[4] = { 0x87, 0x44, 0x24, 0x00 };
928 if (current_pc
<= pc
)
931 if (target_read_memory (pc
, &op
, 1))
934 if (op
!= 0x58) /* popl %eax */
937 if (target_read_memory (pc
+ 1, buf
, 4))
940 if (memcmp (buf
, proto1
, 3) != 0 && memcmp (buf
, proto2
, 4) != 0)
943 if (current_pc
== pc
)
945 cache
->sp_offset
+= 4;
949 if (current_pc
== pc
+ 1)
951 cache
->pc_in_eax
= 1;
955 if (buf
[1] == proto1
[1])
962 i386_skip_probe (CORE_ADDR pc
)
964 /* A function may start with
978 if (target_read_memory (pc
, &op
, 1))
981 if (op
== 0x68 || op
== 0x6a)
985 /* Skip past the `pushl' instruction; it has either a one-byte or a
986 four-byte operand, depending on the opcode. */
992 /* Read the following 8 bytes, which should be `call _probe' (6
993 bytes) followed by `addl $4,%esp' (2 bytes). */
994 read_memory (pc
+ delta
, buf
, sizeof (buf
));
995 if (buf
[0] == 0xe8 && buf
[6] == 0xc4 && buf
[7] == 0x4)
996 pc
+= delta
+ sizeof (buf
);
1002 /* GCC 4.1 and later, can put code in the prologue to realign the
1003 stack pointer. Check whether PC points to such code, and update
1004 CACHE accordingly. Return the first instruction after the code
1005 sequence or CURRENT_PC, whichever is smaller. If we don't
1006 recognize the code, return PC. */
1009 i386_analyze_stack_align (CORE_ADDR pc
, CORE_ADDR current_pc
,
1010 struct i386_frame_cache
*cache
)
1012 /* There are 2 code sequences to re-align stack before the frame
1015 1. Use a caller-saved saved register:
1021 2. Use a callee-saved saved register:
1028 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
1030 0x83 0xe4 0xf0 andl $-16, %esp
1031 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
1036 int offset
, offset_and
;
1037 static int regnums
[8] = {
1038 I386_EAX_REGNUM
, /* %eax */
1039 I386_ECX_REGNUM
, /* %ecx */
1040 I386_EDX_REGNUM
, /* %edx */
1041 I386_EBX_REGNUM
, /* %ebx */
1042 I386_ESP_REGNUM
, /* %esp */
1043 I386_EBP_REGNUM
, /* %ebp */
1044 I386_ESI_REGNUM
, /* %esi */
1045 I386_EDI_REGNUM
/* %edi */
1048 if (target_read_memory (pc
, buf
, sizeof buf
))
1051 /* Check caller-saved saved register. The first instruction has
1052 to be "leal 4(%esp), %reg". */
1053 if (buf
[0] == 0x8d && buf
[2] == 0x24 && buf
[3] == 0x4)
1055 /* MOD must be binary 10 and R/M must be binary 100. */
1056 if ((buf
[1] & 0xc7) != 0x44)
1059 /* REG has register number. */
1060 reg
= (buf
[1] >> 3) & 7;
1065 /* Check callee-saved saved register. The first instruction
1066 has to be "pushl %reg". */
1067 if ((buf
[0] & 0xf8) != 0x50)
1073 /* The next instruction has to be "leal 8(%esp), %reg". */
1074 if (buf
[1] != 0x8d || buf
[3] != 0x24 || buf
[4] != 0x8)
1077 /* MOD must be binary 10 and R/M must be binary 100. */
1078 if ((buf
[2] & 0xc7) != 0x44)
1081 /* REG has register number. Registers in pushl and leal have to
1083 if (reg
!= ((buf
[2] >> 3) & 7))
1089 /* Rigister can't be %esp nor %ebp. */
1090 if (reg
== 4 || reg
== 5)
1093 /* The next instruction has to be "andl $-XXX, %esp". */
1094 if (buf
[offset
+ 1] != 0xe4
1095 || (buf
[offset
] != 0x81 && buf
[offset
] != 0x83))
1098 offset_and
= offset
;
1099 offset
+= buf
[offset
] == 0x81 ? 6 : 3;
1101 /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is
1102 0xfc. REG must be binary 110 and MOD must be binary 01. */
1103 if (buf
[offset
] != 0xff
1104 || buf
[offset
+ 2] != 0xfc
1105 || (buf
[offset
+ 1] & 0xf8) != 0x70)
1108 /* R/M has register. Registers in leal and pushl have to be the
1110 if (reg
!= (buf
[offset
+ 1] & 7))
1113 if (current_pc
> pc
+ offset_and
)
1114 cache
->saved_sp_reg
= regnums
[reg
];
1116 return min (pc
+ offset
+ 3, current_pc
);
1119 /* Maximum instruction length we need to handle. */
1120 #define I386_MAX_MATCHED_INSN_LEN 6
1122 /* Instruction description. */
1126 gdb_byte insn
[I386_MAX_MATCHED_INSN_LEN
];
1127 gdb_byte mask
[I386_MAX_MATCHED_INSN_LEN
];
1130 /* Return whether instruction at PC matches PATTERN. */
1133 i386_match_pattern (CORE_ADDR pc
, struct i386_insn pattern
)
1137 if (target_read_memory (pc
, &op
, 1))
1140 if ((op
& pattern
.mask
[0]) == pattern
.insn
[0])
1142 gdb_byte buf
[I386_MAX_MATCHED_INSN_LEN
- 1];
1143 int insn_matched
= 1;
1146 gdb_assert (pattern
.len
> 1);
1147 gdb_assert (pattern
.len
<= I386_MAX_MATCHED_INSN_LEN
);
1149 if (target_read_memory (pc
+ 1, buf
, pattern
.len
- 1))
1152 for (i
= 1; i
< pattern
.len
; i
++)
1154 if ((buf
[i
- 1] & pattern
.mask
[i
]) != pattern
.insn
[i
])
1157 return insn_matched
;
1162 /* Search for the instruction at PC in the list INSN_PATTERNS. Return
1163 the first instruction description that matches. Otherwise, return
1166 static struct i386_insn
*
1167 i386_match_insn (CORE_ADDR pc
, struct i386_insn
*insn_patterns
)
1169 struct i386_insn
*pattern
;
1171 for (pattern
= insn_patterns
; pattern
->len
> 0; pattern
++)
1173 if (i386_match_pattern (pc
, *pattern
))
1180 /* Return whether PC points inside a sequence of instructions that
1181 matches INSN_PATTERNS. */
1184 i386_match_insn_block (CORE_ADDR pc
, struct i386_insn
*insn_patterns
)
1186 CORE_ADDR current_pc
;
1189 struct i386_insn
*insn
;
1191 insn
= i386_match_insn (pc
, insn_patterns
);
1196 ix
= insn
- insn_patterns
;
1197 for (i
= ix
- 1; i
>= 0; i
--)
1199 current_pc
-= insn_patterns
[i
].len
;
1201 if (!i386_match_pattern (current_pc
, insn_patterns
[i
]))
1205 current_pc
= pc
+ insn
->len
;
1206 for (insn
= insn_patterns
+ ix
+ 1; insn
->len
> 0; insn
++)
1208 if (!i386_match_pattern (current_pc
, *insn
))
1211 current_pc
+= insn
->len
;
1217 /* Some special instructions that might be migrated by GCC into the
1218 part of the prologue that sets up the new stack frame. Because the
1219 stack frame hasn't been setup yet, no registers have been saved
1220 yet, and only the scratch registers %eax, %ecx and %edx can be
1223 struct i386_insn i386_frame_setup_skip_insns
[] =
1225 /* Check for `movb imm8, r' and `movl imm32, r'.
1227 ??? Should we handle 16-bit operand-sizes here? */
1229 /* `movb imm8, %al' and `movb imm8, %ah' */
1230 /* `movb imm8, %cl' and `movb imm8, %ch' */
1231 { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } },
1232 /* `movb imm8, %dl' and `movb imm8, %dh' */
1233 { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } },
1234 /* `movl imm32, %eax' and `movl imm32, %ecx' */
1235 { 5, { 0xb8 }, { 0xfe } },
1236 /* `movl imm32, %edx' */
1237 { 5, { 0xba }, { 0xff } },
1239 /* Check for `mov imm32, r32'. Note that there is an alternative
1240 encoding for `mov m32, %eax'.
1242 ??? Should we handle SIB adressing here?
1243 ??? Should we handle 16-bit operand-sizes here? */
1245 /* `movl m32, %eax' */
1246 { 5, { 0xa1 }, { 0xff } },
1247 /* `movl m32, %eax' and `mov; m32, %ecx' */
1248 { 6, { 0x89, 0x05 }, {0xff, 0xf7 } },
1249 /* `movl m32, %edx' */
1250 { 6, { 0x89, 0x15 }, {0xff, 0xff } },
1252 /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'.
1253 Because of the symmetry, there are actually two ways to encode
1254 these instructions; opcode bytes 0x29 and 0x2b for `subl' and
1255 opcode bytes 0x31 and 0x33 for `xorl'. */
1257 /* `subl %eax, %eax' */
1258 { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } },
1259 /* `subl %ecx, %ecx' */
1260 { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } },
1261 /* `subl %edx, %edx' */
1262 { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } },
1263 /* `xorl %eax, %eax' */
1264 { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } },
1265 /* `xorl %ecx, %ecx' */
1266 { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } },
1267 /* `xorl %edx, %edx' */
1268 { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } },
1273 /* Check whether PC points to a no-op instruction. */
1275 i386_skip_noop (CORE_ADDR pc
)
1280 if (target_read_memory (pc
, &op
, 1))
1286 /* Ignore `nop' instruction. */
1290 if (target_read_memory (pc
, &op
, 1))
1294 /* Ignore no-op instruction `mov %edi, %edi'.
1295 Microsoft system dlls often start with
1296 a `mov %edi,%edi' instruction.
1297 The 5 bytes before the function start are
1298 filled with `nop' instructions.
1299 This pattern can be used for hot-patching:
1300 The `mov %edi, %edi' instruction can be replaced by a
1301 near jump to the location of the 5 `nop' instructions
1302 which can be replaced by a 32-bit jump to anywhere
1303 in the 32-bit address space. */
1305 else if (op
== 0x8b)
1307 if (target_read_memory (pc
+ 1, &op
, 1))
1313 if (target_read_memory (pc
, &op
, 1))
1323 /* Check whether PC points at a code that sets up a new stack frame.
1324 If so, it updates CACHE and returns the address of the first
1325 instruction after the sequence that sets up the frame or LIMIT,
1326 whichever is smaller. If we don't recognize the code, return PC. */
1329 i386_analyze_frame_setup (struct gdbarch
*gdbarch
,
1330 CORE_ADDR pc
, CORE_ADDR limit
,
1331 struct i386_frame_cache
*cache
)
1333 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1334 struct i386_insn
*insn
;
1341 if (target_read_memory (pc
, &op
, 1))
1344 if (op
== 0x55) /* pushl %ebp */
1346 /* Take into account that we've executed the `pushl %ebp' that
1347 starts this instruction sequence. */
1348 cache
->saved_regs
[I386_EBP_REGNUM
] = 0;
1349 cache
->sp_offset
+= 4;
1352 /* If that's all, return now. */
1356 /* Check for some special instructions that might be migrated by
1357 GCC into the prologue and skip them. At this point in the
1358 prologue, code should only touch the scratch registers %eax,
1359 %ecx and %edx, so while the number of posibilities is sheer,
1362 Make sure we only skip these instructions if we later see the
1363 `movl %esp, %ebp' that actually sets up the frame. */
1364 while (pc
+ skip
< limit
)
1366 insn
= i386_match_insn (pc
+ skip
, i386_frame_setup_skip_insns
);
1373 /* If that's all, return now. */
1374 if (limit
<= pc
+ skip
)
1377 if (target_read_memory (pc
+ skip
, &op
, 1))
1380 /* Check for `movl %esp, %ebp' -- can be written in two ways. */
1384 if (read_memory_unsigned_integer (pc
+ skip
+ 1, 1, byte_order
)
1389 if (read_memory_unsigned_integer (pc
+ skip
+ 1, 1, byte_order
)
1397 /* OK, we actually have a frame. We just don't know how large
1398 it is yet. Set its size to zero. We'll adjust it if
1399 necessary. We also now commit to skipping the special
1400 instructions mentioned before. */
1404 /* If that's all, return now. */
1408 /* Check for stack adjustment
1412 NOTE: You can't subtract a 16-bit immediate from a 32-bit
1413 reg, so we don't have to worry about a data16 prefix. */
1414 if (target_read_memory (pc
, &op
, 1))
1418 /* `subl' with 8-bit immediate. */
1419 if (read_memory_unsigned_integer (pc
+ 1, 1, byte_order
) != 0xec)
1420 /* Some instruction starting with 0x83 other than `subl'. */
1423 /* `subl' with signed 8-bit immediate (though it wouldn't
1424 make sense to be negative). */
1425 cache
->locals
= read_memory_integer (pc
+ 2, 1, byte_order
);
1428 else if (op
== 0x81)
1430 /* Maybe it is `subl' with a 32-bit immediate. */
1431 if (read_memory_unsigned_integer (pc
+ 1, 1, byte_order
) != 0xec)
1432 /* Some instruction starting with 0x81 other than `subl'. */
1435 /* It is `subl' with a 32-bit immediate. */
1436 cache
->locals
= read_memory_integer (pc
+ 2, 4, byte_order
);
1441 /* Some instruction other than `subl'. */
1445 else if (op
== 0xc8) /* enter */
1447 cache
->locals
= read_memory_unsigned_integer (pc
+ 1, 2, byte_order
);
1454 /* Check whether PC points at code that saves registers on the stack.
1455 If so, it updates CACHE and returns the address of the first
1456 instruction after the register saves or CURRENT_PC, whichever is
1457 smaller. Otherwise, return PC. */
1460 i386_analyze_register_saves (CORE_ADDR pc
, CORE_ADDR current_pc
,
1461 struct i386_frame_cache
*cache
)
1463 CORE_ADDR offset
= 0;
1467 if (cache
->locals
> 0)
1468 offset
-= cache
->locals
;
1469 for (i
= 0; i
< 8 && pc
< current_pc
; i
++)
1471 if (target_read_memory (pc
, &op
, 1))
1473 if (op
< 0x50 || op
> 0x57)
1477 cache
->saved_regs
[op
- 0x50] = offset
;
1478 cache
->sp_offset
+= 4;
1485 /* Do a full analysis of the prologue at PC and update CACHE
1486 accordingly. Bail out early if CURRENT_PC is reached. Return the
1487 address where the analysis stopped.
1489 We handle these cases:
1491 The startup sequence can be at the start of the function, or the
1492 function can start with a branch to startup code at the end.
1494 %ebp can be set up with either the 'enter' instruction, or "pushl
1495 %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was
1496 once used in the System V compiler).
1498 Local space is allocated just below the saved %ebp by either the
1499 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a
1500 16-bit unsigned argument for space to allocate, and the 'addl'
1501 instruction could have either a signed byte, or 32-bit immediate.
1503 Next, the registers used by this function are pushed. With the
1504 System V compiler they will always be in the order: %edi, %esi,
1505 %ebx (and sometimes a harmless bug causes it to also save but not
1506 restore %eax); however, the code below is willing to see the pushes
1507 in any order, and will handle up to 8 of them.
1509 If the setup sequence is at the end of the function, then the next
1510 instruction will be a branch back to the start. */
1513 i386_analyze_prologue (struct gdbarch
*gdbarch
,
1514 CORE_ADDR pc
, CORE_ADDR current_pc
,
1515 struct i386_frame_cache
*cache
)
1517 pc
= i386_skip_noop (pc
);
1518 pc
= i386_follow_jump (gdbarch
, pc
);
1519 pc
= i386_analyze_struct_return (pc
, current_pc
, cache
);
1520 pc
= i386_skip_probe (pc
);
1521 pc
= i386_analyze_stack_align (pc
, current_pc
, cache
);
1522 pc
= i386_analyze_frame_setup (gdbarch
, pc
, current_pc
, cache
);
1523 return i386_analyze_register_saves (pc
, current_pc
, cache
);
1526 /* Return PC of first real instruction. */
1529 i386_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
1531 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1533 static gdb_byte pic_pat
[6] =
1535 0xe8, 0, 0, 0, 0, /* call 0x0 */
1536 0x5b, /* popl %ebx */
1538 struct i386_frame_cache cache
;
1544 pc
= i386_analyze_prologue (gdbarch
, start_pc
, 0xffffffff, &cache
);
1545 if (cache
.locals
< 0)
1548 /* Found valid frame setup. */
1550 /* The native cc on SVR4 in -K PIC mode inserts the following code
1551 to get the address of the global offset table (GOT) into register
1556 movl %ebx,x(%ebp) (optional)
1559 This code is with the rest of the prologue (at the end of the
1560 function), so we have to skip it to get to the first real
1561 instruction at the start of the function. */
1563 for (i
= 0; i
< 6; i
++)
1565 if (target_read_memory (pc
+ i
, &op
, 1))
1568 if (pic_pat
[i
] != op
)
1575 if (target_read_memory (pc
+ delta
, &op
, 1))
1578 if (op
== 0x89) /* movl %ebx, x(%ebp) */
1580 op
= read_memory_unsigned_integer (pc
+ delta
+ 1, 1, byte_order
);
1582 if (op
== 0x5d) /* One byte offset from %ebp. */
1584 else if (op
== 0x9d) /* Four byte offset from %ebp. */
1586 else /* Unexpected instruction. */
1589 if (target_read_memory (pc
+ delta
, &op
, 1))
1594 if (delta
> 0 && op
== 0x81
1595 && read_memory_unsigned_integer (pc
+ delta
+ 1, 1, byte_order
)
1602 /* If the function starts with a branch (to startup code at the end)
1603 the last instruction should bring us back to the first
1604 instruction of the real code. */
1605 if (i386_follow_jump (gdbarch
, start_pc
) != start_pc
)
1606 pc
= i386_follow_jump (gdbarch
, pc
);
1611 /* Check that the code pointed to by PC corresponds to a call to
1612 __main, skip it if so. Return PC otherwise. */
1615 i386_skip_main_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1617 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1620 if (target_read_memory (pc
, &op
, 1))
1626 if (target_read_memory (pc
+ 1, buf
, sizeof buf
) == 0)
1628 /* Make sure address is computed correctly as a 32bit
1629 integer even if CORE_ADDR is 64 bit wide. */
1630 struct minimal_symbol
*s
;
1631 CORE_ADDR call_dest
;
1633 call_dest
= pc
+ 5 + extract_signed_integer (buf
, 4, byte_order
);
1634 call_dest
= call_dest
& 0xffffffffU
;
1635 s
= lookup_minimal_symbol_by_pc (call_dest
);
1637 && SYMBOL_LINKAGE_NAME (s
) != NULL
1638 && strcmp (SYMBOL_LINKAGE_NAME (s
), "__main") == 0)
1646 /* This function is 64-bit safe. */
1649 i386_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1653 frame_unwind_register (next_frame
, gdbarch_pc_regnum (gdbarch
), buf
);
1654 return extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
1658 /* Normal frames. */
1661 i386_frame_cache_1 (struct frame_info
*this_frame
,
1662 struct i386_frame_cache
*cache
)
1664 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1665 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1669 cache
->pc
= get_frame_func (this_frame
);
1671 /* In principle, for normal frames, %ebp holds the frame pointer,
1672 which holds the base address for the current stack frame.
1673 However, for functions that don't need it, the frame pointer is
1674 optional. For these "frameless" functions the frame pointer is
1675 actually the frame pointer of the calling frame. Signal
1676 trampolines are just a special case of a "frameless" function.
1677 They (usually) share their frame pointer with the frame that was
1678 in progress when the signal occurred. */
1680 get_frame_register (this_frame
, I386_EBP_REGNUM
, buf
);
1681 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
);
1682 if (cache
->base
== 0)
1688 /* For normal frames, %eip is stored at 4(%ebp). */
1689 cache
->saved_regs
[I386_EIP_REGNUM
] = 4;
1692 i386_analyze_prologue (gdbarch
, cache
->pc
, get_frame_pc (this_frame
),
1695 if (cache
->locals
< 0)
1697 /* We didn't find a valid frame, which means that CACHE->base
1698 currently holds the frame pointer for our calling frame. If
1699 we're at the start of a function, or somewhere half-way its
1700 prologue, the function's frame probably hasn't been fully
1701 setup yet. Try to reconstruct the base address for the stack
1702 frame by looking at the stack pointer. For truly "frameless"
1703 functions this might work too. */
1705 if (cache
->saved_sp_reg
!= -1)
1707 /* Saved stack pointer has been saved. */
1708 get_frame_register (this_frame
, cache
->saved_sp_reg
, buf
);
1709 cache
->saved_sp
= extract_unsigned_integer (buf
, 4, byte_order
);
1711 /* We're halfway aligning the stack. */
1712 cache
->base
= ((cache
->saved_sp
- 4) & 0xfffffff0) - 4;
1713 cache
->saved_regs
[I386_EIP_REGNUM
] = cache
->saved_sp
- 4;
1715 /* This will be added back below. */
1716 cache
->saved_regs
[I386_EIP_REGNUM
] -= cache
->base
;
1718 else if (cache
->pc
!= 0
1719 || target_read_memory (get_frame_pc (this_frame
), buf
, 1))
1721 /* We're in a known function, but did not find a frame
1722 setup. Assume that the function does not use %ebp.
1723 Alternatively, we may have jumped to an invalid
1724 address; in that case there is definitely no new
1726 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
1727 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
)
1731 /* We're in an unknown function. We could not find the start
1732 of the function to analyze the prologue; our best option is
1733 to assume a typical frame layout with the caller's %ebp
1735 cache
->saved_regs
[I386_EBP_REGNUM
] = 0;
1738 if (cache
->saved_sp_reg
!= -1)
1740 /* Saved stack pointer has been saved (but the SAVED_SP_REG
1741 register may be unavailable). */
1742 if (cache
->saved_sp
== 0
1743 && frame_register_read (this_frame
, cache
->saved_sp_reg
, buf
))
1744 cache
->saved_sp
= extract_unsigned_integer (buf
, 4, byte_order
);
1746 /* Now that we have the base address for the stack frame we can
1747 calculate the value of %esp in the calling frame. */
1748 else if (cache
->saved_sp
== 0)
1749 cache
->saved_sp
= cache
->base
+ 8;
1751 /* Adjust all the saved registers such that they contain addresses
1752 instead of offsets. */
1753 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
1754 if (cache
->saved_regs
[i
] != -1)
1755 cache
->saved_regs
[i
] += cache
->base
;
1760 static struct i386_frame_cache
*
1761 i386_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1763 volatile struct gdb_exception ex
;
1764 struct i386_frame_cache
*cache
;
1769 cache
= i386_alloc_frame_cache ();
1770 *this_cache
= cache
;
1772 TRY_CATCH (ex
, RETURN_MASK_ERROR
)
1774 i386_frame_cache_1 (this_frame
, cache
);
1776 if (ex
.reason
< 0 && ex
.error
!= NOT_AVAILABLE_ERROR
)
1777 throw_exception (ex
);
1783 i386_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
1784 struct frame_id
*this_id
)
1786 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1788 /* This marks the outermost frame. */
1789 if (cache
->base
== 0)
1792 /* See the end of i386_push_dummy_call. */
1793 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
1796 static enum unwind_stop_reason
1797 i386_frame_unwind_stop_reason (struct frame_info
*this_frame
,
1800 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1803 return UNWIND_UNAVAILABLE
;
1805 /* This marks the outermost frame. */
1806 if (cache
->base
== 0)
1807 return UNWIND_OUTERMOST
;
1809 return UNWIND_NO_REASON
;
1812 static struct value
*
1813 i386_frame_prev_register (struct frame_info
*this_frame
, void **this_cache
,
1816 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1818 gdb_assert (regnum
>= 0);
1820 /* The System V ABI says that:
1822 "The flags register contains the system flags, such as the
1823 direction flag and the carry flag. The direction flag must be
1824 set to the forward (that is, zero) direction before entry and
1825 upon exit from a function. Other user flags have no specified
1826 role in the standard calling sequence and are not preserved."
1828 To guarantee the "upon exit" part of that statement we fake a
1829 saved flags register that has its direction flag cleared.
1831 Note that GCC doesn't seem to rely on the fact that the direction
1832 flag is cleared after a function return; it always explicitly
1833 clears the flag before operations where it matters.
1835 FIXME: kettenis/20030316: I'm not quite sure whether this is the
1836 right thing to do. The way we fake the flags register here makes
1837 it impossible to change it. */
1839 if (regnum
== I386_EFLAGS_REGNUM
)
1843 val
= get_frame_register_unsigned (this_frame
, regnum
);
1845 return frame_unwind_got_constant (this_frame
, regnum
, val
);
1848 if (regnum
== I386_EIP_REGNUM
&& cache
->pc_in_eax
)
1849 return frame_unwind_got_register (this_frame
, regnum
, I386_EAX_REGNUM
);
1851 if (regnum
== I386_ESP_REGNUM
1852 && (cache
->saved_sp
!= 0 || cache
->saved_sp_reg
!= -1))
1854 /* If the SP has been saved, but we don't know where, then this
1855 means that SAVED_SP_REG register was found unavailable back
1856 when we built the cache. */
1857 if (cache
->saved_sp
== 0)
1858 return frame_unwind_got_register (this_frame
, regnum
,
1859 cache
->saved_sp_reg
);
1861 return frame_unwind_got_constant (this_frame
, regnum
,
1865 if (regnum
< I386_NUM_SAVED_REGS
&& cache
->saved_regs
[regnum
] != -1)
1866 return frame_unwind_got_memory (this_frame
, regnum
,
1867 cache
->saved_regs
[regnum
]);
1869 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
1872 static const struct frame_unwind i386_frame_unwind
=
1875 i386_frame_unwind_stop_reason
,
1877 i386_frame_prev_register
,
1879 default_frame_sniffer
1882 /* Normal frames, but in a function epilogue. */
1884 /* The epilogue is defined here as the 'ret' instruction, which will
1885 follow any instruction such as 'leave' or 'pop %ebp' that destroys
1886 the function's stack frame. */
1889 i386_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1892 struct symtab
*symtab
;
1894 symtab
= find_pc_symtab (pc
);
1895 if (symtab
&& symtab
->epilogue_unwind_valid
)
1898 if (target_read_memory (pc
, &insn
, 1))
1899 return 0; /* Can't read memory at pc. */
1901 if (insn
!= 0xc3) /* 'ret' instruction. */
1908 i386_epilogue_frame_sniffer (const struct frame_unwind
*self
,
1909 struct frame_info
*this_frame
,
1910 void **this_prologue_cache
)
1912 if (frame_relative_level (this_frame
) == 0)
1913 return i386_in_function_epilogue_p (get_frame_arch (this_frame
),
1914 get_frame_pc (this_frame
));
1919 static struct i386_frame_cache
*
1920 i386_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1922 volatile struct gdb_exception ex
;
1923 struct i386_frame_cache
*cache
;
1929 cache
= i386_alloc_frame_cache ();
1930 *this_cache
= cache
;
1932 TRY_CATCH (ex
, RETURN_MASK_ERROR
)
1934 cache
->pc
= get_frame_func (this_frame
);
1936 /* At this point the stack looks as if we just entered the
1937 function, with the return address at the top of the
1939 sp
= get_frame_register_unsigned (this_frame
, I386_ESP_REGNUM
);
1940 cache
->base
= sp
+ cache
->sp_offset
;
1941 cache
->saved_sp
= cache
->base
+ 8;
1942 cache
->saved_regs
[I386_EIP_REGNUM
] = cache
->base
+ 4;
1946 if (ex
.reason
< 0 && ex
.error
!= NOT_AVAILABLE_ERROR
)
1947 throw_exception (ex
);
1952 static enum unwind_stop_reason
1953 i386_epilogue_frame_unwind_stop_reason (struct frame_info
*this_frame
,
1956 struct i386_frame_cache
*cache
=
1957 i386_epilogue_frame_cache (this_frame
, this_cache
);
1960 return UNWIND_UNAVAILABLE
;
1962 return UNWIND_NO_REASON
;
1966 i386_epilogue_frame_this_id (struct frame_info
*this_frame
,
1968 struct frame_id
*this_id
)
1970 struct i386_frame_cache
*cache
=
1971 i386_epilogue_frame_cache (this_frame
, this_cache
);
1976 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
1979 static struct value
*
1980 i386_epilogue_frame_prev_register (struct frame_info
*this_frame
,
1981 void **this_cache
, int regnum
)
1983 /* Make sure we've initialized the cache. */
1984 i386_epilogue_frame_cache (this_frame
, this_cache
);
1986 return i386_frame_prev_register (this_frame
, this_cache
, regnum
);
1989 static const struct frame_unwind i386_epilogue_frame_unwind
=
1992 i386_epilogue_frame_unwind_stop_reason
,
1993 i386_epilogue_frame_this_id
,
1994 i386_epilogue_frame_prev_register
,
1996 i386_epilogue_frame_sniffer
2000 /* Stack-based trampolines. */
2002 /* These trampolines are used on cross x86 targets, when taking the
2003 address of a nested function. When executing these trampolines,
2004 no stack frame is set up, so we are in a similar situation as in
2005 epilogues and i386_epilogue_frame_this_id can be re-used. */
2007 /* Static chain passed in register. */
2009 struct i386_insn i386_tramp_chain_in_reg_insns
[] =
2011 /* `movl imm32, %eax' and `movl imm32, %ecx' */
2012 { 5, { 0xb8 }, { 0xfe } },
2015 { 5, { 0xe9 }, { 0xff } },
2020 /* Static chain passed on stack (when regparm=3). */
2022 struct i386_insn i386_tramp_chain_on_stack_insns
[] =
2025 { 5, { 0x68 }, { 0xff } },
2028 { 5, { 0xe9 }, { 0xff } },
2033 /* Return whether PC points inside a stack trampoline. */
2036 i386_in_stack_tramp_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2041 /* A stack trampoline is detected if no name is associated
2042 to the current pc and if it points inside a trampoline
2045 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
2049 if (target_read_memory (pc
, &insn
, 1))
2052 if (!i386_match_insn_block (pc
, i386_tramp_chain_in_reg_insns
)
2053 && !i386_match_insn_block (pc
, i386_tramp_chain_on_stack_insns
))
2060 i386_stack_tramp_frame_sniffer (const struct frame_unwind
*self
,
2061 struct frame_info
*this_frame
,
2064 if (frame_relative_level (this_frame
) == 0)
2065 return i386_in_stack_tramp_p (get_frame_arch (this_frame
),
2066 get_frame_pc (this_frame
));
2071 static const struct frame_unwind i386_stack_tramp_frame_unwind
=
2074 i386_epilogue_frame_unwind_stop_reason
,
2075 i386_epilogue_frame_this_id
,
2076 i386_epilogue_frame_prev_register
,
2078 i386_stack_tramp_frame_sniffer
2081 /* Generate a bytecode expression to get the value of the saved PC. */
2084 i386_gen_return_address (struct gdbarch
*gdbarch
,
2085 struct agent_expr
*ax
, struct axs_value
*value
,
2088 /* The following sequence assumes the traditional use of the base
2090 ax_reg (ax
, I386_EBP_REGNUM
);
2092 ax_simple (ax
, aop_add
);
2093 value
->type
= register_type (gdbarch
, I386_EIP_REGNUM
);
2094 value
->kind
= axs_lvalue_memory
;
2098 /* Signal trampolines. */
2100 static struct i386_frame_cache
*
2101 i386_sigtramp_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2103 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2104 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2105 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2106 volatile struct gdb_exception ex
;
2107 struct i386_frame_cache
*cache
;
2114 cache
= i386_alloc_frame_cache ();
2116 TRY_CATCH (ex
, RETURN_MASK_ERROR
)
2118 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
2119 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
) - 4;
2121 addr
= tdep
->sigcontext_addr (this_frame
);
2122 if (tdep
->sc_reg_offset
)
2126 gdb_assert (tdep
->sc_num_regs
<= I386_NUM_SAVED_REGS
);
2128 for (i
= 0; i
< tdep
->sc_num_regs
; i
++)
2129 if (tdep
->sc_reg_offset
[i
] != -1)
2130 cache
->saved_regs
[i
] = addr
+ tdep
->sc_reg_offset
[i
];
2134 cache
->saved_regs
[I386_EIP_REGNUM
] = addr
+ tdep
->sc_pc_offset
;
2135 cache
->saved_regs
[I386_ESP_REGNUM
] = addr
+ tdep
->sc_sp_offset
;
2140 if (ex
.reason
< 0 && ex
.error
!= NOT_AVAILABLE_ERROR
)
2141 throw_exception (ex
);
2143 *this_cache
= cache
;
2147 static enum unwind_stop_reason
2148 i386_sigtramp_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2151 struct i386_frame_cache
*cache
=
2152 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2155 return UNWIND_UNAVAILABLE
;
2157 return UNWIND_NO_REASON
;
2161 i386_sigtramp_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2162 struct frame_id
*this_id
)
2164 struct i386_frame_cache
*cache
=
2165 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2170 /* See the end of i386_push_dummy_call. */
2171 (*this_id
) = frame_id_build (cache
->base
+ 8, get_frame_pc (this_frame
));
2174 static struct value
*
2175 i386_sigtramp_frame_prev_register (struct frame_info
*this_frame
,
2176 void **this_cache
, int regnum
)
2178 /* Make sure we've initialized the cache. */
2179 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2181 return i386_frame_prev_register (this_frame
, this_cache
, regnum
);
2185 i386_sigtramp_frame_sniffer (const struct frame_unwind
*self
,
2186 struct frame_info
*this_frame
,
2187 void **this_prologue_cache
)
2189 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (this_frame
));
2191 /* We shouldn't even bother if we don't have a sigcontext_addr
2193 if (tdep
->sigcontext_addr
== NULL
)
2196 if (tdep
->sigtramp_p
!= NULL
)
2198 if (tdep
->sigtramp_p (this_frame
))
2202 if (tdep
->sigtramp_start
!= 0)
2204 CORE_ADDR pc
= get_frame_pc (this_frame
);
2206 gdb_assert (tdep
->sigtramp_end
!= 0);
2207 if (pc
>= tdep
->sigtramp_start
&& pc
< tdep
->sigtramp_end
)
2214 static const struct frame_unwind i386_sigtramp_frame_unwind
=
2217 i386_sigtramp_frame_unwind_stop_reason
,
2218 i386_sigtramp_frame_this_id
,
2219 i386_sigtramp_frame_prev_register
,
2221 i386_sigtramp_frame_sniffer
2226 i386_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
2228 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
2233 static const struct frame_base i386_frame_base
=
2236 i386_frame_base_address
,
2237 i386_frame_base_address
,
2238 i386_frame_base_address
2241 static struct frame_id
2242 i386_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
2246 fp
= get_frame_register_unsigned (this_frame
, I386_EBP_REGNUM
);
2248 /* See the end of i386_push_dummy_call. */
2249 return frame_id_build (fp
+ 8, get_frame_pc (this_frame
));
2252 /* _Decimal128 function return values need 16-byte alignment on the
2256 i386_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
2258 return sp
& -(CORE_ADDR
)16;
2262 /* Figure out where the longjmp will land. Slurp the args out of the
2263 stack. We expect the first arg to be a pointer to the jmp_buf
2264 structure from which we extract the address that we will land at.
2265 This address is copied into PC. This routine returns non-zero on
2269 i386_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
2272 CORE_ADDR sp
, jb_addr
;
2273 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2274 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2275 int jb_pc_offset
= gdbarch_tdep (gdbarch
)->jb_pc_offset
;
2277 /* If JB_PC_OFFSET is -1, we have no way to find out where the
2278 longjmp will land. */
2279 if (jb_pc_offset
== -1)
2282 get_frame_register (frame
, I386_ESP_REGNUM
, buf
);
2283 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
2284 if (target_read_memory (sp
+ 4, buf
, 4))
2287 jb_addr
= extract_unsigned_integer (buf
, 4, byte_order
);
2288 if (target_read_memory (jb_addr
+ jb_pc_offset
, buf
, 4))
2291 *pc
= extract_unsigned_integer (buf
, 4, byte_order
);
2296 /* Check whether TYPE must be 16-byte-aligned when passed as a
2297 function argument. 16-byte vectors, _Decimal128 and structures or
2298 unions containing such types must be 16-byte-aligned; other
2299 arguments are 4-byte-aligned. */
2302 i386_16_byte_align_p (struct type
*type
)
2304 type
= check_typedef (type
);
2305 if ((TYPE_CODE (type
) == TYPE_CODE_DECFLOAT
2306 || (TYPE_CODE (type
) == TYPE_CODE_ARRAY
&& TYPE_VECTOR (type
)))
2307 && TYPE_LENGTH (type
) == 16)
2309 if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
2310 return i386_16_byte_align_p (TYPE_TARGET_TYPE (type
));
2311 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
2312 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
2315 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
2317 if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type
, i
)))
2325 i386_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2326 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
2327 struct value
**args
, CORE_ADDR sp
, int struct_return
,
2328 CORE_ADDR struct_addr
)
2330 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2336 /* Determine the total space required for arguments and struct
2337 return address in a first pass (allowing for 16-byte-aligned
2338 arguments), then push arguments in a second pass. */
2340 for (write_pass
= 0; write_pass
< 2; write_pass
++)
2342 int args_space_used
= 0;
2343 int have_16_byte_aligned_arg
= 0;
2349 /* Push value address. */
2350 store_unsigned_integer (buf
, 4, byte_order
, struct_addr
);
2351 write_memory (sp
, buf
, 4);
2352 args_space_used
+= 4;
2358 for (i
= 0; i
< nargs
; i
++)
2360 int len
= TYPE_LENGTH (value_enclosing_type (args
[i
]));
2364 if (i386_16_byte_align_p (value_enclosing_type (args
[i
])))
2365 args_space_used
= align_up (args_space_used
, 16);
2367 write_memory (sp
+ args_space_used
,
2368 value_contents_all (args
[i
]), len
);
2369 /* The System V ABI says that:
2371 "An argument's size is increased, if necessary, to make it a
2372 multiple of [32-bit] words. This may require tail padding,
2373 depending on the size of the argument."
2375 This makes sure the stack stays word-aligned. */
2376 args_space_used
+= align_up (len
, 4);
2380 if (i386_16_byte_align_p (value_enclosing_type (args
[i
])))
2382 args_space
= align_up (args_space
, 16);
2383 have_16_byte_aligned_arg
= 1;
2385 args_space
+= align_up (len
, 4);
2391 if (have_16_byte_aligned_arg
)
2392 args_space
= align_up (args_space
, 16);
2397 /* Store return address. */
2399 store_unsigned_integer (buf
, 4, byte_order
, bp_addr
);
2400 write_memory (sp
, buf
, 4);
2402 /* Finally, update the stack pointer... */
2403 store_unsigned_integer (buf
, 4, byte_order
, sp
);
2404 regcache_cooked_write (regcache
, I386_ESP_REGNUM
, buf
);
2406 /* ...and fake a frame pointer. */
2407 regcache_cooked_write (regcache
, I386_EBP_REGNUM
, buf
);
2409 /* MarkK wrote: This "+ 8" is all over the place:
2410 (i386_frame_this_id, i386_sigtramp_frame_this_id,
2411 i386_dummy_id). It's there, since all frame unwinders for
2412 a given target have to agree (within a certain margin) on the
2413 definition of the stack address of a frame. Otherwise frame id
2414 comparison might not work correctly. Since DWARF2/GCC uses the
2415 stack address *before* the function call as a frame's CFA. On
2416 the i386, when %ebp is used as a frame pointer, the offset
2417 between the contents %ebp and the CFA as defined by GCC. */
2421 /* These registers are used for returning integers (and on some
2422 targets also for returning `struct' and `union' values when their
2423 size and alignment match an integer type). */
2424 #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */
2425 #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */
2427 /* Read, for architecture GDBARCH, a function return value of TYPE
2428 from REGCACHE, and copy that into VALBUF. */
2431 i386_extract_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
2432 struct regcache
*regcache
, gdb_byte
*valbuf
)
2434 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2435 int len
= TYPE_LENGTH (type
);
2436 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
2438 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2440 if (tdep
->st0_regnum
< 0)
2442 warning (_("Cannot find floating-point return value."));
2443 memset (valbuf
, 0, len
);
2447 /* Floating-point return values can be found in %st(0). Convert
2448 its contents to the desired type. This is probably not
2449 exactly how it would happen on the target itself, but it is
2450 the best we can do. */
2451 regcache_raw_read (regcache
, I386_ST0_REGNUM
, buf
);
2452 convert_typed_floating (buf
, i387_ext_type (gdbarch
), valbuf
, type
);
2456 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
2457 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
2459 if (len
<= low_size
)
2461 regcache_raw_read (regcache
, LOW_RETURN_REGNUM
, buf
);
2462 memcpy (valbuf
, buf
, len
);
2464 else if (len
<= (low_size
+ high_size
))
2466 regcache_raw_read (regcache
, LOW_RETURN_REGNUM
, buf
);
2467 memcpy (valbuf
, buf
, low_size
);
2468 regcache_raw_read (regcache
, HIGH_RETURN_REGNUM
, buf
);
2469 memcpy (valbuf
+ low_size
, buf
, len
- low_size
);
2472 internal_error (__FILE__
, __LINE__
,
2473 _("Cannot extract return value of %d bytes long."),
2478 /* Write, for architecture GDBARCH, a function return value of TYPE
2479 from VALBUF into REGCACHE. */
2482 i386_store_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
2483 struct regcache
*regcache
, const gdb_byte
*valbuf
)
2485 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2486 int len
= TYPE_LENGTH (type
);
2488 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2491 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
2493 if (tdep
->st0_regnum
< 0)
2495 warning (_("Cannot set floating-point return value."));
2499 /* Returning floating-point values is a bit tricky. Apart from
2500 storing the return value in %st(0), we have to simulate the
2501 state of the FPU at function return point. */
2503 /* Convert the value found in VALBUF to the extended
2504 floating-point format used by the FPU. This is probably
2505 not exactly how it would happen on the target itself, but
2506 it is the best we can do. */
2507 convert_typed_floating (valbuf
, type
, buf
, i387_ext_type (gdbarch
));
2508 regcache_raw_write (regcache
, I386_ST0_REGNUM
, buf
);
2510 /* Set the top of the floating-point register stack to 7. The
2511 actual value doesn't really matter, but 7 is what a normal
2512 function return would end up with if the program started out
2513 with a freshly initialized FPU. */
2514 regcache_raw_read_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), &fstat
);
2516 regcache_raw_write_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), fstat
);
2518 /* Mark %st(1) through %st(7) as empty. Since we set the top of
2519 the floating-point register stack to 7, the appropriate value
2520 for the tag word is 0x3fff. */
2521 regcache_raw_write_unsigned (regcache
, I387_FTAG_REGNUM (tdep
), 0x3fff);
2525 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
2526 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
2528 if (len
<= low_size
)
2529 regcache_raw_write_part (regcache
, LOW_RETURN_REGNUM
, 0, len
, valbuf
);
2530 else if (len
<= (low_size
+ high_size
))
2532 regcache_raw_write (regcache
, LOW_RETURN_REGNUM
, valbuf
);
2533 regcache_raw_write_part (regcache
, HIGH_RETURN_REGNUM
, 0,
2534 len
- low_size
, valbuf
+ low_size
);
2537 internal_error (__FILE__
, __LINE__
,
2538 _("Cannot store return value of %d bytes long."), len
);
2543 /* This is the variable that is set with "set struct-convention", and
2544 its legitimate values. */
2545 static const char default_struct_convention
[] = "default";
2546 static const char pcc_struct_convention
[] = "pcc";
2547 static const char reg_struct_convention
[] = "reg";
2548 static const char *const valid_conventions
[] =
2550 default_struct_convention
,
2551 pcc_struct_convention
,
2552 reg_struct_convention
,
2555 static const char *struct_convention
= default_struct_convention
;
2557 /* Return non-zero if TYPE, which is assumed to be a structure,
2558 a union type, or an array type, should be returned in registers
2559 for architecture GDBARCH. */
2562 i386_reg_struct_return_p (struct gdbarch
*gdbarch
, struct type
*type
)
2564 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2565 enum type_code code
= TYPE_CODE (type
);
2566 int len
= TYPE_LENGTH (type
);
2568 gdb_assert (code
== TYPE_CODE_STRUCT
2569 || code
== TYPE_CODE_UNION
2570 || code
== TYPE_CODE_ARRAY
);
2572 if (struct_convention
== pcc_struct_convention
2573 || (struct_convention
== default_struct_convention
2574 && tdep
->struct_return
== pcc_struct_return
))
2577 /* Structures consisting of a single `float', `double' or 'long
2578 double' member are returned in %st(0). */
2579 if (code
== TYPE_CODE_STRUCT
&& TYPE_NFIELDS (type
) == 1)
2581 type
= check_typedef (TYPE_FIELD_TYPE (type
, 0));
2582 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2583 return (len
== 4 || len
== 8 || len
== 12);
2586 return (len
== 1 || len
== 2 || len
== 4 || len
== 8);
2589 /* Determine, for architecture GDBARCH, how a return value of TYPE
2590 should be returned. If it is supposed to be returned in registers,
2591 and READBUF is non-zero, read the appropriate value from REGCACHE,
2592 and copy it into READBUF. If WRITEBUF is non-zero, write the value
2593 from WRITEBUF into REGCACHE. */
2595 static enum return_value_convention
2596 i386_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
2597 struct type
*type
, struct regcache
*regcache
,
2598 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2600 enum type_code code
= TYPE_CODE (type
);
2602 if (((code
== TYPE_CODE_STRUCT
2603 || code
== TYPE_CODE_UNION
2604 || code
== TYPE_CODE_ARRAY
)
2605 && !i386_reg_struct_return_p (gdbarch
, type
))
2606 /* 128-bit decimal float uses the struct return convention. */
2607 || (code
== TYPE_CODE_DECFLOAT
&& TYPE_LENGTH (type
) == 16))
2609 /* The System V ABI says that:
2611 "A function that returns a structure or union also sets %eax
2612 to the value of the original address of the caller's area
2613 before it returns. Thus when the caller receives control
2614 again, the address of the returned object resides in register
2615 %eax and can be used to access the object."
2617 So the ABI guarantees that we can always find the return
2618 value just after the function has returned. */
2620 /* Note that the ABI doesn't mention functions returning arrays,
2621 which is something possible in certain languages such as Ada.
2622 In this case, the value is returned as if it was wrapped in
2623 a record, so the convention applied to records also applies
2630 regcache_raw_read_unsigned (regcache
, I386_EAX_REGNUM
, &addr
);
2631 read_memory (addr
, readbuf
, TYPE_LENGTH (type
));
2634 return RETURN_VALUE_ABI_RETURNS_ADDRESS
;
2637 /* This special case is for structures consisting of a single
2638 `float', `double' or 'long double' member. These structures are
2639 returned in %st(0). For these structures, we call ourselves
2640 recursively, changing TYPE into the type of the first member of
2641 the structure. Since that should work for all structures that
2642 have only one member, we don't bother to check the member's type
2644 if (code
== TYPE_CODE_STRUCT
&& TYPE_NFIELDS (type
) == 1)
2646 type
= check_typedef (TYPE_FIELD_TYPE (type
, 0));
2647 return i386_return_value (gdbarch
, func_type
, type
, regcache
,
2652 i386_extract_return_value (gdbarch
, type
, regcache
, readbuf
);
2654 i386_store_return_value (gdbarch
, type
, regcache
, writebuf
);
2656 return RETURN_VALUE_REGISTER_CONVENTION
;
2661 i387_ext_type (struct gdbarch
*gdbarch
)
2663 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2665 if (!tdep
->i387_ext_type
)
2667 tdep
->i387_ext_type
= tdesc_find_type (gdbarch
, "i387_ext");
2668 gdb_assert (tdep
->i387_ext_type
!= NULL
);
2671 return tdep
->i387_ext_type
;
2674 /* Construct vector type for pseudo YMM registers. We can't use
2675 tdesc_find_type since YMM isn't described in target description. */
2677 static struct type
*
2678 i386_ymm_type (struct gdbarch
*gdbarch
)
2680 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2682 if (!tdep
->i386_ymm_type
)
2684 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2686 /* The type we're building is this: */
2688 union __gdb_builtin_type_vec256i
2690 int128_t uint128
[2];
2691 int64_t v2_int64
[4];
2692 int32_t v4_int32
[8];
2693 int16_t v8_int16
[16];
2694 int8_t v16_int8
[32];
2695 double v2_double
[4];
2702 t
= arch_composite_type (gdbarch
,
2703 "__gdb_builtin_type_vec256i", TYPE_CODE_UNION
);
2704 append_composite_type_field (t
, "v8_float",
2705 init_vector_type (bt
->builtin_float
, 8));
2706 append_composite_type_field (t
, "v4_double",
2707 init_vector_type (bt
->builtin_double
, 4));
2708 append_composite_type_field (t
, "v32_int8",
2709 init_vector_type (bt
->builtin_int8
, 32));
2710 append_composite_type_field (t
, "v16_int16",
2711 init_vector_type (bt
->builtin_int16
, 16));
2712 append_composite_type_field (t
, "v8_int32",
2713 init_vector_type (bt
->builtin_int32
, 8));
2714 append_composite_type_field (t
, "v4_int64",
2715 init_vector_type (bt
->builtin_int64
, 4));
2716 append_composite_type_field (t
, "v2_int128",
2717 init_vector_type (bt
->builtin_int128
, 2));
2719 TYPE_VECTOR (t
) = 1;
2720 TYPE_NAME (t
) = "builtin_type_vec256i";
2721 tdep
->i386_ymm_type
= t
;
2724 return tdep
->i386_ymm_type
;
2727 /* Construct vector type for MMX registers. */
2728 static struct type
*
2729 i386_mmx_type (struct gdbarch
*gdbarch
)
2731 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2733 if (!tdep
->i386_mmx_type
)
2735 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2737 /* The type we're building is this: */
2739 union __gdb_builtin_type_vec64i
2742 int32_t v2_int32
[2];
2743 int16_t v4_int16
[4];
2750 t
= arch_composite_type (gdbarch
,
2751 "__gdb_builtin_type_vec64i", TYPE_CODE_UNION
);
2753 append_composite_type_field (t
, "uint64", bt
->builtin_int64
);
2754 append_composite_type_field (t
, "v2_int32",
2755 init_vector_type (bt
->builtin_int32
, 2));
2756 append_composite_type_field (t
, "v4_int16",
2757 init_vector_type (bt
->builtin_int16
, 4));
2758 append_composite_type_field (t
, "v8_int8",
2759 init_vector_type (bt
->builtin_int8
, 8));
2761 TYPE_VECTOR (t
) = 1;
2762 TYPE_NAME (t
) = "builtin_type_vec64i";
2763 tdep
->i386_mmx_type
= t
;
2766 return tdep
->i386_mmx_type
;
2769 /* Return the GDB type object for the "standard" data type of data in
2772 static struct type
*
2773 i386_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
2775 if (i386_mmx_regnum_p (gdbarch
, regnum
))
2776 return i386_mmx_type (gdbarch
);
2777 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
2778 return i386_ymm_type (gdbarch
);
2781 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2782 if (i386_byte_regnum_p (gdbarch
, regnum
))
2783 return bt
->builtin_int8
;
2784 else if (i386_word_regnum_p (gdbarch
, regnum
))
2785 return bt
->builtin_int16
;
2786 else if (i386_dword_regnum_p (gdbarch
, regnum
))
2787 return bt
->builtin_int32
;
2790 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
2793 /* Map a cooked register onto a raw register or memory. For the i386,
2794 the MMX registers need to be mapped onto floating point registers. */
2797 i386_mmx_regnum_to_fp_regnum (struct regcache
*regcache
, int regnum
)
2799 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_regcache_arch (regcache
));
2804 mmxreg
= regnum
- tdep
->mm0_regnum
;
2805 regcache_raw_read_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), &fstat
);
2806 tos
= (fstat
>> 11) & 0x7;
2807 fpreg
= (mmxreg
+ tos
) % 8;
2809 return (I387_ST0_REGNUM (tdep
) + fpreg
);
2812 /* A helper function for us by i386_pseudo_register_read_value and
2813 amd64_pseudo_register_read_value. It does all the work but reads
2814 the data into an already-allocated value. */
2817 i386_pseudo_register_read_into_value (struct gdbarch
*gdbarch
,
2818 struct regcache
*regcache
,
2820 struct value
*result_value
)
2822 gdb_byte raw_buf
[MAX_REGISTER_SIZE
];
2823 enum register_status status
;
2824 gdb_byte
*buf
= value_contents_raw (result_value
);
2826 if (i386_mmx_regnum_p (gdbarch
, regnum
))
2828 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
2830 /* Extract (always little endian). */
2831 status
= regcache_raw_read (regcache
, fpnum
, raw_buf
);
2832 if (status
!= REG_VALID
)
2833 mark_value_bytes_unavailable (result_value
, 0,
2834 TYPE_LENGTH (value_type (result_value
)));
2836 memcpy (buf
, raw_buf
, register_size (gdbarch
, regnum
));
2840 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2842 if (i386_ymm_regnum_p (gdbarch
, regnum
))
2844 regnum
-= tdep
->ymm0_regnum
;
2846 /* Extract (always little endian). Read lower 128bits. */
2847 status
= regcache_raw_read (regcache
,
2848 I387_XMM0_REGNUM (tdep
) + regnum
,
2850 if (status
!= REG_VALID
)
2851 mark_value_bytes_unavailable (result_value
, 0, 16);
2853 memcpy (buf
, raw_buf
, 16);
2854 /* Read upper 128bits. */
2855 status
= regcache_raw_read (regcache
,
2856 tdep
->ymm0h_regnum
+ regnum
,
2858 if (status
!= REG_VALID
)
2859 mark_value_bytes_unavailable (result_value
, 16, 32);
2861 memcpy (buf
+ 16, raw_buf
, 16);
2863 else if (i386_word_regnum_p (gdbarch
, regnum
))
2865 int gpnum
= regnum
- tdep
->ax_regnum
;
2867 /* Extract (always little endian). */
2868 status
= regcache_raw_read (regcache
, gpnum
, raw_buf
);
2869 if (status
!= REG_VALID
)
2870 mark_value_bytes_unavailable (result_value
, 0,
2871 TYPE_LENGTH (value_type (result_value
)));
2873 memcpy (buf
, raw_buf
, 2);
2875 else if (i386_byte_regnum_p (gdbarch
, regnum
))
2877 /* Check byte pseudo registers last since this function will
2878 be called from amd64_pseudo_register_read, which handles
2879 byte pseudo registers differently. */
2880 int gpnum
= regnum
- tdep
->al_regnum
;
2882 /* Extract (always little endian). We read both lower and
2884 status
= regcache_raw_read (regcache
, gpnum
% 4, raw_buf
);
2885 if (status
!= REG_VALID
)
2886 mark_value_bytes_unavailable (result_value
, 0,
2887 TYPE_LENGTH (value_type (result_value
)));
2888 else if (gpnum
>= 4)
2889 memcpy (buf
, raw_buf
+ 1, 1);
2891 memcpy (buf
, raw_buf
, 1);
2894 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
2898 static struct value
*
2899 i386_pseudo_register_read_value (struct gdbarch
*gdbarch
,
2900 struct regcache
*regcache
,
2903 struct value
*result
;
2905 result
= allocate_value (register_type (gdbarch
, regnum
));
2906 VALUE_LVAL (result
) = lval_register
;
2907 VALUE_REGNUM (result
) = regnum
;
2909 i386_pseudo_register_read_into_value (gdbarch
, regcache
, regnum
, result
);
2915 i386_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2916 int regnum
, const gdb_byte
*buf
)
2918 gdb_byte raw_buf
[MAX_REGISTER_SIZE
];
2920 if (i386_mmx_regnum_p (gdbarch
, regnum
))
2922 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
2925 regcache_raw_read (regcache
, fpnum
, raw_buf
);
2926 /* ... Modify ... (always little endian). */
2927 memcpy (raw_buf
, buf
, register_size (gdbarch
, regnum
));
2929 regcache_raw_write (regcache
, fpnum
, raw_buf
);
2933 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2935 if (i386_ymm_regnum_p (gdbarch
, regnum
))
2937 regnum
-= tdep
->ymm0_regnum
;
2939 /* ... Write lower 128bits. */
2940 regcache_raw_write (regcache
,
2941 I387_XMM0_REGNUM (tdep
) + regnum
,
2943 /* ... Write upper 128bits. */
2944 regcache_raw_write (regcache
,
2945 tdep
->ymm0h_regnum
+ regnum
,
2948 else if (i386_word_regnum_p (gdbarch
, regnum
))
2950 int gpnum
= regnum
- tdep
->ax_regnum
;
2953 regcache_raw_read (regcache
, gpnum
, raw_buf
);
2954 /* ... Modify ... (always little endian). */
2955 memcpy (raw_buf
, buf
, 2);
2957 regcache_raw_write (regcache
, gpnum
, raw_buf
);
2959 else if (i386_byte_regnum_p (gdbarch
, regnum
))
2961 /* Check byte pseudo registers last since this function will
2962 be called from amd64_pseudo_register_read, which handles
2963 byte pseudo registers differently. */
2964 int gpnum
= regnum
- tdep
->al_regnum
;
2966 /* Read ... We read both lower and upper registers. */
2967 regcache_raw_read (regcache
, gpnum
% 4, raw_buf
);
2968 /* ... Modify ... (always little endian). */
2970 memcpy (raw_buf
+ 1, buf
, 1);
2972 memcpy (raw_buf
, buf
, 1);
2974 regcache_raw_write (regcache
, gpnum
% 4, raw_buf
);
2977 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
2982 /* Return the register number of the register allocated by GCC after
2983 REGNUM, or -1 if there is no such register. */
2986 i386_next_regnum (int regnum
)
2988 /* GCC allocates the registers in the order:
2990 %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ...
2992 Since storing a variable in %esp doesn't make any sense we return
2993 -1 for %ebp and for %esp itself. */
2994 static int next_regnum
[] =
2996 I386_EDX_REGNUM
, /* Slot for %eax. */
2997 I386_EBX_REGNUM
, /* Slot for %ecx. */
2998 I386_ECX_REGNUM
, /* Slot for %edx. */
2999 I386_ESI_REGNUM
, /* Slot for %ebx. */
3000 -1, -1, /* Slots for %esp and %ebp. */
3001 I386_EDI_REGNUM
, /* Slot for %esi. */
3002 I386_EBP_REGNUM
/* Slot for %edi. */
3005 if (regnum
>= 0 && regnum
< sizeof (next_regnum
) / sizeof (next_regnum
[0]))
3006 return next_regnum
[regnum
];
3011 /* Return nonzero if a value of type TYPE stored in register REGNUM
3012 needs any special handling. */
3015 i386_convert_register_p (struct gdbarch
*gdbarch
,
3016 int regnum
, struct type
*type
)
3018 int len
= TYPE_LENGTH (type
);
3020 /* Values may be spread across multiple registers. Most debugging
3021 formats aren't expressive enough to specify the locations, so
3022 some heuristics is involved. Right now we only handle types that
3023 have a length that is a multiple of the word size, since GCC
3024 doesn't seem to put any other types into registers. */
3025 if (len
> 4 && len
% 4 == 0)
3027 int last_regnum
= regnum
;
3031 last_regnum
= i386_next_regnum (last_regnum
);
3035 if (last_regnum
!= -1)
3039 return i387_convert_register_p (gdbarch
, regnum
, type
);
3042 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
3043 return its contents in TO. */
3046 i386_register_to_value (struct frame_info
*frame
, int regnum
,
3047 struct type
*type
, gdb_byte
*to
,
3048 int *optimizedp
, int *unavailablep
)
3050 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3051 int len
= TYPE_LENGTH (type
);
3053 if (i386_fp_regnum_p (gdbarch
, regnum
))
3054 return i387_register_to_value (frame
, regnum
, type
, to
,
3055 optimizedp
, unavailablep
);
3057 /* Read a value spread across multiple registers. */
3059 gdb_assert (len
> 4 && len
% 4 == 0);
3063 gdb_assert (regnum
!= -1);
3064 gdb_assert (register_size (gdbarch
, regnum
) == 4);
3066 if (!get_frame_register_bytes (frame
, regnum
, 0,
3067 register_size (gdbarch
, regnum
),
3068 to
, optimizedp
, unavailablep
))
3071 regnum
= i386_next_regnum (regnum
);
3076 *optimizedp
= *unavailablep
= 0;
3080 /* Write the contents FROM of a value of type TYPE into register
3081 REGNUM in frame FRAME. */
3084 i386_value_to_register (struct frame_info
*frame
, int regnum
,
3085 struct type
*type
, const gdb_byte
*from
)
3087 int len
= TYPE_LENGTH (type
);
3089 if (i386_fp_regnum_p (get_frame_arch (frame
), regnum
))
3091 i387_value_to_register (frame
, regnum
, type
, from
);
3095 /* Write a value spread across multiple registers. */
3097 gdb_assert (len
> 4 && len
% 4 == 0);
3101 gdb_assert (regnum
!= -1);
3102 gdb_assert (register_size (get_frame_arch (frame
), regnum
) == 4);
3104 put_frame_register (frame
, regnum
, from
);
3105 regnum
= i386_next_regnum (regnum
);
3111 /* Supply register REGNUM from the buffer specified by GREGS and LEN
3112 in the general-purpose register set REGSET to register cache
3113 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3116 i386_supply_gregset (const struct regset
*regset
, struct regcache
*regcache
,
3117 int regnum
, const void *gregs
, size_t len
)
3119 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
3120 const gdb_byte
*regs
= gregs
;
3123 gdb_assert (len
== tdep
->sizeof_gregset
);
3125 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
3127 if ((regnum
== i
|| regnum
== -1)
3128 && tdep
->gregset_reg_offset
[i
] != -1)
3129 regcache_raw_supply (regcache
, i
, regs
+ tdep
->gregset_reg_offset
[i
]);
3133 /* Collect register REGNUM from the register cache REGCACHE and store
3134 it in the buffer specified by GREGS and LEN as described by the
3135 general-purpose register set REGSET. If REGNUM is -1, do this for
3136 all registers in REGSET. */
3139 i386_collect_gregset (const struct regset
*regset
,
3140 const struct regcache
*regcache
,
3141 int regnum
, void *gregs
, size_t len
)
3143 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
3144 gdb_byte
*regs
= gregs
;
3147 gdb_assert (len
== tdep
->sizeof_gregset
);
3149 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
3151 if ((regnum
== i
|| regnum
== -1)
3152 && tdep
->gregset_reg_offset
[i
] != -1)
3153 regcache_raw_collect (regcache
, i
, regs
+ tdep
->gregset_reg_offset
[i
]);
3157 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
3158 in the floating-point register set REGSET to register cache
3159 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3162 i386_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
3163 int regnum
, const void *fpregs
, size_t len
)
3165 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
3167 if (len
== I387_SIZEOF_FXSAVE
)
3169 i387_supply_fxsave (regcache
, regnum
, fpregs
);
3173 gdb_assert (len
== tdep
->sizeof_fpregset
);
3174 i387_supply_fsave (regcache
, regnum
, fpregs
);
3177 /* Collect register REGNUM from the register cache REGCACHE and store
3178 it in the buffer specified by FPREGS and LEN as described by the
3179 floating-point register set REGSET. If REGNUM is -1, do this for
3180 all registers in REGSET. */
3183 i386_collect_fpregset (const struct regset
*regset
,
3184 const struct regcache
*regcache
,
3185 int regnum
, void *fpregs
, size_t len
)
3187 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
3189 if (len
== I387_SIZEOF_FXSAVE
)
3191 i387_collect_fxsave (regcache
, regnum
, fpregs
);
3195 gdb_assert (len
== tdep
->sizeof_fpregset
);
3196 i387_collect_fsave (regcache
, regnum
, fpregs
);
3199 /* Similar to i386_supply_fpregset, but use XSAVE extended state. */
3202 i386_supply_xstateregset (const struct regset
*regset
,
3203 struct regcache
*regcache
, int regnum
,
3204 const void *xstateregs
, size_t len
)
3206 i387_supply_xsave (regcache
, regnum
, xstateregs
);
3209 /* Similar to i386_collect_fpregset , but use XSAVE extended state. */
3212 i386_collect_xstateregset (const struct regset
*regset
,
3213 const struct regcache
*regcache
,
3214 int regnum
, void *xstateregs
, size_t len
)
3216 i387_collect_xsave (regcache
, regnum
, xstateregs
, 1);
3219 /* Return the appropriate register set for the core section identified
3220 by SECT_NAME and SECT_SIZE. */
3222 const struct regset
*
3223 i386_regset_from_core_section (struct gdbarch
*gdbarch
,
3224 const char *sect_name
, size_t sect_size
)
3226 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3228 if (strcmp (sect_name
, ".reg") == 0 && sect_size
== tdep
->sizeof_gregset
)
3230 if (tdep
->gregset
== NULL
)
3231 tdep
->gregset
= regset_alloc (gdbarch
, i386_supply_gregset
,
3232 i386_collect_gregset
);
3233 return tdep
->gregset
;
3236 if ((strcmp (sect_name
, ".reg2") == 0 && sect_size
== tdep
->sizeof_fpregset
)
3237 || (strcmp (sect_name
, ".reg-xfp") == 0
3238 && sect_size
== I387_SIZEOF_FXSAVE
))
3240 if (tdep
->fpregset
== NULL
)
3241 tdep
->fpregset
= regset_alloc (gdbarch
, i386_supply_fpregset
,
3242 i386_collect_fpregset
);
3243 return tdep
->fpregset
;
3246 if (strcmp (sect_name
, ".reg-xstate") == 0)
3248 if (tdep
->xstateregset
== NULL
)
3249 tdep
->xstateregset
= regset_alloc (gdbarch
,
3250 i386_supply_xstateregset
,
3251 i386_collect_xstateregset
);
3253 return tdep
->xstateregset
;
3260 /* Stuff for WIN32 PE style DLL's but is pretty generic really. */
3263 i386_pe_skip_trampoline_code (struct frame_info
*frame
,
3264 CORE_ADDR pc
, char *name
)
3266 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3267 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3270 if (pc
&& read_memory_unsigned_integer (pc
, 2, byte_order
) == 0x25ff)
3272 unsigned long indirect
=
3273 read_memory_unsigned_integer (pc
+ 2, 4, byte_order
);
3274 struct minimal_symbol
*indsym
=
3275 indirect
? lookup_minimal_symbol_by_pc (indirect
) : 0;
3276 const char *symname
= indsym
? SYMBOL_LINKAGE_NAME (indsym
) : 0;
3280 if (strncmp (symname
, "__imp_", 6) == 0
3281 || strncmp (symname
, "_imp_", 5) == 0)
3283 read_memory_unsigned_integer (indirect
, 4, byte_order
);
3286 return 0; /* Not a trampoline. */
3290 /* Return whether the THIS_FRAME corresponds to a sigtramp
3294 i386_sigtramp_p (struct frame_info
*this_frame
)
3296 CORE_ADDR pc
= get_frame_pc (this_frame
);
3299 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
3300 return (name
&& strcmp ("_sigtramp", name
) == 0);
3304 /* We have two flavours of disassembly. The machinery on this page
3305 deals with switching between those. */
3308 i386_print_insn (bfd_vma pc
, struct disassemble_info
*info
)
3310 gdb_assert (disassembly_flavor
== att_flavor
3311 || disassembly_flavor
== intel_flavor
);
3313 /* FIXME: kettenis/20020915: Until disassembler_options is properly
3314 constified, cast to prevent a compiler warning. */
3315 info
->disassembler_options
= (char *) disassembly_flavor
;
3317 return print_insn_i386 (pc
, info
);
3321 /* There are a few i386 architecture variants that differ only
3322 slightly from the generic i386 target. For now, we don't give them
3323 their own source file, but include them here. As a consequence,
3324 they'll always be included. */
3326 /* System V Release 4 (SVR4). */
3328 /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp
3332 i386_svr4_sigtramp_p (struct frame_info
*this_frame
)
3334 CORE_ADDR pc
= get_frame_pc (this_frame
);
3337 /* UnixWare uses _sigacthandler. The origin of the other symbols is
3338 currently unknown. */
3339 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
3340 return (name
&& (strcmp ("_sigreturn", name
) == 0
3341 || strcmp ("_sigacthandler", name
) == 0
3342 || strcmp ("sigvechandler", name
) == 0));
3345 /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the
3346 address of the associated sigcontext (ucontext) structure. */
3349 i386_svr4_sigcontext_addr (struct frame_info
*this_frame
)
3351 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3352 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3356 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
3357 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
3359 return read_memory_unsigned_integer (sp
+ 8, 4, byte_order
);
3366 i386_elf_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
3368 /* We typically use stabs-in-ELF with the SVR4 register numbering. */
3369 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
3372 /* System V Release 4 (SVR4). */
3375 i386_svr4_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
3377 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3379 /* System V Release 4 uses ELF. */
3380 i386_elf_init_abi (info
, gdbarch
);
3382 /* System V Release 4 has shared libraries. */
3383 set_gdbarch_skip_trampoline_code (gdbarch
, find_solib_trampoline_target
);
3385 tdep
->sigtramp_p
= i386_svr4_sigtramp_p
;
3386 tdep
->sigcontext_addr
= i386_svr4_sigcontext_addr
;
3387 tdep
->sc_pc_offset
= 36 + 14 * 4;
3388 tdep
->sc_sp_offset
= 36 + 17 * 4;
3390 tdep
->jb_pc_offset
= 20;
3396 i386_go32_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
3398 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3400 /* DJGPP doesn't have any special frames for signal handlers. */
3401 tdep
->sigtramp_p
= NULL
;
3403 tdep
->jb_pc_offset
= 36;
3405 /* DJGPP does not support the SSE registers. */
3406 if (! tdesc_has_registers (info
.target_desc
))
3407 tdep
->tdesc
= tdesc_i386_mmx
;
3409 /* Native compiler is GCC, which uses the SVR4 register numbering
3410 even in COFF and STABS. See the comment in i386_gdbarch_init,
3411 before the calls to set_gdbarch_stab_reg_to_regnum and
3412 set_gdbarch_sdb_reg_to_regnum. */
3413 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
3414 set_gdbarch_sdb_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
3416 set_gdbarch_has_dos_based_file_system (gdbarch
, 1);
3420 /* i386 register groups. In addition to the normal groups, add "mmx"
3423 static struct reggroup
*i386_sse_reggroup
;
3424 static struct reggroup
*i386_mmx_reggroup
;
3427 i386_init_reggroups (void)
3429 i386_sse_reggroup
= reggroup_new ("sse", USER_REGGROUP
);
3430 i386_mmx_reggroup
= reggroup_new ("mmx", USER_REGGROUP
);
3434 i386_add_reggroups (struct gdbarch
*gdbarch
)
3436 reggroup_add (gdbarch
, i386_sse_reggroup
);
3437 reggroup_add (gdbarch
, i386_mmx_reggroup
);
3438 reggroup_add (gdbarch
, general_reggroup
);
3439 reggroup_add (gdbarch
, float_reggroup
);
3440 reggroup_add (gdbarch
, all_reggroup
);
3441 reggroup_add (gdbarch
, save_reggroup
);
3442 reggroup_add (gdbarch
, restore_reggroup
);
3443 reggroup_add (gdbarch
, vector_reggroup
);
3444 reggroup_add (gdbarch
, system_reggroup
);
3448 i386_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
3449 struct reggroup
*group
)
3451 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3452 int fp_regnum_p
, mmx_regnum_p
, xmm_regnum_p
, mxcsr_regnum_p
,
3453 ymm_regnum_p
, ymmh_regnum_p
;
3455 /* Don't include pseudo registers, except for MMX, in any register
3457 if (i386_byte_regnum_p (gdbarch
, regnum
))
3460 if (i386_word_regnum_p (gdbarch
, regnum
))
3463 if (i386_dword_regnum_p (gdbarch
, regnum
))
3466 mmx_regnum_p
= i386_mmx_regnum_p (gdbarch
, regnum
);
3467 if (group
== i386_mmx_reggroup
)
3468 return mmx_regnum_p
;
3470 xmm_regnum_p
= i386_xmm_regnum_p (gdbarch
, regnum
);
3471 mxcsr_regnum_p
= i386_mxcsr_regnum_p (gdbarch
, regnum
);
3472 if (group
== i386_sse_reggroup
)
3473 return xmm_regnum_p
|| mxcsr_regnum_p
;
3475 ymm_regnum_p
= i386_ymm_regnum_p (gdbarch
, regnum
);
3476 if (group
== vector_reggroup
)
3477 return (mmx_regnum_p
3481 && ((tdep
->xcr0
& I386_XSTATE_AVX_MASK
)
3482 == I386_XSTATE_SSE_MASK
)));
3484 fp_regnum_p
= (i386_fp_regnum_p (gdbarch
, regnum
)
3485 || i386_fpc_regnum_p (gdbarch
, regnum
));
3486 if (group
== float_reggroup
)
3489 /* For "info reg all", don't include upper YMM registers nor XMM
3490 registers when AVX is supported. */
3491 ymmh_regnum_p
= i386_ymmh_regnum_p (gdbarch
, regnum
);
3492 if (group
== all_reggroup
3494 && (tdep
->xcr0
& I386_XSTATE_AVX
))
3498 if (group
== general_reggroup
)
3499 return (!fp_regnum_p
3506 return default_register_reggroup_p (gdbarch
, regnum
, group
);
3510 /* Get the ARGIth function argument for the current function. */
3513 i386_fetch_pointer_argument (struct frame_info
*frame
, int argi
,
3516 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3517 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3518 CORE_ADDR sp
= get_frame_register_unsigned (frame
, I386_ESP_REGNUM
);
3519 return read_memory_unsigned_integer (sp
+ (4 * (argi
+ 1)), 4, byte_order
);
3523 i386_skip_permanent_breakpoint (struct regcache
*regcache
)
3525 CORE_ADDR current_pc
= regcache_read_pc (regcache
);
3527 /* On i386, breakpoint is exactly 1 byte long, so we just
3528 adjust the PC in the regcache. */
3530 regcache_write_pc (regcache
, current_pc
);
3534 #define PREFIX_REPZ 0x01
3535 #define PREFIX_REPNZ 0x02
3536 #define PREFIX_LOCK 0x04
3537 #define PREFIX_DATA 0x08
3538 #define PREFIX_ADDR 0x10
3550 /* i386 arith/logic operations */
3563 struct i386_record_s
3565 struct gdbarch
*gdbarch
;
3566 struct regcache
*regcache
;
3567 CORE_ADDR orig_addr
;
3573 uint8_t mod
, reg
, rm
;
3582 /* Parse "modrm" part in current memory address that irp->addr point to
3583 Return -1 if something wrong. */
3586 i386_record_modrm (struct i386_record_s
*irp
)
3588 struct gdbarch
*gdbarch
= irp
->gdbarch
;
3590 if (target_read_memory (irp
->addr
, &irp
->modrm
, 1))
3593 printf_unfiltered (_("Process record: error reading memory at "
3594 "addr %s len = 1.\n"),
3595 paddress (gdbarch
, irp
->addr
));
3599 irp
->mod
= (irp
->modrm
>> 6) & 3;
3600 irp
->reg
= (irp
->modrm
>> 3) & 7;
3601 irp
->rm
= irp
->modrm
& 7;
3606 /* Get the memory address that current instruction write to and set it to
3607 the argument "addr".
3608 Return -1 if something wrong. */
3611 i386_record_lea_modrm_addr (struct i386_record_s
*irp
, uint64_t *addr
)
3613 struct gdbarch
*gdbarch
= irp
->gdbarch
;
3614 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3626 uint8_t base
= irp
->rm
;
3631 if (target_read_memory (irp
->addr
, &byte
, 1))
3634 printf_unfiltered (_("Process record: error reading memory "
3635 "at addr %s len = 1.\n"),
3636 paddress (gdbarch
, irp
->addr
));
3640 scale
= (byte
>> 6) & 3;
3641 index
= ((byte
>> 3) & 7) | irp
->rex_x
;
3649 if ((base
& 7) == 5)
3652 if (target_read_memory (irp
->addr
, buf
, 4))
3655 printf_unfiltered (_("Process record: error reading "
3656 "memory at addr %s len = 4.\n"),
3657 paddress (gdbarch
, irp
->addr
));
3661 *addr
= extract_signed_integer (buf
, 4, byte_order
);
3662 if (irp
->regmap
[X86_RECORD_R8_REGNUM
] && !havesib
)
3663 *addr
+= irp
->addr
+ irp
->rip_offset
;
3667 if (target_read_memory (irp
->addr
, buf
, 1))
3670 printf_unfiltered (_("Process record: error reading memory "
3671 "at addr %s len = 1.\n"),
3672 paddress (gdbarch
, irp
->addr
));
3676 *addr
= (int8_t) buf
[0];
3679 if (target_read_memory (irp
->addr
, buf
, 4))
3682 printf_unfiltered (_("Process record: error reading memory "
3683 "at addr %s len = 4.\n"),
3684 paddress (gdbarch
, irp
->addr
));
3687 *addr
= extract_signed_integer (buf
, 4, byte_order
);
3695 if (base
== 4 && irp
->popl_esp_hack
)
3696 *addr
+= irp
->popl_esp_hack
;
3697 regcache_raw_read_unsigned (irp
->regcache
, irp
->regmap
[base
],
3700 if (irp
->aflag
== 2)
3705 *addr
= (uint32_t) (offset64
+ *addr
);
3707 if (havesib
&& (index
!= 4 || scale
!= 0))
3709 regcache_raw_read_unsigned (irp
->regcache
, irp
->regmap
[index
],
3711 if (irp
->aflag
== 2)
3712 *addr
+= offset64
<< scale
;
3714 *addr
= (uint32_t) (*addr
+ (offset64
<< scale
));
3725 if (target_read_memory (irp
->addr
, buf
, 2))
3728 printf_unfiltered (_("Process record: error reading "
3729 "memory at addr %s len = 2.\n"),
3730 paddress (gdbarch
, irp
->addr
));
3734 *addr
= extract_signed_integer (buf
, 2, byte_order
);
3740 if (target_read_memory (irp
->addr
, buf
, 1))
3743 printf_unfiltered (_("Process record: error reading memory "
3744 "at addr %s len = 1.\n"),
3745 paddress (gdbarch
, irp
->addr
));
3749 *addr
= (int8_t) buf
[0];
3752 if (target_read_memory (irp
->addr
, buf
, 2))
3755 printf_unfiltered (_("Process record: error reading memory "
3756 "at addr %s len = 2.\n"),
3757 paddress (gdbarch
, irp
->addr
));
3761 *addr
= extract_signed_integer (buf
, 2, byte_order
);
3768 regcache_raw_read_unsigned (irp
->regcache
,
3769 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
3771 *addr
= (uint32_t) (*addr
+ offset64
);
3772 regcache_raw_read_unsigned (irp
->regcache
,
3773 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
3775 *addr
= (uint32_t) (*addr
+ offset64
);
3778 regcache_raw_read_unsigned (irp
->regcache
,
3779 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
3781 *addr
= (uint32_t) (*addr
+ offset64
);
3782 regcache_raw_read_unsigned (irp
->regcache
,
3783 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
3785 *addr
= (uint32_t) (*addr
+ offset64
);
3788 regcache_raw_read_unsigned (irp
->regcache
,
3789 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
3791 *addr
= (uint32_t) (*addr
+ offset64
);
3792 regcache_raw_read_unsigned (irp
->regcache
,
3793 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
3795 *addr
= (uint32_t) (*addr
+ offset64
);
3798 regcache_raw_read_unsigned (irp
->regcache
,
3799 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
3801 *addr
= (uint32_t) (*addr
+ offset64
);
3802 regcache_raw_read_unsigned (irp
->regcache
,
3803 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
3805 *addr
= (uint32_t) (*addr
+ offset64
);
3808 regcache_raw_read_unsigned (irp
->regcache
,
3809 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
3811 *addr
= (uint32_t) (*addr
+ offset64
);
3814 regcache_raw_read_unsigned (irp
->regcache
,
3815 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
3817 *addr
= (uint32_t) (*addr
+ offset64
);
3820 regcache_raw_read_unsigned (irp
->regcache
,
3821 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
3823 *addr
= (uint32_t) (*addr
+ offset64
);
3826 regcache_raw_read_unsigned (irp
->regcache
,
3827 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
3829 *addr
= (uint32_t) (*addr
+ offset64
);
3839 /* Record the value of the memory that willbe changed in current instruction
3840 to "record_arch_list".
3841 Return -1 if something wrong. */
3844 i386_record_lea_modrm (struct i386_record_s
*irp
)
3846 struct gdbarch
*gdbarch
= irp
->gdbarch
;
3849 if (irp
->override
>= 0)
3851 if (record_memory_query
)
3855 target_terminal_ours ();
3857 Process record ignores the memory change of instruction at address %s\n\
3858 because it can't get the value of the segment register.\n\
3859 Do you want to stop the program?"),
3860 paddress (gdbarch
, irp
->orig_addr
));
3861 target_terminal_inferior ();
3869 if (i386_record_lea_modrm_addr (irp
, &addr
))
3872 if (record_arch_list_add_mem (addr
, 1 << irp
->ot
))
3878 /* Record the push operation to "record_arch_list".
3879 Return -1 if something wrong. */
3882 i386_record_push (struct i386_record_s
*irp
, int size
)
3886 if (record_arch_list_add_reg (irp
->regcache
,
3887 irp
->regmap
[X86_RECORD_RESP_REGNUM
]))
3889 regcache_raw_read_unsigned (irp
->regcache
,
3890 irp
->regmap
[X86_RECORD_RESP_REGNUM
],
3892 if (record_arch_list_add_mem ((CORE_ADDR
) addr
- size
, size
))
3899 /* Defines contents to record. */
3900 #define I386_SAVE_FPU_REGS 0xfffd
3901 #define I386_SAVE_FPU_ENV 0xfffe
3902 #define I386_SAVE_FPU_ENV_REG_STACK 0xffff
3904 /* Record the value of floating point registers which will be changed
3905 by the current instruction to "record_arch_list". Return -1 if
3906 something is wrong. */
3908 static int i386_record_floats (struct gdbarch
*gdbarch
,
3909 struct i386_record_s
*ir
,
3912 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3915 /* Oza: Because of floating point insn push/pop of fpu stack is going to
3916 happen. Currently we store st0-st7 registers, but we need not store all
3917 registers all the time, in future we use ftag register and record only
3918 those who are not marked as an empty. */
3920 if (I386_SAVE_FPU_REGS
== iregnum
)
3922 for (i
= I387_ST0_REGNUM (tdep
); i
<= I387_ST0_REGNUM (tdep
) + 7; i
++)
3924 if (record_arch_list_add_reg (ir
->regcache
, i
))
3928 else if (I386_SAVE_FPU_ENV
== iregnum
)
3930 for (i
= I387_FCTRL_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
3932 if (record_arch_list_add_reg (ir
->regcache
, i
))
3936 else if (I386_SAVE_FPU_ENV_REG_STACK
== iregnum
)
3938 for (i
= I387_ST0_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
3940 if (record_arch_list_add_reg (ir
->regcache
, i
))
3944 else if ((iregnum
>= I387_ST0_REGNUM (tdep
)) &&
3945 (iregnum
<= I387_FOP_REGNUM (tdep
)))
3947 if (record_arch_list_add_reg (ir
->regcache
,iregnum
))
3952 /* Parameter error. */
3955 if(I386_SAVE_FPU_ENV
!= iregnum
)
3957 for (i
= I387_FCTRL_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
3959 if (record_arch_list_add_reg (ir
->regcache
, i
))
3966 /* Parse the current instruction and record the values of the registers and
3967 memory that will be changed in current instruction to "record_arch_list".
3968 Return -1 if something wrong. */
3970 #define I386_RECORD_ARCH_LIST_ADD_REG(regnum) \
3971 record_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)])
3974 i386_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
3975 CORE_ADDR input_addr
)
3977 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3983 gdb_byte buf
[MAX_REGISTER_SIZE
];
3984 struct i386_record_s ir
;
3985 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3990 memset (&ir
, 0, sizeof (struct i386_record_s
));
3991 ir
.regcache
= regcache
;
3992 ir
.addr
= input_addr
;
3993 ir
.orig_addr
= input_addr
;
3997 ir
.popl_esp_hack
= 0;
3998 ir
.regmap
= tdep
->record_regmap
;
3999 ir
.gdbarch
= gdbarch
;
4001 if (record_debug
> 1)
4002 fprintf_unfiltered (gdb_stdlog
, "Process record: i386_process_record "
4004 paddress (gdbarch
, ir
.addr
));
4009 if (target_read_memory (ir
.addr
, &opcode8
, 1))
4012 printf_unfiltered (_("Process record: error reading memory at "
4013 "addr %s len = 1.\n"),
4014 paddress (gdbarch
, ir
.addr
));
4018 switch (opcode8
) /* Instruction prefixes */
4020 case REPE_PREFIX_OPCODE
:
4021 prefixes
|= PREFIX_REPZ
;
4023 case REPNE_PREFIX_OPCODE
:
4024 prefixes
|= PREFIX_REPNZ
;
4026 case LOCK_PREFIX_OPCODE
:
4027 prefixes
|= PREFIX_LOCK
;
4029 case CS_PREFIX_OPCODE
:
4030 ir
.override
= X86_RECORD_CS_REGNUM
;
4032 case SS_PREFIX_OPCODE
:
4033 ir
.override
= X86_RECORD_SS_REGNUM
;
4035 case DS_PREFIX_OPCODE
:
4036 ir
.override
= X86_RECORD_DS_REGNUM
;
4038 case ES_PREFIX_OPCODE
:
4039 ir
.override
= X86_RECORD_ES_REGNUM
;
4041 case FS_PREFIX_OPCODE
:
4042 ir
.override
= X86_RECORD_FS_REGNUM
;
4044 case GS_PREFIX_OPCODE
:
4045 ir
.override
= X86_RECORD_GS_REGNUM
;
4047 case DATA_PREFIX_OPCODE
:
4048 prefixes
|= PREFIX_DATA
;
4050 case ADDR_PREFIX_OPCODE
:
4051 prefixes
|= PREFIX_ADDR
;
4053 case 0x40: /* i386 inc %eax */
4054 case 0x41: /* i386 inc %ecx */
4055 case 0x42: /* i386 inc %edx */
4056 case 0x43: /* i386 inc %ebx */
4057 case 0x44: /* i386 inc %esp */
4058 case 0x45: /* i386 inc %ebp */
4059 case 0x46: /* i386 inc %esi */
4060 case 0x47: /* i386 inc %edi */
4061 case 0x48: /* i386 dec %eax */
4062 case 0x49: /* i386 dec %ecx */
4063 case 0x4a: /* i386 dec %edx */
4064 case 0x4b: /* i386 dec %ebx */
4065 case 0x4c: /* i386 dec %esp */
4066 case 0x4d: /* i386 dec %ebp */
4067 case 0x4e: /* i386 dec %esi */
4068 case 0x4f: /* i386 dec %edi */
4069 if (ir
.regmap
[X86_RECORD_R8_REGNUM
]) /* 64 bit target */
4073 rex_w
= (opcode8
>> 3) & 1;
4074 rex_r
= (opcode8
& 0x4) << 1;
4075 ir
.rex_x
= (opcode8
& 0x2) << 2;
4076 ir
.rex_b
= (opcode8
& 0x1) << 3;
4078 else /* 32 bit target */
4087 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && rex_w
== 1)
4093 if (prefixes
& PREFIX_DATA
)
4096 if (prefixes
& PREFIX_ADDR
)
4098 else if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4101 /* Now check op code. */
4102 opcode
= (uint32_t) opcode8
;
4107 if (target_read_memory (ir
.addr
, &opcode8
, 1))
4110 printf_unfiltered (_("Process record: error reading memory at "
4111 "addr %s len = 1.\n"),
4112 paddress (gdbarch
, ir
.addr
));
4116 opcode
= (uint32_t) opcode8
| 0x0f00;
4120 case 0x00: /* arith & logic */
4168 if (((opcode
>> 3) & 7) != OP_CMPL
)
4170 if ((opcode
& 1) == 0)
4173 ir
.ot
= ir
.dflag
+ OT_WORD
;
4175 switch ((opcode
>> 1) & 3)
4177 case 0: /* OP Ev, Gv */
4178 if (i386_record_modrm (&ir
))
4182 if (i386_record_lea_modrm (&ir
))
4188 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4190 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4193 case 1: /* OP Gv, Ev */
4194 if (i386_record_modrm (&ir
))
4197 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4199 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4201 case 2: /* OP A, Iv */
4202 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4206 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4209 case 0x80: /* GRP1 */
4213 if (i386_record_modrm (&ir
))
4216 if (ir
.reg
!= OP_CMPL
)
4218 if ((opcode
& 1) == 0)
4221 ir
.ot
= ir
.dflag
+ OT_WORD
;
4228 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
4229 if (i386_record_lea_modrm (&ir
))
4233 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
4235 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4238 case 0x40: /* inc */
4247 case 0x48: /* dec */
4256 I386_RECORD_ARCH_LIST_ADD_REG (opcode
& 7);
4257 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4260 case 0xf6: /* GRP3 */
4262 if ((opcode
& 1) == 0)
4265 ir
.ot
= ir
.dflag
+ OT_WORD
;
4266 if (i386_record_modrm (&ir
))
4269 if (ir
.mod
!= 3 && ir
.reg
== 0)
4270 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
4275 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4281 if (i386_record_lea_modrm (&ir
))
4287 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4289 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4291 if (ir
.reg
== 3) /* neg */
4292 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4298 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4299 if (ir
.ot
!= OT_BYTE
)
4300 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
4301 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4305 opcode
= opcode
<< 8 | ir
.modrm
;
4311 case 0xfe: /* GRP4 */
4312 case 0xff: /* GRP5 */
4313 if (i386_record_modrm (&ir
))
4315 if (ir
.reg
>= 2 && opcode
== 0xfe)
4318 opcode
= opcode
<< 8 | ir
.modrm
;
4325 if ((opcode
& 1) == 0)
4328 ir
.ot
= ir
.dflag
+ OT_WORD
;
4331 if (i386_record_lea_modrm (&ir
))
4337 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4339 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4341 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4344 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4346 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4348 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4351 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
4352 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4354 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4358 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4361 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4363 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4368 opcode
= opcode
<< 8 | ir
.modrm
;
4374 case 0x84: /* test */
4378 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4381 case 0x98: /* CWDE/CBW */
4382 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4385 case 0x99: /* CDQ/CWD */
4386 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4387 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
4390 case 0x0faf: /* imul */
4393 ir
.ot
= ir
.dflag
+ OT_WORD
;
4394 if (i386_record_modrm (&ir
))
4397 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
4398 else if (opcode
== 0x6b)
4401 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4403 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4404 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4407 case 0x0fc0: /* xadd */
4409 if ((opcode
& 1) == 0)
4412 ir
.ot
= ir
.dflag
+ OT_WORD
;
4413 if (i386_record_modrm (&ir
))
4418 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4420 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4421 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4423 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4427 if (i386_record_lea_modrm (&ir
))
4429 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4431 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4433 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4436 case 0x0fb0: /* cmpxchg */
4438 if ((opcode
& 1) == 0)
4441 ir
.ot
= ir
.dflag
+ OT_WORD
;
4442 if (i386_record_modrm (&ir
))
4447 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4448 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4450 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4454 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4455 if (i386_record_lea_modrm (&ir
))
4458 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4461 case 0x0fc7: /* cmpxchg8b */
4462 if (i386_record_modrm (&ir
))
4467 opcode
= opcode
<< 8 | ir
.modrm
;
4470 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4471 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
4472 if (i386_record_lea_modrm (&ir
))
4474 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4477 case 0x50: /* push */
4487 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4489 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4493 case 0x06: /* push es */
4494 case 0x0e: /* push cs */
4495 case 0x16: /* push ss */
4496 case 0x1e: /* push ds */
4497 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4502 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4506 case 0x0fa0: /* push fs */
4507 case 0x0fa8: /* push gs */
4508 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4513 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4517 case 0x60: /* pusha */
4518 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4523 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 4)))
4527 case 0x58: /* pop */
4535 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4536 I386_RECORD_ARCH_LIST_ADD_REG ((opcode
& 0x7) | ir
.rex_b
);
4539 case 0x61: /* popa */
4540 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4545 for (regnum
= X86_RECORD_REAX_REGNUM
;
4546 regnum
<= X86_RECORD_REDI_REGNUM
;
4548 I386_RECORD_ARCH_LIST_ADD_REG (regnum
);
4551 case 0x8f: /* pop */
4552 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4553 ir
.ot
= ir
.dflag
? OT_QUAD
: OT_WORD
;
4555 ir
.ot
= ir
.dflag
+ OT_WORD
;
4556 if (i386_record_modrm (&ir
))
4559 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
4562 ir
.popl_esp_hack
= 1 << ir
.ot
;
4563 if (i386_record_lea_modrm (&ir
))
4566 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4569 case 0xc8: /* enter */
4570 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
4571 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4573 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4577 case 0xc9: /* leave */
4578 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4579 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
4582 case 0x07: /* pop es */
4583 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4588 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4589 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM
);
4590 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4593 case 0x17: /* pop ss */
4594 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4599 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4600 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM
);
4601 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4604 case 0x1f: /* pop ds */
4605 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4610 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4611 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM
);
4612 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4615 case 0x0fa1: /* pop fs */
4616 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4617 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM
);
4618 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4621 case 0x0fa9: /* pop gs */
4622 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4623 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM
);
4624 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4627 case 0x88: /* mov */
4631 if ((opcode
& 1) == 0)
4634 ir
.ot
= ir
.dflag
+ OT_WORD
;
4636 if (i386_record_modrm (&ir
))
4641 if (opcode
== 0xc6 || opcode
== 0xc7)
4642 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
4643 if (i386_record_lea_modrm (&ir
))
4648 if (opcode
== 0xc6 || opcode
== 0xc7)
4650 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4652 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4656 case 0x8a: /* mov */
4658 if ((opcode
& 1) == 0)
4661 ir
.ot
= ir
.dflag
+ OT_WORD
;
4662 if (i386_record_modrm (&ir
))
4665 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4667 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4670 case 0x8c: /* mov seg */
4671 if (i386_record_modrm (&ir
))
4676 opcode
= opcode
<< 8 | ir
.modrm
;
4681 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4685 if (i386_record_lea_modrm (&ir
))
4690 case 0x8e: /* mov seg */
4691 if (i386_record_modrm (&ir
))
4696 regnum
= X86_RECORD_ES_REGNUM
;
4699 regnum
= X86_RECORD_SS_REGNUM
;
4702 regnum
= X86_RECORD_DS_REGNUM
;
4705 regnum
= X86_RECORD_FS_REGNUM
;
4708 regnum
= X86_RECORD_GS_REGNUM
;
4712 opcode
= opcode
<< 8 | ir
.modrm
;
4716 I386_RECORD_ARCH_LIST_ADD_REG (regnum
);
4717 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4720 case 0x0fb6: /* movzbS */
4721 case 0x0fb7: /* movzwS */
4722 case 0x0fbe: /* movsbS */
4723 case 0x0fbf: /* movswS */
4724 if (i386_record_modrm (&ir
))
4726 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
4729 case 0x8d: /* lea */
4730 if (i386_record_modrm (&ir
))
4735 opcode
= opcode
<< 8 | ir
.modrm
;
4740 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4742 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4745 case 0xa0: /* mov EAX */
4748 case 0xd7: /* xlat */
4749 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4752 case 0xa2: /* mov EAX */
4754 if (ir
.override
>= 0)
4756 if (record_memory_query
)
4760 target_terminal_ours ();
4762 Process record ignores the memory change of instruction at address %s\n\
4763 because it can't get the value of the segment register.\n\
4764 Do you want to stop the program?"),
4765 paddress (gdbarch
, ir
.orig_addr
));
4766 target_terminal_inferior ();
4773 if ((opcode
& 1) == 0)
4776 ir
.ot
= ir
.dflag
+ OT_WORD
;
4779 if (target_read_memory (ir
.addr
, buf
, 8))
4782 printf_unfiltered (_("Process record: error reading "
4783 "memory at addr 0x%s len = 8.\n"),
4784 paddress (gdbarch
, ir
.addr
));
4788 addr
= extract_unsigned_integer (buf
, 8, byte_order
);
4792 if (target_read_memory (ir
.addr
, buf
, 4))
4795 printf_unfiltered (_("Process record: error reading "
4796 "memory at addr 0x%s len = 4.\n"),
4797 paddress (gdbarch
, ir
.addr
));
4801 addr
= extract_unsigned_integer (buf
, 4, byte_order
);
4805 if (target_read_memory (ir
.addr
, buf
, 2))
4808 printf_unfiltered (_("Process record: error reading "
4809 "memory at addr 0x%s len = 2.\n"),
4810 paddress (gdbarch
, ir
.addr
));
4814 addr
= extract_unsigned_integer (buf
, 2, byte_order
);
4816 if (record_arch_list_add_mem (addr
, 1 << ir
.ot
))
4821 case 0xb0: /* mov R, Ib */
4829 I386_RECORD_ARCH_LIST_ADD_REG ((ir
.regmap
[X86_RECORD_R8_REGNUM
])
4830 ? ((opcode
& 0x7) | ir
.rex_b
)
4831 : ((opcode
& 0x7) & 0x3));
4834 case 0xb8: /* mov R, Iv */
4842 I386_RECORD_ARCH_LIST_ADD_REG ((opcode
& 0x7) | ir
.rex_b
);
4845 case 0x91: /* xchg R, EAX */
4852 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4853 I386_RECORD_ARCH_LIST_ADD_REG (opcode
& 0x7);
4856 case 0x86: /* xchg Ev, Gv */
4858 if ((opcode
& 1) == 0)
4861 ir
.ot
= ir
.dflag
+ OT_WORD
;
4862 if (i386_record_modrm (&ir
))
4867 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4869 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4873 if (i386_record_lea_modrm (&ir
))
4877 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4879 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4882 case 0xc4: /* les Gv */
4883 case 0xc5: /* lds Gv */
4884 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4890 case 0x0fb2: /* lss Gv */
4891 case 0x0fb4: /* lfs Gv */
4892 case 0x0fb5: /* lgs Gv */
4893 if (i386_record_modrm (&ir
))
4901 opcode
= opcode
<< 8 | ir
.modrm
;
4906 case 0xc4: /* les Gv */
4907 regnum
= X86_RECORD_ES_REGNUM
;
4909 case 0xc5: /* lds Gv */
4910 regnum
= X86_RECORD_DS_REGNUM
;
4912 case 0x0fb2: /* lss Gv */
4913 regnum
= X86_RECORD_SS_REGNUM
;
4915 case 0x0fb4: /* lfs Gv */
4916 regnum
= X86_RECORD_FS_REGNUM
;
4918 case 0x0fb5: /* lgs Gv */
4919 regnum
= X86_RECORD_GS_REGNUM
;
4922 I386_RECORD_ARCH_LIST_ADD_REG (regnum
);
4923 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
4924 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4927 case 0xc0: /* shifts */
4933 if ((opcode
& 1) == 0)
4936 ir
.ot
= ir
.dflag
+ OT_WORD
;
4937 if (i386_record_modrm (&ir
))
4939 if (ir
.mod
!= 3 && (opcode
== 0xd2 || opcode
== 0xd3))
4941 if (i386_record_lea_modrm (&ir
))
4947 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4949 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4951 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4958 if (i386_record_modrm (&ir
))
4962 if (record_arch_list_add_reg (ir
.regcache
, ir
.rm
))
4967 if (i386_record_lea_modrm (&ir
))
4972 case 0xd8: /* Floats. */
4980 if (i386_record_modrm (&ir
))
4982 ir
.reg
|= ((opcode
& 7) << 3);
4988 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
4996 /* For fcom, ficom nothing to do. */
5002 /* For fcomp, ficomp pop FPU stack, store all. */
5003 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5030 /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul,
5031 fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension
5032 of code, always affects st(0) register. */
5033 if (i386_record_floats (gdbarch
, &ir
, I387_ST0_REGNUM (tdep
)))
5057 /* Handling fld, fild. */
5058 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5062 switch (ir
.reg
>> 4)
5065 if (record_arch_list_add_mem (addr64
, 4))
5069 if (record_arch_list_add_mem (addr64
, 8))
5075 if (record_arch_list_add_mem (addr64
, 2))
5081 switch (ir
.reg
>> 4)
5084 if (record_arch_list_add_mem (addr64
, 4))
5086 if (3 == (ir
.reg
& 7))
5088 /* For fstp m32fp. */
5089 if (i386_record_floats (gdbarch
, &ir
,
5090 I386_SAVE_FPU_REGS
))
5095 if (record_arch_list_add_mem (addr64
, 4))
5097 if ((3 == (ir
.reg
& 7))
5098 || (5 == (ir
.reg
& 7))
5099 || (7 == (ir
.reg
& 7)))
5101 /* For fstp insn. */
5102 if (i386_record_floats (gdbarch
, &ir
,
5103 I386_SAVE_FPU_REGS
))
5108 if (record_arch_list_add_mem (addr64
, 8))
5110 if (3 == (ir
.reg
& 7))
5112 /* For fstp m64fp. */
5113 if (i386_record_floats (gdbarch
, &ir
,
5114 I386_SAVE_FPU_REGS
))
5119 if ((3 <= (ir
.reg
& 7)) && (6 <= (ir
.reg
& 7)))
5121 /* For fistp, fbld, fild, fbstp. */
5122 if (i386_record_floats (gdbarch
, &ir
,
5123 I386_SAVE_FPU_REGS
))
5128 if (record_arch_list_add_mem (addr64
, 2))
5137 if (i386_record_floats (gdbarch
, &ir
,
5138 I386_SAVE_FPU_ENV_REG_STACK
))
5143 if (i386_record_floats (gdbarch
, &ir
, I387_FCTRL_REGNUM (tdep
)))
5148 if (i386_record_floats (gdbarch
, &ir
,
5149 I386_SAVE_FPU_ENV_REG_STACK
))
5155 if (record_arch_list_add_mem (addr64
, 28))
5160 if (record_arch_list_add_mem (addr64
, 14))
5166 if (record_arch_list_add_mem (addr64
, 2))
5168 /* Insn fstp, fbstp. */
5169 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5174 if (record_arch_list_add_mem (addr64
, 10))
5180 if (record_arch_list_add_mem (addr64
, 28))
5186 if (record_arch_list_add_mem (addr64
, 14))
5190 if (record_arch_list_add_mem (addr64
, 80))
5193 if (i386_record_floats (gdbarch
, &ir
,
5194 I386_SAVE_FPU_ENV_REG_STACK
))
5198 if (record_arch_list_add_mem (addr64
, 8))
5201 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5206 opcode
= opcode
<< 8 | ir
.modrm
;
5211 /* Opcode is an extension of modR/M byte. */
5217 if (i386_record_floats (gdbarch
, &ir
, I387_ST0_REGNUM (tdep
)))
5221 if (0x0c == (ir
.modrm
>> 4))
5223 if ((ir
.modrm
& 0x0f) <= 7)
5225 if (i386_record_floats (gdbarch
, &ir
,
5226 I386_SAVE_FPU_REGS
))
5231 if (i386_record_floats (gdbarch
, &ir
,
5232 I387_ST0_REGNUM (tdep
)))
5234 /* If only st(0) is changing, then we have already
5236 if ((ir
.modrm
& 0x0f) - 0x08)
5238 if (i386_record_floats (gdbarch
, &ir
,
5239 I387_ST0_REGNUM (tdep
) +
5240 ((ir
.modrm
& 0x0f) - 0x08)))
5258 if (i386_record_floats (gdbarch
, &ir
,
5259 I387_ST0_REGNUM (tdep
)))
5277 if (i386_record_floats (gdbarch
, &ir
,
5278 I386_SAVE_FPU_REGS
))
5282 if (i386_record_floats (gdbarch
, &ir
,
5283 I387_ST0_REGNUM (tdep
)))
5285 if (i386_record_floats (gdbarch
, &ir
,
5286 I387_ST0_REGNUM (tdep
) + 1))
5293 if (0xe9 == ir
.modrm
)
5295 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5298 else if ((0x0c == ir
.modrm
>> 4) || (0x0d == ir
.modrm
>> 4))
5300 if (i386_record_floats (gdbarch
, &ir
,
5301 I387_ST0_REGNUM (tdep
)))
5303 if (((ir
.modrm
& 0x0f) > 0) && ((ir
.modrm
& 0x0f) <= 7))
5305 if (i386_record_floats (gdbarch
, &ir
,
5306 I387_ST0_REGNUM (tdep
) +
5310 else if ((ir
.modrm
& 0x0f) - 0x08)
5312 if (i386_record_floats (gdbarch
, &ir
,
5313 I387_ST0_REGNUM (tdep
) +
5314 ((ir
.modrm
& 0x0f) - 0x08)))
5320 if (0xe3 == ir
.modrm
)
5322 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_ENV
))
5325 else if ((0x0c == ir
.modrm
>> 4) || (0x0d == ir
.modrm
>> 4))
5327 if (i386_record_floats (gdbarch
, &ir
,
5328 I387_ST0_REGNUM (tdep
)))
5330 if (((ir
.modrm
& 0x0f) > 0) && ((ir
.modrm
& 0x0f) <= 7))
5332 if (i386_record_floats (gdbarch
, &ir
,
5333 I387_ST0_REGNUM (tdep
) +
5337 else if ((ir
.modrm
& 0x0f) - 0x08)
5339 if (i386_record_floats (gdbarch
, &ir
,
5340 I387_ST0_REGNUM (tdep
) +
5341 ((ir
.modrm
& 0x0f) - 0x08)))
5347 if ((0x0c == ir
.modrm
>> 4)
5348 || (0x0d == ir
.modrm
>> 4)
5349 || (0x0f == ir
.modrm
>> 4))
5351 if ((ir
.modrm
& 0x0f) <= 7)
5353 if (i386_record_floats (gdbarch
, &ir
,
5354 I387_ST0_REGNUM (tdep
) +
5360 if (i386_record_floats (gdbarch
, &ir
,
5361 I387_ST0_REGNUM (tdep
) +
5362 ((ir
.modrm
& 0x0f) - 0x08)))
5368 if (0x0c == ir
.modrm
>> 4)
5370 if (i386_record_floats (gdbarch
, &ir
,
5371 I387_FTAG_REGNUM (tdep
)))
5374 else if ((0x0d == ir
.modrm
>> 4) || (0x0e == ir
.modrm
>> 4))
5376 if ((ir
.modrm
& 0x0f) <= 7)
5378 if (i386_record_floats (gdbarch
, &ir
,
5379 I387_ST0_REGNUM (tdep
) +
5385 if (i386_record_floats (gdbarch
, &ir
,
5386 I386_SAVE_FPU_REGS
))
5392 if ((0x0c == ir
.modrm
>> 4)
5393 || (0x0e == ir
.modrm
>> 4)
5394 || (0x0f == ir
.modrm
>> 4)
5395 || (0xd9 == ir
.modrm
))
5397 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5402 if (0xe0 == ir
.modrm
)
5404 if (record_arch_list_add_reg (ir
.regcache
, I386_EAX_REGNUM
))
5407 else if ((0x0f == ir
.modrm
>> 4) || (0x0e == ir
.modrm
>> 4))
5409 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5417 case 0xa4: /* movsS */
5419 case 0xaa: /* stosS */
5421 case 0x6c: /* insS */
5423 regcache_raw_read_unsigned (ir
.regcache
,
5424 ir
.regmap
[X86_RECORD_RECX_REGNUM
],
5430 if ((opcode
& 1) == 0)
5433 ir
.ot
= ir
.dflag
+ OT_WORD
;
5434 regcache_raw_read_unsigned (ir
.regcache
,
5435 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
5438 regcache_raw_read_unsigned (ir
.regcache
,
5439 ir
.regmap
[X86_RECORD_ES_REGNUM
],
5441 regcache_raw_read_unsigned (ir
.regcache
,
5442 ir
.regmap
[X86_RECORD_DS_REGNUM
],
5444 if (ir
.aflag
&& (es
!= ds
))
5446 /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */
5447 if (record_memory_query
)
5451 target_terminal_ours ();
5453 Process record ignores the memory change of instruction at address %s\n\
5454 because it can't get the value of the segment register.\n\
5455 Do you want to stop the program?"),
5456 paddress (gdbarch
, ir
.orig_addr
));
5457 target_terminal_inferior ();
5464 if (record_arch_list_add_mem (addr
, 1 << ir
.ot
))
5468 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5469 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5470 if (opcode
== 0xa4 || opcode
== 0xa5)
5471 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
5472 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
5473 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5477 case 0xa6: /* cmpsS */
5479 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
5480 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
5481 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5482 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5483 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5486 case 0xac: /* lodsS */
5488 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5489 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
5490 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5491 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5492 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5495 case 0xae: /* scasS */
5497 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
5498 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5499 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5500 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5503 case 0x6e: /* outsS */
5505 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
5506 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5507 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5508 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5511 case 0xe4: /* port I/O */
5515 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5516 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5526 case 0xc2: /* ret im */
5527 case 0xc3: /* ret */
5528 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5529 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5532 case 0xca: /* lret im */
5533 case 0xcb: /* lret */
5534 case 0xcf: /* iret */
5535 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
5536 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5537 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5540 case 0xe8: /* call im */
5541 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5543 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5547 case 0x9a: /* lcall im */
5548 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5553 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
5554 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5558 case 0xe9: /* jmp im */
5559 case 0xea: /* ljmp im */
5560 case 0xeb: /* jmp Jb */
5561 case 0x70: /* jcc Jb */
5577 case 0x0f80: /* jcc Jv */
5595 case 0x0f90: /* setcc Gv */
5611 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5613 if (i386_record_modrm (&ir
))
5616 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rex_b
? (ir
.rm
| ir
.rex_b
)
5620 if (i386_record_lea_modrm (&ir
))
5625 case 0x0f40: /* cmov Gv, Ev */
5641 if (i386_record_modrm (&ir
))
5644 if (ir
.dflag
== OT_BYTE
)
5646 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
5650 case 0x9c: /* pushf */
5651 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5652 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5654 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5658 case 0x9d: /* popf */
5659 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5660 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5663 case 0x9e: /* sahf */
5664 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5670 case 0xf5: /* cmc */
5671 case 0xf8: /* clc */
5672 case 0xf9: /* stc */
5673 case 0xfc: /* cld */
5674 case 0xfd: /* std */
5675 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5678 case 0x9f: /* lahf */
5679 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5684 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5685 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5688 /* bit operations */
5689 case 0x0fba: /* bt/bts/btr/btc Gv, im */
5690 ir
.ot
= ir
.dflag
+ OT_WORD
;
5691 if (i386_record_modrm (&ir
))
5696 opcode
= opcode
<< 8 | ir
.modrm
;
5702 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5705 if (i386_record_lea_modrm (&ir
))
5709 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5712 case 0x0fa3: /* bt Gv, Ev */
5713 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5716 case 0x0fab: /* bts */
5717 case 0x0fb3: /* btr */
5718 case 0x0fbb: /* btc */
5719 ir
.ot
= ir
.dflag
+ OT_WORD
;
5720 if (i386_record_modrm (&ir
))
5723 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5727 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
5729 regcache_raw_read_unsigned (ir
.regcache
,
5730 ir
.regmap
[ir
.reg
| rex_r
],
5735 addr64
+= ((int16_t) addr
>> 4) << 4;
5738 addr64
+= ((int32_t) addr
>> 5) << 5;
5741 addr64
+= ((int64_t) addr
>> 6) << 6;
5744 if (record_arch_list_add_mem (addr64
, 1 << ir
.ot
))
5746 if (i386_record_lea_modrm (&ir
))
5749 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5752 case 0x0fbc: /* bsf */
5753 case 0x0fbd: /* bsr */
5754 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
5755 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5759 case 0x27: /* daa */
5760 case 0x2f: /* das */
5761 case 0x37: /* aaa */
5762 case 0x3f: /* aas */
5763 case 0xd4: /* aam */
5764 case 0xd5: /* aad */
5765 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5770 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5771 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5775 case 0x90: /* nop */
5776 if (prefixes
& PREFIX_LOCK
)
5783 case 0x9b: /* fwait */
5784 if (target_read_memory (ir
.addr
, &opcode8
, 1))
5787 printf_unfiltered (_("Process record: error reading memory at "
5788 "addr 0x%s len = 1.\n"),
5789 paddress (gdbarch
, ir
.addr
));
5792 opcode
= (uint32_t) opcode8
;
5798 case 0xcc: /* int3 */
5799 printf_unfiltered (_("Process record does not support instruction "
5806 case 0xcd: /* int */
5810 if (target_read_memory (ir
.addr
, &interrupt
, 1))
5813 printf_unfiltered (_("Process record: error reading memory "
5814 "at addr %s len = 1.\n"),
5815 paddress (gdbarch
, ir
.addr
));
5819 if (interrupt
!= 0x80
5820 || tdep
->i386_intx80_record
== NULL
)
5822 printf_unfiltered (_("Process record does not support "
5823 "instruction int 0x%02x.\n"),
5828 ret
= tdep
->i386_intx80_record (ir
.regcache
);
5835 case 0xce: /* into */
5836 printf_unfiltered (_("Process record does not support "
5837 "instruction into.\n"));
5842 case 0xfa: /* cli */
5843 case 0xfb: /* sti */
5846 case 0x62: /* bound */
5847 printf_unfiltered (_("Process record does not support "
5848 "instruction bound.\n"));
5853 case 0x0fc8: /* bswap reg */
5861 I386_RECORD_ARCH_LIST_ADD_REG ((opcode
& 7) | ir
.rex_b
);
5864 case 0xd6: /* salc */
5865 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5870 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5871 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5874 case 0xe0: /* loopnz */
5875 case 0xe1: /* loopz */
5876 case 0xe2: /* loop */
5877 case 0xe3: /* jecxz */
5878 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5879 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5882 case 0x0f30: /* wrmsr */
5883 printf_unfiltered (_("Process record does not support "
5884 "instruction wrmsr.\n"));
5889 case 0x0f32: /* rdmsr */
5890 printf_unfiltered (_("Process record does not support "
5891 "instruction rdmsr.\n"));
5896 case 0x0f31: /* rdtsc */
5897 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5898 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5901 case 0x0f34: /* sysenter */
5904 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5909 if (tdep
->i386_sysenter_record
== NULL
)
5911 printf_unfiltered (_("Process record does not support "
5912 "instruction sysenter.\n"));
5916 ret
= tdep
->i386_sysenter_record (ir
.regcache
);
5922 case 0x0f35: /* sysexit */
5923 printf_unfiltered (_("Process record does not support "
5924 "instruction sysexit.\n"));
5929 case 0x0f05: /* syscall */
5932 if (tdep
->i386_syscall_record
== NULL
)
5934 printf_unfiltered (_("Process record does not support "
5935 "instruction syscall.\n"));
5939 ret
= tdep
->i386_syscall_record (ir
.regcache
);
5945 case 0x0f07: /* sysret */
5946 printf_unfiltered (_("Process record does not support "
5947 "instruction sysret.\n"));
5952 case 0x0fa2: /* cpuid */
5953 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5954 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5955 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5956 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM
);
5959 case 0xf4: /* hlt */
5960 printf_unfiltered (_("Process record does not support "
5961 "instruction hlt.\n"));
5967 if (i386_record_modrm (&ir
))
5974 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5978 if (i386_record_lea_modrm (&ir
))
5987 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5991 opcode
= opcode
<< 8 | ir
.modrm
;
5998 if (i386_record_modrm (&ir
))
6009 opcode
= opcode
<< 8 | ir
.modrm
;
6012 if (ir
.override
>= 0)
6014 if (record_memory_query
)
6018 target_terminal_ours ();
6020 Process record ignores the memory change of instruction at address %s\n\
6021 because it can't get the value of the segment register.\n\
6022 Do you want to stop the program?"),
6023 paddress (gdbarch
, ir
.orig_addr
));
6024 target_terminal_inferior ();
6031 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
6033 if (record_arch_list_add_mem (addr64
, 2))
6036 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6038 if (record_arch_list_add_mem (addr64
, 8))
6043 if (record_arch_list_add_mem (addr64
, 4))
6054 case 0: /* monitor */
6057 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6061 opcode
= opcode
<< 8 | ir
.modrm
;
6069 if (ir
.override
>= 0)
6071 if (record_memory_query
)
6075 target_terminal_ours ();
6077 Process record ignores the memory change of instruction at address %s\n\
6078 because it can't get the value of the segment register.\n\
6079 Do you want to stop the program?"),
6080 paddress (gdbarch
, ir
.orig_addr
));
6081 target_terminal_inferior ();
6090 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
6092 if (record_arch_list_add_mem (addr64
, 2))
6095 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6097 if (record_arch_list_add_mem (addr64
, 8))
6102 if (record_arch_list_add_mem (addr64
, 4))
6114 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6115 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
6119 else if (ir
.rm
== 1)
6126 opcode
= opcode
<< 8 | ir
.modrm
;
6133 if (record_arch_list_add_reg (ir
.regcache
, ir
.rm
| ir
.rex_b
))
6139 if (i386_record_lea_modrm (&ir
))
6142 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6145 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6147 case 7: /* invlpg */
6150 if (ir
.rm
== 0 && ir
.regmap
[X86_RECORD_R8_REGNUM
])
6151 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM
);
6155 opcode
= opcode
<< 8 | ir
.modrm
;
6160 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6164 opcode
= opcode
<< 8 | ir
.modrm
;
6170 case 0x0f08: /* invd */
6171 case 0x0f09: /* wbinvd */
6174 case 0x63: /* arpl */
6175 if (i386_record_modrm (&ir
))
6177 if (ir
.mod
== 3 || ir
.regmap
[X86_RECORD_R8_REGNUM
])
6179 I386_RECORD_ARCH_LIST_ADD_REG (ir
.regmap
[X86_RECORD_R8_REGNUM
]
6180 ? (ir
.reg
| rex_r
) : ir
.rm
);
6184 ir
.ot
= ir
.dflag
? OT_LONG
: OT_WORD
;
6185 if (i386_record_lea_modrm (&ir
))
6188 if (!ir
.regmap
[X86_RECORD_R8_REGNUM
])
6189 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6192 case 0x0f02: /* lar */
6193 case 0x0f03: /* lsl */
6194 if (i386_record_modrm (&ir
))
6196 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
6197 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6201 if (i386_record_modrm (&ir
))
6203 if (ir
.mod
== 3 && ir
.reg
== 3)
6206 opcode
= opcode
<< 8 | ir
.modrm
;
6218 /* nop (multi byte) */
6221 case 0x0f20: /* mov reg, crN */
6222 case 0x0f22: /* mov crN, reg */
6223 if (i386_record_modrm (&ir
))
6225 if ((ir
.modrm
& 0xc0) != 0xc0)
6228 opcode
= opcode
<< 8 | ir
.modrm
;
6239 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6241 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6245 opcode
= opcode
<< 8 | ir
.modrm
;
6251 case 0x0f21: /* mov reg, drN */
6252 case 0x0f23: /* mov drN, reg */
6253 if (i386_record_modrm (&ir
))
6255 if ((ir
.modrm
& 0xc0) != 0xc0 || ir
.reg
== 4
6256 || ir
.reg
== 5 || ir
.reg
>= 8)
6259 opcode
= opcode
<< 8 | ir
.modrm
;
6263 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6265 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6268 case 0x0f06: /* clts */
6269 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6272 /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */
6274 case 0x0f0d: /* 3DNow! prefetch */
6277 case 0x0f0e: /* 3DNow! femms */
6278 case 0x0f77: /* emms */
6279 if (i386_fpc_regnum_p (gdbarch
, I387_FTAG_REGNUM(tdep
)))
6281 record_arch_list_add_reg (ir
.regcache
, I387_FTAG_REGNUM(tdep
));
6284 case 0x0f0f: /* 3DNow! data */
6285 if (i386_record_modrm (&ir
))
6287 if (target_read_memory (ir
.addr
, &opcode8
, 1))
6289 printf_unfiltered (_("Process record: error reading memory at "
6290 "addr %s len = 1.\n"),
6291 paddress (gdbarch
, ir
.addr
));
6297 case 0x0c: /* 3DNow! pi2fw */
6298 case 0x0d: /* 3DNow! pi2fd */
6299 case 0x1c: /* 3DNow! pf2iw */
6300 case 0x1d: /* 3DNow! pf2id */
6301 case 0x8a: /* 3DNow! pfnacc */
6302 case 0x8e: /* 3DNow! pfpnacc */
6303 case 0x90: /* 3DNow! pfcmpge */
6304 case 0x94: /* 3DNow! pfmin */
6305 case 0x96: /* 3DNow! pfrcp */
6306 case 0x97: /* 3DNow! pfrsqrt */
6307 case 0x9a: /* 3DNow! pfsub */
6308 case 0x9e: /* 3DNow! pfadd */
6309 case 0xa0: /* 3DNow! pfcmpgt */
6310 case 0xa4: /* 3DNow! pfmax */
6311 case 0xa6: /* 3DNow! pfrcpit1 */
6312 case 0xa7: /* 3DNow! pfrsqit1 */
6313 case 0xaa: /* 3DNow! pfsubr */
6314 case 0xae: /* 3DNow! pfacc */
6315 case 0xb0: /* 3DNow! pfcmpeq */
6316 case 0xb4: /* 3DNow! pfmul */
6317 case 0xb6: /* 3DNow! pfrcpit2 */
6318 case 0xb7: /* 3DNow! pmulhrw */
6319 case 0xbb: /* 3DNow! pswapd */
6320 case 0xbf: /* 3DNow! pavgusb */
6321 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.reg
))
6322 goto no_support_3dnow_data
;
6323 record_arch_list_add_reg (ir
.regcache
, ir
.reg
);
6327 no_support_3dnow_data
:
6328 opcode
= (opcode
<< 8) | opcode8
;
6334 case 0x0faa: /* rsm */
6335 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6336 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6337 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6338 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
6339 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM
);
6340 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
6341 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
6342 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
6343 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
6347 if (i386_record_modrm (&ir
))
6351 case 0: /* fxsave */
6355 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6356 if (i386_record_lea_modrm_addr (&ir
, &tmpu64
))
6358 if (record_arch_list_add_mem (tmpu64
, 512))
6363 case 1: /* fxrstor */
6367 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6369 for (i
= I387_MM0_REGNUM (tdep
);
6370 i386_mmx_regnum_p (gdbarch
, i
); i
++)
6371 record_arch_list_add_reg (ir
.regcache
, i
);
6373 for (i
= I387_XMM0_REGNUM (tdep
);
6374 i386_xmm_regnum_p (gdbarch
, i
); i
++)
6375 record_arch_list_add_reg (ir
.regcache
, i
);
6377 if (i386_mxcsr_regnum_p (gdbarch
, I387_MXCSR_REGNUM(tdep
)))
6378 record_arch_list_add_reg (ir
.regcache
, I387_MXCSR_REGNUM(tdep
));
6380 for (i
= I387_ST0_REGNUM (tdep
);
6381 i386_fp_regnum_p (gdbarch
, i
); i
++)
6382 record_arch_list_add_reg (ir
.regcache
, i
);
6384 for (i
= I387_FCTRL_REGNUM (tdep
);
6385 i386_fpc_regnum_p (gdbarch
, i
); i
++)
6386 record_arch_list_add_reg (ir
.regcache
, i
);
6390 case 2: /* ldmxcsr */
6391 if (!i386_mxcsr_regnum_p (gdbarch
, I387_MXCSR_REGNUM(tdep
)))
6393 record_arch_list_add_reg (ir
.regcache
, I387_MXCSR_REGNUM(tdep
));
6396 case 3: /* stmxcsr */
6398 if (i386_record_lea_modrm (&ir
))
6402 case 5: /* lfence */
6403 case 6: /* mfence */
6404 case 7: /* sfence clflush */
6408 opcode
= (opcode
<< 8) | ir
.modrm
;
6414 case 0x0fc3: /* movnti */
6415 ir
.ot
= (ir
.dflag
== 2) ? OT_QUAD
: OT_LONG
;
6416 if (i386_record_modrm (&ir
))
6421 if (i386_record_lea_modrm (&ir
))
6425 /* Add prefix to opcode. */
6552 reswitch_prefix_add
:
6560 if (target_read_memory (ir
.addr
, &opcode8
, 1))
6562 printf_unfiltered (_("Process record: error reading memory at "
6563 "addr %s len = 1.\n"),
6564 paddress (gdbarch
, ir
.addr
));
6568 opcode
= (uint32_t) opcode8
| opcode
<< 8;
6569 goto reswitch_prefix_add
;
6572 case 0x0f10: /* movups */
6573 case 0x660f10: /* movupd */
6574 case 0xf30f10: /* movss */
6575 case 0xf20f10: /* movsd */
6576 case 0x0f12: /* movlps */
6577 case 0x660f12: /* movlpd */
6578 case 0xf30f12: /* movsldup */
6579 case 0xf20f12: /* movddup */
6580 case 0x0f14: /* unpcklps */
6581 case 0x660f14: /* unpcklpd */
6582 case 0x0f15: /* unpckhps */
6583 case 0x660f15: /* unpckhpd */
6584 case 0x0f16: /* movhps */
6585 case 0x660f16: /* movhpd */
6586 case 0xf30f16: /* movshdup */
6587 case 0x0f28: /* movaps */
6588 case 0x660f28: /* movapd */
6589 case 0x0f2a: /* cvtpi2ps */
6590 case 0x660f2a: /* cvtpi2pd */
6591 case 0xf30f2a: /* cvtsi2ss */
6592 case 0xf20f2a: /* cvtsi2sd */
6593 case 0x0f2c: /* cvttps2pi */
6594 case 0x660f2c: /* cvttpd2pi */
6595 case 0x0f2d: /* cvtps2pi */
6596 case 0x660f2d: /* cvtpd2pi */
6597 case 0x660f3800: /* pshufb */
6598 case 0x660f3801: /* phaddw */
6599 case 0x660f3802: /* phaddd */
6600 case 0x660f3803: /* phaddsw */
6601 case 0x660f3804: /* pmaddubsw */
6602 case 0x660f3805: /* phsubw */
6603 case 0x660f3806: /* phsubd */
6604 case 0x660f3807: /* phsubsw */
6605 case 0x660f3808: /* psignb */
6606 case 0x660f3809: /* psignw */
6607 case 0x660f380a: /* psignd */
6608 case 0x660f380b: /* pmulhrsw */
6609 case 0x660f3810: /* pblendvb */
6610 case 0x660f3814: /* blendvps */
6611 case 0x660f3815: /* blendvpd */
6612 case 0x660f381c: /* pabsb */
6613 case 0x660f381d: /* pabsw */
6614 case 0x660f381e: /* pabsd */
6615 case 0x660f3820: /* pmovsxbw */
6616 case 0x660f3821: /* pmovsxbd */
6617 case 0x660f3822: /* pmovsxbq */
6618 case 0x660f3823: /* pmovsxwd */
6619 case 0x660f3824: /* pmovsxwq */
6620 case 0x660f3825: /* pmovsxdq */
6621 case 0x660f3828: /* pmuldq */
6622 case 0x660f3829: /* pcmpeqq */
6623 case 0x660f382a: /* movntdqa */
6624 case 0x660f3a08: /* roundps */
6625 case 0x660f3a09: /* roundpd */
6626 case 0x660f3a0a: /* roundss */
6627 case 0x660f3a0b: /* roundsd */
6628 case 0x660f3a0c: /* blendps */
6629 case 0x660f3a0d: /* blendpd */
6630 case 0x660f3a0e: /* pblendw */
6631 case 0x660f3a0f: /* palignr */
6632 case 0x660f3a20: /* pinsrb */
6633 case 0x660f3a21: /* insertps */
6634 case 0x660f3a22: /* pinsrd pinsrq */
6635 case 0x660f3a40: /* dpps */
6636 case 0x660f3a41: /* dppd */
6637 case 0x660f3a42: /* mpsadbw */
6638 case 0x660f3a60: /* pcmpestrm */
6639 case 0x660f3a61: /* pcmpestri */
6640 case 0x660f3a62: /* pcmpistrm */
6641 case 0x660f3a63: /* pcmpistri */
6642 case 0x0f51: /* sqrtps */
6643 case 0x660f51: /* sqrtpd */
6644 case 0xf20f51: /* sqrtsd */
6645 case 0xf30f51: /* sqrtss */
6646 case 0x0f52: /* rsqrtps */
6647 case 0xf30f52: /* rsqrtss */
6648 case 0x0f53: /* rcpps */
6649 case 0xf30f53: /* rcpss */
6650 case 0x0f54: /* andps */
6651 case 0x660f54: /* andpd */
6652 case 0x0f55: /* andnps */
6653 case 0x660f55: /* andnpd */
6654 case 0x0f56: /* orps */
6655 case 0x660f56: /* orpd */
6656 case 0x0f57: /* xorps */
6657 case 0x660f57: /* xorpd */
6658 case 0x0f58: /* addps */
6659 case 0x660f58: /* addpd */
6660 case 0xf20f58: /* addsd */
6661 case 0xf30f58: /* addss */
6662 case 0x0f59: /* mulps */
6663 case 0x660f59: /* mulpd */
6664 case 0xf20f59: /* mulsd */
6665 case 0xf30f59: /* mulss */
6666 case 0x0f5a: /* cvtps2pd */
6667 case 0x660f5a: /* cvtpd2ps */
6668 case 0xf20f5a: /* cvtsd2ss */
6669 case 0xf30f5a: /* cvtss2sd */
6670 case 0x0f5b: /* cvtdq2ps */
6671 case 0x660f5b: /* cvtps2dq */
6672 case 0xf30f5b: /* cvttps2dq */
6673 case 0x0f5c: /* subps */
6674 case 0x660f5c: /* subpd */
6675 case 0xf20f5c: /* subsd */
6676 case 0xf30f5c: /* subss */
6677 case 0x0f5d: /* minps */
6678 case 0x660f5d: /* minpd */
6679 case 0xf20f5d: /* minsd */
6680 case 0xf30f5d: /* minss */
6681 case 0x0f5e: /* divps */
6682 case 0x660f5e: /* divpd */
6683 case 0xf20f5e: /* divsd */
6684 case 0xf30f5e: /* divss */
6685 case 0x0f5f: /* maxps */
6686 case 0x660f5f: /* maxpd */
6687 case 0xf20f5f: /* maxsd */
6688 case 0xf30f5f: /* maxss */
6689 case 0x660f60: /* punpcklbw */
6690 case 0x660f61: /* punpcklwd */
6691 case 0x660f62: /* punpckldq */
6692 case 0x660f63: /* packsswb */
6693 case 0x660f64: /* pcmpgtb */
6694 case 0x660f65: /* pcmpgtw */
6695 case 0x660f66: /* pcmpgtd */
6696 case 0x660f67: /* packuswb */
6697 case 0x660f68: /* punpckhbw */
6698 case 0x660f69: /* punpckhwd */
6699 case 0x660f6a: /* punpckhdq */
6700 case 0x660f6b: /* packssdw */
6701 case 0x660f6c: /* punpcklqdq */
6702 case 0x660f6d: /* punpckhqdq */
6703 case 0x660f6e: /* movd */
6704 case 0x660f6f: /* movdqa */
6705 case 0xf30f6f: /* movdqu */
6706 case 0x660f70: /* pshufd */
6707 case 0xf20f70: /* pshuflw */
6708 case 0xf30f70: /* pshufhw */
6709 case 0x660f74: /* pcmpeqb */
6710 case 0x660f75: /* pcmpeqw */
6711 case 0x660f76: /* pcmpeqd */
6712 case 0x660f7c: /* haddpd */
6713 case 0xf20f7c: /* haddps */
6714 case 0x660f7d: /* hsubpd */
6715 case 0xf20f7d: /* hsubps */
6716 case 0xf30f7e: /* movq */
6717 case 0x0fc2: /* cmpps */
6718 case 0x660fc2: /* cmppd */
6719 case 0xf20fc2: /* cmpsd */
6720 case 0xf30fc2: /* cmpss */
6721 case 0x660fc4: /* pinsrw */
6722 case 0x0fc6: /* shufps */
6723 case 0x660fc6: /* shufpd */
6724 case 0x660fd0: /* addsubpd */
6725 case 0xf20fd0: /* addsubps */
6726 case 0x660fd1: /* psrlw */
6727 case 0x660fd2: /* psrld */
6728 case 0x660fd3: /* psrlq */
6729 case 0x660fd4: /* paddq */
6730 case 0x660fd5: /* pmullw */
6731 case 0xf30fd6: /* movq2dq */
6732 case 0x660fd8: /* psubusb */
6733 case 0x660fd9: /* psubusw */
6734 case 0x660fda: /* pminub */
6735 case 0x660fdb: /* pand */
6736 case 0x660fdc: /* paddusb */
6737 case 0x660fdd: /* paddusw */
6738 case 0x660fde: /* pmaxub */
6739 case 0x660fdf: /* pandn */
6740 case 0x660fe0: /* pavgb */
6741 case 0x660fe1: /* psraw */
6742 case 0x660fe2: /* psrad */
6743 case 0x660fe3: /* pavgw */
6744 case 0x660fe4: /* pmulhuw */
6745 case 0x660fe5: /* pmulhw */
6746 case 0x660fe6: /* cvttpd2dq */
6747 case 0xf20fe6: /* cvtpd2dq */
6748 case 0xf30fe6: /* cvtdq2pd */
6749 case 0x660fe8: /* psubsb */
6750 case 0x660fe9: /* psubsw */
6751 case 0x660fea: /* pminsw */
6752 case 0x660feb: /* por */
6753 case 0x660fec: /* paddsb */
6754 case 0x660fed: /* paddsw */
6755 case 0x660fee: /* pmaxsw */
6756 case 0x660fef: /* pxor */
6757 case 0xf20ff0: /* lddqu */
6758 case 0x660ff1: /* psllw */
6759 case 0x660ff2: /* pslld */
6760 case 0x660ff3: /* psllq */
6761 case 0x660ff4: /* pmuludq */
6762 case 0x660ff5: /* pmaddwd */
6763 case 0x660ff6: /* psadbw */
6764 case 0x660ff8: /* psubb */
6765 case 0x660ff9: /* psubw */
6766 case 0x660ffa: /* psubd */
6767 case 0x660ffb: /* psubq */
6768 case 0x660ffc: /* paddb */
6769 case 0x660ffd: /* paddw */
6770 case 0x660ffe: /* paddd */
6771 if (i386_record_modrm (&ir
))
6774 if (!i386_xmm_regnum_p (gdbarch
, I387_XMM0_REGNUM (tdep
) + ir
.reg
))
6776 record_arch_list_add_reg (ir
.regcache
,
6777 I387_XMM0_REGNUM (tdep
) + ir
.reg
);
6778 if ((opcode
& 0xfffffffc) == 0x660f3a60)
6779 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6782 case 0x0f11: /* movups */
6783 case 0x660f11: /* movupd */
6784 case 0xf30f11: /* movss */
6785 case 0xf20f11: /* movsd */
6786 case 0x0f13: /* movlps */
6787 case 0x660f13: /* movlpd */
6788 case 0x0f17: /* movhps */
6789 case 0x660f17: /* movhpd */
6790 case 0x0f29: /* movaps */
6791 case 0x660f29: /* movapd */
6792 case 0x660f3a14: /* pextrb */
6793 case 0x660f3a15: /* pextrw */
6794 case 0x660f3a16: /* pextrd pextrq */
6795 case 0x660f3a17: /* extractps */
6796 case 0x660f7f: /* movdqa */
6797 case 0xf30f7f: /* movdqu */
6798 if (i386_record_modrm (&ir
))
6802 if (opcode
== 0x0f13 || opcode
== 0x660f13
6803 || opcode
== 0x0f17 || opcode
== 0x660f17)
6806 if (!i386_xmm_regnum_p (gdbarch
,
6807 I387_XMM0_REGNUM (tdep
) + ir
.rm
))
6809 record_arch_list_add_reg (ir
.regcache
,
6810 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
6832 if (i386_record_lea_modrm (&ir
))
6837 case 0x0f2b: /* movntps */
6838 case 0x660f2b: /* movntpd */
6839 case 0x0fe7: /* movntq */
6840 case 0x660fe7: /* movntdq */
6843 if (opcode
== 0x0fe7)
6847 if (i386_record_lea_modrm (&ir
))
6851 case 0xf30f2c: /* cvttss2si */
6852 case 0xf20f2c: /* cvttsd2si */
6853 case 0xf30f2d: /* cvtss2si */
6854 case 0xf20f2d: /* cvtsd2si */
6855 case 0xf20f38f0: /* crc32 */
6856 case 0xf20f38f1: /* crc32 */
6857 case 0x0f50: /* movmskps */
6858 case 0x660f50: /* movmskpd */
6859 case 0x0fc5: /* pextrw */
6860 case 0x660fc5: /* pextrw */
6861 case 0x0fd7: /* pmovmskb */
6862 case 0x660fd7: /* pmovmskb */
6863 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
6866 case 0x0f3800: /* pshufb */
6867 case 0x0f3801: /* phaddw */
6868 case 0x0f3802: /* phaddd */
6869 case 0x0f3803: /* phaddsw */
6870 case 0x0f3804: /* pmaddubsw */
6871 case 0x0f3805: /* phsubw */
6872 case 0x0f3806: /* phsubd */
6873 case 0x0f3807: /* phsubsw */
6874 case 0x0f3808: /* psignb */
6875 case 0x0f3809: /* psignw */
6876 case 0x0f380a: /* psignd */
6877 case 0x0f380b: /* pmulhrsw */
6878 case 0x0f381c: /* pabsb */
6879 case 0x0f381d: /* pabsw */
6880 case 0x0f381e: /* pabsd */
6881 case 0x0f382b: /* packusdw */
6882 case 0x0f3830: /* pmovzxbw */
6883 case 0x0f3831: /* pmovzxbd */
6884 case 0x0f3832: /* pmovzxbq */
6885 case 0x0f3833: /* pmovzxwd */
6886 case 0x0f3834: /* pmovzxwq */
6887 case 0x0f3835: /* pmovzxdq */
6888 case 0x0f3837: /* pcmpgtq */
6889 case 0x0f3838: /* pminsb */
6890 case 0x0f3839: /* pminsd */
6891 case 0x0f383a: /* pminuw */
6892 case 0x0f383b: /* pminud */
6893 case 0x0f383c: /* pmaxsb */
6894 case 0x0f383d: /* pmaxsd */
6895 case 0x0f383e: /* pmaxuw */
6896 case 0x0f383f: /* pmaxud */
6897 case 0x0f3840: /* pmulld */
6898 case 0x0f3841: /* phminposuw */
6899 case 0x0f3a0f: /* palignr */
6900 case 0x0f60: /* punpcklbw */
6901 case 0x0f61: /* punpcklwd */
6902 case 0x0f62: /* punpckldq */
6903 case 0x0f63: /* packsswb */
6904 case 0x0f64: /* pcmpgtb */
6905 case 0x0f65: /* pcmpgtw */
6906 case 0x0f66: /* pcmpgtd */
6907 case 0x0f67: /* packuswb */
6908 case 0x0f68: /* punpckhbw */
6909 case 0x0f69: /* punpckhwd */
6910 case 0x0f6a: /* punpckhdq */
6911 case 0x0f6b: /* packssdw */
6912 case 0x0f6e: /* movd */
6913 case 0x0f6f: /* movq */
6914 case 0x0f70: /* pshufw */
6915 case 0x0f74: /* pcmpeqb */
6916 case 0x0f75: /* pcmpeqw */
6917 case 0x0f76: /* pcmpeqd */
6918 case 0x0fc4: /* pinsrw */
6919 case 0x0fd1: /* psrlw */
6920 case 0x0fd2: /* psrld */
6921 case 0x0fd3: /* psrlq */
6922 case 0x0fd4: /* paddq */
6923 case 0x0fd5: /* pmullw */
6924 case 0xf20fd6: /* movdq2q */
6925 case 0x0fd8: /* psubusb */
6926 case 0x0fd9: /* psubusw */
6927 case 0x0fda: /* pminub */
6928 case 0x0fdb: /* pand */
6929 case 0x0fdc: /* paddusb */
6930 case 0x0fdd: /* paddusw */
6931 case 0x0fde: /* pmaxub */
6932 case 0x0fdf: /* pandn */
6933 case 0x0fe0: /* pavgb */
6934 case 0x0fe1: /* psraw */
6935 case 0x0fe2: /* psrad */
6936 case 0x0fe3: /* pavgw */
6937 case 0x0fe4: /* pmulhuw */
6938 case 0x0fe5: /* pmulhw */
6939 case 0x0fe8: /* psubsb */
6940 case 0x0fe9: /* psubsw */
6941 case 0x0fea: /* pminsw */
6942 case 0x0feb: /* por */
6943 case 0x0fec: /* paddsb */
6944 case 0x0fed: /* paddsw */
6945 case 0x0fee: /* pmaxsw */
6946 case 0x0fef: /* pxor */
6947 case 0x0ff1: /* psllw */
6948 case 0x0ff2: /* pslld */
6949 case 0x0ff3: /* psllq */
6950 case 0x0ff4: /* pmuludq */
6951 case 0x0ff5: /* pmaddwd */
6952 case 0x0ff6: /* psadbw */
6953 case 0x0ff8: /* psubb */
6954 case 0x0ff9: /* psubw */
6955 case 0x0ffa: /* psubd */
6956 case 0x0ffb: /* psubq */
6957 case 0x0ffc: /* paddb */
6958 case 0x0ffd: /* paddw */
6959 case 0x0ffe: /* paddd */
6960 if (i386_record_modrm (&ir
))
6962 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.reg
))
6964 record_arch_list_add_reg (ir
.regcache
,
6965 I387_MM0_REGNUM (tdep
) + ir
.reg
);
6968 case 0x0f71: /* psllw */
6969 case 0x0f72: /* pslld */
6970 case 0x0f73: /* psllq */
6971 if (i386_record_modrm (&ir
))
6973 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.rm
))
6975 record_arch_list_add_reg (ir
.regcache
,
6976 I387_MM0_REGNUM (tdep
) + ir
.rm
);
6979 case 0x660f71: /* psllw */
6980 case 0x660f72: /* pslld */
6981 case 0x660f73: /* psllq */
6982 if (i386_record_modrm (&ir
))
6985 if (!i386_xmm_regnum_p (gdbarch
, I387_XMM0_REGNUM (tdep
) + ir
.rm
))
6987 record_arch_list_add_reg (ir
.regcache
,
6988 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
6991 case 0x0f7e: /* movd */
6992 case 0x660f7e: /* movd */
6993 if (i386_record_modrm (&ir
))
6996 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
7003 if (i386_record_lea_modrm (&ir
))
7008 case 0x0f7f: /* movq */
7009 if (i386_record_modrm (&ir
))
7013 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.rm
))
7015 record_arch_list_add_reg (ir
.regcache
,
7016 I387_MM0_REGNUM (tdep
) + ir
.rm
);
7021 if (i386_record_lea_modrm (&ir
))
7026 case 0xf30fb8: /* popcnt */
7027 if (i386_record_modrm (&ir
))
7029 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
7030 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7033 case 0x660fd6: /* movq */
7034 if (i386_record_modrm (&ir
))
7039 if (!i386_xmm_regnum_p (gdbarch
,
7040 I387_XMM0_REGNUM (tdep
) + ir
.rm
))
7042 record_arch_list_add_reg (ir
.regcache
,
7043 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
7048 if (i386_record_lea_modrm (&ir
))
7053 case 0x660f3817: /* ptest */
7054 case 0x0f2e: /* ucomiss */
7055 case 0x660f2e: /* ucomisd */
7056 case 0x0f2f: /* comiss */
7057 case 0x660f2f: /* comisd */
7058 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7061 case 0x0ff7: /* maskmovq */
7062 regcache_raw_read_unsigned (ir
.regcache
,
7063 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
7065 if (record_arch_list_add_mem (addr
, 64))
7069 case 0x660ff7: /* maskmovdqu */
7070 regcache_raw_read_unsigned (ir
.regcache
,
7071 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
7073 if (record_arch_list_add_mem (addr
, 128))
7088 /* In the future, maybe still need to deal with need_dasm. */
7089 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM
);
7090 if (record_arch_list_add_end ())
7096 printf_unfiltered (_("Process record does not support instruction 0x%02x "
7097 "at address %s.\n"),
7098 (unsigned int) (opcode
),
7099 paddress (gdbarch
, ir
.orig_addr
));
7103 static const int i386_record_regmap
[] =
7105 I386_EAX_REGNUM
, I386_ECX_REGNUM
, I386_EDX_REGNUM
, I386_EBX_REGNUM
,
7106 I386_ESP_REGNUM
, I386_EBP_REGNUM
, I386_ESI_REGNUM
, I386_EDI_REGNUM
,
7107 0, 0, 0, 0, 0, 0, 0, 0,
7108 I386_EIP_REGNUM
, I386_EFLAGS_REGNUM
, I386_CS_REGNUM
, I386_SS_REGNUM
,
7109 I386_DS_REGNUM
, I386_ES_REGNUM
, I386_FS_REGNUM
, I386_GS_REGNUM
7112 /* Check that the given address appears suitable for a fast
7113 tracepoint, which on x86-64 means that we need an instruction of at
7114 least 5 bytes, so that we can overwrite it with a 4-byte-offset
7115 jump and not have to worry about program jumps to an address in the
7116 middle of the tracepoint jump. On x86, it may be possible to use
7117 4-byte jumps with a 2-byte offset to a trampoline located in the
7118 bottom 64 KiB of memory. Returns 1 if OK, and writes a size
7119 of instruction to replace, and 0 if not, plus an explanatory
7123 i386_fast_tracepoint_valid_at (struct gdbarch
*gdbarch
,
7124 CORE_ADDR addr
, int *isize
, char **msg
)
7127 static struct ui_file
*gdb_null
= NULL
;
7129 /* Ask the target for the minimum instruction length supported. */
7130 jumplen
= target_get_min_fast_tracepoint_insn_len ();
7134 /* If the target does not support the get_min_fast_tracepoint_insn_len
7135 operation, assume that fast tracepoints will always be implemented
7136 using 4-byte relative jumps on both x86 and x86-64. */
7139 else if (jumplen
== 0)
7141 /* If the target does support get_min_fast_tracepoint_insn_len but
7142 returns zero, then the IPA has not loaded yet. In this case,
7143 we optimistically assume that truncated 2-byte relative jumps
7144 will be available on x86, and compensate later if this assumption
7145 turns out to be incorrect. On x86-64 architectures, 4-byte relative
7146 jumps will always be used. */
7147 jumplen
= (register_size (gdbarch
, 0) == 8) ? 5 : 4;
7150 /* Dummy file descriptor for the disassembler. */
7152 gdb_null
= ui_file_new ();
7154 /* Check for fit. */
7155 len
= gdb_print_insn (gdbarch
, addr
, gdb_null
, NULL
);
7161 /* Return a bit of target-specific detail to add to the caller's
7162 generic failure message. */
7164 *msg
= xstrprintf (_("; instruction is only %d bytes long, "
7165 "need at least %d bytes for the jump"),
7178 i386_validate_tdesc_p (struct gdbarch_tdep
*tdep
,
7179 struct tdesc_arch_data
*tdesc_data
)
7181 const struct target_desc
*tdesc
= tdep
->tdesc
;
7182 const struct tdesc_feature
*feature_core
;
7183 const struct tdesc_feature
*feature_sse
, *feature_avx
;
7184 int i
, num_regs
, valid_p
;
7186 if (! tdesc_has_registers (tdesc
))
7189 /* Get core registers. */
7190 feature_core
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.core");
7191 if (feature_core
== NULL
)
7194 /* Get SSE registers. */
7195 feature_sse
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.sse");
7197 /* Try AVX registers. */
7198 feature_avx
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx");
7202 /* The XCR0 bits. */
7205 /* AVX register description requires SSE register description. */
7209 tdep
->xcr0
= I386_XSTATE_AVX_MASK
;
7211 /* It may have been set by OSABI initialization function. */
7212 if (tdep
->num_ymm_regs
== 0)
7214 tdep
->ymmh_register_names
= i386_ymmh_names
;
7215 tdep
->num_ymm_regs
= 8;
7216 tdep
->ymm0h_regnum
= I386_YMM0H_REGNUM
;
7219 for (i
= 0; i
< tdep
->num_ymm_regs
; i
++)
7220 valid_p
&= tdesc_numbered_register (feature_avx
, tdesc_data
,
7221 tdep
->ymm0h_regnum
+ i
,
7222 tdep
->ymmh_register_names
[i
]);
7224 else if (feature_sse
)
7225 tdep
->xcr0
= I386_XSTATE_SSE_MASK
;
7228 tdep
->xcr0
= I386_XSTATE_X87_MASK
;
7229 tdep
->num_xmm_regs
= 0;
7232 num_regs
= tdep
->num_core_regs
;
7233 for (i
= 0; i
< num_regs
; i
++)
7234 valid_p
&= tdesc_numbered_register (feature_core
, tdesc_data
, i
,
7235 tdep
->register_names
[i
]);
7239 /* Need to include %mxcsr, so add one. */
7240 num_regs
+= tdep
->num_xmm_regs
+ 1;
7241 for (; i
< num_regs
; i
++)
7242 valid_p
&= tdesc_numbered_register (feature_sse
, tdesc_data
, i
,
7243 tdep
->register_names
[i
]);
7250 static struct gdbarch
*
7251 i386_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
7253 struct gdbarch_tdep
*tdep
;
7254 struct gdbarch
*gdbarch
;
7255 struct tdesc_arch_data
*tdesc_data
;
7256 const struct target_desc
*tdesc
;
7260 /* If there is already a candidate, use it. */
7261 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
7263 return arches
->gdbarch
;
7265 /* Allocate space for the new architecture. */
7266 tdep
= XCALLOC (1, struct gdbarch_tdep
);
7267 gdbarch
= gdbarch_alloc (&info
, tdep
);
7269 /* General-purpose registers. */
7270 tdep
->gregset
= NULL
;
7271 tdep
->gregset_reg_offset
= NULL
;
7272 tdep
->gregset_num_regs
= I386_NUM_GREGS
;
7273 tdep
->sizeof_gregset
= 0;
7275 /* Floating-point registers. */
7276 tdep
->fpregset
= NULL
;
7277 tdep
->sizeof_fpregset
= I387_SIZEOF_FSAVE
;
7279 tdep
->xstateregset
= NULL
;
7281 /* The default settings include the FPU registers, the MMX registers
7282 and the SSE registers. This can be overridden for a specific ABI
7283 by adjusting the members `st0_regnum', `mm0_regnum' and
7284 `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers
7285 will show up in the output of "info all-registers". */
7287 tdep
->st0_regnum
= I386_ST0_REGNUM
;
7289 /* I386_NUM_XREGS includes %mxcsr, so substract one. */
7290 tdep
->num_xmm_regs
= I386_NUM_XREGS
- 1;
7292 tdep
->jb_pc_offset
= -1;
7293 tdep
->struct_return
= pcc_struct_return
;
7294 tdep
->sigtramp_start
= 0;
7295 tdep
->sigtramp_end
= 0;
7296 tdep
->sigtramp_p
= i386_sigtramp_p
;
7297 tdep
->sigcontext_addr
= NULL
;
7298 tdep
->sc_reg_offset
= NULL
;
7299 tdep
->sc_pc_offset
= -1;
7300 tdep
->sc_sp_offset
= -1;
7302 tdep
->xsave_xcr0_offset
= -1;
7304 tdep
->record_regmap
= i386_record_regmap
;
7306 set_gdbarch_long_long_align_bit (gdbarch
, 32);
7308 /* The format used for `long double' on almost all i386 targets is
7309 the i387 extended floating-point format. In fact, of all targets
7310 in the GCC 2.95 tree, only OSF/1 does it different, and insists
7311 on having a `long double' that's not `long' at all. */
7312 set_gdbarch_long_double_format (gdbarch
, floatformats_i387_ext
);
7314 /* Although the i387 extended floating-point has only 80 significant
7315 bits, a `long double' actually takes up 96, probably to enforce
7317 set_gdbarch_long_double_bit (gdbarch
, 96);
7319 /* Register numbers of various important registers. */
7320 set_gdbarch_sp_regnum (gdbarch
, I386_ESP_REGNUM
); /* %esp */
7321 set_gdbarch_pc_regnum (gdbarch
, I386_EIP_REGNUM
); /* %eip */
7322 set_gdbarch_ps_regnum (gdbarch
, I386_EFLAGS_REGNUM
); /* %eflags */
7323 set_gdbarch_fp0_regnum (gdbarch
, I386_ST0_REGNUM
); /* %st(0) */
7325 /* NOTE: kettenis/20040418: GCC does have two possible register
7326 numbering schemes on the i386: dbx and SVR4. These schemes
7327 differ in how they number %ebp, %esp, %eflags, and the
7328 floating-point registers, and are implemented by the arrays
7329 dbx_register_map[] and svr4_dbx_register_map in
7330 gcc/config/i386.c. GCC also defines a third numbering scheme in
7331 gcc/config/i386.c, which it designates as the "default" register
7332 map used in 64bit mode. This last register numbering scheme is
7333 implemented in dbx64_register_map, and is used for AMD64; see
7336 Currently, each GCC i386 target always uses the same register
7337 numbering scheme across all its supported debugging formats
7338 i.e. SDB (COFF), stabs and DWARF 2. This is because
7339 gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the
7340 DBX_REGISTER_NUMBER macro which is defined by each target's
7341 respective config header in a manner independent of the requested
7342 output debugging format.
7344 This does not match the arrangement below, which presumes that
7345 the SDB and stabs numbering schemes differ from the DWARF and
7346 DWARF 2 ones. The reason for this arrangement is that it is
7347 likely to get the numbering scheme for the target's
7348 default/native debug format right. For targets where GCC is the
7349 native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for
7350 targets where the native toolchain uses a different numbering
7351 scheme for a particular debug format (stabs-in-ELF on Solaris)
7352 the defaults below will have to be overridden, like
7353 i386_elf_init_abi() does. */
7355 /* Use the dbx register numbering scheme for stabs and COFF. */
7356 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
7357 set_gdbarch_sdb_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
7359 /* Use the SVR4 register numbering scheme for DWARF 2. */
7360 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
7362 /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to
7363 be in use on any of the supported i386 targets. */
7365 set_gdbarch_print_float_info (gdbarch
, i387_print_float_info
);
7367 set_gdbarch_get_longjmp_target (gdbarch
, i386_get_longjmp_target
);
7369 /* Call dummy code. */
7370 set_gdbarch_push_dummy_call (gdbarch
, i386_push_dummy_call
);
7371 set_gdbarch_frame_align (gdbarch
, i386_frame_align
);
7373 set_gdbarch_convert_register_p (gdbarch
, i386_convert_register_p
);
7374 set_gdbarch_register_to_value (gdbarch
, i386_register_to_value
);
7375 set_gdbarch_value_to_register (gdbarch
, i386_value_to_register
);
7377 set_gdbarch_return_value (gdbarch
, i386_return_value
);
7379 set_gdbarch_skip_prologue (gdbarch
, i386_skip_prologue
);
7381 /* Stack grows downward. */
7382 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
7384 set_gdbarch_breakpoint_from_pc (gdbarch
, i386_breakpoint_from_pc
);
7385 set_gdbarch_decr_pc_after_break (gdbarch
, 1);
7386 set_gdbarch_max_insn_length (gdbarch
, I386_MAX_INSN_LEN
);
7388 set_gdbarch_frame_args_skip (gdbarch
, 8);
7390 set_gdbarch_print_insn (gdbarch
, i386_print_insn
);
7392 set_gdbarch_dummy_id (gdbarch
, i386_dummy_id
);
7394 set_gdbarch_unwind_pc (gdbarch
, i386_unwind_pc
);
7396 /* Add the i386 register groups. */
7397 i386_add_reggroups (gdbarch
);
7398 tdep
->register_reggroup_p
= i386_register_reggroup_p
;
7400 /* Helper for function argument information. */
7401 set_gdbarch_fetch_pointer_argument (gdbarch
, i386_fetch_pointer_argument
);
7403 /* Hook the function epilogue frame unwinder. This unwinder is
7404 appended to the list first, so that it supercedes the DWARF
7405 unwinder in function epilogues (where the DWARF unwinder
7406 currently fails). */
7407 frame_unwind_append_unwinder (gdbarch
, &i386_epilogue_frame_unwind
);
7409 /* Hook in the DWARF CFI frame unwinder. This unwinder is appended
7410 to the list before the prologue-based unwinders, so that DWARF
7411 CFI info will be used if it is available. */
7412 dwarf2_append_unwinders (gdbarch
);
7414 frame_base_set_default (gdbarch
, &i386_frame_base
);
7416 /* Pseudo registers may be changed by amd64_init_abi. */
7417 set_gdbarch_pseudo_register_read_value (gdbarch
,
7418 i386_pseudo_register_read_value
);
7419 set_gdbarch_pseudo_register_write (gdbarch
, i386_pseudo_register_write
);
7421 set_tdesc_pseudo_register_type (gdbarch
, i386_pseudo_register_type
);
7422 set_tdesc_pseudo_register_name (gdbarch
, i386_pseudo_register_name
);
7424 /* Override the normal target description method to make the AVX
7425 upper halves anonymous. */
7426 set_gdbarch_register_name (gdbarch
, i386_register_name
);
7428 /* Even though the default ABI only includes general-purpose registers,
7429 floating-point registers and the SSE registers, we have to leave a
7430 gap for the upper AVX registers. */
7431 set_gdbarch_num_regs (gdbarch
, I386_AVX_NUM_REGS
);
7433 /* Get the x86 target description from INFO. */
7434 tdesc
= info
.target_desc
;
7435 if (! tdesc_has_registers (tdesc
))
7437 tdep
->tdesc
= tdesc
;
7439 tdep
->num_core_regs
= I386_NUM_GREGS
+ I387_NUM_REGS
;
7440 tdep
->register_names
= i386_register_names
;
7442 /* No upper YMM registers. */
7443 tdep
->ymmh_register_names
= NULL
;
7444 tdep
->ymm0h_regnum
= -1;
7446 tdep
->num_byte_regs
= 8;
7447 tdep
->num_word_regs
= 8;
7448 tdep
->num_dword_regs
= 0;
7449 tdep
->num_mmx_regs
= 8;
7450 tdep
->num_ymm_regs
= 0;
7452 tdesc_data
= tdesc_data_alloc ();
7454 set_gdbarch_relocate_instruction (gdbarch
, i386_relocate_instruction
);
7456 set_gdbarch_gen_return_address (gdbarch
, i386_gen_return_address
);
7458 /* Hook in ABI-specific overrides, if they have been registered. */
7459 info
.tdep_info
= (void *) tdesc_data
;
7460 gdbarch_init_osabi (info
, gdbarch
);
7462 if (!i386_validate_tdesc_p (tdep
, tdesc_data
))
7464 tdesc_data_cleanup (tdesc_data
);
7466 gdbarch_free (gdbarch
);
7470 /* Wire in pseudo registers. Number of pseudo registers may be
7472 set_gdbarch_num_pseudo_regs (gdbarch
, (tdep
->num_byte_regs
7473 + tdep
->num_word_regs
7474 + tdep
->num_dword_regs
7475 + tdep
->num_mmx_regs
7476 + tdep
->num_ymm_regs
));
7478 /* Target description may be changed. */
7479 tdesc
= tdep
->tdesc
;
7481 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
7483 /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */
7484 set_gdbarch_register_reggroup_p (gdbarch
, tdep
->register_reggroup_p
);
7486 /* Make %al the first pseudo-register. */
7487 tdep
->al_regnum
= gdbarch_num_regs (gdbarch
);
7488 tdep
->ax_regnum
= tdep
->al_regnum
+ tdep
->num_byte_regs
;
7490 ymm0_regnum
= tdep
->ax_regnum
+ tdep
->num_word_regs
;
7491 if (tdep
->num_dword_regs
)
7493 /* Support dword pseudo-register if it hasn't been disabled. */
7494 tdep
->eax_regnum
= ymm0_regnum
;
7495 ymm0_regnum
+= tdep
->num_dword_regs
;
7498 tdep
->eax_regnum
= -1;
7500 mm0_regnum
= ymm0_regnum
;
7501 if (tdep
->num_ymm_regs
)
7503 /* Support YMM pseudo-register if it is available. */
7504 tdep
->ymm0_regnum
= ymm0_regnum
;
7505 mm0_regnum
+= tdep
->num_ymm_regs
;
7508 tdep
->ymm0_regnum
= -1;
7510 if (tdep
->num_mmx_regs
!= 0)
7512 /* Support MMX pseudo-register if MMX hasn't been disabled. */
7513 tdep
->mm0_regnum
= mm0_regnum
;
7516 tdep
->mm0_regnum
= -1;
7518 /* Hook in the legacy prologue-based unwinders last (fallback). */
7519 frame_unwind_append_unwinder (gdbarch
, &i386_stack_tramp_frame_unwind
);
7520 frame_unwind_append_unwinder (gdbarch
, &i386_sigtramp_frame_unwind
);
7521 frame_unwind_append_unwinder (gdbarch
, &i386_frame_unwind
);
7523 /* If we have a register mapping, enable the generic core file
7524 support, unless it has already been enabled. */
7525 if (tdep
->gregset_reg_offset
7526 && !gdbarch_regset_from_core_section_p (gdbarch
))
7527 set_gdbarch_regset_from_core_section (gdbarch
,
7528 i386_regset_from_core_section
);
7530 set_gdbarch_skip_permanent_breakpoint (gdbarch
,
7531 i386_skip_permanent_breakpoint
);
7533 set_gdbarch_fast_tracepoint_valid_at (gdbarch
,
7534 i386_fast_tracepoint_valid_at
);
7539 static enum gdb_osabi
7540 i386_coff_osabi_sniffer (bfd
*abfd
)
7542 if (strcmp (bfd_get_target (abfd
), "coff-go32-exe") == 0
7543 || strcmp (bfd_get_target (abfd
), "coff-go32") == 0)
7544 return GDB_OSABI_GO32
;
7546 return GDB_OSABI_UNKNOWN
;
7550 /* Provide a prototype to silence -Wmissing-prototypes. */
7551 void _initialize_i386_tdep (void);
7554 _initialize_i386_tdep (void)
7556 register_gdbarch_init (bfd_arch_i386
, i386_gdbarch_init
);
7558 /* Add the variable that controls the disassembly flavor. */
7559 add_setshow_enum_cmd ("disassembly-flavor", no_class
, valid_flavors
,
7560 &disassembly_flavor
, _("\
7561 Set the disassembly flavor."), _("\
7562 Show the disassembly flavor."), _("\
7563 The valid values are \"att\" and \"intel\", and the default value is \"att\"."),
7565 NULL
, /* FIXME: i18n: */
7566 &setlist
, &showlist
);
7568 /* Add the variable that controls the convention for returning
7570 add_setshow_enum_cmd ("struct-convention", no_class
, valid_conventions
,
7571 &struct_convention
, _("\
7572 Set the convention for returning small structs."), _("\
7573 Show the convention for returning small structs."), _("\
7574 Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\
7577 NULL
, /* FIXME: i18n: */
7578 &setlist
, &showlist
);
7580 gdbarch_register_osabi_sniffer (bfd_arch_i386
, bfd_target_coff_flavour
,
7581 i386_coff_osabi_sniffer
);
7583 gdbarch_register_osabi (bfd_arch_i386
, 0, GDB_OSABI_SVR4
,
7584 i386_svr4_init_abi
);
7585 gdbarch_register_osabi (bfd_arch_i386
, 0, GDB_OSABI_GO32
,
7586 i386_go32_init_abi
);
7588 /* Initialize the i386-specific register groups. */
7589 i386_init_reggroups ();
7591 /* Initialize the standard target descriptions. */
7592 initialize_tdesc_i386 ();
7593 initialize_tdesc_i386_mmx ();
7594 initialize_tdesc_i386_avx ();
7596 /* Tell remote stub that we support XML target description. */
7597 register_remote_support_xml ("i386");