1 /* Intel 386 target-dependent stuff.
3 Copyright (C) 1988-2014 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "opcode/i386.h"
22 #include "arch-utils.h"
24 #include "dummy-frame.h"
25 #include "dwarf2-frame.h"
28 #include "frame-base.h"
29 #include "frame-unwind.h"
37 #include "reggroups.h"
46 #include "exceptions.h"
47 #include "gdb_assert.h"
50 #include "i386-tdep.h"
51 #include "i387-tdep.h"
52 #include "i386-xstate.h"
55 #include "record-full.h"
58 #include "features/i386/i386.c"
59 #include "features/i386/i386-avx.c"
60 #include "features/i386/i386-mpx.c"
61 #include "features/i386/i386-mmx.c"
66 #include "stap-probe.h"
67 #include "user-regs.h"
68 #include "cli/cli-utils.h"
69 #include "expression.h"
70 #include "parser-defs.h"
75 static const char *i386_register_names
[] =
77 "eax", "ecx", "edx", "ebx",
78 "esp", "ebp", "esi", "edi",
79 "eip", "eflags", "cs", "ss",
80 "ds", "es", "fs", "gs",
81 "st0", "st1", "st2", "st3",
82 "st4", "st5", "st6", "st7",
83 "fctrl", "fstat", "ftag", "fiseg",
84 "fioff", "foseg", "fooff", "fop",
85 "xmm0", "xmm1", "xmm2", "xmm3",
86 "xmm4", "xmm5", "xmm6", "xmm7",
90 static const char *i386_ymm_names
[] =
92 "ymm0", "ymm1", "ymm2", "ymm3",
93 "ymm4", "ymm5", "ymm6", "ymm7",
96 static const char *i386_ymmh_names
[] =
98 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
99 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
102 static const char *i386_mpx_names
[] =
104 "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus"
107 /* Register names for MPX pseudo-registers. */
109 static const char *i386_bnd_names
[] =
111 "bnd0", "bnd1", "bnd2", "bnd3"
114 /* Register names for MMX pseudo-registers. */
116 static const char *i386_mmx_names
[] =
118 "mm0", "mm1", "mm2", "mm3",
119 "mm4", "mm5", "mm6", "mm7"
122 /* Register names for byte pseudo-registers. */
124 static const char *i386_byte_names
[] =
126 "al", "cl", "dl", "bl",
127 "ah", "ch", "dh", "bh"
130 /* Register names for word pseudo-registers. */
132 static const char *i386_word_names
[] =
134 "ax", "cx", "dx", "bx",
141 i386_mmx_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
143 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
144 int mm0_regnum
= tdep
->mm0_regnum
;
149 regnum
-= mm0_regnum
;
150 return regnum
>= 0 && regnum
< tdep
->num_mmx_regs
;
156 i386_byte_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
158 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
160 regnum
-= tdep
->al_regnum
;
161 return regnum
>= 0 && regnum
< tdep
->num_byte_regs
;
167 i386_word_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
169 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
171 regnum
-= tdep
->ax_regnum
;
172 return regnum
>= 0 && regnum
< tdep
->num_word_regs
;
175 /* Dword register? */
178 i386_dword_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
180 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
181 int eax_regnum
= tdep
->eax_regnum
;
186 regnum
-= eax_regnum
;
187 return regnum
>= 0 && regnum
< tdep
->num_dword_regs
;
191 i386_ymmh_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
193 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
194 int ymm0h_regnum
= tdep
->ymm0h_regnum
;
196 if (ymm0h_regnum
< 0)
199 regnum
-= ymm0h_regnum
;
200 return regnum
>= 0 && regnum
< tdep
->num_ymm_regs
;
206 i386_ymm_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
208 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
209 int ymm0_regnum
= tdep
->ymm0_regnum
;
214 regnum
-= ymm0_regnum
;
215 return regnum
>= 0 && regnum
< tdep
->num_ymm_regs
;
221 i386_bnd_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
223 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
224 int bnd0_regnum
= tdep
->bnd0_regnum
;
229 regnum
-= bnd0_regnum
;
230 return regnum
>= 0 && regnum
< I387_NUM_BND_REGS
;
236 i386_xmm_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
238 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
239 int num_xmm_regs
= I387_NUM_XMM_REGS (tdep
);
241 if (num_xmm_regs
== 0)
244 regnum
-= I387_XMM0_REGNUM (tdep
);
245 return regnum
>= 0 && regnum
< num_xmm_regs
;
249 i386_mxcsr_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
251 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
253 if (I387_NUM_XMM_REGS (tdep
) == 0)
256 return (regnum
== I387_MXCSR_REGNUM (tdep
));
262 i386_fp_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
264 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
266 if (I387_ST0_REGNUM (tdep
) < 0)
269 return (I387_ST0_REGNUM (tdep
) <= regnum
270 && regnum
< I387_FCTRL_REGNUM (tdep
));
274 i386_fpc_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
276 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
278 if (I387_ST0_REGNUM (tdep
) < 0)
281 return (I387_FCTRL_REGNUM (tdep
) <= regnum
282 && regnum
< I387_XMM0_REGNUM (tdep
));
285 /* BNDr (raw) register? */
288 i386_bndr_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
290 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
292 if (I387_BND0R_REGNUM (tdep
) < 0)
295 regnum
-= tdep
->bnd0r_regnum
;
296 return regnum
>= 0 && regnum
< I387_NUM_BND_REGS
;
299 /* BND control register? */
302 i386_mpx_ctrl_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
304 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
306 if (I387_BNDCFGU_REGNUM (tdep
) < 0)
309 regnum
-= I387_BNDCFGU_REGNUM (tdep
);
310 return regnum
>= 0 && regnum
< I387_NUM_MPX_CTRL_REGS
;
313 /* Return the name of register REGNUM, or the empty string if it is
314 an anonymous register. */
317 i386_register_name (struct gdbarch
*gdbarch
, int regnum
)
319 /* Hide the upper YMM registers. */
320 if (i386_ymmh_regnum_p (gdbarch
, regnum
))
323 return tdesc_register_name (gdbarch
, regnum
);
326 /* Return the name of register REGNUM. */
329 i386_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
331 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
332 if (i386_bnd_regnum_p (gdbarch
, regnum
))
333 return i386_bnd_names
[regnum
- tdep
->bnd0_regnum
];
334 if (i386_mmx_regnum_p (gdbarch
, regnum
))
335 return i386_mmx_names
[regnum
- I387_MM0_REGNUM (tdep
)];
336 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
337 return i386_ymm_names
[regnum
- tdep
->ymm0_regnum
];
338 else if (i386_byte_regnum_p (gdbarch
, regnum
))
339 return i386_byte_names
[regnum
- tdep
->al_regnum
];
340 else if (i386_word_regnum_p (gdbarch
, regnum
))
341 return i386_word_names
[regnum
- tdep
->ax_regnum
];
343 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
346 /* Convert a dbx register number REG to the appropriate register
347 number used by GDB. */
350 i386_dbx_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
352 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
354 /* This implements what GCC calls the "default" register map
355 (dbx_register_map[]). */
357 if (reg
>= 0 && reg
<= 7)
359 /* General-purpose registers. The debug info calls %ebp
360 register 4, and %esp register 5. */
367 else if (reg
>= 12 && reg
<= 19)
369 /* Floating-point registers. */
370 return reg
- 12 + I387_ST0_REGNUM (tdep
);
372 else if (reg
>= 21 && reg
<= 28)
375 int ymm0_regnum
= tdep
->ymm0_regnum
;
378 && i386_xmm_regnum_p (gdbarch
, reg
))
379 return reg
- 21 + ymm0_regnum
;
381 return reg
- 21 + I387_XMM0_REGNUM (tdep
);
383 else if (reg
>= 29 && reg
<= 36)
386 return reg
- 29 + I387_MM0_REGNUM (tdep
);
389 /* This will hopefully provoke a warning. */
390 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
393 /* Convert SVR4 register number REG to the appropriate register number
397 i386_svr4_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
399 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
401 /* This implements the GCC register map that tries to be compatible
402 with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */
404 /* The SVR4 register numbering includes %eip and %eflags, and
405 numbers the floating point registers differently. */
406 if (reg
>= 0 && reg
<= 9)
408 /* General-purpose registers. */
411 else if (reg
>= 11 && reg
<= 18)
413 /* Floating-point registers. */
414 return reg
- 11 + I387_ST0_REGNUM (tdep
);
416 else if (reg
>= 21 && reg
<= 36)
418 /* The SSE and MMX registers have the same numbers as with dbx. */
419 return i386_dbx_reg_to_regnum (gdbarch
, reg
);
424 case 37: return I387_FCTRL_REGNUM (tdep
);
425 case 38: return I387_FSTAT_REGNUM (tdep
);
426 case 39: return I387_MXCSR_REGNUM (tdep
);
427 case 40: return I386_ES_REGNUM
;
428 case 41: return I386_CS_REGNUM
;
429 case 42: return I386_SS_REGNUM
;
430 case 43: return I386_DS_REGNUM
;
431 case 44: return I386_FS_REGNUM
;
432 case 45: return I386_GS_REGNUM
;
435 /* This will hopefully provoke a warning. */
436 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
441 /* This is the variable that is set with "set disassembly-flavor", and
442 its legitimate values. */
443 static const char att_flavor
[] = "att";
444 static const char intel_flavor
[] = "intel";
445 static const char *const valid_flavors
[] =
451 static const char *disassembly_flavor
= att_flavor
;
454 /* Use the program counter to determine the contents and size of a
455 breakpoint instruction. Return a pointer to a string of bytes that
456 encode a breakpoint instruction, store the length of the string in
457 *LEN and optionally adjust *PC to point to the correct memory
458 location for inserting the breakpoint.
460 On the i386 we have a single breakpoint that fits in a single byte
461 and can be inserted anywhere.
463 This function is 64-bit safe. */
465 static const gdb_byte
*
466 i386_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pc
, int *len
)
468 static gdb_byte break_insn
[] = { 0xcc }; /* int 3 */
470 *len
= sizeof (break_insn
);
474 /* Displaced instruction handling. */
476 /* Skip the legacy instruction prefixes in INSN.
477 Not all prefixes are valid for any particular insn
478 but we needn't care, the insn will fault if it's invalid.
479 The result is a pointer to the first opcode byte,
480 or NULL if we run off the end of the buffer. */
483 i386_skip_prefixes (gdb_byte
*insn
, size_t max_len
)
485 gdb_byte
*end
= insn
+ max_len
;
491 case DATA_PREFIX_OPCODE
:
492 case ADDR_PREFIX_OPCODE
:
493 case CS_PREFIX_OPCODE
:
494 case DS_PREFIX_OPCODE
:
495 case ES_PREFIX_OPCODE
:
496 case FS_PREFIX_OPCODE
:
497 case GS_PREFIX_OPCODE
:
498 case SS_PREFIX_OPCODE
:
499 case LOCK_PREFIX_OPCODE
:
500 case REPE_PREFIX_OPCODE
:
501 case REPNE_PREFIX_OPCODE
:
513 i386_absolute_jmp_p (const gdb_byte
*insn
)
515 /* jmp far (absolute address in operand). */
521 /* jump near, absolute indirect (/4). */
522 if ((insn
[1] & 0x38) == 0x20)
525 /* jump far, absolute indirect (/5). */
526 if ((insn
[1] & 0x38) == 0x28)
533 /* Return non-zero if INSN is a jump, zero otherwise. */
536 i386_jmp_p (const gdb_byte
*insn
)
538 /* jump short, relative. */
542 /* jump near, relative. */
546 return i386_absolute_jmp_p (insn
);
550 i386_absolute_call_p (const gdb_byte
*insn
)
552 /* call far, absolute. */
558 /* Call near, absolute indirect (/2). */
559 if ((insn
[1] & 0x38) == 0x10)
562 /* Call far, absolute indirect (/3). */
563 if ((insn
[1] & 0x38) == 0x18)
571 i386_ret_p (const gdb_byte
*insn
)
575 case 0xc2: /* ret near, pop N bytes. */
576 case 0xc3: /* ret near */
577 case 0xca: /* ret far, pop N bytes. */
578 case 0xcb: /* ret far */
579 case 0xcf: /* iret */
588 i386_call_p (const gdb_byte
*insn
)
590 if (i386_absolute_call_p (insn
))
593 /* call near, relative. */
600 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
601 length in bytes. Otherwise, return zero. */
604 i386_syscall_p (const gdb_byte
*insn
, int *lengthp
)
606 /* Is it 'int $0x80'? */
607 if ((insn
[0] == 0xcd && insn
[1] == 0x80)
608 /* Or is it 'sysenter'? */
609 || (insn
[0] == 0x0f && insn
[1] == 0x34)
610 /* Or is it 'syscall'? */
611 || (insn
[0] == 0x0f && insn
[1] == 0x05))
620 /* The gdbarch insn_is_call method. */
623 i386_insn_is_call (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
625 gdb_byte buf
[I386_MAX_INSN_LEN
], *insn
;
627 read_code (addr
, buf
, I386_MAX_INSN_LEN
);
628 insn
= i386_skip_prefixes (buf
, I386_MAX_INSN_LEN
);
630 return i386_call_p (insn
);
633 /* The gdbarch insn_is_ret method. */
636 i386_insn_is_ret (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
638 gdb_byte buf
[I386_MAX_INSN_LEN
], *insn
;
640 read_code (addr
, buf
, I386_MAX_INSN_LEN
);
641 insn
= i386_skip_prefixes (buf
, I386_MAX_INSN_LEN
);
643 return i386_ret_p (insn
);
646 /* The gdbarch insn_is_jump method. */
649 i386_insn_is_jump (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
651 gdb_byte buf
[I386_MAX_INSN_LEN
], *insn
;
653 read_code (addr
, buf
, I386_MAX_INSN_LEN
);
654 insn
= i386_skip_prefixes (buf
, I386_MAX_INSN_LEN
);
656 return i386_jmp_p (insn
);
659 /* Some kernels may run one past a syscall insn, so we have to cope.
660 Otherwise this is just simple_displaced_step_copy_insn. */
662 struct displaced_step_closure
*
663 i386_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
664 CORE_ADDR from
, CORE_ADDR to
,
665 struct regcache
*regs
)
667 size_t len
= gdbarch_max_insn_length (gdbarch
);
668 gdb_byte
*buf
= xmalloc (len
);
670 read_memory (from
, buf
, len
);
672 /* GDB may get control back after the insn after the syscall.
673 Presumably this is a kernel bug.
674 If this is a syscall, make sure there's a nop afterwards. */
679 insn
= i386_skip_prefixes (buf
, len
);
680 if (insn
!= NULL
&& i386_syscall_p (insn
, &syscall_length
))
681 insn
[syscall_length
] = NOP_OPCODE
;
684 write_memory (to
, buf
, len
);
688 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
689 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
690 displaced_step_dump_bytes (gdb_stdlog
, buf
, len
);
693 return (struct displaced_step_closure
*) buf
;
696 /* Fix up the state of registers and memory after having single-stepped
697 a displaced instruction. */
700 i386_displaced_step_fixup (struct gdbarch
*gdbarch
,
701 struct displaced_step_closure
*closure
,
702 CORE_ADDR from
, CORE_ADDR to
,
703 struct regcache
*regs
)
705 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
707 /* The offset we applied to the instruction's address.
708 This could well be negative (when viewed as a signed 32-bit
709 value), but ULONGEST won't reflect that, so take care when
711 ULONGEST insn_offset
= to
- from
;
713 /* Since we use simple_displaced_step_copy_insn, our closure is a
714 copy of the instruction. */
715 gdb_byte
*insn
= (gdb_byte
*) closure
;
716 /* The start of the insn, needed in case we see some prefixes. */
717 gdb_byte
*insn_start
= insn
;
720 fprintf_unfiltered (gdb_stdlog
,
721 "displaced: fixup (%s, %s), "
722 "insn = 0x%02x 0x%02x ...\n",
723 paddress (gdbarch
, from
), paddress (gdbarch
, to
),
726 /* The list of issues to contend with here is taken from
727 resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20.
728 Yay for Free Software! */
730 /* Relocate the %eip, if necessary. */
732 /* The instruction recognizers we use assume any leading prefixes
733 have been skipped. */
735 /* This is the size of the buffer in closure. */
736 size_t max_insn_len
= gdbarch_max_insn_length (gdbarch
);
737 gdb_byte
*opcode
= i386_skip_prefixes (insn
, max_insn_len
);
738 /* If there are too many prefixes, just ignore the insn.
739 It will fault when run. */
744 /* Except in the case of absolute or indirect jump or call
745 instructions, or a return instruction, the new eip is relative to
746 the displaced instruction; make it relative. Well, signal
747 handler returns don't need relocation either, but we use the
748 value of %eip to recognize those; see below. */
749 if (! i386_absolute_jmp_p (insn
)
750 && ! i386_absolute_call_p (insn
)
751 && ! i386_ret_p (insn
))
756 regcache_cooked_read_unsigned (regs
, I386_EIP_REGNUM
, &orig_eip
);
758 /* A signal trampoline system call changes the %eip, resuming
759 execution of the main program after the signal handler has
760 returned. That makes them like 'return' instructions; we
761 shouldn't relocate %eip.
763 But most system calls don't, and we do need to relocate %eip.
765 Our heuristic for distinguishing these cases: if stepping
766 over the system call instruction left control directly after
767 the instruction, the we relocate --- control almost certainly
768 doesn't belong in the displaced copy. Otherwise, we assume
769 the instruction has put control where it belongs, and leave
770 it unrelocated. Goodness help us if there are PC-relative
772 if (i386_syscall_p (insn
, &insn_len
)
773 && orig_eip
!= to
+ (insn
- insn_start
) + insn_len
774 /* GDB can get control back after the insn after the syscall.
775 Presumably this is a kernel bug.
776 i386_displaced_step_copy_insn ensures its a nop,
777 we add one to the length for it. */
778 && orig_eip
!= to
+ (insn
- insn_start
) + insn_len
+ 1)
781 fprintf_unfiltered (gdb_stdlog
,
782 "displaced: syscall changed %%eip; "
787 ULONGEST eip
= (orig_eip
- insn_offset
) & 0xffffffffUL
;
789 /* If we just stepped over a breakpoint insn, we don't backup
790 the pc on purpose; this is to match behaviour without
793 regcache_cooked_write_unsigned (regs
, I386_EIP_REGNUM
, eip
);
796 fprintf_unfiltered (gdb_stdlog
,
798 "relocated %%eip from %s to %s\n",
799 paddress (gdbarch
, orig_eip
),
800 paddress (gdbarch
, eip
));
804 /* If the instruction was PUSHFL, then the TF bit will be set in the
805 pushed value, and should be cleared. We'll leave this for later,
806 since GDB already messes up the TF flag when stepping over a
809 /* If the instruction was a call, the return address now atop the
810 stack is the address following the copied instruction. We need
811 to make it the address following the original instruction. */
812 if (i386_call_p (insn
))
816 const ULONGEST retaddr_len
= 4;
818 regcache_cooked_read_unsigned (regs
, I386_ESP_REGNUM
, &esp
);
819 retaddr
= read_memory_unsigned_integer (esp
, retaddr_len
, byte_order
);
820 retaddr
= (retaddr
- insn_offset
) & 0xffffffffUL
;
821 write_memory_unsigned_integer (esp
, retaddr_len
, byte_order
, retaddr
);
824 fprintf_unfiltered (gdb_stdlog
,
825 "displaced: relocated return addr at %s to %s\n",
826 paddress (gdbarch
, esp
),
827 paddress (gdbarch
, retaddr
));
832 append_insns (CORE_ADDR
*to
, ULONGEST len
, const gdb_byte
*buf
)
834 target_write_memory (*to
, buf
, len
);
839 i386_relocate_instruction (struct gdbarch
*gdbarch
,
840 CORE_ADDR
*to
, CORE_ADDR oldloc
)
842 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
843 gdb_byte buf
[I386_MAX_INSN_LEN
];
844 int offset
= 0, rel32
, newrel
;
846 gdb_byte
*insn
= buf
;
848 read_memory (oldloc
, buf
, I386_MAX_INSN_LEN
);
850 insn_length
= gdb_buffered_insn_length (gdbarch
, insn
,
851 I386_MAX_INSN_LEN
, oldloc
);
853 /* Get past the prefixes. */
854 insn
= i386_skip_prefixes (insn
, I386_MAX_INSN_LEN
);
856 /* Adjust calls with 32-bit relative addresses as push/jump, with
857 the address pushed being the location where the original call in
858 the user program would return to. */
861 gdb_byte push_buf
[16];
862 unsigned int ret_addr
;
864 /* Where "ret" in the original code will return to. */
865 ret_addr
= oldloc
+ insn_length
;
866 push_buf
[0] = 0x68; /* pushq $... */
867 store_unsigned_integer (&push_buf
[1], 4, byte_order
, ret_addr
);
869 append_insns (to
, 5, push_buf
);
871 /* Convert the relative call to a relative jump. */
874 /* Adjust the destination offset. */
875 rel32
= extract_signed_integer (insn
+ 1, 4, byte_order
);
876 newrel
= (oldloc
- *to
) + rel32
;
877 store_signed_integer (insn
+ 1, 4, byte_order
, newrel
);
880 fprintf_unfiltered (gdb_stdlog
,
881 "Adjusted insn rel32=%s at %s to"
883 hex_string (rel32
), paddress (gdbarch
, oldloc
),
884 hex_string (newrel
), paddress (gdbarch
, *to
));
886 /* Write the adjusted jump into its displaced location. */
887 append_insns (to
, 5, insn
);
891 /* Adjust jumps with 32-bit relative addresses. Calls are already
895 /* Adjust conditional jumps. */
896 else if (insn
[0] == 0x0f && (insn
[1] & 0xf0) == 0x80)
901 rel32
= extract_signed_integer (insn
+ offset
, 4, byte_order
);
902 newrel
= (oldloc
- *to
) + rel32
;
903 store_signed_integer (insn
+ offset
, 4, byte_order
, newrel
);
905 fprintf_unfiltered (gdb_stdlog
,
906 "Adjusted insn rel32=%s at %s to"
908 hex_string (rel32
), paddress (gdbarch
, oldloc
),
909 hex_string (newrel
), paddress (gdbarch
, *to
));
912 /* Write the adjusted instructions into their displaced
914 append_insns (to
, insn_length
, buf
);
918 #ifdef I386_REGNO_TO_SYMMETRY
919 #error "The Sequent Symmetry is no longer supported."
922 /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi
923 and %esp "belong" to the calling function. Therefore these
924 registers should be saved if they're going to be modified. */
926 /* The maximum number of saved registers. This should include all
927 registers mentioned above, and %eip. */
928 #define I386_NUM_SAVED_REGS I386_NUM_GREGS
930 struct i386_frame_cache
938 /* Saved registers. */
939 CORE_ADDR saved_regs
[I386_NUM_SAVED_REGS
];
944 /* Stack space reserved for local variables. */
948 /* Allocate and initialize a frame cache. */
950 static struct i386_frame_cache
*
951 i386_alloc_frame_cache (void)
953 struct i386_frame_cache
*cache
;
956 cache
= FRAME_OBSTACK_ZALLOC (struct i386_frame_cache
);
961 cache
->sp_offset
= -4;
964 /* Saved registers. We initialize these to -1 since zero is a valid
965 offset (that's where %ebp is supposed to be stored). */
966 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
967 cache
->saved_regs
[i
] = -1;
969 cache
->saved_sp_reg
= -1;
970 cache
->pc_in_eax
= 0;
972 /* Frameless until proven otherwise. */
978 /* If the instruction at PC is a jump, return the address of its
979 target. Otherwise, return PC. */
982 i386_follow_jump (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
984 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
989 if (target_read_code (pc
, &op
, 1))
996 op
= read_code_unsigned_integer (pc
+ 1, 1, byte_order
);
1002 /* Relative jump: if data16 == 0, disp32, else disp16. */
1005 delta
= read_memory_integer (pc
+ 2, 2, byte_order
);
1007 /* Include the size of the jmp instruction (including the
1013 delta
= read_memory_integer (pc
+ 1, 4, byte_order
);
1015 /* Include the size of the jmp instruction. */
1020 /* Relative jump, disp8 (ignore data16). */
1021 delta
= read_memory_integer (pc
+ data16
+ 1, 1, byte_order
);
1023 delta
+= data16
+ 2;
1030 /* Check whether PC points at a prologue for a function returning a
1031 structure or union. If so, it updates CACHE and returns the
1032 address of the first instruction after the code sequence that
1033 removes the "hidden" argument from the stack or CURRENT_PC,
1034 whichever is smaller. Otherwise, return PC. */
1037 i386_analyze_struct_return (CORE_ADDR pc
, CORE_ADDR current_pc
,
1038 struct i386_frame_cache
*cache
)
1040 /* Functions that return a structure or union start with:
1043 xchgl %eax, (%esp) 0x87 0x04 0x24
1044 or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00
1046 (the System V compiler puts out the second `xchg' instruction,
1047 and the assembler doesn't try to optimize it, so the 'sib' form
1048 gets generated). This sequence is used to get the address of the
1049 return buffer for a function that returns a structure. */
1050 static gdb_byte proto1
[3] = { 0x87, 0x04, 0x24 };
1051 static gdb_byte proto2
[4] = { 0x87, 0x44, 0x24, 0x00 };
1055 if (current_pc
<= pc
)
1058 if (target_read_code (pc
, &op
, 1))
1061 if (op
!= 0x58) /* popl %eax */
1064 if (target_read_code (pc
+ 1, buf
, 4))
1067 if (memcmp (buf
, proto1
, 3) != 0 && memcmp (buf
, proto2
, 4) != 0)
1070 if (current_pc
== pc
)
1072 cache
->sp_offset
+= 4;
1076 if (current_pc
== pc
+ 1)
1078 cache
->pc_in_eax
= 1;
1082 if (buf
[1] == proto1
[1])
1089 i386_skip_probe (CORE_ADDR pc
)
1091 /* A function may start with
1105 if (target_read_code (pc
, &op
, 1))
1108 if (op
== 0x68 || op
== 0x6a)
1112 /* Skip past the `pushl' instruction; it has either a one-byte or a
1113 four-byte operand, depending on the opcode. */
1119 /* Read the following 8 bytes, which should be `call _probe' (6
1120 bytes) followed by `addl $4,%esp' (2 bytes). */
1121 read_memory (pc
+ delta
, buf
, sizeof (buf
));
1122 if (buf
[0] == 0xe8 && buf
[6] == 0xc4 && buf
[7] == 0x4)
1123 pc
+= delta
+ sizeof (buf
);
1129 /* GCC 4.1 and later, can put code in the prologue to realign the
1130 stack pointer. Check whether PC points to such code, and update
1131 CACHE accordingly. Return the first instruction after the code
1132 sequence or CURRENT_PC, whichever is smaller. If we don't
1133 recognize the code, return PC. */
1136 i386_analyze_stack_align (CORE_ADDR pc
, CORE_ADDR current_pc
,
1137 struct i386_frame_cache
*cache
)
1139 /* There are 2 code sequences to re-align stack before the frame
1142 1. Use a caller-saved saved register:
1148 2. Use a callee-saved saved register:
1155 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
1157 0x83 0xe4 0xf0 andl $-16, %esp
1158 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
1163 int offset
, offset_and
;
1164 static int regnums
[8] = {
1165 I386_EAX_REGNUM
, /* %eax */
1166 I386_ECX_REGNUM
, /* %ecx */
1167 I386_EDX_REGNUM
, /* %edx */
1168 I386_EBX_REGNUM
, /* %ebx */
1169 I386_ESP_REGNUM
, /* %esp */
1170 I386_EBP_REGNUM
, /* %ebp */
1171 I386_ESI_REGNUM
, /* %esi */
1172 I386_EDI_REGNUM
/* %edi */
1175 if (target_read_code (pc
, buf
, sizeof buf
))
1178 /* Check caller-saved saved register. The first instruction has
1179 to be "leal 4(%esp), %reg". */
1180 if (buf
[0] == 0x8d && buf
[2] == 0x24 && buf
[3] == 0x4)
1182 /* MOD must be binary 10 and R/M must be binary 100. */
1183 if ((buf
[1] & 0xc7) != 0x44)
1186 /* REG has register number. */
1187 reg
= (buf
[1] >> 3) & 7;
1192 /* Check callee-saved saved register. The first instruction
1193 has to be "pushl %reg". */
1194 if ((buf
[0] & 0xf8) != 0x50)
1200 /* The next instruction has to be "leal 8(%esp), %reg". */
1201 if (buf
[1] != 0x8d || buf
[3] != 0x24 || buf
[4] != 0x8)
1204 /* MOD must be binary 10 and R/M must be binary 100. */
1205 if ((buf
[2] & 0xc7) != 0x44)
1208 /* REG has register number. Registers in pushl and leal have to
1210 if (reg
!= ((buf
[2] >> 3) & 7))
1216 /* Rigister can't be %esp nor %ebp. */
1217 if (reg
== 4 || reg
== 5)
1220 /* The next instruction has to be "andl $-XXX, %esp". */
1221 if (buf
[offset
+ 1] != 0xe4
1222 || (buf
[offset
] != 0x81 && buf
[offset
] != 0x83))
1225 offset_and
= offset
;
1226 offset
+= buf
[offset
] == 0x81 ? 6 : 3;
1228 /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is
1229 0xfc. REG must be binary 110 and MOD must be binary 01. */
1230 if (buf
[offset
] != 0xff
1231 || buf
[offset
+ 2] != 0xfc
1232 || (buf
[offset
+ 1] & 0xf8) != 0x70)
1235 /* R/M has register. Registers in leal and pushl have to be the
1237 if (reg
!= (buf
[offset
+ 1] & 7))
1240 if (current_pc
> pc
+ offset_and
)
1241 cache
->saved_sp_reg
= regnums
[reg
];
1243 return min (pc
+ offset
+ 3, current_pc
);
1246 /* Maximum instruction length we need to handle. */
1247 #define I386_MAX_MATCHED_INSN_LEN 6
1249 /* Instruction description. */
1253 gdb_byte insn
[I386_MAX_MATCHED_INSN_LEN
];
1254 gdb_byte mask
[I386_MAX_MATCHED_INSN_LEN
];
1257 /* Return whether instruction at PC matches PATTERN. */
1260 i386_match_pattern (CORE_ADDR pc
, struct i386_insn pattern
)
1264 if (target_read_code (pc
, &op
, 1))
1267 if ((op
& pattern
.mask
[0]) == pattern
.insn
[0])
1269 gdb_byte buf
[I386_MAX_MATCHED_INSN_LEN
- 1];
1270 int insn_matched
= 1;
1273 gdb_assert (pattern
.len
> 1);
1274 gdb_assert (pattern
.len
<= I386_MAX_MATCHED_INSN_LEN
);
1276 if (target_read_code (pc
+ 1, buf
, pattern
.len
- 1))
1279 for (i
= 1; i
< pattern
.len
; i
++)
1281 if ((buf
[i
- 1] & pattern
.mask
[i
]) != pattern
.insn
[i
])
1284 return insn_matched
;
1289 /* Search for the instruction at PC in the list INSN_PATTERNS. Return
1290 the first instruction description that matches. Otherwise, return
1293 static struct i386_insn
*
1294 i386_match_insn (CORE_ADDR pc
, struct i386_insn
*insn_patterns
)
1296 struct i386_insn
*pattern
;
1298 for (pattern
= insn_patterns
; pattern
->len
> 0; pattern
++)
1300 if (i386_match_pattern (pc
, *pattern
))
1307 /* Return whether PC points inside a sequence of instructions that
1308 matches INSN_PATTERNS. */
1311 i386_match_insn_block (CORE_ADDR pc
, struct i386_insn
*insn_patterns
)
1313 CORE_ADDR current_pc
;
1315 struct i386_insn
*insn
;
1317 insn
= i386_match_insn (pc
, insn_patterns
);
1322 ix
= insn
- insn_patterns
;
1323 for (i
= ix
- 1; i
>= 0; i
--)
1325 current_pc
-= insn_patterns
[i
].len
;
1327 if (!i386_match_pattern (current_pc
, insn_patterns
[i
]))
1331 current_pc
= pc
+ insn
->len
;
1332 for (insn
= insn_patterns
+ ix
+ 1; insn
->len
> 0; insn
++)
1334 if (!i386_match_pattern (current_pc
, *insn
))
1337 current_pc
+= insn
->len
;
1343 /* Some special instructions that might be migrated by GCC into the
1344 part of the prologue that sets up the new stack frame. Because the
1345 stack frame hasn't been setup yet, no registers have been saved
1346 yet, and only the scratch registers %eax, %ecx and %edx can be
1349 struct i386_insn i386_frame_setup_skip_insns
[] =
1351 /* Check for `movb imm8, r' and `movl imm32, r'.
1353 ??? Should we handle 16-bit operand-sizes here? */
1355 /* `movb imm8, %al' and `movb imm8, %ah' */
1356 /* `movb imm8, %cl' and `movb imm8, %ch' */
1357 { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } },
1358 /* `movb imm8, %dl' and `movb imm8, %dh' */
1359 { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } },
1360 /* `movl imm32, %eax' and `movl imm32, %ecx' */
1361 { 5, { 0xb8 }, { 0xfe } },
1362 /* `movl imm32, %edx' */
1363 { 5, { 0xba }, { 0xff } },
1365 /* Check for `mov imm32, r32'. Note that there is an alternative
1366 encoding for `mov m32, %eax'.
1368 ??? Should we handle SIB adressing here?
1369 ??? Should we handle 16-bit operand-sizes here? */
1371 /* `movl m32, %eax' */
1372 { 5, { 0xa1 }, { 0xff } },
1373 /* `movl m32, %eax' and `mov; m32, %ecx' */
1374 { 6, { 0x89, 0x05 }, {0xff, 0xf7 } },
1375 /* `movl m32, %edx' */
1376 { 6, { 0x89, 0x15 }, {0xff, 0xff } },
1378 /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'.
1379 Because of the symmetry, there are actually two ways to encode
1380 these instructions; opcode bytes 0x29 and 0x2b for `subl' and
1381 opcode bytes 0x31 and 0x33 for `xorl'. */
1383 /* `subl %eax, %eax' */
1384 { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } },
1385 /* `subl %ecx, %ecx' */
1386 { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } },
1387 /* `subl %edx, %edx' */
1388 { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } },
1389 /* `xorl %eax, %eax' */
1390 { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } },
1391 /* `xorl %ecx, %ecx' */
1392 { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } },
1393 /* `xorl %edx, %edx' */
1394 { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } },
1399 /* Check whether PC points to a no-op instruction. */
1401 i386_skip_noop (CORE_ADDR pc
)
1406 if (target_read_code (pc
, &op
, 1))
1412 /* Ignore `nop' instruction. */
1416 if (target_read_code (pc
, &op
, 1))
1420 /* Ignore no-op instruction `mov %edi, %edi'.
1421 Microsoft system dlls often start with
1422 a `mov %edi,%edi' instruction.
1423 The 5 bytes before the function start are
1424 filled with `nop' instructions.
1425 This pattern can be used for hot-patching:
1426 The `mov %edi, %edi' instruction can be replaced by a
1427 near jump to the location of the 5 `nop' instructions
1428 which can be replaced by a 32-bit jump to anywhere
1429 in the 32-bit address space. */
1431 else if (op
== 0x8b)
1433 if (target_read_code (pc
+ 1, &op
, 1))
1439 if (target_read_code (pc
, &op
, 1))
1449 /* Check whether PC points at a code that sets up a new stack frame.
1450 If so, it updates CACHE and returns the address of the first
1451 instruction after the sequence that sets up the frame or LIMIT,
1452 whichever is smaller. If we don't recognize the code, return PC. */
1455 i386_analyze_frame_setup (struct gdbarch
*gdbarch
,
1456 CORE_ADDR pc
, CORE_ADDR limit
,
1457 struct i386_frame_cache
*cache
)
1459 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1460 struct i386_insn
*insn
;
1467 if (target_read_code (pc
, &op
, 1))
1470 if (op
== 0x55) /* pushl %ebp */
1472 /* Take into account that we've executed the `pushl %ebp' that
1473 starts this instruction sequence. */
1474 cache
->saved_regs
[I386_EBP_REGNUM
] = 0;
1475 cache
->sp_offset
+= 4;
1478 /* If that's all, return now. */
1482 /* Check for some special instructions that might be migrated by
1483 GCC into the prologue and skip them. At this point in the
1484 prologue, code should only touch the scratch registers %eax,
1485 %ecx and %edx, so while the number of posibilities is sheer,
1488 Make sure we only skip these instructions if we later see the
1489 `movl %esp, %ebp' that actually sets up the frame. */
1490 while (pc
+ skip
< limit
)
1492 insn
= i386_match_insn (pc
+ skip
, i386_frame_setup_skip_insns
);
1499 /* If that's all, return now. */
1500 if (limit
<= pc
+ skip
)
1503 if (target_read_code (pc
+ skip
, &op
, 1))
1506 /* The i386 prologue looks like
1512 and a different prologue can be generated for atom.
1516 lea -0x10(%esp),%esp
1518 We handle both of them here. */
1522 /* Check for `movl %esp, %ebp' -- can be written in two ways. */
1524 if (read_code_unsigned_integer (pc
+ skip
+ 1, 1, byte_order
)
1530 if (read_code_unsigned_integer (pc
+ skip
+ 1, 1, byte_order
)
1535 case 0x8d: /* Check for 'lea (%ebp), %ebp'. */
1536 if (read_code_unsigned_integer (pc
+ skip
+ 1, 2, byte_order
)
1545 /* OK, we actually have a frame. We just don't know how large
1546 it is yet. Set its size to zero. We'll adjust it if
1547 necessary. We also now commit to skipping the special
1548 instructions mentioned before. */
1551 /* If that's all, return now. */
1555 /* Check for stack adjustment
1561 NOTE: You can't subtract a 16-bit immediate from a 32-bit
1562 reg, so we don't have to worry about a data16 prefix. */
1563 if (target_read_code (pc
, &op
, 1))
1567 /* `subl' with 8-bit immediate. */
1568 if (read_code_unsigned_integer (pc
+ 1, 1, byte_order
) != 0xec)
1569 /* Some instruction starting with 0x83 other than `subl'. */
1572 /* `subl' with signed 8-bit immediate (though it wouldn't
1573 make sense to be negative). */
1574 cache
->locals
= read_code_integer (pc
+ 2, 1, byte_order
);
1577 else if (op
== 0x81)
1579 /* Maybe it is `subl' with a 32-bit immediate. */
1580 if (read_code_unsigned_integer (pc
+ 1, 1, byte_order
) != 0xec)
1581 /* Some instruction starting with 0x81 other than `subl'. */
1584 /* It is `subl' with a 32-bit immediate. */
1585 cache
->locals
= read_code_integer (pc
+ 2, 4, byte_order
);
1588 else if (op
== 0x8d)
1590 /* The ModR/M byte is 0x64. */
1591 if (read_code_unsigned_integer (pc
+ 1, 1, byte_order
) != 0x64)
1593 /* 'lea' with 8-bit displacement. */
1594 cache
->locals
= -1 * read_code_integer (pc
+ 3, 1, byte_order
);
1599 /* Some instruction other than `subl' nor 'lea'. */
1603 else if (op
== 0xc8) /* enter */
1605 cache
->locals
= read_code_unsigned_integer (pc
+ 1, 2, byte_order
);
1612 /* Check whether PC points at code that saves registers on the stack.
1613 If so, it updates CACHE and returns the address of the first
1614 instruction after the register saves or CURRENT_PC, whichever is
1615 smaller. Otherwise, return PC. */
1618 i386_analyze_register_saves (CORE_ADDR pc
, CORE_ADDR current_pc
,
1619 struct i386_frame_cache
*cache
)
1621 CORE_ADDR offset
= 0;
1625 if (cache
->locals
> 0)
1626 offset
-= cache
->locals
;
1627 for (i
= 0; i
< 8 && pc
< current_pc
; i
++)
1629 if (target_read_code (pc
, &op
, 1))
1631 if (op
< 0x50 || op
> 0x57)
1635 cache
->saved_regs
[op
- 0x50] = offset
;
1636 cache
->sp_offset
+= 4;
1643 /* Do a full analysis of the prologue at PC and update CACHE
1644 accordingly. Bail out early if CURRENT_PC is reached. Return the
1645 address where the analysis stopped.
1647 We handle these cases:
1649 The startup sequence can be at the start of the function, or the
1650 function can start with a branch to startup code at the end.
1652 %ebp can be set up with either the 'enter' instruction, or "pushl
1653 %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was
1654 once used in the System V compiler).
1656 Local space is allocated just below the saved %ebp by either the
1657 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a
1658 16-bit unsigned argument for space to allocate, and the 'addl'
1659 instruction could have either a signed byte, or 32-bit immediate.
1661 Next, the registers used by this function are pushed. With the
1662 System V compiler they will always be in the order: %edi, %esi,
1663 %ebx (and sometimes a harmless bug causes it to also save but not
1664 restore %eax); however, the code below is willing to see the pushes
1665 in any order, and will handle up to 8 of them.
1667 If the setup sequence is at the end of the function, then the next
1668 instruction will be a branch back to the start. */
1671 i386_analyze_prologue (struct gdbarch
*gdbarch
,
1672 CORE_ADDR pc
, CORE_ADDR current_pc
,
1673 struct i386_frame_cache
*cache
)
1675 pc
= i386_skip_noop (pc
);
1676 pc
= i386_follow_jump (gdbarch
, pc
);
1677 pc
= i386_analyze_struct_return (pc
, current_pc
, cache
);
1678 pc
= i386_skip_probe (pc
);
1679 pc
= i386_analyze_stack_align (pc
, current_pc
, cache
);
1680 pc
= i386_analyze_frame_setup (gdbarch
, pc
, current_pc
, cache
);
1681 return i386_analyze_register_saves (pc
, current_pc
, cache
);
1684 /* Return PC of first real instruction. */
1687 i386_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
1689 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1691 static gdb_byte pic_pat
[6] =
1693 0xe8, 0, 0, 0, 0, /* call 0x0 */
1694 0x5b, /* popl %ebx */
1696 struct i386_frame_cache cache
;
1700 CORE_ADDR func_addr
;
1702 if (find_pc_partial_function (start_pc
, NULL
, &func_addr
, NULL
))
1704 CORE_ADDR post_prologue_pc
1705 = skip_prologue_using_sal (gdbarch
, func_addr
);
1706 struct symtab
*s
= find_pc_symtab (func_addr
);
1708 /* Clang always emits a line note before the prologue and another
1709 one after. We trust clang to emit usable line notes. */
1710 if (post_prologue_pc
1712 && s
->producer
!= NULL
1713 && strncmp (s
->producer
, "clang ", sizeof ("clang ") - 1) == 0))
1714 return max (start_pc
, post_prologue_pc
);
1718 pc
= i386_analyze_prologue (gdbarch
, start_pc
, 0xffffffff, &cache
);
1719 if (cache
.locals
< 0)
1722 /* Found valid frame setup. */
1724 /* The native cc on SVR4 in -K PIC mode inserts the following code
1725 to get the address of the global offset table (GOT) into register
1730 movl %ebx,x(%ebp) (optional)
1733 This code is with the rest of the prologue (at the end of the
1734 function), so we have to skip it to get to the first real
1735 instruction at the start of the function. */
1737 for (i
= 0; i
< 6; i
++)
1739 if (target_read_code (pc
+ i
, &op
, 1))
1742 if (pic_pat
[i
] != op
)
1749 if (target_read_code (pc
+ delta
, &op
, 1))
1752 if (op
== 0x89) /* movl %ebx, x(%ebp) */
1754 op
= read_code_unsigned_integer (pc
+ delta
+ 1, 1, byte_order
);
1756 if (op
== 0x5d) /* One byte offset from %ebp. */
1758 else if (op
== 0x9d) /* Four byte offset from %ebp. */
1760 else /* Unexpected instruction. */
1763 if (target_read_code (pc
+ delta
, &op
, 1))
1768 if (delta
> 0 && op
== 0x81
1769 && read_code_unsigned_integer (pc
+ delta
+ 1, 1, byte_order
)
1776 /* If the function starts with a branch (to startup code at the end)
1777 the last instruction should bring us back to the first
1778 instruction of the real code. */
1779 if (i386_follow_jump (gdbarch
, start_pc
) != start_pc
)
1780 pc
= i386_follow_jump (gdbarch
, pc
);
1785 /* Check that the code pointed to by PC corresponds to a call to
1786 __main, skip it if so. Return PC otherwise. */
1789 i386_skip_main_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1791 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1794 if (target_read_code (pc
, &op
, 1))
1800 if (target_read_code (pc
+ 1, buf
, sizeof buf
) == 0)
1802 /* Make sure address is computed correctly as a 32bit
1803 integer even if CORE_ADDR is 64 bit wide. */
1804 struct bound_minimal_symbol s
;
1805 CORE_ADDR call_dest
;
1807 call_dest
= pc
+ 5 + extract_signed_integer (buf
, 4, byte_order
);
1808 call_dest
= call_dest
& 0xffffffffU
;
1809 s
= lookup_minimal_symbol_by_pc (call_dest
);
1810 if (s
.minsym
!= NULL
1811 && SYMBOL_LINKAGE_NAME (s
.minsym
) != NULL
1812 && strcmp (SYMBOL_LINKAGE_NAME (s
.minsym
), "__main") == 0)
1820 /* This function is 64-bit safe. */
1823 i386_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1827 frame_unwind_register (next_frame
, gdbarch_pc_regnum (gdbarch
), buf
);
1828 return extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
1832 /* Normal frames. */
1835 i386_frame_cache_1 (struct frame_info
*this_frame
,
1836 struct i386_frame_cache
*cache
)
1838 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1839 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1843 cache
->pc
= get_frame_func (this_frame
);
1845 /* In principle, for normal frames, %ebp holds the frame pointer,
1846 which holds the base address for the current stack frame.
1847 However, for functions that don't need it, the frame pointer is
1848 optional. For these "frameless" functions the frame pointer is
1849 actually the frame pointer of the calling frame. Signal
1850 trampolines are just a special case of a "frameless" function.
1851 They (usually) share their frame pointer with the frame that was
1852 in progress when the signal occurred. */
1854 get_frame_register (this_frame
, I386_EBP_REGNUM
, buf
);
1855 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
);
1856 if (cache
->base
== 0)
1862 /* For normal frames, %eip is stored at 4(%ebp). */
1863 cache
->saved_regs
[I386_EIP_REGNUM
] = 4;
1866 i386_analyze_prologue (gdbarch
, cache
->pc
, get_frame_pc (this_frame
),
1869 if (cache
->locals
< 0)
1871 /* We didn't find a valid frame, which means that CACHE->base
1872 currently holds the frame pointer for our calling frame. If
1873 we're at the start of a function, or somewhere half-way its
1874 prologue, the function's frame probably hasn't been fully
1875 setup yet. Try to reconstruct the base address for the stack
1876 frame by looking at the stack pointer. For truly "frameless"
1877 functions this might work too. */
1879 if (cache
->saved_sp_reg
!= -1)
1881 /* Saved stack pointer has been saved. */
1882 get_frame_register (this_frame
, cache
->saved_sp_reg
, buf
);
1883 cache
->saved_sp
= extract_unsigned_integer (buf
, 4, byte_order
);
1885 /* We're halfway aligning the stack. */
1886 cache
->base
= ((cache
->saved_sp
- 4) & 0xfffffff0) - 4;
1887 cache
->saved_regs
[I386_EIP_REGNUM
] = cache
->saved_sp
- 4;
1889 /* This will be added back below. */
1890 cache
->saved_regs
[I386_EIP_REGNUM
] -= cache
->base
;
1892 else if (cache
->pc
!= 0
1893 || target_read_code (get_frame_pc (this_frame
), buf
, 1))
1895 /* We're in a known function, but did not find a frame
1896 setup. Assume that the function does not use %ebp.
1897 Alternatively, we may have jumped to an invalid
1898 address; in that case there is definitely no new
1900 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
1901 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
)
1905 /* We're in an unknown function. We could not find the start
1906 of the function to analyze the prologue; our best option is
1907 to assume a typical frame layout with the caller's %ebp
1909 cache
->saved_regs
[I386_EBP_REGNUM
] = 0;
1912 if (cache
->saved_sp_reg
!= -1)
1914 /* Saved stack pointer has been saved (but the SAVED_SP_REG
1915 register may be unavailable). */
1916 if (cache
->saved_sp
== 0
1917 && deprecated_frame_register_read (this_frame
,
1918 cache
->saved_sp_reg
, buf
))
1919 cache
->saved_sp
= extract_unsigned_integer (buf
, 4, byte_order
);
1921 /* Now that we have the base address for the stack frame we can
1922 calculate the value of %esp in the calling frame. */
1923 else if (cache
->saved_sp
== 0)
1924 cache
->saved_sp
= cache
->base
+ 8;
1926 /* Adjust all the saved registers such that they contain addresses
1927 instead of offsets. */
1928 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
1929 if (cache
->saved_regs
[i
] != -1)
1930 cache
->saved_regs
[i
] += cache
->base
;
1935 static struct i386_frame_cache
*
1936 i386_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1938 volatile struct gdb_exception ex
;
1939 struct i386_frame_cache
*cache
;
1944 cache
= i386_alloc_frame_cache ();
1945 *this_cache
= cache
;
1947 TRY_CATCH (ex
, RETURN_MASK_ERROR
)
1949 i386_frame_cache_1 (this_frame
, cache
);
1951 if (ex
.reason
< 0 && ex
.error
!= NOT_AVAILABLE_ERROR
)
1952 throw_exception (ex
);
1958 i386_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
1959 struct frame_id
*this_id
)
1961 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1964 (*this_id
) = frame_id_build_unavailable_stack (cache
->pc
);
1965 else if (cache
->base
== 0)
1967 /* This marks the outermost frame. */
1971 /* See the end of i386_push_dummy_call. */
1972 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
1976 static enum unwind_stop_reason
1977 i386_frame_unwind_stop_reason (struct frame_info
*this_frame
,
1980 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1983 return UNWIND_UNAVAILABLE
;
1985 /* This marks the outermost frame. */
1986 if (cache
->base
== 0)
1987 return UNWIND_OUTERMOST
;
1989 return UNWIND_NO_REASON
;
1992 static struct value
*
1993 i386_frame_prev_register (struct frame_info
*this_frame
, void **this_cache
,
1996 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1998 gdb_assert (regnum
>= 0);
2000 /* The System V ABI says that:
2002 "The flags register contains the system flags, such as the
2003 direction flag and the carry flag. The direction flag must be
2004 set to the forward (that is, zero) direction before entry and
2005 upon exit from a function. Other user flags have no specified
2006 role in the standard calling sequence and are not preserved."
2008 To guarantee the "upon exit" part of that statement we fake a
2009 saved flags register that has its direction flag cleared.
2011 Note that GCC doesn't seem to rely on the fact that the direction
2012 flag is cleared after a function return; it always explicitly
2013 clears the flag before operations where it matters.
2015 FIXME: kettenis/20030316: I'm not quite sure whether this is the
2016 right thing to do. The way we fake the flags register here makes
2017 it impossible to change it. */
2019 if (regnum
== I386_EFLAGS_REGNUM
)
2023 val
= get_frame_register_unsigned (this_frame
, regnum
);
2025 return frame_unwind_got_constant (this_frame
, regnum
, val
);
2028 if (regnum
== I386_EIP_REGNUM
&& cache
->pc_in_eax
)
2029 return frame_unwind_got_register (this_frame
, regnum
, I386_EAX_REGNUM
);
2031 if (regnum
== I386_ESP_REGNUM
2032 && (cache
->saved_sp
!= 0 || cache
->saved_sp_reg
!= -1))
2034 /* If the SP has been saved, but we don't know where, then this
2035 means that SAVED_SP_REG register was found unavailable back
2036 when we built the cache. */
2037 if (cache
->saved_sp
== 0)
2038 return frame_unwind_got_register (this_frame
, regnum
,
2039 cache
->saved_sp_reg
);
2041 return frame_unwind_got_constant (this_frame
, regnum
,
2045 if (regnum
< I386_NUM_SAVED_REGS
&& cache
->saved_regs
[regnum
] != -1)
2046 return frame_unwind_got_memory (this_frame
, regnum
,
2047 cache
->saved_regs
[regnum
]);
2049 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
2052 static const struct frame_unwind i386_frame_unwind
=
2055 i386_frame_unwind_stop_reason
,
2057 i386_frame_prev_register
,
2059 default_frame_sniffer
2062 /* Normal frames, but in a function epilogue. */
2064 /* The epilogue is defined here as the 'ret' instruction, which will
2065 follow any instruction such as 'leave' or 'pop %ebp' that destroys
2066 the function's stack frame. */
2069 i386_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2072 struct symtab
*symtab
;
2074 symtab
= find_pc_symtab (pc
);
2075 if (symtab
&& symtab
->epilogue_unwind_valid
)
2078 if (target_read_memory (pc
, &insn
, 1))
2079 return 0; /* Can't read memory at pc. */
2081 if (insn
!= 0xc3) /* 'ret' instruction. */
2088 i386_epilogue_frame_sniffer (const struct frame_unwind
*self
,
2089 struct frame_info
*this_frame
,
2090 void **this_prologue_cache
)
2092 if (frame_relative_level (this_frame
) == 0)
2093 return i386_in_function_epilogue_p (get_frame_arch (this_frame
),
2094 get_frame_pc (this_frame
));
2099 static struct i386_frame_cache
*
2100 i386_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2102 volatile struct gdb_exception ex
;
2103 struct i386_frame_cache
*cache
;
2109 cache
= i386_alloc_frame_cache ();
2110 *this_cache
= cache
;
2112 TRY_CATCH (ex
, RETURN_MASK_ERROR
)
2114 cache
->pc
= get_frame_func (this_frame
);
2116 /* At this point the stack looks as if we just entered the
2117 function, with the return address at the top of the
2119 sp
= get_frame_register_unsigned (this_frame
, I386_ESP_REGNUM
);
2120 cache
->base
= sp
+ cache
->sp_offset
;
2121 cache
->saved_sp
= cache
->base
+ 8;
2122 cache
->saved_regs
[I386_EIP_REGNUM
] = cache
->base
+ 4;
2126 if (ex
.reason
< 0 && ex
.error
!= NOT_AVAILABLE_ERROR
)
2127 throw_exception (ex
);
2132 static enum unwind_stop_reason
2133 i386_epilogue_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2136 struct i386_frame_cache
*cache
=
2137 i386_epilogue_frame_cache (this_frame
, this_cache
);
2140 return UNWIND_UNAVAILABLE
;
2142 return UNWIND_NO_REASON
;
2146 i386_epilogue_frame_this_id (struct frame_info
*this_frame
,
2148 struct frame_id
*this_id
)
2150 struct i386_frame_cache
*cache
=
2151 i386_epilogue_frame_cache (this_frame
, this_cache
);
2154 (*this_id
) = frame_id_build_unavailable_stack (cache
->pc
);
2156 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
2159 static struct value
*
2160 i386_epilogue_frame_prev_register (struct frame_info
*this_frame
,
2161 void **this_cache
, int regnum
)
2163 /* Make sure we've initialized the cache. */
2164 i386_epilogue_frame_cache (this_frame
, this_cache
);
2166 return i386_frame_prev_register (this_frame
, this_cache
, regnum
);
2169 static const struct frame_unwind i386_epilogue_frame_unwind
=
2172 i386_epilogue_frame_unwind_stop_reason
,
2173 i386_epilogue_frame_this_id
,
2174 i386_epilogue_frame_prev_register
,
2176 i386_epilogue_frame_sniffer
2180 /* Stack-based trampolines. */
2182 /* These trampolines are used on cross x86 targets, when taking the
2183 address of a nested function. When executing these trampolines,
2184 no stack frame is set up, so we are in a similar situation as in
2185 epilogues and i386_epilogue_frame_this_id can be re-used. */
2187 /* Static chain passed in register. */
2189 struct i386_insn i386_tramp_chain_in_reg_insns
[] =
2191 /* `movl imm32, %eax' and `movl imm32, %ecx' */
2192 { 5, { 0xb8 }, { 0xfe } },
2195 { 5, { 0xe9 }, { 0xff } },
2200 /* Static chain passed on stack (when regparm=3). */
2202 struct i386_insn i386_tramp_chain_on_stack_insns
[] =
2205 { 5, { 0x68 }, { 0xff } },
2208 { 5, { 0xe9 }, { 0xff } },
2213 /* Return whether PC points inside a stack trampoline. */
2216 i386_in_stack_tramp_p (CORE_ADDR pc
)
2221 /* A stack trampoline is detected if no name is associated
2222 to the current pc and if it points inside a trampoline
2225 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
2229 if (target_read_memory (pc
, &insn
, 1))
2232 if (!i386_match_insn_block (pc
, i386_tramp_chain_in_reg_insns
)
2233 && !i386_match_insn_block (pc
, i386_tramp_chain_on_stack_insns
))
2240 i386_stack_tramp_frame_sniffer (const struct frame_unwind
*self
,
2241 struct frame_info
*this_frame
,
2244 if (frame_relative_level (this_frame
) == 0)
2245 return i386_in_stack_tramp_p (get_frame_pc (this_frame
));
2250 static const struct frame_unwind i386_stack_tramp_frame_unwind
=
2253 i386_epilogue_frame_unwind_stop_reason
,
2254 i386_epilogue_frame_this_id
,
2255 i386_epilogue_frame_prev_register
,
2257 i386_stack_tramp_frame_sniffer
2260 /* Generate a bytecode expression to get the value of the saved PC. */
2263 i386_gen_return_address (struct gdbarch
*gdbarch
,
2264 struct agent_expr
*ax
, struct axs_value
*value
,
2267 /* The following sequence assumes the traditional use of the base
2269 ax_reg (ax
, I386_EBP_REGNUM
);
2271 ax_simple (ax
, aop_add
);
2272 value
->type
= register_type (gdbarch
, I386_EIP_REGNUM
);
2273 value
->kind
= axs_lvalue_memory
;
2277 /* Signal trampolines. */
2279 static struct i386_frame_cache
*
2280 i386_sigtramp_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2282 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2283 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2284 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2285 volatile struct gdb_exception ex
;
2286 struct i386_frame_cache
*cache
;
2293 cache
= i386_alloc_frame_cache ();
2295 TRY_CATCH (ex
, RETURN_MASK_ERROR
)
2297 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
2298 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
) - 4;
2300 addr
= tdep
->sigcontext_addr (this_frame
);
2301 if (tdep
->sc_reg_offset
)
2305 gdb_assert (tdep
->sc_num_regs
<= I386_NUM_SAVED_REGS
);
2307 for (i
= 0; i
< tdep
->sc_num_regs
; i
++)
2308 if (tdep
->sc_reg_offset
[i
] != -1)
2309 cache
->saved_regs
[i
] = addr
+ tdep
->sc_reg_offset
[i
];
2313 cache
->saved_regs
[I386_EIP_REGNUM
] = addr
+ tdep
->sc_pc_offset
;
2314 cache
->saved_regs
[I386_ESP_REGNUM
] = addr
+ tdep
->sc_sp_offset
;
2319 if (ex
.reason
< 0 && ex
.error
!= NOT_AVAILABLE_ERROR
)
2320 throw_exception (ex
);
2322 *this_cache
= cache
;
2326 static enum unwind_stop_reason
2327 i386_sigtramp_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2330 struct i386_frame_cache
*cache
=
2331 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2334 return UNWIND_UNAVAILABLE
;
2336 return UNWIND_NO_REASON
;
2340 i386_sigtramp_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2341 struct frame_id
*this_id
)
2343 struct i386_frame_cache
*cache
=
2344 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2347 (*this_id
) = frame_id_build_unavailable_stack (get_frame_pc (this_frame
));
2350 /* See the end of i386_push_dummy_call. */
2351 (*this_id
) = frame_id_build (cache
->base
+ 8, get_frame_pc (this_frame
));
2355 static struct value
*
2356 i386_sigtramp_frame_prev_register (struct frame_info
*this_frame
,
2357 void **this_cache
, int regnum
)
2359 /* Make sure we've initialized the cache. */
2360 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2362 return i386_frame_prev_register (this_frame
, this_cache
, regnum
);
2366 i386_sigtramp_frame_sniffer (const struct frame_unwind
*self
,
2367 struct frame_info
*this_frame
,
2368 void **this_prologue_cache
)
2370 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (this_frame
));
2372 /* We shouldn't even bother if we don't have a sigcontext_addr
2374 if (tdep
->sigcontext_addr
== NULL
)
2377 if (tdep
->sigtramp_p
!= NULL
)
2379 if (tdep
->sigtramp_p (this_frame
))
2383 if (tdep
->sigtramp_start
!= 0)
2385 CORE_ADDR pc
= get_frame_pc (this_frame
);
2387 gdb_assert (tdep
->sigtramp_end
!= 0);
2388 if (pc
>= tdep
->sigtramp_start
&& pc
< tdep
->sigtramp_end
)
2395 static const struct frame_unwind i386_sigtramp_frame_unwind
=
2398 i386_sigtramp_frame_unwind_stop_reason
,
2399 i386_sigtramp_frame_this_id
,
2400 i386_sigtramp_frame_prev_register
,
2402 i386_sigtramp_frame_sniffer
2407 i386_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
2409 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
2414 static const struct frame_base i386_frame_base
=
2417 i386_frame_base_address
,
2418 i386_frame_base_address
,
2419 i386_frame_base_address
2422 static struct frame_id
2423 i386_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
2427 fp
= get_frame_register_unsigned (this_frame
, I386_EBP_REGNUM
);
2429 /* See the end of i386_push_dummy_call. */
2430 return frame_id_build (fp
+ 8, get_frame_pc (this_frame
));
2433 /* _Decimal128 function return values need 16-byte alignment on the
2437 i386_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
2439 return sp
& -(CORE_ADDR
)16;
2443 /* Figure out where the longjmp will land. Slurp the args out of the
2444 stack. We expect the first arg to be a pointer to the jmp_buf
2445 structure from which we extract the address that we will land at.
2446 This address is copied into PC. This routine returns non-zero on
2450 i386_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
2453 CORE_ADDR sp
, jb_addr
;
2454 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2455 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2456 int jb_pc_offset
= gdbarch_tdep (gdbarch
)->jb_pc_offset
;
2458 /* If JB_PC_OFFSET is -1, we have no way to find out where the
2459 longjmp will land. */
2460 if (jb_pc_offset
== -1)
2463 get_frame_register (frame
, I386_ESP_REGNUM
, buf
);
2464 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
2465 if (target_read_memory (sp
+ 4, buf
, 4))
2468 jb_addr
= extract_unsigned_integer (buf
, 4, byte_order
);
2469 if (target_read_memory (jb_addr
+ jb_pc_offset
, buf
, 4))
2472 *pc
= extract_unsigned_integer (buf
, 4, byte_order
);
2477 /* Check whether TYPE must be 16-byte-aligned when passed as a
2478 function argument. 16-byte vectors, _Decimal128 and structures or
2479 unions containing such types must be 16-byte-aligned; other
2480 arguments are 4-byte-aligned. */
2483 i386_16_byte_align_p (struct type
*type
)
2485 type
= check_typedef (type
);
2486 if ((TYPE_CODE (type
) == TYPE_CODE_DECFLOAT
2487 || (TYPE_CODE (type
) == TYPE_CODE_ARRAY
&& TYPE_VECTOR (type
)))
2488 && TYPE_LENGTH (type
) == 16)
2490 if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
2491 return i386_16_byte_align_p (TYPE_TARGET_TYPE (type
));
2492 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
2493 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
2496 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
2498 if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type
, i
)))
2505 /* Implementation for set_gdbarch_push_dummy_code. */
2508 i386_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
, CORE_ADDR funaddr
,
2509 struct value
**args
, int nargs
, struct type
*value_type
,
2510 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
,
2511 struct regcache
*regcache
)
2513 /* Use 0xcc breakpoint - 1 byte. */
2517 /* Keep the stack aligned. */
2522 i386_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2523 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
2524 struct value
**args
, CORE_ADDR sp
, int struct_return
,
2525 CORE_ADDR struct_addr
)
2527 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2533 /* Determine the total space required for arguments and struct
2534 return address in a first pass (allowing for 16-byte-aligned
2535 arguments), then push arguments in a second pass. */
2537 for (write_pass
= 0; write_pass
< 2; write_pass
++)
2539 int args_space_used
= 0;
2545 /* Push value address. */
2546 store_unsigned_integer (buf
, 4, byte_order
, struct_addr
);
2547 write_memory (sp
, buf
, 4);
2548 args_space_used
+= 4;
2554 for (i
= 0; i
< nargs
; i
++)
2556 int len
= TYPE_LENGTH (value_enclosing_type (args
[i
]));
2560 if (i386_16_byte_align_p (value_enclosing_type (args
[i
])))
2561 args_space_used
= align_up (args_space_used
, 16);
2563 write_memory (sp
+ args_space_used
,
2564 value_contents_all (args
[i
]), len
);
2565 /* The System V ABI says that:
2567 "An argument's size is increased, if necessary, to make it a
2568 multiple of [32-bit] words. This may require tail padding,
2569 depending on the size of the argument."
2571 This makes sure the stack stays word-aligned. */
2572 args_space_used
+= align_up (len
, 4);
2576 if (i386_16_byte_align_p (value_enclosing_type (args
[i
])))
2577 args_space
= align_up (args_space
, 16);
2578 args_space
+= align_up (len
, 4);
2586 /* The original System V ABI only requires word alignment,
2587 but modern incarnations need 16-byte alignment in order
2588 to support SSE. Since wasting a few bytes here isn't
2589 harmful we unconditionally enforce 16-byte alignment. */
2594 /* Store return address. */
2596 store_unsigned_integer (buf
, 4, byte_order
, bp_addr
);
2597 write_memory (sp
, buf
, 4);
2599 /* Finally, update the stack pointer... */
2600 store_unsigned_integer (buf
, 4, byte_order
, sp
);
2601 regcache_cooked_write (regcache
, I386_ESP_REGNUM
, buf
);
2603 /* ...and fake a frame pointer. */
2604 regcache_cooked_write (regcache
, I386_EBP_REGNUM
, buf
);
2606 /* MarkK wrote: This "+ 8" is all over the place:
2607 (i386_frame_this_id, i386_sigtramp_frame_this_id,
2608 i386_dummy_id). It's there, since all frame unwinders for
2609 a given target have to agree (within a certain margin) on the
2610 definition of the stack address of a frame. Otherwise frame id
2611 comparison might not work correctly. Since DWARF2/GCC uses the
2612 stack address *before* the function call as a frame's CFA. On
2613 the i386, when %ebp is used as a frame pointer, the offset
2614 between the contents %ebp and the CFA as defined by GCC. */
2618 /* These registers are used for returning integers (and on some
2619 targets also for returning `struct' and `union' values when their
2620 size and alignment match an integer type). */
2621 #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */
2622 #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */
2624 /* Read, for architecture GDBARCH, a function return value of TYPE
2625 from REGCACHE, and copy that into VALBUF. */
2628 i386_extract_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
2629 struct regcache
*regcache
, gdb_byte
*valbuf
)
2631 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2632 int len
= TYPE_LENGTH (type
);
2633 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
2635 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2637 if (tdep
->st0_regnum
< 0)
2639 warning (_("Cannot find floating-point return value."));
2640 memset (valbuf
, 0, len
);
2644 /* Floating-point return values can be found in %st(0). Convert
2645 its contents to the desired type. This is probably not
2646 exactly how it would happen on the target itself, but it is
2647 the best we can do. */
2648 regcache_raw_read (regcache
, I386_ST0_REGNUM
, buf
);
2649 convert_typed_floating (buf
, i387_ext_type (gdbarch
), valbuf
, type
);
2653 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
2654 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
2656 if (len
<= low_size
)
2658 regcache_raw_read (regcache
, LOW_RETURN_REGNUM
, buf
);
2659 memcpy (valbuf
, buf
, len
);
2661 else if (len
<= (low_size
+ high_size
))
2663 regcache_raw_read (regcache
, LOW_RETURN_REGNUM
, buf
);
2664 memcpy (valbuf
, buf
, low_size
);
2665 regcache_raw_read (regcache
, HIGH_RETURN_REGNUM
, buf
);
2666 memcpy (valbuf
+ low_size
, buf
, len
- low_size
);
2669 internal_error (__FILE__
, __LINE__
,
2670 _("Cannot extract return value of %d bytes long."),
2675 /* Write, for architecture GDBARCH, a function return value of TYPE
2676 from VALBUF into REGCACHE. */
2679 i386_store_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
2680 struct regcache
*regcache
, const gdb_byte
*valbuf
)
2682 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2683 int len
= TYPE_LENGTH (type
);
2685 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2688 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
2690 if (tdep
->st0_regnum
< 0)
2692 warning (_("Cannot set floating-point return value."));
2696 /* Returning floating-point values is a bit tricky. Apart from
2697 storing the return value in %st(0), we have to simulate the
2698 state of the FPU at function return point. */
2700 /* Convert the value found in VALBUF to the extended
2701 floating-point format used by the FPU. This is probably
2702 not exactly how it would happen on the target itself, but
2703 it is the best we can do. */
2704 convert_typed_floating (valbuf
, type
, buf
, i387_ext_type (gdbarch
));
2705 regcache_raw_write (regcache
, I386_ST0_REGNUM
, buf
);
2707 /* Set the top of the floating-point register stack to 7. The
2708 actual value doesn't really matter, but 7 is what a normal
2709 function return would end up with if the program started out
2710 with a freshly initialized FPU. */
2711 regcache_raw_read_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), &fstat
);
2713 regcache_raw_write_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), fstat
);
2715 /* Mark %st(1) through %st(7) as empty. Since we set the top of
2716 the floating-point register stack to 7, the appropriate value
2717 for the tag word is 0x3fff. */
2718 regcache_raw_write_unsigned (regcache
, I387_FTAG_REGNUM (tdep
), 0x3fff);
2722 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
2723 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
2725 if (len
<= low_size
)
2726 regcache_raw_write_part (regcache
, LOW_RETURN_REGNUM
, 0, len
, valbuf
);
2727 else if (len
<= (low_size
+ high_size
))
2729 regcache_raw_write (regcache
, LOW_RETURN_REGNUM
, valbuf
);
2730 regcache_raw_write_part (regcache
, HIGH_RETURN_REGNUM
, 0,
2731 len
- low_size
, valbuf
+ low_size
);
2734 internal_error (__FILE__
, __LINE__
,
2735 _("Cannot store return value of %d bytes long."), len
);
2740 /* This is the variable that is set with "set struct-convention", and
2741 its legitimate values. */
2742 static const char default_struct_convention
[] = "default";
2743 static const char pcc_struct_convention
[] = "pcc";
2744 static const char reg_struct_convention
[] = "reg";
2745 static const char *const valid_conventions
[] =
2747 default_struct_convention
,
2748 pcc_struct_convention
,
2749 reg_struct_convention
,
2752 static const char *struct_convention
= default_struct_convention
;
2754 /* Return non-zero if TYPE, which is assumed to be a structure,
2755 a union type, or an array type, should be returned in registers
2756 for architecture GDBARCH. */
2759 i386_reg_struct_return_p (struct gdbarch
*gdbarch
, struct type
*type
)
2761 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2762 enum type_code code
= TYPE_CODE (type
);
2763 int len
= TYPE_LENGTH (type
);
2765 gdb_assert (code
== TYPE_CODE_STRUCT
2766 || code
== TYPE_CODE_UNION
2767 || code
== TYPE_CODE_ARRAY
);
2769 if (struct_convention
== pcc_struct_convention
2770 || (struct_convention
== default_struct_convention
2771 && tdep
->struct_return
== pcc_struct_return
))
2774 /* Structures consisting of a single `float', `double' or 'long
2775 double' member are returned in %st(0). */
2776 if (code
== TYPE_CODE_STRUCT
&& TYPE_NFIELDS (type
) == 1)
2778 type
= check_typedef (TYPE_FIELD_TYPE (type
, 0));
2779 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2780 return (len
== 4 || len
== 8 || len
== 12);
2783 return (len
== 1 || len
== 2 || len
== 4 || len
== 8);
2786 /* Determine, for architecture GDBARCH, how a return value of TYPE
2787 should be returned. If it is supposed to be returned in registers,
2788 and READBUF is non-zero, read the appropriate value from REGCACHE,
2789 and copy it into READBUF. If WRITEBUF is non-zero, write the value
2790 from WRITEBUF into REGCACHE. */
2792 static enum return_value_convention
2793 i386_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
2794 struct type
*type
, struct regcache
*regcache
,
2795 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2797 enum type_code code
= TYPE_CODE (type
);
2799 if (((code
== TYPE_CODE_STRUCT
2800 || code
== TYPE_CODE_UNION
2801 || code
== TYPE_CODE_ARRAY
)
2802 && !i386_reg_struct_return_p (gdbarch
, type
))
2803 /* Complex double and long double uses the struct return covention. */
2804 || (code
== TYPE_CODE_COMPLEX
&& TYPE_LENGTH (type
) == 16)
2805 || (code
== TYPE_CODE_COMPLEX
&& TYPE_LENGTH (type
) == 24)
2806 /* 128-bit decimal float uses the struct return convention. */
2807 || (code
== TYPE_CODE_DECFLOAT
&& TYPE_LENGTH (type
) == 16))
2809 /* The System V ABI says that:
2811 "A function that returns a structure or union also sets %eax
2812 to the value of the original address of the caller's area
2813 before it returns. Thus when the caller receives control
2814 again, the address of the returned object resides in register
2815 %eax and can be used to access the object."
2817 So the ABI guarantees that we can always find the return
2818 value just after the function has returned. */
2820 /* Note that the ABI doesn't mention functions returning arrays,
2821 which is something possible in certain languages such as Ada.
2822 In this case, the value is returned as if it was wrapped in
2823 a record, so the convention applied to records also applies
2830 regcache_raw_read_unsigned (regcache
, I386_EAX_REGNUM
, &addr
);
2831 read_memory (addr
, readbuf
, TYPE_LENGTH (type
));
2834 return RETURN_VALUE_ABI_RETURNS_ADDRESS
;
2837 /* This special case is for structures consisting of a single
2838 `float', `double' or 'long double' member. These structures are
2839 returned in %st(0). For these structures, we call ourselves
2840 recursively, changing TYPE into the type of the first member of
2841 the structure. Since that should work for all structures that
2842 have only one member, we don't bother to check the member's type
2844 if (code
== TYPE_CODE_STRUCT
&& TYPE_NFIELDS (type
) == 1)
2846 type
= check_typedef (TYPE_FIELD_TYPE (type
, 0));
2847 return i386_return_value (gdbarch
, function
, type
, regcache
,
2852 i386_extract_return_value (gdbarch
, type
, regcache
, readbuf
);
2854 i386_store_return_value (gdbarch
, type
, regcache
, writebuf
);
2856 return RETURN_VALUE_REGISTER_CONVENTION
;
2861 i387_ext_type (struct gdbarch
*gdbarch
)
2863 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2865 if (!tdep
->i387_ext_type
)
2867 tdep
->i387_ext_type
= tdesc_find_type (gdbarch
, "i387_ext");
2868 gdb_assert (tdep
->i387_ext_type
!= NULL
);
2871 return tdep
->i387_ext_type
;
2874 /* Construct type for pseudo BND registers. We can't use
2875 tdesc_find_type since a complement of one value has to be used
2876 to describe the upper bound. */
2878 static struct type
*
2879 i386_bnd_type (struct gdbarch
*gdbarch
)
2881 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2884 if (!tdep
->i386_bnd_type
)
2886 struct type
*t
, *bound_t
;
2887 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2889 /* The type we're building is described bellow: */
2894 void *ubound
; /* One complement of raw ubound field. */
2898 t
= arch_composite_type (gdbarch
,
2899 "__gdb_builtin_type_bound128", TYPE_CODE_STRUCT
);
2901 append_composite_type_field (t
, "lbound", bt
->builtin_data_ptr
);
2902 append_composite_type_field (t
, "ubound", bt
->builtin_data_ptr
);
2904 TYPE_NAME (t
) = "builtin_type_bound128";
2905 tdep
->i386_bnd_type
= t
;
2908 return tdep
->i386_bnd_type
;
2911 /* Construct vector type for pseudo YMM registers. We can't use
2912 tdesc_find_type since YMM isn't described in target description. */
2914 static struct type
*
2915 i386_ymm_type (struct gdbarch
*gdbarch
)
2917 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2919 if (!tdep
->i386_ymm_type
)
2921 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2923 /* The type we're building is this: */
2925 union __gdb_builtin_type_vec256i
2927 int128_t uint128
[2];
2928 int64_t v2_int64
[4];
2929 int32_t v4_int32
[8];
2930 int16_t v8_int16
[16];
2931 int8_t v16_int8
[32];
2932 double v2_double
[4];
2939 t
= arch_composite_type (gdbarch
,
2940 "__gdb_builtin_type_vec256i", TYPE_CODE_UNION
);
2941 append_composite_type_field (t
, "v8_float",
2942 init_vector_type (bt
->builtin_float
, 8));
2943 append_composite_type_field (t
, "v4_double",
2944 init_vector_type (bt
->builtin_double
, 4));
2945 append_composite_type_field (t
, "v32_int8",
2946 init_vector_type (bt
->builtin_int8
, 32));
2947 append_composite_type_field (t
, "v16_int16",
2948 init_vector_type (bt
->builtin_int16
, 16));
2949 append_composite_type_field (t
, "v8_int32",
2950 init_vector_type (bt
->builtin_int32
, 8));
2951 append_composite_type_field (t
, "v4_int64",
2952 init_vector_type (bt
->builtin_int64
, 4));
2953 append_composite_type_field (t
, "v2_int128",
2954 init_vector_type (bt
->builtin_int128
, 2));
2956 TYPE_VECTOR (t
) = 1;
2957 TYPE_NAME (t
) = "builtin_type_vec256i";
2958 tdep
->i386_ymm_type
= t
;
2961 return tdep
->i386_ymm_type
;
2964 /* Construct vector type for MMX registers. */
2965 static struct type
*
2966 i386_mmx_type (struct gdbarch
*gdbarch
)
2968 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2970 if (!tdep
->i386_mmx_type
)
2972 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2974 /* The type we're building is this: */
2976 union __gdb_builtin_type_vec64i
2979 int32_t v2_int32
[2];
2980 int16_t v4_int16
[4];
2987 t
= arch_composite_type (gdbarch
,
2988 "__gdb_builtin_type_vec64i", TYPE_CODE_UNION
);
2990 append_composite_type_field (t
, "uint64", bt
->builtin_int64
);
2991 append_composite_type_field (t
, "v2_int32",
2992 init_vector_type (bt
->builtin_int32
, 2));
2993 append_composite_type_field (t
, "v4_int16",
2994 init_vector_type (bt
->builtin_int16
, 4));
2995 append_composite_type_field (t
, "v8_int8",
2996 init_vector_type (bt
->builtin_int8
, 8));
2998 TYPE_VECTOR (t
) = 1;
2999 TYPE_NAME (t
) = "builtin_type_vec64i";
3000 tdep
->i386_mmx_type
= t
;
3003 return tdep
->i386_mmx_type
;
3006 /* Return the GDB type object for the "standard" data type of data in
3010 i386_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
3012 if (i386_bnd_regnum_p (gdbarch
, regnum
))
3013 return i386_bnd_type (gdbarch
);
3014 if (i386_mmx_regnum_p (gdbarch
, regnum
))
3015 return i386_mmx_type (gdbarch
);
3016 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
3017 return i386_ymm_type (gdbarch
);
3020 const struct builtin_type
*bt
= builtin_type (gdbarch
);
3021 if (i386_byte_regnum_p (gdbarch
, regnum
))
3022 return bt
->builtin_int8
;
3023 else if (i386_word_regnum_p (gdbarch
, regnum
))
3024 return bt
->builtin_int16
;
3025 else if (i386_dword_regnum_p (gdbarch
, regnum
))
3026 return bt
->builtin_int32
;
3029 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
3032 /* Map a cooked register onto a raw register or memory. For the i386,
3033 the MMX registers need to be mapped onto floating point registers. */
3036 i386_mmx_regnum_to_fp_regnum (struct regcache
*regcache
, int regnum
)
3038 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_regcache_arch (regcache
));
3043 mmxreg
= regnum
- tdep
->mm0_regnum
;
3044 regcache_raw_read_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), &fstat
);
3045 tos
= (fstat
>> 11) & 0x7;
3046 fpreg
= (mmxreg
+ tos
) % 8;
3048 return (I387_ST0_REGNUM (tdep
) + fpreg
);
3051 /* A helper function for us by i386_pseudo_register_read_value and
3052 amd64_pseudo_register_read_value. It does all the work but reads
3053 the data into an already-allocated value. */
3056 i386_pseudo_register_read_into_value (struct gdbarch
*gdbarch
,
3057 struct regcache
*regcache
,
3059 struct value
*result_value
)
3061 gdb_byte raw_buf
[MAX_REGISTER_SIZE
];
3062 enum register_status status
;
3063 gdb_byte
*buf
= value_contents_raw (result_value
);
3065 if (i386_mmx_regnum_p (gdbarch
, regnum
))
3067 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
3069 /* Extract (always little endian). */
3070 status
= regcache_raw_read (regcache
, fpnum
, raw_buf
);
3071 if (status
!= REG_VALID
)
3072 mark_value_bytes_unavailable (result_value
, 0,
3073 TYPE_LENGTH (value_type (result_value
)));
3075 memcpy (buf
, raw_buf
, register_size (gdbarch
, regnum
));
3079 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3080 if (i386_bnd_regnum_p (gdbarch
, regnum
))
3082 regnum
-= tdep
->bnd0_regnum
;
3084 /* Extract (always little endian). Read lower 128bits. */
3085 status
= regcache_raw_read (regcache
,
3086 I387_BND0R_REGNUM (tdep
) + regnum
,
3088 if (status
!= REG_VALID
)
3089 mark_value_bytes_unavailable (result_value
, 0, 16);
3092 enum bfd_endian byte_order
= gdbarch_byte_order (target_gdbarch ());
3093 LONGEST upper
, lower
;
3094 int size
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_data_ptr
);
3096 lower
= extract_unsigned_integer (raw_buf
, 8, byte_order
);
3097 upper
= extract_unsigned_integer (raw_buf
+ 8, 8, byte_order
);
3100 memcpy (buf
, &lower
, size
);
3101 memcpy (buf
+ size
, &upper
, size
);
3104 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
3106 regnum
-= tdep
->ymm0_regnum
;
3108 /* Extract (always little endian). Read lower 128bits. */
3109 status
= regcache_raw_read (regcache
,
3110 I387_XMM0_REGNUM (tdep
) + regnum
,
3112 if (status
!= REG_VALID
)
3113 mark_value_bytes_unavailable (result_value
, 0, 16);
3115 memcpy (buf
, raw_buf
, 16);
3116 /* Read upper 128bits. */
3117 status
= regcache_raw_read (regcache
,
3118 tdep
->ymm0h_regnum
+ regnum
,
3120 if (status
!= REG_VALID
)
3121 mark_value_bytes_unavailable (result_value
, 16, 32);
3123 memcpy (buf
+ 16, raw_buf
, 16);
3125 else if (i386_word_regnum_p (gdbarch
, regnum
))
3127 int gpnum
= regnum
- tdep
->ax_regnum
;
3129 /* Extract (always little endian). */
3130 status
= regcache_raw_read (regcache
, gpnum
, raw_buf
);
3131 if (status
!= REG_VALID
)
3132 mark_value_bytes_unavailable (result_value
, 0,
3133 TYPE_LENGTH (value_type (result_value
)));
3135 memcpy (buf
, raw_buf
, 2);
3137 else if (i386_byte_regnum_p (gdbarch
, regnum
))
3139 /* Check byte pseudo registers last since this function will
3140 be called from amd64_pseudo_register_read, which handles
3141 byte pseudo registers differently. */
3142 int gpnum
= regnum
- tdep
->al_regnum
;
3144 /* Extract (always little endian). We read both lower and
3146 status
= regcache_raw_read (regcache
, gpnum
% 4, raw_buf
);
3147 if (status
!= REG_VALID
)
3148 mark_value_bytes_unavailable (result_value
, 0,
3149 TYPE_LENGTH (value_type (result_value
)));
3150 else if (gpnum
>= 4)
3151 memcpy (buf
, raw_buf
+ 1, 1);
3153 memcpy (buf
, raw_buf
, 1);
3156 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
3160 static struct value
*
3161 i386_pseudo_register_read_value (struct gdbarch
*gdbarch
,
3162 struct regcache
*regcache
,
3165 struct value
*result
;
3167 result
= allocate_value (register_type (gdbarch
, regnum
));
3168 VALUE_LVAL (result
) = lval_register
;
3169 VALUE_REGNUM (result
) = regnum
;
3171 i386_pseudo_register_read_into_value (gdbarch
, regcache
, regnum
, result
);
3177 i386_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
3178 int regnum
, const gdb_byte
*buf
)
3180 gdb_byte raw_buf
[MAX_REGISTER_SIZE
];
3182 if (i386_mmx_regnum_p (gdbarch
, regnum
))
3184 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
3187 regcache_raw_read (regcache
, fpnum
, raw_buf
);
3188 /* ... Modify ... (always little endian). */
3189 memcpy (raw_buf
, buf
, register_size (gdbarch
, regnum
));
3191 regcache_raw_write (regcache
, fpnum
, raw_buf
);
3195 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3197 if (i386_bnd_regnum_p (gdbarch
, regnum
))
3199 ULONGEST upper
, lower
;
3200 int size
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_data_ptr
);
3201 enum bfd_endian byte_order
= gdbarch_byte_order (target_gdbarch ());
3203 /* New values from input value. */
3204 regnum
-= tdep
->bnd0_regnum
;
3205 lower
= extract_unsigned_integer (buf
, size
, byte_order
);
3206 upper
= extract_unsigned_integer (buf
+ size
, size
, byte_order
);
3208 /* Fetching register buffer. */
3209 regcache_raw_read (regcache
,
3210 I387_BND0R_REGNUM (tdep
) + regnum
,
3215 /* Set register bits. */
3216 memcpy (raw_buf
, &lower
, 8);
3217 memcpy (raw_buf
+ 8, &upper
, 8);
3220 regcache_raw_write (regcache
,
3221 I387_BND0R_REGNUM (tdep
) + regnum
,
3224 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
3226 regnum
-= tdep
->ymm0_regnum
;
3228 /* ... Write lower 128bits. */
3229 regcache_raw_write (regcache
,
3230 I387_XMM0_REGNUM (tdep
) + regnum
,
3232 /* ... Write upper 128bits. */
3233 regcache_raw_write (regcache
,
3234 tdep
->ymm0h_regnum
+ regnum
,
3237 else if (i386_word_regnum_p (gdbarch
, regnum
))
3239 int gpnum
= regnum
- tdep
->ax_regnum
;
3242 regcache_raw_read (regcache
, gpnum
, raw_buf
);
3243 /* ... Modify ... (always little endian). */
3244 memcpy (raw_buf
, buf
, 2);
3246 regcache_raw_write (regcache
, gpnum
, raw_buf
);
3248 else if (i386_byte_regnum_p (gdbarch
, regnum
))
3250 /* Check byte pseudo registers last since this function will
3251 be called from amd64_pseudo_register_read, which handles
3252 byte pseudo registers differently. */
3253 int gpnum
= regnum
- tdep
->al_regnum
;
3255 /* Read ... We read both lower and upper registers. */
3256 regcache_raw_read (regcache
, gpnum
% 4, raw_buf
);
3257 /* ... Modify ... (always little endian). */
3259 memcpy (raw_buf
+ 1, buf
, 1);
3261 memcpy (raw_buf
, buf
, 1);
3263 regcache_raw_write (regcache
, gpnum
% 4, raw_buf
);
3266 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
3271 /* Return the register number of the register allocated by GCC after
3272 REGNUM, or -1 if there is no such register. */
3275 i386_next_regnum (int regnum
)
3277 /* GCC allocates the registers in the order:
3279 %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ...
3281 Since storing a variable in %esp doesn't make any sense we return
3282 -1 for %ebp and for %esp itself. */
3283 static int next_regnum
[] =
3285 I386_EDX_REGNUM
, /* Slot for %eax. */
3286 I386_EBX_REGNUM
, /* Slot for %ecx. */
3287 I386_ECX_REGNUM
, /* Slot for %edx. */
3288 I386_ESI_REGNUM
, /* Slot for %ebx. */
3289 -1, -1, /* Slots for %esp and %ebp. */
3290 I386_EDI_REGNUM
, /* Slot for %esi. */
3291 I386_EBP_REGNUM
/* Slot for %edi. */
3294 if (regnum
>= 0 && regnum
< sizeof (next_regnum
) / sizeof (next_regnum
[0]))
3295 return next_regnum
[regnum
];
3300 /* Return nonzero if a value of type TYPE stored in register REGNUM
3301 needs any special handling. */
3304 i386_convert_register_p (struct gdbarch
*gdbarch
,
3305 int regnum
, struct type
*type
)
3307 int len
= TYPE_LENGTH (type
);
3309 /* Values may be spread across multiple registers. Most debugging
3310 formats aren't expressive enough to specify the locations, so
3311 some heuristics is involved. Right now we only handle types that
3312 have a length that is a multiple of the word size, since GCC
3313 doesn't seem to put any other types into registers. */
3314 if (len
> 4 && len
% 4 == 0)
3316 int last_regnum
= regnum
;
3320 last_regnum
= i386_next_regnum (last_regnum
);
3324 if (last_regnum
!= -1)
3328 return i387_convert_register_p (gdbarch
, regnum
, type
);
3331 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
3332 return its contents in TO. */
3335 i386_register_to_value (struct frame_info
*frame
, int regnum
,
3336 struct type
*type
, gdb_byte
*to
,
3337 int *optimizedp
, int *unavailablep
)
3339 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3340 int len
= TYPE_LENGTH (type
);
3342 if (i386_fp_regnum_p (gdbarch
, regnum
))
3343 return i387_register_to_value (frame
, regnum
, type
, to
,
3344 optimizedp
, unavailablep
);
3346 /* Read a value spread across multiple registers. */
3348 gdb_assert (len
> 4 && len
% 4 == 0);
3352 gdb_assert (regnum
!= -1);
3353 gdb_assert (register_size (gdbarch
, regnum
) == 4);
3355 if (!get_frame_register_bytes (frame
, regnum
, 0,
3356 register_size (gdbarch
, regnum
),
3357 to
, optimizedp
, unavailablep
))
3360 regnum
= i386_next_regnum (regnum
);
3365 *optimizedp
= *unavailablep
= 0;
3369 /* Write the contents FROM of a value of type TYPE into register
3370 REGNUM in frame FRAME. */
3373 i386_value_to_register (struct frame_info
*frame
, int regnum
,
3374 struct type
*type
, const gdb_byte
*from
)
3376 int len
= TYPE_LENGTH (type
);
3378 if (i386_fp_regnum_p (get_frame_arch (frame
), regnum
))
3380 i387_value_to_register (frame
, regnum
, type
, from
);
3384 /* Write a value spread across multiple registers. */
3386 gdb_assert (len
> 4 && len
% 4 == 0);
3390 gdb_assert (regnum
!= -1);
3391 gdb_assert (register_size (get_frame_arch (frame
), regnum
) == 4);
3393 put_frame_register (frame
, regnum
, from
);
3394 regnum
= i386_next_regnum (regnum
);
3400 /* Supply register REGNUM from the buffer specified by GREGS and LEN
3401 in the general-purpose register set REGSET to register cache
3402 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3405 i386_supply_gregset (const struct regset
*regset
, struct regcache
*regcache
,
3406 int regnum
, const void *gregs
, size_t len
)
3408 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
3409 const gdb_byte
*regs
= gregs
;
3412 gdb_assert (len
== tdep
->sizeof_gregset
);
3414 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
3416 if ((regnum
== i
|| regnum
== -1)
3417 && tdep
->gregset_reg_offset
[i
] != -1)
3418 regcache_raw_supply (regcache
, i
, regs
+ tdep
->gregset_reg_offset
[i
]);
3422 /* Collect register REGNUM from the register cache REGCACHE and store
3423 it in the buffer specified by GREGS and LEN as described by the
3424 general-purpose register set REGSET. If REGNUM is -1, do this for
3425 all registers in REGSET. */
3428 i386_collect_gregset (const struct regset
*regset
,
3429 const struct regcache
*regcache
,
3430 int regnum
, void *gregs
, size_t len
)
3432 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
3433 gdb_byte
*regs
= gregs
;
3436 gdb_assert (len
== tdep
->sizeof_gregset
);
3438 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
3440 if ((regnum
== i
|| regnum
== -1)
3441 && tdep
->gregset_reg_offset
[i
] != -1)
3442 regcache_raw_collect (regcache
, i
, regs
+ tdep
->gregset_reg_offset
[i
]);
3446 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
3447 in the floating-point register set REGSET to register cache
3448 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3451 i386_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
3452 int regnum
, const void *fpregs
, size_t len
)
3454 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
3456 if (len
== I387_SIZEOF_FXSAVE
)
3458 i387_supply_fxsave (regcache
, regnum
, fpregs
);
3462 gdb_assert (len
== tdep
->sizeof_fpregset
);
3463 i387_supply_fsave (regcache
, regnum
, fpregs
);
3466 /* Collect register REGNUM from the register cache REGCACHE and store
3467 it in the buffer specified by FPREGS and LEN as described by the
3468 floating-point register set REGSET. If REGNUM is -1, do this for
3469 all registers in REGSET. */
3472 i386_collect_fpregset (const struct regset
*regset
,
3473 const struct regcache
*regcache
,
3474 int regnum
, void *fpregs
, size_t len
)
3476 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
3478 if (len
== I387_SIZEOF_FXSAVE
)
3480 i387_collect_fxsave (regcache
, regnum
, fpregs
);
3484 gdb_assert (len
== tdep
->sizeof_fpregset
);
3485 i387_collect_fsave (regcache
, regnum
, fpregs
);
3488 /* Similar to i386_supply_fpregset, but use XSAVE extended state. */
3491 i386_supply_xstateregset (const struct regset
*regset
,
3492 struct regcache
*regcache
, int regnum
,
3493 const void *xstateregs
, size_t len
)
3495 i387_supply_xsave (regcache
, regnum
, xstateregs
);
3498 /* Similar to i386_collect_fpregset , but use XSAVE extended state. */
3501 i386_collect_xstateregset (const struct regset
*regset
,
3502 const struct regcache
*regcache
,
3503 int regnum
, void *xstateregs
, size_t len
)
3505 i387_collect_xsave (regcache
, regnum
, xstateregs
, 1);
3508 /* Return the appropriate register set for the core section identified
3509 by SECT_NAME and SECT_SIZE. */
3511 const struct regset
*
3512 i386_regset_from_core_section (struct gdbarch
*gdbarch
,
3513 const char *sect_name
, size_t sect_size
)
3515 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3517 if (strcmp (sect_name
, ".reg") == 0 && sect_size
== tdep
->sizeof_gregset
)
3519 if (tdep
->gregset
== NULL
)
3520 tdep
->gregset
= regset_alloc (gdbarch
, i386_supply_gregset
,
3521 i386_collect_gregset
);
3522 return tdep
->gregset
;
3525 if ((strcmp (sect_name
, ".reg2") == 0 && sect_size
== tdep
->sizeof_fpregset
)
3526 || (strcmp (sect_name
, ".reg-xfp") == 0
3527 && sect_size
== I387_SIZEOF_FXSAVE
))
3529 if (tdep
->fpregset
== NULL
)
3530 tdep
->fpregset
= regset_alloc (gdbarch
, i386_supply_fpregset
,
3531 i386_collect_fpregset
);
3532 return tdep
->fpregset
;
3535 if (strcmp (sect_name
, ".reg-xstate") == 0)
3537 if (tdep
->xstateregset
== NULL
)
3538 tdep
->xstateregset
= regset_alloc (gdbarch
,
3539 i386_supply_xstateregset
,
3540 i386_collect_xstateregset
);
3542 return tdep
->xstateregset
;
3549 /* Stuff for WIN32 PE style DLL's but is pretty generic really. */
3552 i386_pe_skip_trampoline_code (struct frame_info
*frame
,
3553 CORE_ADDR pc
, char *name
)
3555 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3556 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3559 if (pc
&& read_memory_unsigned_integer (pc
, 2, byte_order
) == 0x25ff)
3561 unsigned long indirect
=
3562 read_memory_unsigned_integer (pc
+ 2, 4, byte_order
);
3563 struct minimal_symbol
*indsym
=
3564 indirect
? lookup_minimal_symbol_by_pc (indirect
).minsym
: 0;
3565 const char *symname
= indsym
? SYMBOL_LINKAGE_NAME (indsym
) : 0;
3569 if (strncmp (symname
, "__imp_", 6) == 0
3570 || strncmp (symname
, "_imp_", 5) == 0)
3572 read_memory_unsigned_integer (indirect
, 4, byte_order
);
3575 return 0; /* Not a trampoline. */
3579 /* Return whether the THIS_FRAME corresponds to a sigtramp
3583 i386_sigtramp_p (struct frame_info
*this_frame
)
3585 CORE_ADDR pc
= get_frame_pc (this_frame
);
3588 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
3589 return (name
&& strcmp ("_sigtramp", name
) == 0);
3593 /* We have two flavours of disassembly. The machinery on this page
3594 deals with switching between those. */
3597 i386_print_insn (bfd_vma pc
, struct disassemble_info
*info
)
3599 gdb_assert (disassembly_flavor
== att_flavor
3600 || disassembly_flavor
== intel_flavor
);
3602 /* FIXME: kettenis/20020915: Until disassembler_options is properly
3603 constified, cast to prevent a compiler warning. */
3604 info
->disassembler_options
= (char *) disassembly_flavor
;
3606 return print_insn_i386 (pc
, info
);
3610 /* There are a few i386 architecture variants that differ only
3611 slightly from the generic i386 target. For now, we don't give them
3612 their own source file, but include them here. As a consequence,
3613 they'll always be included. */
3615 /* System V Release 4 (SVR4). */
3617 /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp
3621 i386_svr4_sigtramp_p (struct frame_info
*this_frame
)
3623 CORE_ADDR pc
= get_frame_pc (this_frame
);
3626 /* The origin of these symbols is currently unknown. */
3627 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
3628 return (name
&& (strcmp ("_sigreturn", name
) == 0
3629 || strcmp ("sigvechandler", name
) == 0));
3632 /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the
3633 address of the associated sigcontext (ucontext) structure. */
3636 i386_svr4_sigcontext_addr (struct frame_info
*this_frame
)
3638 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3639 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3643 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
3644 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
3646 return read_memory_unsigned_integer (sp
+ 8, 4, byte_order
);
3651 /* Implementation of `gdbarch_stap_is_single_operand', as defined in
3655 i386_stap_is_single_operand (struct gdbarch
*gdbarch
, const char *s
)
3657 return (*s
== '$' /* Literal number. */
3658 || (isdigit (*s
) && s
[1] == '(' && s
[2] == '%') /* Displacement. */
3659 || (*s
== '(' && s
[1] == '%') /* Register indirection. */
3660 || (*s
== '%' && isalpha (s
[1]))); /* Register access. */
3663 /* Helper function for i386_stap_parse_special_token.
3665 This function parses operands of the form `-8+3+1(%rbp)', which
3666 must be interpreted as `*(-8 + 3 - 1 + (void *) $eax)'.
3668 Return 1 if the operand was parsed successfully, zero
3672 i386_stap_parse_special_token_triplet (struct gdbarch
*gdbarch
,
3673 struct stap_parse_info
*p
)
3675 const char *s
= p
->arg
;
3677 if (isdigit (*s
) || *s
== '-' || *s
== '+')
3681 long displacements
[3];
3697 displacements
[0] = strtol (s
, &endp
, 10);
3700 if (*s
!= '+' && *s
!= '-')
3702 /* We are not dealing with a triplet. */
3715 displacements
[1] = strtol (s
, &endp
, 10);
3718 if (*s
!= '+' && *s
!= '-')
3720 /* We are not dealing with a triplet. */
3733 displacements
[2] = strtol (s
, &endp
, 10);
3736 if (*s
!= '(' || s
[1] != '%')
3742 while (isalnum (*s
))
3749 regname
= alloca (len
+ 1);
3751 strncpy (regname
, start
, len
);
3752 regname
[len
] = '\0';
3754 if (user_reg_map_name_to_regnum (gdbarch
, regname
, len
) == -1)
3755 error (_("Invalid register name `%s' on expression `%s'."),
3756 regname
, p
->saved_arg
);
3758 for (i
= 0; i
< 3; i
++)
3760 write_exp_elt_opcode (OP_LONG
);
3761 write_exp_elt_type (builtin_type (gdbarch
)->builtin_long
);
3762 write_exp_elt_longcst (displacements
[i
]);
3763 write_exp_elt_opcode (OP_LONG
);
3765 write_exp_elt_opcode (UNOP_NEG
);
3768 write_exp_elt_opcode (OP_REGISTER
);
3771 write_exp_string (str
);
3772 write_exp_elt_opcode (OP_REGISTER
);
3774 write_exp_elt_opcode (UNOP_CAST
);
3775 write_exp_elt_type (builtin_type (gdbarch
)->builtin_data_ptr
);
3776 write_exp_elt_opcode (UNOP_CAST
);
3778 write_exp_elt_opcode (BINOP_ADD
);
3779 write_exp_elt_opcode (BINOP_ADD
);
3780 write_exp_elt_opcode (BINOP_ADD
);
3782 write_exp_elt_opcode (UNOP_CAST
);
3783 write_exp_elt_type (lookup_pointer_type (p
->arg_type
));
3784 write_exp_elt_opcode (UNOP_CAST
);
3786 write_exp_elt_opcode (UNOP_IND
);
3796 /* Helper function for i386_stap_parse_special_token.
3798 This function parses operands of the form `register base +
3799 (register index * size) + offset', as represented in
3800 `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'.
3802 Return 1 if the operand was parsed successfully, zero
3806 i386_stap_parse_special_token_three_arg_disp (struct gdbarch
*gdbarch
,
3807 struct stap_parse_info
*p
)
3809 const char *s
= p
->arg
;
3811 if (isdigit (*s
) || *s
== '(' || *s
== '-' || *s
== '+')
3813 int offset_minus
= 0;
3822 struct stoken base_token
, index_token
;
3832 if (offset_minus
&& !isdigit (*s
))
3839 offset
= strtol (s
, &endp
, 10);
3843 if (*s
!= '(' || s
[1] != '%')
3849 while (isalnum (*s
))
3852 if (*s
!= ',' || s
[1] != '%')
3855 len_base
= s
- start
;
3856 base
= alloca (len_base
+ 1);
3857 strncpy (base
, start
, len_base
);
3858 base
[len_base
] = '\0';
3860 if (user_reg_map_name_to_regnum (gdbarch
, base
, len_base
) == -1)
3861 error (_("Invalid register name `%s' on expression `%s'."),
3862 base
, p
->saved_arg
);
3867 while (isalnum (*s
))
3870 len_index
= s
- start
;
3871 index
= alloca (len_index
+ 1);
3872 strncpy (index
, start
, len_index
);
3873 index
[len_index
] = '\0';
3875 if (user_reg_map_name_to_regnum (gdbarch
, index
, len_index
) == -1)
3876 error (_("Invalid register name `%s' on expression `%s'."),
3877 index
, p
->saved_arg
);
3879 if (*s
!= ',' && *s
!= ')')
3895 size
= strtol (s
, &endp
, 10);
3906 write_exp_elt_opcode (OP_LONG
);
3907 write_exp_elt_type (builtin_type (gdbarch
)->builtin_long
);
3908 write_exp_elt_longcst (offset
);
3909 write_exp_elt_opcode (OP_LONG
);
3911 write_exp_elt_opcode (UNOP_NEG
);
3914 write_exp_elt_opcode (OP_REGISTER
);
3915 base_token
.ptr
= base
;
3916 base_token
.length
= len_base
;
3917 write_exp_string (base_token
);
3918 write_exp_elt_opcode (OP_REGISTER
);
3921 write_exp_elt_opcode (BINOP_ADD
);
3923 write_exp_elt_opcode (OP_REGISTER
);
3924 index_token
.ptr
= index
;
3925 index_token
.length
= len_index
;
3926 write_exp_string (index_token
);
3927 write_exp_elt_opcode (OP_REGISTER
);
3931 write_exp_elt_opcode (OP_LONG
);
3932 write_exp_elt_type (builtin_type (gdbarch
)->builtin_long
);
3933 write_exp_elt_longcst (size
);
3934 write_exp_elt_opcode (OP_LONG
);
3936 write_exp_elt_opcode (UNOP_NEG
);
3937 write_exp_elt_opcode (BINOP_MUL
);
3940 write_exp_elt_opcode (BINOP_ADD
);
3942 write_exp_elt_opcode (UNOP_CAST
);
3943 write_exp_elt_type (lookup_pointer_type (p
->arg_type
));
3944 write_exp_elt_opcode (UNOP_CAST
);
3946 write_exp_elt_opcode (UNOP_IND
);
3956 /* Implementation of `gdbarch_stap_parse_special_token', as defined in
3960 i386_stap_parse_special_token (struct gdbarch
*gdbarch
,
3961 struct stap_parse_info
*p
)
3963 /* In order to parse special tokens, we use a state-machine that go
3964 through every known token and try to get a match. */
3968 THREE_ARG_DISPLACEMENT
,
3972 current_state
= TRIPLET
;
3974 /* The special tokens to be parsed here are:
3976 - `register base + (register index * size) + offset', as represented
3977 in `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'.
3979 - Operands of the form `-8+3+1(%rbp)', which must be interpreted as
3980 `*(-8 + 3 - 1 + (void *) $eax)'. */
3982 while (current_state
!= DONE
)
3984 switch (current_state
)
3987 if (i386_stap_parse_special_token_triplet (gdbarch
, p
))
3991 case THREE_ARG_DISPLACEMENT
:
3992 if (i386_stap_parse_special_token_three_arg_disp (gdbarch
, p
))
3997 /* Advancing to the next state. */
4009 i386_elf_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
4011 static const char *const stap_integer_prefixes
[] = { "$", NULL
};
4012 static const char *const stap_register_prefixes
[] = { "%", NULL
};
4013 static const char *const stap_register_indirection_prefixes
[] = { "(",
4015 static const char *const stap_register_indirection_suffixes
[] = { ")",
4018 /* We typically use stabs-in-ELF with the SVR4 register numbering. */
4019 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
4021 /* Registering SystemTap handlers. */
4022 set_gdbarch_stap_integer_prefixes (gdbarch
, stap_integer_prefixes
);
4023 set_gdbarch_stap_register_prefixes (gdbarch
, stap_register_prefixes
);
4024 set_gdbarch_stap_register_indirection_prefixes (gdbarch
,
4025 stap_register_indirection_prefixes
);
4026 set_gdbarch_stap_register_indirection_suffixes (gdbarch
,
4027 stap_register_indirection_suffixes
);
4028 set_gdbarch_stap_is_single_operand (gdbarch
,
4029 i386_stap_is_single_operand
);
4030 set_gdbarch_stap_parse_special_token (gdbarch
,
4031 i386_stap_parse_special_token
);
4034 /* System V Release 4 (SVR4). */
4037 i386_svr4_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
4039 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4041 /* System V Release 4 uses ELF. */
4042 i386_elf_init_abi (info
, gdbarch
);
4044 /* System V Release 4 has shared libraries. */
4045 set_gdbarch_skip_trampoline_code (gdbarch
, find_solib_trampoline_target
);
4047 tdep
->sigtramp_p
= i386_svr4_sigtramp_p
;
4048 tdep
->sigcontext_addr
= i386_svr4_sigcontext_addr
;
4049 tdep
->sc_pc_offset
= 36 + 14 * 4;
4050 tdep
->sc_sp_offset
= 36 + 17 * 4;
4052 tdep
->jb_pc_offset
= 20;
4058 i386_go32_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
4060 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4062 /* DJGPP doesn't have any special frames for signal handlers. */
4063 tdep
->sigtramp_p
= NULL
;
4065 tdep
->jb_pc_offset
= 36;
4067 /* DJGPP does not support the SSE registers. */
4068 if (! tdesc_has_registers (info
.target_desc
))
4069 tdep
->tdesc
= tdesc_i386_mmx
;
4071 /* Native compiler is GCC, which uses the SVR4 register numbering
4072 even in COFF and STABS. See the comment in i386_gdbarch_init,
4073 before the calls to set_gdbarch_stab_reg_to_regnum and
4074 set_gdbarch_sdb_reg_to_regnum. */
4075 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
4076 set_gdbarch_sdb_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
4078 set_gdbarch_has_dos_based_file_system (gdbarch
, 1);
4082 /* i386 register groups. In addition to the normal groups, add "mmx"
4085 static struct reggroup
*i386_sse_reggroup
;
4086 static struct reggroup
*i386_mmx_reggroup
;
4089 i386_init_reggroups (void)
4091 i386_sse_reggroup
= reggroup_new ("sse", USER_REGGROUP
);
4092 i386_mmx_reggroup
= reggroup_new ("mmx", USER_REGGROUP
);
4096 i386_add_reggroups (struct gdbarch
*gdbarch
)
4098 reggroup_add (gdbarch
, i386_sse_reggroup
);
4099 reggroup_add (gdbarch
, i386_mmx_reggroup
);
4100 reggroup_add (gdbarch
, general_reggroup
);
4101 reggroup_add (gdbarch
, float_reggroup
);
4102 reggroup_add (gdbarch
, all_reggroup
);
4103 reggroup_add (gdbarch
, save_reggroup
);
4104 reggroup_add (gdbarch
, restore_reggroup
);
4105 reggroup_add (gdbarch
, vector_reggroup
);
4106 reggroup_add (gdbarch
, system_reggroup
);
4110 i386_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
4111 struct reggroup
*group
)
4113 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4114 int fp_regnum_p
, mmx_regnum_p
, xmm_regnum_p
, mxcsr_regnum_p
,
4115 ymm_regnum_p
, ymmh_regnum_p
, bndr_regnum_p
, bnd_regnum_p
,
4118 /* Don't include pseudo registers, except for MMX, in any register
4120 if (i386_byte_regnum_p (gdbarch
, regnum
))
4123 if (i386_word_regnum_p (gdbarch
, regnum
))
4126 if (i386_dword_regnum_p (gdbarch
, regnum
))
4129 mmx_regnum_p
= i386_mmx_regnum_p (gdbarch
, regnum
);
4130 if (group
== i386_mmx_reggroup
)
4131 return mmx_regnum_p
;
4133 xmm_regnum_p
= i386_xmm_regnum_p (gdbarch
, regnum
);
4134 mxcsr_regnum_p
= i386_mxcsr_regnum_p (gdbarch
, regnum
);
4135 if (group
== i386_sse_reggroup
)
4136 return xmm_regnum_p
|| mxcsr_regnum_p
;
4138 ymm_regnum_p
= i386_ymm_regnum_p (gdbarch
, regnum
);
4139 if (group
== vector_reggroup
)
4140 return (mmx_regnum_p
4144 && ((tdep
->xcr0
& I386_XSTATE_AVX_MASK
)
4145 == I386_XSTATE_SSE_MASK
)));
4147 fp_regnum_p
= (i386_fp_regnum_p (gdbarch
, regnum
)
4148 || i386_fpc_regnum_p (gdbarch
, regnum
));
4149 if (group
== float_reggroup
)
4152 /* For "info reg all", don't include upper YMM registers nor XMM
4153 registers when AVX is supported. */
4154 ymmh_regnum_p
= i386_ymmh_regnum_p (gdbarch
, regnum
);
4155 if (group
== all_reggroup
4157 && (tdep
->xcr0
& I386_XSTATE_AVX
))
4161 bnd_regnum_p
= i386_bnd_regnum_p (gdbarch
, regnum
);
4162 if (group
== all_reggroup
4163 && ((bnd_regnum_p
&& (tdep
->xcr0
& I386_XSTATE_MPX_MASK
))))
4164 return bnd_regnum_p
;
4166 bndr_regnum_p
= i386_bndr_regnum_p (gdbarch
, regnum
);
4167 if (group
== all_reggroup
4168 && ((bndr_regnum_p
&& (tdep
->xcr0
& I386_XSTATE_MPX_MASK
))))
4171 mpx_ctrl_regnum_p
= i386_mpx_ctrl_regnum_p (gdbarch
, regnum
);
4172 if (group
== all_reggroup
4173 && ((mpx_ctrl_regnum_p
&& (tdep
->xcr0
& I386_XSTATE_MPX_MASK
))))
4174 return mpx_ctrl_regnum_p
;
4176 if (group
== general_reggroup
)
4177 return (!fp_regnum_p
4185 && !mpx_ctrl_regnum_p
);
4187 return default_register_reggroup_p (gdbarch
, regnum
, group
);
4191 /* Get the ARGIth function argument for the current function. */
4194 i386_fetch_pointer_argument (struct frame_info
*frame
, int argi
,
4197 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4198 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4199 CORE_ADDR sp
= get_frame_register_unsigned (frame
, I386_ESP_REGNUM
);
4200 return read_memory_unsigned_integer (sp
+ (4 * (argi
+ 1)), 4, byte_order
);
4204 i386_skip_permanent_breakpoint (struct regcache
*regcache
)
4206 CORE_ADDR current_pc
= regcache_read_pc (regcache
);
4208 /* On i386, breakpoint is exactly 1 byte long, so we just
4209 adjust the PC in the regcache. */
4211 regcache_write_pc (regcache
, current_pc
);
4215 #define PREFIX_REPZ 0x01
4216 #define PREFIX_REPNZ 0x02
4217 #define PREFIX_LOCK 0x04
4218 #define PREFIX_DATA 0x08
4219 #define PREFIX_ADDR 0x10
4231 /* i386 arith/logic operations */
4244 struct i386_record_s
4246 struct gdbarch
*gdbarch
;
4247 struct regcache
*regcache
;
4248 CORE_ADDR orig_addr
;
4254 uint8_t mod
, reg
, rm
;
4263 /* Parse the "modrm" part of the memory address irp->addr points at.
4264 Returns -1 if something goes wrong, 0 otherwise. */
4267 i386_record_modrm (struct i386_record_s
*irp
)
4269 struct gdbarch
*gdbarch
= irp
->gdbarch
;
4271 if (record_read_memory (gdbarch
, irp
->addr
, &irp
->modrm
, 1))
4275 irp
->mod
= (irp
->modrm
>> 6) & 3;
4276 irp
->reg
= (irp
->modrm
>> 3) & 7;
4277 irp
->rm
= irp
->modrm
& 7;
4282 /* Extract the memory address that the current instruction writes to,
4283 and return it in *ADDR. Return -1 if something goes wrong. */
4286 i386_record_lea_modrm_addr (struct i386_record_s
*irp
, uint64_t *addr
)
4288 struct gdbarch
*gdbarch
= irp
->gdbarch
;
4289 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4294 if (irp
->aflag
|| irp
->regmap
[X86_RECORD_R8_REGNUM
])
4301 uint8_t base
= irp
->rm
;
4306 if (record_read_memory (gdbarch
, irp
->addr
, &byte
, 1))
4309 scale
= (byte
>> 6) & 3;
4310 index
= ((byte
>> 3) & 7) | irp
->rex_x
;
4318 if ((base
& 7) == 5)
4321 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 4))
4324 *addr
= extract_signed_integer (buf
, 4, byte_order
);
4325 if (irp
->regmap
[X86_RECORD_R8_REGNUM
] && !havesib
)
4326 *addr
+= irp
->addr
+ irp
->rip_offset
;
4330 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 1))
4333 *addr
= (int8_t) buf
[0];
4336 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 4))
4338 *addr
= extract_signed_integer (buf
, 4, byte_order
);
4346 if (base
== 4 && irp
->popl_esp_hack
)
4347 *addr
+= irp
->popl_esp_hack
;
4348 regcache_raw_read_unsigned (irp
->regcache
, irp
->regmap
[base
],
4351 if (irp
->aflag
== 2)
4356 *addr
= (uint32_t) (offset64
+ *addr
);
4358 if (havesib
&& (index
!= 4 || scale
!= 0))
4360 regcache_raw_read_unsigned (irp
->regcache
, irp
->regmap
[index
],
4362 if (irp
->aflag
== 2)
4363 *addr
+= offset64
<< scale
;
4365 *addr
= (uint32_t) (*addr
+ (offset64
<< scale
));
4370 /* Since we are in 64-bit mode with ADDR32 prefix, zero-extend
4371 address from 32-bit to 64-bit. */
4372 *addr
= (uint32_t) *addr
;
4383 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 2))
4386 *addr
= extract_signed_integer (buf
, 2, byte_order
);
4392 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 1))
4395 *addr
= (int8_t) buf
[0];
4398 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 2))
4401 *addr
= extract_signed_integer (buf
, 2, byte_order
);
4408 regcache_raw_read_unsigned (irp
->regcache
,
4409 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
4411 *addr
= (uint32_t) (*addr
+ offset64
);
4412 regcache_raw_read_unsigned (irp
->regcache
,
4413 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
4415 *addr
= (uint32_t) (*addr
+ offset64
);
4418 regcache_raw_read_unsigned (irp
->regcache
,
4419 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
4421 *addr
= (uint32_t) (*addr
+ offset64
);
4422 regcache_raw_read_unsigned (irp
->regcache
,
4423 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
4425 *addr
= (uint32_t) (*addr
+ offset64
);
4428 regcache_raw_read_unsigned (irp
->regcache
,
4429 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
4431 *addr
= (uint32_t) (*addr
+ offset64
);
4432 regcache_raw_read_unsigned (irp
->regcache
,
4433 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
4435 *addr
= (uint32_t) (*addr
+ offset64
);
4438 regcache_raw_read_unsigned (irp
->regcache
,
4439 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
4441 *addr
= (uint32_t) (*addr
+ offset64
);
4442 regcache_raw_read_unsigned (irp
->regcache
,
4443 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
4445 *addr
= (uint32_t) (*addr
+ offset64
);
4448 regcache_raw_read_unsigned (irp
->regcache
,
4449 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
4451 *addr
= (uint32_t) (*addr
+ offset64
);
4454 regcache_raw_read_unsigned (irp
->regcache
,
4455 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
4457 *addr
= (uint32_t) (*addr
+ offset64
);
4460 regcache_raw_read_unsigned (irp
->regcache
,
4461 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
4463 *addr
= (uint32_t) (*addr
+ offset64
);
4466 regcache_raw_read_unsigned (irp
->regcache
,
4467 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
4469 *addr
= (uint32_t) (*addr
+ offset64
);
4479 /* Record the address and contents of the memory that will be changed
4480 by the current instruction. Return -1 if something goes wrong, 0
4484 i386_record_lea_modrm (struct i386_record_s
*irp
)
4486 struct gdbarch
*gdbarch
= irp
->gdbarch
;
4489 if (irp
->override
>= 0)
4491 if (record_full_memory_query
)
4495 target_terminal_ours ();
4497 Process record ignores the memory change of instruction at address %s\n\
4498 because it can't get the value of the segment register.\n\
4499 Do you want to stop the program?"),
4500 paddress (gdbarch
, irp
->orig_addr
));
4501 target_terminal_inferior ();
4509 if (i386_record_lea_modrm_addr (irp
, &addr
))
4512 if (record_full_arch_list_add_mem (addr
, 1 << irp
->ot
))
4518 /* Record the effects of a push operation. Return -1 if something
4519 goes wrong, 0 otherwise. */
4522 i386_record_push (struct i386_record_s
*irp
, int size
)
4526 if (record_full_arch_list_add_reg (irp
->regcache
,
4527 irp
->regmap
[X86_RECORD_RESP_REGNUM
]))
4529 regcache_raw_read_unsigned (irp
->regcache
,
4530 irp
->regmap
[X86_RECORD_RESP_REGNUM
],
4532 if (record_full_arch_list_add_mem ((CORE_ADDR
) addr
- size
, size
))
4539 /* Defines contents to record. */
4540 #define I386_SAVE_FPU_REGS 0xfffd
4541 #define I386_SAVE_FPU_ENV 0xfffe
4542 #define I386_SAVE_FPU_ENV_REG_STACK 0xffff
4544 /* Record the values of the floating point registers which will be
4545 changed by the current instruction. Returns -1 if something is
4546 wrong, 0 otherwise. */
4548 static int i386_record_floats (struct gdbarch
*gdbarch
,
4549 struct i386_record_s
*ir
,
4552 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4555 /* Oza: Because of floating point insn push/pop of fpu stack is going to
4556 happen. Currently we store st0-st7 registers, but we need not store all
4557 registers all the time, in future we use ftag register and record only
4558 those who are not marked as an empty. */
4560 if (I386_SAVE_FPU_REGS
== iregnum
)
4562 for (i
= I387_ST0_REGNUM (tdep
); i
<= I387_ST0_REGNUM (tdep
) + 7; i
++)
4564 if (record_full_arch_list_add_reg (ir
->regcache
, i
))
4568 else if (I386_SAVE_FPU_ENV
== iregnum
)
4570 for (i
= I387_FCTRL_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
4572 if (record_full_arch_list_add_reg (ir
->regcache
, i
))
4576 else if (I386_SAVE_FPU_ENV_REG_STACK
== iregnum
)
4578 for (i
= I387_ST0_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
4580 if (record_full_arch_list_add_reg (ir
->regcache
, i
))
4584 else if ((iregnum
>= I387_ST0_REGNUM (tdep
)) &&
4585 (iregnum
<= I387_FOP_REGNUM (tdep
)))
4587 if (record_full_arch_list_add_reg (ir
->regcache
,iregnum
))
4592 /* Parameter error. */
4595 if(I386_SAVE_FPU_ENV
!= iregnum
)
4597 for (i
= I387_FCTRL_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
4599 if (record_full_arch_list_add_reg (ir
->regcache
, i
))
4606 /* Parse the current instruction, and record the values of the
4607 registers and memory that will be changed by the current
4608 instruction. Returns -1 if something goes wrong, 0 otherwise. */
4610 #define I386_RECORD_FULL_ARCH_LIST_ADD_REG(regnum) \
4611 record_full_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)])
4614 i386_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4615 CORE_ADDR input_addr
)
4617 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4623 gdb_byte buf
[MAX_REGISTER_SIZE
];
4624 struct i386_record_s ir
;
4625 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4629 memset (&ir
, 0, sizeof (struct i386_record_s
));
4630 ir
.regcache
= regcache
;
4631 ir
.addr
= input_addr
;
4632 ir
.orig_addr
= input_addr
;
4636 ir
.popl_esp_hack
= 0;
4637 ir
.regmap
= tdep
->record_regmap
;
4638 ir
.gdbarch
= gdbarch
;
4640 if (record_debug
> 1)
4641 fprintf_unfiltered (gdb_stdlog
, "Process record: i386_process_record "
4643 paddress (gdbarch
, ir
.addr
));
4648 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
4651 switch (opcode8
) /* Instruction prefixes */
4653 case REPE_PREFIX_OPCODE
:
4654 prefixes
|= PREFIX_REPZ
;
4656 case REPNE_PREFIX_OPCODE
:
4657 prefixes
|= PREFIX_REPNZ
;
4659 case LOCK_PREFIX_OPCODE
:
4660 prefixes
|= PREFIX_LOCK
;
4662 case CS_PREFIX_OPCODE
:
4663 ir
.override
= X86_RECORD_CS_REGNUM
;
4665 case SS_PREFIX_OPCODE
:
4666 ir
.override
= X86_RECORD_SS_REGNUM
;
4668 case DS_PREFIX_OPCODE
:
4669 ir
.override
= X86_RECORD_DS_REGNUM
;
4671 case ES_PREFIX_OPCODE
:
4672 ir
.override
= X86_RECORD_ES_REGNUM
;
4674 case FS_PREFIX_OPCODE
:
4675 ir
.override
= X86_RECORD_FS_REGNUM
;
4677 case GS_PREFIX_OPCODE
:
4678 ir
.override
= X86_RECORD_GS_REGNUM
;
4680 case DATA_PREFIX_OPCODE
:
4681 prefixes
|= PREFIX_DATA
;
4683 case ADDR_PREFIX_OPCODE
:
4684 prefixes
|= PREFIX_ADDR
;
4686 case 0x40: /* i386 inc %eax */
4687 case 0x41: /* i386 inc %ecx */
4688 case 0x42: /* i386 inc %edx */
4689 case 0x43: /* i386 inc %ebx */
4690 case 0x44: /* i386 inc %esp */
4691 case 0x45: /* i386 inc %ebp */
4692 case 0x46: /* i386 inc %esi */
4693 case 0x47: /* i386 inc %edi */
4694 case 0x48: /* i386 dec %eax */
4695 case 0x49: /* i386 dec %ecx */
4696 case 0x4a: /* i386 dec %edx */
4697 case 0x4b: /* i386 dec %ebx */
4698 case 0x4c: /* i386 dec %esp */
4699 case 0x4d: /* i386 dec %ebp */
4700 case 0x4e: /* i386 dec %esi */
4701 case 0x4f: /* i386 dec %edi */
4702 if (ir
.regmap
[X86_RECORD_R8_REGNUM
]) /* 64 bit target */
4705 rex_w
= (opcode8
>> 3) & 1;
4706 rex_r
= (opcode8
& 0x4) << 1;
4707 ir
.rex_x
= (opcode8
& 0x2) << 2;
4708 ir
.rex_b
= (opcode8
& 0x1) << 3;
4710 else /* 32 bit target */
4719 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && rex_w
== 1)
4725 if (prefixes
& PREFIX_DATA
)
4728 if (prefixes
& PREFIX_ADDR
)
4730 else if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4733 /* Now check op code. */
4734 opcode
= (uint32_t) opcode8
;
4739 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
4742 opcode
= (uint32_t) opcode8
| 0x0f00;
4746 case 0x00: /* arith & logic */
4794 if (((opcode
>> 3) & 7) != OP_CMPL
)
4796 if ((opcode
& 1) == 0)
4799 ir
.ot
= ir
.dflag
+ OT_WORD
;
4801 switch ((opcode
>> 1) & 3)
4803 case 0: /* OP Ev, Gv */
4804 if (i386_record_modrm (&ir
))
4808 if (i386_record_lea_modrm (&ir
))
4814 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4816 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
4819 case 1: /* OP Gv, Ev */
4820 if (i386_record_modrm (&ir
))
4823 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4825 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
4827 case 2: /* OP A, Iv */
4828 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4832 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4835 case 0x80: /* GRP1 */
4839 if (i386_record_modrm (&ir
))
4842 if (ir
.reg
!= OP_CMPL
)
4844 if ((opcode
& 1) == 0)
4847 ir
.ot
= ir
.dflag
+ OT_WORD
;
4854 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
4855 if (i386_record_lea_modrm (&ir
))
4859 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
4861 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4864 case 0x40: /* inc */
4873 case 0x48: /* dec */
4882 I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode
& 7);
4883 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4886 case 0xf6: /* GRP3 */
4888 if ((opcode
& 1) == 0)
4891 ir
.ot
= ir
.dflag
+ OT_WORD
;
4892 if (i386_record_modrm (&ir
))
4895 if (ir
.mod
!= 3 && ir
.reg
== 0)
4896 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
4901 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4907 if (i386_record_lea_modrm (&ir
))
4913 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4915 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
4917 if (ir
.reg
== 3) /* neg */
4918 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4924 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4925 if (ir
.ot
!= OT_BYTE
)
4926 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
4927 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4931 opcode
= opcode
<< 8 | ir
.modrm
;
4937 case 0xfe: /* GRP4 */
4938 case 0xff: /* GRP5 */
4939 if (i386_record_modrm (&ir
))
4941 if (ir
.reg
>= 2 && opcode
== 0xfe)
4944 opcode
= opcode
<< 8 | ir
.modrm
;
4951 if ((opcode
& 1) == 0)
4954 ir
.ot
= ir
.dflag
+ OT_WORD
;
4957 if (i386_record_lea_modrm (&ir
))
4963 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4965 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
4967 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4970 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4972 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4974 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4977 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
4978 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4980 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4984 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4987 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4989 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4994 opcode
= opcode
<< 8 | ir
.modrm
;
5000 case 0x84: /* test */
5004 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5007 case 0x98: /* CWDE/CBW */
5008 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5011 case 0x99: /* CDQ/CWD */
5012 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5013 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5016 case 0x0faf: /* imul */
5019 ir
.ot
= ir
.dflag
+ OT_WORD
;
5020 if (i386_record_modrm (&ir
))
5023 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
5024 else if (opcode
== 0x6b)
5027 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5029 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5030 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5033 case 0x0fc0: /* xadd */
5035 if ((opcode
& 1) == 0)
5038 ir
.ot
= ir
.dflag
+ OT_WORD
;
5039 if (i386_record_modrm (&ir
))
5044 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5046 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5047 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5049 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5053 if (i386_record_lea_modrm (&ir
))
5055 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5057 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5059 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5062 case 0x0fb0: /* cmpxchg */
5064 if ((opcode
& 1) == 0)
5067 ir
.ot
= ir
.dflag
+ OT_WORD
;
5068 if (i386_record_modrm (&ir
))
5073 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5074 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5076 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5080 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5081 if (i386_record_lea_modrm (&ir
))
5084 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5087 case 0x0fc7: /* cmpxchg8b */
5088 if (i386_record_modrm (&ir
))
5093 opcode
= opcode
<< 8 | ir
.modrm
;
5096 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5097 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5098 if (i386_record_lea_modrm (&ir
))
5100 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5103 case 0x50: /* push */
5113 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5115 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5119 case 0x06: /* push es */
5120 case 0x0e: /* push cs */
5121 case 0x16: /* push ss */
5122 case 0x1e: /* push ds */
5123 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5128 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5132 case 0x0fa0: /* push fs */
5133 case 0x0fa8: /* push gs */
5134 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5139 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5143 case 0x60: /* pusha */
5144 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5149 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 4)))
5153 case 0x58: /* pop */
5161 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5162 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode
& 0x7) | ir
.rex_b
);
5165 case 0x61: /* popa */
5166 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5171 for (regnum
= X86_RECORD_REAX_REGNUM
;
5172 regnum
<= X86_RECORD_REDI_REGNUM
;
5174 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum
);
5177 case 0x8f: /* pop */
5178 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5179 ir
.ot
= ir
.dflag
? OT_QUAD
: OT_WORD
;
5181 ir
.ot
= ir
.dflag
+ OT_WORD
;
5182 if (i386_record_modrm (&ir
))
5185 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5188 ir
.popl_esp_hack
= 1 << ir
.ot
;
5189 if (i386_record_lea_modrm (&ir
))
5192 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5195 case 0xc8: /* enter */
5196 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
5197 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5199 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5203 case 0xc9: /* leave */
5204 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5205 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
5208 case 0x07: /* pop es */
5209 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5214 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5215 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM
);
5216 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5219 case 0x17: /* pop ss */
5220 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5225 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5226 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM
);
5227 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5230 case 0x1f: /* pop ds */
5231 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5236 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5237 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM
);
5238 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5241 case 0x0fa1: /* pop fs */
5242 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5243 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM
);
5244 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5247 case 0x0fa9: /* pop gs */
5248 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5249 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM
);
5250 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5253 case 0x88: /* mov */
5257 if ((opcode
& 1) == 0)
5260 ir
.ot
= ir
.dflag
+ OT_WORD
;
5262 if (i386_record_modrm (&ir
))
5267 if (opcode
== 0xc6 || opcode
== 0xc7)
5268 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
5269 if (i386_record_lea_modrm (&ir
))
5274 if (opcode
== 0xc6 || opcode
== 0xc7)
5276 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5278 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5282 case 0x8a: /* mov */
5284 if ((opcode
& 1) == 0)
5287 ir
.ot
= ir
.dflag
+ OT_WORD
;
5288 if (i386_record_modrm (&ir
))
5291 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5293 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5296 case 0x8c: /* mov seg */
5297 if (i386_record_modrm (&ir
))
5302 opcode
= opcode
<< 8 | ir
.modrm
;
5307 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5311 if (i386_record_lea_modrm (&ir
))
5316 case 0x8e: /* mov seg */
5317 if (i386_record_modrm (&ir
))
5322 regnum
= X86_RECORD_ES_REGNUM
;
5325 regnum
= X86_RECORD_SS_REGNUM
;
5328 regnum
= X86_RECORD_DS_REGNUM
;
5331 regnum
= X86_RECORD_FS_REGNUM
;
5334 regnum
= X86_RECORD_GS_REGNUM
;
5338 opcode
= opcode
<< 8 | ir
.modrm
;
5342 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum
);
5343 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5346 case 0x0fb6: /* movzbS */
5347 case 0x0fb7: /* movzwS */
5348 case 0x0fbe: /* movsbS */
5349 case 0x0fbf: /* movswS */
5350 if (i386_record_modrm (&ir
))
5352 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
5355 case 0x8d: /* lea */
5356 if (i386_record_modrm (&ir
))
5361 opcode
= opcode
<< 8 | ir
.modrm
;
5366 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5368 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5371 case 0xa0: /* mov EAX */
5374 case 0xd7: /* xlat */
5375 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5378 case 0xa2: /* mov EAX */
5380 if (ir
.override
>= 0)
5382 if (record_full_memory_query
)
5386 target_terminal_ours ();
5388 Process record ignores the memory change of instruction at address %s\n\
5389 because it can't get the value of the segment register.\n\
5390 Do you want to stop the program?"),
5391 paddress (gdbarch
, ir
.orig_addr
));
5392 target_terminal_inferior ();
5399 if ((opcode
& 1) == 0)
5402 ir
.ot
= ir
.dflag
+ OT_WORD
;
5405 if (record_read_memory (gdbarch
, ir
.addr
, buf
, 8))
5408 addr
= extract_unsigned_integer (buf
, 8, byte_order
);
5412 if (record_read_memory (gdbarch
, ir
.addr
, buf
, 4))
5415 addr
= extract_unsigned_integer (buf
, 4, byte_order
);
5419 if (record_read_memory (gdbarch
, ir
.addr
, buf
, 2))
5422 addr
= extract_unsigned_integer (buf
, 2, byte_order
);
5424 if (record_full_arch_list_add_mem (addr
, 1 << ir
.ot
))
5429 case 0xb0: /* mov R, Ib */
5437 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((ir
.regmap
[X86_RECORD_R8_REGNUM
])
5438 ? ((opcode
& 0x7) | ir
.rex_b
)
5439 : ((opcode
& 0x7) & 0x3));
5442 case 0xb8: /* mov R, Iv */
5450 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode
& 0x7) | ir
.rex_b
);
5453 case 0x91: /* xchg R, EAX */
5460 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5461 I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode
& 0x7);
5464 case 0x86: /* xchg Ev, Gv */
5466 if ((opcode
& 1) == 0)
5469 ir
.ot
= ir
.dflag
+ OT_WORD
;
5470 if (i386_record_modrm (&ir
))
5475 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5477 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5481 if (i386_record_lea_modrm (&ir
))
5485 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5487 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5490 case 0xc4: /* les Gv */
5491 case 0xc5: /* lds Gv */
5492 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5498 case 0x0fb2: /* lss Gv */
5499 case 0x0fb4: /* lfs Gv */
5500 case 0x0fb5: /* lgs Gv */
5501 if (i386_record_modrm (&ir
))
5509 opcode
= opcode
<< 8 | ir
.modrm
;
5514 case 0xc4: /* les Gv */
5515 regnum
= X86_RECORD_ES_REGNUM
;
5517 case 0xc5: /* lds Gv */
5518 regnum
= X86_RECORD_DS_REGNUM
;
5520 case 0x0fb2: /* lss Gv */
5521 regnum
= X86_RECORD_SS_REGNUM
;
5523 case 0x0fb4: /* lfs Gv */
5524 regnum
= X86_RECORD_FS_REGNUM
;
5526 case 0x0fb5: /* lgs Gv */
5527 regnum
= X86_RECORD_GS_REGNUM
;
5530 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum
);
5531 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
5532 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5535 case 0xc0: /* shifts */
5541 if ((opcode
& 1) == 0)
5544 ir
.ot
= ir
.dflag
+ OT_WORD
;
5545 if (i386_record_modrm (&ir
))
5547 if (ir
.mod
!= 3 && (opcode
== 0xd2 || opcode
== 0xd3))
5549 if (i386_record_lea_modrm (&ir
))
5555 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5557 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5559 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5566 if (i386_record_modrm (&ir
))
5570 if (record_full_arch_list_add_reg (ir
.regcache
, ir
.rm
))
5575 if (i386_record_lea_modrm (&ir
))
5580 case 0xd8: /* Floats. */
5588 if (i386_record_modrm (&ir
))
5590 ir
.reg
|= ((opcode
& 7) << 3);
5596 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
5604 /* For fcom, ficom nothing to do. */
5610 /* For fcomp, ficomp pop FPU stack, store all. */
5611 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5638 /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul,
5639 fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension
5640 of code, always affects st(0) register. */
5641 if (i386_record_floats (gdbarch
, &ir
, I387_ST0_REGNUM (tdep
)))
5665 /* Handling fld, fild. */
5666 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5670 switch (ir
.reg
>> 4)
5673 if (record_full_arch_list_add_mem (addr64
, 4))
5677 if (record_full_arch_list_add_mem (addr64
, 8))
5683 if (record_full_arch_list_add_mem (addr64
, 2))
5689 switch (ir
.reg
>> 4)
5692 if (record_full_arch_list_add_mem (addr64
, 4))
5694 if (3 == (ir
.reg
& 7))
5696 /* For fstp m32fp. */
5697 if (i386_record_floats (gdbarch
, &ir
,
5698 I386_SAVE_FPU_REGS
))
5703 if (record_full_arch_list_add_mem (addr64
, 4))
5705 if ((3 == (ir
.reg
& 7))
5706 || (5 == (ir
.reg
& 7))
5707 || (7 == (ir
.reg
& 7)))
5709 /* For fstp insn. */
5710 if (i386_record_floats (gdbarch
, &ir
,
5711 I386_SAVE_FPU_REGS
))
5716 if (record_full_arch_list_add_mem (addr64
, 8))
5718 if (3 == (ir
.reg
& 7))
5720 /* For fstp m64fp. */
5721 if (i386_record_floats (gdbarch
, &ir
,
5722 I386_SAVE_FPU_REGS
))
5727 if ((3 <= (ir
.reg
& 7)) && (6 <= (ir
.reg
& 7)))
5729 /* For fistp, fbld, fild, fbstp. */
5730 if (i386_record_floats (gdbarch
, &ir
,
5731 I386_SAVE_FPU_REGS
))
5736 if (record_full_arch_list_add_mem (addr64
, 2))
5745 if (i386_record_floats (gdbarch
, &ir
,
5746 I386_SAVE_FPU_ENV_REG_STACK
))
5751 if (i386_record_floats (gdbarch
, &ir
, I387_FCTRL_REGNUM (tdep
)))
5756 if (i386_record_floats (gdbarch
, &ir
,
5757 I386_SAVE_FPU_ENV_REG_STACK
))
5763 if (record_full_arch_list_add_mem (addr64
, 28))
5768 if (record_full_arch_list_add_mem (addr64
, 14))
5774 if (record_full_arch_list_add_mem (addr64
, 2))
5776 /* Insn fstp, fbstp. */
5777 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5782 if (record_full_arch_list_add_mem (addr64
, 10))
5788 if (record_full_arch_list_add_mem (addr64
, 28))
5794 if (record_full_arch_list_add_mem (addr64
, 14))
5798 if (record_full_arch_list_add_mem (addr64
, 80))
5801 if (i386_record_floats (gdbarch
, &ir
,
5802 I386_SAVE_FPU_ENV_REG_STACK
))
5806 if (record_full_arch_list_add_mem (addr64
, 8))
5809 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5814 opcode
= opcode
<< 8 | ir
.modrm
;
5819 /* Opcode is an extension of modR/M byte. */
5825 if (i386_record_floats (gdbarch
, &ir
, I387_ST0_REGNUM (tdep
)))
5829 if (0x0c == (ir
.modrm
>> 4))
5831 if ((ir
.modrm
& 0x0f) <= 7)
5833 if (i386_record_floats (gdbarch
, &ir
,
5834 I386_SAVE_FPU_REGS
))
5839 if (i386_record_floats (gdbarch
, &ir
,
5840 I387_ST0_REGNUM (tdep
)))
5842 /* If only st(0) is changing, then we have already
5844 if ((ir
.modrm
& 0x0f) - 0x08)
5846 if (i386_record_floats (gdbarch
, &ir
,
5847 I387_ST0_REGNUM (tdep
) +
5848 ((ir
.modrm
& 0x0f) - 0x08)))
5866 if (i386_record_floats (gdbarch
, &ir
,
5867 I387_ST0_REGNUM (tdep
)))
5885 if (i386_record_floats (gdbarch
, &ir
,
5886 I386_SAVE_FPU_REGS
))
5890 if (i386_record_floats (gdbarch
, &ir
,
5891 I387_ST0_REGNUM (tdep
)))
5893 if (i386_record_floats (gdbarch
, &ir
,
5894 I387_ST0_REGNUM (tdep
) + 1))
5901 if (0xe9 == ir
.modrm
)
5903 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5906 else if ((0x0c == ir
.modrm
>> 4) || (0x0d == ir
.modrm
>> 4))
5908 if (i386_record_floats (gdbarch
, &ir
,
5909 I387_ST0_REGNUM (tdep
)))
5911 if (((ir
.modrm
& 0x0f) > 0) && ((ir
.modrm
& 0x0f) <= 7))
5913 if (i386_record_floats (gdbarch
, &ir
,
5914 I387_ST0_REGNUM (tdep
) +
5918 else if ((ir
.modrm
& 0x0f) - 0x08)
5920 if (i386_record_floats (gdbarch
, &ir
,
5921 I387_ST0_REGNUM (tdep
) +
5922 ((ir
.modrm
& 0x0f) - 0x08)))
5928 if (0xe3 == ir
.modrm
)
5930 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_ENV
))
5933 else if ((0x0c == ir
.modrm
>> 4) || (0x0d == ir
.modrm
>> 4))
5935 if (i386_record_floats (gdbarch
, &ir
,
5936 I387_ST0_REGNUM (tdep
)))
5938 if (((ir
.modrm
& 0x0f) > 0) && ((ir
.modrm
& 0x0f) <= 7))
5940 if (i386_record_floats (gdbarch
, &ir
,
5941 I387_ST0_REGNUM (tdep
) +
5945 else if ((ir
.modrm
& 0x0f) - 0x08)
5947 if (i386_record_floats (gdbarch
, &ir
,
5948 I387_ST0_REGNUM (tdep
) +
5949 ((ir
.modrm
& 0x0f) - 0x08)))
5955 if ((0x0c == ir
.modrm
>> 4)
5956 || (0x0d == ir
.modrm
>> 4)
5957 || (0x0f == ir
.modrm
>> 4))
5959 if ((ir
.modrm
& 0x0f) <= 7)
5961 if (i386_record_floats (gdbarch
, &ir
,
5962 I387_ST0_REGNUM (tdep
) +
5968 if (i386_record_floats (gdbarch
, &ir
,
5969 I387_ST0_REGNUM (tdep
) +
5970 ((ir
.modrm
& 0x0f) - 0x08)))
5976 if (0x0c == ir
.modrm
>> 4)
5978 if (i386_record_floats (gdbarch
, &ir
,
5979 I387_FTAG_REGNUM (tdep
)))
5982 else if ((0x0d == ir
.modrm
>> 4) || (0x0e == ir
.modrm
>> 4))
5984 if ((ir
.modrm
& 0x0f) <= 7)
5986 if (i386_record_floats (gdbarch
, &ir
,
5987 I387_ST0_REGNUM (tdep
) +
5993 if (i386_record_floats (gdbarch
, &ir
,
5994 I386_SAVE_FPU_REGS
))
6000 if ((0x0c == ir
.modrm
>> 4)
6001 || (0x0e == ir
.modrm
>> 4)
6002 || (0x0f == ir
.modrm
>> 4)
6003 || (0xd9 == ir
.modrm
))
6005 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
6010 if (0xe0 == ir
.modrm
)
6012 if (record_full_arch_list_add_reg (ir
.regcache
,
6016 else if ((0x0f == ir
.modrm
>> 4) || (0x0e == ir
.modrm
>> 4))
6018 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
6026 case 0xa4: /* movsS */
6028 case 0xaa: /* stosS */
6030 case 0x6c: /* insS */
6032 regcache_raw_read_unsigned (ir
.regcache
,
6033 ir
.regmap
[X86_RECORD_RECX_REGNUM
],
6039 if ((opcode
& 1) == 0)
6042 ir
.ot
= ir
.dflag
+ OT_WORD
;
6043 regcache_raw_read_unsigned (ir
.regcache
,
6044 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
6047 regcache_raw_read_unsigned (ir
.regcache
,
6048 ir
.regmap
[X86_RECORD_ES_REGNUM
],
6050 regcache_raw_read_unsigned (ir
.regcache
,
6051 ir
.regmap
[X86_RECORD_DS_REGNUM
],
6053 if (ir
.aflag
&& (es
!= ds
))
6055 /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */
6056 if (record_full_memory_query
)
6060 target_terminal_ours ();
6062 Process record ignores the memory change of instruction at address %s\n\
6063 because it can't get the value of the segment register.\n\
6064 Do you want to stop the program?"),
6065 paddress (gdbarch
, ir
.orig_addr
));
6066 target_terminal_inferior ();
6073 if (record_full_arch_list_add_mem (addr
, 1 << ir
.ot
))
6077 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
6078 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6079 if (opcode
== 0xa4 || opcode
== 0xa5)
6080 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
6081 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
6082 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6086 case 0xa6: /* cmpsS */
6088 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
6089 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
6090 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
6091 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6092 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6095 case 0xac: /* lodsS */
6097 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6098 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
6099 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
6100 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6101 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6104 case 0xae: /* scasS */
6106 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
6107 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
6108 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6109 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6112 case 0x6e: /* outsS */
6114 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
6115 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
6116 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6117 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6120 case 0xe4: /* port I/O */
6124 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6125 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6135 case 0xc2: /* ret im */
6136 case 0xc3: /* ret */
6137 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
6138 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6141 case 0xca: /* lret im */
6142 case 0xcb: /* lret */
6143 case 0xcf: /* iret */
6144 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
6145 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
6146 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6149 case 0xe8: /* call im */
6150 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
6152 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
6156 case 0x9a: /* lcall im */
6157 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6162 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
6163 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
6167 case 0xe9: /* jmp im */
6168 case 0xea: /* ljmp im */
6169 case 0xeb: /* jmp Jb */
6170 case 0x70: /* jcc Jb */
6186 case 0x0f80: /* jcc Jv */
6204 case 0x0f90: /* setcc Gv */
6220 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6222 if (i386_record_modrm (&ir
))
6225 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rex_b
? (ir
.rm
| ir
.rex_b
)
6229 if (i386_record_lea_modrm (&ir
))
6234 case 0x0f40: /* cmov Gv, Ev */
6250 if (i386_record_modrm (&ir
))
6253 if (ir
.dflag
== OT_BYTE
)
6255 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
6259 case 0x9c: /* pushf */
6260 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6261 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
6263 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
6267 case 0x9d: /* popf */
6268 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
6269 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6272 case 0x9e: /* sahf */
6273 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6279 case 0xf5: /* cmc */
6280 case 0xf8: /* clc */
6281 case 0xf9: /* stc */
6282 case 0xfc: /* cld */
6283 case 0xfd: /* std */
6284 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6287 case 0x9f: /* lahf */
6288 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6293 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6294 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6297 /* bit operations */
6298 case 0x0fba: /* bt/bts/btr/btc Gv, im */
6299 ir
.ot
= ir
.dflag
+ OT_WORD
;
6300 if (i386_record_modrm (&ir
))
6305 opcode
= opcode
<< 8 | ir
.modrm
;
6311 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6314 if (i386_record_lea_modrm (&ir
))
6318 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6321 case 0x0fa3: /* bt Gv, Ev */
6322 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6325 case 0x0fab: /* bts */
6326 case 0x0fb3: /* btr */
6327 case 0x0fbb: /* btc */
6328 ir
.ot
= ir
.dflag
+ OT_WORD
;
6329 if (i386_record_modrm (&ir
))
6332 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6336 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
6338 regcache_raw_read_unsigned (ir
.regcache
,
6339 ir
.regmap
[ir
.reg
| rex_r
],
6344 addr64
+= ((int16_t) addr
>> 4) << 4;
6347 addr64
+= ((int32_t) addr
>> 5) << 5;
6350 addr64
+= ((int64_t) addr
>> 6) << 6;
6353 if (record_full_arch_list_add_mem (addr64
, 1 << ir
.ot
))
6355 if (i386_record_lea_modrm (&ir
))
6358 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6361 case 0x0fbc: /* bsf */
6362 case 0x0fbd: /* bsr */
6363 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
6364 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6368 case 0x27: /* daa */
6369 case 0x2f: /* das */
6370 case 0x37: /* aaa */
6371 case 0x3f: /* aas */
6372 case 0xd4: /* aam */
6373 case 0xd5: /* aad */
6374 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6379 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6380 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6384 case 0x90: /* nop */
6385 if (prefixes
& PREFIX_LOCK
)
6392 case 0x9b: /* fwait */
6393 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
6395 opcode
= (uint32_t) opcode8
;
6401 case 0xcc: /* int3 */
6402 printf_unfiltered (_("Process record does not support instruction "
6409 case 0xcd: /* int */
6413 if (record_read_memory (gdbarch
, ir
.addr
, &interrupt
, 1))
6416 if (interrupt
!= 0x80
6417 || tdep
->i386_intx80_record
== NULL
)
6419 printf_unfiltered (_("Process record does not support "
6420 "instruction int 0x%02x.\n"),
6425 ret
= tdep
->i386_intx80_record (ir
.regcache
);
6432 case 0xce: /* into */
6433 printf_unfiltered (_("Process record does not support "
6434 "instruction into.\n"));
6439 case 0xfa: /* cli */
6440 case 0xfb: /* sti */
6443 case 0x62: /* bound */
6444 printf_unfiltered (_("Process record does not support "
6445 "instruction bound.\n"));
6450 case 0x0fc8: /* bswap reg */
6458 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode
& 7) | ir
.rex_b
);
6461 case 0xd6: /* salc */
6462 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6467 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6468 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6471 case 0xe0: /* loopnz */
6472 case 0xe1: /* loopz */
6473 case 0xe2: /* loop */
6474 case 0xe3: /* jecxz */
6475 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6476 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6479 case 0x0f30: /* wrmsr */
6480 printf_unfiltered (_("Process record does not support "
6481 "instruction wrmsr.\n"));
6486 case 0x0f32: /* rdmsr */
6487 printf_unfiltered (_("Process record does not support "
6488 "instruction rdmsr.\n"));
6493 case 0x0f31: /* rdtsc */
6494 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6495 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
6498 case 0x0f34: /* sysenter */
6501 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6506 if (tdep
->i386_sysenter_record
== NULL
)
6508 printf_unfiltered (_("Process record does not support "
6509 "instruction sysenter.\n"));
6513 ret
= tdep
->i386_sysenter_record (ir
.regcache
);
6519 case 0x0f35: /* sysexit */
6520 printf_unfiltered (_("Process record does not support "
6521 "instruction sysexit.\n"));
6526 case 0x0f05: /* syscall */
6529 if (tdep
->i386_syscall_record
== NULL
)
6531 printf_unfiltered (_("Process record does not support "
6532 "instruction syscall.\n"));
6536 ret
= tdep
->i386_syscall_record (ir
.regcache
);
6542 case 0x0f07: /* sysret */
6543 printf_unfiltered (_("Process record does not support "
6544 "instruction sysret.\n"));
6549 case 0x0fa2: /* cpuid */
6550 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6551 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6552 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
6553 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM
);
6556 case 0xf4: /* hlt */
6557 printf_unfiltered (_("Process record does not support "
6558 "instruction hlt.\n"));
6564 if (i386_record_modrm (&ir
))
6571 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6575 if (i386_record_lea_modrm (&ir
))
6584 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6588 opcode
= opcode
<< 8 | ir
.modrm
;
6595 if (i386_record_modrm (&ir
))
6606 opcode
= opcode
<< 8 | ir
.modrm
;
6609 if (ir
.override
>= 0)
6611 if (record_full_memory_query
)
6615 target_terminal_ours ();
6617 Process record ignores the memory change of instruction at address %s\n\
6618 because it can't get the value of the segment register.\n\
6619 Do you want to stop the program?"),
6620 paddress (gdbarch
, ir
.orig_addr
));
6621 target_terminal_inferior ();
6628 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
6630 if (record_full_arch_list_add_mem (addr64
, 2))
6633 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6635 if (record_full_arch_list_add_mem (addr64
, 8))
6640 if (record_full_arch_list_add_mem (addr64
, 4))
6651 case 0: /* monitor */
6654 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6658 opcode
= opcode
<< 8 | ir
.modrm
;
6666 if (ir
.override
>= 0)
6668 if (record_full_memory_query
)
6672 target_terminal_ours ();
6674 Process record ignores the memory change of instruction at address %s\n\
6675 because it can't get the value of the segment register.\n\
6676 Do you want to stop the program?"),
6677 paddress (gdbarch
, ir
.orig_addr
));
6678 target_terminal_inferior ();
6687 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
6689 if (record_full_arch_list_add_mem (addr64
, 2))
6692 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6694 if (record_full_arch_list_add_mem (addr64
, 8))
6699 if (record_full_arch_list_add_mem (addr64
, 4))
6711 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6712 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
6716 else if (ir
.rm
== 1)
6723 opcode
= opcode
<< 8 | ir
.modrm
;
6730 if (record_full_arch_list_add_reg (ir
.regcache
, ir
.rm
| ir
.rex_b
))
6736 if (i386_record_lea_modrm (&ir
))
6739 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6742 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6744 case 7: /* invlpg */
6747 if (ir
.rm
== 0 && ir
.regmap
[X86_RECORD_R8_REGNUM
])
6748 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM
);
6752 opcode
= opcode
<< 8 | ir
.modrm
;
6757 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6761 opcode
= opcode
<< 8 | ir
.modrm
;
6767 case 0x0f08: /* invd */
6768 case 0x0f09: /* wbinvd */
6771 case 0x63: /* arpl */
6772 if (i386_record_modrm (&ir
))
6774 if (ir
.mod
== 3 || ir
.regmap
[X86_RECORD_R8_REGNUM
])
6776 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.regmap
[X86_RECORD_R8_REGNUM
]
6777 ? (ir
.reg
| rex_r
) : ir
.rm
);
6781 ir
.ot
= ir
.dflag
? OT_LONG
: OT_WORD
;
6782 if (i386_record_lea_modrm (&ir
))
6785 if (!ir
.regmap
[X86_RECORD_R8_REGNUM
])
6786 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6789 case 0x0f02: /* lar */
6790 case 0x0f03: /* lsl */
6791 if (i386_record_modrm (&ir
))
6793 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
6794 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6798 if (i386_record_modrm (&ir
))
6800 if (ir
.mod
== 3 && ir
.reg
== 3)
6803 opcode
= opcode
<< 8 | ir
.modrm
;
6815 /* nop (multi byte) */
6818 case 0x0f20: /* mov reg, crN */
6819 case 0x0f22: /* mov crN, reg */
6820 if (i386_record_modrm (&ir
))
6822 if ((ir
.modrm
& 0xc0) != 0xc0)
6825 opcode
= opcode
<< 8 | ir
.modrm
;
6836 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6838 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6842 opcode
= opcode
<< 8 | ir
.modrm
;
6848 case 0x0f21: /* mov reg, drN */
6849 case 0x0f23: /* mov drN, reg */
6850 if (i386_record_modrm (&ir
))
6852 if ((ir
.modrm
& 0xc0) != 0xc0 || ir
.reg
== 4
6853 || ir
.reg
== 5 || ir
.reg
>= 8)
6856 opcode
= opcode
<< 8 | ir
.modrm
;
6860 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6862 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6865 case 0x0f06: /* clts */
6866 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6869 /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */
6871 case 0x0f0d: /* 3DNow! prefetch */
6874 case 0x0f0e: /* 3DNow! femms */
6875 case 0x0f77: /* emms */
6876 if (i386_fpc_regnum_p (gdbarch
, I387_FTAG_REGNUM(tdep
)))
6878 record_full_arch_list_add_reg (ir
.regcache
, I387_FTAG_REGNUM(tdep
));
6881 case 0x0f0f: /* 3DNow! data */
6882 if (i386_record_modrm (&ir
))
6884 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
6889 case 0x0c: /* 3DNow! pi2fw */
6890 case 0x0d: /* 3DNow! pi2fd */
6891 case 0x1c: /* 3DNow! pf2iw */
6892 case 0x1d: /* 3DNow! pf2id */
6893 case 0x8a: /* 3DNow! pfnacc */
6894 case 0x8e: /* 3DNow! pfpnacc */
6895 case 0x90: /* 3DNow! pfcmpge */
6896 case 0x94: /* 3DNow! pfmin */
6897 case 0x96: /* 3DNow! pfrcp */
6898 case 0x97: /* 3DNow! pfrsqrt */
6899 case 0x9a: /* 3DNow! pfsub */
6900 case 0x9e: /* 3DNow! pfadd */
6901 case 0xa0: /* 3DNow! pfcmpgt */
6902 case 0xa4: /* 3DNow! pfmax */
6903 case 0xa6: /* 3DNow! pfrcpit1 */
6904 case 0xa7: /* 3DNow! pfrsqit1 */
6905 case 0xaa: /* 3DNow! pfsubr */
6906 case 0xae: /* 3DNow! pfacc */
6907 case 0xb0: /* 3DNow! pfcmpeq */
6908 case 0xb4: /* 3DNow! pfmul */
6909 case 0xb6: /* 3DNow! pfrcpit2 */
6910 case 0xb7: /* 3DNow! pmulhrw */
6911 case 0xbb: /* 3DNow! pswapd */
6912 case 0xbf: /* 3DNow! pavgusb */
6913 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.reg
))
6914 goto no_support_3dnow_data
;
6915 record_full_arch_list_add_reg (ir
.regcache
, ir
.reg
);
6919 no_support_3dnow_data
:
6920 opcode
= (opcode
<< 8) | opcode8
;
6926 case 0x0faa: /* rsm */
6927 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6928 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6929 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6930 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
6931 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM
);
6932 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
6933 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
6934 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
6935 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
6939 if (i386_record_modrm (&ir
))
6943 case 0: /* fxsave */
6947 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6948 if (i386_record_lea_modrm_addr (&ir
, &tmpu64
))
6950 if (record_full_arch_list_add_mem (tmpu64
, 512))
6955 case 1: /* fxrstor */
6959 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6961 for (i
= I387_MM0_REGNUM (tdep
);
6962 i386_mmx_regnum_p (gdbarch
, i
); i
++)
6963 record_full_arch_list_add_reg (ir
.regcache
, i
);
6965 for (i
= I387_XMM0_REGNUM (tdep
);
6966 i386_xmm_regnum_p (gdbarch
, i
); i
++)
6967 record_full_arch_list_add_reg (ir
.regcache
, i
);
6969 if (i386_mxcsr_regnum_p (gdbarch
, I387_MXCSR_REGNUM(tdep
)))
6970 record_full_arch_list_add_reg (ir
.regcache
,
6971 I387_MXCSR_REGNUM(tdep
));
6973 for (i
= I387_ST0_REGNUM (tdep
);
6974 i386_fp_regnum_p (gdbarch
, i
); i
++)
6975 record_full_arch_list_add_reg (ir
.regcache
, i
);
6977 for (i
= I387_FCTRL_REGNUM (tdep
);
6978 i386_fpc_regnum_p (gdbarch
, i
); i
++)
6979 record_full_arch_list_add_reg (ir
.regcache
, i
);
6983 case 2: /* ldmxcsr */
6984 if (!i386_mxcsr_regnum_p (gdbarch
, I387_MXCSR_REGNUM(tdep
)))
6986 record_full_arch_list_add_reg (ir
.regcache
, I387_MXCSR_REGNUM(tdep
));
6989 case 3: /* stmxcsr */
6991 if (i386_record_lea_modrm (&ir
))
6995 case 5: /* lfence */
6996 case 6: /* mfence */
6997 case 7: /* sfence clflush */
7001 opcode
= (opcode
<< 8) | ir
.modrm
;
7007 case 0x0fc3: /* movnti */
7008 ir
.ot
= (ir
.dflag
== 2) ? OT_QUAD
: OT_LONG
;
7009 if (i386_record_modrm (&ir
))
7014 if (i386_record_lea_modrm (&ir
))
7018 /* Add prefix to opcode. */
7133 /* Mask out PREFIX_ADDR. */
7134 switch ((prefixes
& ~PREFIX_ADDR
))
7146 reswitch_prefix_add
:
7154 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
7157 opcode
= (uint32_t) opcode8
| opcode
<< 8;
7158 goto reswitch_prefix_add
;
7161 case 0x0f10: /* movups */
7162 case 0x660f10: /* movupd */
7163 case 0xf30f10: /* movss */
7164 case 0xf20f10: /* movsd */
7165 case 0x0f12: /* movlps */
7166 case 0x660f12: /* movlpd */
7167 case 0xf30f12: /* movsldup */
7168 case 0xf20f12: /* movddup */
7169 case 0x0f14: /* unpcklps */
7170 case 0x660f14: /* unpcklpd */
7171 case 0x0f15: /* unpckhps */
7172 case 0x660f15: /* unpckhpd */
7173 case 0x0f16: /* movhps */
7174 case 0x660f16: /* movhpd */
7175 case 0xf30f16: /* movshdup */
7176 case 0x0f28: /* movaps */
7177 case 0x660f28: /* movapd */
7178 case 0x0f2a: /* cvtpi2ps */
7179 case 0x660f2a: /* cvtpi2pd */
7180 case 0xf30f2a: /* cvtsi2ss */
7181 case 0xf20f2a: /* cvtsi2sd */
7182 case 0x0f2c: /* cvttps2pi */
7183 case 0x660f2c: /* cvttpd2pi */
7184 case 0x0f2d: /* cvtps2pi */
7185 case 0x660f2d: /* cvtpd2pi */
7186 case 0x660f3800: /* pshufb */
7187 case 0x660f3801: /* phaddw */
7188 case 0x660f3802: /* phaddd */
7189 case 0x660f3803: /* phaddsw */
7190 case 0x660f3804: /* pmaddubsw */
7191 case 0x660f3805: /* phsubw */
7192 case 0x660f3806: /* phsubd */
7193 case 0x660f3807: /* phsubsw */
7194 case 0x660f3808: /* psignb */
7195 case 0x660f3809: /* psignw */
7196 case 0x660f380a: /* psignd */
7197 case 0x660f380b: /* pmulhrsw */
7198 case 0x660f3810: /* pblendvb */
7199 case 0x660f3814: /* blendvps */
7200 case 0x660f3815: /* blendvpd */
7201 case 0x660f381c: /* pabsb */
7202 case 0x660f381d: /* pabsw */
7203 case 0x660f381e: /* pabsd */
7204 case 0x660f3820: /* pmovsxbw */
7205 case 0x660f3821: /* pmovsxbd */
7206 case 0x660f3822: /* pmovsxbq */
7207 case 0x660f3823: /* pmovsxwd */
7208 case 0x660f3824: /* pmovsxwq */
7209 case 0x660f3825: /* pmovsxdq */
7210 case 0x660f3828: /* pmuldq */
7211 case 0x660f3829: /* pcmpeqq */
7212 case 0x660f382a: /* movntdqa */
7213 case 0x660f3a08: /* roundps */
7214 case 0x660f3a09: /* roundpd */
7215 case 0x660f3a0a: /* roundss */
7216 case 0x660f3a0b: /* roundsd */
7217 case 0x660f3a0c: /* blendps */
7218 case 0x660f3a0d: /* blendpd */
7219 case 0x660f3a0e: /* pblendw */
7220 case 0x660f3a0f: /* palignr */
7221 case 0x660f3a20: /* pinsrb */
7222 case 0x660f3a21: /* insertps */
7223 case 0x660f3a22: /* pinsrd pinsrq */
7224 case 0x660f3a40: /* dpps */
7225 case 0x660f3a41: /* dppd */
7226 case 0x660f3a42: /* mpsadbw */
7227 case 0x660f3a60: /* pcmpestrm */
7228 case 0x660f3a61: /* pcmpestri */
7229 case 0x660f3a62: /* pcmpistrm */
7230 case 0x660f3a63: /* pcmpistri */
7231 case 0x0f51: /* sqrtps */
7232 case 0x660f51: /* sqrtpd */
7233 case 0xf20f51: /* sqrtsd */
7234 case 0xf30f51: /* sqrtss */
7235 case 0x0f52: /* rsqrtps */
7236 case 0xf30f52: /* rsqrtss */
7237 case 0x0f53: /* rcpps */
7238 case 0xf30f53: /* rcpss */
7239 case 0x0f54: /* andps */
7240 case 0x660f54: /* andpd */
7241 case 0x0f55: /* andnps */
7242 case 0x660f55: /* andnpd */
7243 case 0x0f56: /* orps */
7244 case 0x660f56: /* orpd */
7245 case 0x0f57: /* xorps */
7246 case 0x660f57: /* xorpd */
7247 case 0x0f58: /* addps */
7248 case 0x660f58: /* addpd */
7249 case 0xf20f58: /* addsd */
7250 case 0xf30f58: /* addss */
7251 case 0x0f59: /* mulps */
7252 case 0x660f59: /* mulpd */
7253 case 0xf20f59: /* mulsd */
7254 case 0xf30f59: /* mulss */
7255 case 0x0f5a: /* cvtps2pd */
7256 case 0x660f5a: /* cvtpd2ps */
7257 case 0xf20f5a: /* cvtsd2ss */
7258 case 0xf30f5a: /* cvtss2sd */
7259 case 0x0f5b: /* cvtdq2ps */
7260 case 0x660f5b: /* cvtps2dq */
7261 case 0xf30f5b: /* cvttps2dq */
7262 case 0x0f5c: /* subps */
7263 case 0x660f5c: /* subpd */
7264 case 0xf20f5c: /* subsd */
7265 case 0xf30f5c: /* subss */
7266 case 0x0f5d: /* minps */
7267 case 0x660f5d: /* minpd */
7268 case 0xf20f5d: /* minsd */
7269 case 0xf30f5d: /* minss */
7270 case 0x0f5e: /* divps */
7271 case 0x660f5e: /* divpd */
7272 case 0xf20f5e: /* divsd */
7273 case 0xf30f5e: /* divss */
7274 case 0x0f5f: /* maxps */
7275 case 0x660f5f: /* maxpd */
7276 case 0xf20f5f: /* maxsd */
7277 case 0xf30f5f: /* maxss */
7278 case 0x660f60: /* punpcklbw */
7279 case 0x660f61: /* punpcklwd */
7280 case 0x660f62: /* punpckldq */
7281 case 0x660f63: /* packsswb */
7282 case 0x660f64: /* pcmpgtb */
7283 case 0x660f65: /* pcmpgtw */
7284 case 0x660f66: /* pcmpgtd */
7285 case 0x660f67: /* packuswb */
7286 case 0x660f68: /* punpckhbw */
7287 case 0x660f69: /* punpckhwd */
7288 case 0x660f6a: /* punpckhdq */
7289 case 0x660f6b: /* packssdw */
7290 case 0x660f6c: /* punpcklqdq */
7291 case 0x660f6d: /* punpckhqdq */
7292 case 0x660f6e: /* movd */
7293 case 0x660f6f: /* movdqa */
7294 case 0xf30f6f: /* movdqu */
7295 case 0x660f70: /* pshufd */
7296 case 0xf20f70: /* pshuflw */
7297 case 0xf30f70: /* pshufhw */
7298 case 0x660f74: /* pcmpeqb */
7299 case 0x660f75: /* pcmpeqw */
7300 case 0x660f76: /* pcmpeqd */
7301 case 0x660f7c: /* haddpd */
7302 case 0xf20f7c: /* haddps */
7303 case 0x660f7d: /* hsubpd */
7304 case 0xf20f7d: /* hsubps */
7305 case 0xf30f7e: /* movq */
7306 case 0x0fc2: /* cmpps */
7307 case 0x660fc2: /* cmppd */
7308 case 0xf20fc2: /* cmpsd */
7309 case 0xf30fc2: /* cmpss */
7310 case 0x660fc4: /* pinsrw */
7311 case 0x0fc6: /* shufps */
7312 case 0x660fc6: /* shufpd */
7313 case 0x660fd0: /* addsubpd */
7314 case 0xf20fd0: /* addsubps */
7315 case 0x660fd1: /* psrlw */
7316 case 0x660fd2: /* psrld */
7317 case 0x660fd3: /* psrlq */
7318 case 0x660fd4: /* paddq */
7319 case 0x660fd5: /* pmullw */
7320 case 0xf30fd6: /* movq2dq */
7321 case 0x660fd8: /* psubusb */
7322 case 0x660fd9: /* psubusw */
7323 case 0x660fda: /* pminub */
7324 case 0x660fdb: /* pand */
7325 case 0x660fdc: /* paddusb */
7326 case 0x660fdd: /* paddusw */
7327 case 0x660fde: /* pmaxub */
7328 case 0x660fdf: /* pandn */
7329 case 0x660fe0: /* pavgb */
7330 case 0x660fe1: /* psraw */
7331 case 0x660fe2: /* psrad */
7332 case 0x660fe3: /* pavgw */
7333 case 0x660fe4: /* pmulhuw */
7334 case 0x660fe5: /* pmulhw */
7335 case 0x660fe6: /* cvttpd2dq */
7336 case 0xf20fe6: /* cvtpd2dq */
7337 case 0xf30fe6: /* cvtdq2pd */
7338 case 0x660fe8: /* psubsb */
7339 case 0x660fe9: /* psubsw */
7340 case 0x660fea: /* pminsw */
7341 case 0x660feb: /* por */
7342 case 0x660fec: /* paddsb */
7343 case 0x660fed: /* paddsw */
7344 case 0x660fee: /* pmaxsw */
7345 case 0x660fef: /* pxor */
7346 case 0xf20ff0: /* lddqu */
7347 case 0x660ff1: /* psllw */
7348 case 0x660ff2: /* pslld */
7349 case 0x660ff3: /* psllq */
7350 case 0x660ff4: /* pmuludq */
7351 case 0x660ff5: /* pmaddwd */
7352 case 0x660ff6: /* psadbw */
7353 case 0x660ff8: /* psubb */
7354 case 0x660ff9: /* psubw */
7355 case 0x660ffa: /* psubd */
7356 case 0x660ffb: /* psubq */
7357 case 0x660ffc: /* paddb */
7358 case 0x660ffd: /* paddw */
7359 case 0x660ffe: /* paddd */
7360 if (i386_record_modrm (&ir
))
7363 if (!i386_xmm_regnum_p (gdbarch
, I387_XMM0_REGNUM (tdep
) + ir
.reg
))
7365 record_full_arch_list_add_reg (ir
.regcache
,
7366 I387_XMM0_REGNUM (tdep
) + ir
.reg
);
7367 if ((opcode
& 0xfffffffc) == 0x660f3a60)
7368 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7371 case 0x0f11: /* movups */
7372 case 0x660f11: /* movupd */
7373 case 0xf30f11: /* movss */
7374 case 0xf20f11: /* movsd */
7375 case 0x0f13: /* movlps */
7376 case 0x660f13: /* movlpd */
7377 case 0x0f17: /* movhps */
7378 case 0x660f17: /* movhpd */
7379 case 0x0f29: /* movaps */
7380 case 0x660f29: /* movapd */
7381 case 0x660f3a14: /* pextrb */
7382 case 0x660f3a15: /* pextrw */
7383 case 0x660f3a16: /* pextrd pextrq */
7384 case 0x660f3a17: /* extractps */
7385 case 0x660f7f: /* movdqa */
7386 case 0xf30f7f: /* movdqu */
7387 if (i386_record_modrm (&ir
))
7391 if (opcode
== 0x0f13 || opcode
== 0x660f13
7392 || opcode
== 0x0f17 || opcode
== 0x660f17)
7395 if (!i386_xmm_regnum_p (gdbarch
,
7396 I387_XMM0_REGNUM (tdep
) + ir
.rm
))
7398 record_full_arch_list_add_reg (ir
.regcache
,
7399 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
7421 if (i386_record_lea_modrm (&ir
))
7426 case 0x0f2b: /* movntps */
7427 case 0x660f2b: /* movntpd */
7428 case 0x0fe7: /* movntq */
7429 case 0x660fe7: /* movntdq */
7432 if (opcode
== 0x0fe7)
7436 if (i386_record_lea_modrm (&ir
))
7440 case 0xf30f2c: /* cvttss2si */
7441 case 0xf20f2c: /* cvttsd2si */
7442 case 0xf30f2d: /* cvtss2si */
7443 case 0xf20f2d: /* cvtsd2si */
7444 case 0xf20f38f0: /* crc32 */
7445 case 0xf20f38f1: /* crc32 */
7446 case 0x0f50: /* movmskps */
7447 case 0x660f50: /* movmskpd */
7448 case 0x0fc5: /* pextrw */
7449 case 0x660fc5: /* pextrw */
7450 case 0x0fd7: /* pmovmskb */
7451 case 0x660fd7: /* pmovmskb */
7452 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
7455 case 0x0f3800: /* pshufb */
7456 case 0x0f3801: /* phaddw */
7457 case 0x0f3802: /* phaddd */
7458 case 0x0f3803: /* phaddsw */
7459 case 0x0f3804: /* pmaddubsw */
7460 case 0x0f3805: /* phsubw */
7461 case 0x0f3806: /* phsubd */
7462 case 0x0f3807: /* phsubsw */
7463 case 0x0f3808: /* psignb */
7464 case 0x0f3809: /* psignw */
7465 case 0x0f380a: /* psignd */
7466 case 0x0f380b: /* pmulhrsw */
7467 case 0x0f381c: /* pabsb */
7468 case 0x0f381d: /* pabsw */
7469 case 0x0f381e: /* pabsd */
7470 case 0x0f382b: /* packusdw */
7471 case 0x0f3830: /* pmovzxbw */
7472 case 0x0f3831: /* pmovzxbd */
7473 case 0x0f3832: /* pmovzxbq */
7474 case 0x0f3833: /* pmovzxwd */
7475 case 0x0f3834: /* pmovzxwq */
7476 case 0x0f3835: /* pmovzxdq */
7477 case 0x0f3837: /* pcmpgtq */
7478 case 0x0f3838: /* pminsb */
7479 case 0x0f3839: /* pminsd */
7480 case 0x0f383a: /* pminuw */
7481 case 0x0f383b: /* pminud */
7482 case 0x0f383c: /* pmaxsb */
7483 case 0x0f383d: /* pmaxsd */
7484 case 0x0f383e: /* pmaxuw */
7485 case 0x0f383f: /* pmaxud */
7486 case 0x0f3840: /* pmulld */
7487 case 0x0f3841: /* phminposuw */
7488 case 0x0f3a0f: /* palignr */
7489 case 0x0f60: /* punpcklbw */
7490 case 0x0f61: /* punpcklwd */
7491 case 0x0f62: /* punpckldq */
7492 case 0x0f63: /* packsswb */
7493 case 0x0f64: /* pcmpgtb */
7494 case 0x0f65: /* pcmpgtw */
7495 case 0x0f66: /* pcmpgtd */
7496 case 0x0f67: /* packuswb */
7497 case 0x0f68: /* punpckhbw */
7498 case 0x0f69: /* punpckhwd */
7499 case 0x0f6a: /* punpckhdq */
7500 case 0x0f6b: /* packssdw */
7501 case 0x0f6e: /* movd */
7502 case 0x0f6f: /* movq */
7503 case 0x0f70: /* pshufw */
7504 case 0x0f74: /* pcmpeqb */
7505 case 0x0f75: /* pcmpeqw */
7506 case 0x0f76: /* pcmpeqd */
7507 case 0x0fc4: /* pinsrw */
7508 case 0x0fd1: /* psrlw */
7509 case 0x0fd2: /* psrld */
7510 case 0x0fd3: /* psrlq */
7511 case 0x0fd4: /* paddq */
7512 case 0x0fd5: /* pmullw */
7513 case 0xf20fd6: /* movdq2q */
7514 case 0x0fd8: /* psubusb */
7515 case 0x0fd9: /* psubusw */
7516 case 0x0fda: /* pminub */
7517 case 0x0fdb: /* pand */
7518 case 0x0fdc: /* paddusb */
7519 case 0x0fdd: /* paddusw */
7520 case 0x0fde: /* pmaxub */
7521 case 0x0fdf: /* pandn */
7522 case 0x0fe0: /* pavgb */
7523 case 0x0fe1: /* psraw */
7524 case 0x0fe2: /* psrad */
7525 case 0x0fe3: /* pavgw */
7526 case 0x0fe4: /* pmulhuw */
7527 case 0x0fe5: /* pmulhw */
7528 case 0x0fe8: /* psubsb */
7529 case 0x0fe9: /* psubsw */
7530 case 0x0fea: /* pminsw */
7531 case 0x0feb: /* por */
7532 case 0x0fec: /* paddsb */
7533 case 0x0fed: /* paddsw */
7534 case 0x0fee: /* pmaxsw */
7535 case 0x0fef: /* pxor */
7536 case 0x0ff1: /* psllw */
7537 case 0x0ff2: /* pslld */
7538 case 0x0ff3: /* psllq */
7539 case 0x0ff4: /* pmuludq */
7540 case 0x0ff5: /* pmaddwd */
7541 case 0x0ff6: /* psadbw */
7542 case 0x0ff8: /* psubb */
7543 case 0x0ff9: /* psubw */
7544 case 0x0ffa: /* psubd */
7545 case 0x0ffb: /* psubq */
7546 case 0x0ffc: /* paddb */
7547 case 0x0ffd: /* paddw */
7548 case 0x0ffe: /* paddd */
7549 if (i386_record_modrm (&ir
))
7551 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.reg
))
7553 record_full_arch_list_add_reg (ir
.regcache
,
7554 I387_MM0_REGNUM (tdep
) + ir
.reg
);
7557 case 0x0f71: /* psllw */
7558 case 0x0f72: /* pslld */
7559 case 0x0f73: /* psllq */
7560 if (i386_record_modrm (&ir
))
7562 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.rm
))
7564 record_full_arch_list_add_reg (ir
.regcache
,
7565 I387_MM0_REGNUM (tdep
) + ir
.rm
);
7568 case 0x660f71: /* psllw */
7569 case 0x660f72: /* pslld */
7570 case 0x660f73: /* psllq */
7571 if (i386_record_modrm (&ir
))
7574 if (!i386_xmm_regnum_p (gdbarch
, I387_XMM0_REGNUM (tdep
) + ir
.rm
))
7576 record_full_arch_list_add_reg (ir
.regcache
,
7577 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
7580 case 0x0f7e: /* movd */
7581 case 0x660f7e: /* movd */
7582 if (i386_record_modrm (&ir
))
7585 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
7592 if (i386_record_lea_modrm (&ir
))
7597 case 0x0f7f: /* movq */
7598 if (i386_record_modrm (&ir
))
7602 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.rm
))
7604 record_full_arch_list_add_reg (ir
.regcache
,
7605 I387_MM0_REGNUM (tdep
) + ir
.rm
);
7610 if (i386_record_lea_modrm (&ir
))
7615 case 0xf30fb8: /* popcnt */
7616 if (i386_record_modrm (&ir
))
7618 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
7619 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7622 case 0x660fd6: /* movq */
7623 if (i386_record_modrm (&ir
))
7628 if (!i386_xmm_regnum_p (gdbarch
,
7629 I387_XMM0_REGNUM (tdep
) + ir
.rm
))
7631 record_full_arch_list_add_reg (ir
.regcache
,
7632 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
7637 if (i386_record_lea_modrm (&ir
))
7642 case 0x660f3817: /* ptest */
7643 case 0x0f2e: /* ucomiss */
7644 case 0x660f2e: /* ucomisd */
7645 case 0x0f2f: /* comiss */
7646 case 0x660f2f: /* comisd */
7647 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7650 case 0x0ff7: /* maskmovq */
7651 regcache_raw_read_unsigned (ir
.regcache
,
7652 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
7654 if (record_full_arch_list_add_mem (addr
, 64))
7658 case 0x660ff7: /* maskmovdqu */
7659 regcache_raw_read_unsigned (ir
.regcache
,
7660 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
7662 if (record_full_arch_list_add_mem (addr
, 128))
7677 /* In the future, maybe still need to deal with need_dasm. */
7678 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM
);
7679 if (record_full_arch_list_add_end ())
7685 printf_unfiltered (_("Process record does not support instruction 0x%02x "
7686 "at address %s.\n"),
7687 (unsigned int) (opcode
),
7688 paddress (gdbarch
, ir
.orig_addr
));
7692 static const int i386_record_regmap
[] =
7694 I386_EAX_REGNUM
, I386_ECX_REGNUM
, I386_EDX_REGNUM
, I386_EBX_REGNUM
,
7695 I386_ESP_REGNUM
, I386_EBP_REGNUM
, I386_ESI_REGNUM
, I386_EDI_REGNUM
,
7696 0, 0, 0, 0, 0, 0, 0, 0,
7697 I386_EIP_REGNUM
, I386_EFLAGS_REGNUM
, I386_CS_REGNUM
, I386_SS_REGNUM
,
7698 I386_DS_REGNUM
, I386_ES_REGNUM
, I386_FS_REGNUM
, I386_GS_REGNUM
7701 /* Check that the given address appears suitable for a fast
7702 tracepoint, which on x86-64 means that we need an instruction of at
7703 least 5 bytes, so that we can overwrite it with a 4-byte-offset
7704 jump and not have to worry about program jumps to an address in the
7705 middle of the tracepoint jump. On x86, it may be possible to use
7706 4-byte jumps with a 2-byte offset to a trampoline located in the
7707 bottom 64 KiB of memory. Returns 1 if OK, and writes a size
7708 of instruction to replace, and 0 if not, plus an explanatory
7712 i386_fast_tracepoint_valid_at (struct gdbarch
*gdbarch
,
7713 CORE_ADDR addr
, int *isize
, char **msg
)
7716 static struct ui_file
*gdb_null
= NULL
;
7718 /* Ask the target for the minimum instruction length supported. */
7719 jumplen
= target_get_min_fast_tracepoint_insn_len ();
7723 /* If the target does not support the get_min_fast_tracepoint_insn_len
7724 operation, assume that fast tracepoints will always be implemented
7725 using 4-byte relative jumps on both x86 and x86-64. */
7728 else if (jumplen
== 0)
7730 /* If the target does support get_min_fast_tracepoint_insn_len but
7731 returns zero, then the IPA has not loaded yet. In this case,
7732 we optimistically assume that truncated 2-byte relative jumps
7733 will be available on x86, and compensate later if this assumption
7734 turns out to be incorrect. On x86-64 architectures, 4-byte relative
7735 jumps will always be used. */
7736 jumplen
= (register_size (gdbarch
, 0) == 8) ? 5 : 4;
7739 /* Dummy file descriptor for the disassembler. */
7741 gdb_null
= ui_file_new ();
7743 /* Check for fit. */
7744 len
= gdb_print_insn (gdbarch
, addr
, gdb_null
, NULL
);
7750 /* Return a bit of target-specific detail to add to the caller's
7751 generic failure message. */
7753 *msg
= xstrprintf (_("; instruction is only %d bytes long, "
7754 "need at least %d bytes for the jump"),
7767 i386_validate_tdesc_p (struct gdbarch_tdep
*tdep
,
7768 struct tdesc_arch_data
*tdesc_data
)
7770 const struct target_desc
*tdesc
= tdep
->tdesc
;
7771 const struct tdesc_feature
*feature_core
;
7772 const struct tdesc_feature
*feature_sse
, *feature_avx
, *feature_mpx
;
7773 int i
, num_regs
, valid_p
;
7775 if (! tdesc_has_registers (tdesc
))
7778 /* Get core registers. */
7779 feature_core
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.core");
7780 if (feature_core
== NULL
)
7783 /* Get SSE registers. */
7784 feature_sse
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.sse");
7786 /* Try AVX registers. */
7787 feature_avx
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx");
7789 /* Try MPX registers. */
7790 feature_mpx
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.mpx");
7794 /* The XCR0 bits. */
7797 /* AVX register description requires SSE register description. */
7801 tdep
->xcr0
= I386_XSTATE_AVX_MASK
;
7803 /* It may have been set by OSABI initialization function. */
7804 if (tdep
->num_ymm_regs
== 0)
7806 tdep
->ymmh_register_names
= i386_ymmh_names
;
7807 tdep
->num_ymm_regs
= 8;
7808 tdep
->ymm0h_regnum
= I386_YMM0H_REGNUM
;
7811 for (i
= 0; i
< tdep
->num_ymm_regs
; i
++)
7812 valid_p
&= tdesc_numbered_register (feature_avx
, tdesc_data
,
7813 tdep
->ymm0h_regnum
+ i
,
7814 tdep
->ymmh_register_names
[i
]);
7816 else if (feature_sse
)
7817 tdep
->xcr0
= I386_XSTATE_SSE_MASK
;
7820 tdep
->xcr0
= I386_XSTATE_X87_MASK
;
7821 tdep
->num_xmm_regs
= 0;
7824 num_regs
= tdep
->num_core_regs
;
7825 for (i
= 0; i
< num_regs
; i
++)
7826 valid_p
&= tdesc_numbered_register (feature_core
, tdesc_data
, i
,
7827 tdep
->register_names
[i
]);
7831 /* Need to include %mxcsr, so add one. */
7832 num_regs
+= tdep
->num_xmm_regs
+ 1;
7833 for (; i
< num_regs
; i
++)
7834 valid_p
&= tdesc_numbered_register (feature_sse
, tdesc_data
, i
,
7835 tdep
->register_names
[i
]);
7840 tdep
->xcr0
= I386_XSTATE_MPX_MASK
;
7842 if (tdep
->bnd0r_regnum
< 0)
7844 tdep
->mpx_register_names
= i386_mpx_names
;
7845 tdep
->bnd0r_regnum
= I386_BND0R_REGNUM
;
7846 tdep
->bndcfgu_regnum
= I386_BNDCFGU_REGNUM
;
7849 for (i
= 0; i
< I387_NUM_MPX_REGS
; i
++)
7850 valid_p
&= tdesc_numbered_register (feature_mpx
, tdesc_data
,
7851 I387_BND0R_REGNUM (tdep
) + i
,
7852 tdep
->mpx_register_names
[i
]);
7859 static struct gdbarch
*
7860 i386_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
7862 struct gdbarch_tdep
*tdep
;
7863 struct gdbarch
*gdbarch
;
7864 struct tdesc_arch_data
*tdesc_data
;
7865 const struct target_desc
*tdesc
;
7871 /* If there is already a candidate, use it. */
7872 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
7874 return arches
->gdbarch
;
7876 /* Allocate space for the new architecture. */
7877 tdep
= XCNEW (struct gdbarch_tdep
);
7878 gdbarch
= gdbarch_alloc (&info
, tdep
);
7880 /* General-purpose registers. */
7881 tdep
->gregset
= NULL
;
7882 tdep
->gregset_reg_offset
= NULL
;
7883 tdep
->gregset_num_regs
= I386_NUM_GREGS
;
7884 tdep
->sizeof_gregset
= 0;
7886 /* Floating-point registers. */
7887 tdep
->fpregset
= NULL
;
7888 tdep
->sizeof_fpregset
= I387_SIZEOF_FSAVE
;
7890 tdep
->xstateregset
= NULL
;
7892 /* The default settings include the FPU registers, the MMX registers
7893 and the SSE registers. This can be overridden for a specific ABI
7894 by adjusting the members `st0_regnum', `mm0_regnum' and
7895 `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers
7896 will show up in the output of "info all-registers". */
7898 tdep
->st0_regnum
= I386_ST0_REGNUM
;
7900 /* I386_NUM_XREGS includes %mxcsr, so substract one. */
7901 tdep
->num_xmm_regs
= I386_NUM_XREGS
- 1;
7903 tdep
->jb_pc_offset
= -1;
7904 tdep
->struct_return
= pcc_struct_return
;
7905 tdep
->sigtramp_start
= 0;
7906 tdep
->sigtramp_end
= 0;
7907 tdep
->sigtramp_p
= i386_sigtramp_p
;
7908 tdep
->sigcontext_addr
= NULL
;
7909 tdep
->sc_reg_offset
= NULL
;
7910 tdep
->sc_pc_offset
= -1;
7911 tdep
->sc_sp_offset
= -1;
7913 tdep
->xsave_xcr0_offset
= -1;
7915 tdep
->record_regmap
= i386_record_regmap
;
7917 set_gdbarch_long_long_align_bit (gdbarch
, 32);
7919 /* The format used for `long double' on almost all i386 targets is
7920 the i387 extended floating-point format. In fact, of all targets
7921 in the GCC 2.95 tree, only OSF/1 does it different, and insists
7922 on having a `long double' that's not `long' at all. */
7923 set_gdbarch_long_double_format (gdbarch
, floatformats_i387_ext
);
7925 /* Although the i387 extended floating-point has only 80 significant
7926 bits, a `long double' actually takes up 96, probably to enforce
7928 set_gdbarch_long_double_bit (gdbarch
, 96);
7930 /* Register numbers of various important registers. */
7931 set_gdbarch_sp_regnum (gdbarch
, I386_ESP_REGNUM
); /* %esp */
7932 set_gdbarch_pc_regnum (gdbarch
, I386_EIP_REGNUM
); /* %eip */
7933 set_gdbarch_ps_regnum (gdbarch
, I386_EFLAGS_REGNUM
); /* %eflags */
7934 set_gdbarch_fp0_regnum (gdbarch
, I386_ST0_REGNUM
); /* %st(0) */
7936 /* NOTE: kettenis/20040418: GCC does have two possible register
7937 numbering schemes on the i386: dbx and SVR4. These schemes
7938 differ in how they number %ebp, %esp, %eflags, and the
7939 floating-point registers, and are implemented by the arrays
7940 dbx_register_map[] and svr4_dbx_register_map in
7941 gcc/config/i386.c. GCC also defines a third numbering scheme in
7942 gcc/config/i386.c, which it designates as the "default" register
7943 map used in 64bit mode. This last register numbering scheme is
7944 implemented in dbx64_register_map, and is used for AMD64; see
7947 Currently, each GCC i386 target always uses the same register
7948 numbering scheme across all its supported debugging formats
7949 i.e. SDB (COFF), stabs and DWARF 2. This is because
7950 gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the
7951 DBX_REGISTER_NUMBER macro which is defined by each target's
7952 respective config header in a manner independent of the requested
7953 output debugging format.
7955 This does not match the arrangement below, which presumes that
7956 the SDB and stabs numbering schemes differ from the DWARF and
7957 DWARF 2 ones. The reason for this arrangement is that it is
7958 likely to get the numbering scheme for the target's
7959 default/native debug format right. For targets where GCC is the
7960 native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for
7961 targets where the native toolchain uses a different numbering
7962 scheme for a particular debug format (stabs-in-ELF on Solaris)
7963 the defaults below will have to be overridden, like
7964 i386_elf_init_abi() does. */
7966 /* Use the dbx register numbering scheme for stabs and COFF. */
7967 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
7968 set_gdbarch_sdb_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
7970 /* Use the SVR4 register numbering scheme for DWARF 2. */
7971 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
7973 /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to
7974 be in use on any of the supported i386 targets. */
7976 set_gdbarch_print_float_info (gdbarch
, i387_print_float_info
);
7978 set_gdbarch_get_longjmp_target (gdbarch
, i386_get_longjmp_target
);
7980 /* Call dummy code. */
7981 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
7982 set_gdbarch_push_dummy_code (gdbarch
, i386_push_dummy_code
);
7983 set_gdbarch_push_dummy_call (gdbarch
, i386_push_dummy_call
);
7984 set_gdbarch_frame_align (gdbarch
, i386_frame_align
);
7986 set_gdbarch_convert_register_p (gdbarch
, i386_convert_register_p
);
7987 set_gdbarch_register_to_value (gdbarch
, i386_register_to_value
);
7988 set_gdbarch_value_to_register (gdbarch
, i386_value_to_register
);
7990 set_gdbarch_return_value (gdbarch
, i386_return_value
);
7992 set_gdbarch_skip_prologue (gdbarch
, i386_skip_prologue
);
7994 /* Stack grows downward. */
7995 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
7997 set_gdbarch_breakpoint_from_pc (gdbarch
, i386_breakpoint_from_pc
);
7998 set_gdbarch_decr_pc_after_break (gdbarch
, 1);
7999 set_gdbarch_max_insn_length (gdbarch
, I386_MAX_INSN_LEN
);
8001 set_gdbarch_frame_args_skip (gdbarch
, 8);
8003 set_gdbarch_print_insn (gdbarch
, i386_print_insn
);
8005 set_gdbarch_dummy_id (gdbarch
, i386_dummy_id
);
8007 set_gdbarch_unwind_pc (gdbarch
, i386_unwind_pc
);
8009 /* Add the i386 register groups. */
8010 i386_add_reggroups (gdbarch
);
8011 tdep
->register_reggroup_p
= i386_register_reggroup_p
;
8013 /* Helper for function argument information. */
8014 set_gdbarch_fetch_pointer_argument (gdbarch
, i386_fetch_pointer_argument
);
8016 /* Hook the function epilogue frame unwinder. This unwinder is
8017 appended to the list first, so that it supercedes the DWARF
8018 unwinder in function epilogues (where the DWARF unwinder
8019 currently fails). */
8020 frame_unwind_append_unwinder (gdbarch
, &i386_epilogue_frame_unwind
);
8022 /* Hook in the DWARF CFI frame unwinder. This unwinder is appended
8023 to the list before the prologue-based unwinders, so that DWARF
8024 CFI info will be used if it is available. */
8025 dwarf2_append_unwinders (gdbarch
);
8027 frame_base_set_default (gdbarch
, &i386_frame_base
);
8029 /* Pseudo registers may be changed by amd64_init_abi. */
8030 set_gdbarch_pseudo_register_read_value (gdbarch
,
8031 i386_pseudo_register_read_value
);
8032 set_gdbarch_pseudo_register_write (gdbarch
, i386_pseudo_register_write
);
8034 set_tdesc_pseudo_register_type (gdbarch
, i386_pseudo_register_type
);
8035 set_tdesc_pseudo_register_name (gdbarch
, i386_pseudo_register_name
);
8037 /* Override the normal target description method to make the AVX
8038 upper halves anonymous. */
8039 set_gdbarch_register_name (gdbarch
, i386_register_name
);
8041 /* Even though the default ABI only includes general-purpose registers,
8042 floating-point registers and the SSE registers, we have to leave a
8043 gap for the upper AVX registers and the MPX registers. */
8044 set_gdbarch_num_regs (gdbarch
, I386_MPX_NUM_REGS
);
8046 /* Get the x86 target description from INFO. */
8047 tdesc
= info
.target_desc
;
8048 if (! tdesc_has_registers (tdesc
))
8050 tdep
->tdesc
= tdesc
;
8052 tdep
->num_core_regs
= I386_NUM_GREGS
+ I387_NUM_REGS
;
8053 tdep
->register_names
= i386_register_names
;
8055 /* No upper YMM registers. */
8056 tdep
->ymmh_register_names
= NULL
;
8057 tdep
->ymm0h_regnum
= -1;
8059 tdep
->num_byte_regs
= 8;
8060 tdep
->num_word_regs
= 8;
8061 tdep
->num_dword_regs
= 0;
8062 tdep
->num_mmx_regs
= 8;
8063 tdep
->num_ymm_regs
= 0;
8065 /* No MPX registers. */
8066 tdep
->bnd0r_regnum
= -1;
8067 tdep
->bndcfgu_regnum
= -1;
8069 tdesc_data
= tdesc_data_alloc ();
8071 set_gdbarch_relocate_instruction (gdbarch
, i386_relocate_instruction
);
8073 set_gdbarch_gen_return_address (gdbarch
, i386_gen_return_address
);
8075 set_gdbarch_insn_is_call (gdbarch
, i386_insn_is_call
);
8076 set_gdbarch_insn_is_ret (gdbarch
, i386_insn_is_ret
);
8077 set_gdbarch_insn_is_jump (gdbarch
, i386_insn_is_jump
);
8079 /* Hook in ABI-specific overrides, if they have been registered. */
8080 info
.tdep_info
= (void *) tdesc_data
;
8081 gdbarch_init_osabi (info
, gdbarch
);
8083 if (!i386_validate_tdesc_p (tdep
, tdesc_data
))
8085 tdesc_data_cleanup (tdesc_data
);
8087 gdbarch_free (gdbarch
);
8091 num_bnd_cooked
= (tdep
->bnd0r_regnum
> 0 ? I387_NUM_BND_REGS
: 0);
8093 /* Wire in pseudo registers. Number of pseudo registers may be
8095 set_gdbarch_num_pseudo_regs (gdbarch
, (tdep
->num_byte_regs
8096 + tdep
->num_word_regs
8097 + tdep
->num_dword_regs
8098 + tdep
->num_mmx_regs
8099 + tdep
->num_ymm_regs
8102 /* Target description may be changed. */
8103 tdesc
= tdep
->tdesc
;
8105 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
8107 /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */
8108 set_gdbarch_register_reggroup_p (gdbarch
, tdep
->register_reggroup_p
);
8110 /* Make %al the first pseudo-register. */
8111 tdep
->al_regnum
= gdbarch_num_regs (gdbarch
);
8112 tdep
->ax_regnum
= tdep
->al_regnum
+ tdep
->num_byte_regs
;
8114 ymm0_regnum
= tdep
->ax_regnum
+ tdep
->num_word_regs
;
8115 if (tdep
->num_dword_regs
)
8117 /* Support dword pseudo-register if it hasn't been disabled. */
8118 tdep
->eax_regnum
= ymm0_regnum
;
8119 ymm0_regnum
+= tdep
->num_dword_regs
;
8122 tdep
->eax_regnum
= -1;
8124 mm0_regnum
= ymm0_regnum
;
8125 if (tdep
->num_ymm_regs
)
8127 /* Support YMM pseudo-register if it is available. */
8128 tdep
->ymm0_regnum
= ymm0_regnum
;
8129 mm0_regnum
+= tdep
->num_ymm_regs
;
8132 tdep
->ymm0_regnum
= -1;
8134 bnd0_regnum
= mm0_regnum
;
8135 if (tdep
->num_mmx_regs
!= 0)
8137 /* Support MMX pseudo-register if MMX hasn't been disabled. */
8138 tdep
->mm0_regnum
= mm0_regnum
;
8139 bnd0_regnum
+= tdep
->num_mmx_regs
;
8142 tdep
->mm0_regnum
= -1;
8144 if (tdep
->bnd0r_regnum
> 0)
8145 tdep
->bnd0_regnum
= bnd0_regnum
;
8147 tdep
-> bnd0_regnum
= -1;
8149 /* Hook in the legacy prologue-based unwinders last (fallback). */
8150 frame_unwind_append_unwinder (gdbarch
, &i386_stack_tramp_frame_unwind
);
8151 frame_unwind_append_unwinder (gdbarch
, &i386_sigtramp_frame_unwind
);
8152 frame_unwind_append_unwinder (gdbarch
, &i386_frame_unwind
);
8154 /* If we have a register mapping, enable the generic core file
8155 support, unless it has already been enabled. */
8156 if (tdep
->gregset_reg_offset
8157 && !gdbarch_regset_from_core_section_p (gdbarch
))
8158 set_gdbarch_regset_from_core_section (gdbarch
,
8159 i386_regset_from_core_section
);
8161 set_gdbarch_skip_permanent_breakpoint (gdbarch
,
8162 i386_skip_permanent_breakpoint
);
8164 set_gdbarch_fast_tracepoint_valid_at (gdbarch
,
8165 i386_fast_tracepoint_valid_at
);
8170 static enum gdb_osabi
8171 i386_coff_osabi_sniffer (bfd
*abfd
)
8173 if (strcmp (bfd_get_target (abfd
), "coff-go32-exe") == 0
8174 || strcmp (bfd_get_target (abfd
), "coff-go32") == 0)
8175 return GDB_OSABI_GO32
;
8177 return GDB_OSABI_UNKNOWN
;
8181 /* Provide a prototype to silence -Wmissing-prototypes. */
8182 void _initialize_i386_tdep (void);
8185 _initialize_i386_tdep (void)
8187 register_gdbarch_init (bfd_arch_i386
, i386_gdbarch_init
);
8189 /* Add the variable that controls the disassembly flavor. */
8190 add_setshow_enum_cmd ("disassembly-flavor", no_class
, valid_flavors
,
8191 &disassembly_flavor
, _("\
8192 Set the disassembly flavor."), _("\
8193 Show the disassembly flavor."), _("\
8194 The valid values are \"att\" and \"intel\", and the default value is \"att\"."),
8196 NULL
, /* FIXME: i18n: */
8197 &setlist
, &showlist
);
8199 /* Add the variable that controls the convention for returning
8201 add_setshow_enum_cmd ("struct-convention", no_class
, valid_conventions
,
8202 &struct_convention
, _("\
8203 Set the convention for returning small structs."), _("\
8204 Show the convention for returning small structs."), _("\
8205 Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\
8208 NULL
, /* FIXME: i18n: */
8209 &setlist
, &showlist
);
8211 gdbarch_register_osabi_sniffer (bfd_arch_i386
, bfd_target_coff_flavour
,
8212 i386_coff_osabi_sniffer
);
8214 gdbarch_register_osabi (bfd_arch_i386
, 0, GDB_OSABI_SVR4
,
8215 i386_svr4_init_abi
);
8216 gdbarch_register_osabi (bfd_arch_i386
, 0, GDB_OSABI_GO32
,
8217 i386_go32_init_abi
);
8219 /* Initialize the i386-specific register groups. */
8220 i386_init_reggroups ();
8222 /* Initialize the standard target descriptions. */
8223 initialize_tdesc_i386 ();
8224 initialize_tdesc_i386_mmx ();
8225 initialize_tdesc_i386_avx ();
8226 initialize_tdesc_i386_mpx ();
8228 /* Tell remote stub that we support XML target description. */
8229 register_remote_support_xml ("i386");