1 /* Intel 386 target-dependent stuff.
3 Copyright (C) 1988-2013 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "opcode/i386.h"
22 #include "arch-utils.h"
24 #include "dummy-frame.h"
25 #include "dwarf2-frame.h"
28 #include "frame-base.h"
29 #include "frame-unwind.h"
37 #include "reggroups.h"
46 #include "exceptions.h"
47 #include "gdb_assert.h"
50 #include "i386-tdep.h"
51 #include "i387-tdep.h"
52 #include "i386-xstate.h"
55 #include "record-full.h"
58 #include "features/i386/i386.c"
59 #include "features/i386/i386-avx.c"
60 #include "features/i386/i386-mpx.c"
61 #include "features/i386/i386-mmx.c"
66 #include "stap-probe.h"
67 #include "user-regs.h"
68 #include "cli/cli-utils.h"
69 #include "expression.h"
70 #include "parser-defs.h"
75 static const char *i386_register_names
[] =
77 "eax", "ecx", "edx", "ebx",
78 "esp", "ebp", "esi", "edi",
79 "eip", "eflags", "cs", "ss",
80 "ds", "es", "fs", "gs",
81 "st0", "st1", "st2", "st3",
82 "st4", "st5", "st6", "st7",
83 "fctrl", "fstat", "ftag", "fiseg",
84 "fioff", "foseg", "fooff", "fop",
85 "xmm0", "xmm1", "xmm2", "xmm3",
86 "xmm4", "xmm5", "xmm6", "xmm7",
90 static const char *i386_ymm_names
[] =
92 "ymm0", "ymm1", "ymm2", "ymm3",
93 "ymm4", "ymm5", "ymm6", "ymm7",
96 static const char *i386_ymmh_names
[] =
98 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
99 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
102 static const char *i386_mpx_names
[] =
104 "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus"
107 /* Register names for MPX pseudo-registers. */
109 static const char *i386_bnd_names
[] =
111 "bnd0", "bnd1", "bnd2", "bnd3"
114 /* Register names for MMX pseudo-registers. */
116 static const char *i386_mmx_names
[] =
118 "mm0", "mm1", "mm2", "mm3",
119 "mm4", "mm5", "mm6", "mm7"
122 /* Register names for byte pseudo-registers. */
124 static const char *i386_byte_names
[] =
126 "al", "cl", "dl", "bl",
127 "ah", "ch", "dh", "bh"
130 /* Register names for word pseudo-registers. */
132 static const char *i386_word_names
[] =
134 "ax", "cx", "dx", "bx",
141 i386_mmx_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
143 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
144 int mm0_regnum
= tdep
->mm0_regnum
;
149 regnum
-= mm0_regnum
;
150 return regnum
>= 0 && regnum
< tdep
->num_mmx_regs
;
156 i386_byte_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
158 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
160 regnum
-= tdep
->al_regnum
;
161 return regnum
>= 0 && regnum
< tdep
->num_byte_regs
;
167 i386_word_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
169 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
171 regnum
-= tdep
->ax_regnum
;
172 return regnum
>= 0 && regnum
< tdep
->num_word_regs
;
175 /* Dword register? */
178 i386_dword_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
180 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
181 int eax_regnum
= tdep
->eax_regnum
;
186 regnum
-= eax_regnum
;
187 return regnum
>= 0 && regnum
< tdep
->num_dword_regs
;
191 i386_ymmh_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
193 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
194 int ymm0h_regnum
= tdep
->ymm0h_regnum
;
196 if (ymm0h_regnum
< 0)
199 regnum
-= ymm0h_regnum
;
200 return regnum
>= 0 && regnum
< tdep
->num_ymm_regs
;
206 i386_ymm_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
208 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
209 int ymm0_regnum
= tdep
->ymm0_regnum
;
214 regnum
-= ymm0_regnum
;
215 return regnum
>= 0 && regnum
< tdep
->num_ymm_regs
;
221 i386_bnd_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
223 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
224 int bnd0_regnum
= tdep
->bnd0_regnum
;
229 regnum
-= bnd0_regnum
;
230 return regnum
>= 0 && regnum
< I387_NUM_BND_REGS
;
236 i386_xmm_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
238 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
239 int num_xmm_regs
= I387_NUM_XMM_REGS (tdep
);
241 if (num_xmm_regs
== 0)
244 regnum
-= I387_XMM0_REGNUM (tdep
);
245 return regnum
>= 0 && regnum
< num_xmm_regs
;
249 i386_mxcsr_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
251 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
253 if (I387_NUM_XMM_REGS (tdep
) == 0)
256 return (regnum
== I387_MXCSR_REGNUM (tdep
));
262 i386_fp_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
264 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
266 if (I387_ST0_REGNUM (tdep
) < 0)
269 return (I387_ST0_REGNUM (tdep
) <= regnum
270 && regnum
< I387_FCTRL_REGNUM (tdep
));
274 i386_fpc_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
276 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
278 if (I387_ST0_REGNUM (tdep
) < 0)
281 return (I387_FCTRL_REGNUM (tdep
) <= regnum
282 && regnum
< I387_XMM0_REGNUM (tdep
));
285 /* BNDr (raw) register? */
288 i386_bndr_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
290 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
292 if (I387_BND0R_REGNUM (tdep
) < 0)
295 regnum
-= tdep
->bnd0r_regnum
;
296 return regnum
>= 0 && regnum
< I387_NUM_BND_REGS
;
299 /* BND control register? */
302 i386_mpx_ctrl_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
304 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
306 if (I387_BNDCFGU_REGNUM (tdep
) < 0)
309 regnum
-= I387_BNDCFGU_REGNUM (tdep
);
310 return regnum
>= 0 && regnum
< I387_NUM_MPX_CTRL_REGS
;
313 /* Return the name of register REGNUM, or the empty string if it is
314 an anonymous register. */
317 i386_register_name (struct gdbarch
*gdbarch
, int regnum
)
319 /* Hide the upper YMM registers. */
320 if (i386_ymmh_regnum_p (gdbarch
, regnum
))
323 return tdesc_register_name (gdbarch
, regnum
);
326 /* Return the name of register REGNUM. */
329 i386_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
331 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
332 if (i386_bnd_regnum_p (gdbarch
, regnum
))
333 return i386_bnd_names
[regnum
- tdep
->bnd0_regnum
];
334 if (i386_mmx_regnum_p (gdbarch
, regnum
))
335 return i386_mmx_names
[regnum
- I387_MM0_REGNUM (tdep
)];
336 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
337 return i386_ymm_names
[regnum
- tdep
->ymm0_regnum
];
338 else if (i386_byte_regnum_p (gdbarch
, regnum
))
339 return i386_byte_names
[regnum
- tdep
->al_regnum
];
340 else if (i386_word_regnum_p (gdbarch
, regnum
))
341 return i386_word_names
[regnum
- tdep
->ax_regnum
];
343 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
346 /* Convert a dbx register number REG to the appropriate register
347 number used by GDB. */
350 i386_dbx_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
352 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
354 /* This implements what GCC calls the "default" register map
355 (dbx_register_map[]). */
357 if (reg
>= 0 && reg
<= 7)
359 /* General-purpose registers. The debug info calls %ebp
360 register 4, and %esp register 5. */
367 else if (reg
>= 12 && reg
<= 19)
369 /* Floating-point registers. */
370 return reg
- 12 + I387_ST0_REGNUM (tdep
);
372 else if (reg
>= 21 && reg
<= 28)
375 int ymm0_regnum
= tdep
->ymm0_regnum
;
378 && i386_xmm_regnum_p (gdbarch
, reg
))
379 return reg
- 21 + ymm0_regnum
;
381 return reg
- 21 + I387_XMM0_REGNUM (tdep
);
383 else if (reg
>= 29 && reg
<= 36)
386 return reg
- 29 + I387_MM0_REGNUM (tdep
);
389 /* This will hopefully provoke a warning. */
390 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
393 /* Convert SVR4 register number REG to the appropriate register number
397 i386_svr4_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
399 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
401 /* This implements the GCC register map that tries to be compatible
402 with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */
404 /* The SVR4 register numbering includes %eip and %eflags, and
405 numbers the floating point registers differently. */
406 if (reg
>= 0 && reg
<= 9)
408 /* General-purpose registers. */
411 else if (reg
>= 11 && reg
<= 18)
413 /* Floating-point registers. */
414 return reg
- 11 + I387_ST0_REGNUM (tdep
);
416 else if (reg
>= 21 && reg
<= 36)
418 /* The SSE and MMX registers have the same numbers as with dbx. */
419 return i386_dbx_reg_to_regnum (gdbarch
, reg
);
424 case 37: return I387_FCTRL_REGNUM (tdep
);
425 case 38: return I387_FSTAT_REGNUM (tdep
);
426 case 39: return I387_MXCSR_REGNUM (tdep
);
427 case 40: return I386_ES_REGNUM
;
428 case 41: return I386_CS_REGNUM
;
429 case 42: return I386_SS_REGNUM
;
430 case 43: return I386_DS_REGNUM
;
431 case 44: return I386_FS_REGNUM
;
432 case 45: return I386_GS_REGNUM
;
435 /* This will hopefully provoke a warning. */
436 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
441 /* This is the variable that is set with "set disassembly-flavor", and
442 its legitimate values. */
443 static const char att_flavor
[] = "att";
444 static const char intel_flavor
[] = "intel";
445 static const char *const valid_flavors
[] =
451 static const char *disassembly_flavor
= att_flavor
;
454 /* Use the program counter to determine the contents and size of a
455 breakpoint instruction. Return a pointer to a string of bytes that
456 encode a breakpoint instruction, store the length of the string in
457 *LEN and optionally adjust *PC to point to the correct memory
458 location for inserting the breakpoint.
460 On the i386 we have a single breakpoint that fits in a single byte
461 and can be inserted anywhere.
463 This function is 64-bit safe. */
465 static const gdb_byte
*
466 i386_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pc
, int *len
)
468 static gdb_byte break_insn
[] = { 0xcc }; /* int 3 */
470 *len
= sizeof (break_insn
);
474 /* Displaced instruction handling. */
476 /* Skip the legacy instruction prefixes in INSN.
477 Not all prefixes are valid for any particular insn
478 but we needn't care, the insn will fault if it's invalid.
479 The result is a pointer to the first opcode byte,
480 or NULL if we run off the end of the buffer. */
483 i386_skip_prefixes (gdb_byte
*insn
, size_t max_len
)
485 gdb_byte
*end
= insn
+ max_len
;
491 case DATA_PREFIX_OPCODE
:
492 case ADDR_PREFIX_OPCODE
:
493 case CS_PREFIX_OPCODE
:
494 case DS_PREFIX_OPCODE
:
495 case ES_PREFIX_OPCODE
:
496 case FS_PREFIX_OPCODE
:
497 case GS_PREFIX_OPCODE
:
498 case SS_PREFIX_OPCODE
:
499 case LOCK_PREFIX_OPCODE
:
500 case REPE_PREFIX_OPCODE
:
501 case REPNE_PREFIX_OPCODE
:
513 i386_absolute_jmp_p (const gdb_byte
*insn
)
515 /* jmp far (absolute address in operand). */
521 /* jump near, absolute indirect (/4). */
522 if ((insn
[1] & 0x38) == 0x20)
525 /* jump far, absolute indirect (/5). */
526 if ((insn
[1] & 0x38) == 0x28)
534 i386_absolute_call_p (const gdb_byte
*insn
)
536 /* call far, absolute. */
542 /* Call near, absolute indirect (/2). */
543 if ((insn
[1] & 0x38) == 0x10)
546 /* Call far, absolute indirect (/3). */
547 if ((insn
[1] & 0x38) == 0x18)
555 i386_ret_p (const gdb_byte
*insn
)
559 case 0xc2: /* ret near, pop N bytes. */
560 case 0xc3: /* ret near */
561 case 0xca: /* ret far, pop N bytes. */
562 case 0xcb: /* ret far */
563 case 0xcf: /* iret */
572 i386_call_p (const gdb_byte
*insn
)
574 if (i386_absolute_call_p (insn
))
577 /* call near, relative. */
584 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
585 length in bytes. Otherwise, return zero. */
588 i386_syscall_p (const gdb_byte
*insn
, int *lengthp
)
590 /* Is it 'int $0x80'? */
591 if ((insn
[0] == 0xcd && insn
[1] == 0x80)
592 /* Or is it 'sysenter'? */
593 || (insn
[0] == 0x0f && insn
[1] == 0x34)
594 /* Or is it 'syscall'? */
595 || (insn
[0] == 0x0f && insn
[1] == 0x05))
604 /* Some kernels may run one past a syscall insn, so we have to cope.
605 Otherwise this is just simple_displaced_step_copy_insn. */
607 struct displaced_step_closure
*
608 i386_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
609 CORE_ADDR from
, CORE_ADDR to
,
610 struct regcache
*regs
)
612 size_t len
= gdbarch_max_insn_length (gdbarch
);
613 gdb_byte
*buf
= xmalloc (len
);
615 read_memory (from
, buf
, len
);
617 /* GDB may get control back after the insn after the syscall.
618 Presumably this is a kernel bug.
619 If this is a syscall, make sure there's a nop afterwards. */
624 insn
= i386_skip_prefixes (buf
, len
);
625 if (insn
!= NULL
&& i386_syscall_p (insn
, &syscall_length
))
626 insn
[syscall_length
] = NOP_OPCODE
;
629 write_memory (to
, buf
, len
);
633 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
634 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
635 displaced_step_dump_bytes (gdb_stdlog
, buf
, len
);
638 return (struct displaced_step_closure
*) buf
;
641 /* Fix up the state of registers and memory after having single-stepped
642 a displaced instruction. */
645 i386_displaced_step_fixup (struct gdbarch
*gdbarch
,
646 struct displaced_step_closure
*closure
,
647 CORE_ADDR from
, CORE_ADDR to
,
648 struct regcache
*regs
)
650 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
652 /* The offset we applied to the instruction's address.
653 This could well be negative (when viewed as a signed 32-bit
654 value), but ULONGEST won't reflect that, so take care when
656 ULONGEST insn_offset
= to
- from
;
658 /* Since we use simple_displaced_step_copy_insn, our closure is a
659 copy of the instruction. */
660 gdb_byte
*insn
= (gdb_byte
*) closure
;
661 /* The start of the insn, needed in case we see some prefixes. */
662 gdb_byte
*insn_start
= insn
;
665 fprintf_unfiltered (gdb_stdlog
,
666 "displaced: fixup (%s, %s), "
667 "insn = 0x%02x 0x%02x ...\n",
668 paddress (gdbarch
, from
), paddress (gdbarch
, to
),
671 /* The list of issues to contend with here is taken from
672 resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20.
673 Yay for Free Software! */
675 /* Relocate the %eip, if necessary. */
677 /* The instruction recognizers we use assume any leading prefixes
678 have been skipped. */
680 /* This is the size of the buffer in closure. */
681 size_t max_insn_len
= gdbarch_max_insn_length (gdbarch
);
682 gdb_byte
*opcode
= i386_skip_prefixes (insn
, max_insn_len
);
683 /* If there are too many prefixes, just ignore the insn.
684 It will fault when run. */
689 /* Except in the case of absolute or indirect jump or call
690 instructions, or a return instruction, the new eip is relative to
691 the displaced instruction; make it relative. Well, signal
692 handler returns don't need relocation either, but we use the
693 value of %eip to recognize those; see below. */
694 if (! i386_absolute_jmp_p (insn
)
695 && ! i386_absolute_call_p (insn
)
696 && ! i386_ret_p (insn
))
701 regcache_cooked_read_unsigned (regs
, I386_EIP_REGNUM
, &orig_eip
);
703 /* A signal trampoline system call changes the %eip, resuming
704 execution of the main program after the signal handler has
705 returned. That makes them like 'return' instructions; we
706 shouldn't relocate %eip.
708 But most system calls don't, and we do need to relocate %eip.
710 Our heuristic for distinguishing these cases: if stepping
711 over the system call instruction left control directly after
712 the instruction, the we relocate --- control almost certainly
713 doesn't belong in the displaced copy. Otherwise, we assume
714 the instruction has put control where it belongs, and leave
715 it unrelocated. Goodness help us if there are PC-relative
717 if (i386_syscall_p (insn
, &insn_len
)
718 && orig_eip
!= to
+ (insn
- insn_start
) + insn_len
719 /* GDB can get control back after the insn after the syscall.
720 Presumably this is a kernel bug.
721 i386_displaced_step_copy_insn ensures its a nop,
722 we add one to the length for it. */
723 && orig_eip
!= to
+ (insn
- insn_start
) + insn_len
+ 1)
726 fprintf_unfiltered (gdb_stdlog
,
727 "displaced: syscall changed %%eip; "
732 ULONGEST eip
= (orig_eip
- insn_offset
) & 0xffffffffUL
;
734 /* If we just stepped over a breakpoint insn, we don't backup
735 the pc on purpose; this is to match behaviour without
738 regcache_cooked_write_unsigned (regs
, I386_EIP_REGNUM
, eip
);
741 fprintf_unfiltered (gdb_stdlog
,
743 "relocated %%eip from %s to %s\n",
744 paddress (gdbarch
, orig_eip
),
745 paddress (gdbarch
, eip
));
749 /* If the instruction was PUSHFL, then the TF bit will be set in the
750 pushed value, and should be cleared. We'll leave this for later,
751 since GDB already messes up the TF flag when stepping over a
754 /* If the instruction was a call, the return address now atop the
755 stack is the address following the copied instruction. We need
756 to make it the address following the original instruction. */
757 if (i386_call_p (insn
))
761 const ULONGEST retaddr_len
= 4;
763 regcache_cooked_read_unsigned (regs
, I386_ESP_REGNUM
, &esp
);
764 retaddr
= read_memory_unsigned_integer (esp
, retaddr_len
, byte_order
);
765 retaddr
= (retaddr
- insn_offset
) & 0xffffffffUL
;
766 write_memory_unsigned_integer (esp
, retaddr_len
, byte_order
, retaddr
);
769 fprintf_unfiltered (gdb_stdlog
,
770 "displaced: relocated return addr at %s to %s\n",
771 paddress (gdbarch
, esp
),
772 paddress (gdbarch
, retaddr
));
777 append_insns (CORE_ADDR
*to
, ULONGEST len
, const gdb_byte
*buf
)
779 target_write_memory (*to
, buf
, len
);
784 i386_relocate_instruction (struct gdbarch
*gdbarch
,
785 CORE_ADDR
*to
, CORE_ADDR oldloc
)
787 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
788 gdb_byte buf
[I386_MAX_INSN_LEN
];
789 int offset
= 0, rel32
, newrel
;
791 gdb_byte
*insn
= buf
;
793 read_memory (oldloc
, buf
, I386_MAX_INSN_LEN
);
795 insn_length
= gdb_buffered_insn_length (gdbarch
, insn
,
796 I386_MAX_INSN_LEN
, oldloc
);
798 /* Get past the prefixes. */
799 insn
= i386_skip_prefixes (insn
, I386_MAX_INSN_LEN
);
801 /* Adjust calls with 32-bit relative addresses as push/jump, with
802 the address pushed being the location where the original call in
803 the user program would return to. */
806 gdb_byte push_buf
[16];
807 unsigned int ret_addr
;
809 /* Where "ret" in the original code will return to. */
810 ret_addr
= oldloc
+ insn_length
;
811 push_buf
[0] = 0x68; /* pushq $... */
812 store_unsigned_integer (&push_buf
[1], 4, byte_order
, ret_addr
);
814 append_insns (to
, 5, push_buf
);
816 /* Convert the relative call to a relative jump. */
819 /* Adjust the destination offset. */
820 rel32
= extract_signed_integer (insn
+ 1, 4, byte_order
);
821 newrel
= (oldloc
- *to
) + rel32
;
822 store_signed_integer (insn
+ 1, 4, byte_order
, newrel
);
825 fprintf_unfiltered (gdb_stdlog
,
826 "Adjusted insn rel32=%s at %s to"
828 hex_string (rel32
), paddress (gdbarch
, oldloc
),
829 hex_string (newrel
), paddress (gdbarch
, *to
));
831 /* Write the adjusted jump into its displaced location. */
832 append_insns (to
, 5, insn
);
836 /* Adjust jumps with 32-bit relative addresses. Calls are already
840 /* Adjust conditional jumps. */
841 else if (insn
[0] == 0x0f && (insn
[1] & 0xf0) == 0x80)
846 rel32
= extract_signed_integer (insn
+ offset
, 4, byte_order
);
847 newrel
= (oldloc
- *to
) + rel32
;
848 store_signed_integer (insn
+ offset
, 4, byte_order
, newrel
);
850 fprintf_unfiltered (gdb_stdlog
,
851 "Adjusted insn rel32=%s at %s to"
853 hex_string (rel32
), paddress (gdbarch
, oldloc
),
854 hex_string (newrel
), paddress (gdbarch
, *to
));
857 /* Write the adjusted instructions into their displaced
859 append_insns (to
, insn_length
, buf
);
863 #ifdef I386_REGNO_TO_SYMMETRY
864 #error "The Sequent Symmetry is no longer supported."
867 /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi
868 and %esp "belong" to the calling function. Therefore these
869 registers should be saved if they're going to be modified. */
871 /* The maximum number of saved registers. This should include all
872 registers mentioned above, and %eip. */
873 #define I386_NUM_SAVED_REGS I386_NUM_GREGS
875 struct i386_frame_cache
883 /* Saved registers. */
884 CORE_ADDR saved_regs
[I386_NUM_SAVED_REGS
];
889 /* Stack space reserved for local variables. */
893 /* Allocate and initialize a frame cache. */
895 static struct i386_frame_cache
*
896 i386_alloc_frame_cache (void)
898 struct i386_frame_cache
*cache
;
901 cache
= FRAME_OBSTACK_ZALLOC (struct i386_frame_cache
);
906 cache
->sp_offset
= -4;
909 /* Saved registers. We initialize these to -1 since zero is a valid
910 offset (that's where %ebp is supposed to be stored). */
911 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
912 cache
->saved_regs
[i
] = -1;
914 cache
->saved_sp_reg
= -1;
915 cache
->pc_in_eax
= 0;
917 /* Frameless until proven otherwise. */
923 /* If the instruction at PC is a jump, return the address of its
924 target. Otherwise, return PC. */
927 i386_follow_jump (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
929 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
934 if (target_read_memory (pc
, &op
, 1))
940 op
= read_memory_unsigned_integer (pc
+ 1, 1, byte_order
);
946 /* Relative jump: if data16 == 0, disp32, else disp16. */
949 delta
= read_memory_integer (pc
+ 2, 2, byte_order
);
951 /* Include the size of the jmp instruction (including the
957 delta
= read_memory_integer (pc
+ 1, 4, byte_order
);
959 /* Include the size of the jmp instruction. */
964 /* Relative jump, disp8 (ignore data16). */
965 delta
= read_memory_integer (pc
+ data16
+ 1, 1, byte_order
);
974 /* Check whether PC points at a prologue for a function returning a
975 structure or union. If so, it updates CACHE and returns the
976 address of the first instruction after the code sequence that
977 removes the "hidden" argument from the stack or CURRENT_PC,
978 whichever is smaller. Otherwise, return PC. */
981 i386_analyze_struct_return (CORE_ADDR pc
, CORE_ADDR current_pc
,
982 struct i386_frame_cache
*cache
)
984 /* Functions that return a structure or union start with:
987 xchgl %eax, (%esp) 0x87 0x04 0x24
988 or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00
990 (the System V compiler puts out the second `xchg' instruction,
991 and the assembler doesn't try to optimize it, so the 'sib' form
992 gets generated). This sequence is used to get the address of the
993 return buffer for a function that returns a structure. */
994 static gdb_byte proto1
[3] = { 0x87, 0x04, 0x24 };
995 static gdb_byte proto2
[4] = { 0x87, 0x44, 0x24, 0x00 };
999 if (current_pc
<= pc
)
1002 if (target_read_memory (pc
, &op
, 1))
1005 if (op
!= 0x58) /* popl %eax */
1008 if (target_read_memory (pc
+ 1, buf
, 4))
1011 if (memcmp (buf
, proto1
, 3) != 0 && memcmp (buf
, proto2
, 4) != 0)
1014 if (current_pc
== pc
)
1016 cache
->sp_offset
+= 4;
1020 if (current_pc
== pc
+ 1)
1022 cache
->pc_in_eax
= 1;
1026 if (buf
[1] == proto1
[1])
1033 i386_skip_probe (CORE_ADDR pc
)
1035 /* A function may start with
1049 if (target_read_memory (pc
, &op
, 1))
1052 if (op
== 0x68 || op
== 0x6a)
1056 /* Skip past the `pushl' instruction; it has either a one-byte or a
1057 four-byte operand, depending on the opcode. */
1063 /* Read the following 8 bytes, which should be `call _probe' (6
1064 bytes) followed by `addl $4,%esp' (2 bytes). */
1065 read_memory (pc
+ delta
, buf
, sizeof (buf
));
1066 if (buf
[0] == 0xe8 && buf
[6] == 0xc4 && buf
[7] == 0x4)
1067 pc
+= delta
+ sizeof (buf
);
1073 /* GCC 4.1 and later, can put code in the prologue to realign the
1074 stack pointer. Check whether PC points to such code, and update
1075 CACHE accordingly. Return the first instruction after the code
1076 sequence or CURRENT_PC, whichever is smaller. If we don't
1077 recognize the code, return PC. */
1080 i386_analyze_stack_align (CORE_ADDR pc
, CORE_ADDR current_pc
,
1081 struct i386_frame_cache
*cache
)
1083 /* There are 2 code sequences to re-align stack before the frame
1086 1. Use a caller-saved saved register:
1092 2. Use a callee-saved saved register:
1099 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
1101 0x83 0xe4 0xf0 andl $-16, %esp
1102 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
1107 int offset
, offset_and
;
1108 static int regnums
[8] = {
1109 I386_EAX_REGNUM
, /* %eax */
1110 I386_ECX_REGNUM
, /* %ecx */
1111 I386_EDX_REGNUM
, /* %edx */
1112 I386_EBX_REGNUM
, /* %ebx */
1113 I386_ESP_REGNUM
, /* %esp */
1114 I386_EBP_REGNUM
, /* %ebp */
1115 I386_ESI_REGNUM
, /* %esi */
1116 I386_EDI_REGNUM
/* %edi */
1119 if (target_read_memory (pc
, buf
, sizeof buf
))
1122 /* Check caller-saved saved register. The first instruction has
1123 to be "leal 4(%esp), %reg". */
1124 if (buf
[0] == 0x8d && buf
[2] == 0x24 && buf
[3] == 0x4)
1126 /* MOD must be binary 10 and R/M must be binary 100. */
1127 if ((buf
[1] & 0xc7) != 0x44)
1130 /* REG has register number. */
1131 reg
= (buf
[1] >> 3) & 7;
1136 /* Check callee-saved saved register. The first instruction
1137 has to be "pushl %reg". */
1138 if ((buf
[0] & 0xf8) != 0x50)
1144 /* The next instruction has to be "leal 8(%esp), %reg". */
1145 if (buf
[1] != 0x8d || buf
[3] != 0x24 || buf
[4] != 0x8)
1148 /* MOD must be binary 10 and R/M must be binary 100. */
1149 if ((buf
[2] & 0xc7) != 0x44)
1152 /* REG has register number. Registers in pushl and leal have to
1154 if (reg
!= ((buf
[2] >> 3) & 7))
1160 /* Rigister can't be %esp nor %ebp. */
1161 if (reg
== 4 || reg
== 5)
1164 /* The next instruction has to be "andl $-XXX, %esp". */
1165 if (buf
[offset
+ 1] != 0xe4
1166 || (buf
[offset
] != 0x81 && buf
[offset
] != 0x83))
1169 offset_and
= offset
;
1170 offset
+= buf
[offset
] == 0x81 ? 6 : 3;
1172 /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is
1173 0xfc. REG must be binary 110 and MOD must be binary 01. */
1174 if (buf
[offset
] != 0xff
1175 || buf
[offset
+ 2] != 0xfc
1176 || (buf
[offset
+ 1] & 0xf8) != 0x70)
1179 /* R/M has register. Registers in leal and pushl have to be the
1181 if (reg
!= (buf
[offset
+ 1] & 7))
1184 if (current_pc
> pc
+ offset_and
)
1185 cache
->saved_sp_reg
= regnums
[reg
];
1187 return min (pc
+ offset
+ 3, current_pc
);
1190 /* Maximum instruction length we need to handle. */
1191 #define I386_MAX_MATCHED_INSN_LEN 6
1193 /* Instruction description. */
1197 gdb_byte insn
[I386_MAX_MATCHED_INSN_LEN
];
1198 gdb_byte mask
[I386_MAX_MATCHED_INSN_LEN
];
1201 /* Return whether instruction at PC matches PATTERN. */
1204 i386_match_pattern (CORE_ADDR pc
, struct i386_insn pattern
)
1208 if (target_read_memory (pc
, &op
, 1))
1211 if ((op
& pattern
.mask
[0]) == pattern
.insn
[0])
1213 gdb_byte buf
[I386_MAX_MATCHED_INSN_LEN
- 1];
1214 int insn_matched
= 1;
1217 gdb_assert (pattern
.len
> 1);
1218 gdb_assert (pattern
.len
<= I386_MAX_MATCHED_INSN_LEN
);
1220 if (target_read_memory (pc
+ 1, buf
, pattern
.len
- 1))
1223 for (i
= 1; i
< pattern
.len
; i
++)
1225 if ((buf
[i
- 1] & pattern
.mask
[i
]) != pattern
.insn
[i
])
1228 return insn_matched
;
1233 /* Search for the instruction at PC in the list INSN_PATTERNS. Return
1234 the first instruction description that matches. Otherwise, return
1237 static struct i386_insn
*
1238 i386_match_insn (CORE_ADDR pc
, struct i386_insn
*insn_patterns
)
1240 struct i386_insn
*pattern
;
1242 for (pattern
= insn_patterns
; pattern
->len
> 0; pattern
++)
1244 if (i386_match_pattern (pc
, *pattern
))
1251 /* Return whether PC points inside a sequence of instructions that
1252 matches INSN_PATTERNS. */
1255 i386_match_insn_block (CORE_ADDR pc
, struct i386_insn
*insn_patterns
)
1257 CORE_ADDR current_pc
;
1259 struct i386_insn
*insn
;
1261 insn
= i386_match_insn (pc
, insn_patterns
);
1266 ix
= insn
- insn_patterns
;
1267 for (i
= ix
- 1; i
>= 0; i
--)
1269 current_pc
-= insn_patterns
[i
].len
;
1271 if (!i386_match_pattern (current_pc
, insn_patterns
[i
]))
1275 current_pc
= pc
+ insn
->len
;
1276 for (insn
= insn_patterns
+ ix
+ 1; insn
->len
> 0; insn
++)
1278 if (!i386_match_pattern (current_pc
, *insn
))
1281 current_pc
+= insn
->len
;
1287 /* Some special instructions that might be migrated by GCC into the
1288 part of the prologue that sets up the new stack frame. Because the
1289 stack frame hasn't been setup yet, no registers have been saved
1290 yet, and only the scratch registers %eax, %ecx and %edx can be
1293 struct i386_insn i386_frame_setup_skip_insns
[] =
1295 /* Check for `movb imm8, r' and `movl imm32, r'.
1297 ??? Should we handle 16-bit operand-sizes here? */
1299 /* `movb imm8, %al' and `movb imm8, %ah' */
1300 /* `movb imm8, %cl' and `movb imm8, %ch' */
1301 { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } },
1302 /* `movb imm8, %dl' and `movb imm8, %dh' */
1303 { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } },
1304 /* `movl imm32, %eax' and `movl imm32, %ecx' */
1305 { 5, { 0xb8 }, { 0xfe } },
1306 /* `movl imm32, %edx' */
1307 { 5, { 0xba }, { 0xff } },
1309 /* Check for `mov imm32, r32'. Note that there is an alternative
1310 encoding for `mov m32, %eax'.
1312 ??? Should we handle SIB adressing here?
1313 ??? Should we handle 16-bit operand-sizes here? */
1315 /* `movl m32, %eax' */
1316 { 5, { 0xa1 }, { 0xff } },
1317 /* `movl m32, %eax' and `mov; m32, %ecx' */
1318 { 6, { 0x89, 0x05 }, {0xff, 0xf7 } },
1319 /* `movl m32, %edx' */
1320 { 6, { 0x89, 0x15 }, {0xff, 0xff } },
1322 /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'.
1323 Because of the symmetry, there are actually two ways to encode
1324 these instructions; opcode bytes 0x29 and 0x2b for `subl' and
1325 opcode bytes 0x31 and 0x33 for `xorl'. */
1327 /* `subl %eax, %eax' */
1328 { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } },
1329 /* `subl %ecx, %ecx' */
1330 { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } },
1331 /* `subl %edx, %edx' */
1332 { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } },
1333 /* `xorl %eax, %eax' */
1334 { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } },
1335 /* `xorl %ecx, %ecx' */
1336 { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } },
1337 /* `xorl %edx, %edx' */
1338 { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } },
1343 /* Check whether PC points to a no-op instruction. */
1345 i386_skip_noop (CORE_ADDR pc
)
1350 if (target_read_memory (pc
, &op
, 1))
1356 /* Ignore `nop' instruction. */
1360 if (target_read_memory (pc
, &op
, 1))
1364 /* Ignore no-op instruction `mov %edi, %edi'.
1365 Microsoft system dlls often start with
1366 a `mov %edi,%edi' instruction.
1367 The 5 bytes before the function start are
1368 filled with `nop' instructions.
1369 This pattern can be used for hot-patching:
1370 The `mov %edi, %edi' instruction can be replaced by a
1371 near jump to the location of the 5 `nop' instructions
1372 which can be replaced by a 32-bit jump to anywhere
1373 in the 32-bit address space. */
1375 else if (op
== 0x8b)
1377 if (target_read_memory (pc
+ 1, &op
, 1))
1383 if (target_read_memory (pc
, &op
, 1))
1393 /* Check whether PC points at a code that sets up a new stack frame.
1394 If so, it updates CACHE and returns the address of the first
1395 instruction after the sequence that sets up the frame or LIMIT,
1396 whichever is smaller. If we don't recognize the code, return PC. */
1399 i386_analyze_frame_setup (struct gdbarch
*gdbarch
,
1400 CORE_ADDR pc
, CORE_ADDR limit
,
1401 struct i386_frame_cache
*cache
)
1403 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1404 struct i386_insn
*insn
;
1411 if (target_read_memory (pc
, &op
, 1))
1414 if (op
== 0x55) /* pushl %ebp */
1416 /* Take into account that we've executed the `pushl %ebp' that
1417 starts this instruction sequence. */
1418 cache
->saved_regs
[I386_EBP_REGNUM
] = 0;
1419 cache
->sp_offset
+= 4;
1422 /* If that's all, return now. */
1426 /* Check for some special instructions that might be migrated by
1427 GCC into the prologue and skip them. At this point in the
1428 prologue, code should only touch the scratch registers %eax,
1429 %ecx and %edx, so while the number of posibilities is sheer,
1432 Make sure we only skip these instructions if we later see the
1433 `movl %esp, %ebp' that actually sets up the frame. */
1434 while (pc
+ skip
< limit
)
1436 insn
= i386_match_insn (pc
+ skip
, i386_frame_setup_skip_insns
);
1443 /* If that's all, return now. */
1444 if (limit
<= pc
+ skip
)
1447 if (target_read_memory (pc
+ skip
, &op
, 1))
1450 /* The i386 prologue looks like
1456 and a different prologue can be generated for atom.
1460 lea -0x10(%esp),%esp
1462 We handle both of them here. */
1466 /* Check for `movl %esp, %ebp' -- can be written in two ways. */
1468 if (read_memory_unsigned_integer (pc
+ skip
+ 1, 1, byte_order
)
1474 if (read_memory_unsigned_integer (pc
+ skip
+ 1, 1, byte_order
)
1479 case 0x8d: /* Check for 'lea (%ebp), %ebp'. */
1480 if (read_memory_unsigned_integer (pc
+ skip
+ 1, 2, byte_order
)
1489 /* OK, we actually have a frame. We just don't know how large
1490 it is yet. Set its size to zero. We'll adjust it if
1491 necessary. We also now commit to skipping the special
1492 instructions mentioned before. */
1495 /* If that's all, return now. */
1499 /* Check for stack adjustment
1505 NOTE: You can't subtract a 16-bit immediate from a 32-bit
1506 reg, so we don't have to worry about a data16 prefix. */
1507 if (target_read_memory (pc
, &op
, 1))
1511 /* `subl' with 8-bit immediate. */
1512 if (read_memory_unsigned_integer (pc
+ 1, 1, byte_order
) != 0xec)
1513 /* Some instruction starting with 0x83 other than `subl'. */
1516 /* `subl' with signed 8-bit immediate (though it wouldn't
1517 make sense to be negative). */
1518 cache
->locals
= read_memory_integer (pc
+ 2, 1, byte_order
);
1521 else if (op
== 0x81)
1523 /* Maybe it is `subl' with a 32-bit immediate. */
1524 if (read_memory_unsigned_integer (pc
+ 1, 1, byte_order
) != 0xec)
1525 /* Some instruction starting with 0x81 other than `subl'. */
1528 /* It is `subl' with a 32-bit immediate. */
1529 cache
->locals
= read_memory_integer (pc
+ 2, 4, byte_order
);
1532 else if (op
== 0x8d)
1534 /* The ModR/M byte is 0x64. */
1535 if (read_memory_unsigned_integer (pc
+ 1, 1, byte_order
) != 0x64)
1537 /* 'lea' with 8-bit displacement. */
1538 cache
->locals
= -1 * read_memory_integer (pc
+ 3, 1, byte_order
);
1543 /* Some instruction other than `subl' nor 'lea'. */
1547 else if (op
== 0xc8) /* enter */
1549 cache
->locals
= read_memory_unsigned_integer (pc
+ 1, 2, byte_order
);
1556 /* Check whether PC points at code that saves registers on the stack.
1557 If so, it updates CACHE and returns the address of the first
1558 instruction after the register saves or CURRENT_PC, whichever is
1559 smaller. Otherwise, return PC. */
1562 i386_analyze_register_saves (CORE_ADDR pc
, CORE_ADDR current_pc
,
1563 struct i386_frame_cache
*cache
)
1565 CORE_ADDR offset
= 0;
1569 if (cache
->locals
> 0)
1570 offset
-= cache
->locals
;
1571 for (i
= 0; i
< 8 && pc
< current_pc
; i
++)
1573 if (target_read_memory (pc
, &op
, 1))
1575 if (op
< 0x50 || op
> 0x57)
1579 cache
->saved_regs
[op
- 0x50] = offset
;
1580 cache
->sp_offset
+= 4;
1587 /* Do a full analysis of the prologue at PC and update CACHE
1588 accordingly. Bail out early if CURRENT_PC is reached. Return the
1589 address where the analysis stopped.
1591 We handle these cases:
1593 The startup sequence can be at the start of the function, or the
1594 function can start with a branch to startup code at the end.
1596 %ebp can be set up with either the 'enter' instruction, or "pushl
1597 %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was
1598 once used in the System V compiler).
1600 Local space is allocated just below the saved %ebp by either the
1601 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a
1602 16-bit unsigned argument for space to allocate, and the 'addl'
1603 instruction could have either a signed byte, or 32-bit immediate.
1605 Next, the registers used by this function are pushed. With the
1606 System V compiler they will always be in the order: %edi, %esi,
1607 %ebx (and sometimes a harmless bug causes it to also save but not
1608 restore %eax); however, the code below is willing to see the pushes
1609 in any order, and will handle up to 8 of them.
1611 If the setup sequence is at the end of the function, then the next
1612 instruction will be a branch back to the start. */
1615 i386_analyze_prologue (struct gdbarch
*gdbarch
,
1616 CORE_ADDR pc
, CORE_ADDR current_pc
,
1617 struct i386_frame_cache
*cache
)
1619 pc
= i386_skip_noop (pc
);
1620 pc
= i386_follow_jump (gdbarch
, pc
);
1621 pc
= i386_analyze_struct_return (pc
, current_pc
, cache
);
1622 pc
= i386_skip_probe (pc
);
1623 pc
= i386_analyze_stack_align (pc
, current_pc
, cache
);
1624 pc
= i386_analyze_frame_setup (gdbarch
, pc
, current_pc
, cache
);
1625 return i386_analyze_register_saves (pc
, current_pc
, cache
);
1628 /* Return PC of first real instruction. */
1631 i386_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
1633 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1635 static gdb_byte pic_pat
[6] =
1637 0xe8, 0, 0, 0, 0, /* call 0x0 */
1638 0x5b, /* popl %ebx */
1640 struct i386_frame_cache cache
;
1644 CORE_ADDR func_addr
;
1646 if (find_pc_partial_function (start_pc
, NULL
, &func_addr
, NULL
))
1648 CORE_ADDR post_prologue_pc
1649 = skip_prologue_using_sal (gdbarch
, func_addr
);
1650 struct symtab
*s
= find_pc_symtab (func_addr
);
1652 /* Clang always emits a line note before the prologue and another
1653 one after. We trust clang to emit usable line notes. */
1654 if (post_prologue_pc
1656 && s
->producer
!= NULL
1657 && strncmp (s
->producer
, "clang ", sizeof ("clang ") - 1) == 0))
1658 return max (start_pc
, post_prologue_pc
);
1662 pc
= i386_analyze_prologue (gdbarch
, start_pc
, 0xffffffff, &cache
);
1663 if (cache
.locals
< 0)
1666 /* Found valid frame setup. */
1668 /* The native cc on SVR4 in -K PIC mode inserts the following code
1669 to get the address of the global offset table (GOT) into register
1674 movl %ebx,x(%ebp) (optional)
1677 This code is with the rest of the prologue (at the end of the
1678 function), so we have to skip it to get to the first real
1679 instruction at the start of the function. */
1681 for (i
= 0; i
< 6; i
++)
1683 if (target_read_memory (pc
+ i
, &op
, 1))
1686 if (pic_pat
[i
] != op
)
1693 if (target_read_memory (pc
+ delta
, &op
, 1))
1696 if (op
== 0x89) /* movl %ebx, x(%ebp) */
1698 op
= read_memory_unsigned_integer (pc
+ delta
+ 1, 1, byte_order
);
1700 if (op
== 0x5d) /* One byte offset from %ebp. */
1702 else if (op
== 0x9d) /* Four byte offset from %ebp. */
1704 else /* Unexpected instruction. */
1707 if (target_read_memory (pc
+ delta
, &op
, 1))
1712 if (delta
> 0 && op
== 0x81
1713 && read_memory_unsigned_integer (pc
+ delta
+ 1, 1, byte_order
)
1720 /* If the function starts with a branch (to startup code at the end)
1721 the last instruction should bring us back to the first
1722 instruction of the real code. */
1723 if (i386_follow_jump (gdbarch
, start_pc
) != start_pc
)
1724 pc
= i386_follow_jump (gdbarch
, pc
);
1729 /* Check that the code pointed to by PC corresponds to a call to
1730 __main, skip it if so. Return PC otherwise. */
1733 i386_skip_main_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1735 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1738 if (target_read_memory (pc
, &op
, 1))
1744 if (target_read_memory (pc
+ 1, buf
, sizeof buf
) == 0)
1746 /* Make sure address is computed correctly as a 32bit
1747 integer even if CORE_ADDR is 64 bit wide. */
1748 struct bound_minimal_symbol s
;
1749 CORE_ADDR call_dest
;
1751 call_dest
= pc
+ 5 + extract_signed_integer (buf
, 4, byte_order
);
1752 call_dest
= call_dest
& 0xffffffffU
;
1753 s
= lookup_minimal_symbol_by_pc (call_dest
);
1754 if (s
.minsym
!= NULL
1755 && SYMBOL_LINKAGE_NAME (s
.minsym
) != NULL
1756 && strcmp (SYMBOL_LINKAGE_NAME (s
.minsym
), "__main") == 0)
1764 /* This function is 64-bit safe. */
1767 i386_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1771 frame_unwind_register (next_frame
, gdbarch_pc_regnum (gdbarch
), buf
);
1772 return extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
1776 /* Normal frames. */
1779 i386_frame_cache_1 (struct frame_info
*this_frame
,
1780 struct i386_frame_cache
*cache
)
1782 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1783 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1787 cache
->pc
= get_frame_func (this_frame
);
1789 /* In principle, for normal frames, %ebp holds the frame pointer,
1790 which holds the base address for the current stack frame.
1791 However, for functions that don't need it, the frame pointer is
1792 optional. For these "frameless" functions the frame pointer is
1793 actually the frame pointer of the calling frame. Signal
1794 trampolines are just a special case of a "frameless" function.
1795 They (usually) share their frame pointer with the frame that was
1796 in progress when the signal occurred. */
1798 get_frame_register (this_frame
, I386_EBP_REGNUM
, buf
);
1799 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
);
1800 if (cache
->base
== 0)
1806 /* For normal frames, %eip is stored at 4(%ebp). */
1807 cache
->saved_regs
[I386_EIP_REGNUM
] = 4;
1810 i386_analyze_prologue (gdbarch
, cache
->pc
, get_frame_pc (this_frame
),
1813 if (cache
->locals
< 0)
1815 /* We didn't find a valid frame, which means that CACHE->base
1816 currently holds the frame pointer for our calling frame. If
1817 we're at the start of a function, or somewhere half-way its
1818 prologue, the function's frame probably hasn't been fully
1819 setup yet. Try to reconstruct the base address for the stack
1820 frame by looking at the stack pointer. For truly "frameless"
1821 functions this might work too. */
1823 if (cache
->saved_sp_reg
!= -1)
1825 /* Saved stack pointer has been saved. */
1826 get_frame_register (this_frame
, cache
->saved_sp_reg
, buf
);
1827 cache
->saved_sp
= extract_unsigned_integer (buf
, 4, byte_order
);
1829 /* We're halfway aligning the stack. */
1830 cache
->base
= ((cache
->saved_sp
- 4) & 0xfffffff0) - 4;
1831 cache
->saved_regs
[I386_EIP_REGNUM
] = cache
->saved_sp
- 4;
1833 /* This will be added back below. */
1834 cache
->saved_regs
[I386_EIP_REGNUM
] -= cache
->base
;
1836 else if (cache
->pc
!= 0
1837 || target_read_memory (get_frame_pc (this_frame
), buf
, 1))
1839 /* We're in a known function, but did not find a frame
1840 setup. Assume that the function does not use %ebp.
1841 Alternatively, we may have jumped to an invalid
1842 address; in that case there is definitely no new
1844 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
1845 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
)
1849 /* We're in an unknown function. We could not find the start
1850 of the function to analyze the prologue; our best option is
1851 to assume a typical frame layout with the caller's %ebp
1853 cache
->saved_regs
[I386_EBP_REGNUM
] = 0;
1856 if (cache
->saved_sp_reg
!= -1)
1858 /* Saved stack pointer has been saved (but the SAVED_SP_REG
1859 register may be unavailable). */
1860 if (cache
->saved_sp
== 0
1861 && deprecated_frame_register_read (this_frame
,
1862 cache
->saved_sp_reg
, buf
))
1863 cache
->saved_sp
= extract_unsigned_integer (buf
, 4, byte_order
);
1865 /* Now that we have the base address for the stack frame we can
1866 calculate the value of %esp in the calling frame. */
1867 else if (cache
->saved_sp
== 0)
1868 cache
->saved_sp
= cache
->base
+ 8;
1870 /* Adjust all the saved registers such that they contain addresses
1871 instead of offsets. */
1872 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
1873 if (cache
->saved_regs
[i
] != -1)
1874 cache
->saved_regs
[i
] += cache
->base
;
1879 static struct i386_frame_cache
*
1880 i386_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1882 volatile struct gdb_exception ex
;
1883 struct i386_frame_cache
*cache
;
1888 cache
= i386_alloc_frame_cache ();
1889 *this_cache
= cache
;
1891 TRY_CATCH (ex
, RETURN_MASK_ERROR
)
1893 i386_frame_cache_1 (this_frame
, cache
);
1895 if (ex
.reason
< 0 && ex
.error
!= NOT_AVAILABLE_ERROR
)
1896 throw_exception (ex
);
1902 i386_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
1903 struct frame_id
*this_id
)
1905 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1907 /* This marks the outermost frame. */
1908 if (cache
->base
== 0)
1911 /* See the end of i386_push_dummy_call. */
1912 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
1915 static enum unwind_stop_reason
1916 i386_frame_unwind_stop_reason (struct frame_info
*this_frame
,
1919 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1922 return UNWIND_UNAVAILABLE
;
1924 /* This marks the outermost frame. */
1925 if (cache
->base
== 0)
1926 return UNWIND_OUTERMOST
;
1928 return UNWIND_NO_REASON
;
1931 static struct value
*
1932 i386_frame_prev_register (struct frame_info
*this_frame
, void **this_cache
,
1935 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1937 gdb_assert (regnum
>= 0);
1939 /* The System V ABI says that:
1941 "The flags register contains the system flags, such as the
1942 direction flag and the carry flag. The direction flag must be
1943 set to the forward (that is, zero) direction before entry and
1944 upon exit from a function. Other user flags have no specified
1945 role in the standard calling sequence and are not preserved."
1947 To guarantee the "upon exit" part of that statement we fake a
1948 saved flags register that has its direction flag cleared.
1950 Note that GCC doesn't seem to rely on the fact that the direction
1951 flag is cleared after a function return; it always explicitly
1952 clears the flag before operations where it matters.
1954 FIXME: kettenis/20030316: I'm not quite sure whether this is the
1955 right thing to do. The way we fake the flags register here makes
1956 it impossible to change it. */
1958 if (regnum
== I386_EFLAGS_REGNUM
)
1962 val
= get_frame_register_unsigned (this_frame
, regnum
);
1964 return frame_unwind_got_constant (this_frame
, regnum
, val
);
1967 if (regnum
== I386_EIP_REGNUM
&& cache
->pc_in_eax
)
1968 return frame_unwind_got_register (this_frame
, regnum
, I386_EAX_REGNUM
);
1970 if (regnum
== I386_ESP_REGNUM
1971 && (cache
->saved_sp
!= 0 || cache
->saved_sp_reg
!= -1))
1973 /* If the SP has been saved, but we don't know where, then this
1974 means that SAVED_SP_REG register was found unavailable back
1975 when we built the cache. */
1976 if (cache
->saved_sp
== 0)
1977 return frame_unwind_got_register (this_frame
, regnum
,
1978 cache
->saved_sp_reg
);
1980 return frame_unwind_got_constant (this_frame
, regnum
,
1984 if (regnum
< I386_NUM_SAVED_REGS
&& cache
->saved_regs
[regnum
] != -1)
1985 return frame_unwind_got_memory (this_frame
, regnum
,
1986 cache
->saved_regs
[regnum
]);
1988 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
1991 static const struct frame_unwind i386_frame_unwind
=
1994 i386_frame_unwind_stop_reason
,
1996 i386_frame_prev_register
,
1998 default_frame_sniffer
2001 /* Normal frames, but in a function epilogue. */
2003 /* The epilogue is defined here as the 'ret' instruction, which will
2004 follow any instruction such as 'leave' or 'pop %ebp' that destroys
2005 the function's stack frame. */
2008 i386_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2011 struct symtab
*symtab
;
2013 symtab
= find_pc_symtab (pc
);
2014 if (symtab
&& symtab
->epilogue_unwind_valid
)
2017 if (target_read_memory (pc
, &insn
, 1))
2018 return 0; /* Can't read memory at pc. */
2020 if (insn
!= 0xc3) /* 'ret' instruction. */
2027 i386_epilogue_frame_sniffer (const struct frame_unwind
*self
,
2028 struct frame_info
*this_frame
,
2029 void **this_prologue_cache
)
2031 if (frame_relative_level (this_frame
) == 0)
2032 return i386_in_function_epilogue_p (get_frame_arch (this_frame
),
2033 get_frame_pc (this_frame
));
2038 static struct i386_frame_cache
*
2039 i386_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2041 volatile struct gdb_exception ex
;
2042 struct i386_frame_cache
*cache
;
2048 cache
= i386_alloc_frame_cache ();
2049 *this_cache
= cache
;
2051 TRY_CATCH (ex
, RETURN_MASK_ERROR
)
2053 cache
->pc
= get_frame_func (this_frame
);
2055 /* At this point the stack looks as if we just entered the
2056 function, with the return address at the top of the
2058 sp
= get_frame_register_unsigned (this_frame
, I386_ESP_REGNUM
);
2059 cache
->base
= sp
+ cache
->sp_offset
;
2060 cache
->saved_sp
= cache
->base
+ 8;
2061 cache
->saved_regs
[I386_EIP_REGNUM
] = cache
->base
+ 4;
2065 if (ex
.reason
< 0 && ex
.error
!= NOT_AVAILABLE_ERROR
)
2066 throw_exception (ex
);
2071 static enum unwind_stop_reason
2072 i386_epilogue_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2075 struct i386_frame_cache
*cache
=
2076 i386_epilogue_frame_cache (this_frame
, this_cache
);
2079 return UNWIND_UNAVAILABLE
;
2081 return UNWIND_NO_REASON
;
2085 i386_epilogue_frame_this_id (struct frame_info
*this_frame
,
2087 struct frame_id
*this_id
)
2089 struct i386_frame_cache
*cache
=
2090 i386_epilogue_frame_cache (this_frame
, this_cache
);
2095 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
2098 static struct value
*
2099 i386_epilogue_frame_prev_register (struct frame_info
*this_frame
,
2100 void **this_cache
, int regnum
)
2102 /* Make sure we've initialized the cache. */
2103 i386_epilogue_frame_cache (this_frame
, this_cache
);
2105 return i386_frame_prev_register (this_frame
, this_cache
, regnum
);
2108 static const struct frame_unwind i386_epilogue_frame_unwind
=
2111 i386_epilogue_frame_unwind_stop_reason
,
2112 i386_epilogue_frame_this_id
,
2113 i386_epilogue_frame_prev_register
,
2115 i386_epilogue_frame_sniffer
2119 /* Stack-based trampolines. */
2121 /* These trampolines are used on cross x86 targets, when taking the
2122 address of a nested function. When executing these trampolines,
2123 no stack frame is set up, so we are in a similar situation as in
2124 epilogues and i386_epilogue_frame_this_id can be re-used. */
2126 /* Static chain passed in register. */
2128 struct i386_insn i386_tramp_chain_in_reg_insns
[] =
2130 /* `movl imm32, %eax' and `movl imm32, %ecx' */
2131 { 5, { 0xb8 }, { 0xfe } },
2134 { 5, { 0xe9 }, { 0xff } },
2139 /* Static chain passed on stack (when regparm=3). */
2141 struct i386_insn i386_tramp_chain_on_stack_insns
[] =
2144 { 5, { 0x68 }, { 0xff } },
2147 { 5, { 0xe9 }, { 0xff } },
2152 /* Return whether PC points inside a stack trampoline. */
2155 i386_in_stack_tramp_p (CORE_ADDR pc
)
2160 /* A stack trampoline is detected if no name is associated
2161 to the current pc and if it points inside a trampoline
2164 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
2168 if (target_read_memory (pc
, &insn
, 1))
2171 if (!i386_match_insn_block (pc
, i386_tramp_chain_in_reg_insns
)
2172 && !i386_match_insn_block (pc
, i386_tramp_chain_on_stack_insns
))
2179 i386_stack_tramp_frame_sniffer (const struct frame_unwind
*self
,
2180 struct frame_info
*this_frame
,
2183 if (frame_relative_level (this_frame
) == 0)
2184 return i386_in_stack_tramp_p (get_frame_pc (this_frame
));
2189 static const struct frame_unwind i386_stack_tramp_frame_unwind
=
2192 i386_epilogue_frame_unwind_stop_reason
,
2193 i386_epilogue_frame_this_id
,
2194 i386_epilogue_frame_prev_register
,
2196 i386_stack_tramp_frame_sniffer
2199 /* Generate a bytecode expression to get the value of the saved PC. */
2202 i386_gen_return_address (struct gdbarch
*gdbarch
,
2203 struct agent_expr
*ax
, struct axs_value
*value
,
2206 /* The following sequence assumes the traditional use of the base
2208 ax_reg (ax
, I386_EBP_REGNUM
);
2210 ax_simple (ax
, aop_add
);
2211 value
->type
= register_type (gdbarch
, I386_EIP_REGNUM
);
2212 value
->kind
= axs_lvalue_memory
;
2216 /* Signal trampolines. */
2218 static struct i386_frame_cache
*
2219 i386_sigtramp_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2221 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2222 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2223 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2224 volatile struct gdb_exception ex
;
2225 struct i386_frame_cache
*cache
;
2232 cache
= i386_alloc_frame_cache ();
2234 TRY_CATCH (ex
, RETURN_MASK_ERROR
)
2236 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
2237 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
) - 4;
2239 addr
= tdep
->sigcontext_addr (this_frame
);
2240 if (tdep
->sc_reg_offset
)
2244 gdb_assert (tdep
->sc_num_regs
<= I386_NUM_SAVED_REGS
);
2246 for (i
= 0; i
< tdep
->sc_num_regs
; i
++)
2247 if (tdep
->sc_reg_offset
[i
] != -1)
2248 cache
->saved_regs
[i
] = addr
+ tdep
->sc_reg_offset
[i
];
2252 cache
->saved_regs
[I386_EIP_REGNUM
] = addr
+ tdep
->sc_pc_offset
;
2253 cache
->saved_regs
[I386_ESP_REGNUM
] = addr
+ tdep
->sc_sp_offset
;
2258 if (ex
.reason
< 0 && ex
.error
!= NOT_AVAILABLE_ERROR
)
2259 throw_exception (ex
);
2261 *this_cache
= cache
;
2265 static enum unwind_stop_reason
2266 i386_sigtramp_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2269 struct i386_frame_cache
*cache
=
2270 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2273 return UNWIND_UNAVAILABLE
;
2275 return UNWIND_NO_REASON
;
2279 i386_sigtramp_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2280 struct frame_id
*this_id
)
2282 struct i386_frame_cache
*cache
=
2283 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2288 /* See the end of i386_push_dummy_call. */
2289 (*this_id
) = frame_id_build (cache
->base
+ 8, get_frame_pc (this_frame
));
2292 static struct value
*
2293 i386_sigtramp_frame_prev_register (struct frame_info
*this_frame
,
2294 void **this_cache
, int regnum
)
2296 /* Make sure we've initialized the cache. */
2297 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2299 return i386_frame_prev_register (this_frame
, this_cache
, regnum
);
2303 i386_sigtramp_frame_sniffer (const struct frame_unwind
*self
,
2304 struct frame_info
*this_frame
,
2305 void **this_prologue_cache
)
2307 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (this_frame
));
2309 /* We shouldn't even bother if we don't have a sigcontext_addr
2311 if (tdep
->sigcontext_addr
== NULL
)
2314 if (tdep
->sigtramp_p
!= NULL
)
2316 if (tdep
->sigtramp_p (this_frame
))
2320 if (tdep
->sigtramp_start
!= 0)
2322 CORE_ADDR pc
= get_frame_pc (this_frame
);
2324 gdb_assert (tdep
->sigtramp_end
!= 0);
2325 if (pc
>= tdep
->sigtramp_start
&& pc
< tdep
->sigtramp_end
)
2332 static const struct frame_unwind i386_sigtramp_frame_unwind
=
2335 i386_sigtramp_frame_unwind_stop_reason
,
2336 i386_sigtramp_frame_this_id
,
2337 i386_sigtramp_frame_prev_register
,
2339 i386_sigtramp_frame_sniffer
2344 i386_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
2346 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
2351 static const struct frame_base i386_frame_base
=
2354 i386_frame_base_address
,
2355 i386_frame_base_address
,
2356 i386_frame_base_address
2359 static struct frame_id
2360 i386_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
2364 fp
= get_frame_register_unsigned (this_frame
, I386_EBP_REGNUM
);
2366 /* See the end of i386_push_dummy_call. */
2367 return frame_id_build (fp
+ 8, get_frame_pc (this_frame
));
2370 /* _Decimal128 function return values need 16-byte alignment on the
2374 i386_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
2376 return sp
& -(CORE_ADDR
)16;
2380 /* Figure out where the longjmp will land. Slurp the args out of the
2381 stack. We expect the first arg to be a pointer to the jmp_buf
2382 structure from which we extract the address that we will land at.
2383 This address is copied into PC. This routine returns non-zero on
2387 i386_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
2390 CORE_ADDR sp
, jb_addr
;
2391 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2392 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2393 int jb_pc_offset
= gdbarch_tdep (gdbarch
)->jb_pc_offset
;
2395 /* If JB_PC_OFFSET is -1, we have no way to find out where the
2396 longjmp will land. */
2397 if (jb_pc_offset
== -1)
2400 get_frame_register (frame
, I386_ESP_REGNUM
, buf
);
2401 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
2402 if (target_read_memory (sp
+ 4, buf
, 4))
2405 jb_addr
= extract_unsigned_integer (buf
, 4, byte_order
);
2406 if (target_read_memory (jb_addr
+ jb_pc_offset
, buf
, 4))
2409 *pc
= extract_unsigned_integer (buf
, 4, byte_order
);
2414 /* Check whether TYPE must be 16-byte-aligned when passed as a
2415 function argument. 16-byte vectors, _Decimal128 and structures or
2416 unions containing such types must be 16-byte-aligned; other
2417 arguments are 4-byte-aligned. */
2420 i386_16_byte_align_p (struct type
*type
)
2422 type
= check_typedef (type
);
2423 if ((TYPE_CODE (type
) == TYPE_CODE_DECFLOAT
2424 || (TYPE_CODE (type
) == TYPE_CODE_ARRAY
&& TYPE_VECTOR (type
)))
2425 && TYPE_LENGTH (type
) == 16)
2427 if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
2428 return i386_16_byte_align_p (TYPE_TARGET_TYPE (type
));
2429 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
2430 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
2433 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
2435 if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type
, i
)))
2442 /* Implementation for set_gdbarch_push_dummy_code. */
2445 i386_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
, CORE_ADDR funaddr
,
2446 struct value
**args
, int nargs
, struct type
*value_type
,
2447 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
,
2448 struct regcache
*regcache
)
2450 /* Use 0xcc breakpoint - 1 byte. */
2454 /* Keep the stack aligned. */
2459 i386_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2460 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
2461 struct value
**args
, CORE_ADDR sp
, int struct_return
,
2462 CORE_ADDR struct_addr
)
2464 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2470 /* Determine the total space required for arguments and struct
2471 return address in a first pass (allowing for 16-byte-aligned
2472 arguments), then push arguments in a second pass. */
2474 for (write_pass
= 0; write_pass
< 2; write_pass
++)
2476 int args_space_used
= 0;
2482 /* Push value address. */
2483 store_unsigned_integer (buf
, 4, byte_order
, struct_addr
);
2484 write_memory (sp
, buf
, 4);
2485 args_space_used
+= 4;
2491 for (i
= 0; i
< nargs
; i
++)
2493 int len
= TYPE_LENGTH (value_enclosing_type (args
[i
]));
2497 if (i386_16_byte_align_p (value_enclosing_type (args
[i
])))
2498 args_space_used
= align_up (args_space_used
, 16);
2500 write_memory (sp
+ args_space_used
,
2501 value_contents_all (args
[i
]), len
);
2502 /* The System V ABI says that:
2504 "An argument's size is increased, if necessary, to make it a
2505 multiple of [32-bit] words. This may require tail padding,
2506 depending on the size of the argument."
2508 This makes sure the stack stays word-aligned. */
2509 args_space_used
+= align_up (len
, 4);
2513 if (i386_16_byte_align_p (value_enclosing_type (args
[i
])))
2514 args_space
= align_up (args_space
, 16);
2515 args_space
+= align_up (len
, 4);
2523 /* The original System V ABI only requires word alignment,
2524 but modern incarnations need 16-byte alignment in order
2525 to support SSE. Since wasting a few bytes here isn't
2526 harmful we unconditionally enforce 16-byte alignment. */
2531 /* Store return address. */
2533 store_unsigned_integer (buf
, 4, byte_order
, bp_addr
);
2534 write_memory (sp
, buf
, 4);
2536 /* Finally, update the stack pointer... */
2537 store_unsigned_integer (buf
, 4, byte_order
, sp
);
2538 regcache_cooked_write (regcache
, I386_ESP_REGNUM
, buf
);
2540 /* ...and fake a frame pointer. */
2541 regcache_cooked_write (regcache
, I386_EBP_REGNUM
, buf
);
2543 /* MarkK wrote: This "+ 8" is all over the place:
2544 (i386_frame_this_id, i386_sigtramp_frame_this_id,
2545 i386_dummy_id). It's there, since all frame unwinders for
2546 a given target have to agree (within a certain margin) on the
2547 definition of the stack address of a frame. Otherwise frame id
2548 comparison might not work correctly. Since DWARF2/GCC uses the
2549 stack address *before* the function call as a frame's CFA. On
2550 the i386, when %ebp is used as a frame pointer, the offset
2551 between the contents %ebp and the CFA as defined by GCC. */
2555 /* These registers are used for returning integers (and on some
2556 targets also for returning `struct' and `union' values when their
2557 size and alignment match an integer type). */
2558 #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */
2559 #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */
2561 /* Read, for architecture GDBARCH, a function return value of TYPE
2562 from REGCACHE, and copy that into VALBUF. */
2565 i386_extract_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
2566 struct regcache
*regcache
, gdb_byte
*valbuf
)
2568 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2569 int len
= TYPE_LENGTH (type
);
2570 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
2572 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2574 if (tdep
->st0_regnum
< 0)
2576 warning (_("Cannot find floating-point return value."));
2577 memset (valbuf
, 0, len
);
2581 /* Floating-point return values can be found in %st(0). Convert
2582 its contents to the desired type. This is probably not
2583 exactly how it would happen on the target itself, but it is
2584 the best we can do. */
2585 regcache_raw_read (regcache
, I386_ST0_REGNUM
, buf
);
2586 convert_typed_floating (buf
, i387_ext_type (gdbarch
), valbuf
, type
);
2590 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
2591 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
2593 if (len
<= low_size
)
2595 regcache_raw_read (regcache
, LOW_RETURN_REGNUM
, buf
);
2596 memcpy (valbuf
, buf
, len
);
2598 else if (len
<= (low_size
+ high_size
))
2600 regcache_raw_read (regcache
, LOW_RETURN_REGNUM
, buf
);
2601 memcpy (valbuf
, buf
, low_size
);
2602 regcache_raw_read (regcache
, HIGH_RETURN_REGNUM
, buf
);
2603 memcpy (valbuf
+ low_size
, buf
, len
- low_size
);
2606 internal_error (__FILE__
, __LINE__
,
2607 _("Cannot extract return value of %d bytes long."),
2612 /* Write, for architecture GDBARCH, a function return value of TYPE
2613 from VALBUF into REGCACHE. */
2616 i386_store_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
2617 struct regcache
*regcache
, const gdb_byte
*valbuf
)
2619 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2620 int len
= TYPE_LENGTH (type
);
2622 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2625 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
2627 if (tdep
->st0_regnum
< 0)
2629 warning (_("Cannot set floating-point return value."));
2633 /* Returning floating-point values is a bit tricky. Apart from
2634 storing the return value in %st(0), we have to simulate the
2635 state of the FPU at function return point. */
2637 /* Convert the value found in VALBUF to the extended
2638 floating-point format used by the FPU. This is probably
2639 not exactly how it would happen on the target itself, but
2640 it is the best we can do. */
2641 convert_typed_floating (valbuf
, type
, buf
, i387_ext_type (gdbarch
));
2642 regcache_raw_write (regcache
, I386_ST0_REGNUM
, buf
);
2644 /* Set the top of the floating-point register stack to 7. The
2645 actual value doesn't really matter, but 7 is what a normal
2646 function return would end up with if the program started out
2647 with a freshly initialized FPU. */
2648 regcache_raw_read_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), &fstat
);
2650 regcache_raw_write_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), fstat
);
2652 /* Mark %st(1) through %st(7) as empty. Since we set the top of
2653 the floating-point register stack to 7, the appropriate value
2654 for the tag word is 0x3fff. */
2655 regcache_raw_write_unsigned (regcache
, I387_FTAG_REGNUM (tdep
), 0x3fff);
2659 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
2660 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
2662 if (len
<= low_size
)
2663 regcache_raw_write_part (regcache
, LOW_RETURN_REGNUM
, 0, len
, valbuf
);
2664 else if (len
<= (low_size
+ high_size
))
2666 regcache_raw_write (regcache
, LOW_RETURN_REGNUM
, valbuf
);
2667 regcache_raw_write_part (regcache
, HIGH_RETURN_REGNUM
, 0,
2668 len
- low_size
, valbuf
+ low_size
);
2671 internal_error (__FILE__
, __LINE__
,
2672 _("Cannot store return value of %d bytes long."), len
);
2677 /* This is the variable that is set with "set struct-convention", and
2678 its legitimate values. */
2679 static const char default_struct_convention
[] = "default";
2680 static const char pcc_struct_convention
[] = "pcc";
2681 static const char reg_struct_convention
[] = "reg";
2682 static const char *const valid_conventions
[] =
2684 default_struct_convention
,
2685 pcc_struct_convention
,
2686 reg_struct_convention
,
2689 static const char *struct_convention
= default_struct_convention
;
2691 /* Return non-zero if TYPE, which is assumed to be a structure,
2692 a union type, or an array type, should be returned in registers
2693 for architecture GDBARCH. */
2696 i386_reg_struct_return_p (struct gdbarch
*gdbarch
, struct type
*type
)
2698 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2699 enum type_code code
= TYPE_CODE (type
);
2700 int len
= TYPE_LENGTH (type
);
2702 gdb_assert (code
== TYPE_CODE_STRUCT
2703 || code
== TYPE_CODE_UNION
2704 || code
== TYPE_CODE_ARRAY
);
2706 if (struct_convention
== pcc_struct_convention
2707 || (struct_convention
== default_struct_convention
2708 && tdep
->struct_return
== pcc_struct_return
))
2711 /* Structures consisting of a single `float', `double' or 'long
2712 double' member are returned in %st(0). */
2713 if (code
== TYPE_CODE_STRUCT
&& TYPE_NFIELDS (type
) == 1)
2715 type
= check_typedef (TYPE_FIELD_TYPE (type
, 0));
2716 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2717 return (len
== 4 || len
== 8 || len
== 12);
2720 return (len
== 1 || len
== 2 || len
== 4 || len
== 8);
2723 /* Determine, for architecture GDBARCH, how a return value of TYPE
2724 should be returned. If it is supposed to be returned in registers,
2725 and READBUF is non-zero, read the appropriate value from REGCACHE,
2726 and copy it into READBUF. If WRITEBUF is non-zero, write the value
2727 from WRITEBUF into REGCACHE. */
2729 static enum return_value_convention
2730 i386_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
2731 struct type
*type
, struct regcache
*regcache
,
2732 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2734 enum type_code code
= TYPE_CODE (type
);
2736 if (((code
== TYPE_CODE_STRUCT
2737 || code
== TYPE_CODE_UNION
2738 || code
== TYPE_CODE_ARRAY
)
2739 && !i386_reg_struct_return_p (gdbarch
, type
))
2740 /* Complex double and long double uses the struct return covention. */
2741 || (code
== TYPE_CODE_COMPLEX
&& TYPE_LENGTH (type
) == 16)
2742 || (code
== TYPE_CODE_COMPLEX
&& TYPE_LENGTH (type
) == 24)
2743 /* 128-bit decimal float uses the struct return convention. */
2744 || (code
== TYPE_CODE_DECFLOAT
&& TYPE_LENGTH (type
) == 16))
2746 /* The System V ABI says that:
2748 "A function that returns a structure or union also sets %eax
2749 to the value of the original address of the caller's area
2750 before it returns. Thus when the caller receives control
2751 again, the address of the returned object resides in register
2752 %eax and can be used to access the object."
2754 So the ABI guarantees that we can always find the return
2755 value just after the function has returned. */
2757 /* Note that the ABI doesn't mention functions returning arrays,
2758 which is something possible in certain languages such as Ada.
2759 In this case, the value is returned as if it was wrapped in
2760 a record, so the convention applied to records also applies
2767 regcache_raw_read_unsigned (regcache
, I386_EAX_REGNUM
, &addr
);
2768 read_memory (addr
, readbuf
, TYPE_LENGTH (type
));
2771 return RETURN_VALUE_ABI_RETURNS_ADDRESS
;
2774 /* This special case is for structures consisting of a single
2775 `float', `double' or 'long double' member. These structures are
2776 returned in %st(0). For these structures, we call ourselves
2777 recursively, changing TYPE into the type of the first member of
2778 the structure. Since that should work for all structures that
2779 have only one member, we don't bother to check the member's type
2781 if (code
== TYPE_CODE_STRUCT
&& TYPE_NFIELDS (type
) == 1)
2783 type
= check_typedef (TYPE_FIELD_TYPE (type
, 0));
2784 return i386_return_value (gdbarch
, function
, type
, regcache
,
2789 i386_extract_return_value (gdbarch
, type
, regcache
, readbuf
);
2791 i386_store_return_value (gdbarch
, type
, regcache
, writebuf
);
2793 return RETURN_VALUE_REGISTER_CONVENTION
;
2798 i387_ext_type (struct gdbarch
*gdbarch
)
2800 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2802 if (!tdep
->i387_ext_type
)
2804 tdep
->i387_ext_type
= tdesc_find_type (gdbarch
, "i387_ext");
2805 gdb_assert (tdep
->i387_ext_type
!= NULL
);
2808 return tdep
->i387_ext_type
;
2811 /* Construct type for pseudo BND registers. We can't use
2812 tdesc_find_type since a complement of one value has to be used
2813 to describe the upper bound. */
2815 static struct type
*
2816 i386_bnd_type (struct gdbarch
*gdbarch
)
2818 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2821 if (!tdep
->i386_bnd_type
)
2823 struct type
*t
, *bound_t
;
2824 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2826 /* The type we're building is described bellow: */
2831 void *ubound
; /* One complement of raw ubound field. */
2835 t
= arch_composite_type (gdbarch
,
2836 "__gdb_builtin_type_bound128", TYPE_CODE_STRUCT
);
2838 append_composite_type_field (t
, "lbound", bt
->builtin_data_ptr
);
2839 append_composite_type_field (t
, "ubound", bt
->builtin_data_ptr
);
2841 TYPE_NAME (t
) = "builtin_type_bound128";
2842 tdep
->i386_bnd_type
= t
;
2845 return tdep
->i386_bnd_type
;
2848 /* Construct vector type for pseudo YMM registers. We can't use
2849 tdesc_find_type since YMM isn't described in target description. */
2851 static struct type
*
2852 i386_ymm_type (struct gdbarch
*gdbarch
)
2854 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2856 if (!tdep
->i386_ymm_type
)
2858 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2860 /* The type we're building is this: */
2862 union __gdb_builtin_type_vec256i
2864 int128_t uint128
[2];
2865 int64_t v2_int64
[4];
2866 int32_t v4_int32
[8];
2867 int16_t v8_int16
[16];
2868 int8_t v16_int8
[32];
2869 double v2_double
[4];
2876 t
= arch_composite_type (gdbarch
,
2877 "__gdb_builtin_type_vec256i", TYPE_CODE_UNION
);
2878 append_composite_type_field (t
, "v8_float",
2879 init_vector_type (bt
->builtin_float
, 8));
2880 append_composite_type_field (t
, "v4_double",
2881 init_vector_type (bt
->builtin_double
, 4));
2882 append_composite_type_field (t
, "v32_int8",
2883 init_vector_type (bt
->builtin_int8
, 32));
2884 append_composite_type_field (t
, "v16_int16",
2885 init_vector_type (bt
->builtin_int16
, 16));
2886 append_composite_type_field (t
, "v8_int32",
2887 init_vector_type (bt
->builtin_int32
, 8));
2888 append_composite_type_field (t
, "v4_int64",
2889 init_vector_type (bt
->builtin_int64
, 4));
2890 append_composite_type_field (t
, "v2_int128",
2891 init_vector_type (bt
->builtin_int128
, 2));
2893 TYPE_VECTOR (t
) = 1;
2894 TYPE_NAME (t
) = "builtin_type_vec256i";
2895 tdep
->i386_ymm_type
= t
;
2898 return tdep
->i386_ymm_type
;
2901 /* Construct vector type for MMX registers. */
2902 static struct type
*
2903 i386_mmx_type (struct gdbarch
*gdbarch
)
2905 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2907 if (!tdep
->i386_mmx_type
)
2909 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2911 /* The type we're building is this: */
2913 union __gdb_builtin_type_vec64i
2916 int32_t v2_int32
[2];
2917 int16_t v4_int16
[4];
2924 t
= arch_composite_type (gdbarch
,
2925 "__gdb_builtin_type_vec64i", TYPE_CODE_UNION
);
2927 append_composite_type_field (t
, "uint64", bt
->builtin_int64
);
2928 append_composite_type_field (t
, "v2_int32",
2929 init_vector_type (bt
->builtin_int32
, 2));
2930 append_composite_type_field (t
, "v4_int16",
2931 init_vector_type (bt
->builtin_int16
, 4));
2932 append_composite_type_field (t
, "v8_int8",
2933 init_vector_type (bt
->builtin_int8
, 8));
2935 TYPE_VECTOR (t
) = 1;
2936 TYPE_NAME (t
) = "builtin_type_vec64i";
2937 tdep
->i386_mmx_type
= t
;
2940 return tdep
->i386_mmx_type
;
2943 /* Return the GDB type object for the "standard" data type of data in
2947 i386_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
2949 if (i386_bnd_regnum_p (gdbarch
, regnum
))
2950 return i386_bnd_type (gdbarch
);
2951 if (i386_mmx_regnum_p (gdbarch
, regnum
))
2952 return i386_mmx_type (gdbarch
);
2953 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
2954 return i386_ymm_type (gdbarch
);
2957 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2958 if (i386_byte_regnum_p (gdbarch
, regnum
))
2959 return bt
->builtin_int8
;
2960 else if (i386_word_regnum_p (gdbarch
, regnum
))
2961 return bt
->builtin_int16
;
2962 else if (i386_dword_regnum_p (gdbarch
, regnum
))
2963 return bt
->builtin_int32
;
2966 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
2969 /* Map a cooked register onto a raw register or memory. For the i386,
2970 the MMX registers need to be mapped onto floating point registers. */
2973 i386_mmx_regnum_to_fp_regnum (struct regcache
*regcache
, int regnum
)
2975 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_regcache_arch (regcache
));
2980 mmxreg
= regnum
- tdep
->mm0_regnum
;
2981 regcache_raw_read_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), &fstat
);
2982 tos
= (fstat
>> 11) & 0x7;
2983 fpreg
= (mmxreg
+ tos
) % 8;
2985 return (I387_ST0_REGNUM (tdep
) + fpreg
);
2988 /* A helper function for us by i386_pseudo_register_read_value and
2989 amd64_pseudo_register_read_value. It does all the work but reads
2990 the data into an already-allocated value. */
2993 i386_pseudo_register_read_into_value (struct gdbarch
*gdbarch
,
2994 struct regcache
*regcache
,
2996 struct value
*result_value
)
2998 gdb_byte raw_buf
[MAX_REGISTER_SIZE
];
2999 enum register_status status
;
3000 gdb_byte
*buf
= value_contents_raw (result_value
);
3002 if (i386_mmx_regnum_p (gdbarch
, regnum
))
3004 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
3006 /* Extract (always little endian). */
3007 status
= regcache_raw_read (regcache
, fpnum
, raw_buf
);
3008 if (status
!= REG_VALID
)
3009 mark_value_bytes_unavailable (result_value
, 0,
3010 TYPE_LENGTH (value_type (result_value
)));
3012 memcpy (buf
, raw_buf
, register_size (gdbarch
, regnum
));
3016 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3017 if (i386_bnd_regnum_p (gdbarch
, regnum
))
3019 regnum
-= tdep
->bnd0_regnum
;
3021 /* Extract (always little endian). Read lower 128bits. */
3022 status
= regcache_raw_read (regcache
,
3023 I387_BND0R_REGNUM (tdep
) + regnum
,
3025 if (status
!= REG_VALID
)
3026 mark_value_bytes_unavailable (result_value
, 0, 16);
3029 enum bfd_endian byte_order
= gdbarch_byte_order (target_gdbarch ());
3030 LONGEST upper
, lower
;
3031 int size
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_data_ptr
);
3033 lower
= extract_unsigned_integer (raw_buf
, 8, byte_order
);
3034 upper
= extract_unsigned_integer (raw_buf
+ 8, 8, byte_order
);
3037 memcpy (buf
, &lower
, size
);
3038 memcpy (buf
+ size
, &upper
, size
);
3041 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
3043 regnum
-= tdep
->ymm0_regnum
;
3045 /* Extract (always little endian). Read lower 128bits. */
3046 status
= regcache_raw_read (regcache
,
3047 I387_XMM0_REGNUM (tdep
) + regnum
,
3049 if (status
!= REG_VALID
)
3050 mark_value_bytes_unavailable (result_value
, 0, 16);
3052 memcpy (buf
, raw_buf
, 16);
3053 /* Read upper 128bits. */
3054 status
= regcache_raw_read (regcache
,
3055 tdep
->ymm0h_regnum
+ regnum
,
3057 if (status
!= REG_VALID
)
3058 mark_value_bytes_unavailable (result_value
, 16, 32);
3060 memcpy (buf
+ 16, raw_buf
, 16);
3062 else if (i386_word_regnum_p (gdbarch
, regnum
))
3064 int gpnum
= regnum
- tdep
->ax_regnum
;
3066 /* Extract (always little endian). */
3067 status
= regcache_raw_read (regcache
, gpnum
, raw_buf
);
3068 if (status
!= REG_VALID
)
3069 mark_value_bytes_unavailable (result_value
, 0,
3070 TYPE_LENGTH (value_type (result_value
)));
3072 memcpy (buf
, raw_buf
, 2);
3074 else if (i386_byte_regnum_p (gdbarch
, regnum
))
3076 /* Check byte pseudo registers last since this function will
3077 be called from amd64_pseudo_register_read, which handles
3078 byte pseudo registers differently. */
3079 int gpnum
= regnum
- tdep
->al_regnum
;
3081 /* Extract (always little endian). We read both lower and
3083 status
= regcache_raw_read (regcache
, gpnum
% 4, raw_buf
);
3084 if (status
!= REG_VALID
)
3085 mark_value_bytes_unavailable (result_value
, 0,
3086 TYPE_LENGTH (value_type (result_value
)));
3087 else if (gpnum
>= 4)
3088 memcpy (buf
, raw_buf
+ 1, 1);
3090 memcpy (buf
, raw_buf
, 1);
3093 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
3097 static struct value
*
3098 i386_pseudo_register_read_value (struct gdbarch
*gdbarch
,
3099 struct regcache
*regcache
,
3102 struct value
*result
;
3104 result
= allocate_value (register_type (gdbarch
, regnum
));
3105 VALUE_LVAL (result
) = lval_register
;
3106 VALUE_REGNUM (result
) = regnum
;
3108 i386_pseudo_register_read_into_value (gdbarch
, regcache
, regnum
, result
);
3114 i386_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
3115 int regnum
, const gdb_byte
*buf
)
3117 gdb_byte raw_buf
[MAX_REGISTER_SIZE
];
3119 if (i386_mmx_regnum_p (gdbarch
, regnum
))
3121 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
3124 regcache_raw_read (regcache
, fpnum
, raw_buf
);
3125 /* ... Modify ... (always little endian). */
3126 memcpy (raw_buf
, buf
, register_size (gdbarch
, regnum
));
3128 regcache_raw_write (regcache
, fpnum
, raw_buf
);
3132 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3134 if (i386_bnd_regnum_p (gdbarch
, regnum
))
3136 ULONGEST upper
, lower
;
3137 int size
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_data_ptr
);
3138 enum bfd_endian byte_order
= gdbarch_byte_order (target_gdbarch ());
3140 /* New values from input value. */
3141 regnum
-= tdep
->bnd0_regnum
;
3142 lower
= extract_unsigned_integer (buf
, size
, byte_order
);
3143 upper
= extract_unsigned_integer (buf
+ size
, size
, byte_order
);
3145 /* Fetching register buffer. */
3146 regcache_raw_read (regcache
,
3147 I387_BND0R_REGNUM (tdep
) + regnum
,
3152 /* Set register bits. */
3153 memcpy (raw_buf
, &lower
, 8);
3154 memcpy (raw_buf
+ 8, &upper
, 8);
3157 regcache_raw_write (regcache
,
3158 I387_BND0R_REGNUM (tdep
) + regnum
,
3161 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
3163 regnum
-= tdep
->ymm0_regnum
;
3165 /* ... Write lower 128bits. */
3166 regcache_raw_write (regcache
,
3167 I387_XMM0_REGNUM (tdep
) + regnum
,
3169 /* ... Write upper 128bits. */
3170 regcache_raw_write (regcache
,
3171 tdep
->ymm0h_regnum
+ regnum
,
3174 else if (i386_word_regnum_p (gdbarch
, regnum
))
3176 int gpnum
= regnum
- tdep
->ax_regnum
;
3179 regcache_raw_read (regcache
, gpnum
, raw_buf
);
3180 /* ... Modify ... (always little endian). */
3181 memcpy (raw_buf
, buf
, 2);
3183 regcache_raw_write (regcache
, gpnum
, raw_buf
);
3185 else if (i386_byte_regnum_p (gdbarch
, regnum
))
3187 /* Check byte pseudo registers last since this function will
3188 be called from amd64_pseudo_register_read, which handles
3189 byte pseudo registers differently. */
3190 int gpnum
= regnum
- tdep
->al_regnum
;
3192 /* Read ... We read both lower and upper registers. */
3193 regcache_raw_read (regcache
, gpnum
% 4, raw_buf
);
3194 /* ... Modify ... (always little endian). */
3196 memcpy (raw_buf
+ 1, buf
, 1);
3198 memcpy (raw_buf
, buf
, 1);
3200 regcache_raw_write (regcache
, gpnum
% 4, raw_buf
);
3203 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
3208 /* Return the register number of the register allocated by GCC after
3209 REGNUM, or -1 if there is no such register. */
3212 i386_next_regnum (int regnum
)
3214 /* GCC allocates the registers in the order:
3216 %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ...
3218 Since storing a variable in %esp doesn't make any sense we return
3219 -1 for %ebp and for %esp itself. */
3220 static int next_regnum
[] =
3222 I386_EDX_REGNUM
, /* Slot for %eax. */
3223 I386_EBX_REGNUM
, /* Slot for %ecx. */
3224 I386_ECX_REGNUM
, /* Slot for %edx. */
3225 I386_ESI_REGNUM
, /* Slot for %ebx. */
3226 -1, -1, /* Slots for %esp and %ebp. */
3227 I386_EDI_REGNUM
, /* Slot for %esi. */
3228 I386_EBP_REGNUM
/* Slot for %edi. */
3231 if (regnum
>= 0 && regnum
< sizeof (next_regnum
) / sizeof (next_regnum
[0]))
3232 return next_regnum
[regnum
];
3237 /* Return nonzero if a value of type TYPE stored in register REGNUM
3238 needs any special handling. */
3241 i386_convert_register_p (struct gdbarch
*gdbarch
,
3242 int regnum
, struct type
*type
)
3244 int len
= TYPE_LENGTH (type
);
3246 /* Values may be spread across multiple registers. Most debugging
3247 formats aren't expressive enough to specify the locations, so
3248 some heuristics is involved. Right now we only handle types that
3249 have a length that is a multiple of the word size, since GCC
3250 doesn't seem to put any other types into registers. */
3251 if (len
> 4 && len
% 4 == 0)
3253 int last_regnum
= regnum
;
3257 last_regnum
= i386_next_regnum (last_regnum
);
3261 if (last_regnum
!= -1)
3265 return i387_convert_register_p (gdbarch
, regnum
, type
);
3268 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
3269 return its contents in TO. */
3272 i386_register_to_value (struct frame_info
*frame
, int regnum
,
3273 struct type
*type
, gdb_byte
*to
,
3274 int *optimizedp
, int *unavailablep
)
3276 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3277 int len
= TYPE_LENGTH (type
);
3279 if (i386_fp_regnum_p (gdbarch
, regnum
))
3280 return i387_register_to_value (frame
, regnum
, type
, to
,
3281 optimizedp
, unavailablep
);
3283 /* Read a value spread across multiple registers. */
3285 gdb_assert (len
> 4 && len
% 4 == 0);
3289 gdb_assert (regnum
!= -1);
3290 gdb_assert (register_size (gdbarch
, regnum
) == 4);
3292 if (!get_frame_register_bytes (frame
, regnum
, 0,
3293 register_size (gdbarch
, regnum
),
3294 to
, optimizedp
, unavailablep
))
3297 regnum
= i386_next_regnum (regnum
);
3302 *optimizedp
= *unavailablep
= 0;
3306 /* Write the contents FROM of a value of type TYPE into register
3307 REGNUM in frame FRAME. */
3310 i386_value_to_register (struct frame_info
*frame
, int regnum
,
3311 struct type
*type
, const gdb_byte
*from
)
3313 int len
= TYPE_LENGTH (type
);
3315 if (i386_fp_regnum_p (get_frame_arch (frame
), regnum
))
3317 i387_value_to_register (frame
, regnum
, type
, from
);
3321 /* Write a value spread across multiple registers. */
3323 gdb_assert (len
> 4 && len
% 4 == 0);
3327 gdb_assert (regnum
!= -1);
3328 gdb_assert (register_size (get_frame_arch (frame
), regnum
) == 4);
3330 put_frame_register (frame
, regnum
, from
);
3331 regnum
= i386_next_regnum (regnum
);
3337 /* Supply register REGNUM from the buffer specified by GREGS and LEN
3338 in the general-purpose register set REGSET to register cache
3339 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3342 i386_supply_gregset (const struct regset
*regset
, struct regcache
*regcache
,
3343 int regnum
, const void *gregs
, size_t len
)
3345 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
3346 const gdb_byte
*regs
= gregs
;
3349 gdb_assert (len
== tdep
->sizeof_gregset
);
3351 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
3353 if ((regnum
== i
|| regnum
== -1)
3354 && tdep
->gregset_reg_offset
[i
] != -1)
3355 regcache_raw_supply (regcache
, i
, regs
+ tdep
->gregset_reg_offset
[i
]);
3359 /* Collect register REGNUM from the register cache REGCACHE and store
3360 it in the buffer specified by GREGS and LEN as described by the
3361 general-purpose register set REGSET. If REGNUM is -1, do this for
3362 all registers in REGSET. */
3365 i386_collect_gregset (const struct regset
*regset
,
3366 const struct regcache
*regcache
,
3367 int regnum
, void *gregs
, size_t len
)
3369 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
3370 gdb_byte
*regs
= gregs
;
3373 gdb_assert (len
== tdep
->sizeof_gregset
);
3375 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
3377 if ((regnum
== i
|| regnum
== -1)
3378 && tdep
->gregset_reg_offset
[i
] != -1)
3379 regcache_raw_collect (regcache
, i
, regs
+ tdep
->gregset_reg_offset
[i
]);
3383 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
3384 in the floating-point register set REGSET to register cache
3385 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3388 i386_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
3389 int regnum
, const void *fpregs
, size_t len
)
3391 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
3393 if (len
== I387_SIZEOF_FXSAVE
)
3395 i387_supply_fxsave (regcache
, regnum
, fpregs
);
3399 gdb_assert (len
== tdep
->sizeof_fpregset
);
3400 i387_supply_fsave (regcache
, regnum
, fpregs
);
3403 /* Collect register REGNUM from the register cache REGCACHE and store
3404 it in the buffer specified by FPREGS and LEN as described by the
3405 floating-point register set REGSET. If REGNUM is -1, do this for
3406 all registers in REGSET. */
3409 i386_collect_fpregset (const struct regset
*regset
,
3410 const struct regcache
*regcache
,
3411 int regnum
, void *fpregs
, size_t len
)
3413 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
3415 if (len
== I387_SIZEOF_FXSAVE
)
3417 i387_collect_fxsave (regcache
, regnum
, fpregs
);
3421 gdb_assert (len
== tdep
->sizeof_fpregset
);
3422 i387_collect_fsave (regcache
, regnum
, fpregs
);
3425 /* Similar to i386_supply_fpregset, but use XSAVE extended state. */
3428 i386_supply_xstateregset (const struct regset
*regset
,
3429 struct regcache
*regcache
, int regnum
,
3430 const void *xstateregs
, size_t len
)
3432 i387_supply_xsave (regcache
, regnum
, xstateregs
);
3435 /* Similar to i386_collect_fpregset , but use XSAVE extended state. */
3438 i386_collect_xstateregset (const struct regset
*regset
,
3439 const struct regcache
*regcache
,
3440 int regnum
, void *xstateregs
, size_t len
)
3442 i387_collect_xsave (regcache
, regnum
, xstateregs
, 1);
3445 /* Return the appropriate register set for the core section identified
3446 by SECT_NAME and SECT_SIZE. */
3448 const struct regset
*
3449 i386_regset_from_core_section (struct gdbarch
*gdbarch
,
3450 const char *sect_name
, size_t sect_size
)
3452 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3454 if (strcmp (sect_name
, ".reg") == 0 && sect_size
== tdep
->sizeof_gregset
)
3456 if (tdep
->gregset
== NULL
)
3457 tdep
->gregset
= regset_alloc (gdbarch
, i386_supply_gregset
,
3458 i386_collect_gregset
);
3459 return tdep
->gregset
;
3462 if ((strcmp (sect_name
, ".reg2") == 0 && sect_size
== tdep
->sizeof_fpregset
)
3463 || (strcmp (sect_name
, ".reg-xfp") == 0
3464 && sect_size
== I387_SIZEOF_FXSAVE
))
3466 if (tdep
->fpregset
== NULL
)
3467 tdep
->fpregset
= regset_alloc (gdbarch
, i386_supply_fpregset
,
3468 i386_collect_fpregset
);
3469 return tdep
->fpregset
;
3472 if (strcmp (sect_name
, ".reg-xstate") == 0)
3474 if (tdep
->xstateregset
== NULL
)
3475 tdep
->xstateregset
= regset_alloc (gdbarch
,
3476 i386_supply_xstateregset
,
3477 i386_collect_xstateregset
);
3479 return tdep
->xstateregset
;
3486 /* Stuff for WIN32 PE style DLL's but is pretty generic really. */
3489 i386_pe_skip_trampoline_code (struct frame_info
*frame
,
3490 CORE_ADDR pc
, char *name
)
3492 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3493 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3496 if (pc
&& read_memory_unsigned_integer (pc
, 2, byte_order
) == 0x25ff)
3498 unsigned long indirect
=
3499 read_memory_unsigned_integer (pc
+ 2, 4, byte_order
);
3500 struct minimal_symbol
*indsym
=
3501 indirect
? lookup_minimal_symbol_by_pc (indirect
).minsym
: 0;
3502 const char *symname
= indsym
? SYMBOL_LINKAGE_NAME (indsym
) : 0;
3506 if (strncmp (symname
, "__imp_", 6) == 0
3507 || strncmp (symname
, "_imp_", 5) == 0)
3509 read_memory_unsigned_integer (indirect
, 4, byte_order
);
3512 return 0; /* Not a trampoline. */
3516 /* Return whether the THIS_FRAME corresponds to a sigtramp
3520 i386_sigtramp_p (struct frame_info
*this_frame
)
3522 CORE_ADDR pc
= get_frame_pc (this_frame
);
3525 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
3526 return (name
&& strcmp ("_sigtramp", name
) == 0);
3530 /* We have two flavours of disassembly. The machinery on this page
3531 deals with switching between those. */
3534 i386_print_insn (bfd_vma pc
, struct disassemble_info
*info
)
3536 gdb_assert (disassembly_flavor
== att_flavor
3537 || disassembly_flavor
== intel_flavor
);
3539 /* FIXME: kettenis/20020915: Until disassembler_options is properly
3540 constified, cast to prevent a compiler warning. */
3541 info
->disassembler_options
= (char *) disassembly_flavor
;
3543 return print_insn_i386 (pc
, info
);
3547 /* There are a few i386 architecture variants that differ only
3548 slightly from the generic i386 target. For now, we don't give them
3549 their own source file, but include them here. As a consequence,
3550 they'll always be included. */
3552 /* System V Release 4 (SVR4). */
3554 /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp
3558 i386_svr4_sigtramp_p (struct frame_info
*this_frame
)
3560 CORE_ADDR pc
= get_frame_pc (this_frame
);
3563 /* The origin of these symbols is currently unknown. */
3564 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
3565 return (name
&& (strcmp ("_sigreturn", name
) == 0
3566 || strcmp ("sigvechandler", name
) == 0));
3569 /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the
3570 address of the associated sigcontext (ucontext) structure. */
3573 i386_svr4_sigcontext_addr (struct frame_info
*this_frame
)
3575 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3576 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3580 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
3581 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
3583 return read_memory_unsigned_integer (sp
+ 8, 4, byte_order
);
3588 /* Implementation of `gdbarch_stap_is_single_operand', as defined in
3592 i386_stap_is_single_operand (struct gdbarch
*gdbarch
, const char *s
)
3594 return (*s
== '$' /* Literal number. */
3595 || (isdigit (*s
) && s
[1] == '(' && s
[2] == '%') /* Displacement. */
3596 || (*s
== '(' && s
[1] == '%') /* Register indirection. */
3597 || (*s
== '%' && isalpha (s
[1]))); /* Register access. */
3600 /* Implementation of `gdbarch_stap_parse_special_token', as defined in
3604 i386_stap_parse_special_token (struct gdbarch
*gdbarch
,
3605 struct stap_parse_info
*p
)
3607 /* In order to parse special tokens, we use a state-machine that go
3608 through every known token and try to get a match. */
3612 THREE_ARG_DISPLACEMENT
,
3616 current_state
= TRIPLET
;
3618 /* The special tokens to be parsed here are:
3620 - `register base + (register index * size) + offset', as represented
3621 in `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'.
3623 - Operands of the form `-8+3+1(%rbp)', which must be interpreted as
3624 `*(-8 + 3 - 1 + (void *) $eax)'. */
3626 while (current_state
!= DONE
)
3628 const char *s
= p
->arg
;
3630 switch (current_state
)
3634 if (isdigit (*s
) || *s
== '-' || *s
== '+')
3638 long displacements
[3];
3654 displacements
[0] = strtol (s
, &endp
, 10);
3657 if (*s
!= '+' && *s
!= '-')
3659 /* We are not dealing with a triplet. */
3672 displacements
[1] = strtol (s
, &endp
, 10);
3675 if (*s
!= '+' && *s
!= '-')
3677 /* We are not dealing with a triplet. */
3690 displacements
[2] = strtol (s
, &endp
, 10);
3693 if (*s
!= '(' || s
[1] != '%')
3699 while (isalnum (*s
))
3706 regname
= alloca (len
+ 1);
3708 strncpy (regname
, start
, len
);
3709 regname
[len
] = '\0';
3711 if (user_reg_map_name_to_regnum (gdbarch
,
3712 regname
, len
) == -1)
3713 error (_("Invalid register name `%s' "
3714 "on expression `%s'."),
3715 regname
, p
->saved_arg
);
3717 for (i
= 0; i
< 3; i
++)
3719 write_exp_elt_opcode (OP_LONG
);
3721 (builtin_type (gdbarch
)->builtin_long
);
3722 write_exp_elt_longcst (displacements
[i
]);
3723 write_exp_elt_opcode (OP_LONG
);
3725 write_exp_elt_opcode (UNOP_NEG
);
3728 write_exp_elt_opcode (OP_REGISTER
);
3731 write_exp_string (str
);
3732 write_exp_elt_opcode (OP_REGISTER
);
3734 write_exp_elt_opcode (UNOP_CAST
);
3735 write_exp_elt_type (builtin_type (gdbarch
)->builtin_data_ptr
);
3736 write_exp_elt_opcode (UNOP_CAST
);
3738 write_exp_elt_opcode (BINOP_ADD
);
3739 write_exp_elt_opcode (BINOP_ADD
);
3740 write_exp_elt_opcode (BINOP_ADD
);
3742 write_exp_elt_opcode (UNOP_CAST
);
3743 write_exp_elt_type (lookup_pointer_type (p
->arg_type
));
3744 write_exp_elt_opcode (UNOP_CAST
);
3746 write_exp_elt_opcode (UNOP_IND
);
3754 case THREE_ARG_DISPLACEMENT
:
3756 if (isdigit (*s
) || *s
== '(' || *s
== '-' || *s
== '+')
3758 int offset_minus
= 0;
3767 struct stoken base_token
, index_token
;
3777 if (offset_minus
&& !isdigit (*s
))
3784 offset
= strtol (s
, &endp
, 10);
3788 if (*s
!= '(' || s
[1] != '%')
3794 while (isalnum (*s
))
3797 if (*s
!= ',' || s
[1] != '%')
3800 len_base
= s
- start
;
3801 base
= alloca (len_base
+ 1);
3802 strncpy (base
, start
, len_base
);
3803 base
[len_base
] = '\0';
3805 if (user_reg_map_name_to_regnum (gdbarch
,
3806 base
, len_base
) == -1)
3807 error (_("Invalid register name `%s' "
3808 "on expression `%s'."),
3809 base
, p
->saved_arg
);
3814 while (isalnum (*s
))
3817 len_index
= s
- start
;
3818 index
= alloca (len_index
+ 1);
3819 strncpy (index
, start
, len_index
);
3820 index
[len_index
] = '\0';
3822 if (user_reg_map_name_to_regnum (gdbarch
,
3823 index
, len_index
) == -1)
3824 error (_("Invalid register name `%s' "
3825 "on expression `%s'."),
3826 index
, p
->saved_arg
);
3828 if (*s
!= ',' && *s
!= ')')
3844 size
= strtol (s
, &endp
, 10);
3855 write_exp_elt_opcode (OP_LONG
);
3857 (builtin_type (gdbarch
)->builtin_long
);
3858 write_exp_elt_longcst (offset
);
3859 write_exp_elt_opcode (OP_LONG
);
3861 write_exp_elt_opcode (UNOP_NEG
);
3864 write_exp_elt_opcode (OP_REGISTER
);
3865 base_token
.ptr
= base
;
3866 base_token
.length
= len_base
;
3867 write_exp_string (base_token
);
3868 write_exp_elt_opcode (OP_REGISTER
);
3871 write_exp_elt_opcode (BINOP_ADD
);
3873 write_exp_elt_opcode (OP_REGISTER
);
3874 index_token
.ptr
= index
;
3875 index_token
.length
= len_index
;
3876 write_exp_string (index_token
);
3877 write_exp_elt_opcode (OP_REGISTER
);
3881 write_exp_elt_opcode (OP_LONG
);
3883 (builtin_type (gdbarch
)->builtin_long
);
3884 write_exp_elt_longcst (size
);
3885 write_exp_elt_opcode (OP_LONG
);
3887 write_exp_elt_opcode (UNOP_NEG
);
3888 write_exp_elt_opcode (BINOP_MUL
);
3891 write_exp_elt_opcode (BINOP_ADD
);
3893 write_exp_elt_opcode (UNOP_CAST
);
3894 write_exp_elt_type (lookup_pointer_type (p
->arg_type
));
3895 write_exp_elt_opcode (UNOP_CAST
);
3897 write_exp_elt_opcode (UNOP_IND
);
3907 /* Advancing to the next state. */
3919 i386_elf_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
3921 /* We typically use stabs-in-ELF with the SVR4 register numbering. */
3922 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
3924 /* Registering SystemTap handlers. */
3925 set_gdbarch_stap_integer_prefix (gdbarch
, "$");
3926 set_gdbarch_stap_register_prefix (gdbarch
, "%");
3927 set_gdbarch_stap_register_indirection_prefix (gdbarch
, "(");
3928 set_gdbarch_stap_register_indirection_suffix (gdbarch
, ")");
3929 set_gdbarch_stap_is_single_operand (gdbarch
,
3930 i386_stap_is_single_operand
);
3931 set_gdbarch_stap_parse_special_token (gdbarch
,
3932 i386_stap_parse_special_token
);
3935 /* System V Release 4 (SVR4). */
3938 i386_svr4_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
3940 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3942 /* System V Release 4 uses ELF. */
3943 i386_elf_init_abi (info
, gdbarch
);
3945 /* System V Release 4 has shared libraries. */
3946 set_gdbarch_skip_trampoline_code (gdbarch
, find_solib_trampoline_target
);
3948 tdep
->sigtramp_p
= i386_svr4_sigtramp_p
;
3949 tdep
->sigcontext_addr
= i386_svr4_sigcontext_addr
;
3950 tdep
->sc_pc_offset
= 36 + 14 * 4;
3951 tdep
->sc_sp_offset
= 36 + 17 * 4;
3953 tdep
->jb_pc_offset
= 20;
3959 i386_go32_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
3961 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3963 /* DJGPP doesn't have any special frames for signal handlers. */
3964 tdep
->sigtramp_p
= NULL
;
3966 tdep
->jb_pc_offset
= 36;
3968 /* DJGPP does not support the SSE registers. */
3969 if (! tdesc_has_registers (info
.target_desc
))
3970 tdep
->tdesc
= tdesc_i386_mmx
;
3972 /* Native compiler is GCC, which uses the SVR4 register numbering
3973 even in COFF and STABS. See the comment in i386_gdbarch_init,
3974 before the calls to set_gdbarch_stab_reg_to_regnum and
3975 set_gdbarch_sdb_reg_to_regnum. */
3976 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
3977 set_gdbarch_sdb_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
3979 set_gdbarch_has_dos_based_file_system (gdbarch
, 1);
3983 /* i386 register groups. In addition to the normal groups, add "mmx"
3986 static struct reggroup
*i386_sse_reggroup
;
3987 static struct reggroup
*i386_mmx_reggroup
;
3990 i386_init_reggroups (void)
3992 i386_sse_reggroup
= reggroup_new ("sse", USER_REGGROUP
);
3993 i386_mmx_reggroup
= reggroup_new ("mmx", USER_REGGROUP
);
3997 i386_add_reggroups (struct gdbarch
*gdbarch
)
3999 reggroup_add (gdbarch
, i386_sse_reggroup
);
4000 reggroup_add (gdbarch
, i386_mmx_reggroup
);
4001 reggroup_add (gdbarch
, general_reggroup
);
4002 reggroup_add (gdbarch
, float_reggroup
);
4003 reggroup_add (gdbarch
, all_reggroup
);
4004 reggroup_add (gdbarch
, save_reggroup
);
4005 reggroup_add (gdbarch
, restore_reggroup
);
4006 reggroup_add (gdbarch
, vector_reggroup
);
4007 reggroup_add (gdbarch
, system_reggroup
);
4011 i386_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
4012 struct reggroup
*group
)
4014 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4015 int fp_regnum_p
, mmx_regnum_p
, xmm_regnum_p
, mxcsr_regnum_p
,
4016 ymm_regnum_p
, ymmh_regnum_p
, bndr_regnum_p
, bnd_regnum_p
,
4019 /* Don't include pseudo registers, except for MMX, in any register
4021 if (i386_byte_regnum_p (gdbarch
, regnum
))
4024 if (i386_word_regnum_p (gdbarch
, regnum
))
4027 if (i386_dword_regnum_p (gdbarch
, regnum
))
4030 mmx_regnum_p
= i386_mmx_regnum_p (gdbarch
, regnum
);
4031 if (group
== i386_mmx_reggroup
)
4032 return mmx_regnum_p
;
4034 xmm_regnum_p
= i386_xmm_regnum_p (gdbarch
, regnum
);
4035 mxcsr_regnum_p
= i386_mxcsr_regnum_p (gdbarch
, regnum
);
4036 if (group
== i386_sse_reggroup
)
4037 return xmm_regnum_p
|| mxcsr_regnum_p
;
4039 ymm_regnum_p
= i386_ymm_regnum_p (gdbarch
, regnum
);
4040 if (group
== vector_reggroup
)
4041 return (mmx_regnum_p
4045 && ((tdep
->xcr0
& I386_XSTATE_AVX_MASK
)
4046 == I386_XSTATE_SSE_MASK
)));
4048 fp_regnum_p
= (i386_fp_regnum_p (gdbarch
, regnum
)
4049 || i386_fpc_regnum_p (gdbarch
, regnum
));
4050 if (group
== float_reggroup
)
4053 /* For "info reg all", don't include upper YMM registers nor XMM
4054 registers when AVX is supported. */
4055 ymmh_regnum_p
= i386_ymmh_regnum_p (gdbarch
, regnum
);
4056 if (group
== all_reggroup
4058 && (tdep
->xcr0
& I386_XSTATE_AVX
))
4062 bnd_regnum_p
= i386_bnd_regnum_p (gdbarch
, regnum
);
4063 if (group
== all_reggroup
4064 && ((bnd_regnum_p
&& (tdep
->xcr0
& I386_XSTATE_MPX_MASK
))))
4065 return bnd_regnum_p
;
4067 bndr_regnum_p
= i386_bndr_regnum_p (gdbarch
, regnum
);
4068 if (group
== all_reggroup
4069 && ((bndr_regnum_p
&& (tdep
->xcr0
& I386_XSTATE_MPX_MASK
))))
4072 mpx_ctrl_regnum_p
= i386_mpx_ctrl_regnum_p (gdbarch
, regnum
);
4073 if (group
== all_reggroup
4074 && ((mpx_ctrl_regnum_p
&& (tdep
->xcr0
& I386_XSTATE_MPX_MASK
))))
4075 return mpx_ctrl_regnum_p
;
4077 if (group
== general_reggroup
)
4078 return (!fp_regnum_p
4086 && !mpx_ctrl_regnum_p
);
4088 return default_register_reggroup_p (gdbarch
, regnum
, group
);
4092 /* Get the ARGIth function argument for the current function. */
4095 i386_fetch_pointer_argument (struct frame_info
*frame
, int argi
,
4098 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4099 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4100 CORE_ADDR sp
= get_frame_register_unsigned (frame
, I386_ESP_REGNUM
);
4101 return read_memory_unsigned_integer (sp
+ (4 * (argi
+ 1)), 4, byte_order
);
4105 i386_skip_permanent_breakpoint (struct regcache
*regcache
)
4107 CORE_ADDR current_pc
= regcache_read_pc (regcache
);
4109 /* On i386, breakpoint is exactly 1 byte long, so we just
4110 adjust the PC in the regcache. */
4112 regcache_write_pc (regcache
, current_pc
);
4116 #define PREFIX_REPZ 0x01
4117 #define PREFIX_REPNZ 0x02
4118 #define PREFIX_LOCK 0x04
4119 #define PREFIX_DATA 0x08
4120 #define PREFIX_ADDR 0x10
4132 /* i386 arith/logic operations */
4145 struct i386_record_s
4147 struct gdbarch
*gdbarch
;
4148 struct regcache
*regcache
;
4149 CORE_ADDR orig_addr
;
4155 uint8_t mod
, reg
, rm
;
4164 /* Parse the "modrm" part of the memory address irp->addr points at.
4165 Returns -1 if something goes wrong, 0 otherwise. */
4168 i386_record_modrm (struct i386_record_s
*irp
)
4170 struct gdbarch
*gdbarch
= irp
->gdbarch
;
4172 if (record_read_memory (gdbarch
, irp
->addr
, &irp
->modrm
, 1))
4176 irp
->mod
= (irp
->modrm
>> 6) & 3;
4177 irp
->reg
= (irp
->modrm
>> 3) & 7;
4178 irp
->rm
= irp
->modrm
& 7;
4183 /* Extract the memory address that the current instruction writes to,
4184 and return it in *ADDR. Return -1 if something goes wrong. */
4187 i386_record_lea_modrm_addr (struct i386_record_s
*irp
, uint64_t *addr
)
4189 struct gdbarch
*gdbarch
= irp
->gdbarch
;
4190 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4202 uint8_t base
= irp
->rm
;
4207 if (record_read_memory (gdbarch
, irp
->addr
, &byte
, 1))
4210 scale
= (byte
>> 6) & 3;
4211 index
= ((byte
>> 3) & 7) | irp
->rex_x
;
4219 if ((base
& 7) == 5)
4222 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 4))
4225 *addr
= extract_signed_integer (buf
, 4, byte_order
);
4226 if (irp
->regmap
[X86_RECORD_R8_REGNUM
] && !havesib
)
4227 *addr
+= irp
->addr
+ irp
->rip_offset
;
4231 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 1))
4234 *addr
= (int8_t) buf
[0];
4237 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 4))
4239 *addr
= extract_signed_integer (buf
, 4, byte_order
);
4247 if (base
== 4 && irp
->popl_esp_hack
)
4248 *addr
+= irp
->popl_esp_hack
;
4249 regcache_raw_read_unsigned (irp
->regcache
, irp
->regmap
[base
],
4252 if (irp
->aflag
== 2)
4257 *addr
= (uint32_t) (offset64
+ *addr
);
4259 if (havesib
&& (index
!= 4 || scale
!= 0))
4261 regcache_raw_read_unsigned (irp
->regcache
, irp
->regmap
[index
],
4263 if (irp
->aflag
== 2)
4264 *addr
+= offset64
<< scale
;
4266 *addr
= (uint32_t) (*addr
+ (offset64
<< scale
));
4277 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 2))
4280 *addr
= extract_signed_integer (buf
, 2, byte_order
);
4286 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 1))
4289 *addr
= (int8_t) buf
[0];
4292 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 2))
4295 *addr
= extract_signed_integer (buf
, 2, byte_order
);
4302 regcache_raw_read_unsigned (irp
->regcache
,
4303 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
4305 *addr
= (uint32_t) (*addr
+ offset64
);
4306 regcache_raw_read_unsigned (irp
->regcache
,
4307 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
4309 *addr
= (uint32_t) (*addr
+ offset64
);
4312 regcache_raw_read_unsigned (irp
->regcache
,
4313 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
4315 *addr
= (uint32_t) (*addr
+ offset64
);
4316 regcache_raw_read_unsigned (irp
->regcache
,
4317 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
4319 *addr
= (uint32_t) (*addr
+ offset64
);
4322 regcache_raw_read_unsigned (irp
->regcache
,
4323 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
4325 *addr
= (uint32_t) (*addr
+ offset64
);
4326 regcache_raw_read_unsigned (irp
->regcache
,
4327 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
4329 *addr
= (uint32_t) (*addr
+ offset64
);
4332 regcache_raw_read_unsigned (irp
->regcache
,
4333 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
4335 *addr
= (uint32_t) (*addr
+ offset64
);
4336 regcache_raw_read_unsigned (irp
->regcache
,
4337 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
4339 *addr
= (uint32_t) (*addr
+ offset64
);
4342 regcache_raw_read_unsigned (irp
->regcache
,
4343 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
4345 *addr
= (uint32_t) (*addr
+ offset64
);
4348 regcache_raw_read_unsigned (irp
->regcache
,
4349 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
4351 *addr
= (uint32_t) (*addr
+ offset64
);
4354 regcache_raw_read_unsigned (irp
->regcache
,
4355 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
4357 *addr
= (uint32_t) (*addr
+ offset64
);
4360 regcache_raw_read_unsigned (irp
->regcache
,
4361 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
4363 *addr
= (uint32_t) (*addr
+ offset64
);
4373 /* Record the address and contents of the memory that will be changed
4374 by the current instruction. Return -1 if something goes wrong, 0
4378 i386_record_lea_modrm (struct i386_record_s
*irp
)
4380 struct gdbarch
*gdbarch
= irp
->gdbarch
;
4383 if (irp
->override
>= 0)
4385 if (record_full_memory_query
)
4389 target_terminal_ours ();
4391 Process record ignores the memory change of instruction at address %s\n\
4392 because it can't get the value of the segment register.\n\
4393 Do you want to stop the program?"),
4394 paddress (gdbarch
, irp
->orig_addr
));
4395 target_terminal_inferior ();
4403 if (i386_record_lea_modrm_addr (irp
, &addr
))
4406 if (record_full_arch_list_add_mem (addr
, 1 << irp
->ot
))
4412 /* Record the effects of a push operation. Return -1 if something
4413 goes wrong, 0 otherwise. */
4416 i386_record_push (struct i386_record_s
*irp
, int size
)
4420 if (record_full_arch_list_add_reg (irp
->regcache
,
4421 irp
->regmap
[X86_RECORD_RESP_REGNUM
]))
4423 regcache_raw_read_unsigned (irp
->regcache
,
4424 irp
->regmap
[X86_RECORD_RESP_REGNUM
],
4426 if (record_full_arch_list_add_mem ((CORE_ADDR
) addr
- size
, size
))
4433 /* Defines contents to record. */
4434 #define I386_SAVE_FPU_REGS 0xfffd
4435 #define I386_SAVE_FPU_ENV 0xfffe
4436 #define I386_SAVE_FPU_ENV_REG_STACK 0xffff
4438 /* Record the values of the floating point registers which will be
4439 changed by the current instruction. Returns -1 if something is
4440 wrong, 0 otherwise. */
4442 static int i386_record_floats (struct gdbarch
*gdbarch
,
4443 struct i386_record_s
*ir
,
4446 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4449 /* Oza: Because of floating point insn push/pop of fpu stack is going to
4450 happen. Currently we store st0-st7 registers, but we need not store all
4451 registers all the time, in future we use ftag register and record only
4452 those who are not marked as an empty. */
4454 if (I386_SAVE_FPU_REGS
== iregnum
)
4456 for (i
= I387_ST0_REGNUM (tdep
); i
<= I387_ST0_REGNUM (tdep
) + 7; i
++)
4458 if (record_full_arch_list_add_reg (ir
->regcache
, i
))
4462 else if (I386_SAVE_FPU_ENV
== iregnum
)
4464 for (i
= I387_FCTRL_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
4466 if (record_full_arch_list_add_reg (ir
->regcache
, i
))
4470 else if (I386_SAVE_FPU_ENV_REG_STACK
== iregnum
)
4472 for (i
= I387_ST0_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
4474 if (record_full_arch_list_add_reg (ir
->regcache
, i
))
4478 else if ((iregnum
>= I387_ST0_REGNUM (tdep
)) &&
4479 (iregnum
<= I387_FOP_REGNUM (tdep
)))
4481 if (record_full_arch_list_add_reg (ir
->regcache
,iregnum
))
4486 /* Parameter error. */
4489 if(I386_SAVE_FPU_ENV
!= iregnum
)
4491 for (i
= I387_FCTRL_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
4493 if (record_full_arch_list_add_reg (ir
->regcache
, i
))
4500 /* Parse the current instruction, and record the values of the
4501 registers and memory that will be changed by the current
4502 instruction. Returns -1 if something goes wrong, 0 otherwise. */
4504 #define I386_RECORD_FULL_ARCH_LIST_ADD_REG(regnum) \
4505 record_full_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)])
4508 i386_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4509 CORE_ADDR input_addr
)
4511 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4517 gdb_byte buf
[MAX_REGISTER_SIZE
];
4518 struct i386_record_s ir
;
4519 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4523 memset (&ir
, 0, sizeof (struct i386_record_s
));
4524 ir
.regcache
= regcache
;
4525 ir
.addr
= input_addr
;
4526 ir
.orig_addr
= input_addr
;
4530 ir
.popl_esp_hack
= 0;
4531 ir
.regmap
= tdep
->record_regmap
;
4532 ir
.gdbarch
= gdbarch
;
4534 if (record_debug
> 1)
4535 fprintf_unfiltered (gdb_stdlog
, "Process record: i386_process_record "
4537 paddress (gdbarch
, ir
.addr
));
4542 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
4545 switch (opcode8
) /* Instruction prefixes */
4547 case REPE_PREFIX_OPCODE
:
4548 prefixes
|= PREFIX_REPZ
;
4550 case REPNE_PREFIX_OPCODE
:
4551 prefixes
|= PREFIX_REPNZ
;
4553 case LOCK_PREFIX_OPCODE
:
4554 prefixes
|= PREFIX_LOCK
;
4556 case CS_PREFIX_OPCODE
:
4557 ir
.override
= X86_RECORD_CS_REGNUM
;
4559 case SS_PREFIX_OPCODE
:
4560 ir
.override
= X86_RECORD_SS_REGNUM
;
4562 case DS_PREFIX_OPCODE
:
4563 ir
.override
= X86_RECORD_DS_REGNUM
;
4565 case ES_PREFIX_OPCODE
:
4566 ir
.override
= X86_RECORD_ES_REGNUM
;
4568 case FS_PREFIX_OPCODE
:
4569 ir
.override
= X86_RECORD_FS_REGNUM
;
4571 case GS_PREFIX_OPCODE
:
4572 ir
.override
= X86_RECORD_GS_REGNUM
;
4574 case DATA_PREFIX_OPCODE
:
4575 prefixes
|= PREFIX_DATA
;
4577 case ADDR_PREFIX_OPCODE
:
4578 prefixes
|= PREFIX_ADDR
;
4580 case 0x40: /* i386 inc %eax */
4581 case 0x41: /* i386 inc %ecx */
4582 case 0x42: /* i386 inc %edx */
4583 case 0x43: /* i386 inc %ebx */
4584 case 0x44: /* i386 inc %esp */
4585 case 0x45: /* i386 inc %ebp */
4586 case 0x46: /* i386 inc %esi */
4587 case 0x47: /* i386 inc %edi */
4588 case 0x48: /* i386 dec %eax */
4589 case 0x49: /* i386 dec %ecx */
4590 case 0x4a: /* i386 dec %edx */
4591 case 0x4b: /* i386 dec %ebx */
4592 case 0x4c: /* i386 dec %esp */
4593 case 0x4d: /* i386 dec %ebp */
4594 case 0x4e: /* i386 dec %esi */
4595 case 0x4f: /* i386 dec %edi */
4596 if (ir
.regmap
[X86_RECORD_R8_REGNUM
]) /* 64 bit target */
4599 rex_w
= (opcode8
>> 3) & 1;
4600 rex_r
= (opcode8
& 0x4) << 1;
4601 ir
.rex_x
= (opcode8
& 0x2) << 2;
4602 ir
.rex_b
= (opcode8
& 0x1) << 3;
4604 else /* 32 bit target */
4613 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && rex_w
== 1)
4619 if (prefixes
& PREFIX_DATA
)
4622 if (prefixes
& PREFIX_ADDR
)
4624 else if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4627 /* Now check op code. */
4628 opcode
= (uint32_t) opcode8
;
4633 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
4636 opcode
= (uint32_t) opcode8
| 0x0f00;
4640 case 0x00: /* arith & logic */
4688 if (((opcode
>> 3) & 7) != OP_CMPL
)
4690 if ((opcode
& 1) == 0)
4693 ir
.ot
= ir
.dflag
+ OT_WORD
;
4695 switch ((opcode
>> 1) & 3)
4697 case 0: /* OP Ev, Gv */
4698 if (i386_record_modrm (&ir
))
4702 if (i386_record_lea_modrm (&ir
))
4708 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4710 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
4713 case 1: /* OP Gv, Ev */
4714 if (i386_record_modrm (&ir
))
4717 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4719 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
4721 case 2: /* OP A, Iv */
4722 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4726 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4729 case 0x80: /* GRP1 */
4733 if (i386_record_modrm (&ir
))
4736 if (ir
.reg
!= OP_CMPL
)
4738 if ((opcode
& 1) == 0)
4741 ir
.ot
= ir
.dflag
+ OT_WORD
;
4748 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
4749 if (i386_record_lea_modrm (&ir
))
4753 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
4755 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4758 case 0x40: /* inc */
4767 case 0x48: /* dec */
4776 I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode
& 7);
4777 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4780 case 0xf6: /* GRP3 */
4782 if ((opcode
& 1) == 0)
4785 ir
.ot
= ir
.dflag
+ OT_WORD
;
4786 if (i386_record_modrm (&ir
))
4789 if (ir
.mod
!= 3 && ir
.reg
== 0)
4790 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
4795 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4801 if (i386_record_lea_modrm (&ir
))
4807 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4809 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
4811 if (ir
.reg
== 3) /* neg */
4812 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4818 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4819 if (ir
.ot
!= OT_BYTE
)
4820 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
4821 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4825 opcode
= opcode
<< 8 | ir
.modrm
;
4831 case 0xfe: /* GRP4 */
4832 case 0xff: /* GRP5 */
4833 if (i386_record_modrm (&ir
))
4835 if (ir
.reg
>= 2 && opcode
== 0xfe)
4838 opcode
= opcode
<< 8 | ir
.modrm
;
4845 if ((opcode
& 1) == 0)
4848 ir
.ot
= ir
.dflag
+ OT_WORD
;
4851 if (i386_record_lea_modrm (&ir
))
4857 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4859 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
4861 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4864 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4866 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4868 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4871 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
4872 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4874 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4878 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4881 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4883 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4888 opcode
= opcode
<< 8 | ir
.modrm
;
4894 case 0x84: /* test */
4898 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4901 case 0x98: /* CWDE/CBW */
4902 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4905 case 0x99: /* CDQ/CWD */
4906 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4907 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
4910 case 0x0faf: /* imul */
4913 ir
.ot
= ir
.dflag
+ OT_WORD
;
4914 if (i386_record_modrm (&ir
))
4917 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
4918 else if (opcode
== 0x6b)
4921 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4923 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
4924 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4927 case 0x0fc0: /* xadd */
4929 if ((opcode
& 1) == 0)
4932 ir
.ot
= ir
.dflag
+ OT_WORD
;
4933 if (i386_record_modrm (&ir
))
4938 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4940 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
4941 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4943 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
4947 if (i386_record_lea_modrm (&ir
))
4949 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4951 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
4953 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4956 case 0x0fb0: /* cmpxchg */
4958 if ((opcode
& 1) == 0)
4961 ir
.ot
= ir
.dflag
+ OT_WORD
;
4962 if (i386_record_modrm (&ir
))
4967 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4968 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4970 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
4974 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4975 if (i386_record_lea_modrm (&ir
))
4978 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4981 case 0x0fc7: /* cmpxchg8b */
4982 if (i386_record_modrm (&ir
))
4987 opcode
= opcode
<< 8 | ir
.modrm
;
4990 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4991 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
4992 if (i386_record_lea_modrm (&ir
))
4994 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4997 case 0x50: /* push */
5007 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5009 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5013 case 0x06: /* push es */
5014 case 0x0e: /* push cs */
5015 case 0x16: /* push ss */
5016 case 0x1e: /* push ds */
5017 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5022 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5026 case 0x0fa0: /* push fs */
5027 case 0x0fa8: /* push gs */
5028 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5033 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5037 case 0x60: /* pusha */
5038 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5043 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 4)))
5047 case 0x58: /* pop */
5055 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5056 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode
& 0x7) | ir
.rex_b
);
5059 case 0x61: /* popa */
5060 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5065 for (regnum
= X86_RECORD_REAX_REGNUM
;
5066 regnum
<= X86_RECORD_REDI_REGNUM
;
5068 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum
);
5071 case 0x8f: /* pop */
5072 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5073 ir
.ot
= ir
.dflag
? OT_QUAD
: OT_WORD
;
5075 ir
.ot
= ir
.dflag
+ OT_WORD
;
5076 if (i386_record_modrm (&ir
))
5079 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5082 ir
.popl_esp_hack
= 1 << ir
.ot
;
5083 if (i386_record_lea_modrm (&ir
))
5086 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5089 case 0xc8: /* enter */
5090 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
5091 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5093 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5097 case 0xc9: /* leave */
5098 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5099 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
5102 case 0x07: /* pop es */
5103 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5108 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5109 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM
);
5110 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5113 case 0x17: /* pop ss */
5114 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5119 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5120 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM
);
5121 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5124 case 0x1f: /* pop ds */
5125 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5130 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5131 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM
);
5132 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5135 case 0x0fa1: /* pop fs */
5136 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5137 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM
);
5138 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5141 case 0x0fa9: /* pop gs */
5142 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5143 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM
);
5144 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5147 case 0x88: /* mov */
5151 if ((opcode
& 1) == 0)
5154 ir
.ot
= ir
.dflag
+ OT_WORD
;
5156 if (i386_record_modrm (&ir
))
5161 if (opcode
== 0xc6 || opcode
== 0xc7)
5162 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
5163 if (i386_record_lea_modrm (&ir
))
5168 if (opcode
== 0xc6 || opcode
== 0xc7)
5170 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5172 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5176 case 0x8a: /* mov */
5178 if ((opcode
& 1) == 0)
5181 ir
.ot
= ir
.dflag
+ OT_WORD
;
5182 if (i386_record_modrm (&ir
))
5185 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5187 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5190 case 0x8c: /* mov seg */
5191 if (i386_record_modrm (&ir
))
5196 opcode
= opcode
<< 8 | ir
.modrm
;
5201 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5205 if (i386_record_lea_modrm (&ir
))
5210 case 0x8e: /* mov seg */
5211 if (i386_record_modrm (&ir
))
5216 regnum
= X86_RECORD_ES_REGNUM
;
5219 regnum
= X86_RECORD_SS_REGNUM
;
5222 regnum
= X86_RECORD_DS_REGNUM
;
5225 regnum
= X86_RECORD_FS_REGNUM
;
5228 regnum
= X86_RECORD_GS_REGNUM
;
5232 opcode
= opcode
<< 8 | ir
.modrm
;
5236 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum
);
5237 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5240 case 0x0fb6: /* movzbS */
5241 case 0x0fb7: /* movzwS */
5242 case 0x0fbe: /* movsbS */
5243 case 0x0fbf: /* movswS */
5244 if (i386_record_modrm (&ir
))
5246 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
5249 case 0x8d: /* lea */
5250 if (i386_record_modrm (&ir
))
5255 opcode
= opcode
<< 8 | ir
.modrm
;
5260 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5262 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5265 case 0xa0: /* mov EAX */
5268 case 0xd7: /* xlat */
5269 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5272 case 0xa2: /* mov EAX */
5274 if (ir
.override
>= 0)
5276 if (record_full_memory_query
)
5280 target_terminal_ours ();
5282 Process record ignores the memory change of instruction at address %s\n\
5283 because it can't get the value of the segment register.\n\
5284 Do you want to stop the program?"),
5285 paddress (gdbarch
, ir
.orig_addr
));
5286 target_terminal_inferior ();
5293 if ((opcode
& 1) == 0)
5296 ir
.ot
= ir
.dflag
+ OT_WORD
;
5299 if (record_read_memory (gdbarch
, ir
.addr
, buf
, 8))
5302 addr
= extract_unsigned_integer (buf
, 8, byte_order
);
5306 if (record_read_memory (gdbarch
, ir
.addr
, buf
, 4))
5309 addr
= extract_unsigned_integer (buf
, 4, byte_order
);
5313 if (record_read_memory (gdbarch
, ir
.addr
, buf
, 2))
5316 addr
= extract_unsigned_integer (buf
, 2, byte_order
);
5318 if (record_full_arch_list_add_mem (addr
, 1 << ir
.ot
))
5323 case 0xb0: /* mov R, Ib */
5331 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((ir
.regmap
[X86_RECORD_R8_REGNUM
])
5332 ? ((opcode
& 0x7) | ir
.rex_b
)
5333 : ((opcode
& 0x7) & 0x3));
5336 case 0xb8: /* mov R, Iv */
5344 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode
& 0x7) | ir
.rex_b
);
5347 case 0x91: /* xchg R, EAX */
5354 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5355 I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode
& 0x7);
5358 case 0x86: /* xchg Ev, Gv */
5360 if ((opcode
& 1) == 0)
5363 ir
.ot
= ir
.dflag
+ OT_WORD
;
5364 if (i386_record_modrm (&ir
))
5369 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5371 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5375 if (i386_record_lea_modrm (&ir
))
5379 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5381 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5384 case 0xc4: /* les Gv */
5385 case 0xc5: /* lds Gv */
5386 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5392 case 0x0fb2: /* lss Gv */
5393 case 0x0fb4: /* lfs Gv */
5394 case 0x0fb5: /* lgs Gv */
5395 if (i386_record_modrm (&ir
))
5403 opcode
= opcode
<< 8 | ir
.modrm
;
5408 case 0xc4: /* les Gv */
5409 regnum
= X86_RECORD_ES_REGNUM
;
5411 case 0xc5: /* lds Gv */
5412 regnum
= X86_RECORD_DS_REGNUM
;
5414 case 0x0fb2: /* lss Gv */
5415 regnum
= X86_RECORD_SS_REGNUM
;
5417 case 0x0fb4: /* lfs Gv */
5418 regnum
= X86_RECORD_FS_REGNUM
;
5420 case 0x0fb5: /* lgs Gv */
5421 regnum
= X86_RECORD_GS_REGNUM
;
5424 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum
);
5425 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
5426 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5429 case 0xc0: /* shifts */
5435 if ((opcode
& 1) == 0)
5438 ir
.ot
= ir
.dflag
+ OT_WORD
;
5439 if (i386_record_modrm (&ir
))
5441 if (ir
.mod
!= 3 && (opcode
== 0xd2 || opcode
== 0xd3))
5443 if (i386_record_lea_modrm (&ir
))
5449 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5451 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5453 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5460 if (i386_record_modrm (&ir
))
5464 if (record_full_arch_list_add_reg (ir
.regcache
, ir
.rm
))
5469 if (i386_record_lea_modrm (&ir
))
5474 case 0xd8: /* Floats. */
5482 if (i386_record_modrm (&ir
))
5484 ir
.reg
|= ((opcode
& 7) << 3);
5490 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
5498 /* For fcom, ficom nothing to do. */
5504 /* For fcomp, ficomp pop FPU stack, store all. */
5505 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5532 /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul,
5533 fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension
5534 of code, always affects st(0) register. */
5535 if (i386_record_floats (gdbarch
, &ir
, I387_ST0_REGNUM (tdep
)))
5559 /* Handling fld, fild. */
5560 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5564 switch (ir
.reg
>> 4)
5567 if (record_full_arch_list_add_mem (addr64
, 4))
5571 if (record_full_arch_list_add_mem (addr64
, 8))
5577 if (record_full_arch_list_add_mem (addr64
, 2))
5583 switch (ir
.reg
>> 4)
5586 if (record_full_arch_list_add_mem (addr64
, 4))
5588 if (3 == (ir
.reg
& 7))
5590 /* For fstp m32fp. */
5591 if (i386_record_floats (gdbarch
, &ir
,
5592 I386_SAVE_FPU_REGS
))
5597 if (record_full_arch_list_add_mem (addr64
, 4))
5599 if ((3 == (ir
.reg
& 7))
5600 || (5 == (ir
.reg
& 7))
5601 || (7 == (ir
.reg
& 7)))
5603 /* For fstp insn. */
5604 if (i386_record_floats (gdbarch
, &ir
,
5605 I386_SAVE_FPU_REGS
))
5610 if (record_full_arch_list_add_mem (addr64
, 8))
5612 if (3 == (ir
.reg
& 7))
5614 /* For fstp m64fp. */
5615 if (i386_record_floats (gdbarch
, &ir
,
5616 I386_SAVE_FPU_REGS
))
5621 if ((3 <= (ir
.reg
& 7)) && (6 <= (ir
.reg
& 7)))
5623 /* For fistp, fbld, fild, fbstp. */
5624 if (i386_record_floats (gdbarch
, &ir
,
5625 I386_SAVE_FPU_REGS
))
5630 if (record_full_arch_list_add_mem (addr64
, 2))
5639 if (i386_record_floats (gdbarch
, &ir
,
5640 I386_SAVE_FPU_ENV_REG_STACK
))
5645 if (i386_record_floats (gdbarch
, &ir
, I387_FCTRL_REGNUM (tdep
)))
5650 if (i386_record_floats (gdbarch
, &ir
,
5651 I386_SAVE_FPU_ENV_REG_STACK
))
5657 if (record_full_arch_list_add_mem (addr64
, 28))
5662 if (record_full_arch_list_add_mem (addr64
, 14))
5668 if (record_full_arch_list_add_mem (addr64
, 2))
5670 /* Insn fstp, fbstp. */
5671 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5676 if (record_full_arch_list_add_mem (addr64
, 10))
5682 if (record_full_arch_list_add_mem (addr64
, 28))
5688 if (record_full_arch_list_add_mem (addr64
, 14))
5692 if (record_full_arch_list_add_mem (addr64
, 80))
5695 if (i386_record_floats (gdbarch
, &ir
,
5696 I386_SAVE_FPU_ENV_REG_STACK
))
5700 if (record_full_arch_list_add_mem (addr64
, 8))
5703 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5708 opcode
= opcode
<< 8 | ir
.modrm
;
5713 /* Opcode is an extension of modR/M byte. */
5719 if (i386_record_floats (gdbarch
, &ir
, I387_ST0_REGNUM (tdep
)))
5723 if (0x0c == (ir
.modrm
>> 4))
5725 if ((ir
.modrm
& 0x0f) <= 7)
5727 if (i386_record_floats (gdbarch
, &ir
,
5728 I386_SAVE_FPU_REGS
))
5733 if (i386_record_floats (gdbarch
, &ir
,
5734 I387_ST0_REGNUM (tdep
)))
5736 /* If only st(0) is changing, then we have already
5738 if ((ir
.modrm
& 0x0f) - 0x08)
5740 if (i386_record_floats (gdbarch
, &ir
,
5741 I387_ST0_REGNUM (tdep
) +
5742 ((ir
.modrm
& 0x0f) - 0x08)))
5760 if (i386_record_floats (gdbarch
, &ir
,
5761 I387_ST0_REGNUM (tdep
)))
5779 if (i386_record_floats (gdbarch
, &ir
,
5780 I386_SAVE_FPU_REGS
))
5784 if (i386_record_floats (gdbarch
, &ir
,
5785 I387_ST0_REGNUM (tdep
)))
5787 if (i386_record_floats (gdbarch
, &ir
,
5788 I387_ST0_REGNUM (tdep
) + 1))
5795 if (0xe9 == ir
.modrm
)
5797 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5800 else if ((0x0c == ir
.modrm
>> 4) || (0x0d == ir
.modrm
>> 4))
5802 if (i386_record_floats (gdbarch
, &ir
,
5803 I387_ST0_REGNUM (tdep
)))
5805 if (((ir
.modrm
& 0x0f) > 0) && ((ir
.modrm
& 0x0f) <= 7))
5807 if (i386_record_floats (gdbarch
, &ir
,
5808 I387_ST0_REGNUM (tdep
) +
5812 else if ((ir
.modrm
& 0x0f) - 0x08)
5814 if (i386_record_floats (gdbarch
, &ir
,
5815 I387_ST0_REGNUM (tdep
) +
5816 ((ir
.modrm
& 0x0f) - 0x08)))
5822 if (0xe3 == ir
.modrm
)
5824 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_ENV
))
5827 else if ((0x0c == ir
.modrm
>> 4) || (0x0d == ir
.modrm
>> 4))
5829 if (i386_record_floats (gdbarch
, &ir
,
5830 I387_ST0_REGNUM (tdep
)))
5832 if (((ir
.modrm
& 0x0f) > 0) && ((ir
.modrm
& 0x0f) <= 7))
5834 if (i386_record_floats (gdbarch
, &ir
,
5835 I387_ST0_REGNUM (tdep
) +
5839 else if ((ir
.modrm
& 0x0f) - 0x08)
5841 if (i386_record_floats (gdbarch
, &ir
,
5842 I387_ST0_REGNUM (tdep
) +
5843 ((ir
.modrm
& 0x0f) - 0x08)))
5849 if ((0x0c == ir
.modrm
>> 4)
5850 || (0x0d == ir
.modrm
>> 4)
5851 || (0x0f == ir
.modrm
>> 4))
5853 if ((ir
.modrm
& 0x0f) <= 7)
5855 if (i386_record_floats (gdbarch
, &ir
,
5856 I387_ST0_REGNUM (tdep
) +
5862 if (i386_record_floats (gdbarch
, &ir
,
5863 I387_ST0_REGNUM (tdep
) +
5864 ((ir
.modrm
& 0x0f) - 0x08)))
5870 if (0x0c == ir
.modrm
>> 4)
5872 if (i386_record_floats (gdbarch
, &ir
,
5873 I387_FTAG_REGNUM (tdep
)))
5876 else if ((0x0d == ir
.modrm
>> 4) || (0x0e == ir
.modrm
>> 4))
5878 if ((ir
.modrm
& 0x0f) <= 7)
5880 if (i386_record_floats (gdbarch
, &ir
,
5881 I387_ST0_REGNUM (tdep
) +
5887 if (i386_record_floats (gdbarch
, &ir
,
5888 I386_SAVE_FPU_REGS
))
5894 if ((0x0c == ir
.modrm
>> 4)
5895 || (0x0e == ir
.modrm
>> 4)
5896 || (0x0f == ir
.modrm
>> 4)
5897 || (0xd9 == ir
.modrm
))
5899 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5904 if (0xe0 == ir
.modrm
)
5906 if (record_full_arch_list_add_reg (ir
.regcache
,
5910 else if ((0x0f == ir
.modrm
>> 4) || (0x0e == ir
.modrm
>> 4))
5912 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5920 case 0xa4: /* movsS */
5922 case 0xaa: /* stosS */
5924 case 0x6c: /* insS */
5926 regcache_raw_read_unsigned (ir
.regcache
,
5927 ir
.regmap
[X86_RECORD_RECX_REGNUM
],
5933 if ((opcode
& 1) == 0)
5936 ir
.ot
= ir
.dflag
+ OT_WORD
;
5937 regcache_raw_read_unsigned (ir
.regcache
,
5938 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
5941 regcache_raw_read_unsigned (ir
.regcache
,
5942 ir
.regmap
[X86_RECORD_ES_REGNUM
],
5944 regcache_raw_read_unsigned (ir
.regcache
,
5945 ir
.regmap
[X86_RECORD_DS_REGNUM
],
5947 if (ir
.aflag
&& (es
!= ds
))
5949 /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */
5950 if (record_full_memory_query
)
5954 target_terminal_ours ();
5956 Process record ignores the memory change of instruction at address %s\n\
5957 because it can't get the value of the segment register.\n\
5958 Do you want to stop the program?"),
5959 paddress (gdbarch
, ir
.orig_addr
));
5960 target_terminal_inferior ();
5967 if (record_full_arch_list_add_mem (addr
, 1 << ir
.ot
))
5971 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5972 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5973 if (opcode
== 0xa4 || opcode
== 0xa5)
5974 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
5975 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
5976 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5980 case 0xa6: /* cmpsS */
5982 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
5983 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
5984 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5985 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5986 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5989 case 0xac: /* lodsS */
5991 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5992 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
5993 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5994 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5995 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5998 case 0xae: /* scasS */
6000 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
6001 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
6002 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6003 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6006 case 0x6e: /* outsS */
6008 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
6009 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
6010 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6011 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6014 case 0xe4: /* port I/O */
6018 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6019 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6029 case 0xc2: /* ret im */
6030 case 0xc3: /* ret */
6031 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
6032 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6035 case 0xca: /* lret im */
6036 case 0xcb: /* lret */
6037 case 0xcf: /* iret */
6038 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
6039 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
6040 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6043 case 0xe8: /* call im */
6044 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
6046 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
6050 case 0x9a: /* lcall im */
6051 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6056 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
6057 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
6061 case 0xe9: /* jmp im */
6062 case 0xea: /* ljmp im */
6063 case 0xeb: /* jmp Jb */
6064 case 0x70: /* jcc Jb */
6080 case 0x0f80: /* jcc Jv */
6098 case 0x0f90: /* setcc Gv */
6114 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6116 if (i386_record_modrm (&ir
))
6119 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rex_b
? (ir
.rm
| ir
.rex_b
)
6123 if (i386_record_lea_modrm (&ir
))
6128 case 0x0f40: /* cmov Gv, Ev */
6144 if (i386_record_modrm (&ir
))
6147 if (ir
.dflag
== OT_BYTE
)
6149 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
6153 case 0x9c: /* pushf */
6154 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6155 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
6157 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
6161 case 0x9d: /* popf */
6162 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
6163 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6166 case 0x9e: /* sahf */
6167 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6173 case 0xf5: /* cmc */
6174 case 0xf8: /* clc */
6175 case 0xf9: /* stc */
6176 case 0xfc: /* cld */
6177 case 0xfd: /* std */
6178 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6181 case 0x9f: /* lahf */
6182 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6187 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6188 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6191 /* bit operations */
6192 case 0x0fba: /* bt/bts/btr/btc Gv, im */
6193 ir
.ot
= ir
.dflag
+ OT_WORD
;
6194 if (i386_record_modrm (&ir
))
6199 opcode
= opcode
<< 8 | ir
.modrm
;
6205 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6208 if (i386_record_lea_modrm (&ir
))
6212 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6215 case 0x0fa3: /* bt Gv, Ev */
6216 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6219 case 0x0fab: /* bts */
6220 case 0x0fb3: /* btr */
6221 case 0x0fbb: /* btc */
6222 ir
.ot
= ir
.dflag
+ OT_WORD
;
6223 if (i386_record_modrm (&ir
))
6226 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6230 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
6232 regcache_raw_read_unsigned (ir
.regcache
,
6233 ir
.regmap
[ir
.reg
| rex_r
],
6238 addr64
+= ((int16_t) addr
>> 4) << 4;
6241 addr64
+= ((int32_t) addr
>> 5) << 5;
6244 addr64
+= ((int64_t) addr
>> 6) << 6;
6247 if (record_full_arch_list_add_mem (addr64
, 1 << ir
.ot
))
6249 if (i386_record_lea_modrm (&ir
))
6252 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6255 case 0x0fbc: /* bsf */
6256 case 0x0fbd: /* bsr */
6257 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
6258 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6262 case 0x27: /* daa */
6263 case 0x2f: /* das */
6264 case 0x37: /* aaa */
6265 case 0x3f: /* aas */
6266 case 0xd4: /* aam */
6267 case 0xd5: /* aad */
6268 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6273 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6274 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6278 case 0x90: /* nop */
6279 if (prefixes
& PREFIX_LOCK
)
6286 case 0x9b: /* fwait */
6287 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
6289 opcode
= (uint32_t) opcode8
;
6295 case 0xcc: /* int3 */
6296 printf_unfiltered (_("Process record does not support instruction "
6303 case 0xcd: /* int */
6307 if (record_read_memory (gdbarch
, ir
.addr
, &interrupt
, 1))
6310 if (interrupt
!= 0x80
6311 || tdep
->i386_intx80_record
== NULL
)
6313 printf_unfiltered (_("Process record does not support "
6314 "instruction int 0x%02x.\n"),
6319 ret
= tdep
->i386_intx80_record (ir
.regcache
);
6326 case 0xce: /* into */
6327 printf_unfiltered (_("Process record does not support "
6328 "instruction into.\n"));
6333 case 0xfa: /* cli */
6334 case 0xfb: /* sti */
6337 case 0x62: /* bound */
6338 printf_unfiltered (_("Process record does not support "
6339 "instruction bound.\n"));
6344 case 0x0fc8: /* bswap reg */
6352 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode
& 7) | ir
.rex_b
);
6355 case 0xd6: /* salc */
6356 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6361 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6362 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6365 case 0xe0: /* loopnz */
6366 case 0xe1: /* loopz */
6367 case 0xe2: /* loop */
6368 case 0xe3: /* jecxz */
6369 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6370 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6373 case 0x0f30: /* wrmsr */
6374 printf_unfiltered (_("Process record does not support "
6375 "instruction wrmsr.\n"));
6380 case 0x0f32: /* rdmsr */
6381 printf_unfiltered (_("Process record does not support "
6382 "instruction rdmsr.\n"));
6387 case 0x0f31: /* rdtsc */
6388 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6389 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
6392 case 0x0f34: /* sysenter */
6395 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6400 if (tdep
->i386_sysenter_record
== NULL
)
6402 printf_unfiltered (_("Process record does not support "
6403 "instruction sysenter.\n"));
6407 ret
= tdep
->i386_sysenter_record (ir
.regcache
);
6413 case 0x0f35: /* sysexit */
6414 printf_unfiltered (_("Process record does not support "
6415 "instruction sysexit.\n"));
6420 case 0x0f05: /* syscall */
6423 if (tdep
->i386_syscall_record
== NULL
)
6425 printf_unfiltered (_("Process record does not support "
6426 "instruction syscall.\n"));
6430 ret
= tdep
->i386_syscall_record (ir
.regcache
);
6436 case 0x0f07: /* sysret */
6437 printf_unfiltered (_("Process record does not support "
6438 "instruction sysret.\n"));
6443 case 0x0fa2: /* cpuid */
6444 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6445 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6446 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
6447 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM
);
6450 case 0xf4: /* hlt */
6451 printf_unfiltered (_("Process record does not support "
6452 "instruction hlt.\n"));
6458 if (i386_record_modrm (&ir
))
6465 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6469 if (i386_record_lea_modrm (&ir
))
6478 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6482 opcode
= opcode
<< 8 | ir
.modrm
;
6489 if (i386_record_modrm (&ir
))
6500 opcode
= opcode
<< 8 | ir
.modrm
;
6503 if (ir
.override
>= 0)
6505 if (record_full_memory_query
)
6509 target_terminal_ours ();
6511 Process record ignores the memory change of instruction at address %s\n\
6512 because it can't get the value of the segment register.\n\
6513 Do you want to stop the program?"),
6514 paddress (gdbarch
, ir
.orig_addr
));
6515 target_terminal_inferior ();
6522 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
6524 if (record_full_arch_list_add_mem (addr64
, 2))
6527 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6529 if (record_full_arch_list_add_mem (addr64
, 8))
6534 if (record_full_arch_list_add_mem (addr64
, 4))
6545 case 0: /* monitor */
6548 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6552 opcode
= opcode
<< 8 | ir
.modrm
;
6560 if (ir
.override
>= 0)
6562 if (record_full_memory_query
)
6566 target_terminal_ours ();
6568 Process record ignores the memory change of instruction at address %s\n\
6569 because it can't get the value of the segment register.\n\
6570 Do you want to stop the program?"),
6571 paddress (gdbarch
, ir
.orig_addr
));
6572 target_terminal_inferior ();
6581 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
6583 if (record_full_arch_list_add_mem (addr64
, 2))
6586 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6588 if (record_full_arch_list_add_mem (addr64
, 8))
6593 if (record_full_arch_list_add_mem (addr64
, 4))
6605 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6606 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
6610 else if (ir
.rm
== 1)
6617 opcode
= opcode
<< 8 | ir
.modrm
;
6624 if (record_full_arch_list_add_reg (ir
.regcache
, ir
.rm
| ir
.rex_b
))
6630 if (i386_record_lea_modrm (&ir
))
6633 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6636 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6638 case 7: /* invlpg */
6641 if (ir
.rm
== 0 && ir
.regmap
[X86_RECORD_R8_REGNUM
])
6642 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM
);
6646 opcode
= opcode
<< 8 | ir
.modrm
;
6651 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6655 opcode
= opcode
<< 8 | ir
.modrm
;
6661 case 0x0f08: /* invd */
6662 case 0x0f09: /* wbinvd */
6665 case 0x63: /* arpl */
6666 if (i386_record_modrm (&ir
))
6668 if (ir
.mod
== 3 || ir
.regmap
[X86_RECORD_R8_REGNUM
])
6670 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.regmap
[X86_RECORD_R8_REGNUM
]
6671 ? (ir
.reg
| rex_r
) : ir
.rm
);
6675 ir
.ot
= ir
.dflag
? OT_LONG
: OT_WORD
;
6676 if (i386_record_lea_modrm (&ir
))
6679 if (!ir
.regmap
[X86_RECORD_R8_REGNUM
])
6680 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6683 case 0x0f02: /* lar */
6684 case 0x0f03: /* lsl */
6685 if (i386_record_modrm (&ir
))
6687 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
6688 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6692 if (i386_record_modrm (&ir
))
6694 if (ir
.mod
== 3 && ir
.reg
== 3)
6697 opcode
= opcode
<< 8 | ir
.modrm
;
6709 /* nop (multi byte) */
6712 case 0x0f20: /* mov reg, crN */
6713 case 0x0f22: /* mov crN, reg */
6714 if (i386_record_modrm (&ir
))
6716 if ((ir
.modrm
& 0xc0) != 0xc0)
6719 opcode
= opcode
<< 8 | ir
.modrm
;
6730 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6732 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6736 opcode
= opcode
<< 8 | ir
.modrm
;
6742 case 0x0f21: /* mov reg, drN */
6743 case 0x0f23: /* mov drN, reg */
6744 if (i386_record_modrm (&ir
))
6746 if ((ir
.modrm
& 0xc0) != 0xc0 || ir
.reg
== 4
6747 || ir
.reg
== 5 || ir
.reg
>= 8)
6750 opcode
= opcode
<< 8 | ir
.modrm
;
6754 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6756 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6759 case 0x0f06: /* clts */
6760 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6763 /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */
6765 case 0x0f0d: /* 3DNow! prefetch */
6768 case 0x0f0e: /* 3DNow! femms */
6769 case 0x0f77: /* emms */
6770 if (i386_fpc_regnum_p (gdbarch
, I387_FTAG_REGNUM(tdep
)))
6772 record_full_arch_list_add_reg (ir
.regcache
, I387_FTAG_REGNUM(tdep
));
6775 case 0x0f0f: /* 3DNow! data */
6776 if (i386_record_modrm (&ir
))
6778 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
6783 case 0x0c: /* 3DNow! pi2fw */
6784 case 0x0d: /* 3DNow! pi2fd */
6785 case 0x1c: /* 3DNow! pf2iw */
6786 case 0x1d: /* 3DNow! pf2id */
6787 case 0x8a: /* 3DNow! pfnacc */
6788 case 0x8e: /* 3DNow! pfpnacc */
6789 case 0x90: /* 3DNow! pfcmpge */
6790 case 0x94: /* 3DNow! pfmin */
6791 case 0x96: /* 3DNow! pfrcp */
6792 case 0x97: /* 3DNow! pfrsqrt */
6793 case 0x9a: /* 3DNow! pfsub */
6794 case 0x9e: /* 3DNow! pfadd */
6795 case 0xa0: /* 3DNow! pfcmpgt */
6796 case 0xa4: /* 3DNow! pfmax */
6797 case 0xa6: /* 3DNow! pfrcpit1 */
6798 case 0xa7: /* 3DNow! pfrsqit1 */
6799 case 0xaa: /* 3DNow! pfsubr */
6800 case 0xae: /* 3DNow! pfacc */
6801 case 0xb0: /* 3DNow! pfcmpeq */
6802 case 0xb4: /* 3DNow! pfmul */
6803 case 0xb6: /* 3DNow! pfrcpit2 */
6804 case 0xb7: /* 3DNow! pmulhrw */
6805 case 0xbb: /* 3DNow! pswapd */
6806 case 0xbf: /* 3DNow! pavgusb */
6807 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.reg
))
6808 goto no_support_3dnow_data
;
6809 record_full_arch_list_add_reg (ir
.regcache
, ir
.reg
);
6813 no_support_3dnow_data
:
6814 opcode
= (opcode
<< 8) | opcode8
;
6820 case 0x0faa: /* rsm */
6821 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6822 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6823 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6824 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
6825 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM
);
6826 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
6827 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
6828 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
6829 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
6833 if (i386_record_modrm (&ir
))
6837 case 0: /* fxsave */
6841 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6842 if (i386_record_lea_modrm_addr (&ir
, &tmpu64
))
6844 if (record_full_arch_list_add_mem (tmpu64
, 512))
6849 case 1: /* fxrstor */
6853 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6855 for (i
= I387_MM0_REGNUM (tdep
);
6856 i386_mmx_regnum_p (gdbarch
, i
); i
++)
6857 record_full_arch_list_add_reg (ir
.regcache
, i
);
6859 for (i
= I387_XMM0_REGNUM (tdep
);
6860 i386_xmm_regnum_p (gdbarch
, i
); i
++)
6861 record_full_arch_list_add_reg (ir
.regcache
, i
);
6863 if (i386_mxcsr_regnum_p (gdbarch
, I387_MXCSR_REGNUM(tdep
)))
6864 record_full_arch_list_add_reg (ir
.regcache
,
6865 I387_MXCSR_REGNUM(tdep
));
6867 for (i
= I387_ST0_REGNUM (tdep
);
6868 i386_fp_regnum_p (gdbarch
, i
); i
++)
6869 record_full_arch_list_add_reg (ir
.regcache
, i
);
6871 for (i
= I387_FCTRL_REGNUM (tdep
);
6872 i386_fpc_regnum_p (gdbarch
, i
); i
++)
6873 record_full_arch_list_add_reg (ir
.regcache
, i
);
6877 case 2: /* ldmxcsr */
6878 if (!i386_mxcsr_regnum_p (gdbarch
, I387_MXCSR_REGNUM(tdep
)))
6880 record_full_arch_list_add_reg (ir
.regcache
, I387_MXCSR_REGNUM(tdep
));
6883 case 3: /* stmxcsr */
6885 if (i386_record_lea_modrm (&ir
))
6889 case 5: /* lfence */
6890 case 6: /* mfence */
6891 case 7: /* sfence clflush */
6895 opcode
= (opcode
<< 8) | ir
.modrm
;
6901 case 0x0fc3: /* movnti */
6902 ir
.ot
= (ir
.dflag
== 2) ? OT_QUAD
: OT_LONG
;
6903 if (i386_record_modrm (&ir
))
6908 if (i386_record_lea_modrm (&ir
))
6912 /* Add prefix to opcode. */
7039 reswitch_prefix_add
:
7047 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
7050 opcode
= (uint32_t) opcode8
| opcode
<< 8;
7051 goto reswitch_prefix_add
;
7054 case 0x0f10: /* movups */
7055 case 0x660f10: /* movupd */
7056 case 0xf30f10: /* movss */
7057 case 0xf20f10: /* movsd */
7058 case 0x0f12: /* movlps */
7059 case 0x660f12: /* movlpd */
7060 case 0xf30f12: /* movsldup */
7061 case 0xf20f12: /* movddup */
7062 case 0x0f14: /* unpcklps */
7063 case 0x660f14: /* unpcklpd */
7064 case 0x0f15: /* unpckhps */
7065 case 0x660f15: /* unpckhpd */
7066 case 0x0f16: /* movhps */
7067 case 0x660f16: /* movhpd */
7068 case 0xf30f16: /* movshdup */
7069 case 0x0f28: /* movaps */
7070 case 0x660f28: /* movapd */
7071 case 0x0f2a: /* cvtpi2ps */
7072 case 0x660f2a: /* cvtpi2pd */
7073 case 0xf30f2a: /* cvtsi2ss */
7074 case 0xf20f2a: /* cvtsi2sd */
7075 case 0x0f2c: /* cvttps2pi */
7076 case 0x660f2c: /* cvttpd2pi */
7077 case 0x0f2d: /* cvtps2pi */
7078 case 0x660f2d: /* cvtpd2pi */
7079 case 0x660f3800: /* pshufb */
7080 case 0x660f3801: /* phaddw */
7081 case 0x660f3802: /* phaddd */
7082 case 0x660f3803: /* phaddsw */
7083 case 0x660f3804: /* pmaddubsw */
7084 case 0x660f3805: /* phsubw */
7085 case 0x660f3806: /* phsubd */
7086 case 0x660f3807: /* phsubsw */
7087 case 0x660f3808: /* psignb */
7088 case 0x660f3809: /* psignw */
7089 case 0x660f380a: /* psignd */
7090 case 0x660f380b: /* pmulhrsw */
7091 case 0x660f3810: /* pblendvb */
7092 case 0x660f3814: /* blendvps */
7093 case 0x660f3815: /* blendvpd */
7094 case 0x660f381c: /* pabsb */
7095 case 0x660f381d: /* pabsw */
7096 case 0x660f381e: /* pabsd */
7097 case 0x660f3820: /* pmovsxbw */
7098 case 0x660f3821: /* pmovsxbd */
7099 case 0x660f3822: /* pmovsxbq */
7100 case 0x660f3823: /* pmovsxwd */
7101 case 0x660f3824: /* pmovsxwq */
7102 case 0x660f3825: /* pmovsxdq */
7103 case 0x660f3828: /* pmuldq */
7104 case 0x660f3829: /* pcmpeqq */
7105 case 0x660f382a: /* movntdqa */
7106 case 0x660f3a08: /* roundps */
7107 case 0x660f3a09: /* roundpd */
7108 case 0x660f3a0a: /* roundss */
7109 case 0x660f3a0b: /* roundsd */
7110 case 0x660f3a0c: /* blendps */
7111 case 0x660f3a0d: /* blendpd */
7112 case 0x660f3a0e: /* pblendw */
7113 case 0x660f3a0f: /* palignr */
7114 case 0x660f3a20: /* pinsrb */
7115 case 0x660f3a21: /* insertps */
7116 case 0x660f3a22: /* pinsrd pinsrq */
7117 case 0x660f3a40: /* dpps */
7118 case 0x660f3a41: /* dppd */
7119 case 0x660f3a42: /* mpsadbw */
7120 case 0x660f3a60: /* pcmpestrm */
7121 case 0x660f3a61: /* pcmpestri */
7122 case 0x660f3a62: /* pcmpistrm */
7123 case 0x660f3a63: /* pcmpistri */
7124 case 0x0f51: /* sqrtps */
7125 case 0x660f51: /* sqrtpd */
7126 case 0xf20f51: /* sqrtsd */
7127 case 0xf30f51: /* sqrtss */
7128 case 0x0f52: /* rsqrtps */
7129 case 0xf30f52: /* rsqrtss */
7130 case 0x0f53: /* rcpps */
7131 case 0xf30f53: /* rcpss */
7132 case 0x0f54: /* andps */
7133 case 0x660f54: /* andpd */
7134 case 0x0f55: /* andnps */
7135 case 0x660f55: /* andnpd */
7136 case 0x0f56: /* orps */
7137 case 0x660f56: /* orpd */
7138 case 0x0f57: /* xorps */
7139 case 0x660f57: /* xorpd */
7140 case 0x0f58: /* addps */
7141 case 0x660f58: /* addpd */
7142 case 0xf20f58: /* addsd */
7143 case 0xf30f58: /* addss */
7144 case 0x0f59: /* mulps */
7145 case 0x660f59: /* mulpd */
7146 case 0xf20f59: /* mulsd */
7147 case 0xf30f59: /* mulss */
7148 case 0x0f5a: /* cvtps2pd */
7149 case 0x660f5a: /* cvtpd2ps */
7150 case 0xf20f5a: /* cvtsd2ss */
7151 case 0xf30f5a: /* cvtss2sd */
7152 case 0x0f5b: /* cvtdq2ps */
7153 case 0x660f5b: /* cvtps2dq */
7154 case 0xf30f5b: /* cvttps2dq */
7155 case 0x0f5c: /* subps */
7156 case 0x660f5c: /* subpd */
7157 case 0xf20f5c: /* subsd */
7158 case 0xf30f5c: /* subss */
7159 case 0x0f5d: /* minps */
7160 case 0x660f5d: /* minpd */
7161 case 0xf20f5d: /* minsd */
7162 case 0xf30f5d: /* minss */
7163 case 0x0f5e: /* divps */
7164 case 0x660f5e: /* divpd */
7165 case 0xf20f5e: /* divsd */
7166 case 0xf30f5e: /* divss */
7167 case 0x0f5f: /* maxps */
7168 case 0x660f5f: /* maxpd */
7169 case 0xf20f5f: /* maxsd */
7170 case 0xf30f5f: /* maxss */
7171 case 0x660f60: /* punpcklbw */
7172 case 0x660f61: /* punpcklwd */
7173 case 0x660f62: /* punpckldq */
7174 case 0x660f63: /* packsswb */
7175 case 0x660f64: /* pcmpgtb */
7176 case 0x660f65: /* pcmpgtw */
7177 case 0x660f66: /* pcmpgtd */
7178 case 0x660f67: /* packuswb */
7179 case 0x660f68: /* punpckhbw */
7180 case 0x660f69: /* punpckhwd */
7181 case 0x660f6a: /* punpckhdq */
7182 case 0x660f6b: /* packssdw */
7183 case 0x660f6c: /* punpcklqdq */
7184 case 0x660f6d: /* punpckhqdq */
7185 case 0x660f6e: /* movd */
7186 case 0x660f6f: /* movdqa */
7187 case 0xf30f6f: /* movdqu */
7188 case 0x660f70: /* pshufd */
7189 case 0xf20f70: /* pshuflw */
7190 case 0xf30f70: /* pshufhw */
7191 case 0x660f74: /* pcmpeqb */
7192 case 0x660f75: /* pcmpeqw */
7193 case 0x660f76: /* pcmpeqd */
7194 case 0x660f7c: /* haddpd */
7195 case 0xf20f7c: /* haddps */
7196 case 0x660f7d: /* hsubpd */
7197 case 0xf20f7d: /* hsubps */
7198 case 0xf30f7e: /* movq */
7199 case 0x0fc2: /* cmpps */
7200 case 0x660fc2: /* cmppd */
7201 case 0xf20fc2: /* cmpsd */
7202 case 0xf30fc2: /* cmpss */
7203 case 0x660fc4: /* pinsrw */
7204 case 0x0fc6: /* shufps */
7205 case 0x660fc6: /* shufpd */
7206 case 0x660fd0: /* addsubpd */
7207 case 0xf20fd0: /* addsubps */
7208 case 0x660fd1: /* psrlw */
7209 case 0x660fd2: /* psrld */
7210 case 0x660fd3: /* psrlq */
7211 case 0x660fd4: /* paddq */
7212 case 0x660fd5: /* pmullw */
7213 case 0xf30fd6: /* movq2dq */
7214 case 0x660fd8: /* psubusb */
7215 case 0x660fd9: /* psubusw */
7216 case 0x660fda: /* pminub */
7217 case 0x660fdb: /* pand */
7218 case 0x660fdc: /* paddusb */
7219 case 0x660fdd: /* paddusw */
7220 case 0x660fde: /* pmaxub */
7221 case 0x660fdf: /* pandn */
7222 case 0x660fe0: /* pavgb */
7223 case 0x660fe1: /* psraw */
7224 case 0x660fe2: /* psrad */
7225 case 0x660fe3: /* pavgw */
7226 case 0x660fe4: /* pmulhuw */
7227 case 0x660fe5: /* pmulhw */
7228 case 0x660fe6: /* cvttpd2dq */
7229 case 0xf20fe6: /* cvtpd2dq */
7230 case 0xf30fe6: /* cvtdq2pd */
7231 case 0x660fe8: /* psubsb */
7232 case 0x660fe9: /* psubsw */
7233 case 0x660fea: /* pminsw */
7234 case 0x660feb: /* por */
7235 case 0x660fec: /* paddsb */
7236 case 0x660fed: /* paddsw */
7237 case 0x660fee: /* pmaxsw */
7238 case 0x660fef: /* pxor */
7239 case 0xf20ff0: /* lddqu */
7240 case 0x660ff1: /* psllw */
7241 case 0x660ff2: /* pslld */
7242 case 0x660ff3: /* psllq */
7243 case 0x660ff4: /* pmuludq */
7244 case 0x660ff5: /* pmaddwd */
7245 case 0x660ff6: /* psadbw */
7246 case 0x660ff8: /* psubb */
7247 case 0x660ff9: /* psubw */
7248 case 0x660ffa: /* psubd */
7249 case 0x660ffb: /* psubq */
7250 case 0x660ffc: /* paddb */
7251 case 0x660ffd: /* paddw */
7252 case 0x660ffe: /* paddd */
7253 if (i386_record_modrm (&ir
))
7256 if (!i386_xmm_regnum_p (gdbarch
, I387_XMM0_REGNUM (tdep
) + ir
.reg
))
7258 record_full_arch_list_add_reg (ir
.regcache
,
7259 I387_XMM0_REGNUM (tdep
) + ir
.reg
);
7260 if ((opcode
& 0xfffffffc) == 0x660f3a60)
7261 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7264 case 0x0f11: /* movups */
7265 case 0x660f11: /* movupd */
7266 case 0xf30f11: /* movss */
7267 case 0xf20f11: /* movsd */
7268 case 0x0f13: /* movlps */
7269 case 0x660f13: /* movlpd */
7270 case 0x0f17: /* movhps */
7271 case 0x660f17: /* movhpd */
7272 case 0x0f29: /* movaps */
7273 case 0x660f29: /* movapd */
7274 case 0x660f3a14: /* pextrb */
7275 case 0x660f3a15: /* pextrw */
7276 case 0x660f3a16: /* pextrd pextrq */
7277 case 0x660f3a17: /* extractps */
7278 case 0x660f7f: /* movdqa */
7279 case 0xf30f7f: /* movdqu */
7280 if (i386_record_modrm (&ir
))
7284 if (opcode
== 0x0f13 || opcode
== 0x660f13
7285 || opcode
== 0x0f17 || opcode
== 0x660f17)
7288 if (!i386_xmm_regnum_p (gdbarch
,
7289 I387_XMM0_REGNUM (tdep
) + ir
.rm
))
7291 record_full_arch_list_add_reg (ir
.regcache
,
7292 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
7314 if (i386_record_lea_modrm (&ir
))
7319 case 0x0f2b: /* movntps */
7320 case 0x660f2b: /* movntpd */
7321 case 0x0fe7: /* movntq */
7322 case 0x660fe7: /* movntdq */
7325 if (opcode
== 0x0fe7)
7329 if (i386_record_lea_modrm (&ir
))
7333 case 0xf30f2c: /* cvttss2si */
7334 case 0xf20f2c: /* cvttsd2si */
7335 case 0xf30f2d: /* cvtss2si */
7336 case 0xf20f2d: /* cvtsd2si */
7337 case 0xf20f38f0: /* crc32 */
7338 case 0xf20f38f1: /* crc32 */
7339 case 0x0f50: /* movmskps */
7340 case 0x660f50: /* movmskpd */
7341 case 0x0fc5: /* pextrw */
7342 case 0x660fc5: /* pextrw */
7343 case 0x0fd7: /* pmovmskb */
7344 case 0x660fd7: /* pmovmskb */
7345 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
7348 case 0x0f3800: /* pshufb */
7349 case 0x0f3801: /* phaddw */
7350 case 0x0f3802: /* phaddd */
7351 case 0x0f3803: /* phaddsw */
7352 case 0x0f3804: /* pmaddubsw */
7353 case 0x0f3805: /* phsubw */
7354 case 0x0f3806: /* phsubd */
7355 case 0x0f3807: /* phsubsw */
7356 case 0x0f3808: /* psignb */
7357 case 0x0f3809: /* psignw */
7358 case 0x0f380a: /* psignd */
7359 case 0x0f380b: /* pmulhrsw */
7360 case 0x0f381c: /* pabsb */
7361 case 0x0f381d: /* pabsw */
7362 case 0x0f381e: /* pabsd */
7363 case 0x0f382b: /* packusdw */
7364 case 0x0f3830: /* pmovzxbw */
7365 case 0x0f3831: /* pmovzxbd */
7366 case 0x0f3832: /* pmovzxbq */
7367 case 0x0f3833: /* pmovzxwd */
7368 case 0x0f3834: /* pmovzxwq */
7369 case 0x0f3835: /* pmovzxdq */
7370 case 0x0f3837: /* pcmpgtq */
7371 case 0x0f3838: /* pminsb */
7372 case 0x0f3839: /* pminsd */
7373 case 0x0f383a: /* pminuw */
7374 case 0x0f383b: /* pminud */
7375 case 0x0f383c: /* pmaxsb */
7376 case 0x0f383d: /* pmaxsd */
7377 case 0x0f383e: /* pmaxuw */
7378 case 0x0f383f: /* pmaxud */
7379 case 0x0f3840: /* pmulld */
7380 case 0x0f3841: /* phminposuw */
7381 case 0x0f3a0f: /* palignr */
7382 case 0x0f60: /* punpcklbw */
7383 case 0x0f61: /* punpcklwd */
7384 case 0x0f62: /* punpckldq */
7385 case 0x0f63: /* packsswb */
7386 case 0x0f64: /* pcmpgtb */
7387 case 0x0f65: /* pcmpgtw */
7388 case 0x0f66: /* pcmpgtd */
7389 case 0x0f67: /* packuswb */
7390 case 0x0f68: /* punpckhbw */
7391 case 0x0f69: /* punpckhwd */
7392 case 0x0f6a: /* punpckhdq */
7393 case 0x0f6b: /* packssdw */
7394 case 0x0f6e: /* movd */
7395 case 0x0f6f: /* movq */
7396 case 0x0f70: /* pshufw */
7397 case 0x0f74: /* pcmpeqb */
7398 case 0x0f75: /* pcmpeqw */
7399 case 0x0f76: /* pcmpeqd */
7400 case 0x0fc4: /* pinsrw */
7401 case 0x0fd1: /* psrlw */
7402 case 0x0fd2: /* psrld */
7403 case 0x0fd3: /* psrlq */
7404 case 0x0fd4: /* paddq */
7405 case 0x0fd5: /* pmullw */
7406 case 0xf20fd6: /* movdq2q */
7407 case 0x0fd8: /* psubusb */
7408 case 0x0fd9: /* psubusw */
7409 case 0x0fda: /* pminub */
7410 case 0x0fdb: /* pand */
7411 case 0x0fdc: /* paddusb */
7412 case 0x0fdd: /* paddusw */
7413 case 0x0fde: /* pmaxub */
7414 case 0x0fdf: /* pandn */
7415 case 0x0fe0: /* pavgb */
7416 case 0x0fe1: /* psraw */
7417 case 0x0fe2: /* psrad */
7418 case 0x0fe3: /* pavgw */
7419 case 0x0fe4: /* pmulhuw */
7420 case 0x0fe5: /* pmulhw */
7421 case 0x0fe8: /* psubsb */
7422 case 0x0fe9: /* psubsw */
7423 case 0x0fea: /* pminsw */
7424 case 0x0feb: /* por */
7425 case 0x0fec: /* paddsb */
7426 case 0x0fed: /* paddsw */
7427 case 0x0fee: /* pmaxsw */
7428 case 0x0fef: /* pxor */
7429 case 0x0ff1: /* psllw */
7430 case 0x0ff2: /* pslld */
7431 case 0x0ff3: /* psllq */
7432 case 0x0ff4: /* pmuludq */
7433 case 0x0ff5: /* pmaddwd */
7434 case 0x0ff6: /* psadbw */
7435 case 0x0ff8: /* psubb */
7436 case 0x0ff9: /* psubw */
7437 case 0x0ffa: /* psubd */
7438 case 0x0ffb: /* psubq */
7439 case 0x0ffc: /* paddb */
7440 case 0x0ffd: /* paddw */
7441 case 0x0ffe: /* paddd */
7442 if (i386_record_modrm (&ir
))
7444 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.reg
))
7446 record_full_arch_list_add_reg (ir
.regcache
,
7447 I387_MM0_REGNUM (tdep
) + ir
.reg
);
7450 case 0x0f71: /* psllw */
7451 case 0x0f72: /* pslld */
7452 case 0x0f73: /* psllq */
7453 if (i386_record_modrm (&ir
))
7455 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.rm
))
7457 record_full_arch_list_add_reg (ir
.regcache
,
7458 I387_MM0_REGNUM (tdep
) + ir
.rm
);
7461 case 0x660f71: /* psllw */
7462 case 0x660f72: /* pslld */
7463 case 0x660f73: /* psllq */
7464 if (i386_record_modrm (&ir
))
7467 if (!i386_xmm_regnum_p (gdbarch
, I387_XMM0_REGNUM (tdep
) + ir
.rm
))
7469 record_full_arch_list_add_reg (ir
.regcache
,
7470 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
7473 case 0x0f7e: /* movd */
7474 case 0x660f7e: /* movd */
7475 if (i386_record_modrm (&ir
))
7478 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
7485 if (i386_record_lea_modrm (&ir
))
7490 case 0x0f7f: /* movq */
7491 if (i386_record_modrm (&ir
))
7495 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.rm
))
7497 record_full_arch_list_add_reg (ir
.regcache
,
7498 I387_MM0_REGNUM (tdep
) + ir
.rm
);
7503 if (i386_record_lea_modrm (&ir
))
7508 case 0xf30fb8: /* popcnt */
7509 if (i386_record_modrm (&ir
))
7511 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
7512 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7515 case 0x660fd6: /* movq */
7516 if (i386_record_modrm (&ir
))
7521 if (!i386_xmm_regnum_p (gdbarch
,
7522 I387_XMM0_REGNUM (tdep
) + ir
.rm
))
7524 record_full_arch_list_add_reg (ir
.regcache
,
7525 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
7530 if (i386_record_lea_modrm (&ir
))
7535 case 0x660f3817: /* ptest */
7536 case 0x0f2e: /* ucomiss */
7537 case 0x660f2e: /* ucomisd */
7538 case 0x0f2f: /* comiss */
7539 case 0x660f2f: /* comisd */
7540 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7543 case 0x0ff7: /* maskmovq */
7544 regcache_raw_read_unsigned (ir
.regcache
,
7545 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
7547 if (record_full_arch_list_add_mem (addr
, 64))
7551 case 0x660ff7: /* maskmovdqu */
7552 regcache_raw_read_unsigned (ir
.regcache
,
7553 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
7555 if (record_full_arch_list_add_mem (addr
, 128))
7570 /* In the future, maybe still need to deal with need_dasm. */
7571 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM
);
7572 if (record_full_arch_list_add_end ())
7578 printf_unfiltered (_("Process record does not support instruction 0x%02x "
7579 "at address %s.\n"),
7580 (unsigned int) (opcode
),
7581 paddress (gdbarch
, ir
.orig_addr
));
7585 static const int i386_record_regmap
[] =
7587 I386_EAX_REGNUM
, I386_ECX_REGNUM
, I386_EDX_REGNUM
, I386_EBX_REGNUM
,
7588 I386_ESP_REGNUM
, I386_EBP_REGNUM
, I386_ESI_REGNUM
, I386_EDI_REGNUM
,
7589 0, 0, 0, 0, 0, 0, 0, 0,
7590 I386_EIP_REGNUM
, I386_EFLAGS_REGNUM
, I386_CS_REGNUM
, I386_SS_REGNUM
,
7591 I386_DS_REGNUM
, I386_ES_REGNUM
, I386_FS_REGNUM
, I386_GS_REGNUM
7594 /* Check that the given address appears suitable for a fast
7595 tracepoint, which on x86-64 means that we need an instruction of at
7596 least 5 bytes, so that we can overwrite it with a 4-byte-offset
7597 jump and not have to worry about program jumps to an address in the
7598 middle of the tracepoint jump. On x86, it may be possible to use
7599 4-byte jumps with a 2-byte offset to a trampoline located in the
7600 bottom 64 KiB of memory. Returns 1 if OK, and writes a size
7601 of instruction to replace, and 0 if not, plus an explanatory
7605 i386_fast_tracepoint_valid_at (struct gdbarch
*gdbarch
,
7606 CORE_ADDR addr
, int *isize
, char **msg
)
7609 static struct ui_file
*gdb_null
= NULL
;
7611 /* Ask the target for the minimum instruction length supported. */
7612 jumplen
= target_get_min_fast_tracepoint_insn_len ();
7616 /* If the target does not support the get_min_fast_tracepoint_insn_len
7617 operation, assume that fast tracepoints will always be implemented
7618 using 4-byte relative jumps on both x86 and x86-64. */
7621 else if (jumplen
== 0)
7623 /* If the target does support get_min_fast_tracepoint_insn_len but
7624 returns zero, then the IPA has not loaded yet. In this case,
7625 we optimistically assume that truncated 2-byte relative jumps
7626 will be available on x86, and compensate later if this assumption
7627 turns out to be incorrect. On x86-64 architectures, 4-byte relative
7628 jumps will always be used. */
7629 jumplen
= (register_size (gdbarch
, 0) == 8) ? 5 : 4;
7632 /* Dummy file descriptor for the disassembler. */
7634 gdb_null
= ui_file_new ();
7636 /* Check for fit. */
7637 len
= gdb_print_insn (gdbarch
, addr
, gdb_null
, NULL
);
7643 /* Return a bit of target-specific detail to add to the caller's
7644 generic failure message. */
7646 *msg
= xstrprintf (_("; instruction is only %d bytes long, "
7647 "need at least %d bytes for the jump"),
7660 i386_validate_tdesc_p (struct gdbarch_tdep
*tdep
,
7661 struct tdesc_arch_data
*tdesc_data
)
7663 const struct target_desc
*tdesc
= tdep
->tdesc
;
7664 const struct tdesc_feature
*feature_core
;
7665 const struct tdesc_feature
*feature_sse
, *feature_avx
, *feature_mpx
;
7666 int i
, num_regs
, valid_p
;
7668 if (! tdesc_has_registers (tdesc
))
7671 /* Get core registers. */
7672 feature_core
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.core");
7673 if (feature_core
== NULL
)
7676 /* Get SSE registers. */
7677 feature_sse
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.sse");
7679 /* Try AVX registers. */
7680 feature_avx
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx");
7682 /* Try MPX registers. */
7683 feature_mpx
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.mpx");
7687 /* The XCR0 bits. */
7690 /* AVX register description requires SSE register description. */
7694 tdep
->xcr0
= I386_XSTATE_AVX_MASK
;
7696 /* It may have been set by OSABI initialization function. */
7697 if (tdep
->num_ymm_regs
== 0)
7699 tdep
->ymmh_register_names
= i386_ymmh_names
;
7700 tdep
->num_ymm_regs
= 8;
7701 tdep
->ymm0h_regnum
= I386_YMM0H_REGNUM
;
7704 for (i
= 0; i
< tdep
->num_ymm_regs
; i
++)
7705 valid_p
&= tdesc_numbered_register (feature_avx
, tdesc_data
,
7706 tdep
->ymm0h_regnum
+ i
,
7707 tdep
->ymmh_register_names
[i
]);
7709 else if (feature_sse
)
7710 tdep
->xcr0
= I386_XSTATE_SSE_MASK
;
7713 tdep
->xcr0
= I386_XSTATE_X87_MASK
;
7714 tdep
->num_xmm_regs
= 0;
7717 num_regs
= tdep
->num_core_regs
;
7718 for (i
= 0; i
< num_regs
; i
++)
7719 valid_p
&= tdesc_numbered_register (feature_core
, tdesc_data
, i
,
7720 tdep
->register_names
[i
]);
7724 /* Need to include %mxcsr, so add one. */
7725 num_regs
+= tdep
->num_xmm_regs
+ 1;
7726 for (; i
< num_regs
; i
++)
7727 valid_p
&= tdesc_numbered_register (feature_sse
, tdesc_data
, i
,
7728 tdep
->register_names
[i
]);
7733 tdep
->xcr0
= I386_XSTATE_MPX_MASK
;
7735 if (tdep
->bnd0r_regnum
< 0)
7737 tdep
->mpx_register_names
= i386_mpx_names
;
7738 tdep
->bnd0r_regnum
= I386_BND0R_REGNUM
;
7739 tdep
->bndcfgu_regnum
= I386_BNDCFGU_REGNUM
;
7742 for (i
= 0; i
< I387_NUM_MPX_REGS
; i
++)
7743 valid_p
&= tdesc_numbered_register (feature_mpx
, tdesc_data
,
7744 I387_BND0R_REGNUM (tdep
) + i
,
7745 tdep
->mpx_register_names
[i
]);
7752 static struct gdbarch
*
7753 i386_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
7755 struct gdbarch_tdep
*tdep
;
7756 struct gdbarch
*gdbarch
;
7757 struct tdesc_arch_data
*tdesc_data
;
7758 const struct target_desc
*tdesc
;
7764 /* If there is already a candidate, use it. */
7765 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
7767 return arches
->gdbarch
;
7769 /* Allocate space for the new architecture. */
7770 tdep
= XCALLOC (1, struct gdbarch_tdep
);
7771 gdbarch
= gdbarch_alloc (&info
, tdep
);
7773 /* General-purpose registers. */
7774 tdep
->gregset
= NULL
;
7775 tdep
->gregset_reg_offset
= NULL
;
7776 tdep
->gregset_num_regs
= I386_NUM_GREGS
;
7777 tdep
->sizeof_gregset
= 0;
7779 /* Floating-point registers. */
7780 tdep
->fpregset
= NULL
;
7781 tdep
->sizeof_fpregset
= I387_SIZEOF_FSAVE
;
7783 tdep
->xstateregset
= NULL
;
7785 /* The default settings include the FPU registers, the MMX registers
7786 and the SSE registers. This can be overridden for a specific ABI
7787 by adjusting the members `st0_regnum', `mm0_regnum' and
7788 `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers
7789 will show up in the output of "info all-registers". */
7791 tdep
->st0_regnum
= I386_ST0_REGNUM
;
7793 /* I386_NUM_XREGS includes %mxcsr, so substract one. */
7794 tdep
->num_xmm_regs
= I386_NUM_XREGS
- 1;
7796 tdep
->jb_pc_offset
= -1;
7797 tdep
->struct_return
= pcc_struct_return
;
7798 tdep
->sigtramp_start
= 0;
7799 tdep
->sigtramp_end
= 0;
7800 tdep
->sigtramp_p
= i386_sigtramp_p
;
7801 tdep
->sigcontext_addr
= NULL
;
7802 tdep
->sc_reg_offset
= NULL
;
7803 tdep
->sc_pc_offset
= -1;
7804 tdep
->sc_sp_offset
= -1;
7806 tdep
->xsave_xcr0_offset
= -1;
7808 tdep
->record_regmap
= i386_record_regmap
;
7810 set_gdbarch_long_long_align_bit (gdbarch
, 32);
7812 /* The format used for `long double' on almost all i386 targets is
7813 the i387 extended floating-point format. In fact, of all targets
7814 in the GCC 2.95 tree, only OSF/1 does it different, and insists
7815 on having a `long double' that's not `long' at all. */
7816 set_gdbarch_long_double_format (gdbarch
, floatformats_i387_ext
);
7818 /* Although the i387 extended floating-point has only 80 significant
7819 bits, a `long double' actually takes up 96, probably to enforce
7821 set_gdbarch_long_double_bit (gdbarch
, 96);
7823 /* Register numbers of various important registers. */
7824 set_gdbarch_sp_regnum (gdbarch
, I386_ESP_REGNUM
); /* %esp */
7825 set_gdbarch_pc_regnum (gdbarch
, I386_EIP_REGNUM
); /* %eip */
7826 set_gdbarch_ps_regnum (gdbarch
, I386_EFLAGS_REGNUM
); /* %eflags */
7827 set_gdbarch_fp0_regnum (gdbarch
, I386_ST0_REGNUM
); /* %st(0) */
7829 /* NOTE: kettenis/20040418: GCC does have two possible register
7830 numbering schemes on the i386: dbx and SVR4. These schemes
7831 differ in how they number %ebp, %esp, %eflags, and the
7832 floating-point registers, and are implemented by the arrays
7833 dbx_register_map[] and svr4_dbx_register_map in
7834 gcc/config/i386.c. GCC also defines a third numbering scheme in
7835 gcc/config/i386.c, which it designates as the "default" register
7836 map used in 64bit mode. This last register numbering scheme is
7837 implemented in dbx64_register_map, and is used for AMD64; see
7840 Currently, each GCC i386 target always uses the same register
7841 numbering scheme across all its supported debugging formats
7842 i.e. SDB (COFF), stabs and DWARF 2. This is because
7843 gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the
7844 DBX_REGISTER_NUMBER macro which is defined by each target's
7845 respective config header in a manner independent of the requested
7846 output debugging format.
7848 This does not match the arrangement below, which presumes that
7849 the SDB and stabs numbering schemes differ from the DWARF and
7850 DWARF 2 ones. The reason for this arrangement is that it is
7851 likely to get the numbering scheme for the target's
7852 default/native debug format right. For targets where GCC is the
7853 native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for
7854 targets where the native toolchain uses a different numbering
7855 scheme for a particular debug format (stabs-in-ELF on Solaris)
7856 the defaults below will have to be overridden, like
7857 i386_elf_init_abi() does. */
7859 /* Use the dbx register numbering scheme for stabs and COFF. */
7860 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
7861 set_gdbarch_sdb_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
7863 /* Use the SVR4 register numbering scheme for DWARF 2. */
7864 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
7866 /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to
7867 be in use on any of the supported i386 targets. */
7869 set_gdbarch_print_float_info (gdbarch
, i387_print_float_info
);
7871 set_gdbarch_get_longjmp_target (gdbarch
, i386_get_longjmp_target
);
7873 /* Call dummy code. */
7874 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
7875 set_gdbarch_push_dummy_code (gdbarch
, i386_push_dummy_code
);
7876 set_gdbarch_push_dummy_call (gdbarch
, i386_push_dummy_call
);
7877 set_gdbarch_frame_align (gdbarch
, i386_frame_align
);
7879 set_gdbarch_convert_register_p (gdbarch
, i386_convert_register_p
);
7880 set_gdbarch_register_to_value (gdbarch
, i386_register_to_value
);
7881 set_gdbarch_value_to_register (gdbarch
, i386_value_to_register
);
7883 set_gdbarch_return_value (gdbarch
, i386_return_value
);
7885 set_gdbarch_skip_prologue (gdbarch
, i386_skip_prologue
);
7887 /* Stack grows downward. */
7888 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
7890 set_gdbarch_breakpoint_from_pc (gdbarch
, i386_breakpoint_from_pc
);
7891 set_gdbarch_decr_pc_after_break (gdbarch
, 1);
7892 set_gdbarch_max_insn_length (gdbarch
, I386_MAX_INSN_LEN
);
7894 set_gdbarch_frame_args_skip (gdbarch
, 8);
7896 set_gdbarch_print_insn (gdbarch
, i386_print_insn
);
7898 set_gdbarch_dummy_id (gdbarch
, i386_dummy_id
);
7900 set_gdbarch_unwind_pc (gdbarch
, i386_unwind_pc
);
7902 /* Add the i386 register groups. */
7903 i386_add_reggroups (gdbarch
);
7904 tdep
->register_reggroup_p
= i386_register_reggroup_p
;
7906 /* Helper for function argument information. */
7907 set_gdbarch_fetch_pointer_argument (gdbarch
, i386_fetch_pointer_argument
);
7909 /* Hook the function epilogue frame unwinder. This unwinder is
7910 appended to the list first, so that it supercedes the DWARF
7911 unwinder in function epilogues (where the DWARF unwinder
7912 currently fails). */
7913 frame_unwind_append_unwinder (gdbarch
, &i386_epilogue_frame_unwind
);
7915 /* Hook in the DWARF CFI frame unwinder. This unwinder is appended
7916 to the list before the prologue-based unwinders, so that DWARF
7917 CFI info will be used if it is available. */
7918 dwarf2_append_unwinders (gdbarch
);
7920 frame_base_set_default (gdbarch
, &i386_frame_base
);
7922 /* Pseudo registers may be changed by amd64_init_abi. */
7923 set_gdbarch_pseudo_register_read_value (gdbarch
,
7924 i386_pseudo_register_read_value
);
7925 set_gdbarch_pseudo_register_write (gdbarch
, i386_pseudo_register_write
);
7927 set_tdesc_pseudo_register_type (gdbarch
, i386_pseudo_register_type
);
7928 set_tdesc_pseudo_register_name (gdbarch
, i386_pseudo_register_name
);
7930 /* Override the normal target description method to make the AVX
7931 upper halves anonymous. */
7932 set_gdbarch_register_name (gdbarch
, i386_register_name
);
7934 /* Even though the default ABI only includes general-purpose registers,
7935 floating-point registers and the SSE registers, we have to leave a
7936 gap for the upper AVX registers and the MPX registers. */
7937 set_gdbarch_num_regs (gdbarch
, I386_MPX_NUM_REGS
);
7939 /* Get the x86 target description from INFO. */
7940 tdesc
= info
.target_desc
;
7941 if (! tdesc_has_registers (tdesc
))
7943 tdep
->tdesc
= tdesc
;
7945 tdep
->num_core_regs
= I386_NUM_GREGS
+ I387_NUM_REGS
;
7946 tdep
->register_names
= i386_register_names
;
7948 /* No upper YMM registers. */
7949 tdep
->ymmh_register_names
= NULL
;
7950 tdep
->ymm0h_regnum
= -1;
7952 tdep
->num_byte_regs
= 8;
7953 tdep
->num_word_regs
= 8;
7954 tdep
->num_dword_regs
= 0;
7955 tdep
->num_mmx_regs
= 8;
7956 tdep
->num_ymm_regs
= 0;
7958 /* No MPX registers. */
7959 tdep
->bnd0r_regnum
= -1;
7960 tdep
->bndcfgu_regnum
= -1;
7962 tdesc_data
= tdesc_data_alloc ();
7964 set_gdbarch_relocate_instruction (gdbarch
, i386_relocate_instruction
);
7966 set_gdbarch_gen_return_address (gdbarch
, i386_gen_return_address
);
7968 /* Hook in ABI-specific overrides, if they have been registered. */
7969 info
.tdep_info
= (void *) tdesc_data
;
7970 gdbarch_init_osabi (info
, gdbarch
);
7972 if (!i386_validate_tdesc_p (tdep
, tdesc_data
))
7974 tdesc_data_cleanup (tdesc_data
);
7976 gdbarch_free (gdbarch
);
7980 num_bnd_cooked
= (tdep
->bnd0r_regnum
> 0 ? I387_NUM_BND_REGS
: 0);
7982 /* Wire in pseudo registers. Number of pseudo registers may be
7984 set_gdbarch_num_pseudo_regs (gdbarch
, (tdep
->num_byte_regs
7985 + tdep
->num_word_regs
7986 + tdep
->num_dword_regs
7987 + tdep
->num_mmx_regs
7988 + tdep
->num_ymm_regs
7991 /* Target description may be changed. */
7992 tdesc
= tdep
->tdesc
;
7994 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
7996 /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */
7997 set_gdbarch_register_reggroup_p (gdbarch
, tdep
->register_reggroup_p
);
7999 /* Make %al the first pseudo-register. */
8000 tdep
->al_regnum
= gdbarch_num_regs (gdbarch
);
8001 tdep
->ax_regnum
= tdep
->al_regnum
+ tdep
->num_byte_regs
;
8003 ymm0_regnum
= tdep
->ax_regnum
+ tdep
->num_word_regs
;
8004 if (tdep
->num_dword_regs
)
8006 /* Support dword pseudo-register if it hasn't been disabled. */
8007 tdep
->eax_regnum
= ymm0_regnum
;
8008 ymm0_regnum
+= tdep
->num_dword_regs
;
8011 tdep
->eax_regnum
= -1;
8013 mm0_regnum
= ymm0_regnum
;
8014 if (tdep
->num_ymm_regs
)
8016 /* Support YMM pseudo-register if it is available. */
8017 tdep
->ymm0_regnum
= ymm0_regnum
;
8018 mm0_regnum
+= tdep
->num_ymm_regs
;
8021 tdep
->ymm0_regnum
= -1;
8023 bnd0_regnum
= mm0_regnum
;
8024 if (tdep
->num_mmx_regs
!= 0)
8026 /* Support MMX pseudo-register if MMX hasn't been disabled. */
8027 tdep
->mm0_regnum
= mm0_regnum
;
8028 bnd0_regnum
+= tdep
->num_mmx_regs
;
8031 tdep
->mm0_regnum
= -1;
8033 if (tdep
->bnd0r_regnum
> 0)
8034 tdep
->bnd0_regnum
= bnd0_regnum
;
8036 tdep
-> bnd0_regnum
= -1;
8038 /* Hook in the legacy prologue-based unwinders last (fallback). */
8039 frame_unwind_append_unwinder (gdbarch
, &i386_stack_tramp_frame_unwind
);
8040 frame_unwind_append_unwinder (gdbarch
, &i386_sigtramp_frame_unwind
);
8041 frame_unwind_append_unwinder (gdbarch
, &i386_frame_unwind
);
8043 /* If we have a register mapping, enable the generic core file
8044 support, unless it has already been enabled. */
8045 if (tdep
->gregset_reg_offset
8046 && !gdbarch_regset_from_core_section_p (gdbarch
))
8047 set_gdbarch_regset_from_core_section (gdbarch
,
8048 i386_regset_from_core_section
);
8050 set_gdbarch_skip_permanent_breakpoint (gdbarch
,
8051 i386_skip_permanent_breakpoint
);
8053 set_gdbarch_fast_tracepoint_valid_at (gdbarch
,
8054 i386_fast_tracepoint_valid_at
);
8059 static enum gdb_osabi
8060 i386_coff_osabi_sniffer (bfd
*abfd
)
8062 if (strcmp (bfd_get_target (abfd
), "coff-go32-exe") == 0
8063 || strcmp (bfd_get_target (abfd
), "coff-go32") == 0)
8064 return GDB_OSABI_GO32
;
8066 return GDB_OSABI_UNKNOWN
;
8070 /* Provide a prototype to silence -Wmissing-prototypes. */
8071 void _initialize_i386_tdep (void);
8074 _initialize_i386_tdep (void)
8076 register_gdbarch_init (bfd_arch_i386
, i386_gdbarch_init
);
8078 /* Add the variable that controls the disassembly flavor. */
8079 add_setshow_enum_cmd ("disassembly-flavor", no_class
, valid_flavors
,
8080 &disassembly_flavor
, _("\
8081 Set the disassembly flavor."), _("\
8082 Show the disassembly flavor."), _("\
8083 The valid values are \"att\" and \"intel\", and the default value is \"att\"."),
8085 NULL
, /* FIXME: i18n: */
8086 &setlist
, &showlist
);
8088 /* Add the variable that controls the convention for returning
8090 add_setshow_enum_cmd ("struct-convention", no_class
, valid_conventions
,
8091 &struct_convention
, _("\
8092 Set the convention for returning small structs."), _("\
8093 Show the convention for returning small structs."), _("\
8094 Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\
8097 NULL
, /* FIXME: i18n: */
8098 &setlist
, &showlist
);
8100 gdbarch_register_osabi_sniffer (bfd_arch_i386
, bfd_target_coff_flavour
,
8101 i386_coff_osabi_sniffer
);
8103 gdbarch_register_osabi (bfd_arch_i386
, 0, GDB_OSABI_SVR4
,
8104 i386_svr4_init_abi
);
8105 gdbarch_register_osabi (bfd_arch_i386
, 0, GDB_OSABI_GO32
,
8106 i386_go32_init_abi
);
8108 /* Initialize the i386-specific register groups. */
8109 i386_init_reggroups ();
8111 /* Initialize the standard target descriptions. */
8112 initialize_tdesc_i386 ();
8113 initialize_tdesc_i386_mmx ();
8114 initialize_tdesc_i386_avx ();
8115 initialize_tdesc_i386_mpx ();
8117 /* Tell remote stub that we support XML target description. */
8118 register_remote_support_xml ("i386");