1 /* Intel 386 target-dependent stuff.
3 Copyright (C) 1988-2012 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "opcode/i386.h"
22 #include "arch-utils.h"
24 #include "dummy-frame.h"
25 #include "dwarf2-frame.h"
28 #include "frame-base.h"
29 #include "frame-unwind.h"
37 #include "reggroups.h"
46 #include "exceptions.h"
47 #include "gdb_assert.h"
48 #include "gdb_string.h"
50 #include "i386-tdep.h"
51 #include "i387-tdep.h"
52 #include "i386-xstate.h"
57 #include "features/i386/i386.c"
58 #include "features/i386/i386-avx.c"
59 #include "features/i386/i386-mmx.c"
64 #include "stap-probe.h"
65 #include "user-regs.h"
66 #include "cli/cli-utils.h"
67 #include "expression.h"
68 #include "parser-defs.h"
73 static const char *i386_register_names
[] =
75 "eax", "ecx", "edx", "ebx",
76 "esp", "ebp", "esi", "edi",
77 "eip", "eflags", "cs", "ss",
78 "ds", "es", "fs", "gs",
79 "st0", "st1", "st2", "st3",
80 "st4", "st5", "st6", "st7",
81 "fctrl", "fstat", "ftag", "fiseg",
82 "fioff", "foseg", "fooff", "fop",
83 "xmm0", "xmm1", "xmm2", "xmm3",
84 "xmm4", "xmm5", "xmm6", "xmm7",
88 static const char *i386_ymm_names
[] =
90 "ymm0", "ymm1", "ymm2", "ymm3",
91 "ymm4", "ymm5", "ymm6", "ymm7",
94 static const char *i386_ymmh_names
[] =
96 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
97 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
100 /* Register names for MMX pseudo-registers. */
102 static const char *i386_mmx_names
[] =
104 "mm0", "mm1", "mm2", "mm3",
105 "mm4", "mm5", "mm6", "mm7"
108 /* Register names for byte pseudo-registers. */
110 static const char *i386_byte_names
[] =
112 "al", "cl", "dl", "bl",
113 "ah", "ch", "dh", "bh"
116 /* Register names for word pseudo-registers. */
118 static const char *i386_word_names
[] =
120 "ax", "cx", "dx", "bx",
127 i386_mmx_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
129 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
130 int mm0_regnum
= tdep
->mm0_regnum
;
135 regnum
-= mm0_regnum
;
136 return regnum
>= 0 && regnum
< tdep
->num_mmx_regs
;
142 i386_byte_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
144 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
146 regnum
-= tdep
->al_regnum
;
147 return regnum
>= 0 && regnum
< tdep
->num_byte_regs
;
153 i386_word_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
155 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
157 regnum
-= tdep
->ax_regnum
;
158 return regnum
>= 0 && regnum
< tdep
->num_word_regs
;
161 /* Dword register? */
164 i386_dword_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
166 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
167 int eax_regnum
= tdep
->eax_regnum
;
172 regnum
-= eax_regnum
;
173 return regnum
>= 0 && regnum
< tdep
->num_dword_regs
;
177 i386_ymmh_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
179 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
180 int ymm0h_regnum
= tdep
->ymm0h_regnum
;
182 if (ymm0h_regnum
< 0)
185 regnum
-= ymm0h_regnum
;
186 return regnum
>= 0 && regnum
< tdep
->num_ymm_regs
;
192 i386_ymm_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
194 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
195 int ymm0_regnum
= tdep
->ymm0_regnum
;
200 regnum
-= ymm0_regnum
;
201 return regnum
>= 0 && regnum
< tdep
->num_ymm_regs
;
207 i386_xmm_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
209 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
210 int num_xmm_regs
= I387_NUM_XMM_REGS (tdep
);
212 if (num_xmm_regs
== 0)
215 regnum
-= I387_XMM0_REGNUM (tdep
);
216 return regnum
>= 0 && regnum
< num_xmm_regs
;
220 i386_mxcsr_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
222 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
224 if (I387_NUM_XMM_REGS (tdep
) == 0)
227 return (regnum
== I387_MXCSR_REGNUM (tdep
));
233 i386_fp_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
235 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
237 if (I387_ST0_REGNUM (tdep
) < 0)
240 return (I387_ST0_REGNUM (tdep
) <= regnum
241 && regnum
< I387_FCTRL_REGNUM (tdep
));
245 i386_fpc_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
247 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
249 if (I387_ST0_REGNUM (tdep
) < 0)
252 return (I387_FCTRL_REGNUM (tdep
) <= regnum
253 && regnum
< I387_XMM0_REGNUM (tdep
));
256 /* Return the name of register REGNUM, or the empty string if it is
257 an anonymous register. */
260 i386_register_name (struct gdbarch
*gdbarch
, int regnum
)
262 /* Hide the upper YMM registers. */
263 if (i386_ymmh_regnum_p (gdbarch
, regnum
))
266 return tdesc_register_name (gdbarch
, regnum
);
269 /* Return the name of register REGNUM. */
272 i386_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
274 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
275 if (i386_mmx_regnum_p (gdbarch
, regnum
))
276 return i386_mmx_names
[regnum
- I387_MM0_REGNUM (tdep
)];
277 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
278 return i386_ymm_names
[regnum
- tdep
->ymm0_regnum
];
279 else if (i386_byte_regnum_p (gdbarch
, regnum
))
280 return i386_byte_names
[regnum
- tdep
->al_regnum
];
281 else if (i386_word_regnum_p (gdbarch
, regnum
))
282 return i386_word_names
[regnum
- tdep
->ax_regnum
];
284 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
287 /* Convert a dbx register number REG to the appropriate register
288 number used by GDB. */
291 i386_dbx_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
293 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
295 /* This implements what GCC calls the "default" register map
296 (dbx_register_map[]). */
298 if (reg
>= 0 && reg
<= 7)
300 /* General-purpose registers. The debug info calls %ebp
301 register 4, and %esp register 5. */
308 else if (reg
>= 12 && reg
<= 19)
310 /* Floating-point registers. */
311 return reg
- 12 + I387_ST0_REGNUM (tdep
);
313 else if (reg
>= 21 && reg
<= 28)
316 int ymm0_regnum
= tdep
->ymm0_regnum
;
319 && i386_xmm_regnum_p (gdbarch
, reg
))
320 return reg
- 21 + ymm0_regnum
;
322 return reg
- 21 + I387_XMM0_REGNUM (tdep
);
324 else if (reg
>= 29 && reg
<= 36)
327 return reg
- 29 + I387_MM0_REGNUM (tdep
);
330 /* This will hopefully provoke a warning. */
331 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
334 /* Convert SVR4 register number REG to the appropriate register number
338 i386_svr4_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
340 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
342 /* This implements the GCC register map that tries to be compatible
343 with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */
345 /* The SVR4 register numbering includes %eip and %eflags, and
346 numbers the floating point registers differently. */
347 if (reg
>= 0 && reg
<= 9)
349 /* General-purpose registers. */
352 else if (reg
>= 11 && reg
<= 18)
354 /* Floating-point registers. */
355 return reg
- 11 + I387_ST0_REGNUM (tdep
);
357 else if (reg
>= 21 && reg
<= 36)
359 /* The SSE and MMX registers have the same numbers as with dbx. */
360 return i386_dbx_reg_to_regnum (gdbarch
, reg
);
365 case 37: return I387_FCTRL_REGNUM (tdep
);
366 case 38: return I387_FSTAT_REGNUM (tdep
);
367 case 39: return I387_MXCSR_REGNUM (tdep
);
368 case 40: return I386_ES_REGNUM
;
369 case 41: return I386_CS_REGNUM
;
370 case 42: return I386_SS_REGNUM
;
371 case 43: return I386_DS_REGNUM
;
372 case 44: return I386_FS_REGNUM
;
373 case 45: return I386_GS_REGNUM
;
376 /* This will hopefully provoke a warning. */
377 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
382 /* This is the variable that is set with "set disassembly-flavor", and
383 its legitimate values. */
384 static const char att_flavor
[] = "att";
385 static const char intel_flavor
[] = "intel";
386 static const char *const valid_flavors
[] =
392 static const char *disassembly_flavor
= att_flavor
;
395 /* Use the program counter to determine the contents and size of a
396 breakpoint instruction. Return a pointer to a string of bytes that
397 encode a breakpoint instruction, store the length of the string in
398 *LEN and optionally adjust *PC to point to the correct memory
399 location for inserting the breakpoint.
401 On the i386 we have a single breakpoint that fits in a single byte
402 and can be inserted anywhere.
404 This function is 64-bit safe. */
406 static const gdb_byte
*
407 i386_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pc
, int *len
)
409 static gdb_byte break_insn
[] = { 0xcc }; /* int 3 */
411 *len
= sizeof (break_insn
);
415 /* Displaced instruction handling. */
417 /* Skip the legacy instruction prefixes in INSN.
418 Not all prefixes are valid for any particular insn
419 but we needn't care, the insn will fault if it's invalid.
420 The result is a pointer to the first opcode byte,
421 or NULL if we run off the end of the buffer. */
424 i386_skip_prefixes (gdb_byte
*insn
, size_t max_len
)
426 gdb_byte
*end
= insn
+ max_len
;
432 case DATA_PREFIX_OPCODE
:
433 case ADDR_PREFIX_OPCODE
:
434 case CS_PREFIX_OPCODE
:
435 case DS_PREFIX_OPCODE
:
436 case ES_PREFIX_OPCODE
:
437 case FS_PREFIX_OPCODE
:
438 case GS_PREFIX_OPCODE
:
439 case SS_PREFIX_OPCODE
:
440 case LOCK_PREFIX_OPCODE
:
441 case REPE_PREFIX_OPCODE
:
442 case REPNE_PREFIX_OPCODE
:
454 i386_absolute_jmp_p (const gdb_byte
*insn
)
456 /* jmp far (absolute address in operand). */
462 /* jump near, absolute indirect (/4). */
463 if ((insn
[1] & 0x38) == 0x20)
466 /* jump far, absolute indirect (/5). */
467 if ((insn
[1] & 0x38) == 0x28)
475 i386_absolute_call_p (const gdb_byte
*insn
)
477 /* call far, absolute. */
483 /* Call near, absolute indirect (/2). */
484 if ((insn
[1] & 0x38) == 0x10)
487 /* Call far, absolute indirect (/3). */
488 if ((insn
[1] & 0x38) == 0x18)
496 i386_ret_p (const gdb_byte
*insn
)
500 case 0xc2: /* ret near, pop N bytes. */
501 case 0xc3: /* ret near */
502 case 0xca: /* ret far, pop N bytes. */
503 case 0xcb: /* ret far */
504 case 0xcf: /* iret */
513 i386_call_p (const gdb_byte
*insn
)
515 if (i386_absolute_call_p (insn
))
518 /* call near, relative. */
525 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
526 length in bytes. Otherwise, return zero. */
529 i386_syscall_p (const gdb_byte
*insn
, int *lengthp
)
531 /* Is it 'int $0x80'? */
532 if ((insn
[0] == 0xcd && insn
[1] == 0x80)
533 /* Or is it 'sysenter'? */
534 || (insn
[0] == 0x0f && insn
[1] == 0x34)
535 /* Or is it 'syscall'? */
536 || (insn
[0] == 0x0f && insn
[1] == 0x05))
545 /* Some kernels may run one past a syscall insn, so we have to cope.
546 Otherwise this is just simple_displaced_step_copy_insn. */
548 struct displaced_step_closure
*
549 i386_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
550 CORE_ADDR from
, CORE_ADDR to
,
551 struct regcache
*regs
)
553 size_t len
= gdbarch_max_insn_length (gdbarch
);
554 gdb_byte
*buf
= xmalloc (len
);
556 read_memory (from
, buf
, len
);
558 /* GDB may get control back after the insn after the syscall.
559 Presumably this is a kernel bug.
560 If this is a syscall, make sure there's a nop afterwards. */
565 insn
= i386_skip_prefixes (buf
, len
);
566 if (insn
!= NULL
&& i386_syscall_p (insn
, &syscall_length
))
567 insn
[syscall_length
] = NOP_OPCODE
;
570 write_memory (to
, buf
, len
);
574 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
575 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
576 displaced_step_dump_bytes (gdb_stdlog
, buf
, len
);
579 return (struct displaced_step_closure
*) buf
;
582 /* Fix up the state of registers and memory after having single-stepped
583 a displaced instruction. */
586 i386_displaced_step_fixup (struct gdbarch
*gdbarch
,
587 struct displaced_step_closure
*closure
,
588 CORE_ADDR from
, CORE_ADDR to
,
589 struct regcache
*regs
)
591 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
593 /* The offset we applied to the instruction's address.
594 This could well be negative (when viewed as a signed 32-bit
595 value), but ULONGEST won't reflect that, so take care when
597 ULONGEST insn_offset
= to
- from
;
599 /* Since we use simple_displaced_step_copy_insn, our closure is a
600 copy of the instruction. */
601 gdb_byte
*insn
= (gdb_byte
*) closure
;
602 /* The start of the insn, needed in case we see some prefixes. */
603 gdb_byte
*insn_start
= insn
;
606 fprintf_unfiltered (gdb_stdlog
,
607 "displaced: fixup (%s, %s), "
608 "insn = 0x%02x 0x%02x ...\n",
609 paddress (gdbarch
, from
), paddress (gdbarch
, to
),
612 /* The list of issues to contend with here is taken from
613 resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20.
614 Yay for Free Software! */
616 /* Relocate the %eip, if necessary. */
618 /* The instruction recognizers we use assume any leading prefixes
619 have been skipped. */
621 /* This is the size of the buffer in closure. */
622 size_t max_insn_len
= gdbarch_max_insn_length (gdbarch
);
623 gdb_byte
*opcode
= i386_skip_prefixes (insn
, max_insn_len
);
624 /* If there are too many prefixes, just ignore the insn.
625 It will fault when run. */
630 /* Except in the case of absolute or indirect jump or call
631 instructions, or a return instruction, the new eip is relative to
632 the displaced instruction; make it relative. Well, signal
633 handler returns don't need relocation either, but we use the
634 value of %eip to recognize those; see below. */
635 if (! i386_absolute_jmp_p (insn
)
636 && ! i386_absolute_call_p (insn
)
637 && ! i386_ret_p (insn
))
642 regcache_cooked_read_unsigned (regs
, I386_EIP_REGNUM
, &orig_eip
);
644 /* A signal trampoline system call changes the %eip, resuming
645 execution of the main program after the signal handler has
646 returned. That makes them like 'return' instructions; we
647 shouldn't relocate %eip.
649 But most system calls don't, and we do need to relocate %eip.
651 Our heuristic for distinguishing these cases: if stepping
652 over the system call instruction left control directly after
653 the instruction, the we relocate --- control almost certainly
654 doesn't belong in the displaced copy. Otherwise, we assume
655 the instruction has put control where it belongs, and leave
656 it unrelocated. Goodness help us if there are PC-relative
658 if (i386_syscall_p (insn
, &insn_len
)
659 && orig_eip
!= to
+ (insn
- insn_start
) + insn_len
660 /* GDB can get control back after the insn after the syscall.
661 Presumably this is a kernel bug.
662 i386_displaced_step_copy_insn ensures its a nop,
663 we add one to the length for it. */
664 && orig_eip
!= to
+ (insn
- insn_start
) + insn_len
+ 1)
667 fprintf_unfiltered (gdb_stdlog
,
668 "displaced: syscall changed %%eip; "
673 ULONGEST eip
= (orig_eip
- insn_offset
) & 0xffffffffUL
;
675 /* If we just stepped over a breakpoint insn, we don't backup
676 the pc on purpose; this is to match behaviour without
679 regcache_cooked_write_unsigned (regs
, I386_EIP_REGNUM
, eip
);
682 fprintf_unfiltered (gdb_stdlog
,
684 "relocated %%eip from %s to %s\n",
685 paddress (gdbarch
, orig_eip
),
686 paddress (gdbarch
, eip
));
690 /* If the instruction was PUSHFL, then the TF bit will be set in the
691 pushed value, and should be cleared. We'll leave this for later,
692 since GDB already messes up the TF flag when stepping over a
695 /* If the instruction was a call, the return address now atop the
696 stack is the address following the copied instruction. We need
697 to make it the address following the original instruction. */
698 if (i386_call_p (insn
))
702 const ULONGEST retaddr_len
= 4;
704 regcache_cooked_read_unsigned (regs
, I386_ESP_REGNUM
, &esp
);
705 retaddr
= read_memory_unsigned_integer (esp
, retaddr_len
, byte_order
);
706 retaddr
= (retaddr
- insn_offset
) & 0xffffffffUL
;
707 write_memory_unsigned_integer (esp
, retaddr_len
, byte_order
, retaddr
);
710 fprintf_unfiltered (gdb_stdlog
,
711 "displaced: relocated return addr at %s to %s\n",
712 paddress (gdbarch
, esp
),
713 paddress (gdbarch
, retaddr
));
718 append_insns (CORE_ADDR
*to
, ULONGEST len
, const gdb_byte
*buf
)
720 target_write_memory (*to
, buf
, len
);
725 i386_relocate_instruction (struct gdbarch
*gdbarch
,
726 CORE_ADDR
*to
, CORE_ADDR oldloc
)
728 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
729 gdb_byte buf
[I386_MAX_INSN_LEN
];
730 int offset
= 0, rel32
, newrel
;
732 gdb_byte
*insn
= buf
;
734 read_memory (oldloc
, buf
, I386_MAX_INSN_LEN
);
736 insn_length
= gdb_buffered_insn_length (gdbarch
, insn
,
737 I386_MAX_INSN_LEN
, oldloc
);
739 /* Get past the prefixes. */
740 insn
= i386_skip_prefixes (insn
, I386_MAX_INSN_LEN
);
742 /* Adjust calls with 32-bit relative addresses as push/jump, with
743 the address pushed being the location where the original call in
744 the user program would return to. */
747 gdb_byte push_buf
[16];
748 unsigned int ret_addr
;
750 /* Where "ret" in the original code will return to. */
751 ret_addr
= oldloc
+ insn_length
;
752 push_buf
[0] = 0x68; /* pushq $... */
753 memcpy (&push_buf
[1], &ret_addr
, 4);
755 append_insns (to
, 5, push_buf
);
757 /* Convert the relative call to a relative jump. */
760 /* Adjust the destination offset. */
761 rel32
= extract_signed_integer (insn
+ 1, 4, byte_order
);
762 newrel
= (oldloc
- *to
) + rel32
;
763 store_signed_integer (insn
+ 1, 4, byte_order
, newrel
);
766 fprintf_unfiltered (gdb_stdlog
,
767 "Adjusted insn rel32=%s at %s to"
769 hex_string (rel32
), paddress (gdbarch
, oldloc
),
770 hex_string (newrel
), paddress (gdbarch
, *to
));
772 /* Write the adjusted jump into its displaced location. */
773 append_insns (to
, 5, insn
);
777 /* Adjust jumps with 32-bit relative addresses. Calls are already
781 /* Adjust conditional jumps. */
782 else if (insn
[0] == 0x0f && (insn
[1] & 0xf0) == 0x80)
787 rel32
= extract_signed_integer (insn
+ offset
, 4, byte_order
);
788 newrel
= (oldloc
- *to
) + rel32
;
789 store_signed_integer (insn
+ offset
, 4, byte_order
, newrel
);
791 fprintf_unfiltered (gdb_stdlog
,
792 "Adjusted insn rel32=%s at %s to"
794 hex_string (rel32
), paddress (gdbarch
, oldloc
),
795 hex_string (newrel
), paddress (gdbarch
, *to
));
798 /* Write the adjusted instructions into their displaced
800 append_insns (to
, insn_length
, buf
);
804 #ifdef I386_REGNO_TO_SYMMETRY
805 #error "The Sequent Symmetry is no longer supported."
808 /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi
809 and %esp "belong" to the calling function. Therefore these
810 registers should be saved if they're going to be modified. */
812 /* The maximum number of saved registers. This should include all
813 registers mentioned above, and %eip. */
814 #define I386_NUM_SAVED_REGS I386_NUM_GREGS
816 struct i386_frame_cache
824 /* Saved registers. */
825 CORE_ADDR saved_regs
[I386_NUM_SAVED_REGS
];
830 /* Stack space reserved for local variables. */
834 /* Allocate and initialize a frame cache. */
836 static struct i386_frame_cache
*
837 i386_alloc_frame_cache (void)
839 struct i386_frame_cache
*cache
;
842 cache
= FRAME_OBSTACK_ZALLOC (struct i386_frame_cache
);
847 cache
->sp_offset
= -4;
850 /* Saved registers. We initialize these to -1 since zero is a valid
851 offset (that's where %ebp is supposed to be stored). */
852 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
853 cache
->saved_regs
[i
] = -1;
855 cache
->saved_sp_reg
= -1;
856 cache
->pc_in_eax
= 0;
858 /* Frameless until proven otherwise. */
864 /* If the instruction at PC is a jump, return the address of its
865 target. Otherwise, return PC. */
868 i386_follow_jump (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
870 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
875 if (target_read_memory (pc
, &op
, 1))
881 op
= read_memory_unsigned_integer (pc
+ 1, 1, byte_order
);
887 /* Relative jump: if data16 == 0, disp32, else disp16. */
890 delta
= read_memory_integer (pc
+ 2, 2, byte_order
);
892 /* Include the size of the jmp instruction (including the
898 delta
= read_memory_integer (pc
+ 1, 4, byte_order
);
900 /* Include the size of the jmp instruction. */
905 /* Relative jump, disp8 (ignore data16). */
906 delta
= read_memory_integer (pc
+ data16
+ 1, 1, byte_order
);
915 /* Check whether PC points at a prologue for a function returning a
916 structure or union. If so, it updates CACHE and returns the
917 address of the first instruction after the code sequence that
918 removes the "hidden" argument from the stack or CURRENT_PC,
919 whichever is smaller. Otherwise, return PC. */
922 i386_analyze_struct_return (CORE_ADDR pc
, CORE_ADDR current_pc
,
923 struct i386_frame_cache
*cache
)
925 /* Functions that return a structure or union start with:
928 xchgl %eax, (%esp) 0x87 0x04 0x24
929 or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00
931 (the System V compiler puts out the second `xchg' instruction,
932 and the assembler doesn't try to optimize it, so the 'sib' form
933 gets generated). This sequence is used to get the address of the
934 return buffer for a function that returns a structure. */
935 static gdb_byte proto1
[3] = { 0x87, 0x04, 0x24 };
936 static gdb_byte proto2
[4] = { 0x87, 0x44, 0x24, 0x00 };
940 if (current_pc
<= pc
)
943 if (target_read_memory (pc
, &op
, 1))
946 if (op
!= 0x58) /* popl %eax */
949 if (target_read_memory (pc
+ 1, buf
, 4))
952 if (memcmp (buf
, proto1
, 3) != 0 && memcmp (buf
, proto2
, 4) != 0)
955 if (current_pc
== pc
)
957 cache
->sp_offset
+= 4;
961 if (current_pc
== pc
+ 1)
963 cache
->pc_in_eax
= 1;
967 if (buf
[1] == proto1
[1])
974 i386_skip_probe (CORE_ADDR pc
)
976 /* A function may start with
990 if (target_read_memory (pc
, &op
, 1))
993 if (op
== 0x68 || op
== 0x6a)
997 /* Skip past the `pushl' instruction; it has either a one-byte or a
998 four-byte operand, depending on the opcode. */
1004 /* Read the following 8 bytes, which should be `call _probe' (6
1005 bytes) followed by `addl $4,%esp' (2 bytes). */
1006 read_memory (pc
+ delta
, buf
, sizeof (buf
));
1007 if (buf
[0] == 0xe8 && buf
[6] == 0xc4 && buf
[7] == 0x4)
1008 pc
+= delta
+ sizeof (buf
);
1014 /* GCC 4.1 and later, can put code in the prologue to realign the
1015 stack pointer. Check whether PC points to such code, and update
1016 CACHE accordingly. Return the first instruction after the code
1017 sequence or CURRENT_PC, whichever is smaller. If we don't
1018 recognize the code, return PC. */
1021 i386_analyze_stack_align (CORE_ADDR pc
, CORE_ADDR current_pc
,
1022 struct i386_frame_cache
*cache
)
1024 /* There are 2 code sequences to re-align stack before the frame
1027 1. Use a caller-saved saved register:
1033 2. Use a callee-saved saved register:
1040 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
1042 0x83 0xe4 0xf0 andl $-16, %esp
1043 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
1048 int offset
, offset_and
;
1049 static int regnums
[8] = {
1050 I386_EAX_REGNUM
, /* %eax */
1051 I386_ECX_REGNUM
, /* %ecx */
1052 I386_EDX_REGNUM
, /* %edx */
1053 I386_EBX_REGNUM
, /* %ebx */
1054 I386_ESP_REGNUM
, /* %esp */
1055 I386_EBP_REGNUM
, /* %ebp */
1056 I386_ESI_REGNUM
, /* %esi */
1057 I386_EDI_REGNUM
/* %edi */
1060 if (target_read_memory (pc
, buf
, sizeof buf
))
1063 /* Check caller-saved saved register. The first instruction has
1064 to be "leal 4(%esp), %reg". */
1065 if (buf
[0] == 0x8d && buf
[2] == 0x24 && buf
[3] == 0x4)
1067 /* MOD must be binary 10 and R/M must be binary 100. */
1068 if ((buf
[1] & 0xc7) != 0x44)
1071 /* REG has register number. */
1072 reg
= (buf
[1] >> 3) & 7;
1077 /* Check callee-saved saved register. The first instruction
1078 has to be "pushl %reg". */
1079 if ((buf
[0] & 0xf8) != 0x50)
1085 /* The next instruction has to be "leal 8(%esp), %reg". */
1086 if (buf
[1] != 0x8d || buf
[3] != 0x24 || buf
[4] != 0x8)
1089 /* MOD must be binary 10 and R/M must be binary 100. */
1090 if ((buf
[2] & 0xc7) != 0x44)
1093 /* REG has register number. Registers in pushl and leal have to
1095 if (reg
!= ((buf
[2] >> 3) & 7))
1101 /* Rigister can't be %esp nor %ebp. */
1102 if (reg
== 4 || reg
== 5)
1105 /* The next instruction has to be "andl $-XXX, %esp". */
1106 if (buf
[offset
+ 1] != 0xe4
1107 || (buf
[offset
] != 0x81 && buf
[offset
] != 0x83))
1110 offset_and
= offset
;
1111 offset
+= buf
[offset
] == 0x81 ? 6 : 3;
1113 /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is
1114 0xfc. REG must be binary 110 and MOD must be binary 01. */
1115 if (buf
[offset
] != 0xff
1116 || buf
[offset
+ 2] != 0xfc
1117 || (buf
[offset
+ 1] & 0xf8) != 0x70)
1120 /* R/M has register. Registers in leal and pushl have to be the
1122 if (reg
!= (buf
[offset
+ 1] & 7))
1125 if (current_pc
> pc
+ offset_and
)
1126 cache
->saved_sp_reg
= regnums
[reg
];
1128 return min (pc
+ offset
+ 3, current_pc
);
1131 /* Maximum instruction length we need to handle. */
1132 #define I386_MAX_MATCHED_INSN_LEN 6
1134 /* Instruction description. */
1138 gdb_byte insn
[I386_MAX_MATCHED_INSN_LEN
];
1139 gdb_byte mask
[I386_MAX_MATCHED_INSN_LEN
];
1142 /* Return whether instruction at PC matches PATTERN. */
1145 i386_match_pattern (CORE_ADDR pc
, struct i386_insn pattern
)
1149 if (target_read_memory (pc
, &op
, 1))
1152 if ((op
& pattern
.mask
[0]) == pattern
.insn
[0])
1154 gdb_byte buf
[I386_MAX_MATCHED_INSN_LEN
- 1];
1155 int insn_matched
= 1;
1158 gdb_assert (pattern
.len
> 1);
1159 gdb_assert (pattern
.len
<= I386_MAX_MATCHED_INSN_LEN
);
1161 if (target_read_memory (pc
+ 1, buf
, pattern
.len
- 1))
1164 for (i
= 1; i
< pattern
.len
; i
++)
1166 if ((buf
[i
- 1] & pattern
.mask
[i
]) != pattern
.insn
[i
])
1169 return insn_matched
;
1174 /* Search for the instruction at PC in the list INSN_PATTERNS. Return
1175 the first instruction description that matches. Otherwise, return
1178 static struct i386_insn
*
1179 i386_match_insn (CORE_ADDR pc
, struct i386_insn
*insn_patterns
)
1181 struct i386_insn
*pattern
;
1183 for (pattern
= insn_patterns
; pattern
->len
> 0; pattern
++)
1185 if (i386_match_pattern (pc
, *pattern
))
1192 /* Return whether PC points inside a sequence of instructions that
1193 matches INSN_PATTERNS. */
1196 i386_match_insn_block (CORE_ADDR pc
, struct i386_insn
*insn_patterns
)
1198 CORE_ADDR current_pc
;
1200 struct i386_insn
*insn
;
1202 insn
= i386_match_insn (pc
, insn_patterns
);
1207 ix
= insn
- insn_patterns
;
1208 for (i
= ix
- 1; i
>= 0; i
--)
1210 current_pc
-= insn_patterns
[i
].len
;
1212 if (!i386_match_pattern (current_pc
, insn_patterns
[i
]))
1216 current_pc
= pc
+ insn
->len
;
1217 for (insn
= insn_patterns
+ ix
+ 1; insn
->len
> 0; insn
++)
1219 if (!i386_match_pattern (current_pc
, *insn
))
1222 current_pc
+= insn
->len
;
1228 /* Some special instructions that might be migrated by GCC into the
1229 part of the prologue that sets up the new stack frame. Because the
1230 stack frame hasn't been setup yet, no registers have been saved
1231 yet, and only the scratch registers %eax, %ecx and %edx can be
1234 struct i386_insn i386_frame_setup_skip_insns
[] =
1236 /* Check for `movb imm8, r' and `movl imm32, r'.
1238 ??? Should we handle 16-bit operand-sizes here? */
1240 /* `movb imm8, %al' and `movb imm8, %ah' */
1241 /* `movb imm8, %cl' and `movb imm8, %ch' */
1242 { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } },
1243 /* `movb imm8, %dl' and `movb imm8, %dh' */
1244 { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } },
1245 /* `movl imm32, %eax' and `movl imm32, %ecx' */
1246 { 5, { 0xb8 }, { 0xfe } },
1247 /* `movl imm32, %edx' */
1248 { 5, { 0xba }, { 0xff } },
1250 /* Check for `mov imm32, r32'. Note that there is an alternative
1251 encoding for `mov m32, %eax'.
1253 ??? Should we handle SIB adressing here?
1254 ??? Should we handle 16-bit operand-sizes here? */
1256 /* `movl m32, %eax' */
1257 { 5, { 0xa1 }, { 0xff } },
1258 /* `movl m32, %eax' and `mov; m32, %ecx' */
1259 { 6, { 0x89, 0x05 }, {0xff, 0xf7 } },
1260 /* `movl m32, %edx' */
1261 { 6, { 0x89, 0x15 }, {0xff, 0xff } },
1263 /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'.
1264 Because of the symmetry, there are actually two ways to encode
1265 these instructions; opcode bytes 0x29 and 0x2b for `subl' and
1266 opcode bytes 0x31 and 0x33 for `xorl'. */
1268 /* `subl %eax, %eax' */
1269 { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } },
1270 /* `subl %ecx, %ecx' */
1271 { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } },
1272 /* `subl %edx, %edx' */
1273 { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } },
1274 /* `xorl %eax, %eax' */
1275 { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } },
1276 /* `xorl %ecx, %ecx' */
1277 { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } },
1278 /* `xorl %edx, %edx' */
1279 { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } },
1284 /* Check whether PC points to a no-op instruction. */
1286 i386_skip_noop (CORE_ADDR pc
)
1291 if (target_read_memory (pc
, &op
, 1))
1297 /* Ignore `nop' instruction. */
1301 if (target_read_memory (pc
, &op
, 1))
1305 /* Ignore no-op instruction `mov %edi, %edi'.
1306 Microsoft system dlls often start with
1307 a `mov %edi,%edi' instruction.
1308 The 5 bytes before the function start are
1309 filled with `nop' instructions.
1310 This pattern can be used for hot-patching:
1311 The `mov %edi, %edi' instruction can be replaced by a
1312 near jump to the location of the 5 `nop' instructions
1313 which can be replaced by a 32-bit jump to anywhere
1314 in the 32-bit address space. */
1316 else if (op
== 0x8b)
1318 if (target_read_memory (pc
+ 1, &op
, 1))
1324 if (target_read_memory (pc
, &op
, 1))
1334 /* Check whether PC points at a code that sets up a new stack frame.
1335 If so, it updates CACHE and returns the address of the first
1336 instruction after the sequence that sets up the frame or LIMIT,
1337 whichever is smaller. If we don't recognize the code, return PC. */
1340 i386_analyze_frame_setup (struct gdbarch
*gdbarch
,
1341 CORE_ADDR pc
, CORE_ADDR limit
,
1342 struct i386_frame_cache
*cache
)
1344 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1345 struct i386_insn
*insn
;
1352 if (target_read_memory (pc
, &op
, 1))
1355 if (op
== 0x55) /* pushl %ebp */
1357 /* Take into account that we've executed the `pushl %ebp' that
1358 starts this instruction sequence. */
1359 cache
->saved_regs
[I386_EBP_REGNUM
] = 0;
1360 cache
->sp_offset
+= 4;
1363 /* If that's all, return now. */
1367 /* Check for some special instructions that might be migrated by
1368 GCC into the prologue and skip them. At this point in the
1369 prologue, code should only touch the scratch registers %eax,
1370 %ecx and %edx, so while the number of posibilities is sheer,
1373 Make sure we only skip these instructions if we later see the
1374 `movl %esp, %ebp' that actually sets up the frame. */
1375 while (pc
+ skip
< limit
)
1377 insn
= i386_match_insn (pc
+ skip
, i386_frame_setup_skip_insns
);
1384 /* If that's all, return now. */
1385 if (limit
<= pc
+ skip
)
1388 if (target_read_memory (pc
+ skip
, &op
, 1))
1391 /* Check for `movl %esp, %ebp' -- can be written in two ways. */
1395 if (read_memory_unsigned_integer (pc
+ skip
+ 1, 1, byte_order
)
1400 if (read_memory_unsigned_integer (pc
+ skip
+ 1, 1, byte_order
)
1408 /* OK, we actually have a frame. We just don't know how large
1409 it is yet. Set its size to zero. We'll adjust it if
1410 necessary. We also now commit to skipping the special
1411 instructions mentioned before. */
1415 /* If that's all, return now. */
1419 /* Check for stack adjustment
1423 NOTE: You can't subtract a 16-bit immediate from a 32-bit
1424 reg, so we don't have to worry about a data16 prefix. */
1425 if (target_read_memory (pc
, &op
, 1))
1429 /* `subl' with 8-bit immediate. */
1430 if (read_memory_unsigned_integer (pc
+ 1, 1, byte_order
) != 0xec)
1431 /* Some instruction starting with 0x83 other than `subl'. */
1434 /* `subl' with signed 8-bit immediate (though it wouldn't
1435 make sense to be negative). */
1436 cache
->locals
= read_memory_integer (pc
+ 2, 1, byte_order
);
1439 else if (op
== 0x81)
1441 /* Maybe it is `subl' with a 32-bit immediate. */
1442 if (read_memory_unsigned_integer (pc
+ 1, 1, byte_order
) != 0xec)
1443 /* Some instruction starting with 0x81 other than `subl'. */
1446 /* It is `subl' with a 32-bit immediate. */
1447 cache
->locals
= read_memory_integer (pc
+ 2, 4, byte_order
);
1452 /* Some instruction other than `subl'. */
1456 else if (op
== 0xc8) /* enter */
1458 cache
->locals
= read_memory_unsigned_integer (pc
+ 1, 2, byte_order
);
1465 /* Check whether PC points at code that saves registers on the stack.
1466 If so, it updates CACHE and returns the address of the first
1467 instruction after the register saves or CURRENT_PC, whichever is
1468 smaller. Otherwise, return PC. */
1471 i386_analyze_register_saves (CORE_ADDR pc
, CORE_ADDR current_pc
,
1472 struct i386_frame_cache
*cache
)
1474 CORE_ADDR offset
= 0;
1478 if (cache
->locals
> 0)
1479 offset
-= cache
->locals
;
1480 for (i
= 0; i
< 8 && pc
< current_pc
; i
++)
1482 if (target_read_memory (pc
, &op
, 1))
1484 if (op
< 0x50 || op
> 0x57)
1488 cache
->saved_regs
[op
- 0x50] = offset
;
1489 cache
->sp_offset
+= 4;
1496 /* Do a full analysis of the prologue at PC and update CACHE
1497 accordingly. Bail out early if CURRENT_PC is reached. Return the
1498 address where the analysis stopped.
1500 We handle these cases:
1502 The startup sequence can be at the start of the function, or the
1503 function can start with a branch to startup code at the end.
1505 %ebp can be set up with either the 'enter' instruction, or "pushl
1506 %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was
1507 once used in the System V compiler).
1509 Local space is allocated just below the saved %ebp by either the
1510 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a
1511 16-bit unsigned argument for space to allocate, and the 'addl'
1512 instruction could have either a signed byte, or 32-bit immediate.
1514 Next, the registers used by this function are pushed. With the
1515 System V compiler they will always be in the order: %edi, %esi,
1516 %ebx (and sometimes a harmless bug causes it to also save but not
1517 restore %eax); however, the code below is willing to see the pushes
1518 in any order, and will handle up to 8 of them.
1520 If the setup sequence is at the end of the function, then the next
1521 instruction will be a branch back to the start. */
1524 i386_analyze_prologue (struct gdbarch
*gdbarch
,
1525 CORE_ADDR pc
, CORE_ADDR current_pc
,
1526 struct i386_frame_cache
*cache
)
1528 pc
= i386_skip_noop (pc
);
1529 pc
= i386_follow_jump (gdbarch
, pc
);
1530 pc
= i386_analyze_struct_return (pc
, current_pc
, cache
);
1531 pc
= i386_skip_probe (pc
);
1532 pc
= i386_analyze_stack_align (pc
, current_pc
, cache
);
1533 pc
= i386_analyze_frame_setup (gdbarch
, pc
, current_pc
, cache
);
1534 return i386_analyze_register_saves (pc
, current_pc
, cache
);
1537 /* Return PC of first real instruction. */
1540 i386_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
1542 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1544 static gdb_byte pic_pat
[6] =
1546 0xe8, 0, 0, 0, 0, /* call 0x0 */
1547 0x5b, /* popl %ebx */
1549 struct i386_frame_cache cache
;
1555 pc
= i386_analyze_prologue (gdbarch
, start_pc
, 0xffffffff, &cache
);
1556 if (cache
.locals
< 0)
1559 /* Found valid frame setup. */
1561 /* The native cc on SVR4 in -K PIC mode inserts the following code
1562 to get the address of the global offset table (GOT) into register
1567 movl %ebx,x(%ebp) (optional)
1570 This code is with the rest of the prologue (at the end of the
1571 function), so we have to skip it to get to the first real
1572 instruction at the start of the function. */
1574 for (i
= 0; i
< 6; i
++)
1576 if (target_read_memory (pc
+ i
, &op
, 1))
1579 if (pic_pat
[i
] != op
)
1586 if (target_read_memory (pc
+ delta
, &op
, 1))
1589 if (op
== 0x89) /* movl %ebx, x(%ebp) */
1591 op
= read_memory_unsigned_integer (pc
+ delta
+ 1, 1, byte_order
);
1593 if (op
== 0x5d) /* One byte offset from %ebp. */
1595 else if (op
== 0x9d) /* Four byte offset from %ebp. */
1597 else /* Unexpected instruction. */
1600 if (target_read_memory (pc
+ delta
, &op
, 1))
1605 if (delta
> 0 && op
== 0x81
1606 && read_memory_unsigned_integer (pc
+ delta
+ 1, 1, byte_order
)
1613 /* If the function starts with a branch (to startup code at the end)
1614 the last instruction should bring us back to the first
1615 instruction of the real code. */
1616 if (i386_follow_jump (gdbarch
, start_pc
) != start_pc
)
1617 pc
= i386_follow_jump (gdbarch
, pc
);
1622 /* Check that the code pointed to by PC corresponds to a call to
1623 __main, skip it if so. Return PC otherwise. */
1626 i386_skip_main_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1628 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1631 if (target_read_memory (pc
, &op
, 1))
1637 if (target_read_memory (pc
+ 1, buf
, sizeof buf
) == 0)
1639 /* Make sure address is computed correctly as a 32bit
1640 integer even if CORE_ADDR is 64 bit wide. */
1641 struct minimal_symbol
*s
;
1642 CORE_ADDR call_dest
;
1644 call_dest
= pc
+ 5 + extract_signed_integer (buf
, 4, byte_order
);
1645 call_dest
= call_dest
& 0xffffffffU
;
1646 s
= lookup_minimal_symbol_by_pc (call_dest
);
1648 && SYMBOL_LINKAGE_NAME (s
) != NULL
1649 && strcmp (SYMBOL_LINKAGE_NAME (s
), "__main") == 0)
1657 /* This function is 64-bit safe. */
1660 i386_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1664 frame_unwind_register (next_frame
, gdbarch_pc_regnum (gdbarch
), buf
);
1665 return extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
1669 /* Normal frames. */
1672 i386_frame_cache_1 (struct frame_info
*this_frame
,
1673 struct i386_frame_cache
*cache
)
1675 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1676 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1680 cache
->pc
= get_frame_func (this_frame
);
1682 /* In principle, for normal frames, %ebp holds the frame pointer,
1683 which holds the base address for the current stack frame.
1684 However, for functions that don't need it, the frame pointer is
1685 optional. For these "frameless" functions the frame pointer is
1686 actually the frame pointer of the calling frame. Signal
1687 trampolines are just a special case of a "frameless" function.
1688 They (usually) share their frame pointer with the frame that was
1689 in progress when the signal occurred. */
1691 get_frame_register (this_frame
, I386_EBP_REGNUM
, buf
);
1692 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
);
1693 if (cache
->base
== 0)
1699 /* For normal frames, %eip is stored at 4(%ebp). */
1700 cache
->saved_regs
[I386_EIP_REGNUM
] = 4;
1703 i386_analyze_prologue (gdbarch
, cache
->pc
, get_frame_pc (this_frame
),
1706 if (cache
->locals
< 0)
1708 /* We didn't find a valid frame, which means that CACHE->base
1709 currently holds the frame pointer for our calling frame. If
1710 we're at the start of a function, or somewhere half-way its
1711 prologue, the function's frame probably hasn't been fully
1712 setup yet. Try to reconstruct the base address for the stack
1713 frame by looking at the stack pointer. For truly "frameless"
1714 functions this might work too. */
1716 if (cache
->saved_sp_reg
!= -1)
1718 /* Saved stack pointer has been saved. */
1719 get_frame_register (this_frame
, cache
->saved_sp_reg
, buf
);
1720 cache
->saved_sp
= extract_unsigned_integer (buf
, 4, byte_order
);
1722 /* We're halfway aligning the stack. */
1723 cache
->base
= ((cache
->saved_sp
- 4) & 0xfffffff0) - 4;
1724 cache
->saved_regs
[I386_EIP_REGNUM
] = cache
->saved_sp
- 4;
1726 /* This will be added back below. */
1727 cache
->saved_regs
[I386_EIP_REGNUM
] -= cache
->base
;
1729 else if (cache
->pc
!= 0
1730 || target_read_memory (get_frame_pc (this_frame
), buf
, 1))
1732 /* We're in a known function, but did not find a frame
1733 setup. Assume that the function does not use %ebp.
1734 Alternatively, we may have jumped to an invalid
1735 address; in that case there is definitely no new
1737 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
1738 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
)
1742 /* We're in an unknown function. We could not find the start
1743 of the function to analyze the prologue; our best option is
1744 to assume a typical frame layout with the caller's %ebp
1746 cache
->saved_regs
[I386_EBP_REGNUM
] = 0;
1749 if (cache
->saved_sp_reg
!= -1)
1751 /* Saved stack pointer has been saved (but the SAVED_SP_REG
1752 register may be unavailable). */
1753 if (cache
->saved_sp
== 0
1754 && frame_register_read (this_frame
, cache
->saved_sp_reg
, buf
))
1755 cache
->saved_sp
= extract_unsigned_integer (buf
, 4, byte_order
);
1757 /* Now that we have the base address for the stack frame we can
1758 calculate the value of %esp in the calling frame. */
1759 else if (cache
->saved_sp
== 0)
1760 cache
->saved_sp
= cache
->base
+ 8;
1762 /* Adjust all the saved registers such that they contain addresses
1763 instead of offsets. */
1764 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
1765 if (cache
->saved_regs
[i
] != -1)
1766 cache
->saved_regs
[i
] += cache
->base
;
1771 static struct i386_frame_cache
*
1772 i386_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1774 volatile struct gdb_exception ex
;
1775 struct i386_frame_cache
*cache
;
1780 cache
= i386_alloc_frame_cache ();
1781 *this_cache
= cache
;
1783 TRY_CATCH (ex
, RETURN_MASK_ERROR
)
1785 i386_frame_cache_1 (this_frame
, cache
);
1787 if (ex
.reason
< 0 && ex
.error
!= NOT_AVAILABLE_ERROR
)
1788 throw_exception (ex
);
1794 i386_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
1795 struct frame_id
*this_id
)
1797 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1799 /* This marks the outermost frame. */
1800 if (cache
->base
== 0)
1803 /* See the end of i386_push_dummy_call. */
1804 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
1807 static enum unwind_stop_reason
1808 i386_frame_unwind_stop_reason (struct frame_info
*this_frame
,
1811 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1814 return UNWIND_UNAVAILABLE
;
1816 /* This marks the outermost frame. */
1817 if (cache
->base
== 0)
1818 return UNWIND_OUTERMOST
;
1820 return UNWIND_NO_REASON
;
1823 static struct value
*
1824 i386_frame_prev_register (struct frame_info
*this_frame
, void **this_cache
,
1827 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1829 gdb_assert (regnum
>= 0);
1831 /* The System V ABI says that:
1833 "The flags register contains the system flags, such as the
1834 direction flag and the carry flag. The direction flag must be
1835 set to the forward (that is, zero) direction before entry and
1836 upon exit from a function. Other user flags have no specified
1837 role in the standard calling sequence and are not preserved."
1839 To guarantee the "upon exit" part of that statement we fake a
1840 saved flags register that has its direction flag cleared.
1842 Note that GCC doesn't seem to rely on the fact that the direction
1843 flag is cleared after a function return; it always explicitly
1844 clears the flag before operations where it matters.
1846 FIXME: kettenis/20030316: I'm not quite sure whether this is the
1847 right thing to do. The way we fake the flags register here makes
1848 it impossible to change it. */
1850 if (regnum
== I386_EFLAGS_REGNUM
)
1854 val
= get_frame_register_unsigned (this_frame
, regnum
);
1856 return frame_unwind_got_constant (this_frame
, regnum
, val
);
1859 if (regnum
== I386_EIP_REGNUM
&& cache
->pc_in_eax
)
1860 return frame_unwind_got_register (this_frame
, regnum
, I386_EAX_REGNUM
);
1862 if (regnum
== I386_ESP_REGNUM
1863 && (cache
->saved_sp
!= 0 || cache
->saved_sp_reg
!= -1))
1865 /* If the SP has been saved, but we don't know where, then this
1866 means that SAVED_SP_REG register was found unavailable back
1867 when we built the cache. */
1868 if (cache
->saved_sp
== 0)
1869 return frame_unwind_got_register (this_frame
, regnum
,
1870 cache
->saved_sp_reg
);
1872 return frame_unwind_got_constant (this_frame
, regnum
,
1876 if (regnum
< I386_NUM_SAVED_REGS
&& cache
->saved_regs
[regnum
] != -1)
1877 return frame_unwind_got_memory (this_frame
, regnum
,
1878 cache
->saved_regs
[regnum
]);
1880 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
1883 static const struct frame_unwind i386_frame_unwind
=
1886 i386_frame_unwind_stop_reason
,
1888 i386_frame_prev_register
,
1890 default_frame_sniffer
1893 /* Normal frames, but in a function epilogue. */
1895 /* The epilogue is defined here as the 'ret' instruction, which will
1896 follow any instruction such as 'leave' or 'pop %ebp' that destroys
1897 the function's stack frame. */
1900 i386_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1903 struct symtab
*symtab
;
1905 symtab
= find_pc_symtab (pc
);
1906 if (symtab
&& symtab
->epilogue_unwind_valid
)
1909 if (target_read_memory (pc
, &insn
, 1))
1910 return 0; /* Can't read memory at pc. */
1912 if (insn
!= 0xc3) /* 'ret' instruction. */
1919 i386_epilogue_frame_sniffer (const struct frame_unwind
*self
,
1920 struct frame_info
*this_frame
,
1921 void **this_prologue_cache
)
1923 if (frame_relative_level (this_frame
) == 0)
1924 return i386_in_function_epilogue_p (get_frame_arch (this_frame
),
1925 get_frame_pc (this_frame
));
1930 static struct i386_frame_cache
*
1931 i386_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1933 volatile struct gdb_exception ex
;
1934 struct i386_frame_cache
*cache
;
1940 cache
= i386_alloc_frame_cache ();
1941 *this_cache
= cache
;
1943 TRY_CATCH (ex
, RETURN_MASK_ERROR
)
1945 cache
->pc
= get_frame_func (this_frame
);
1947 /* At this point the stack looks as if we just entered the
1948 function, with the return address at the top of the
1950 sp
= get_frame_register_unsigned (this_frame
, I386_ESP_REGNUM
);
1951 cache
->base
= sp
+ cache
->sp_offset
;
1952 cache
->saved_sp
= cache
->base
+ 8;
1953 cache
->saved_regs
[I386_EIP_REGNUM
] = cache
->base
+ 4;
1957 if (ex
.reason
< 0 && ex
.error
!= NOT_AVAILABLE_ERROR
)
1958 throw_exception (ex
);
1963 static enum unwind_stop_reason
1964 i386_epilogue_frame_unwind_stop_reason (struct frame_info
*this_frame
,
1967 struct i386_frame_cache
*cache
=
1968 i386_epilogue_frame_cache (this_frame
, this_cache
);
1971 return UNWIND_UNAVAILABLE
;
1973 return UNWIND_NO_REASON
;
1977 i386_epilogue_frame_this_id (struct frame_info
*this_frame
,
1979 struct frame_id
*this_id
)
1981 struct i386_frame_cache
*cache
=
1982 i386_epilogue_frame_cache (this_frame
, this_cache
);
1987 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
1990 static struct value
*
1991 i386_epilogue_frame_prev_register (struct frame_info
*this_frame
,
1992 void **this_cache
, int regnum
)
1994 /* Make sure we've initialized the cache. */
1995 i386_epilogue_frame_cache (this_frame
, this_cache
);
1997 return i386_frame_prev_register (this_frame
, this_cache
, regnum
);
2000 static const struct frame_unwind i386_epilogue_frame_unwind
=
2003 i386_epilogue_frame_unwind_stop_reason
,
2004 i386_epilogue_frame_this_id
,
2005 i386_epilogue_frame_prev_register
,
2007 i386_epilogue_frame_sniffer
2011 /* Stack-based trampolines. */
2013 /* These trampolines are used on cross x86 targets, when taking the
2014 address of a nested function. When executing these trampolines,
2015 no stack frame is set up, so we are in a similar situation as in
2016 epilogues and i386_epilogue_frame_this_id can be re-used. */
2018 /* Static chain passed in register. */
2020 struct i386_insn i386_tramp_chain_in_reg_insns
[] =
2022 /* `movl imm32, %eax' and `movl imm32, %ecx' */
2023 { 5, { 0xb8 }, { 0xfe } },
2026 { 5, { 0xe9 }, { 0xff } },
2031 /* Static chain passed on stack (when regparm=3). */
2033 struct i386_insn i386_tramp_chain_on_stack_insns
[] =
2036 { 5, { 0x68 }, { 0xff } },
2039 { 5, { 0xe9 }, { 0xff } },
2044 /* Return whether PC points inside a stack trampoline. */
2047 i386_in_stack_tramp_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2052 /* A stack trampoline is detected if no name is associated
2053 to the current pc and if it points inside a trampoline
2056 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
2060 if (target_read_memory (pc
, &insn
, 1))
2063 if (!i386_match_insn_block (pc
, i386_tramp_chain_in_reg_insns
)
2064 && !i386_match_insn_block (pc
, i386_tramp_chain_on_stack_insns
))
2071 i386_stack_tramp_frame_sniffer (const struct frame_unwind
*self
,
2072 struct frame_info
*this_frame
,
2075 if (frame_relative_level (this_frame
) == 0)
2076 return i386_in_stack_tramp_p (get_frame_arch (this_frame
),
2077 get_frame_pc (this_frame
));
2082 static const struct frame_unwind i386_stack_tramp_frame_unwind
=
2085 i386_epilogue_frame_unwind_stop_reason
,
2086 i386_epilogue_frame_this_id
,
2087 i386_epilogue_frame_prev_register
,
2089 i386_stack_tramp_frame_sniffer
2092 /* Generate a bytecode expression to get the value of the saved PC. */
2095 i386_gen_return_address (struct gdbarch
*gdbarch
,
2096 struct agent_expr
*ax
, struct axs_value
*value
,
2099 /* The following sequence assumes the traditional use of the base
2101 ax_reg (ax
, I386_EBP_REGNUM
);
2103 ax_simple (ax
, aop_add
);
2104 value
->type
= register_type (gdbarch
, I386_EIP_REGNUM
);
2105 value
->kind
= axs_lvalue_memory
;
2109 /* Signal trampolines. */
2111 static struct i386_frame_cache
*
2112 i386_sigtramp_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2114 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2115 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2116 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2117 volatile struct gdb_exception ex
;
2118 struct i386_frame_cache
*cache
;
2125 cache
= i386_alloc_frame_cache ();
2127 TRY_CATCH (ex
, RETURN_MASK_ERROR
)
2129 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
2130 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
) - 4;
2132 addr
= tdep
->sigcontext_addr (this_frame
);
2133 if (tdep
->sc_reg_offset
)
2137 gdb_assert (tdep
->sc_num_regs
<= I386_NUM_SAVED_REGS
);
2139 for (i
= 0; i
< tdep
->sc_num_regs
; i
++)
2140 if (tdep
->sc_reg_offset
[i
] != -1)
2141 cache
->saved_regs
[i
] = addr
+ tdep
->sc_reg_offset
[i
];
2145 cache
->saved_regs
[I386_EIP_REGNUM
] = addr
+ tdep
->sc_pc_offset
;
2146 cache
->saved_regs
[I386_ESP_REGNUM
] = addr
+ tdep
->sc_sp_offset
;
2151 if (ex
.reason
< 0 && ex
.error
!= NOT_AVAILABLE_ERROR
)
2152 throw_exception (ex
);
2154 *this_cache
= cache
;
2158 static enum unwind_stop_reason
2159 i386_sigtramp_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2162 struct i386_frame_cache
*cache
=
2163 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2166 return UNWIND_UNAVAILABLE
;
2168 return UNWIND_NO_REASON
;
2172 i386_sigtramp_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2173 struct frame_id
*this_id
)
2175 struct i386_frame_cache
*cache
=
2176 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2181 /* See the end of i386_push_dummy_call. */
2182 (*this_id
) = frame_id_build (cache
->base
+ 8, get_frame_pc (this_frame
));
2185 static struct value
*
2186 i386_sigtramp_frame_prev_register (struct frame_info
*this_frame
,
2187 void **this_cache
, int regnum
)
2189 /* Make sure we've initialized the cache. */
2190 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2192 return i386_frame_prev_register (this_frame
, this_cache
, regnum
);
2196 i386_sigtramp_frame_sniffer (const struct frame_unwind
*self
,
2197 struct frame_info
*this_frame
,
2198 void **this_prologue_cache
)
2200 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (this_frame
));
2202 /* We shouldn't even bother if we don't have a sigcontext_addr
2204 if (tdep
->sigcontext_addr
== NULL
)
2207 if (tdep
->sigtramp_p
!= NULL
)
2209 if (tdep
->sigtramp_p (this_frame
))
2213 if (tdep
->sigtramp_start
!= 0)
2215 CORE_ADDR pc
= get_frame_pc (this_frame
);
2217 gdb_assert (tdep
->sigtramp_end
!= 0);
2218 if (pc
>= tdep
->sigtramp_start
&& pc
< tdep
->sigtramp_end
)
2225 static const struct frame_unwind i386_sigtramp_frame_unwind
=
2228 i386_sigtramp_frame_unwind_stop_reason
,
2229 i386_sigtramp_frame_this_id
,
2230 i386_sigtramp_frame_prev_register
,
2232 i386_sigtramp_frame_sniffer
2237 i386_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
2239 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
2244 static const struct frame_base i386_frame_base
=
2247 i386_frame_base_address
,
2248 i386_frame_base_address
,
2249 i386_frame_base_address
2252 static struct frame_id
2253 i386_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
2257 fp
= get_frame_register_unsigned (this_frame
, I386_EBP_REGNUM
);
2259 /* See the end of i386_push_dummy_call. */
2260 return frame_id_build (fp
+ 8, get_frame_pc (this_frame
));
2263 /* _Decimal128 function return values need 16-byte alignment on the
2267 i386_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
2269 return sp
& -(CORE_ADDR
)16;
2273 /* Figure out where the longjmp will land. Slurp the args out of the
2274 stack. We expect the first arg to be a pointer to the jmp_buf
2275 structure from which we extract the address that we will land at.
2276 This address is copied into PC. This routine returns non-zero on
2280 i386_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
2283 CORE_ADDR sp
, jb_addr
;
2284 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2285 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2286 int jb_pc_offset
= gdbarch_tdep (gdbarch
)->jb_pc_offset
;
2288 /* If JB_PC_OFFSET is -1, we have no way to find out where the
2289 longjmp will land. */
2290 if (jb_pc_offset
== -1)
2293 get_frame_register (frame
, I386_ESP_REGNUM
, buf
);
2294 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
2295 if (target_read_memory (sp
+ 4, buf
, 4))
2298 jb_addr
= extract_unsigned_integer (buf
, 4, byte_order
);
2299 if (target_read_memory (jb_addr
+ jb_pc_offset
, buf
, 4))
2302 *pc
= extract_unsigned_integer (buf
, 4, byte_order
);
2307 /* Check whether TYPE must be 16-byte-aligned when passed as a
2308 function argument. 16-byte vectors, _Decimal128 and structures or
2309 unions containing such types must be 16-byte-aligned; other
2310 arguments are 4-byte-aligned. */
2313 i386_16_byte_align_p (struct type
*type
)
2315 type
= check_typedef (type
);
2316 if ((TYPE_CODE (type
) == TYPE_CODE_DECFLOAT
2317 || (TYPE_CODE (type
) == TYPE_CODE_ARRAY
&& TYPE_VECTOR (type
)))
2318 && TYPE_LENGTH (type
) == 16)
2320 if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
2321 return i386_16_byte_align_p (TYPE_TARGET_TYPE (type
));
2322 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
2323 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
2326 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
2328 if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type
, i
)))
2336 i386_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2337 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
2338 struct value
**args
, CORE_ADDR sp
, int struct_return
,
2339 CORE_ADDR struct_addr
)
2341 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2347 /* Determine the total space required for arguments and struct
2348 return address in a first pass (allowing for 16-byte-aligned
2349 arguments), then push arguments in a second pass. */
2351 for (write_pass
= 0; write_pass
< 2; write_pass
++)
2353 int args_space_used
= 0;
2354 int have_16_byte_aligned_arg
= 0;
2360 /* Push value address. */
2361 store_unsigned_integer (buf
, 4, byte_order
, struct_addr
);
2362 write_memory (sp
, buf
, 4);
2363 args_space_used
+= 4;
2369 for (i
= 0; i
< nargs
; i
++)
2371 int len
= TYPE_LENGTH (value_enclosing_type (args
[i
]));
2375 if (i386_16_byte_align_p (value_enclosing_type (args
[i
])))
2376 args_space_used
= align_up (args_space_used
, 16);
2378 write_memory (sp
+ args_space_used
,
2379 value_contents_all (args
[i
]), len
);
2380 /* The System V ABI says that:
2382 "An argument's size is increased, if necessary, to make it a
2383 multiple of [32-bit] words. This may require tail padding,
2384 depending on the size of the argument."
2386 This makes sure the stack stays word-aligned. */
2387 args_space_used
+= align_up (len
, 4);
2391 if (i386_16_byte_align_p (value_enclosing_type (args
[i
])))
2393 args_space
= align_up (args_space
, 16);
2394 have_16_byte_aligned_arg
= 1;
2396 args_space
+= align_up (len
, 4);
2402 if (have_16_byte_aligned_arg
)
2403 args_space
= align_up (args_space
, 16);
2408 /* Store return address. */
2410 store_unsigned_integer (buf
, 4, byte_order
, bp_addr
);
2411 write_memory (sp
, buf
, 4);
2413 /* Finally, update the stack pointer... */
2414 store_unsigned_integer (buf
, 4, byte_order
, sp
);
2415 regcache_cooked_write (regcache
, I386_ESP_REGNUM
, buf
);
2417 /* ...and fake a frame pointer. */
2418 regcache_cooked_write (regcache
, I386_EBP_REGNUM
, buf
);
2420 /* MarkK wrote: This "+ 8" is all over the place:
2421 (i386_frame_this_id, i386_sigtramp_frame_this_id,
2422 i386_dummy_id). It's there, since all frame unwinders for
2423 a given target have to agree (within a certain margin) on the
2424 definition of the stack address of a frame. Otherwise frame id
2425 comparison might not work correctly. Since DWARF2/GCC uses the
2426 stack address *before* the function call as a frame's CFA. On
2427 the i386, when %ebp is used as a frame pointer, the offset
2428 between the contents %ebp and the CFA as defined by GCC. */
2432 /* These registers are used for returning integers (and on some
2433 targets also for returning `struct' and `union' values when their
2434 size and alignment match an integer type). */
2435 #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */
2436 #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */
2438 /* Read, for architecture GDBARCH, a function return value of TYPE
2439 from REGCACHE, and copy that into VALBUF. */
2442 i386_extract_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
2443 struct regcache
*regcache
, gdb_byte
*valbuf
)
2445 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2446 int len
= TYPE_LENGTH (type
);
2447 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
2449 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2451 if (tdep
->st0_regnum
< 0)
2453 warning (_("Cannot find floating-point return value."));
2454 memset (valbuf
, 0, len
);
2458 /* Floating-point return values can be found in %st(0). Convert
2459 its contents to the desired type. This is probably not
2460 exactly how it would happen on the target itself, but it is
2461 the best we can do. */
2462 regcache_raw_read (regcache
, I386_ST0_REGNUM
, buf
);
2463 convert_typed_floating (buf
, i387_ext_type (gdbarch
), valbuf
, type
);
2467 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
2468 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
2470 if (len
<= low_size
)
2472 regcache_raw_read (regcache
, LOW_RETURN_REGNUM
, buf
);
2473 memcpy (valbuf
, buf
, len
);
2475 else if (len
<= (low_size
+ high_size
))
2477 regcache_raw_read (regcache
, LOW_RETURN_REGNUM
, buf
);
2478 memcpy (valbuf
, buf
, low_size
);
2479 regcache_raw_read (regcache
, HIGH_RETURN_REGNUM
, buf
);
2480 memcpy (valbuf
+ low_size
, buf
, len
- low_size
);
2483 internal_error (__FILE__
, __LINE__
,
2484 _("Cannot extract return value of %d bytes long."),
2489 /* Write, for architecture GDBARCH, a function return value of TYPE
2490 from VALBUF into REGCACHE. */
2493 i386_store_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
2494 struct regcache
*regcache
, const gdb_byte
*valbuf
)
2496 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2497 int len
= TYPE_LENGTH (type
);
2499 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2502 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
2504 if (tdep
->st0_regnum
< 0)
2506 warning (_("Cannot set floating-point return value."));
2510 /* Returning floating-point values is a bit tricky. Apart from
2511 storing the return value in %st(0), we have to simulate the
2512 state of the FPU at function return point. */
2514 /* Convert the value found in VALBUF to the extended
2515 floating-point format used by the FPU. This is probably
2516 not exactly how it would happen on the target itself, but
2517 it is the best we can do. */
2518 convert_typed_floating (valbuf
, type
, buf
, i387_ext_type (gdbarch
));
2519 regcache_raw_write (regcache
, I386_ST0_REGNUM
, buf
);
2521 /* Set the top of the floating-point register stack to 7. The
2522 actual value doesn't really matter, but 7 is what a normal
2523 function return would end up with if the program started out
2524 with a freshly initialized FPU. */
2525 regcache_raw_read_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), &fstat
);
2527 regcache_raw_write_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), fstat
);
2529 /* Mark %st(1) through %st(7) as empty. Since we set the top of
2530 the floating-point register stack to 7, the appropriate value
2531 for the tag word is 0x3fff. */
2532 regcache_raw_write_unsigned (regcache
, I387_FTAG_REGNUM (tdep
), 0x3fff);
2536 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
2537 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
2539 if (len
<= low_size
)
2540 regcache_raw_write_part (regcache
, LOW_RETURN_REGNUM
, 0, len
, valbuf
);
2541 else if (len
<= (low_size
+ high_size
))
2543 regcache_raw_write (regcache
, LOW_RETURN_REGNUM
, valbuf
);
2544 regcache_raw_write_part (regcache
, HIGH_RETURN_REGNUM
, 0,
2545 len
- low_size
, valbuf
+ low_size
);
2548 internal_error (__FILE__
, __LINE__
,
2549 _("Cannot store return value of %d bytes long."), len
);
2554 /* This is the variable that is set with "set struct-convention", and
2555 its legitimate values. */
2556 static const char default_struct_convention
[] = "default";
2557 static const char pcc_struct_convention
[] = "pcc";
2558 static const char reg_struct_convention
[] = "reg";
2559 static const char *const valid_conventions
[] =
2561 default_struct_convention
,
2562 pcc_struct_convention
,
2563 reg_struct_convention
,
2566 static const char *struct_convention
= default_struct_convention
;
2568 /* Return non-zero if TYPE, which is assumed to be a structure,
2569 a union type, or an array type, should be returned in registers
2570 for architecture GDBARCH. */
2573 i386_reg_struct_return_p (struct gdbarch
*gdbarch
, struct type
*type
)
2575 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2576 enum type_code code
= TYPE_CODE (type
);
2577 int len
= TYPE_LENGTH (type
);
2579 gdb_assert (code
== TYPE_CODE_STRUCT
2580 || code
== TYPE_CODE_UNION
2581 || code
== TYPE_CODE_ARRAY
);
2583 if (struct_convention
== pcc_struct_convention
2584 || (struct_convention
== default_struct_convention
2585 && tdep
->struct_return
== pcc_struct_return
))
2588 /* Structures consisting of a single `float', `double' or 'long
2589 double' member are returned in %st(0). */
2590 if (code
== TYPE_CODE_STRUCT
&& TYPE_NFIELDS (type
) == 1)
2592 type
= check_typedef (TYPE_FIELD_TYPE (type
, 0));
2593 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2594 return (len
== 4 || len
== 8 || len
== 12);
2597 return (len
== 1 || len
== 2 || len
== 4 || len
== 8);
2600 /* Determine, for architecture GDBARCH, how a return value of TYPE
2601 should be returned. If it is supposed to be returned in registers,
2602 and READBUF is non-zero, read the appropriate value from REGCACHE,
2603 and copy it into READBUF. If WRITEBUF is non-zero, write the value
2604 from WRITEBUF into REGCACHE. */
2606 static enum return_value_convention
2607 i386_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
2608 struct type
*type
, struct regcache
*regcache
,
2609 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2611 enum type_code code
= TYPE_CODE (type
);
2613 if (((code
== TYPE_CODE_STRUCT
2614 || code
== TYPE_CODE_UNION
2615 || code
== TYPE_CODE_ARRAY
)
2616 && !i386_reg_struct_return_p (gdbarch
, type
))
2617 /* 128-bit decimal float uses the struct return convention. */
2618 || (code
== TYPE_CODE_DECFLOAT
&& TYPE_LENGTH (type
) == 16))
2620 /* The System V ABI says that:
2622 "A function that returns a structure or union also sets %eax
2623 to the value of the original address of the caller's area
2624 before it returns. Thus when the caller receives control
2625 again, the address of the returned object resides in register
2626 %eax and can be used to access the object."
2628 So the ABI guarantees that we can always find the return
2629 value just after the function has returned. */
2631 /* Note that the ABI doesn't mention functions returning arrays,
2632 which is something possible in certain languages such as Ada.
2633 In this case, the value is returned as if it was wrapped in
2634 a record, so the convention applied to records also applies
2641 regcache_raw_read_unsigned (regcache
, I386_EAX_REGNUM
, &addr
);
2642 read_memory (addr
, readbuf
, TYPE_LENGTH (type
));
2645 return RETURN_VALUE_ABI_RETURNS_ADDRESS
;
2648 /* This special case is for structures consisting of a single
2649 `float', `double' or 'long double' member. These structures are
2650 returned in %st(0). For these structures, we call ourselves
2651 recursively, changing TYPE into the type of the first member of
2652 the structure. Since that should work for all structures that
2653 have only one member, we don't bother to check the member's type
2655 if (code
== TYPE_CODE_STRUCT
&& TYPE_NFIELDS (type
) == 1)
2657 type
= check_typedef (TYPE_FIELD_TYPE (type
, 0));
2658 return i386_return_value (gdbarch
, function
, type
, regcache
,
2663 i386_extract_return_value (gdbarch
, type
, regcache
, readbuf
);
2665 i386_store_return_value (gdbarch
, type
, regcache
, writebuf
);
2667 return RETURN_VALUE_REGISTER_CONVENTION
;
2672 i387_ext_type (struct gdbarch
*gdbarch
)
2674 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2676 if (!tdep
->i387_ext_type
)
2678 tdep
->i387_ext_type
= tdesc_find_type (gdbarch
, "i387_ext");
2679 gdb_assert (tdep
->i387_ext_type
!= NULL
);
2682 return tdep
->i387_ext_type
;
2685 /* Construct vector type for pseudo YMM registers. We can't use
2686 tdesc_find_type since YMM isn't described in target description. */
2688 static struct type
*
2689 i386_ymm_type (struct gdbarch
*gdbarch
)
2691 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2693 if (!tdep
->i386_ymm_type
)
2695 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2697 /* The type we're building is this: */
2699 union __gdb_builtin_type_vec256i
2701 int128_t uint128
[2];
2702 int64_t v2_int64
[4];
2703 int32_t v4_int32
[8];
2704 int16_t v8_int16
[16];
2705 int8_t v16_int8
[32];
2706 double v2_double
[4];
2713 t
= arch_composite_type (gdbarch
,
2714 "__gdb_builtin_type_vec256i", TYPE_CODE_UNION
);
2715 append_composite_type_field (t
, "v8_float",
2716 init_vector_type (bt
->builtin_float
, 8));
2717 append_composite_type_field (t
, "v4_double",
2718 init_vector_type (bt
->builtin_double
, 4));
2719 append_composite_type_field (t
, "v32_int8",
2720 init_vector_type (bt
->builtin_int8
, 32));
2721 append_composite_type_field (t
, "v16_int16",
2722 init_vector_type (bt
->builtin_int16
, 16));
2723 append_composite_type_field (t
, "v8_int32",
2724 init_vector_type (bt
->builtin_int32
, 8));
2725 append_composite_type_field (t
, "v4_int64",
2726 init_vector_type (bt
->builtin_int64
, 4));
2727 append_composite_type_field (t
, "v2_int128",
2728 init_vector_type (bt
->builtin_int128
, 2));
2730 TYPE_VECTOR (t
) = 1;
2731 TYPE_NAME (t
) = "builtin_type_vec256i";
2732 tdep
->i386_ymm_type
= t
;
2735 return tdep
->i386_ymm_type
;
2738 /* Construct vector type for MMX registers. */
2739 static struct type
*
2740 i386_mmx_type (struct gdbarch
*gdbarch
)
2742 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2744 if (!tdep
->i386_mmx_type
)
2746 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2748 /* The type we're building is this: */
2750 union __gdb_builtin_type_vec64i
2753 int32_t v2_int32
[2];
2754 int16_t v4_int16
[4];
2761 t
= arch_composite_type (gdbarch
,
2762 "__gdb_builtin_type_vec64i", TYPE_CODE_UNION
);
2764 append_composite_type_field (t
, "uint64", bt
->builtin_int64
);
2765 append_composite_type_field (t
, "v2_int32",
2766 init_vector_type (bt
->builtin_int32
, 2));
2767 append_composite_type_field (t
, "v4_int16",
2768 init_vector_type (bt
->builtin_int16
, 4));
2769 append_composite_type_field (t
, "v8_int8",
2770 init_vector_type (bt
->builtin_int8
, 8));
2772 TYPE_VECTOR (t
) = 1;
2773 TYPE_NAME (t
) = "builtin_type_vec64i";
2774 tdep
->i386_mmx_type
= t
;
2777 return tdep
->i386_mmx_type
;
2780 /* Return the GDB type object for the "standard" data type of data in
2783 static struct type
*
2784 i386_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
2786 if (i386_mmx_regnum_p (gdbarch
, regnum
))
2787 return i386_mmx_type (gdbarch
);
2788 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
2789 return i386_ymm_type (gdbarch
);
2792 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2793 if (i386_byte_regnum_p (gdbarch
, regnum
))
2794 return bt
->builtin_int8
;
2795 else if (i386_word_regnum_p (gdbarch
, regnum
))
2796 return bt
->builtin_int16
;
2797 else if (i386_dword_regnum_p (gdbarch
, regnum
))
2798 return bt
->builtin_int32
;
2801 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
2804 /* Map a cooked register onto a raw register or memory. For the i386,
2805 the MMX registers need to be mapped onto floating point registers. */
2808 i386_mmx_regnum_to_fp_regnum (struct regcache
*regcache
, int regnum
)
2810 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_regcache_arch (regcache
));
2815 mmxreg
= regnum
- tdep
->mm0_regnum
;
2816 regcache_raw_read_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), &fstat
);
2817 tos
= (fstat
>> 11) & 0x7;
2818 fpreg
= (mmxreg
+ tos
) % 8;
2820 return (I387_ST0_REGNUM (tdep
) + fpreg
);
2823 /* A helper function for us by i386_pseudo_register_read_value and
2824 amd64_pseudo_register_read_value. It does all the work but reads
2825 the data into an already-allocated value. */
2828 i386_pseudo_register_read_into_value (struct gdbarch
*gdbarch
,
2829 struct regcache
*regcache
,
2831 struct value
*result_value
)
2833 gdb_byte raw_buf
[MAX_REGISTER_SIZE
];
2834 enum register_status status
;
2835 gdb_byte
*buf
= value_contents_raw (result_value
);
2837 if (i386_mmx_regnum_p (gdbarch
, regnum
))
2839 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
2841 /* Extract (always little endian). */
2842 status
= regcache_raw_read (regcache
, fpnum
, raw_buf
);
2843 if (status
!= REG_VALID
)
2844 mark_value_bytes_unavailable (result_value
, 0,
2845 TYPE_LENGTH (value_type (result_value
)));
2847 memcpy (buf
, raw_buf
, register_size (gdbarch
, regnum
));
2851 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2853 if (i386_ymm_regnum_p (gdbarch
, regnum
))
2855 regnum
-= tdep
->ymm0_regnum
;
2857 /* Extract (always little endian). Read lower 128bits. */
2858 status
= regcache_raw_read (regcache
,
2859 I387_XMM0_REGNUM (tdep
) + regnum
,
2861 if (status
!= REG_VALID
)
2862 mark_value_bytes_unavailable (result_value
, 0, 16);
2864 memcpy (buf
, raw_buf
, 16);
2865 /* Read upper 128bits. */
2866 status
= regcache_raw_read (regcache
,
2867 tdep
->ymm0h_regnum
+ regnum
,
2869 if (status
!= REG_VALID
)
2870 mark_value_bytes_unavailable (result_value
, 16, 32);
2872 memcpy (buf
+ 16, raw_buf
, 16);
2874 else if (i386_word_regnum_p (gdbarch
, regnum
))
2876 int gpnum
= regnum
- tdep
->ax_regnum
;
2878 /* Extract (always little endian). */
2879 status
= regcache_raw_read (regcache
, gpnum
, raw_buf
);
2880 if (status
!= REG_VALID
)
2881 mark_value_bytes_unavailable (result_value
, 0,
2882 TYPE_LENGTH (value_type (result_value
)));
2884 memcpy (buf
, raw_buf
, 2);
2886 else if (i386_byte_regnum_p (gdbarch
, regnum
))
2888 /* Check byte pseudo registers last since this function will
2889 be called from amd64_pseudo_register_read, which handles
2890 byte pseudo registers differently. */
2891 int gpnum
= regnum
- tdep
->al_regnum
;
2893 /* Extract (always little endian). We read both lower and
2895 status
= regcache_raw_read (regcache
, gpnum
% 4, raw_buf
);
2896 if (status
!= REG_VALID
)
2897 mark_value_bytes_unavailable (result_value
, 0,
2898 TYPE_LENGTH (value_type (result_value
)));
2899 else if (gpnum
>= 4)
2900 memcpy (buf
, raw_buf
+ 1, 1);
2902 memcpy (buf
, raw_buf
, 1);
2905 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
2909 static struct value
*
2910 i386_pseudo_register_read_value (struct gdbarch
*gdbarch
,
2911 struct regcache
*regcache
,
2914 struct value
*result
;
2916 result
= allocate_value (register_type (gdbarch
, regnum
));
2917 VALUE_LVAL (result
) = lval_register
;
2918 VALUE_REGNUM (result
) = regnum
;
2920 i386_pseudo_register_read_into_value (gdbarch
, regcache
, regnum
, result
);
2926 i386_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2927 int regnum
, const gdb_byte
*buf
)
2929 gdb_byte raw_buf
[MAX_REGISTER_SIZE
];
2931 if (i386_mmx_regnum_p (gdbarch
, regnum
))
2933 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
2936 regcache_raw_read (regcache
, fpnum
, raw_buf
);
2937 /* ... Modify ... (always little endian). */
2938 memcpy (raw_buf
, buf
, register_size (gdbarch
, regnum
));
2940 regcache_raw_write (regcache
, fpnum
, raw_buf
);
2944 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2946 if (i386_ymm_regnum_p (gdbarch
, regnum
))
2948 regnum
-= tdep
->ymm0_regnum
;
2950 /* ... Write lower 128bits. */
2951 regcache_raw_write (regcache
,
2952 I387_XMM0_REGNUM (tdep
) + regnum
,
2954 /* ... Write upper 128bits. */
2955 regcache_raw_write (regcache
,
2956 tdep
->ymm0h_regnum
+ regnum
,
2959 else if (i386_word_regnum_p (gdbarch
, regnum
))
2961 int gpnum
= regnum
- tdep
->ax_regnum
;
2964 regcache_raw_read (regcache
, gpnum
, raw_buf
);
2965 /* ... Modify ... (always little endian). */
2966 memcpy (raw_buf
, buf
, 2);
2968 regcache_raw_write (regcache
, gpnum
, raw_buf
);
2970 else if (i386_byte_regnum_p (gdbarch
, regnum
))
2972 /* Check byte pseudo registers last since this function will
2973 be called from amd64_pseudo_register_read, which handles
2974 byte pseudo registers differently. */
2975 int gpnum
= regnum
- tdep
->al_regnum
;
2977 /* Read ... We read both lower and upper registers. */
2978 regcache_raw_read (regcache
, gpnum
% 4, raw_buf
);
2979 /* ... Modify ... (always little endian). */
2981 memcpy (raw_buf
+ 1, buf
, 1);
2983 memcpy (raw_buf
, buf
, 1);
2985 regcache_raw_write (regcache
, gpnum
% 4, raw_buf
);
2988 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
2993 /* Return the register number of the register allocated by GCC after
2994 REGNUM, or -1 if there is no such register. */
2997 i386_next_regnum (int regnum
)
2999 /* GCC allocates the registers in the order:
3001 %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ...
3003 Since storing a variable in %esp doesn't make any sense we return
3004 -1 for %ebp and for %esp itself. */
3005 static int next_regnum
[] =
3007 I386_EDX_REGNUM
, /* Slot for %eax. */
3008 I386_EBX_REGNUM
, /* Slot for %ecx. */
3009 I386_ECX_REGNUM
, /* Slot for %edx. */
3010 I386_ESI_REGNUM
, /* Slot for %ebx. */
3011 -1, -1, /* Slots for %esp and %ebp. */
3012 I386_EDI_REGNUM
, /* Slot for %esi. */
3013 I386_EBP_REGNUM
/* Slot for %edi. */
3016 if (regnum
>= 0 && regnum
< sizeof (next_regnum
) / sizeof (next_regnum
[0]))
3017 return next_regnum
[regnum
];
3022 /* Return nonzero if a value of type TYPE stored in register REGNUM
3023 needs any special handling. */
3026 i386_convert_register_p (struct gdbarch
*gdbarch
,
3027 int regnum
, struct type
*type
)
3029 int len
= TYPE_LENGTH (type
);
3031 /* Values may be spread across multiple registers. Most debugging
3032 formats aren't expressive enough to specify the locations, so
3033 some heuristics is involved. Right now we only handle types that
3034 have a length that is a multiple of the word size, since GCC
3035 doesn't seem to put any other types into registers. */
3036 if (len
> 4 && len
% 4 == 0)
3038 int last_regnum
= regnum
;
3042 last_regnum
= i386_next_regnum (last_regnum
);
3046 if (last_regnum
!= -1)
3050 return i387_convert_register_p (gdbarch
, regnum
, type
);
3053 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
3054 return its contents in TO. */
3057 i386_register_to_value (struct frame_info
*frame
, int regnum
,
3058 struct type
*type
, gdb_byte
*to
,
3059 int *optimizedp
, int *unavailablep
)
3061 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3062 int len
= TYPE_LENGTH (type
);
3064 if (i386_fp_regnum_p (gdbarch
, regnum
))
3065 return i387_register_to_value (frame
, regnum
, type
, to
,
3066 optimizedp
, unavailablep
);
3068 /* Read a value spread across multiple registers. */
3070 gdb_assert (len
> 4 && len
% 4 == 0);
3074 gdb_assert (regnum
!= -1);
3075 gdb_assert (register_size (gdbarch
, regnum
) == 4);
3077 if (!get_frame_register_bytes (frame
, regnum
, 0,
3078 register_size (gdbarch
, regnum
),
3079 to
, optimizedp
, unavailablep
))
3082 regnum
= i386_next_regnum (regnum
);
3087 *optimizedp
= *unavailablep
= 0;
3091 /* Write the contents FROM of a value of type TYPE into register
3092 REGNUM in frame FRAME. */
3095 i386_value_to_register (struct frame_info
*frame
, int regnum
,
3096 struct type
*type
, const gdb_byte
*from
)
3098 int len
= TYPE_LENGTH (type
);
3100 if (i386_fp_regnum_p (get_frame_arch (frame
), regnum
))
3102 i387_value_to_register (frame
, regnum
, type
, from
);
3106 /* Write a value spread across multiple registers. */
3108 gdb_assert (len
> 4 && len
% 4 == 0);
3112 gdb_assert (regnum
!= -1);
3113 gdb_assert (register_size (get_frame_arch (frame
), regnum
) == 4);
3115 put_frame_register (frame
, regnum
, from
);
3116 regnum
= i386_next_regnum (regnum
);
3122 /* Supply register REGNUM from the buffer specified by GREGS and LEN
3123 in the general-purpose register set REGSET to register cache
3124 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3127 i386_supply_gregset (const struct regset
*regset
, struct regcache
*regcache
,
3128 int regnum
, const void *gregs
, size_t len
)
3130 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
3131 const gdb_byte
*regs
= gregs
;
3134 gdb_assert (len
== tdep
->sizeof_gregset
);
3136 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
3138 if ((regnum
== i
|| regnum
== -1)
3139 && tdep
->gregset_reg_offset
[i
] != -1)
3140 regcache_raw_supply (regcache
, i
, regs
+ tdep
->gregset_reg_offset
[i
]);
3144 /* Collect register REGNUM from the register cache REGCACHE and store
3145 it in the buffer specified by GREGS and LEN as described by the
3146 general-purpose register set REGSET. If REGNUM is -1, do this for
3147 all registers in REGSET. */
3150 i386_collect_gregset (const struct regset
*regset
,
3151 const struct regcache
*regcache
,
3152 int regnum
, void *gregs
, size_t len
)
3154 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
3155 gdb_byte
*regs
= gregs
;
3158 gdb_assert (len
== tdep
->sizeof_gregset
);
3160 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
3162 if ((regnum
== i
|| regnum
== -1)
3163 && tdep
->gregset_reg_offset
[i
] != -1)
3164 regcache_raw_collect (regcache
, i
, regs
+ tdep
->gregset_reg_offset
[i
]);
3168 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
3169 in the floating-point register set REGSET to register cache
3170 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3173 i386_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
3174 int regnum
, const void *fpregs
, size_t len
)
3176 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
3178 if (len
== I387_SIZEOF_FXSAVE
)
3180 i387_supply_fxsave (regcache
, regnum
, fpregs
);
3184 gdb_assert (len
== tdep
->sizeof_fpregset
);
3185 i387_supply_fsave (regcache
, regnum
, fpregs
);
3188 /* Collect register REGNUM from the register cache REGCACHE and store
3189 it in the buffer specified by FPREGS and LEN as described by the
3190 floating-point register set REGSET. If REGNUM is -1, do this for
3191 all registers in REGSET. */
3194 i386_collect_fpregset (const struct regset
*regset
,
3195 const struct regcache
*regcache
,
3196 int regnum
, void *fpregs
, size_t len
)
3198 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
3200 if (len
== I387_SIZEOF_FXSAVE
)
3202 i387_collect_fxsave (regcache
, regnum
, fpregs
);
3206 gdb_assert (len
== tdep
->sizeof_fpregset
);
3207 i387_collect_fsave (regcache
, regnum
, fpregs
);
3210 /* Similar to i386_supply_fpregset, but use XSAVE extended state. */
3213 i386_supply_xstateregset (const struct regset
*regset
,
3214 struct regcache
*regcache
, int regnum
,
3215 const void *xstateregs
, size_t len
)
3217 i387_supply_xsave (regcache
, regnum
, xstateregs
);
3220 /* Similar to i386_collect_fpregset , but use XSAVE extended state. */
3223 i386_collect_xstateregset (const struct regset
*regset
,
3224 const struct regcache
*regcache
,
3225 int regnum
, void *xstateregs
, size_t len
)
3227 i387_collect_xsave (regcache
, regnum
, xstateregs
, 1);
3230 /* Return the appropriate register set for the core section identified
3231 by SECT_NAME and SECT_SIZE. */
3233 const struct regset
*
3234 i386_regset_from_core_section (struct gdbarch
*gdbarch
,
3235 const char *sect_name
, size_t sect_size
)
3237 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3239 if (strcmp (sect_name
, ".reg") == 0 && sect_size
== tdep
->sizeof_gregset
)
3241 if (tdep
->gregset
== NULL
)
3242 tdep
->gregset
= regset_alloc (gdbarch
, i386_supply_gregset
,
3243 i386_collect_gregset
);
3244 return tdep
->gregset
;
3247 if ((strcmp (sect_name
, ".reg2") == 0 && sect_size
== tdep
->sizeof_fpregset
)
3248 || (strcmp (sect_name
, ".reg-xfp") == 0
3249 && sect_size
== I387_SIZEOF_FXSAVE
))
3251 if (tdep
->fpregset
== NULL
)
3252 tdep
->fpregset
= regset_alloc (gdbarch
, i386_supply_fpregset
,
3253 i386_collect_fpregset
);
3254 return tdep
->fpregset
;
3257 if (strcmp (sect_name
, ".reg-xstate") == 0)
3259 if (tdep
->xstateregset
== NULL
)
3260 tdep
->xstateregset
= regset_alloc (gdbarch
,
3261 i386_supply_xstateregset
,
3262 i386_collect_xstateregset
);
3264 return tdep
->xstateregset
;
3271 /* Stuff for WIN32 PE style DLL's but is pretty generic really. */
3274 i386_pe_skip_trampoline_code (struct frame_info
*frame
,
3275 CORE_ADDR pc
, char *name
)
3277 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3278 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3281 if (pc
&& read_memory_unsigned_integer (pc
, 2, byte_order
) == 0x25ff)
3283 unsigned long indirect
=
3284 read_memory_unsigned_integer (pc
+ 2, 4, byte_order
);
3285 struct minimal_symbol
*indsym
=
3286 indirect
? lookup_minimal_symbol_by_pc (indirect
) : 0;
3287 const char *symname
= indsym
? SYMBOL_LINKAGE_NAME (indsym
) : 0;
3291 if (strncmp (symname
, "__imp_", 6) == 0
3292 || strncmp (symname
, "_imp_", 5) == 0)
3294 read_memory_unsigned_integer (indirect
, 4, byte_order
);
3297 return 0; /* Not a trampoline. */
3301 /* Return whether the THIS_FRAME corresponds to a sigtramp
3305 i386_sigtramp_p (struct frame_info
*this_frame
)
3307 CORE_ADDR pc
= get_frame_pc (this_frame
);
3310 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
3311 return (name
&& strcmp ("_sigtramp", name
) == 0);
3315 /* We have two flavours of disassembly. The machinery on this page
3316 deals with switching between those. */
3319 i386_print_insn (bfd_vma pc
, struct disassemble_info
*info
)
3321 gdb_assert (disassembly_flavor
== att_flavor
3322 || disassembly_flavor
== intel_flavor
);
3324 /* FIXME: kettenis/20020915: Until disassembler_options is properly
3325 constified, cast to prevent a compiler warning. */
3326 info
->disassembler_options
= (char *) disassembly_flavor
;
3328 return print_insn_i386 (pc
, info
);
3332 /* There are a few i386 architecture variants that differ only
3333 slightly from the generic i386 target. For now, we don't give them
3334 their own source file, but include them here. As a consequence,
3335 they'll always be included. */
3337 /* System V Release 4 (SVR4). */
3339 /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp
3343 i386_svr4_sigtramp_p (struct frame_info
*this_frame
)
3345 CORE_ADDR pc
= get_frame_pc (this_frame
);
3348 /* UnixWare uses _sigacthandler. The origin of the other symbols is
3349 currently unknown. */
3350 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
3351 return (name
&& (strcmp ("_sigreturn", name
) == 0
3352 || strcmp ("_sigacthandler", name
) == 0
3353 || strcmp ("sigvechandler", name
) == 0));
3356 /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the
3357 address of the associated sigcontext (ucontext) structure. */
3360 i386_svr4_sigcontext_addr (struct frame_info
*this_frame
)
3362 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3363 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3367 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
3368 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
3370 return read_memory_unsigned_integer (sp
+ 8, 4, byte_order
);
3375 /* Implementation of `gdbarch_stap_is_single_operand', as defined in
3379 i386_stap_is_single_operand (struct gdbarch
*gdbarch
, const char *s
)
3381 return (*s
== '$' /* Literal number. */
3382 || (isdigit (*s
) && s
[1] == '(' && s
[2] == '%') /* Displacement. */
3383 || (*s
== '(' && s
[1] == '%') /* Register indirection. */
3384 || (*s
== '%' && isalpha (s
[1]))); /* Register access. */
3387 /* Implementation of `gdbarch_stap_parse_special_token', as defined in
3391 i386_stap_parse_special_token (struct gdbarch
*gdbarch
,
3392 struct stap_parse_info
*p
)
3394 /* In order to parse special tokens, we use a state-machine that go
3395 through every known token and try to get a match. */
3399 THREE_ARG_DISPLACEMENT
,
3403 current_state
= TRIPLET
;
3405 /* The special tokens to be parsed here are:
3407 - `register base + (register index * size) + offset', as represented
3408 in `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'.
3410 - Operands of the form `-8+3+1(%rbp)', which must be interpreted as
3411 `*(-8 + 3 - 1 + (void *) $eax)'. */
3413 while (current_state
!= DONE
)
3415 const char *s
= p
->arg
;
3417 switch (current_state
)
3421 if (isdigit (*s
) || *s
== '-' || *s
== '+')
3425 long displacements
[3];
3440 displacements
[0] = strtol (s
, (char **) &s
, 10);
3442 if (*s
!= '+' && *s
!= '-')
3444 /* We are not dealing with a triplet. */
3457 displacements
[1] = strtol (s
, (char **) &s
, 10);
3459 if (*s
!= '+' && *s
!= '-')
3461 /* We are not dealing with a triplet. */
3474 displacements
[2] = strtol (s
, (char **) &s
, 10);
3476 if (*s
!= '(' || s
[1] != '%')
3482 while (isalnum (*s
))
3489 regname
= alloca (len
+ 1);
3491 strncpy (regname
, start
, len
);
3492 regname
[len
] = '\0';
3494 if (user_reg_map_name_to_regnum (gdbarch
,
3495 regname
, len
) == -1)
3496 error (_("Invalid register name `%s' "
3497 "on expression `%s'."),
3498 regname
, p
->saved_arg
);
3500 for (i
= 0; i
< 3; i
++)
3502 write_exp_elt_opcode (OP_LONG
);
3504 (builtin_type (gdbarch
)->builtin_long
);
3505 write_exp_elt_longcst (displacements
[i
]);
3506 write_exp_elt_opcode (OP_LONG
);
3508 write_exp_elt_opcode (UNOP_NEG
);
3511 write_exp_elt_opcode (OP_REGISTER
);
3514 write_exp_string (str
);
3515 write_exp_elt_opcode (OP_REGISTER
);
3517 write_exp_elt_opcode (UNOP_CAST
);
3518 write_exp_elt_type (builtin_type (gdbarch
)->builtin_data_ptr
);
3519 write_exp_elt_opcode (UNOP_CAST
);
3521 write_exp_elt_opcode (BINOP_ADD
);
3522 write_exp_elt_opcode (BINOP_ADD
);
3523 write_exp_elt_opcode (BINOP_ADD
);
3525 write_exp_elt_opcode (UNOP_CAST
);
3526 write_exp_elt_type (lookup_pointer_type (p
->arg_type
));
3527 write_exp_elt_opcode (UNOP_CAST
);
3529 write_exp_elt_opcode (UNOP_IND
);
3537 case THREE_ARG_DISPLACEMENT
:
3539 if (isdigit (*s
) || *s
== '(' || *s
== '-' || *s
== '+')
3541 int offset_minus
= 0;
3550 struct stoken base_token
, index_token
;
3560 if (offset_minus
&& !isdigit (*s
))
3564 offset
= strtol (s
, (char **) &s
, 10);
3566 if (*s
!= '(' || s
[1] != '%')
3572 while (isalnum (*s
))
3575 if (*s
!= ',' || s
[1] != '%')
3578 len_base
= s
- start
;
3579 base
= alloca (len_base
+ 1);
3580 strncpy (base
, start
, len_base
);
3581 base
[len_base
] = '\0';
3583 if (user_reg_map_name_to_regnum (gdbarch
,
3584 base
, len_base
) == -1)
3585 error (_("Invalid register name `%s' "
3586 "on expression `%s'."),
3587 base
, p
->saved_arg
);
3592 while (isalnum (*s
))
3595 len_index
= s
- start
;
3596 index
= alloca (len_index
+ 1);
3597 strncpy (index
, start
, len_index
);
3598 index
[len_index
] = '\0';
3600 if (user_reg_map_name_to_regnum (gdbarch
,
3601 index
, len_index
) == -1)
3602 error (_("Invalid register name `%s' "
3603 "on expression `%s'."),
3604 index
, p
->saved_arg
);
3606 if (*s
!= ',' && *s
!= ')')
3620 size
= strtol (s
, (char **) &s
, 10);
3630 write_exp_elt_opcode (OP_LONG
);
3632 (builtin_type (gdbarch
)->builtin_long
);
3633 write_exp_elt_longcst (offset
);
3634 write_exp_elt_opcode (OP_LONG
);
3636 write_exp_elt_opcode (UNOP_NEG
);
3639 write_exp_elt_opcode (OP_REGISTER
);
3640 base_token
.ptr
= base
;
3641 base_token
.length
= len_base
;
3642 write_exp_string (base_token
);
3643 write_exp_elt_opcode (OP_REGISTER
);
3646 write_exp_elt_opcode (BINOP_ADD
);
3648 write_exp_elt_opcode (OP_REGISTER
);
3649 index_token
.ptr
= index
;
3650 index_token
.length
= len_index
;
3651 write_exp_string (index_token
);
3652 write_exp_elt_opcode (OP_REGISTER
);
3656 write_exp_elt_opcode (OP_LONG
);
3658 (builtin_type (gdbarch
)->builtin_long
);
3659 write_exp_elt_longcst (size
);
3660 write_exp_elt_opcode (OP_LONG
);
3662 write_exp_elt_opcode (UNOP_NEG
);
3663 write_exp_elt_opcode (BINOP_MUL
);
3666 write_exp_elt_opcode (BINOP_ADD
);
3668 write_exp_elt_opcode (UNOP_CAST
);
3669 write_exp_elt_type (lookup_pointer_type (p
->arg_type
));
3670 write_exp_elt_opcode (UNOP_CAST
);
3672 write_exp_elt_opcode (UNOP_IND
);
3682 /* Advancing to the next state. */
3694 i386_elf_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
3696 /* We typically use stabs-in-ELF with the SVR4 register numbering. */
3697 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
3699 /* Registering SystemTap handlers. */
3700 set_gdbarch_stap_integer_prefix (gdbarch
, "$");
3701 set_gdbarch_stap_register_prefix (gdbarch
, "%");
3702 set_gdbarch_stap_register_indirection_prefix (gdbarch
, "(");
3703 set_gdbarch_stap_register_indirection_suffix (gdbarch
, ")");
3704 set_gdbarch_stap_is_single_operand (gdbarch
,
3705 i386_stap_is_single_operand
);
3706 set_gdbarch_stap_parse_special_token (gdbarch
,
3707 i386_stap_parse_special_token
);
3710 /* System V Release 4 (SVR4). */
3713 i386_svr4_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
3715 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3717 /* System V Release 4 uses ELF. */
3718 i386_elf_init_abi (info
, gdbarch
);
3720 /* System V Release 4 has shared libraries. */
3721 set_gdbarch_skip_trampoline_code (gdbarch
, find_solib_trampoline_target
);
3723 tdep
->sigtramp_p
= i386_svr4_sigtramp_p
;
3724 tdep
->sigcontext_addr
= i386_svr4_sigcontext_addr
;
3725 tdep
->sc_pc_offset
= 36 + 14 * 4;
3726 tdep
->sc_sp_offset
= 36 + 17 * 4;
3728 tdep
->jb_pc_offset
= 20;
3734 i386_go32_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
3736 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3738 /* DJGPP doesn't have any special frames for signal handlers. */
3739 tdep
->sigtramp_p
= NULL
;
3741 tdep
->jb_pc_offset
= 36;
3743 /* DJGPP does not support the SSE registers. */
3744 if (! tdesc_has_registers (info
.target_desc
))
3745 tdep
->tdesc
= tdesc_i386_mmx
;
3747 /* Native compiler is GCC, which uses the SVR4 register numbering
3748 even in COFF and STABS. See the comment in i386_gdbarch_init,
3749 before the calls to set_gdbarch_stab_reg_to_regnum and
3750 set_gdbarch_sdb_reg_to_regnum. */
3751 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
3752 set_gdbarch_sdb_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
3754 set_gdbarch_has_dos_based_file_system (gdbarch
, 1);
3758 /* i386 register groups. In addition to the normal groups, add "mmx"
3761 static struct reggroup
*i386_sse_reggroup
;
3762 static struct reggroup
*i386_mmx_reggroup
;
3765 i386_init_reggroups (void)
3767 i386_sse_reggroup
= reggroup_new ("sse", USER_REGGROUP
);
3768 i386_mmx_reggroup
= reggroup_new ("mmx", USER_REGGROUP
);
3772 i386_add_reggroups (struct gdbarch
*gdbarch
)
3774 reggroup_add (gdbarch
, i386_sse_reggroup
);
3775 reggroup_add (gdbarch
, i386_mmx_reggroup
);
3776 reggroup_add (gdbarch
, general_reggroup
);
3777 reggroup_add (gdbarch
, float_reggroup
);
3778 reggroup_add (gdbarch
, all_reggroup
);
3779 reggroup_add (gdbarch
, save_reggroup
);
3780 reggroup_add (gdbarch
, restore_reggroup
);
3781 reggroup_add (gdbarch
, vector_reggroup
);
3782 reggroup_add (gdbarch
, system_reggroup
);
3786 i386_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
3787 struct reggroup
*group
)
3789 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3790 int fp_regnum_p
, mmx_regnum_p
, xmm_regnum_p
, mxcsr_regnum_p
,
3791 ymm_regnum_p
, ymmh_regnum_p
;
3793 /* Don't include pseudo registers, except for MMX, in any register
3795 if (i386_byte_regnum_p (gdbarch
, regnum
))
3798 if (i386_word_regnum_p (gdbarch
, regnum
))
3801 if (i386_dword_regnum_p (gdbarch
, regnum
))
3804 mmx_regnum_p
= i386_mmx_regnum_p (gdbarch
, regnum
);
3805 if (group
== i386_mmx_reggroup
)
3806 return mmx_regnum_p
;
3808 xmm_regnum_p
= i386_xmm_regnum_p (gdbarch
, regnum
);
3809 mxcsr_regnum_p
= i386_mxcsr_regnum_p (gdbarch
, regnum
);
3810 if (group
== i386_sse_reggroup
)
3811 return xmm_regnum_p
|| mxcsr_regnum_p
;
3813 ymm_regnum_p
= i386_ymm_regnum_p (gdbarch
, regnum
);
3814 if (group
== vector_reggroup
)
3815 return (mmx_regnum_p
3819 && ((tdep
->xcr0
& I386_XSTATE_AVX_MASK
)
3820 == I386_XSTATE_SSE_MASK
)));
3822 fp_regnum_p
= (i386_fp_regnum_p (gdbarch
, regnum
)
3823 || i386_fpc_regnum_p (gdbarch
, regnum
));
3824 if (group
== float_reggroup
)
3827 /* For "info reg all", don't include upper YMM registers nor XMM
3828 registers when AVX is supported. */
3829 ymmh_regnum_p
= i386_ymmh_regnum_p (gdbarch
, regnum
);
3830 if (group
== all_reggroup
3832 && (tdep
->xcr0
& I386_XSTATE_AVX
))
3836 if (group
== general_reggroup
)
3837 return (!fp_regnum_p
3844 return default_register_reggroup_p (gdbarch
, regnum
, group
);
3848 /* Get the ARGIth function argument for the current function. */
3851 i386_fetch_pointer_argument (struct frame_info
*frame
, int argi
,
3854 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3855 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3856 CORE_ADDR sp
= get_frame_register_unsigned (frame
, I386_ESP_REGNUM
);
3857 return read_memory_unsigned_integer (sp
+ (4 * (argi
+ 1)), 4, byte_order
);
3861 i386_skip_permanent_breakpoint (struct regcache
*regcache
)
3863 CORE_ADDR current_pc
= regcache_read_pc (regcache
);
3865 /* On i386, breakpoint is exactly 1 byte long, so we just
3866 adjust the PC in the regcache. */
3868 regcache_write_pc (regcache
, current_pc
);
3872 #define PREFIX_REPZ 0x01
3873 #define PREFIX_REPNZ 0x02
3874 #define PREFIX_LOCK 0x04
3875 #define PREFIX_DATA 0x08
3876 #define PREFIX_ADDR 0x10
3888 /* i386 arith/logic operations */
3901 struct i386_record_s
3903 struct gdbarch
*gdbarch
;
3904 struct regcache
*regcache
;
3905 CORE_ADDR orig_addr
;
3911 uint8_t mod
, reg
, rm
;
3920 /* Parse "modrm" part in current memory address that irp->addr point to
3921 Return -1 if something wrong. */
3924 i386_record_modrm (struct i386_record_s
*irp
)
3926 struct gdbarch
*gdbarch
= irp
->gdbarch
;
3928 if (target_read_memory (irp
->addr
, &irp
->modrm
, 1))
3931 printf_unfiltered (_("Process record: error reading memory at "
3932 "addr %s len = 1.\n"),
3933 paddress (gdbarch
, irp
->addr
));
3937 irp
->mod
= (irp
->modrm
>> 6) & 3;
3938 irp
->reg
= (irp
->modrm
>> 3) & 7;
3939 irp
->rm
= irp
->modrm
& 7;
3944 /* Get the memory address that current instruction write to and set it to
3945 the argument "addr".
3946 Return -1 if something wrong. */
3949 i386_record_lea_modrm_addr (struct i386_record_s
*irp
, uint64_t *addr
)
3951 struct gdbarch
*gdbarch
= irp
->gdbarch
;
3952 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3964 uint8_t base
= irp
->rm
;
3969 if (target_read_memory (irp
->addr
, &byte
, 1))
3972 printf_unfiltered (_("Process record: error reading memory "
3973 "at addr %s len = 1.\n"),
3974 paddress (gdbarch
, irp
->addr
));
3978 scale
= (byte
>> 6) & 3;
3979 index
= ((byte
>> 3) & 7) | irp
->rex_x
;
3987 if ((base
& 7) == 5)
3990 if (target_read_memory (irp
->addr
, buf
, 4))
3993 printf_unfiltered (_("Process record: error reading "
3994 "memory at addr %s len = 4.\n"),
3995 paddress (gdbarch
, irp
->addr
));
3999 *addr
= extract_signed_integer (buf
, 4, byte_order
);
4000 if (irp
->regmap
[X86_RECORD_R8_REGNUM
] && !havesib
)
4001 *addr
+= irp
->addr
+ irp
->rip_offset
;
4005 if (target_read_memory (irp
->addr
, buf
, 1))
4008 printf_unfiltered (_("Process record: error reading memory "
4009 "at addr %s len = 1.\n"),
4010 paddress (gdbarch
, irp
->addr
));
4014 *addr
= (int8_t) buf
[0];
4017 if (target_read_memory (irp
->addr
, buf
, 4))
4020 printf_unfiltered (_("Process record: error reading memory "
4021 "at addr %s len = 4.\n"),
4022 paddress (gdbarch
, irp
->addr
));
4025 *addr
= extract_signed_integer (buf
, 4, byte_order
);
4033 if (base
== 4 && irp
->popl_esp_hack
)
4034 *addr
+= irp
->popl_esp_hack
;
4035 regcache_raw_read_unsigned (irp
->regcache
, irp
->regmap
[base
],
4038 if (irp
->aflag
== 2)
4043 *addr
= (uint32_t) (offset64
+ *addr
);
4045 if (havesib
&& (index
!= 4 || scale
!= 0))
4047 regcache_raw_read_unsigned (irp
->regcache
, irp
->regmap
[index
],
4049 if (irp
->aflag
== 2)
4050 *addr
+= offset64
<< scale
;
4052 *addr
= (uint32_t) (*addr
+ (offset64
<< scale
));
4063 if (target_read_memory (irp
->addr
, buf
, 2))
4066 printf_unfiltered (_("Process record: error reading "
4067 "memory at addr %s len = 2.\n"),
4068 paddress (gdbarch
, irp
->addr
));
4072 *addr
= extract_signed_integer (buf
, 2, byte_order
);
4078 if (target_read_memory (irp
->addr
, buf
, 1))
4081 printf_unfiltered (_("Process record: error reading memory "
4082 "at addr %s len = 1.\n"),
4083 paddress (gdbarch
, irp
->addr
));
4087 *addr
= (int8_t) buf
[0];
4090 if (target_read_memory (irp
->addr
, buf
, 2))
4093 printf_unfiltered (_("Process record: error reading memory "
4094 "at addr %s len = 2.\n"),
4095 paddress (gdbarch
, irp
->addr
));
4099 *addr
= extract_signed_integer (buf
, 2, byte_order
);
4106 regcache_raw_read_unsigned (irp
->regcache
,
4107 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
4109 *addr
= (uint32_t) (*addr
+ offset64
);
4110 regcache_raw_read_unsigned (irp
->regcache
,
4111 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
4113 *addr
= (uint32_t) (*addr
+ offset64
);
4116 regcache_raw_read_unsigned (irp
->regcache
,
4117 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
4119 *addr
= (uint32_t) (*addr
+ offset64
);
4120 regcache_raw_read_unsigned (irp
->regcache
,
4121 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
4123 *addr
= (uint32_t) (*addr
+ offset64
);
4126 regcache_raw_read_unsigned (irp
->regcache
,
4127 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
4129 *addr
= (uint32_t) (*addr
+ offset64
);
4130 regcache_raw_read_unsigned (irp
->regcache
,
4131 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
4133 *addr
= (uint32_t) (*addr
+ offset64
);
4136 regcache_raw_read_unsigned (irp
->regcache
,
4137 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
4139 *addr
= (uint32_t) (*addr
+ offset64
);
4140 regcache_raw_read_unsigned (irp
->regcache
,
4141 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
4143 *addr
= (uint32_t) (*addr
+ offset64
);
4146 regcache_raw_read_unsigned (irp
->regcache
,
4147 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
4149 *addr
= (uint32_t) (*addr
+ offset64
);
4152 regcache_raw_read_unsigned (irp
->regcache
,
4153 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
4155 *addr
= (uint32_t) (*addr
+ offset64
);
4158 regcache_raw_read_unsigned (irp
->regcache
,
4159 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
4161 *addr
= (uint32_t) (*addr
+ offset64
);
4164 regcache_raw_read_unsigned (irp
->regcache
,
4165 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
4167 *addr
= (uint32_t) (*addr
+ offset64
);
4177 /* Record the value of the memory that willbe changed in current instruction
4178 to "record_arch_list".
4179 Return -1 if something wrong. */
4182 i386_record_lea_modrm (struct i386_record_s
*irp
)
4184 struct gdbarch
*gdbarch
= irp
->gdbarch
;
4187 if (irp
->override
>= 0)
4189 if (record_memory_query
)
4193 target_terminal_ours ();
4195 Process record ignores the memory change of instruction at address %s\n\
4196 because it can't get the value of the segment register.\n\
4197 Do you want to stop the program?"),
4198 paddress (gdbarch
, irp
->orig_addr
));
4199 target_terminal_inferior ();
4207 if (i386_record_lea_modrm_addr (irp
, &addr
))
4210 if (record_arch_list_add_mem (addr
, 1 << irp
->ot
))
4216 /* Record the push operation to "record_arch_list".
4217 Return -1 if something wrong. */
4220 i386_record_push (struct i386_record_s
*irp
, int size
)
4224 if (record_arch_list_add_reg (irp
->regcache
,
4225 irp
->regmap
[X86_RECORD_RESP_REGNUM
]))
4227 regcache_raw_read_unsigned (irp
->regcache
,
4228 irp
->regmap
[X86_RECORD_RESP_REGNUM
],
4230 if (record_arch_list_add_mem ((CORE_ADDR
) addr
- size
, size
))
4237 /* Defines contents to record. */
4238 #define I386_SAVE_FPU_REGS 0xfffd
4239 #define I386_SAVE_FPU_ENV 0xfffe
4240 #define I386_SAVE_FPU_ENV_REG_STACK 0xffff
4242 /* Record the value of floating point registers which will be changed
4243 by the current instruction to "record_arch_list". Return -1 if
4244 something is wrong. */
4246 static int i386_record_floats (struct gdbarch
*gdbarch
,
4247 struct i386_record_s
*ir
,
4250 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4253 /* Oza: Because of floating point insn push/pop of fpu stack is going to
4254 happen. Currently we store st0-st7 registers, but we need not store all
4255 registers all the time, in future we use ftag register and record only
4256 those who are not marked as an empty. */
4258 if (I386_SAVE_FPU_REGS
== iregnum
)
4260 for (i
= I387_ST0_REGNUM (tdep
); i
<= I387_ST0_REGNUM (tdep
) + 7; i
++)
4262 if (record_arch_list_add_reg (ir
->regcache
, i
))
4266 else if (I386_SAVE_FPU_ENV
== iregnum
)
4268 for (i
= I387_FCTRL_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
4270 if (record_arch_list_add_reg (ir
->regcache
, i
))
4274 else if (I386_SAVE_FPU_ENV_REG_STACK
== iregnum
)
4276 for (i
= I387_ST0_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
4278 if (record_arch_list_add_reg (ir
->regcache
, i
))
4282 else if ((iregnum
>= I387_ST0_REGNUM (tdep
)) &&
4283 (iregnum
<= I387_FOP_REGNUM (tdep
)))
4285 if (record_arch_list_add_reg (ir
->regcache
,iregnum
))
4290 /* Parameter error. */
4293 if(I386_SAVE_FPU_ENV
!= iregnum
)
4295 for (i
= I387_FCTRL_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
4297 if (record_arch_list_add_reg (ir
->regcache
, i
))
4304 /* Parse the current instruction and record the values of the registers and
4305 memory that will be changed in current instruction to "record_arch_list".
4306 Return -1 if something wrong. */
4308 #define I386_RECORD_ARCH_LIST_ADD_REG(regnum) \
4309 record_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)])
4312 i386_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4313 CORE_ADDR input_addr
)
4315 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4321 gdb_byte buf
[MAX_REGISTER_SIZE
];
4322 struct i386_record_s ir
;
4323 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4328 memset (&ir
, 0, sizeof (struct i386_record_s
));
4329 ir
.regcache
= regcache
;
4330 ir
.addr
= input_addr
;
4331 ir
.orig_addr
= input_addr
;
4335 ir
.popl_esp_hack
= 0;
4336 ir
.regmap
= tdep
->record_regmap
;
4337 ir
.gdbarch
= gdbarch
;
4339 if (record_debug
> 1)
4340 fprintf_unfiltered (gdb_stdlog
, "Process record: i386_process_record "
4342 paddress (gdbarch
, ir
.addr
));
4347 if (target_read_memory (ir
.addr
, &opcode8
, 1))
4350 printf_unfiltered (_("Process record: error reading memory at "
4351 "addr %s len = 1.\n"),
4352 paddress (gdbarch
, ir
.addr
));
4356 switch (opcode8
) /* Instruction prefixes */
4358 case REPE_PREFIX_OPCODE
:
4359 prefixes
|= PREFIX_REPZ
;
4361 case REPNE_PREFIX_OPCODE
:
4362 prefixes
|= PREFIX_REPNZ
;
4364 case LOCK_PREFIX_OPCODE
:
4365 prefixes
|= PREFIX_LOCK
;
4367 case CS_PREFIX_OPCODE
:
4368 ir
.override
= X86_RECORD_CS_REGNUM
;
4370 case SS_PREFIX_OPCODE
:
4371 ir
.override
= X86_RECORD_SS_REGNUM
;
4373 case DS_PREFIX_OPCODE
:
4374 ir
.override
= X86_RECORD_DS_REGNUM
;
4376 case ES_PREFIX_OPCODE
:
4377 ir
.override
= X86_RECORD_ES_REGNUM
;
4379 case FS_PREFIX_OPCODE
:
4380 ir
.override
= X86_RECORD_FS_REGNUM
;
4382 case GS_PREFIX_OPCODE
:
4383 ir
.override
= X86_RECORD_GS_REGNUM
;
4385 case DATA_PREFIX_OPCODE
:
4386 prefixes
|= PREFIX_DATA
;
4388 case ADDR_PREFIX_OPCODE
:
4389 prefixes
|= PREFIX_ADDR
;
4391 case 0x40: /* i386 inc %eax */
4392 case 0x41: /* i386 inc %ecx */
4393 case 0x42: /* i386 inc %edx */
4394 case 0x43: /* i386 inc %ebx */
4395 case 0x44: /* i386 inc %esp */
4396 case 0x45: /* i386 inc %ebp */
4397 case 0x46: /* i386 inc %esi */
4398 case 0x47: /* i386 inc %edi */
4399 case 0x48: /* i386 dec %eax */
4400 case 0x49: /* i386 dec %ecx */
4401 case 0x4a: /* i386 dec %edx */
4402 case 0x4b: /* i386 dec %ebx */
4403 case 0x4c: /* i386 dec %esp */
4404 case 0x4d: /* i386 dec %ebp */
4405 case 0x4e: /* i386 dec %esi */
4406 case 0x4f: /* i386 dec %edi */
4407 if (ir
.regmap
[X86_RECORD_R8_REGNUM
]) /* 64 bit target */
4411 rex_w
= (opcode8
>> 3) & 1;
4412 rex_r
= (opcode8
& 0x4) << 1;
4413 ir
.rex_x
= (opcode8
& 0x2) << 2;
4414 ir
.rex_b
= (opcode8
& 0x1) << 3;
4416 else /* 32 bit target */
4425 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && rex_w
== 1)
4431 if (prefixes
& PREFIX_DATA
)
4434 if (prefixes
& PREFIX_ADDR
)
4436 else if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4439 /* Now check op code. */
4440 opcode
= (uint32_t) opcode8
;
4445 if (target_read_memory (ir
.addr
, &opcode8
, 1))
4448 printf_unfiltered (_("Process record: error reading memory at "
4449 "addr %s len = 1.\n"),
4450 paddress (gdbarch
, ir
.addr
));
4454 opcode
= (uint32_t) opcode8
| 0x0f00;
4458 case 0x00: /* arith & logic */
4506 if (((opcode
>> 3) & 7) != OP_CMPL
)
4508 if ((opcode
& 1) == 0)
4511 ir
.ot
= ir
.dflag
+ OT_WORD
;
4513 switch ((opcode
>> 1) & 3)
4515 case 0: /* OP Ev, Gv */
4516 if (i386_record_modrm (&ir
))
4520 if (i386_record_lea_modrm (&ir
))
4526 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4528 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4531 case 1: /* OP Gv, Ev */
4532 if (i386_record_modrm (&ir
))
4535 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4537 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4539 case 2: /* OP A, Iv */
4540 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4544 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4547 case 0x80: /* GRP1 */
4551 if (i386_record_modrm (&ir
))
4554 if (ir
.reg
!= OP_CMPL
)
4556 if ((opcode
& 1) == 0)
4559 ir
.ot
= ir
.dflag
+ OT_WORD
;
4566 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
4567 if (i386_record_lea_modrm (&ir
))
4571 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
4573 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4576 case 0x40: /* inc */
4585 case 0x48: /* dec */
4594 I386_RECORD_ARCH_LIST_ADD_REG (opcode
& 7);
4595 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4598 case 0xf6: /* GRP3 */
4600 if ((opcode
& 1) == 0)
4603 ir
.ot
= ir
.dflag
+ OT_WORD
;
4604 if (i386_record_modrm (&ir
))
4607 if (ir
.mod
!= 3 && ir
.reg
== 0)
4608 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
4613 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4619 if (i386_record_lea_modrm (&ir
))
4625 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4627 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4629 if (ir
.reg
== 3) /* neg */
4630 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4636 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4637 if (ir
.ot
!= OT_BYTE
)
4638 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
4639 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4643 opcode
= opcode
<< 8 | ir
.modrm
;
4649 case 0xfe: /* GRP4 */
4650 case 0xff: /* GRP5 */
4651 if (i386_record_modrm (&ir
))
4653 if (ir
.reg
>= 2 && opcode
== 0xfe)
4656 opcode
= opcode
<< 8 | ir
.modrm
;
4663 if ((opcode
& 1) == 0)
4666 ir
.ot
= ir
.dflag
+ OT_WORD
;
4669 if (i386_record_lea_modrm (&ir
))
4675 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4677 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4679 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4682 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4684 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4686 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4689 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
4690 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4692 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4696 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4699 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4701 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4706 opcode
= opcode
<< 8 | ir
.modrm
;
4712 case 0x84: /* test */
4716 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4719 case 0x98: /* CWDE/CBW */
4720 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4723 case 0x99: /* CDQ/CWD */
4724 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4725 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
4728 case 0x0faf: /* imul */
4731 ir
.ot
= ir
.dflag
+ OT_WORD
;
4732 if (i386_record_modrm (&ir
))
4735 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
4736 else if (opcode
== 0x6b)
4739 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4741 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4742 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4745 case 0x0fc0: /* xadd */
4747 if ((opcode
& 1) == 0)
4750 ir
.ot
= ir
.dflag
+ OT_WORD
;
4751 if (i386_record_modrm (&ir
))
4756 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4758 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4759 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4761 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4765 if (i386_record_lea_modrm (&ir
))
4767 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4769 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4771 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4774 case 0x0fb0: /* cmpxchg */
4776 if ((opcode
& 1) == 0)
4779 ir
.ot
= ir
.dflag
+ OT_WORD
;
4780 if (i386_record_modrm (&ir
))
4785 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4786 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4788 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4792 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4793 if (i386_record_lea_modrm (&ir
))
4796 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4799 case 0x0fc7: /* cmpxchg8b */
4800 if (i386_record_modrm (&ir
))
4805 opcode
= opcode
<< 8 | ir
.modrm
;
4808 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4809 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
4810 if (i386_record_lea_modrm (&ir
))
4812 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4815 case 0x50: /* push */
4825 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4827 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4831 case 0x06: /* push es */
4832 case 0x0e: /* push cs */
4833 case 0x16: /* push ss */
4834 case 0x1e: /* push ds */
4835 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4840 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4844 case 0x0fa0: /* push fs */
4845 case 0x0fa8: /* push gs */
4846 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4851 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4855 case 0x60: /* pusha */
4856 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4861 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 4)))
4865 case 0x58: /* pop */
4873 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4874 I386_RECORD_ARCH_LIST_ADD_REG ((opcode
& 0x7) | ir
.rex_b
);
4877 case 0x61: /* popa */
4878 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4883 for (regnum
= X86_RECORD_REAX_REGNUM
;
4884 regnum
<= X86_RECORD_REDI_REGNUM
;
4886 I386_RECORD_ARCH_LIST_ADD_REG (regnum
);
4889 case 0x8f: /* pop */
4890 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4891 ir
.ot
= ir
.dflag
? OT_QUAD
: OT_WORD
;
4893 ir
.ot
= ir
.dflag
+ OT_WORD
;
4894 if (i386_record_modrm (&ir
))
4897 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
4900 ir
.popl_esp_hack
= 1 << ir
.ot
;
4901 if (i386_record_lea_modrm (&ir
))
4904 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4907 case 0xc8: /* enter */
4908 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
4909 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4911 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4915 case 0xc9: /* leave */
4916 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4917 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
4920 case 0x07: /* pop es */
4921 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4926 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4927 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM
);
4928 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4931 case 0x17: /* pop ss */
4932 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4937 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4938 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM
);
4939 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4942 case 0x1f: /* pop ds */
4943 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4948 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4949 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM
);
4950 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4953 case 0x0fa1: /* pop fs */
4954 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4955 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM
);
4956 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4959 case 0x0fa9: /* pop gs */
4960 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4961 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM
);
4962 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4965 case 0x88: /* mov */
4969 if ((opcode
& 1) == 0)
4972 ir
.ot
= ir
.dflag
+ OT_WORD
;
4974 if (i386_record_modrm (&ir
))
4979 if (opcode
== 0xc6 || opcode
== 0xc7)
4980 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
4981 if (i386_record_lea_modrm (&ir
))
4986 if (opcode
== 0xc6 || opcode
== 0xc7)
4988 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4990 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4994 case 0x8a: /* mov */
4996 if ((opcode
& 1) == 0)
4999 ir
.ot
= ir
.dflag
+ OT_WORD
;
5000 if (i386_record_modrm (&ir
))
5003 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5005 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
5008 case 0x8c: /* mov seg */
5009 if (i386_record_modrm (&ir
))
5014 opcode
= opcode
<< 8 | ir
.modrm
;
5019 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
5023 if (i386_record_lea_modrm (&ir
))
5028 case 0x8e: /* mov seg */
5029 if (i386_record_modrm (&ir
))
5034 regnum
= X86_RECORD_ES_REGNUM
;
5037 regnum
= X86_RECORD_SS_REGNUM
;
5040 regnum
= X86_RECORD_DS_REGNUM
;
5043 regnum
= X86_RECORD_FS_REGNUM
;
5046 regnum
= X86_RECORD_GS_REGNUM
;
5050 opcode
= opcode
<< 8 | ir
.modrm
;
5054 I386_RECORD_ARCH_LIST_ADD_REG (regnum
);
5055 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5058 case 0x0fb6: /* movzbS */
5059 case 0x0fb7: /* movzwS */
5060 case 0x0fbe: /* movsbS */
5061 case 0x0fbf: /* movswS */
5062 if (i386_record_modrm (&ir
))
5064 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
5067 case 0x8d: /* lea */
5068 if (i386_record_modrm (&ir
))
5073 opcode
= opcode
<< 8 | ir
.modrm
;
5078 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5080 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
5083 case 0xa0: /* mov EAX */
5086 case 0xd7: /* xlat */
5087 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5090 case 0xa2: /* mov EAX */
5092 if (ir
.override
>= 0)
5094 if (record_memory_query
)
5098 target_terminal_ours ();
5100 Process record ignores the memory change of instruction at address %s\n\
5101 because it can't get the value of the segment register.\n\
5102 Do you want to stop the program?"),
5103 paddress (gdbarch
, ir
.orig_addr
));
5104 target_terminal_inferior ();
5111 if ((opcode
& 1) == 0)
5114 ir
.ot
= ir
.dflag
+ OT_WORD
;
5117 if (target_read_memory (ir
.addr
, buf
, 8))
5120 printf_unfiltered (_("Process record: error reading "
5121 "memory at addr 0x%s len = 8.\n"),
5122 paddress (gdbarch
, ir
.addr
));
5126 addr
= extract_unsigned_integer (buf
, 8, byte_order
);
5130 if (target_read_memory (ir
.addr
, buf
, 4))
5133 printf_unfiltered (_("Process record: error reading "
5134 "memory at addr 0x%s len = 4.\n"),
5135 paddress (gdbarch
, ir
.addr
));
5139 addr
= extract_unsigned_integer (buf
, 4, byte_order
);
5143 if (target_read_memory (ir
.addr
, buf
, 2))
5146 printf_unfiltered (_("Process record: error reading "
5147 "memory at addr 0x%s len = 2.\n"),
5148 paddress (gdbarch
, ir
.addr
));
5152 addr
= extract_unsigned_integer (buf
, 2, byte_order
);
5154 if (record_arch_list_add_mem (addr
, 1 << ir
.ot
))
5159 case 0xb0: /* mov R, Ib */
5167 I386_RECORD_ARCH_LIST_ADD_REG ((ir
.regmap
[X86_RECORD_R8_REGNUM
])
5168 ? ((opcode
& 0x7) | ir
.rex_b
)
5169 : ((opcode
& 0x7) & 0x3));
5172 case 0xb8: /* mov R, Iv */
5180 I386_RECORD_ARCH_LIST_ADD_REG ((opcode
& 0x7) | ir
.rex_b
);
5183 case 0x91: /* xchg R, EAX */
5190 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5191 I386_RECORD_ARCH_LIST_ADD_REG (opcode
& 0x7);
5194 case 0x86: /* xchg Ev, Gv */
5196 if ((opcode
& 1) == 0)
5199 ir
.ot
= ir
.dflag
+ OT_WORD
;
5200 if (i386_record_modrm (&ir
))
5205 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5207 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
5211 if (i386_record_lea_modrm (&ir
))
5215 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5217 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
5220 case 0xc4: /* les Gv */
5221 case 0xc5: /* lds Gv */
5222 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5228 case 0x0fb2: /* lss Gv */
5229 case 0x0fb4: /* lfs Gv */
5230 case 0x0fb5: /* lgs Gv */
5231 if (i386_record_modrm (&ir
))
5239 opcode
= opcode
<< 8 | ir
.modrm
;
5244 case 0xc4: /* les Gv */
5245 regnum
= X86_RECORD_ES_REGNUM
;
5247 case 0xc5: /* lds Gv */
5248 regnum
= X86_RECORD_DS_REGNUM
;
5250 case 0x0fb2: /* lss Gv */
5251 regnum
= X86_RECORD_SS_REGNUM
;
5253 case 0x0fb4: /* lfs Gv */
5254 regnum
= X86_RECORD_FS_REGNUM
;
5256 case 0x0fb5: /* lgs Gv */
5257 regnum
= X86_RECORD_GS_REGNUM
;
5260 I386_RECORD_ARCH_LIST_ADD_REG (regnum
);
5261 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
5262 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5265 case 0xc0: /* shifts */
5271 if ((opcode
& 1) == 0)
5274 ir
.ot
= ir
.dflag
+ OT_WORD
;
5275 if (i386_record_modrm (&ir
))
5277 if (ir
.mod
!= 3 && (opcode
== 0xd2 || opcode
== 0xd3))
5279 if (i386_record_lea_modrm (&ir
))
5285 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5287 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
5289 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5296 if (i386_record_modrm (&ir
))
5300 if (record_arch_list_add_reg (ir
.regcache
, ir
.rm
))
5305 if (i386_record_lea_modrm (&ir
))
5310 case 0xd8: /* Floats. */
5318 if (i386_record_modrm (&ir
))
5320 ir
.reg
|= ((opcode
& 7) << 3);
5326 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
5334 /* For fcom, ficom nothing to do. */
5340 /* For fcomp, ficomp pop FPU stack, store all. */
5341 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5368 /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul,
5369 fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension
5370 of code, always affects st(0) register. */
5371 if (i386_record_floats (gdbarch
, &ir
, I387_ST0_REGNUM (tdep
)))
5395 /* Handling fld, fild. */
5396 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5400 switch (ir
.reg
>> 4)
5403 if (record_arch_list_add_mem (addr64
, 4))
5407 if (record_arch_list_add_mem (addr64
, 8))
5413 if (record_arch_list_add_mem (addr64
, 2))
5419 switch (ir
.reg
>> 4)
5422 if (record_arch_list_add_mem (addr64
, 4))
5424 if (3 == (ir
.reg
& 7))
5426 /* For fstp m32fp. */
5427 if (i386_record_floats (gdbarch
, &ir
,
5428 I386_SAVE_FPU_REGS
))
5433 if (record_arch_list_add_mem (addr64
, 4))
5435 if ((3 == (ir
.reg
& 7))
5436 || (5 == (ir
.reg
& 7))
5437 || (7 == (ir
.reg
& 7)))
5439 /* For fstp insn. */
5440 if (i386_record_floats (gdbarch
, &ir
,
5441 I386_SAVE_FPU_REGS
))
5446 if (record_arch_list_add_mem (addr64
, 8))
5448 if (3 == (ir
.reg
& 7))
5450 /* For fstp m64fp. */
5451 if (i386_record_floats (gdbarch
, &ir
,
5452 I386_SAVE_FPU_REGS
))
5457 if ((3 <= (ir
.reg
& 7)) && (6 <= (ir
.reg
& 7)))
5459 /* For fistp, fbld, fild, fbstp. */
5460 if (i386_record_floats (gdbarch
, &ir
,
5461 I386_SAVE_FPU_REGS
))
5466 if (record_arch_list_add_mem (addr64
, 2))
5475 if (i386_record_floats (gdbarch
, &ir
,
5476 I386_SAVE_FPU_ENV_REG_STACK
))
5481 if (i386_record_floats (gdbarch
, &ir
, I387_FCTRL_REGNUM (tdep
)))
5486 if (i386_record_floats (gdbarch
, &ir
,
5487 I386_SAVE_FPU_ENV_REG_STACK
))
5493 if (record_arch_list_add_mem (addr64
, 28))
5498 if (record_arch_list_add_mem (addr64
, 14))
5504 if (record_arch_list_add_mem (addr64
, 2))
5506 /* Insn fstp, fbstp. */
5507 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5512 if (record_arch_list_add_mem (addr64
, 10))
5518 if (record_arch_list_add_mem (addr64
, 28))
5524 if (record_arch_list_add_mem (addr64
, 14))
5528 if (record_arch_list_add_mem (addr64
, 80))
5531 if (i386_record_floats (gdbarch
, &ir
,
5532 I386_SAVE_FPU_ENV_REG_STACK
))
5536 if (record_arch_list_add_mem (addr64
, 8))
5539 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5544 opcode
= opcode
<< 8 | ir
.modrm
;
5549 /* Opcode is an extension of modR/M byte. */
5555 if (i386_record_floats (gdbarch
, &ir
, I387_ST0_REGNUM (tdep
)))
5559 if (0x0c == (ir
.modrm
>> 4))
5561 if ((ir
.modrm
& 0x0f) <= 7)
5563 if (i386_record_floats (gdbarch
, &ir
,
5564 I386_SAVE_FPU_REGS
))
5569 if (i386_record_floats (gdbarch
, &ir
,
5570 I387_ST0_REGNUM (tdep
)))
5572 /* If only st(0) is changing, then we have already
5574 if ((ir
.modrm
& 0x0f) - 0x08)
5576 if (i386_record_floats (gdbarch
, &ir
,
5577 I387_ST0_REGNUM (tdep
) +
5578 ((ir
.modrm
& 0x0f) - 0x08)))
5596 if (i386_record_floats (gdbarch
, &ir
,
5597 I387_ST0_REGNUM (tdep
)))
5615 if (i386_record_floats (gdbarch
, &ir
,
5616 I386_SAVE_FPU_REGS
))
5620 if (i386_record_floats (gdbarch
, &ir
,
5621 I387_ST0_REGNUM (tdep
)))
5623 if (i386_record_floats (gdbarch
, &ir
,
5624 I387_ST0_REGNUM (tdep
) + 1))
5631 if (0xe9 == ir
.modrm
)
5633 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5636 else if ((0x0c == ir
.modrm
>> 4) || (0x0d == ir
.modrm
>> 4))
5638 if (i386_record_floats (gdbarch
, &ir
,
5639 I387_ST0_REGNUM (tdep
)))
5641 if (((ir
.modrm
& 0x0f) > 0) && ((ir
.modrm
& 0x0f) <= 7))
5643 if (i386_record_floats (gdbarch
, &ir
,
5644 I387_ST0_REGNUM (tdep
) +
5648 else if ((ir
.modrm
& 0x0f) - 0x08)
5650 if (i386_record_floats (gdbarch
, &ir
,
5651 I387_ST0_REGNUM (tdep
) +
5652 ((ir
.modrm
& 0x0f) - 0x08)))
5658 if (0xe3 == ir
.modrm
)
5660 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_ENV
))
5663 else if ((0x0c == ir
.modrm
>> 4) || (0x0d == ir
.modrm
>> 4))
5665 if (i386_record_floats (gdbarch
, &ir
,
5666 I387_ST0_REGNUM (tdep
)))
5668 if (((ir
.modrm
& 0x0f) > 0) && ((ir
.modrm
& 0x0f) <= 7))
5670 if (i386_record_floats (gdbarch
, &ir
,
5671 I387_ST0_REGNUM (tdep
) +
5675 else if ((ir
.modrm
& 0x0f) - 0x08)
5677 if (i386_record_floats (gdbarch
, &ir
,
5678 I387_ST0_REGNUM (tdep
) +
5679 ((ir
.modrm
& 0x0f) - 0x08)))
5685 if ((0x0c == ir
.modrm
>> 4)
5686 || (0x0d == ir
.modrm
>> 4)
5687 || (0x0f == ir
.modrm
>> 4))
5689 if ((ir
.modrm
& 0x0f) <= 7)
5691 if (i386_record_floats (gdbarch
, &ir
,
5692 I387_ST0_REGNUM (tdep
) +
5698 if (i386_record_floats (gdbarch
, &ir
,
5699 I387_ST0_REGNUM (tdep
) +
5700 ((ir
.modrm
& 0x0f) - 0x08)))
5706 if (0x0c == ir
.modrm
>> 4)
5708 if (i386_record_floats (gdbarch
, &ir
,
5709 I387_FTAG_REGNUM (tdep
)))
5712 else if ((0x0d == ir
.modrm
>> 4) || (0x0e == ir
.modrm
>> 4))
5714 if ((ir
.modrm
& 0x0f) <= 7)
5716 if (i386_record_floats (gdbarch
, &ir
,
5717 I387_ST0_REGNUM (tdep
) +
5723 if (i386_record_floats (gdbarch
, &ir
,
5724 I386_SAVE_FPU_REGS
))
5730 if ((0x0c == ir
.modrm
>> 4)
5731 || (0x0e == ir
.modrm
>> 4)
5732 || (0x0f == ir
.modrm
>> 4)
5733 || (0xd9 == ir
.modrm
))
5735 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5740 if (0xe0 == ir
.modrm
)
5742 if (record_arch_list_add_reg (ir
.regcache
, I386_EAX_REGNUM
))
5745 else if ((0x0f == ir
.modrm
>> 4) || (0x0e == ir
.modrm
>> 4))
5747 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5755 case 0xa4: /* movsS */
5757 case 0xaa: /* stosS */
5759 case 0x6c: /* insS */
5761 regcache_raw_read_unsigned (ir
.regcache
,
5762 ir
.regmap
[X86_RECORD_RECX_REGNUM
],
5768 if ((opcode
& 1) == 0)
5771 ir
.ot
= ir
.dflag
+ OT_WORD
;
5772 regcache_raw_read_unsigned (ir
.regcache
,
5773 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
5776 regcache_raw_read_unsigned (ir
.regcache
,
5777 ir
.regmap
[X86_RECORD_ES_REGNUM
],
5779 regcache_raw_read_unsigned (ir
.regcache
,
5780 ir
.regmap
[X86_RECORD_DS_REGNUM
],
5782 if (ir
.aflag
&& (es
!= ds
))
5784 /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */
5785 if (record_memory_query
)
5789 target_terminal_ours ();
5791 Process record ignores the memory change of instruction at address %s\n\
5792 because it can't get the value of the segment register.\n\
5793 Do you want to stop the program?"),
5794 paddress (gdbarch
, ir
.orig_addr
));
5795 target_terminal_inferior ();
5802 if (record_arch_list_add_mem (addr
, 1 << ir
.ot
))
5806 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5807 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5808 if (opcode
== 0xa4 || opcode
== 0xa5)
5809 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
5810 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
5811 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5815 case 0xa6: /* cmpsS */
5817 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
5818 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
5819 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5820 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5821 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5824 case 0xac: /* lodsS */
5826 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5827 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
5828 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5829 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5830 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5833 case 0xae: /* scasS */
5835 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
5836 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5837 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5838 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5841 case 0x6e: /* outsS */
5843 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
5844 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5845 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5846 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5849 case 0xe4: /* port I/O */
5853 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5854 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5864 case 0xc2: /* ret im */
5865 case 0xc3: /* ret */
5866 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5867 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5870 case 0xca: /* lret im */
5871 case 0xcb: /* lret */
5872 case 0xcf: /* iret */
5873 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
5874 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5875 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5878 case 0xe8: /* call im */
5879 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5881 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5885 case 0x9a: /* lcall im */
5886 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5891 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
5892 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5896 case 0xe9: /* jmp im */
5897 case 0xea: /* ljmp im */
5898 case 0xeb: /* jmp Jb */
5899 case 0x70: /* jcc Jb */
5915 case 0x0f80: /* jcc Jv */
5933 case 0x0f90: /* setcc Gv */
5949 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5951 if (i386_record_modrm (&ir
))
5954 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rex_b
? (ir
.rm
| ir
.rex_b
)
5958 if (i386_record_lea_modrm (&ir
))
5963 case 0x0f40: /* cmov Gv, Ev */
5979 if (i386_record_modrm (&ir
))
5982 if (ir
.dflag
== OT_BYTE
)
5984 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
5988 case 0x9c: /* pushf */
5989 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5990 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5992 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5996 case 0x9d: /* popf */
5997 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5998 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6001 case 0x9e: /* sahf */
6002 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6008 case 0xf5: /* cmc */
6009 case 0xf8: /* clc */
6010 case 0xf9: /* stc */
6011 case 0xfc: /* cld */
6012 case 0xfd: /* std */
6013 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6016 case 0x9f: /* lahf */
6017 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6022 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6023 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6026 /* bit operations */
6027 case 0x0fba: /* bt/bts/btr/btc Gv, im */
6028 ir
.ot
= ir
.dflag
+ OT_WORD
;
6029 if (i386_record_modrm (&ir
))
6034 opcode
= opcode
<< 8 | ir
.modrm
;
6040 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6043 if (i386_record_lea_modrm (&ir
))
6047 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6050 case 0x0fa3: /* bt Gv, Ev */
6051 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6054 case 0x0fab: /* bts */
6055 case 0x0fb3: /* btr */
6056 case 0x0fbb: /* btc */
6057 ir
.ot
= ir
.dflag
+ OT_WORD
;
6058 if (i386_record_modrm (&ir
))
6061 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6065 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
6067 regcache_raw_read_unsigned (ir
.regcache
,
6068 ir
.regmap
[ir
.reg
| rex_r
],
6073 addr64
+= ((int16_t) addr
>> 4) << 4;
6076 addr64
+= ((int32_t) addr
>> 5) << 5;
6079 addr64
+= ((int64_t) addr
>> 6) << 6;
6082 if (record_arch_list_add_mem (addr64
, 1 << ir
.ot
))
6084 if (i386_record_lea_modrm (&ir
))
6087 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6090 case 0x0fbc: /* bsf */
6091 case 0x0fbd: /* bsr */
6092 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
6093 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6097 case 0x27: /* daa */
6098 case 0x2f: /* das */
6099 case 0x37: /* aaa */
6100 case 0x3f: /* aas */
6101 case 0xd4: /* aam */
6102 case 0xd5: /* aad */
6103 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6108 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6109 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6113 case 0x90: /* nop */
6114 if (prefixes
& PREFIX_LOCK
)
6121 case 0x9b: /* fwait */
6122 if (target_read_memory (ir
.addr
, &opcode8
, 1))
6125 printf_unfiltered (_("Process record: error reading memory at "
6126 "addr 0x%s len = 1.\n"),
6127 paddress (gdbarch
, ir
.addr
));
6130 opcode
= (uint32_t) opcode8
;
6136 case 0xcc: /* int3 */
6137 printf_unfiltered (_("Process record does not support instruction "
6144 case 0xcd: /* int */
6148 if (target_read_memory (ir
.addr
, &interrupt
, 1))
6151 printf_unfiltered (_("Process record: error reading memory "
6152 "at addr %s len = 1.\n"),
6153 paddress (gdbarch
, ir
.addr
));
6157 if (interrupt
!= 0x80
6158 || tdep
->i386_intx80_record
== NULL
)
6160 printf_unfiltered (_("Process record does not support "
6161 "instruction int 0x%02x.\n"),
6166 ret
= tdep
->i386_intx80_record (ir
.regcache
);
6173 case 0xce: /* into */
6174 printf_unfiltered (_("Process record does not support "
6175 "instruction into.\n"));
6180 case 0xfa: /* cli */
6181 case 0xfb: /* sti */
6184 case 0x62: /* bound */
6185 printf_unfiltered (_("Process record does not support "
6186 "instruction bound.\n"));
6191 case 0x0fc8: /* bswap reg */
6199 I386_RECORD_ARCH_LIST_ADD_REG ((opcode
& 7) | ir
.rex_b
);
6202 case 0xd6: /* salc */
6203 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6208 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6209 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6212 case 0xe0: /* loopnz */
6213 case 0xe1: /* loopz */
6214 case 0xe2: /* loop */
6215 case 0xe3: /* jecxz */
6216 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6217 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6220 case 0x0f30: /* wrmsr */
6221 printf_unfiltered (_("Process record does not support "
6222 "instruction wrmsr.\n"));
6227 case 0x0f32: /* rdmsr */
6228 printf_unfiltered (_("Process record does not support "
6229 "instruction rdmsr.\n"));
6234 case 0x0f31: /* rdtsc */
6235 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6236 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
6239 case 0x0f34: /* sysenter */
6242 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6247 if (tdep
->i386_sysenter_record
== NULL
)
6249 printf_unfiltered (_("Process record does not support "
6250 "instruction sysenter.\n"));
6254 ret
= tdep
->i386_sysenter_record (ir
.regcache
);
6260 case 0x0f35: /* sysexit */
6261 printf_unfiltered (_("Process record does not support "
6262 "instruction sysexit.\n"));
6267 case 0x0f05: /* syscall */
6270 if (tdep
->i386_syscall_record
== NULL
)
6272 printf_unfiltered (_("Process record does not support "
6273 "instruction syscall.\n"));
6277 ret
= tdep
->i386_syscall_record (ir
.regcache
);
6283 case 0x0f07: /* sysret */
6284 printf_unfiltered (_("Process record does not support "
6285 "instruction sysret.\n"));
6290 case 0x0fa2: /* cpuid */
6291 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6292 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6293 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
6294 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM
);
6297 case 0xf4: /* hlt */
6298 printf_unfiltered (_("Process record does not support "
6299 "instruction hlt.\n"));
6305 if (i386_record_modrm (&ir
))
6312 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6316 if (i386_record_lea_modrm (&ir
))
6325 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6329 opcode
= opcode
<< 8 | ir
.modrm
;
6336 if (i386_record_modrm (&ir
))
6347 opcode
= opcode
<< 8 | ir
.modrm
;
6350 if (ir
.override
>= 0)
6352 if (record_memory_query
)
6356 target_terminal_ours ();
6358 Process record ignores the memory change of instruction at address %s\n\
6359 because it can't get the value of the segment register.\n\
6360 Do you want to stop the program?"),
6361 paddress (gdbarch
, ir
.orig_addr
));
6362 target_terminal_inferior ();
6369 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
6371 if (record_arch_list_add_mem (addr64
, 2))
6374 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6376 if (record_arch_list_add_mem (addr64
, 8))
6381 if (record_arch_list_add_mem (addr64
, 4))
6392 case 0: /* monitor */
6395 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6399 opcode
= opcode
<< 8 | ir
.modrm
;
6407 if (ir
.override
>= 0)
6409 if (record_memory_query
)
6413 target_terminal_ours ();
6415 Process record ignores the memory change of instruction at address %s\n\
6416 because it can't get the value of the segment register.\n\
6417 Do you want to stop the program?"),
6418 paddress (gdbarch
, ir
.orig_addr
));
6419 target_terminal_inferior ();
6428 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
6430 if (record_arch_list_add_mem (addr64
, 2))
6433 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6435 if (record_arch_list_add_mem (addr64
, 8))
6440 if (record_arch_list_add_mem (addr64
, 4))
6452 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6453 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
6457 else if (ir
.rm
== 1)
6464 opcode
= opcode
<< 8 | ir
.modrm
;
6471 if (record_arch_list_add_reg (ir
.regcache
, ir
.rm
| ir
.rex_b
))
6477 if (i386_record_lea_modrm (&ir
))
6480 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6483 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6485 case 7: /* invlpg */
6488 if (ir
.rm
== 0 && ir
.regmap
[X86_RECORD_R8_REGNUM
])
6489 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM
);
6493 opcode
= opcode
<< 8 | ir
.modrm
;
6498 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6502 opcode
= opcode
<< 8 | ir
.modrm
;
6508 case 0x0f08: /* invd */
6509 case 0x0f09: /* wbinvd */
6512 case 0x63: /* arpl */
6513 if (i386_record_modrm (&ir
))
6515 if (ir
.mod
== 3 || ir
.regmap
[X86_RECORD_R8_REGNUM
])
6517 I386_RECORD_ARCH_LIST_ADD_REG (ir
.regmap
[X86_RECORD_R8_REGNUM
]
6518 ? (ir
.reg
| rex_r
) : ir
.rm
);
6522 ir
.ot
= ir
.dflag
? OT_LONG
: OT_WORD
;
6523 if (i386_record_lea_modrm (&ir
))
6526 if (!ir
.regmap
[X86_RECORD_R8_REGNUM
])
6527 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6530 case 0x0f02: /* lar */
6531 case 0x0f03: /* lsl */
6532 if (i386_record_modrm (&ir
))
6534 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
6535 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6539 if (i386_record_modrm (&ir
))
6541 if (ir
.mod
== 3 && ir
.reg
== 3)
6544 opcode
= opcode
<< 8 | ir
.modrm
;
6556 /* nop (multi byte) */
6559 case 0x0f20: /* mov reg, crN */
6560 case 0x0f22: /* mov crN, reg */
6561 if (i386_record_modrm (&ir
))
6563 if ((ir
.modrm
& 0xc0) != 0xc0)
6566 opcode
= opcode
<< 8 | ir
.modrm
;
6577 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6579 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6583 opcode
= opcode
<< 8 | ir
.modrm
;
6589 case 0x0f21: /* mov reg, drN */
6590 case 0x0f23: /* mov drN, reg */
6591 if (i386_record_modrm (&ir
))
6593 if ((ir
.modrm
& 0xc0) != 0xc0 || ir
.reg
== 4
6594 || ir
.reg
== 5 || ir
.reg
>= 8)
6597 opcode
= opcode
<< 8 | ir
.modrm
;
6601 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6603 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6606 case 0x0f06: /* clts */
6607 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6610 /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */
6612 case 0x0f0d: /* 3DNow! prefetch */
6615 case 0x0f0e: /* 3DNow! femms */
6616 case 0x0f77: /* emms */
6617 if (i386_fpc_regnum_p (gdbarch
, I387_FTAG_REGNUM(tdep
)))
6619 record_arch_list_add_reg (ir
.regcache
, I387_FTAG_REGNUM(tdep
));
6622 case 0x0f0f: /* 3DNow! data */
6623 if (i386_record_modrm (&ir
))
6625 if (target_read_memory (ir
.addr
, &opcode8
, 1))
6627 printf_unfiltered (_("Process record: error reading memory at "
6628 "addr %s len = 1.\n"),
6629 paddress (gdbarch
, ir
.addr
));
6635 case 0x0c: /* 3DNow! pi2fw */
6636 case 0x0d: /* 3DNow! pi2fd */
6637 case 0x1c: /* 3DNow! pf2iw */
6638 case 0x1d: /* 3DNow! pf2id */
6639 case 0x8a: /* 3DNow! pfnacc */
6640 case 0x8e: /* 3DNow! pfpnacc */
6641 case 0x90: /* 3DNow! pfcmpge */
6642 case 0x94: /* 3DNow! pfmin */
6643 case 0x96: /* 3DNow! pfrcp */
6644 case 0x97: /* 3DNow! pfrsqrt */
6645 case 0x9a: /* 3DNow! pfsub */
6646 case 0x9e: /* 3DNow! pfadd */
6647 case 0xa0: /* 3DNow! pfcmpgt */
6648 case 0xa4: /* 3DNow! pfmax */
6649 case 0xa6: /* 3DNow! pfrcpit1 */
6650 case 0xa7: /* 3DNow! pfrsqit1 */
6651 case 0xaa: /* 3DNow! pfsubr */
6652 case 0xae: /* 3DNow! pfacc */
6653 case 0xb0: /* 3DNow! pfcmpeq */
6654 case 0xb4: /* 3DNow! pfmul */
6655 case 0xb6: /* 3DNow! pfrcpit2 */
6656 case 0xb7: /* 3DNow! pmulhrw */
6657 case 0xbb: /* 3DNow! pswapd */
6658 case 0xbf: /* 3DNow! pavgusb */
6659 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.reg
))
6660 goto no_support_3dnow_data
;
6661 record_arch_list_add_reg (ir
.regcache
, ir
.reg
);
6665 no_support_3dnow_data
:
6666 opcode
= (opcode
<< 8) | opcode8
;
6672 case 0x0faa: /* rsm */
6673 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6674 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6675 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6676 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
6677 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM
);
6678 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
6679 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
6680 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
6681 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
6685 if (i386_record_modrm (&ir
))
6689 case 0: /* fxsave */
6693 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6694 if (i386_record_lea_modrm_addr (&ir
, &tmpu64
))
6696 if (record_arch_list_add_mem (tmpu64
, 512))
6701 case 1: /* fxrstor */
6705 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6707 for (i
= I387_MM0_REGNUM (tdep
);
6708 i386_mmx_regnum_p (gdbarch
, i
); i
++)
6709 record_arch_list_add_reg (ir
.regcache
, i
);
6711 for (i
= I387_XMM0_REGNUM (tdep
);
6712 i386_xmm_regnum_p (gdbarch
, i
); i
++)
6713 record_arch_list_add_reg (ir
.regcache
, i
);
6715 if (i386_mxcsr_regnum_p (gdbarch
, I387_MXCSR_REGNUM(tdep
)))
6716 record_arch_list_add_reg (ir
.regcache
, I387_MXCSR_REGNUM(tdep
));
6718 for (i
= I387_ST0_REGNUM (tdep
);
6719 i386_fp_regnum_p (gdbarch
, i
); i
++)
6720 record_arch_list_add_reg (ir
.regcache
, i
);
6722 for (i
= I387_FCTRL_REGNUM (tdep
);
6723 i386_fpc_regnum_p (gdbarch
, i
); i
++)
6724 record_arch_list_add_reg (ir
.regcache
, i
);
6728 case 2: /* ldmxcsr */
6729 if (!i386_mxcsr_regnum_p (gdbarch
, I387_MXCSR_REGNUM(tdep
)))
6731 record_arch_list_add_reg (ir
.regcache
, I387_MXCSR_REGNUM(tdep
));
6734 case 3: /* stmxcsr */
6736 if (i386_record_lea_modrm (&ir
))
6740 case 5: /* lfence */
6741 case 6: /* mfence */
6742 case 7: /* sfence clflush */
6746 opcode
= (opcode
<< 8) | ir
.modrm
;
6752 case 0x0fc3: /* movnti */
6753 ir
.ot
= (ir
.dflag
== 2) ? OT_QUAD
: OT_LONG
;
6754 if (i386_record_modrm (&ir
))
6759 if (i386_record_lea_modrm (&ir
))
6763 /* Add prefix to opcode. */
6890 reswitch_prefix_add
:
6898 if (target_read_memory (ir
.addr
, &opcode8
, 1))
6900 printf_unfiltered (_("Process record: error reading memory at "
6901 "addr %s len = 1.\n"),
6902 paddress (gdbarch
, ir
.addr
));
6906 opcode
= (uint32_t) opcode8
| opcode
<< 8;
6907 goto reswitch_prefix_add
;
6910 case 0x0f10: /* movups */
6911 case 0x660f10: /* movupd */
6912 case 0xf30f10: /* movss */
6913 case 0xf20f10: /* movsd */
6914 case 0x0f12: /* movlps */
6915 case 0x660f12: /* movlpd */
6916 case 0xf30f12: /* movsldup */
6917 case 0xf20f12: /* movddup */
6918 case 0x0f14: /* unpcklps */
6919 case 0x660f14: /* unpcklpd */
6920 case 0x0f15: /* unpckhps */
6921 case 0x660f15: /* unpckhpd */
6922 case 0x0f16: /* movhps */
6923 case 0x660f16: /* movhpd */
6924 case 0xf30f16: /* movshdup */
6925 case 0x0f28: /* movaps */
6926 case 0x660f28: /* movapd */
6927 case 0x0f2a: /* cvtpi2ps */
6928 case 0x660f2a: /* cvtpi2pd */
6929 case 0xf30f2a: /* cvtsi2ss */
6930 case 0xf20f2a: /* cvtsi2sd */
6931 case 0x0f2c: /* cvttps2pi */
6932 case 0x660f2c: /* cvttpd2pi */
6933 case 0x0f2d: /* cvtps2pi */
6934 case 0x660f2d: /* cvtpd2pi */
6935 case 0x660f3800: /* pshufb */
6936 case 0x660f3801: /* phaddw */
6937 case 0x660f3802: /* phaddd */
6938 case 0x660f3803: /* phaddsw */
6939 case 0x660f3804: /* pmaddubsw */
6940 case 0x660f3805: /* phsubw */
6941 case 0x660f3806: /* phsubd */
6942 case 0x660f3807: /* phsubsw */
6943 case 0x660f3808: /* psignb */
6944 case 0x660f3809: /* psignw */
6945 case 0x660f380a: /* psignd */
6946 case 0x660f380b: /* pmulhrsw */
6947 case 0x660f3810: /* pblendvb */
6948 case 0x660f3814: /* blendvps */
6949 case 0x660f3815: /* blendvpd */
6950 case 0x660f381c: /* pabsb */
6951 case 0x660f381d: /* pabsw */
6952 case 0x660f381e: /* pabsd */
6953 case 0x660f3820: /* pmovsxbw */
6954 case 0x660f3821: /* pmovsxbd */
6955 case 0x660f3822: /* pmovsxbq */
6956 case 0x660f3823: /* pmovsxwd */
6957 case 0x660f3824: /* pmovsxwq */
6958 case 0x660f3825: /* pmovsxdq */
6959 case 0x660f3828: /* pmuldq */
6960 case 0x660f3829: /* pcmpeqq */
6961 case 0x660f382a: /* movntdqa */
6962 case 0x660f3a08: /* roundps */
6963 case 0x660f3a09: /* roundpd */
6964 case 0x660f3a0a: /* roundss */
6965 case 0x660f3a0b: /* roundsd */
6966 case 0x660f3a0c: /* blendps */
6967 case 0x660f3a0d: /* blendpd */
6968 case 0x660f3a0e: /* pblendw */
6969 case 0x660f3a0f: /* palignr */
6970 case 0x660f3a20: /* pinsrb */
6971 case 0x660f3a21: /* insertps */
6972 case 0x660f3a22: /* pinsrd pinsrq */
6973 case 0x660f3a40: /* dpps */
6974 case 0x660f3a41: /* dppd */
6975 case 0x660f3a42: /* mpsadbw */
6976 case 0x660f3a60: /* pcmpestrm */
6977 case 0x660f3a61: /* pcmpestri */
6978 case 0x660f3a62: /* pcmpistrm */
6979 case 0x660f3a63: /* pcmpistri */
6980 case 0x0f51: /* sqrtps */
6981 case 0x660f51: /* sqrtpd */
6982 case 0xf20f51: /* sqrtsd */
6983 case 0xf30f51: /* sqrtss */
6984 case 0x0f52: /* rsqrtps */
6985 case 0xf30f52: /* rsqrtss */
6986 case 0x0f53: /* rcpps */
6987 case 0xf30f53: /* rcpss */
6988 case 0x0f54: /* andps */
6989 case 0x660f54: /* andpd */
6990 case 0x0f55: /* andnps */
6991 case 0x660f55: /* andnpd */
6992 case 0x0f56: /* orps */
6993 case 0x660f56: /* orpd */
6994 case 0x0f57: /* xorps */
6995 case 0x660f57: /* xorpd */
6996 case 0x0f58: /* addps */
6997 case 0x660f58: /* addpd */
6998 case 0xf20f58: /* addsd */
6999 case 0xf30f58: /* addss */
7000 case 0x0f59: /* mulps */
7001 case 0x660f59: /* mulpd */
7002 case 0xf20f59: /* mulsd */
7003 case 0xf30f59: /* mulss */
7004 case 0x0f5a: /* cvtps2pd */
7005 case 0x660f5a: /* cvtpd2ps */
7006 case 0xf20f5a: /* cvtsd2ss */
7007 case 0xf30f5a: /* cvtss2sd */
7008 case 0x0f5b: /* cvtdq2ps */
7009 case 0x660f5b: /* cvtps2dq */
7010 case 0xf30f5b: /* cvttps2dq */
7011 case 0x0f5c: /* subps */
7012 case 0x660f5c: /* subpd */
7013 case 0xf20f5c: /* subsd */
7014 case 0xf30f5c: /* subss */
7015 case 0x0f5d: /* minps */
7016 case 0x660f5d: /* minpd */
7017 case 0xf20f5d: /* minsd */
7018 case 0xf30f5d: /* minss */
7019 case 0x0f5e: /* divps */
7020 case 0x660f5e: /* divpd */
7021 case 0xf20f5e: /* divsd */
7022 case 0xf30f5e: /* divss */
7023 case 0x0f5f: /* maxps */
7024 case 0x660f5f: /* maxpd */
7025 case 0xf20f5f: /* maxsd */
7026 case 0xf30f5f: /* maxss */
7027 case 0x660f60: /* punpcklbw */
7028 case 0x660f61: /* punpcklwd */
7029 case 0x660f62: /* punpckldq */
7030 case 0x660f63: /* packsswb */
7031 case 0x660f64: /* pcmpgtb */
7032 case 0x660f65: /* pcmpgtw */
7033 case 0x660f66: /* pcmpgtd */
7034 case 0x660f67: /* packuswb */
7035 case 0x660f68: /* punpckhbw */
7036 case 0x660f69: /* punpckhwd */
7037 case 0x660f6a: /* punpckhdq */
7038 case 0x660f6b: /* packssdw */
7039 case 0x660f6c: /* punpcklqdq */
7040 case 0x660f6d: /* punpckhqdq */
7041 case 0x660f6e: /* movd */
7042 case 0x660f6f: /* movdqa */
7043 case 0xf30f6f: /* movdqu */
7044 case 0x660f70: /* pshufd */
7045 case 0xf20f70: /* pshuflw */
7046 case 0xf30f70: /* pshufhw */
7047 case 0x660f74: /* pcmpeqb */
7048 case 0x660f75: /* pcmpeqw */
7049 case 0x660f76: /* pcmpeqd */
7050 case 0x660f7c: /* haddpd */
7051 case 0xf20f7c: /* haddps */
7052 case 0x660f7d: /* hsubpd */
7053 case 0xf20f7d: /* hsubps */
7054 case 0xf30f7e: /* movq */
7055 case 0x0fc2: /* cmpps */
7056 case 0x660fc2: /* cmppd */
7057 case 0xf20fc2: /* cmpsd */
7058 case 0xf30fc2: /* cmpss */
7059 case 0x660fc4: /* pinsrw */
7060 case 0x0fc6: /* shufps */
7061 case 0x660fc6: /* shufpd */
7062 case 0x660fd0: /* addsubpd */
7063 case 0xf20fd0: /* addsubps */
7064 case 0x660fd1: /* psrlw */
7065 case 0x660fd2: /* psrld */
7066 case 0x660fd3: /* psrlq */
7067 case 0x660fd4: /* paddq */
7068 case 0x660fd5: /* pmullw */
7069 case 0xf30fd6: /* movq2dq */
7070 case 0x660fd8: /* psubusb */
7071 case 0x660fd9: /* psubusw */
7072 case 0x660fda: /* pminub */
7073 case 0x660fdb: /* pand */
7074 case 0x660fdc: /* paddusb */
7075 case 0x660fdd: /* paddusw */
7076 case 0x660fde: /* pmaxub */
7077 case 0x660fdf: /* pandn */
7078 case 0x660fe0: /* pavgb */
7079 case 0x660fe1: /* psraw */
7080 case 0x660fe2: /* psrad */
7081 case 0x660fe3: /* pavgw */
7082 case 0x660fe4: /* pmulhuw */
7083 case 0x660fe5: /* pmulhw */
7084 case 0x660fe6: /* cvttpd2dq */
7085 case 0xf20fe6: /* cvtpd2dq */
7086 case 0xf30fe6: /* cvtdq2pd */
7087 case 0x660fe8: /* psubsb */
7088 case 0x660fe9: /* psubsw */
7089 case 0x660fea: /* pminsw */
7090 case 0x660feb: /* por */
7091 case 0x660fec: /* paddsb */
7092 case 0x660fed: /* paddsw */
7093 case 0x660fee: /* pmaxsw */
7094 case 0x660fef: /* pxor */
7095 case 0xf20ff0: /* lddqu */
7096 case 0x660ff1: /* psllw */
7097 case 0x660ff2: /* pslld */
7098 case 0x660ff3: /* psllq */
7099 case 0x660ff4: /* pmuludq */
7100 case 0x660ff5: /* pmaddwd */
7101 case 0x660ff6: /* psadbw */
7102 case 0x660ff8: /* psubb */
7103 case 0x660ff9: /* psubw */
7104 case 0x660ffa: /* psubd */
7105 case 0x660ffb: /* psubq */
7106 case 0x660ffc: /* paddb */
7107 case 0x660ffd: /* paddw */
7108 case 0x660ffe: /* paddd */
7109 if (i386_record_modrm (&ir
))
7112 if (!i386_xmm_regnum_p (gdbarch
, I387_XMM0_REGNUM (tdep
) + ir
.reg
))
7114 record_arch_list_add_reg (ir
.regcache
,
7115 I387_XMM0_REGNUM (tdep
) + ir
.reg
);
7116 if ((opcode
& 0xfffffffc) == 0x660f3a60)
7117 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7120 case 0x0f11: /* movups */
7121 case 0x660f11: /* movupd */
7122 case 0xf30f11: /* movss */
7123 case 0xf20f11: /* movsd */
7124 case 0x0f13: /* movlps */
7125 case 0x660f13: /* movlpd */
7126 case 0x0f17: /* movhps */
7127 case 0x660f17: /* movhpd */
7128 case 0x0f29: /* movaps */
7129 case 0x660f29: /* movapd */
7130 case 0x660f3a14: /* pextrb */
7131 case 0x660f3a15: /* pextrw */
7132 case 0x660f3a16: /* pextrd pextrq */
7133 case 0x660f3a17: /* extractps */
7134 case 0x660f7f: /* movdqa */
7135 case 0xf30f7f: /* movdqu */
7136 if (i386_record_modrm (&ir
))
7140 if (opcode
== 0x0f13 || opcode
== 0x660f13
7141 || opcode
== 0x0f17 || opcode
== 0x660f17)
7144 if (!i386_xmm_regnum_p (gdbarch
,
7145 I387_XMM0_REGNUM (tdep
) + ir
.rm
))
7147 record_arch_list_add_reg (ir
.regcache
,
7148 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
7170 if (i386_record_lea_modrm (&ir
))
7175 case 0x0f2b: /* movntps */
7176 case 0x660f2b: /* movntpd */
7177 case 0x0fe7: /* movntq */
7178 case 0x660fe7: /* movntdq */
7181 if (opcode
== 0x0fe7)
7185 if (i386_record_lea_modrm (&ir
))
7189 case 0xf30f2c: /* cvttss2si */
7190 case 0xf20f2c: /* cvttsd2si */
7191 case 0xf30f2d: /* cvtss2si */
7192 case 0xf20f2d: /* cvtsd2si */
7193 case 0xf20f38f0: /* crc32 */
7194 case 0xf20f38f1: /* crc32 */
7195 case 0x0f50: /* movmskps */
7196 case 0x660f50: /* movmskpd */
7197 case 0x0fc5: /* pextrw */
7198 case 0x660fc5: /* pextrw */
7199 case 0x0fd7: /* pmovmskb */
7200 case 0x660fd7: /* pmovmskb */
7201 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
7204 case 0x0f3800: /* pshufb */
7205 case 0x0f3801: /* phaddw */
7206 case 0x0f3802: /* phaddd */
7207 case 0x0f3803: /* phaddsw */
7208 case 0x0f3804: /* pmaddubsw */
7209 case 0x0f3805: /* phsubw */
7210 case 0x0f3806: /* phsubd */
7211 case 0x0f3807: /* phsubsw */
7212 case 0x0f3808: /* psignb */
7213 case 0x0f3809: /* psignw */
7214 case 0x0f380a: /* psignd */
7215 case 0x0f380b: /* pmulhrsw */
7216 case 0x0f381c: /* pabsb */
7217 case 0x0f381d: /* pabsw */
7218 case 0x0f381e: /* pabsd */
7219 case 0x0f382b: /* packusdw */
7220 case 0x0f3830: /* pmovzxbw */
7221 case 0x0f3831: /* pmovzxbd */
7222 case 0x0f3832: /* pmovzxbq */
7223 case 0x0f3833: /* pmovzxwd */
7224 case 0x0f3834: /* pmovzxwq */
7225 case 0x0f3835: /* pmovzxdq */
7226 case 0x0f3837: /* pcmpgtq */
7227 case 0x0f3838: /* pminsb */
7228 case 0x0f3839: /* pminsd */
7229 case 0x0f383a: /* pminuw */
7230 case 0x0f383b: /* pminud */
7231 case 0x0f383c: /* pmaxsb */
7232 case 0x0f383d: /* pmaxsd */
7233 case 0x0f383e: /* pmaxuw */
7234 case 0x0f383f: /* pmaxud */
7235 case 0x0f3840: /* pmulld */
7236 case 0x0f3841: /* phminposuw */
7237 case 0x0f3a0f: /* palignr */
7238 case 0x0f60: /* punpcklbw */
7239 case 0x0f61: /* punpcklwd */
7240 case 0x0f62: /* punpckldq */
7241 case 0x0f63: /* packsswb */
7242 case 0x0f64: /* pcmpgtb */
7243 case 0x0f65: /* pcmpgtw */
7244 case 0x0f66: /* pcmpgtd */
7245 case 0x0f67: /* packuswb */
7246 case 0x0f68: /* punpckhbw */
7247 case 0x0f69: /* punpckhwd */
7248 case 0x0f6a: /* punpckhdq */
7249 case 0x0f6b: /* packssdw */
7250 case 0x0f6e: /* movd */
7251 case 0x0f6f: /* movq */
7252 case 0x0f70: /* pshufw */
7253 case 0x0f74: /* pcmpeqb */
7254 case 0x0f75: /* pcmpeqw */
7255 case 0x0f76: /* pcmpeqd */
7256 case 0x0fc4: /* pinsrw */
7257 case 0x0fd1: /* psrlw */
7258 case 0x0fd2: /* psrld */
7259 case 0x0fd3: /* psrlq */
7260 case 0x0fd4: /* paddq */
7261 case 0x0fd5: /* pmullw */
7262 case 0xf20fd6: /* movdq2q */
7263 case 0x0fd8: /* psubusb */
7264 case 0x0fd9: /* psubusw */
7265 case 0x0fda: /* pminub */
7266 case 0x0fdb: /* pand */
7267 case 0x0fdc: /* paddusb */
7268 case 0x0fdd: /* paddusw */
7269 case 0x0fde: /* pmaxub */
7270 case 0x0fdf: /* pandn */
7271 case 0x0fe0: /* pavgb */
7272 case 0x0fe1: /* psraw */
7273 case 0x0fe2: /* psrad */
7274 case 0x0fe3: /* pavgw */
7275 case 0x0fe4: /* pmulhuw */
7276 case 0x0fe5: /* pmulhw */
7277 case 0x0fe8: /* psubsb */
7278 case 0x0fe9: /* psubsw */
7279 case 0x0fea: /* pminsw */
7280 case 0x0feb: /* por */
7281 case 0x0fec: /* paddsb */
7282 case 0x0fed: /* paddsw */
7283 case 0x0fee: /* pmaxsw */
7284 case 0x0fef: /* pxor */
7285 case 0x0ff1: /* psllw */
7286 case 0x0ff2: /* pslld */
7287 case 0x0ff3: /* psllq */
7288 case 0x0ff4: /* pmuludq */
7289 case 0x0ff5: /* pmaddwd */
7290 case 0x0ff6: /* psadbw */
7291 case 0x0ff8: /* psubb */
7292 case 0x0ff9: /* psubw */
7293 case 0x0ffa: /* psubd */
7294 case 0x0ffb: /* psubq */
7295 case 0x0ffc: /* paddb */
7296 case 0x0ffd: /* paddw */
7297 case 0x0ffe: /* paddd */
7298 if (i386_record_modrm (&ir
))
7300 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.reg
))
7302 record_arch_list_add_reg (ir
.regcache
,
7303 I387_MM0_REGNUM (tdep
) + ir
.reg
);
7306 case 0x0f71: /* psllw */
7307 case 0x0f72: /* pslld */
7308 case 0x0f73: /* psllq */
7309 if (i386_record_modrm (&ir
))
7311 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.rm
))
7313 record_arch_list_add_reg (ir
.regcache
,
7314 I387_MM0_REGNUM (tdep
) + ir
.rm
);
7317 case 0x660f71: /* psllw */
7318 case 0x660f72: /* pslld */
7319 case 0x660f73: /* psllq */
7320 if (i386_record_modrm (&ir
))
7323 if (!i386_xmm_regnum_p (gdbarch
, I387_XMM0_REGNUM (tdep
) + ir
.rm
))
7325 record_arch_list_add_reg (ir
.regcache
,
7326 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
7329 case 0x0f7e: /* movd */
7330 case 0x660f7e: /* movd */
7331 if (i386_record_modrm (&ir
))
7334 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
7341 if (i386_record_lea_modrm (&ir
))
7346 case 0x0f7f: /* movq */
7347 if (i386_record_modrm (&ir
))
7351 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.rm
))
7353 record_arch_list_add_reg (ir
.regcache
,
7354 I387_MM0_REGNUM (tdep
) + ir
.rm
);
7359 if (i386_record_lea_modrm (&ir
))
7364 case 0xf30fb8: /* popcnt */
7365 if (i386_record_modrm (&ir
))
7367 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
7368 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7371 case 0x660fd6: /* movq */
7372 if (i386_record_modrm (&ir
))
7377 if (!i386_xmm_regnum_p (gdbarch
,
7378 I387_XMM0_REGNUM (tdep
) + ir
.rm
))
7380 record_arch_list_add_reg (ir
.regcache
,
7381 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
7386 if (i386_record_lea_modrm (&ir
))
7391 case 0x660f3817: /* ptest */
7392 case 0x0f2e: /* ucomiss */
7393 case 0x660f2e: /* ucomisd */
7394 case 0x0f2f: /* comiss */
7395 case 0x660f2f: /* comisd */
7396 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7399 case 0x0ff7: /* maskmovq */
7400 regcache_raw_read_unsigned (ir
.regcache
,
7401 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
7403 if (record_arch_list_add_mem (addr
, 64))
7407 case 0x660ff7: /* maskmovdqu */
7408 regcache_raw_read_unsigned (ir
.regcache
,
7409 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
7411 if (record_arch_list_add_mem (addr
, 128))
7426 /* In the future, maybe still need to deal with need_dasm. */
7427 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM
);
7428 if (record_arch_list_add_end ())
7434 printf_unfiltered (_("Process record does not support instruction 0x%02x "
7435 "at address %s.\n"),
7436 (unsigned int) (opcode
),
7437 paddress (gdbarch
, ir
.orig_addr
));
7441 static const int i386_record_regmap
[] =
7443 I386_EAX_REGNUM
, I386_ECX_REGNUM
, I386_EDX_REGNUM
, I386_EBX_REGNUM
,
7444 I386_ESP_REGNUM
, I386_EBP_REGNUM
, I386_ESI_REGNUM
, I386_EDI_REGNUM
,
7445 0, 0, 0, 0, 0, 0, 0, 0,
7446 I386_EIP_REGNUM
, I386_EFLAGS_REGNUM
, I386_CS_REGNUM
, I386_SS_REGNUM
,
7447 I386_DS_REGNUM
, I386_ES_REGNUM
, I386_FS_REGNUM
, I386_GS_REGNUM
7450 /* Check that the given address appears suitable for a fast
7451 tracepoint, which on x86-64 means that we need an instruction of at
7452 least 5 bytes, so that we can overwrite it with a 4-byte-offset
7453 jump and not have to worry about program jumps to an address in the
7454 middle of the tracepoint jump. On x86, it may be possible to use
7455 4-byte jumps with a 2-byte offset to a trampoline located in the
7456 bottom 64 KiB of memory. Returns 1 if OK, and writes a size
7457 of instruction to replace, and 0 if not, plus an explanatory
7461 i386_fast_tracepoint_valid_at (struct gdbarch
*gdbarch
,
7462 CORE_ADDR addr
, int *isize
, char **msg
)
7465 static struct ui_file
*gdb_null
= NULL
;
7467 /* Ask the target for the minimum instruction length supported. */
7468 jumplen
= target_get_min_fast_tracepoint_insn_len ();
7472 /* If the target does not support the get_min_fast_tracepoint_insn_len
7473 operation, assume that fast tracepoints will always be implemented
7474 using 4-byte relative jumps on both x86 and x86-64. */
7477 else if (jumplen
== 0)
7479 /* If the target does support get_min_fast_tracepoint_insn_len but
7480 returns zero, then the IPA has not loaded yet. In this case,
7481 we optimistically assume that truncated 2-byte relative jumps
7482 will be available on x86, and compensate later if this assumption
7483 turns out to be incorrect. On x86-64 architectures, 4-byte relative
7484 jumps will always be used. */
7485 jumplen
= (register_size (gdbarch
, 0) == 8) ? 5 : 4;
7488 /* Dummy file descriptor for the disassembler. */
7490 gdb_null
= ui_file_new ();
7492 /* Check for fit. */
7493 len
= gdb_print_insn (gdbarch
, addr
, gdb_null
, NULL
);
7499 /* Return a bit of target-specific detail to add to the caller's
7500 generic failure message. */
7502 *msg
= xstrprintf (_("; instruction is only %d bytes long, "
7503 "need at least %d bytes for the jump"),
7516 i386_validate_tdesc_p (struct gdbarch_tdep
*tdep
,
7517 struct tdesc_arch_data
*tdesc_data
)
7519 const struct target_desc
*tdesc
= tdep
->tdesc
;
7520 const struct tdesc_feature
*feature_core
;
7521 const struct tdesc_feature
*feature_sse
, *feature_avx
;
7522 int i
, num_regs
, valid_p
;
7524 if (! tdesc_has_registers (tdesc
))
7527 /* Get core registers. */
7528 feature_core
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.core");
7529 if (feature_core
== NULL
)
7532 /* Get SSE registers. */
7533 feature_sse
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.sse");
7535 /* Try AVX registers. */
7536 feature_avx
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx");
7540 /* The XCR0 bits. */
7543 /* AVX register description requires SSE register description. */
7547 tdep
->xcr0
= I386_XSTATE_AVX_MASK
;
7549 /* It may have been set by OSABI initialization function. */
7550 if (tdep
->num_ymm_regs
== 0)
7552 tdep
->ymmh_register_names
= i386_ymmh_names
;
7553 tdep
->num_ymm_regs
= 8;
7554 tdep
->ymm0h_regnum
= I386_YMM0H_REGNUM
;
7557 for (i
= 0; i
< tdep
->num_ymm_regs
; i
++)
7558 valid_p
&= tdesc_numbered_register (feature_avx
, tdesc_data
,
7559 tdep
->ymm0h_regnum
+ i
,
7560 tdep
->ymmh_register_names
[i
]);
7562 else if (feature_sse
)
7563 tdep
->xcr0
= I386_XSTATE_SSE_MASK
;
7566 tdep
->xcr0
= I386_XSTATE_X87_MASK
;
7567 tdep
->num_xmm_regs
= 0;
7570 num_regs
= tdep
->num_core_regs
;
7571 for (i
= 0; i
< num_regs
; i
++)
7572 valid_p
&= tdesc_numbered_register (feature_core
, tdesc_data
, i
,
7573 tdep
->register_names
[i
]);
7577 /* Need to include %mxcsr, so add one. */
7578 num_regs
+= tdep
->num_xmm_regs
+ 1;
7579 for (; i
< num_regs
; i
++)
7580 valid_p
&= tdesc_numbered_register (feature_sse
, tdesc_data
, i
,
7581 tdep
->register_names
[i
]);
7588 static struct gdbarch
*
7589 i386_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
7591 struct gdbarch_tdep
*tdep
;
7592 struct gdbarch
*gdbarch
;
7593 struct tdesc_arch_data
*tdesc_data
;
7594 const struct target_desc
*tdesc
;
7598 /* If there is already a candidate, use it. */
7599 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
7601 return arches
->gdbarch
;
7603 /* Allocate space for the new architecture. */
7604 tdep
= XCALLOC (1, struct gdbarch_tdep
);
7605 gdbarch
= gdbarch_alloc (&info
, tdep
);
7607 /* General-purpose registers. */
7608 tdep
->gregset
= NULL
;
7609 tdep
->gregset_reg_offset
= NULL
;
7610 tdep
->gregset_num_regs
= I386_NUM_GREGS
;
7611 tdep
->sizeof_gregset
= 0;
7613 /* Floating-point registers. */
7614 tdep
->fpregset
= NULL
;
7615 tdep
->sizeof_fpregset
= I387_SIZEOF_FSAVE
;
7617 tdep
->xstateregset
= NULL
;
7619 /* The default settings include the FPU registers, the MMX registers
7620 and the SSE registers. This can be overridden for a specific ABI
7621 by adjusting the members `st0_regnum', `mm0_regnum' and
7622 `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers
7623 will show up in the output of "info all-registers". */
7625 tdep
->st0_regnum
= I386_ST0_REGNUM
;
7627 /* I386_NUM_XREGS includes %mxcsr, so substract one. */
7628 tdep
->num_xmm_regs
= I386_NUM_XREGS
- 1;
7630 tdep
->jb_pc_offset
= -1;
7631 tdep
->struct_return
= pcc_struct_return
;
7632 tdep
->sigtramp_start
= 0;
7633 tdep
->sigtramp_end
= 0;
7634 tdep
->sigtramp_p
= i386_sigtramp_p
;
7635 tdep
->sigcontext_addr
= NULL
;
7636 tdep
->sc_reg_offset
= NULL
;
7637 tdep
->sc_pc_offset
= -1;
7638 tdep
->sc_sp_offset
= -1;
7640 tdep
->xsave_xcr0_offset
= -1;
7642 tdep
->record_regmap
= i386_record_regmap
;
7644 set_gdbarch_long_long_align_bit (gdbarch
, 32);
7646 /* The format used for `long double' on almost all i386 targets is
7647 the i387 extended floating-point format. In fact, of all targets
7648 in the GCC 2.95 tree, only OSF/1 does it different, and insists
7649 on having a `long double' that's not `long' at all. */
7650 set_gdbarch_long_double_format (gdbarch
, floatformats_i387_ext
);
7652 /* Although the i387 extended floating-point has only 80 significant
7653 bits, a `long double' actually takes up 96, probably to enforce
7655 set_gdbarch_long_double_bit (gdbarch
, 96);
7657 /* Register numbers of various important registers. */
7658 set_gdbarch_sp_regnum (gdbarch
, I386_ESP_REGNUM
); /* %esp */
7659 set_gdbarch_pc_regnum (gdbarch
, I386_EIP_REGNUM
); /* %eip */
7660 set_gdbarch_ps_regnum (gdbarch
, I386_EFLAGS_REGNUM
); /* %eflags */
7661 set_gdbarch_fp0_regnum (gdbarch
, I386_ST0_REGNUM
); /* %st(0) */
7663 /* NOTE: kettenis/20040418: GCC does have two possible register
7664 numbering schemes on the i386: dbx and SVR4. These schemes
7665 differ in how they number %ebp, %esp, %eflags, and the
7666 floating-point registers, and are implemented by the arrays
7667 dbx_register_map[] and svr4_dbx_register_map in
7668 gcc/config/i386.c. GCC also defines a third numbering scheme in
7669 gcc/config/i386.c, which it designates as the "default" register
7670 map used in 64bit mode. This last register numbering scheme is
7671 implemented in dbx64_register_map, and is used for AMD64; see
7674 Currently, each GCC i386 target always uses the same register
7675 numbering scheme across all its supported debugging formats
7676 i.e. SDB (COFF), stabs and DWARF 2. This is because
7677 gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the
7678 DBX_REGISTER_NUMBER macro which is defined by each target's
7679 respective config header in a manner independent of the requested
7680 output debugging format.
7682 This does not match the arrangement below, which presumes that
7683 the SDB and stabs numbering schemes differ from the DWARF and
7684 DWARF 2 ones. The reason for this arrangement is that it is
7685 likely to get the numbering scheme for the target's
7686 default/native debug format right. For targets where GCC is the
7687 native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for
7688 targets where the native toolchain uses a different numbering
7689 scheme for a particular debug format (stabs-in-ELF on Solaris)
7690 the defaults below will have to be overridden, like
7691 i386_elf_init_abi() does. */
7693 /* Use the dbx register numbering scheme for stabs and COFF. */
7694 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
7695 set_gdbarch_sdb_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
7697 /* Use the SVR4 register numbering scheme for DWARF 2. */
7698 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
7700 /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to
7701 be in use on any of the supported i386 targets. */
7703 set_gdbarch_print_float_info (gdbarch
, i387_print_float_info
);
7705 set_gdbarch_get_longjmp_target (gdbarch
, i386_get_longjmp_target
);
7707 /* Call dummy code. */
7708 set_gdbarch_push_dummy_call (gdbarch
, i386_push_dummy_call
);
7709 set_gdbarch_frame_align (gdbarch
, i386_frame_align
);
7711 set_gdbarch_convert_register_p (gdbarch
, i386_convert_register_p
);
7712 set_gdbarch_register_to_value (gdbarch
, i386_register_to_value
);
7713 set_gdbarch_value_to_register (gdbarch
, i386_value_to_register
);
7715 set_gdbarch_return_value (gdbarch
, i386_return_value
);
7717 set_gdbarch_skip_prologue (gdbarch
, i386_skip_prologue
);
7719 /* Stack grows downward. */
7720 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
7722 set_gdbarch_breakpoint_from_pc (gdbarch
, i386_breakpoint_from_pc
);
7723 set_gdbarch_decr_pc_after_break (gdbarch
, 1);
7724 set_gdbarch_max_insn_length (gdbarch
, I386_MAX_INSN_LEN
);
7726 set_gdbarch_frame_args_skip (gdbarch
, 8);
7728 set_gdbarch_print_insn (gdbarch
, i386_print_insn
);
7730 set_gdbarch_dummy_id (gdbarch
, i386_dummy_id
);
7732 set_gdbarch_unwind_pc (gdbarch
, i386_unwind_pc
);
7734 /* Add the i386 register groups. */
7735 i386_add_reggroups (gdbarch
);
7736 tdep
->register_reggroup_p
= i386_register_reggroup_p
;
7738 /* Helper for function argument information. */
7739 set_gdbarch_fetch_pointer_argument (gdbarch
, i386_fetch_pointer_argument
);
7741 /* Hook the function epilogue frame unwinder. This unwinder is
7742 appended to the list first, so that it supercedes the DWARF
7743 unwinder in function epilogues (where the DWARF unwinder
7744 currently fails). */
7745 frame_unwind_append_unwinder (gdbarch
, &i386_epilogue_frame_unwind
);
7747 /* Hook in the DWARF CFI frame unwinder. This unwinder is appended
7748 to the list before the prologue-based unwinders, so that DWARF
7749 CFI info will be used if it is available. */
7750 dwarf2_append_unwinders (gdbarch
);
7752 frame_base_set_default (gdbarch
, &i386_frame_base
);
7754 /* Pseudo registers may be changed by amd64_init_abi. */
7755 set_gdbarch_pseudo_register_read_value (gdbarch
,
7756 i386_pseudo_register_read_value
);
7757 set_gdbarch_pseudo_register_write (gdbarch
, i386_pseudo_register_write
);
7759 set_tdesc_pseudo_register_type (gdbarch
, i386_pseudo_register_type
);
7760 set_tdesc_pseudo_register_name (gdbarch
, i386_pseudo_register_name
);
7762 /* Override the normal target description method to make the AVX
7763 upper halves anonymous. */
7764 set_gdbarch_register_name (gdbarch
, i386_register_name
);
7766 /* Even though the default ABI only includes general-purpose registers,
7767 floating-point registers and the SSE registers, we have to leave a
7768 gap for the upper AVX registers. */
7769 set_gdbarch_num_regs (gdbarch
, I386_AVX_NUM_REGS
);
7771 /* Get the x86 target description from INFO. */
7772 tdesc
= info
.target_desc
;
7773 if (! tdesc_has_registers (tdesc
))
7775 tdep
->tdesc
= tdesc
;
7777 tdep
->num_core_regs
= I386_NUM_GREGS
+ I387_NUM_REGS
;
7778 tdep
->register_names
= i386_register_names
;
7780 /* No upper YMM registers. */
7781 tdep
->ymmh_register_names
= NULL
;
7782 tdep
->ymm0h_regnum
= -1;
7784 tdep
->num_byte_regs
= 8;
7785 tdep
->num_word_regs
= 8;
7786 tdep
->num_dword_regs
= 0;
7787 tdep
->num_mmx_regs
= 8;
7788 tdep
->num_ymm_regs
= 0;
7790 tdesc_data
= tdesc_data_alloc ();
7792 set_gdbarch_relocate_instruction (gdbarch
, i386_relocate_instruction
);
7794 set_gdbarch_gen_return_address (gdbarch
, i386_gen_return_address
);
7796 /* Hook in ABI-specific overrides, if they have been registered. */
7797 info
.tdep_info
= (void *) tdesc_data
;
7798 gdbarch_init_osabi (info
, gdbarch
);
7800 if (!i386_validate_tdesc_p (tdep
, tdesc_data
))
7802 tdesc_data_cleanup (tdesc_data
);
7804 gdbarch_free (gdbarch
);
7808 /* Wire in pseudo registers. Number of pseudo registers may be
7810 set_gdbarch_num_pseudo_regs (gdbarch
, (tdep
->num_byte_regs
7811 + tdep
->num_word_regs
7812 + tdep
->num_dword_regs
7813 + tdep
->num_mmx_regs
7814 + tdep
->num_ymm_regs
));
7816 /* Target description may be changed. */
7817 tdesc
= tdep
->tdesc
;
7819 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
7821 /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */
7822 set_gdbarch_register_reggroup_p (gdbarch
, tdep
->register_reggroup_p
);
7824 /* Make %al the first pseudo-register. */
7825 tdep
->al_regnum
= gdbarch_num_regs (gdbarch
);
7826 tdep
->ax_regnum
= tdep
->al_regnum
+ tdep
->num_byte_regs
;
7828 ymm0_regnum
= tdep
->ax_regnum
+ tdep
->num_word_regs
;
7829 if (tdep
->num_dword_regs
)
7831 /* Support dword pseudo-register if it hasn't been disabled. */
7832 tdep
->eax_regnum
= ymm0_regnum
;
7833 ymm0_regnum
+= tdep
->num_dword_regs
;
7836 tdep
->eax_regnum
= -1;
7838 mm0_regnum
= ymm0_regnum
;
7839 if (tdep
->num_ymm_regs
)
7841 /* Support YMM pseudo-register if it is available. */
7842 tdep
->ymm0_regnum
= ymm0_regnum
;
7843 mm0_regnum
+= tdep
->num_ymm_regs
;
7846 tdep
->ymm0_regnum
= -1;
7848 if (tdep
->num_mmx_regs
!= 0)
7850 /* Support MMX pseudo-register if MMX hasn't been disabled. */
7851 tdep
->mm0_regnum
= mm0_regnum
;
7854 tdep
->mm0_regnum
= -1;
7856 /* Hook in the legacy prologue-based unwinders last (fallback). */
7857 frame_unwind_append_unwinder (gdbarch
, &i386_stack_tramp_frame_unwind
);
7858 frame_unwind_append_unwinder (gdbarch
, &i386_sigtramp_frame_unwind
);
7859 frame_unwind_append_unwinder (gdbarch
, &i386_frame_unwind
);
7861 /* If we have a register mapping, enable the generic core file
7862 support, unless it has already been enabled. */
7863 if (tdep
->gregset_reg_offset
7864 && !gdbarch_regset_from_core_section_p (gdbarch
))
7865 set_gdbarch_regset_from_core_section (gdbarch
,
7866 i386_regset_from_core_section
);
7868 set_gdbarch_skip_permanent_breakpoint (gdbarch
,
7869 i386_skip_permanent_breakpoint
);
7871 set_gdbarch_fast_tracepoint_valid_at (gdbarch
,
7872 i386_fast_tracepoint_valid_at
);
7877 static enum gdb_osabi
7878 i386_coff_osabi_sniffer (bfd
*abfd
)
7880 if (strcmp (bfd_get_target (abfd
), "coff-go32-exe") == 0
7881 || strcmp (bfd_get_target (abfd
), "coff-go32") == 0)
7882 return GDB_OSABI_GO32
;
7884 return GDB_OSABI_UNKNOWN
;
7888 /* Provide a prototype to silence -Wmissing-prototypes. */
7889 void _initialize_i386_tdep (void);
7892 _initialize_i386_tdep (void)
7894 register_gdbarch_init (bfd_arch_i386
, i386_gdbarch_init
);
7896 /* Add the variable that controls the disassembly flavor. */
7897 add_setshow_enum_cmd ("disassembly-flavor", no_class
, valid_flavors
,
7898 &disassembly_flavor
, _("\
7899 Set the disassembly flavor."), _("\
7900 Show the disassembly flavor."), _("\
7901 The valid values are \"att\" and \"intel\", and the default value is \"att\"."),
7903 NULL
, /* FIXME: i18n: */
7904 &setlist
, &showlist
);
7906 /* Add the variable that controls the convention for returning
7908 add_setshow_enum_cmd ("struct-convention", no_class
, valid_conventions
,
7909 &struct_convention
, _("\
7910 Set the convention for returning small structs."), _("\
7911 Show the convention for returning small structs."), _("\
7912 Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\
7915 NULL
, /* FIXME: i18n: */
7916 &setlist
, &showlist
);
7918 gdbarch_register_osabi_sniffer (bfd_arch_i386
, bfd_target_coff_flavour
,
7919 i386_coff_osabi_sniffer
);
7921 gdbarch_register_osabi (bfd_arch_i386
, 0, GDB_OSABI_SVR4
,
7922 i386_svr4_init_abi
);
7923 gdbarch_register_osabi (bfd_arch_i386
, 0, GDB_OSABI_GO32
,
7924 i386_go32_init_abi
);
7926 /* Initialize the i386-specific register groups. */
7927 i386_init_reggroups ();
7929 /* Initialize the standard target descriptions. */
7930 initialize_tdesc_i386 ();
7931 initialize_tdesc_i386_mmx ();
7932 initialize_tdesc_i386_avx ();
7934 /* Tell remote stub that we support XML target description. */
7935 register_remote_support_xml ("i386");