1 /* Intel 386 target-dependent stuff.
3 Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009,
5 2010, 2011 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "opcode/i386.h"
24 #include "arch-utils.h"
26 #include "dummy-frame.h"
27 #include "dwarf2-frame.h"
30 #include "frame-base.h"
31 #include "frame-unwind.h"
39 #include "reggroups.h"
48 #include "exceptions.h"
49 #include "gdb_assert.h"
50 #include "gdb_string.h"
52 #include "i386-tdep.h"
53 #include "i387-tdep.h"
54 #include "i386-xstate.h"
59 #include "features/i386/i386.c"
60 #include "features/i386/i386-avx.c"
61 #include "features/i386/i386-mmx.c"
65 static const char *i386_register_names
[] =
67 "eax", "ecx", "edx", "ebx",
68 "esp", "ebp", "esi", "edi",
69 "eip", "eflags", "cs", "ss",
70 "ds", "es", "fs", "gs",
71 "st0", "st1", "st2", "st3",
72 "st4", "st5", "st6", "st7",
73 "fctrl", "fstat", "ftag", "fiseg",
74 "fioff", "foseg", "fooff", "fop",
75 "xmm0", "xmm1", "xmm2", "xmm3",
76 "xmm4", "xmm5", "xmm6", "xmm7",
80 static const char *i386_ymm_names
[] =
82 "ymm0", "ymm1", "ymm2", "ymm3",
83 "ymm4", "ymm5", "ymm6", "ymm7",
86 static const char *i386_ymmh_names
[] =
88 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
89 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
92 /* Register names for MMX pseudo-registers. */
94 static const char *i386_mmx_names
[] =
96 "mm0", "mm1", "mm2", "mm3",
97 "mm4", "mm5", "mm6", "mm7"
100 /* Register names for byte pseudo-registers. */
102 static const char *i386_byte_names
[] =
104 "al", "cl", "dl", "bl",
105 "ah", "ch", "dh", "bh"
108 /* Register names for word pseudo-registers. */
110 static const char *i386_word_names
[] =
112 "ax", "cx", "dx", "bx",
119 i386_mmx_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
121 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
122 int mm0_regnum
= tdep
->mm0_regnum
;
127 regnum
-= mm0_regnum
;
128 return regnum
>= 0 && regnum
< tdep
->num_mmx_regs
;
134 i386_byte_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
136 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
138 regnum
-= tdep
->al_regnum
;
139 return regnum
>= 0 && regnum
< tdep
->num_byte_regs
;
145 i386_word_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
147 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
149 regnum
-= tdep
->ax_regnum
;
150 return regnum
>= 0 && regnum
< tdep
->num_word_regs
;
153 /* Dword register? */
156 i386_dword_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
158 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
159 int eax_regnum
= tdep
->eax_regnum
;
164 regnum
-= eax_regnum
;
165 return regnum
>= 0 && regnum
< tdep
->num_dword_regs
;
169 i386_ymmh_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
171 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
172 int ymm0h_regnum
= tdep
->ymm0h_regnum
;
174 if (ymm0h_regnum
< 0)
177 regnum
-= ymm0h_regnum
;
178 return regnum
>= 0 && regnum
< tdep
->num_ymm_regs
;
184 i386_ymm_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
186 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
187 int ymm0_regnum
= tdep
->ymm0_regnum
;
192 regnum
-= ymm0_regnum
;
193 return regnum
>= 0 && regnum
< tdep
->num_ymm_regs
;
199 i386_xmm_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
201 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
202 int num_xmm_regs
= I387_NUM_XMM_REGS (tdep
);
204 if (num_xmm_regs
== 0)
207 regnum
-= I387_XMM0_REGNUM (tdep
);
208 return regnum
>= 0 && regnum
< num_xmm_regs
;
212 i386_mxcsr_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
214 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
216 if (I387_NUM_XMM_REGS (tdep
) == 0)
219 return (regnum
== I387_MXCSR_REGNUM (tdep
));
225 i386_fp_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
227 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
229 if (I387_ST0_REGNUM (tdep
) < 0)
232 return (I387_ST0_REGNUM (tdep
) <= regnum
233 && regnum
< I387_FCTRL_REGNUM (tdep
));
237 i386_fpc_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
239 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
241 if (I387_ST0_REGNUM (tdep
) < 0)
244 return (I387_FCTRL_REGNUM (tdep
) <= regnum
245 && regnum
< I387_XMM0_REGNUM (tdep
));
248 /* Return the name of register REGNUM, or the empty string if it is
249 an anonymous register. */
252 i386_register_name (struct gdbarch
*gdbarch
, int regnum
)
254 /* Hide the upper YMM registers. */
255 if (i386_ymmh_regnum_p (gdbarch
, regnum
))
258 return tdesc_register_name (gdbarch
, regnum
);
261 /* Return the name of register REGNUM. */
264 i386_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
266 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
267 if (i386_mmx_regnum_p (gdbarch
, regnum
))
268 return i386_mmx_names
[regnum
- I387_MM0_REGNUM (tdep
)];
269 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
270 return i386_ymm_names
[regnum
- tdep
->ymm0_regnum
];
271 else if (i386_byte_regnum_p (gdbarch
, regnum
))
272 return i386_byte_names
[regnum
- tdep
->al_regnum
];
273 else if (i386_word_regnum_p (gdbarch
, regnum
))
274 return i386_word_names
[regnum
- tdep
->ax_regnum
];
276 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
279 /* Convert a dbx register number REG to the appropriate register
280 number used by GDB. */
283 i386_dbx_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
285 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
287 /* This implements what GCC calls the "default" register map
288 (dbx_register_map[]). */
290 if (reg
>= 0 && reg
<= 7)
292 /* General-purpose registers. The debug info calls %ebp
293 register 4, and %esp register 5. */
300 else if (reg
>= 12 && reg
<= 19)
302 /* Floating-point registers. */
303 return reg
- 12 + I387_ST0_REGNUM (tdep
);
305 else if (reg
>= 21 && reg
<= 28)
308 int ymm0_regnum
= tdep
->ymm0_regnum
;
311 && i386_xmm_regnum_p (gdbarch
, reg
))
312 return reg
- 21 + ymm0_regnum
;
314 return reg
- 21 + I387_XMM0_REGNUM (tdep
);
316 else if (reg
>= 29 && reg
<= 36)
319 return reg
- 29 + I387_MM0_REGNUM (tdep
);
322 /* This will hopefully provoke a warning. */
323 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
326 /* Convert SVR4 register number REG to the appropriate register number
330 i386_svr4_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
332 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
334 /* This implements the GCC register map that tries to be compatible
335 with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */
337 /* The SVR4 register numbering includes %eip and %eflags, and
338 numbers the floating point registers differently. */
339 if (reg
>= 0 && reg
<= 9)
341 /* General-purpose registers. */
344 else if (reg
>= 11 && reg
<= 18)
346 /* Floating-point registers. */
347 return reg
- 11 + I387_ST0_REGNUM (tdep
);
349 else if (reg
>= 21 && reg
<= 36)
351 /* The SSE and MMX registers have the same numbers as with dbx. */
352 return i386_dbx_reg_to_regnum (gdbarch
, reg
);
357 case 37: return I387_FCTRL_REGNUM (tdep
);
358 case 38: return I387_FSTAT_REGNUM (tdep
);
359 case 39: return I387_MXCSR_REGNUM (tdep
);
360 case 40: return I386_ES_REGNUM
;
361 case 41: return I386_CS_REGNUM
;
362 case 42: return I386_SS_REGNUM
;
363 case 43: return I386_DS_REGNUM
;
364 case 44: return I386_FS_REGNUM
;
365 case 45: return I386_GS_REGNUM
;
368 /* This will hopefully provoke a warning. */
369 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
374 /* This is the variable that is set with "set disassembly-flavor", and
375 its legitimate values. */
376 static const char att_flavor
[] = "att";
377 static const char intel_flavor
[] = "intel";
378 static const char *valid_flavors
[] =
384 static const char *disassembly_flavor
= att_flavor
;
387 /* Use the program counter to determine the contents and size of a
388 breakpoint instruction. Return a pointer to a string of bytes that
389 encode a breakpoint instruction, store the length of the string in
390 *LEN and optionally adjust *PC to point to the correct memory
391 location for inserting the breakpoint.
393 On the i386 we have a single breakpoint that fits in a single byte
394 and can be inserted anywhere.
396 This function is 64-bit safe. */
398 static const gdb_byte
*
399 i386_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pc
, int *len
)
401 static gdb_byte break_insn
[] = { 0xcc }; /* int 3 */
403 *len
= sizeof (break_insn
);
407 /* Displaced instruction handling. */
409 /* Skip the legacy instruction prefixes in INSN.
410 Not all prefixes are valid for any particular insn
411 but we needn't care, the insn will fault if it's invalid.
412 The result is a pointer to the first opcode byte,
413 or NULL if we run off the end of the buffer. */
416 i386_skip_prefixes (gdb_byte
*insn
, size_t max_len
)
418 gdb_byte
*end
= insn
+ max_len
;
424 case DATA_PREFIX_OPCODE
:
425 case ADDR_PREFIX_OPCODE
:
426 case CS_PREFIX_OPCODE
:
427 case DS_PREFIX_OPCODE
:
428 case ES_PREFIX_OPCODE
:
429 case FS_PREFIX_OPCODE
:
430 case GS_PREFIX_OPCODE
:
431 case SS_PREFIX_OPCODE
:
432 case LOCK_PREFIX_OPCODE
:
433 case REPE_PREFIX_OPCODE
:
434 case REPNE_PREFIX_OPCODE
:
446 i386_absolute_jmp_p (const gdb_byte
*insn
)
448 /* jmp far (absolute address in operand). */
454 /* jump near, absolute indirect (/4). */
455 if ((insn
[1] & 0x38) == 0x20)
458 /* jump far, absolute indirect (/5). */
459 if ((insn
[1] & 0x38) == 0x28)
467 i386_absolute_call_p (const gdb_byte
*insn
)
469 /* call far, absolute. */
475 /* Call near, absolute indirect (/2). */
476 if ((insn
[1] & 0x38) == 0x10)
479 /* Call far, absolute indirect (/3). */
480 if ((insn
[1] & 0x38) == 0x18)
488 i386_ret_p (const gdb_byte
*insn
)
492 case 0xc2: /* ret near, pop N bytes. */
493 case 0xc3: /* ret near */
494 case 0xca: /* ret far, pop N bytes. */
495 case 0xcb: /* ret far */
496 case 0xcf: /* iret */
505 i386_call_p (const gdb_byte
*insn
)
507 if (i386_absolute_call_p (insn
))
510 /* call near, relative. */
517 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
518 length in bytes. Otherwise, return zero. */
521 i386_syscall_p (const gdb_byte
*insn
, int *lengthp
)
532 /* Some kernels may run one past a syscall insn, so we have to cope.
533 Otherwise this is just simple_displaced_step_copy_insn. */
535 struct displaced_step_closure
*
536 i386_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
537 CORE_ADDR from
, CORE_ADDR to
,
538 struct regcache
*regs
)
540 size_t len
= gdbarch_max_insn_length (gdbarch
);
541 gdb_byte
*buf
= xmalloc (len
);
543 read_memory (from
, buf
, len
);
545 /* GDB may get control back after the insn after the syscall.
546 Presumably this is a kernel bug.
547 If this is a syscall, make sure there's a nop afterwards. */
552 insn
= i386_skip_prefixes (buf
, len
);
553 if (insn
!= NULL
&& i386_syscall_p (insn
, &syscall_length
))
554 insn
[syscall_length
] = NOP_OPCODE
;
557 write_memory (to
, buf
, len
);
561 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
562 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
563 displaced_step_dump_bytes (gdb_stdlog
, buf
, len
);
566 return (struct displaced_step_closure
*) buf
;
569 /* Fix up the state of registers and memory after having single-stepped
570 a displaced instruction. */
573 i386_displaced_step_fixup (struct gdbarch
*gdbarch
,
574 struct displaced_step_closure
*closure
,
575 CORE_ADDR from
, CORE_ADDR to
,
576 struct regcache
*regs
)
578 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
580 /* The offset we applied to the instruction's address.
581 This could well be negative (when viewed as a signed 32-bit
582 value), but ULONGEST won't reflect that, so take care when
584 ULONGEST insn_offset
= to
- from
;
586 /* Since we use simple_displaced_step_copy_insn, our closure is a
587 copy of the instruction. */
588 gdb_byte
*insn
= (gdb_byte
*) closure
;
589 /* The start of the insn, needed in case we see some prefixes. */
590 gdb_byte
*insn_start
= insn
;
593 fprintf_unfiltered (gdb_stdlog
,
594 "displaced: fixup (%s, %s), "
595 "insn = 0x%02x 0x%02x ...\n",
596 paddress (gdbarch
, from
), paddress (gdbarch
, to
),
599 /* The list of issues to contend with here is taken from
600 resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20.
601 Yay for Free Software! */
603 /* Relocate the %eip, if necessary. */
605 /* The instruction recognizers we use assume any leading prefixes
606 have been skipped. */
608 /* This is the size of the buffer in closure. */
609 size_t max_insn_len
= gdbarch_max_insn_length (gdbarch
);
610 gdb_byte
*opcode
= i386_skip_prefixes (insn
, max_insn_len
);
611 /* If there are too many prefixes, just ignore the insn.
612 It will fault when run. */
617 /* Except in the case of absolute or indirect jump or call
618 instructions, or a return instruction, the new eip is relative to
619 the displaced instruction; make it relative. Well, signal
620 handler returns don't need relocation either, but we use the
621 value of %eip to recognize those; see below. */
622 if (! i386_absolute_jmp_p (insn
)
623 && ! i386_absolute_call_p (insn
)
624 && ! i386_ret_p (insn
))
629 regcache_cooked_read_unsigned (regs
, I386_EIP_REGNUM
, &orig_eip
);
631 /* A signal trampoline system call changes the %eip, resuming
632 execution of the main program after the signal handler has
633 returned. That makes them like 'return' instructions; we
634 shouldn't relocate %eip.
636 But most system calls don't, and we do need to relocate %eip.
638 Our heuristic for distinguishing these cases: if stepping
639 over the system call instruction left control directly after
640 the instruction, the we relocate --- control almost certainly
641 doesn't belong in the displaced copy. Otherwise, we assume
642 the instruction has put control where it belongs, and leave
643 it unrelocated. Goodness help us if there are PC-relative
645 if (i386_syscall_p (insn
, &insn_len
)
646 && orig_eip
!= to
+ (insn
- insn_start
) + insn_len
647 /* GDB can get control back after the insn after the syscall.
648 Presumably this is a kernel bug.
649 i386_displaced_step_copy_insn ensures its a nop,
650 we add one to the length for it. */
651 && orig_eip
!= to
+ (insn
- insn_start
) + insn_len
+ 1)
654 fprintf_unfiltered (gdb_stdlog
,
655 "displaced: syscall changed %%eip; "
660 ULONGEST eip
= (orig_eip
- insn_offset
) & 0xffffffffUL
;
662 /* If we just stepped over a breakpoint insn, we don't backup
663 the pc on purpose; this is to match behaviour without
666 regcache_cooked_write_unsigned (regs
, I386_EIP_REGNUM
, eip
);
669 fprintf_unfiltered (gdb_stdlog
,
671 "relocated %%eip from %s to %s\n",
672 paddress (gdbarch
, orig_eip
),
673 paddress (gdbarch
, eip
));
677 /* If the instruction was PUSHFL, then the TF bit will be set in the
678 pushed value, and should be cleared. We'll leave this for later,
679 since GDB already messes up the TF flag when stepping over a
682 /* If the instruction was a call, the return address now atop the
683 stack is the address following the copied instruction. We need
684 to make it the address following the original instruction. */
685 if (i386_call_p (insn
))
689 const ULONGEST retaddr_len
= 4;
691 regcache_cooked_read_unsigned (regs
, I386_ESP_REGNUM
, &esp
);
692 retaddr
= read_memory_unsigned_integer (esp
, retaddr_len
, byte_order
);
693 retaddr
= (retaddr
- insn_offset
) & 0xffffffffUL
;
694 write_memory_unsigned_integer (esp
, retaddr_len
, byte_order
, retaddr
);
697 fprintf_unfiltered (gdb_stdlog
,
698 "displaced: relocated return addr at %s to %s\n",
699 paddress (gdbarch
, esp
),
700 paddress (gdbarch
, retaddr
));
705 append_insns (CORE_ADDR
*to
, ULONGEST len
, const gdb_byte
*buf
)
707 target_write_memory (*to
, buf
, len
);
712 i386_relocate_instruction (struct gdbarch
*gdbarch
,
713 CORE_ADDR
*to
, CORE_ADDR oldloc
)
715 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
716 gdb_byte buf
[I386_MAX_INSN_LEN
];
717 int offset
= 0, rel32
, newrel
;
719 gdb_byte
*insn
= buf
;
721 read_memory (oldloc
, buf
, I386_MAX_INSN_LEN
);
723 insn_length
= gdb_buffered_insn_length (gdbarch
, insn
,
724 I386_MAX_INSN_LEN
, oldloc
);
726 /* Get past the prefixes. */
727 insn
= i386_skip_prefixes (insn
, I386_MAX_INSN_LEN
);
729 /* Adjust calls with 32-bit relative addresses as push/jump, with
730 the address pushed being the location where the original call in
731 the user program would return to. */
734 gdb_byte push_buf
[16];
735 unsigned int ret_addr
;
737 /* Where "ret" in the original code will return to. */
738 ret_addr
= oldloc
+ insn_length
;
739 push_buf
[0] = 0x68; /* pushq $... */
740 memcpy (&push_buf
[1], &ret_addr
, 4);
742 append_insns (to
, 5, push_buf
);
744 /* Convert the relative call to a relative jump. */
747 /* Adjust the destination offset. */
748 rel32
= extract_signed_integer (insn
+ 1, 4, byte_order
);
749 newrel
= (oldloc
- *to
) + rel32
;
750 store_signed_integer (insn
+ 1, 4, byte_order
, newrel
);
753 fprintf_unfiltered (gdb_stdlog
,
754 "Adjusted insn rel32=%s at %s to"
756 hex_string (rel32
), paddress (gdbarch
, oldloc
),
757 hex_string (newrel
), paddress (gdbarch
, *to
));
759 /* Write the adjusted jump into its displaced location. */
760 append_insns (to
, 5, insn
);
764 /* Adjust jumps with 32-bit relative addresses. Calls are already
768 /* Adjust conditional jumps. */
769 else if (insn
[0] == 0x0f && (insn
[1] & 0xf0) == 0x80)
774 rel32
= extract_signed_integer (insn
+ offset
, 4, byte_order
);
775 newrel
= (oldloc
- *to
) + rel32
;
776 store_signed_integer (insn
+ offset
, 4, byte_order
, newrel
);
778 fprintf_unfiltered (gdb_stdlog
,
779 "Adjusted insn rel32=%s at %s to"
781 hex_string (rel32
), paddress (gdbarch
, oldloc
),
782 hex_string (newrel
), paddress (gdbarch
, *to
));
785 /* Write the adjusted instructions into their displaced
787 append_insns (to
, insn_length
, buf
);
791 #ifdef I386_REGNO_TO_SYMMETRY
792 #error "The Sequent Symmetry is no longer supported."
795 /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi
796 and %esp "belong" to the calling function. Therefore these
797 registers should be saved if they're going to be modified. */
799 /* The maximum number of saved registers. This should include all
800 registers mentioned above, and %eip. */
801 #define I386_NUM_SAVED_REGS I386_NUM_GREGS
803 struct i386_frame_cache
811 /* Saved registers. */
812 CORE_ADDR saved_regs
[I386_NUM_SAVED_REGS
];
817 /* Stack space reserved for local variables. */
821 /* Allocate and initialize a frame cache. */
823 static struct i386_frame_cache
*
824 i386_alloc_frame_cache (void)
826 struct i386_frame_cache
*cache
;
829 cache
= FRAME_OBSTACK_ZALLOC (struct i386_frame_cache
);
834 cache
->sp_offset
= -4;
837 /* Saved registers. We initialize these to -1 since zero is a valid
838 offset (that's where %ebp is supposed to be stored). */
839 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
840 cache
->saved_regs
[i
] = -1;
842 cache
->saved_sp_reg
= -1;
843 cache
->pc_in_eax
= 0;
845 /* Frameless until proven otherwise. */
851 /* If the instruction at PC is a jump, return the address of its
852 target. Otherwise, return PC. */
855 i386_follow_jump (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
857 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
862 if (target_read_memory (pc
, &op
, 1))
868 op
= read_memory_unsigned_integer (pc
+ 1, 1, byte_order
);
874 /* Relative jump: if data16 == 0, disp32, else disp16. */
877 delta
= read_memory_integer (pc
+ 2, 2, byte_order
);
879 /* Include the size of the jmp instruction (including the
885 delta
= read_memory_integer (pc
+ 1, 4, byte_order
);
887 /* Include the size of the jmp instruction. */
892 /* Relative jump, disp8 (ignore data16). */
893 delta
= read_memory_integer (pc
+ data16
+ 1, 1, byte_order
);
902 /* Check whether PC points at a prologue for a function returning a
903 structure or union. If so, it updates CACHE and returns the
904 address of the first instruction after the code sequence that
905 removes the "hidden" argument from the stack or CURRENT_PC,
906 whichever is smaller. Otherwise, return PC. */
909 i386_analyze_struct_return (CORE_ADDR pc
, CORE_ADDR current_pc
,
910 struct i386_frame_cache
*cache
)
912 /* Functions that return a structure or union start with:
915 xchgl %eax, (%esp) 0x87 0x04 0x24
916 or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00
918 (the System V compiler puts out the second `xchg' instruction,
919 and the assembler doesn't try to optimize it, so the 'sib' form
920 gets generated). This sequence is used to get the address of the
921 return buffer for a function that returns a structure. */
922 static gdb_byte proto1
[3] = { 0x87, 0x04, 0x24 };
923 static gdb_byte proto2
[4] = { 0x87, 0x44, 0x24, 0x00 };
927 if (current_pc
<= pc
)
930 if (target_read_memory (pc
, &op
, 1))
933 if (op
!= 0x58) /* popl %eax */
936 if (target_read_memory (pc
+ 1, buf
, 4))
939 if (memcmp (buf
, proto1
, 3) != 0 && memcmp (buf
, proto2
, 4) != 0)
942 if (current_pc
== pc
)
944 cache
->sp_offset
+= 4;
948 if (current_pc
== pc
+ 1)
950 cache
->pc_in_eax
= 1;
954 if (buf
[1] == proto1
[1])
961 i386_skip_probe (CORE_ADDR pc
)
963 /* A function may start with
977 if (target_read_memory (pc
, &op
, 1))
980 if (op
== 0x68 || op
== 0x6a)
984 /* Skip past the `pushl' instruction; it has either a one-byte or a
985 four-byte operand, depending on the opcode. */
991 /* Read the following 8 bytes, which should be `call _probe' (6
992 bytes) followed by `addl $4,%esp' (2 bytes). */
993 read_memory (pc
+ delta
, buf
, sizeof (buf
));
994 if (buf
[0] == 0xe8 && buf
[6] == 0xc4 && buf
[7] == 0x4)
995 pc
+= delta
+ sizeof (buf
);
1001 /* GCC 4.1 and later, can put code in the prologue to realign the
1002 stack pointer. Check whether PC points to such code, and update
1003 CACHE accordingly. Return the first instruction after the code
1004 sequence or CURRENT_PC, whichever is smaller. If we don't
1005 recognize the code, return PC. */
1008 i386_analyze_stack_align (CORE_ADDR pc
, CORE_ADDR current_pc
,
1009 struct i386_frame_cache
*cache
)
1011 /* There are 2 code sequences to re-align stack before the frame
1014 1. Use a caller-saved saved register:
1020 2. Use a callee-saved saved register:
1027 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
1029 0x83 0xe4 0xf0 andl $-16, %esp
1030 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
1035 int offset
, offset_and
;
1036 static int regnums
[8] = {
1037 I386_EAX_REGNUM
, /* %eax */
1038 I386_ECX_REGNUM
, /* %ecx */
1039 I386_EDX_REGNUM
, /* %edx */
1040 I386_EBX_REGNUM
, /* %ebx */
1041 I386_ESP_REGNUM
, /* %esp */
1042 I386_EBP_REGNUM
, /* %ebp */
1043 I386_ESI_REGNUM
, /* %esi */
1044 I386_EDI_REGNUM
/* %edi */
1047 if (target_read_memory (pc
, buf
, sizeof buf
))
1050 /* Check caller-saved saved register. The first instruction has
1051 to be "leal 4(%esp), %reg". */
1052 if (buf
[0] == 0x8d && buf
[2] == 0x24 && buf
[3] == 0x4)
1054 /* MOD must be binary 10 and R/M must be binary 100. */
1055 if ((buf
[1] & 0xc7) != 0x44)
1058 /* REG has register number. */
1059 reg
= (buf
[1] >> 3) & 7;
1064 /* Check callee-saved saved register. The first instruction
1065 has to be "pushl %reg". */
1066 if ((buf
[0] & 0xf8) != 0x50)
1072 /* The next instruction has to be "leal 8(%esp), %reg". */
1073 if (buf
[1] != 0x8d || buf
[3] != 0x24 || buf
[4] != 0x8)
1076 /* MOD must be binary 10 and R/M must be binary 100. */
1077 if ((buf
[2] & 0xc7) != 0x44)
1080 /* REG has register number. Registers in pushl and leal have to
1082 if (reg
!= ((buf
[2] >> 3) & 7))
1088 /* Rigister can't be %esp nor %ebp. */
1089 if (reg
== 4 || reg
== 5)
1092 /* The next instruction has to be "andl $-XXX, %esp". */
1093 if (buf
[offset
+ 1] != 0xe4
1094 || (buf
[offset
] != 0x81 && buf
[offset
] != 0x83))
1097 offset_and
= offset
;
1098 offset
+= buf
[offset
] == 0x81 ? 6 : 3;
1100 /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is
1101 0xfc. REG must be binary 110 and MOD must be binary 01. */
1102 if (buf
[offset
] != 0xff
1103 || buf
[offset
+ 2] != 0xfc
1104 || (buf
[offset
+ 1] & 0xf8) != 0x70)
1107 /* R/M has register. Registers in leal and pushl have to be the
1109 if (reg
!= (buf
[offset
+ 1] & 7))
1112 if (current_pc
> pc
+ offset_and
)
1113 cache
->saved_sp_reg
= regnums
[reg
];
1115 return min (pc
+ offset
+ 3, current_pc
);
1118 /* Maximum instruction length we need to handle. */
1119 #define I386_MAX_MATCHED_INSN_LEN 6
1121 /* Instruction description. */
1125 gdb_byte insn
[I386_MAX_MATCHED_INSN_LEN
];
1126 gdb_byte mask
[I386_MAX_MATCHED_INSN_LEN
];
1129 /* Search for the instruction at PC in the list SKIP_INSNS. Return
1130 the first instruction description that matches. Otherwise, return
1133 static struct i386_insn
*
1134 i386_match_insn (CORE_ADDR pc
, struct i386_insn
*skip_insns
)
1136 struct i386_insn
*insn
;
1139 if (target_read_memory (pc
, &op
, 1))
1142 for (insn
= skip_insns
; insn
->len
> 0; insn
++)
1144 if ((op
& insn
->mask
[0]) == insn
->insn
[0])
1146 gdb_byte buf
[I386_MAX_MATCHED_INSN_LEN
- 1];
1147 int insn_matched
= 1;
1150 gdb_assert (insn
->len
> 1);
1151 gdb_assert (insn
->len
<= I386_MAX_MATCHED_INSN_LEN
);
1153 if (target_read_memory (pc
+ 1, buf
, insn
->len
- 1))
1156 for (i
= 1; i
< insn
->len
; i
++)
1158 if ((buf
[i
- 1] & insn
->mask
[i
]) != insn
->insn
[i
])
1170 /* Some special instructions that might be migrated by GCC into the
1171 part of the prologue that sets up the new stack frame. Because the
1172 stack frame hasn't been setup yet, no registers have been saved
1173 yet, and only the scratch registers %eax, %ecx and %edx can be
1176 struct i386_insn i386_frame_setup_skip_insns
[] =
1178 /* Check for `movb imm8, r' and `movl imm32, r'.
1180 ??? Should we handle 16-bit operand-sizes here? */
1182 /* `movb imm8, %al' and `movb imm8, %ah' */
1183 /* `movb imm8, %cl' and `movb imm8, %ch' */
1184 { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } },
1185 /* `movb imm8, %dl' and `movb imm8, %dh' */
1186 { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } },
1187 /* `movl imm32, %eax' and `movl imm32, %ecx' */
1188 { 5, { 0xb8 }, { 0xfe } },
1189 /* `movl imm32, %edx' */
1190 { 5, { 0xba }, { 0xff } },
1192 /* Check for `mov imm32, r32'. Note that there is an alternative
1193 encoding for `mov m32, %eax'.
1195 ??? Should we handle SIB adressing here?
1196 ??? Should we handle 16-bit operand-sizes here? */
1198 /* `movl m32, %eax' */
1199 { 5, { 0xa1 }, { 0xff } },
1200 /* `movl m32, %eax' and `mov; m32, %ecx' */
1201 { 6, { 0x89, 0x05 }, {0xff, 0xf7 } },
1202 /* `movl m32, %edx' */
1203 { 6, { 0x89, 0x15 }, {0xff, 0xff } },
1205 /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'.
1206 Because of the symmetry, there are actually two ways to encode
1207 these instructions; opcode bytes 0x29 and 0x2b for `subl' and
1208 opcode bytes 0x31 and 0x33 for `xorl'. */
1210 /* `subl %eax, %eax' */
1211 { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } },
1212 /* `subl %ecx, %ecx' */
1213 { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } },
1214 /* `subl %edx, %edx' */
1215 { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } },
1216 /* `xorl %eax, %eax' */
1217 { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } },
1218 /* `xorl %ecx, %ecx' */
1219 { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } },
1220 /* `xorl %edx, %edx' */
1221 { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } },
1226 /* Check whether PC points to a no-op instruction. */
1228 i386_skip_noop (CORE_ADDR pc
)
1233 if (target_read_memory (pc
, &op
, 1))
1239 /* Ignore `nop' instruction. */
1243 if (target_read_memory (pc
, &op
, 1))
1247 /* Ignore no-op instruction `mov %edi, %edi'.
1248 Microsoft system dlls often start with
1249 a `mov %edi,%edi' instruction.
1250 The 5 bytes before the function start are
1251 filled with `nop' instructions.
1252 This pattern can be used for hot-patching:
1253 The `mov %edi, %edi' instruction can be replaced by a
1254 near jump to the location of the 5 `nop' instructions
1255 which can be replaced by a 32-bit jump to anywhere
1256 in the 32-bit address space. */
1258 else if (op
== 0x8b)
1260 if (target_read_memory (pc
+ 1, &op
, 1))
1266 if (target_read_memory (pc
, &op
, 1))
1276 /* Check whether PC points at a code that sets up a new stack frame.
1277 If so, it updates CACHE and returns the address of the first
1278 instruction after the sequence that sets up the frame or LIMIT,
1279 whichever is smaller. If we don't recognize the code, return PC. */
1282 i386_analyze_frame_setup (struct gdbarch
*gdbarch
,
1283 CORE_ADDR pc
, CORE_ADDR limit
,
1284 struct i386_frame_cache
*cache
)
1286 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1287 struct i386_insn
*insn
;
1294 if (target_read_memory (pc
, &op
, 1))
1297 if (op
== 0x55) /* pushl %ebp */
1299 /* Take into account that we've executed the `pushl %ebp' that
1300 starts this instruction sequence. */
1301 cache
->saved_regs
[I386_EBP_REGNUM
] = 0;
1302 cache
->sp_offset
+= 4;
1305 /* If that's all, return now. */
1309 /* Check for some special instructions that might be migrated by
1310 GCC into the prologue and skip them. At this point in the
1311 prologue, code should only touch the scratch registers %eax,
1312 %ecx and %edx, so while the number of posibilities is sheer,
1315 Make sure we only skip these instructions if we later see the
1316 `movl %esp, %ebp' that actually sets up the frame. */
1317 while (pc
+ skip
< limit
)
1319 insn
= i386_match_insn (pc
+ skip
, i386_frame_setup_skip_insns
);
1326 /* If that's all, return now. */
1327 if (limit
<= pc
+ skip
)
1330 if (target_read_memory (pc
+ skip
, &op
, 1))
1333 /* Check for `movl %esp, %ebp' -- can be written in two ways. */
1337 if (read_memory_unsigned_integer (pc
+ skip
+ 1, 1, byte_order
)
1342 if (read_memory_unsigned_integer (pc
+ skip
+ 1, 1, byte_order
)
1350 /* OK, we actually have a frame. We just don't know how large
1351 it is yet. Set its size to zero. We'll adjust it if
1352 necessary. We also now commit to skipping the special
1353 instructions mentioned before. */
1357 /* If that's all, return now. */
1361 /* Check for stack adjustment
1365 NOTE: You can't subtract a 16-bit immediate from a 32-bit
1366 reg, so we don't have to worry about a data16 prefix. */
1367 if (target_read_memory (pc
, &op
, 1))
1371 /* `subl' with 8-bit immediate. */
1372 if (read_memory_unsigned_integer (pc
+ 1, 1, byte_order
) != 0xec)
1373 /* Some instruction starting with 0x83 other than `subl'. */
1376 /* `subl' with signed 8-bit immediate (though it wouldn't
1377 make sense to be negative). */
1378 cache
->locals
= read_memory_integer (pc
+ 2, 1, byte_order
);
1381 else if (op
== 0x81)
1383 /* Maybe it is `subl' with a 32-bit immediate. */
1384 if (read_memory_unsigned_integer (pc
+ 1, 1, byte_order
) != 0xec)
1385 /* Some instruction starting with 0x81 other than `subl'. */
1388 /* It is `subl' with a 32-bit immediate. */
1389 cache
->locals
= read_memory_integer (pc
+ 2, 4, byte_order
);
1394 /* Some instruction other than `subl'. */
1398 else if (op
== 0xc8) /* enter */
1400 cache
->locals
= read_memory_unsigned_integer (pc
+ 1, 2, byte_order
);
1407 /* Check whether PC points at code that saves registers on the stack.
1408 If so, it updates CACHE and returns the address of the first
1409 instruction after the register saves or CURRENT_PC, whichever is
1410 smaller. Otherwise, return PC. */
1413 i386_analyze_register_saves (CORE_ADDR pc
, CORE_ADDR current_pc
,
1414 struct i386_frame_cache
*cache
)
1416 CORE_ADDR offset
= 0;
1420 if (cache
->locals
> 0)
1421 offset
-= cache
->locals
;
1422 for (i
= 0; i
< 8 && pc
< current_pc
; i
++)
1424 if (target_read_memory (pc
, &op
, 1))
1426 if (op
< 0x50 || op
> 0x57)
1430 cache
->saved_regs
[op
- 0x50] = offset
;
1431 cache
->sp_offset
+= 4;
1438 /* Do a full analysis of the prologue at PC and update CACHE
1439 accordingly. Bail out early if CURRENT_PC is reached. Return the
1440 address where the analysis stopped.
1442 We handle these cases:
1444 The startup sequence can be at the start of the function, or the
1445 function can start with a branch to startup code at the end.
1447 %ebp can be set up with either the 'enter' instruction, or "pushl
1448 %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was
1449 once used in the System V compiler).
1451 Local space is allocated just below the saved %ebp by either the
1452 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a
1453 16-bit unsigned argument for space to allocate, and the 'addl'
1454 instruction could have either a signed byte, or 32-bit immediate.
1456 Next, the registers used by this function are pushed. With the
1457 System V compiler they will always be in the order: %edi, %esi,
1458 %ebx (and sometimes a harmless bug causes it to also save but not
1459 restore %eax); however, the code below is willing to see the pushes
1460 in any order, and will handle up to 8 of them.
1462 If the setup sequence is at the end of the function, then the next
1463 instruction will be a branch back to the start. */
1466 i386_analyze_prologue (struct gdbarch
*gdbarch
,
1467 CORE_ADDR pc
, CORE_ADDR current_pc
,
1468 struct i386_frame_cache
*cache
)
1470 pc
= i386_skip_noop (pc
);
1471 pc
= i386_follow_jump (gdbarch
, pc
);
1472 pc
= i386_analyze_struct_return (pc
, current_pc
, cache
);
1473 pc
= i386_skip_probe (pc
);
1474 pc
= i386_analyze_stack_align (pc
, current_pc
, cache
);
1475 pc
= i386_analyze_frame_setup (gdbarch
, pc
, current_pc
, cache
);
1476 return i386_analyze_register_saves (pc
, current_pc
, cache
);
1479 /* Return PC of first real instruction. */
1482 i386_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
1484 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1486 static gdb_byte pic_pat
[6] =
1488 0xe8, 0, 0, 0, 0, /* call 0x0 */
1489 0x5b, /* popl %ebx */
1491 struct i386_frame_cache cache
;
1497 pc
= i386_analyze_prologue (gdbarch
, start_pc
, 0xffffffff, &cache
);
1498 if (cache
.locals
< 0)
1501 /* Found valid frame setup. */
1503 /* The native cc on SVR4 in -K PIC mode inserts the following code
1504 to get the address of the global offset table (GOT) into register
1509 movl %ebx,x(%ebp) (optional)
1512 This code is with the rest of the prologue (at the end of the
1513 function), so we have to skip it to get to the first real
1514 instruction at the start of the function. */
1516 for (i
= 0; i
< 6; i
++)
1518 if (target_read_memory (pc
+ i
, &op
, 1))
1521 if (pic_pat
[i
] != op
)
1528 if (target_read_memory (pc
+ delta
, &op
, 1))
1531 if (op
== 0x89) /* movl %ebx, x(%ebp) */
1533 op
= read_memory_unsigned_integer (pc
+ delta
+ 1, 1, byte_order
);
1535 if (op
== 0x5d) /* One byte offset from %ebp. */
1537 else if (op
== 0x9d) /* Four byte offset from %ebp. */
1539 else /* Unexpected instruction. */
1542 if (target_read_memory (pc
+ delta
, &op
, 1))
1547 if (delta
> 0 && op
== 0x81
1548 && read_memory_unsigned_integer (pc
+ delta
+ 1, 1, byte_order
)
1555 /* If the function starts with a branch (to startup code at the end)
1556 the last instruction should bring us back to the first
1557 instruction of the real code. */
1558 if (i386_follow_jump (gdbarch
, start_pc
) != start_pc
)
1559 pc
= i386_follow_jump (gdbarch
, pc
);
1564 /* Check that the code pointed to by PC corresponds to a call to
1565 __main, skip it if so. Return PC otherwise. */
1568 i386_skip_main_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1570 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1573 if (target_read_memory (pc
, &op
, 1))
1579 if (target_read_memory (pc
+ 1, buf
, sizeof buf
) == 0)
1581 /* Make sure address is computed correctly as a 32bit
1582 integer even if CORE_ADDR is 64 bit wide. */
1583 struct minimal_symbol
*s
;
1584 CORE_ADDR call_dest
;
1586 call_dest
= pc
+ 5 + extract_signed_integer (buf
, 4, byte_order
);
1587 call_dest
= call_dest
& 0xffffffffU
;
1588 s
= lookup_minimal_symbol_by_pc (call_dest
);
1590 && SYMBOL_LINKAGE_NAME (s
) != NULL
1591 && strcmp (SYMBOL_LINKAGE_NAME (s
), "__main") == 0)
1599 /* This function is 64-bit safe. */
1602 i386_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1606 frame_unwind_register (next_frame
, gdbarch_pc_regnum (gdbarch
), buf
);
1607 return extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
1611 /* Normal frames. */
1614 i386_frame_cache_1 (struct frame_info
*this_frame
,
1615 struct i386_frame_cache
*cache
)
1617 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1618 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1622 cache
->pc
= get_frame_func (this_frame
);
1624 /* In principle, for normal frames, %ebp holds the frame pointer,
1625 which holds the base address for the current stack frame.
1626 However, for functions that don't need it, the frame pointer is
1627 optional. For these "frameless" functions the frame pointer is
1628 actually the frame pointer of the calling frame. Signal
1629 trampolines are just a special case of a "frameless" function.
1630 They (usually) share their frame pointer with the frame that was
1631 in progress when the signal occurred. */
1633 get_frame_register (this_frame
, I386_EBP_REGNUM
, buf
);
1634 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
);
1635 if (cache
->base
== 0)
1638 /* For normal frames, %eip is stored at 4(%ebp). */
1639 cache
->saved_regs
[I386_EIP_REGNUM
] = 4;
1642 i386_analyze_prologue (gdbarch
, cache
->pc
, get_frame_pc (this_frame
),
1645 if (cache
->locals
< 0)
1647 /* We didn't find a valid frame, which means that CACHE->base
1648 currently holds the frame pointer for our calling frame. If
1649 we're at the start of a function, or somewhere half-way its
1650 prologue, the function's frame probably hasn't been fully
1651 setup yet. Try to reconstruct the base address for the stack
1652 frame by looking at the stack pointer. For truly "frameless"
1653 functions this might work too. */
1655 if (cache
->saved_sp_reg
!= -1)
1657 /* Saved stack pointer has been saved. */
1658 get_frame_register (this_frame
, cache
->saved_sp_reg
, buf
);
1659 cache
->saved_sp
= extract_unsigned_integer (buf
, 4, byte_order
);
1661 /* We're halfway aligning the stack. */
1662 cache
->base
= ((cache
->saved_sp
- 4) & 0xfffffff0) - 4;
1663 cache
->saved_regs
[I386_EIP_REGNUM
] = cache
->saved_sp
- 4;
1665 /* This will be added back below. */
1666 cache
->saved_regs
[I386_EIP_REGNUM
] -= cache
->base
;
1668 else if (cache
->pc
!= 0
1669 || target_read_memory (get_frame_pc (this_frame
), buf
, 1))
1671 /* We're in a known function, but did not find a frame
1672 setup. Assume that the function does not use %ebp.
1673 Alternatively, we may have jumped to an invalid
1674 address; in that case there is definitely no new
1676 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
1677 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
)
1681 /* We're in an unknown function. We could not find the start
1682 of the function to analyze the prologue; our best option is
1683 to assume a typical frame layout with the caller's %ebp
1685 cache
->saved_regs
[I386_EBP_REGNUM
] = 0;
1688 if (cache
->saved_sp_reg
!= -1)
1690 /* Saved stack pointer has been saved (but the SAVED_SP_REG
1691 register may be unavailable). */
1692 if (cache
->saved_sp
== 0
1693 && frame_register_read (this_frame
, cache
->saved_sp_reg
, buf
))
1694 cache
->saved_sp
= extract_unsigned_integer (buf
, 4, byte_order
);
1696 /* Now that we have the base address for the stack frame we can
1697 calculate the value of %esp in the calling frame. */
1698 else if (cache
->saved_sp
== 0)
1699 cache
->saved_sp
= cache
->base
+ 8;
1701 /* Adjust all the saved registers such that they contain addresses
1702 instead of offsets. */
1703 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
1704 if (cache
->saved_regs
[i
] != -1)
1705 cache
->saved_regs
[i
] += cache
->base
;
1710 static struct i386_frame_cache
*
1711 i386_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1713 volatile struct gdb_exception ex
;
1714 struct i386_frame_cache
*cache
;
1719 cache
= i386_alloc_frame_cache ();
1720 *this_cache
= cache
;
1722 TRY_CATCH (ex
, RETURN_MASK_ERROR
)
1724 i386_frame_cache_1 (this_frame
, cache
);
1726 if (ex
.reason
< 0 && ex
.error
!= NOT_AVAILABLE_ERROR
)
1727 throw_exception (ex
);
1733 i386_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
1734 struct frame_id
*this_id
)
1736 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1738 /* This marks the outermost frame. */
1739 if (cache
->base
== 0)
1742 /* See the end of i386_push_dummy_call. */
1743 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
1746 static enum unwind_stop_reason
1747 i386_frame_unwind_stop_reason (struct frame_info
*this_frame
,
1750 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1753 return UNWIND_UNAVAILABLE
;
1755 /* This marks the outermost frame. */
1756 if (cache
->base
== 0)
1757 return UNWIND_OUTERMOST
;
1759 return UNWIND_NO_REASON
;
1762 static struct value
*
1763 i386_frame_prev_register (struct frame_info
*this_frame
, void **this_cache
,
1766 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1768 gdb_assert (regnum
>= 0);
1770 /* The System V ABI says that:
1772 "The flags register contains the system flags, such as the
1773 direction flag and the carry flag. The direction flag must be
1774 set to the forward (that is, zero) direction before entry and
1775 upon exit from a function. Other user flags have no specified
1776 role in the standard calling sequence and are not preserved."
1778 To guarantee the "upon exit" part of that statement we fake a
1779 saved flags register that has its direction flag cleared.
1781 Note that GCC doesn't seem to rely on the fact that the direction
1782 flag is cleared after a function return; it always explicitly
1783 clears the flag before operations where it matters.
1785 FIXME: kettenis/20030316: I'm not quite sure whether this is the
1786 right thing to do. The way we fake the flags register here makes
1787 it impossible to change it. */
1789 if (regnum
== I386_EFLAGS_REGNUM
)
1793 val
= get_frame_register_unsigned (this_frame
, regnum
);
1795 return frame_unwind_got_constant (this_frame
, regnum
, val
);
1798 if (regnum
== I386_EIP_REGNUM
&& cache
->pc_in_eax
)
1799 return frame_unwind_got_register (this_frame
, regnum
, I386_EAX_REGNUM
);
1801 if (regnum
== I386_ESP_REGNUM
1802 && (cache
->saved_sp
!= 0 || cache
->saved_sp_reg
!= -1))
1804 /* If the SP has been saved, but we don't know where, then this
1805 means that SAVED_SP_REG register was found unavailable back
1806 when we built the cache. */
1807 if (cache
->saved_sp
== 0)
1808 return frame_unwind_got_register (this_frame
, regnum
,
1809 cache
->saved_sp_reg
);
1811 return frame_unwind_got_constant (this_frame
, regnum
,
1815 if (regnum
< I386_NUM_SAVED_REGS
&& cache
->saved_regs
[regnum
] != -1)
1816 return frame_unwind_got_memory (this_frame
, regnum
,
1817 cache
->saved_regs
[regnum
]);
1819 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
1822 static const struct frame_unwind i386_frame_unwind
=
1825 i386_frame_unwind_stop_reason
,
1827 i386_frame_prev_register
,
1829 default_frame_sniffer
1832 /* Normal frames, but in a function epilogue. */
1834 /* The epilogue is defined here as the 'ret' instruction, which will
1835 follow any instruction such as 'leave' or 'pop %ebp' that destroys
1836 the function's stack frame. */
1839 i386_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1843 if (target_read_memory (pc
, &insn
, 1))
1844 return 0; /* Can't read memory at pc. */
1846 if (insn
!= 0xc3) /* 'ret' instruction. */
1853 i386_epilogue_frame_sniffer (const struct frame_unwind
*self
,
1854 struct frame_info
*this_frame
,
1855 void **this_prologue_cache
)
1857 if (frame_relative_level (this_frame
) == 0)
1858 return i386_in_function_epilogue_p (get_frame_arch (this_frame
),
1859 get_frame_pc (this_frame
));
1864 static struct i386_frame_cache
*
1865 i386_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1867 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1868 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1869 volatile struct gdb_exception ex
;
1870 struct i386_frame_cache
*cache
;
1876 cache
= i386_alloc_frame_cache ();
1877 *this_cache
= cache
;
1879 TRY_CATCH (ex
, RETURN_MASK_ERROR
)
1881 /* Cache base will be %esp plus cache->sp_offset (-4). */
1882 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
1883 cache
->base
= extract_unsigned_integer (buf
, 4,
1884 byte_order
) + cache
->sp_offset
;
1886 /* Cache pc will be the frame func. */
1887 cache
->pc
= get_frame_pc (this_frame
);
1889 /* The saved %esp will be at cache->base plus 8. */
1890 cache
->saved_sp
= cache
->base
+ 8;
1892 /* The saved %eip will be at cache->base plus 4. */
1893 cache
->saved_regs
[I386_EIP_REGNUM
] = cache
->base
+ 4;
1897 if (ex
.reason
< 0 && ex
.error
!= NOT_AVAILABLE_ERROR
)
1898 throw_exception (ex
);
1903 static enum unwind_stop_reason
1904 i386_epilogue_frame_unwind_stop_reason (struct frame_info
*this_frame
,
1907 struct i386_frame_cache
*cache
1908 = i386_epilogue_frame_cache (this_frame
, this_cache
);
1911 return UNWIND_UNAVAILABLE
;
1913 return UNWIND_NO_REASON
;
1917 i386_epilogue_frame_this_id (struct frame_info
*this_frame
,
1919 struct frame_id
*this_id
)
1921 struct i386_frame_cache
*cache
= i386_epilogue_frame_cache (this_frame
,
1927 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
1930 static const struct frame_unwind i386_epilogue_frame_unwind
=
1933 i386_epilogue_frame_unwind_stop_reason
,
1934 i386_epilogue_frame_this_id
,
1935 i386_frame_prev_register
,
1937 i386_epilogue_frame_sniffer
1941 /* Signal trampolines. */
1943 static struct i386_frame_cache
*
1944 i386_sigtramp_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1946 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1947 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1948 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1949 volatile struct gdb_exception ex
;
1950 struct i386_frame_cache
*cache
;
1957 cache
= i386_alloc_frame_cache ();
1959 TRY_CATCH (ex
, RETURN_MASK_ERROR
)
1961 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
1962 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
) - 4;
1964 addr
= tdep
->sigcontext_addr (this_frame
);
1965 if (tdep
->sc_reg_offset
)
1969 gdb_assert (tdep
->sc_num_regs
<= I386_NUM_SAVED_REGS
);
1971 for (i
= 0; i
< tdep
->sc_num_regs
; i
++)
1972 if (tdep
->sc_reg_offset
[i
] != -1)
1973 cache
->saved_regs
[i
] = addr
+ tdep
->sc_reg_offset
[i
];
1977 cache
->saved_regs
[I386_EIP_REGNUM
] = addr
+ tdep
->sc_pc_offset
;
1978 cache
->saved_regs
[I386_ESP_REGNUM
] = addr
+ tdep
->sc_sp_offset
;
1983 if (ex
.reason
< 0 && ex
.error
!= NOT_AVAILABLE_ERROR
)
1984 throw_exception (ex
);
1986 *this_cache
= cache
;
1990 static enum unwind_stop_reason
1991 i386_sigtramp_frame_unwind_stop_reason (struct frame_info
*this_frame
,
1994 struct i386_frame_cache
*cache
=
1995 i386_sigtramp_frame_cache (this_frame
, this_cache
);
1998 return UNWIND_UNAVAILABLE
;
2000 return UNWIND_NO_REASON
;
2004 i386_sigtramp_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2005 struct frame_id
*this_id
)
2007 struct i386_frame_cache
*cache
=
2008 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2013 /* See the end of i386_push_dummy_call. */
2014 (*this_id
) = frame_id_build (cache
->base
+ 8, get_frame_pc (this_frame
));
2017 static struct value
*
2018 i386_sigtramp_frame_prev_register (struct frame_info
*this_frame
,
2019 void **this_cache
, int regnum
)
2021 /* Make sure we've initialized the cache. */
2022 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2024 return i386_frame_prev_register (this_frame
, this_cache
, regnum
);
2028 i386_sigtramp_frame_sniffer (const struct frame_unwind
*self
,
2029 struct frame_info
*this_frame
,
2030 void **this_prologue_cache
)
2032 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (this_frame
));
2034 /* We shouldn't even bother if we don't have a sigcontext_addr
2036 if (tdep
->sigcontext_addr
== NULL
)
2039 if (tdep
->sigtramp_p
!= NULL
)
2041 if (tdep
->sigtramp_p (this_frame
))
2045 if (tdep
->sigtramp_start
!= 0)
2047 CORE_ADDR pc
= get_frame_pc (this_frame
);
2049 gdb_assert (tdep
->sigtramp_end
!= 0);
2050 if (pc
>= tdep
->sigtramp_start
&& pc
< tdep
->sigtramp_end
)
2057 static const struct frame_unwind i386_sigtramp_frame_unwind
=
2060 i386_sigtramp_frame_unwind_stop_reason
,
2061 i386_sigtramp_frame_this_id
,
2062 i386_sigtramp_frame_prev_register
,
2064 i386_sigtramp_frame_sniffer
2069 i386_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
2071 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
2076 static const struct frame_base i386_frame_base
=
2079 i386_frame_base_address
,
2080 i386_frame_base_address
,
2081 i386_frame_base_address
2084 static struct frame_id
2085 i386_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
2089 fp
= get_frame_register_unsigned (this_frame
, I386_EBP_REGNUM
);
2091 /* See the end of i386_push_dummy_call. */
2092 return frame_id_build (fp
+ 8, get_frame_pc (this_frame
));
2096 /* Figure out where the longjmp will land. Slurp the args out of the
2097 stack. We expect the first arg to be a pointer to the jmp_buf
2098 structure from which we extract the address that we will land at.
2099 This address is copied into PC. This routine returns non-zero on
2103 i386_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
2106 CORE_ADDR sp
, jb_addr
;
2107 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2108 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2109 int jb_pc_offset
= gdbarch_tdep (gdbarch
)->jb_pc_offset
;
2111 /* If JB_PC_OFFSET is -1, we have no way to find out where the
2112 longjmp will land. */
2113 if (jb_pc_offset
== -1)
2116 get_frame_register (frame
, I386_ESP_REGNUM
, buf
);
2117 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
2118 if (target_read_memory (sp
+ 4, buf
, 4))
2121 jb_addr
= extract_unsigned_integer (buf
, 4, byte_order
);
2122 if (target_read_memory (jb_addr
+ jb_pc_offset
, buf
, 4))
2125 *pc
= extract_unsigned_integer (buf
, 4, byte_order
);
2130 /* Check whether TYPE must be 16-byte-aligned when passed as a
2131 function argument. 16-byte vectors, _Decimal128 and structures or
2132 unions containing such types must be 16-byte-aligned; other
2133 arguments are 4-byte-aligned. */
2136 i386_16_byte_align_p (struct type
*type
)
2138 type
= check_typedef (type
);
2139 if ((TYPE_CODE (type
) == TYPE_CODE_DECFLOAT
2140 || (TYPE_CODE (type
) == TYPE_CODE_ARRAY
&& TYPE_VECTOR (type
)))
2141 && TYPE_LENGTH (type
) == 16)
2143 if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
2144 return i386_16_byte_align_p (TYPE_TARGET_TYPE (type
));
2145 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
2146 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
2149 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
2151 if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type
, i
)))
2159 i386_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2160 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
2161 struct value
**args
, CORE_ADDR sp
, int struct_return
,
2162 CORE_ADDR struct_addr
)
2164 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2170 /* Determine the total space required for arguments and struct
2171 return address in a first pass (allowing for 16-byte-aligned
2172 arguments), then push arguments in a second pass. */
2174 for (write_pass
= 0; write_pass
< 2; write_pass
++)
2176 int args_space_used
= 0;
2177 int have_16_byte_aligned_arg
= 0;
2183 /* Push value address. */
2184 store_unsigned_integer (buf
, 4, byte_order
, struct_addr
);
2185 write_memory (sp
, buf
, 4);
2186 args_space_used
+= 4;
2192 for (i
= 0; i
< nargs
; i
++)
2194 int len
= TYPE_LENGTH (value_enclosing_type (args
[i
]));
2198 if (i386_16_byte_align_p (value_enclosing_type (args
[i
])))
2199 args_space_used
= align_up (args_space_used
, 16);
2201 write_memory (sp
+ args_space_used
,
2202 value_contents_all (args
[i
]), len
);
2203 /* The System V ABI says that:
2205 "An argument's size is increased, if necessary, to make it a
2206 multiple of [32-bit] words. This may require tail padding,
2207 depending on the size of the argument."
2209 This makes sure the stack stays word-aligned. */
2210 args_space_used
+= align_up (len
, 4);
2214 if (i386_16_byte_align_p (value_enclosing_type (args
[i
])))
2216 args_space
= align_up (args_space
, 16);
2217 have_16_byte_aligned_arg
= 1;
2219 args_space
+= align_up (len
, 4);
2225 if (have_16_byte_aligned_arg
)
2226 args_space
= align_up (args_space
, 16);
2231 /* Store return address. */
2233 store_unsigned_integer (buf
, 4, byte_order
, bp_addr
);
2234 write_memory (sp
, buf
, 4);
2236 /* Finally, update the stack pointer... */
2237 store_unsigned_integer (buf
, 4, byte_order
, sp
);
2238 regcache_cooked_write (regcache
, I386_ESP_REGNUM
, buf
);
2240 /* ...and fake a frame pointer. */
2241 regcache_cooked_write (regcache
, I386_EBP_REGNUM
, buf
);
2243 /* MarkK wrote: This "+ 8" is all over the place:
2244 (i386_frame_this_id, i386_sigtramp_frame_this_id,
2245 i386_dummy_id). It's there, since all frame unwinders for
2246 a given target have to agree (within a certain margin) on the
2247 definition of the stack address of a frame. Otherwise frame id
2248 comparison might not work correctly. Since DWARF2/GCC uses the
2249 stack address *before* the function call as a frame's CFA. On
2250 the i386, when %ebp is used as a frame pointer, the offset
2251 between the contents %ebp and the CFA as defined by GCC. */
2255 /* These registers are used for returning integers (and on some
2256 targets also for returning `struct' and `union' values when their
2257 size and alignment match an integer type). */
2258 #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */
2259 #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */
2261 /* Read, for architecture GDBARCH, a function return value of TYPE
2262 from REGCACHE, and copy that into VALBUF. */
2265 i386_extract_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
2266 struct regcache
*regcache
, gdb_byte
*valbuf
)
2268 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2269 int len
= TYPE_LENGTH (type
);
2270 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
2272 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2274 if (tdep
->st0_regnum
< 0)
2276 warning (_("Cannot find floating-point return value."));
2277 memset (valbuf
, 0, len
);
2281 /* Floating-point return values can be found in %st(0). Convert
2282 its contents to the desired type. This is probably not
2283 exactly how it would happen on the target itself, but it is
2284 the best we can do. */
2285 regcache_raw_read (regcache
, I386_ST0_REGNUM
, buf
);
2286 convert_typed_floating (buf
, i387_ext_type (gdbarch
), valbuf
, type
);
2290 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
2291 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
2293 if (len
<= low_size
)
2295 regcache_raw_read (regcache
, LOW_RETURN_REGNUM
, buf
);
2296 memcpy (valbuf
, buf
, len
);
2298 else if (len
<= (low_size
+ high_size
))
2300 regcache_raw_read (regcache
, LOW_RETURN_REGNUM
, buf
);
2301 memcpy (valbuf
, buf
, low_size
);
2302 regcache_raw_read (regcache
, HIGH_RETURN_REGNUM
, buf
);
2303 memcpy (valbuf
+ low_size
, buf
, len
- low_size
);
2306 internal_error (__FILE__
, __LINE__
,
2307 _("Cannot extract return value of %d bytes long."),
2312 /* Write, for architecture GDBARCH, a function return value of TYPE
2313 from VALBUF into REGCACHE. */
2316 i386_store_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
2317 struct regcache
*regcache
, const gdb_byte
*valbuf
)
2319 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2320 int len
= TYPE_LENGTH (type
);
2322 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2325 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
2327 if (tdep
->st0_regnum
< 0)
2329 warning (_("Cannot set floating-point return value."));
2333 /* Returning floating-point values is a bit tricky. Apart from
2334 storing the return value in %st(0), we have to simulate the
2335 state of the FPU at function return point. */
2337 /* Convert the value found in VALBUF to the extended
2338 floating-point format used by the FPU. This is probably
2339 not exactly how it would happen on the target itself, but
2340 it is the best we can do. */
2341 convert_typed_floating (valbuf
, type
, buf
, i387_ext_type (gdbarch
));
2342 regcache_raw_write (regcache
, I386_ST0_REGNUM
, buf
);
2344 /* Set the top of the floating-point register stack to 7. The
2345 actual value doesn't really matter, but 7 is what a normal
2346 function return would end up with if the program started out
2347 with a freshly initialized FPU. */
2348 regcache_raw_read_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), &fstat
);
2350 regcache_raw_write_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), fstat
);
2352 /* Mark %st(1) through %st(7) as empty. Since we set the top of
2353 the floating-point register stack to 7, the appropriate value
2354 for the tag word is 0x3fff. */
2355 regcache_raw_write_unsigned (regcache
, I387_FTAG_REGNUM (tdep
), 0x3fff);
2359 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
2360 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
2362 if (len
<= low_size
)
2363 regcache_raw_write_part (regcache
, LOW_RETURN_REGNUM
, 0, len
, valbuf
);
2364 else if (len
<= (low_size
+ high_size
))
2366 regcache_raw_write (regcache
, LOW_RETURN_REGNUM
, valbuf
);
2367 regcache_raw_write_part (regcache
, HIGH_RETURN_REGNUM
, 0,
2368 len
- low_size
, valbuf
+ low_size
);
2371 internal_error (__FILE__
, __LINE__
,
2372 _("Cannot store return value of %d bytes long."), len
);
2377 /* This is the variable that is set with "set struct-convention", and
2378 its legitimate values. */
2379 static const char default_struct_convention
[] = "default";
2380 static const char pcc_struct_convention
[] = "pcc";
2381 static const char reg_struct_convention
[] = "reg";
2382 static const char *valid_conventions
[] =
2384 default_struct_convention
,
2385 pcc_struct_convention
,
2386 reg_struct_convention
,
2389 static const char *struct_convention
= default_struct_convention
;
2391 /* Return non-zero if TYPE, which is assumed to be a structure,
2392 a union type, or an array type, should be returned in registers
2393 for architecture GDBARCH. */
2396 i386_reg_struct_return_p (struct gdbarch
*gdbarch
, struct type
*type
)
2398 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2399 enum type_code code
= TYPE_CODE (type
);
2400 int len
= TYPE_LENGTH (type
);
2402 gdb_assert (code
== TYPE_CODE_STRUCT
2403 || code
== TYPE_CODE_UNION
2404 || code
== TYPE_CODE_ARRAY
);
2406 if (struct_convention
== pcc_struct_convention
2407 || (struct_convention
== default_struct_convention
2408 && tdep
->struct_return
== pcc_struct_return
))
2411 /* Structures consisting of a single `float', `double' or 'long
2412 double' member are returned in %st(0). */
2413 if (code
== TYPE_CODE_STRUCT
&& TYPE_NFIELDS (type
) == 1)
2415 type
= check_typedef (TYPE_FIELD_TYPE (type
, 0));
2416 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2417 return (len
== 4 || len
== 8 || len
== 12);
2420 return (len
== 1 || len
== 2 || len
== 4 || len
== 8);
2423 /* Determine, for architecture GDBARCH, how a return value of TYPE
2424 should be returned. If it is supposed to be returned in registers,
2425 and READBUF is non-zero, read the appropriate value from REGCACHE,
2426 and copy it into READBUF. If WRITEBUF is non-zero, write the value
2427 from WRITEBUF into REGCACHE. */
2429 static enum return_value_convention
2430 i386_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
2431 struct type
*type
, struct regcache
*regcache
,
2432 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2434 enum type_code code
= TYPE_CODE (type
);
2436 if (((code
== TYPE_CODE_STRUCT
2437 || code
== TYPE_CODE_UNION
2438 || code
== TYPE_CODE_ARRAY
)
2439 && !i386_reg_struct_return_p (gdbarch
, type
))
2440 /* 128-bit decimal float uses the struct return convention. */
2441 || (code
== TYPE_CODE_DECFLOAT
&& TYPE_LENGTH (type
) == 16))
2443 /* The System V ABI says that:
2445 "A function that returns a structure or union also sets %eax
2446 to the value of the original address of the caller's area
2447 before it returns. Thus when the caller receives control
2448 again, the address of the returned object resides in register
2449 %eax and can be used to access the object."
2451 So the ABI guarantees that we can always find the return
2452 value just after the function has returned. */
2454 /* Note that the ABI doesn't mention functions returning arrays,
2455 which is something possible in certain languages such as Ada.
2456 In this case, the value is returned as if it was wrapped in
2457 a record, so the convention applied to records also applies
2464 regcache_raw_read_unsigned (regcache
, I386_EAX_REGNUM
, &addr
);
2465 read_memory (addr
, readbuf
, TYPE_LENGTH (type
));
2468 return RETURN_VALUE_ABI_RETURNS_ADDRESS
;
2471 /* This special case is for structures consisting of a single
2472 `float', `double' or 'long double' member. These structures are
2473 returned in %st(0). For these structures, we call ourselves
2474 recursively, changing TYPE into the type of the first member of
2475 the structure. Since that should work for all structures that
2476 have only one member, we don't bother to check the member's type
2478 if (code
== TYPE_CODE_STRUCT
&& TYPE_NFIELDS (type
) == 1)
2480 type
= check_typedef (TYPE_FIELD_TYPE (type
, 0));
2481 return i386_return_value (gdbarch
, func_type
, type
, regcache
,
2486 i386_extract_return_value (gdbarch
, type
, regcache
, readbuf
);
2488 i386_store_return_value (gdbarch
, type
, regcache
, writebuf
);
2490 return RETURN_VALUE_REGISTER_CONVENTION
;
2495 i387_ext_type (struct gdbarch
*gdbarch
)
2497 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2499 if (!tdep
->i387_ext_type
)
2501 tdep
->i387_ext_type
= tdesc_find_type (gdbarch
, "i387_ext");
2502 gdb_assert (tdep
->i387_ext_type
!= NULL
);
2505 return tdep
->i387_ext_type
;
2508 /* Construct vector type for pseudo YMM registers. We can't use
2509 tdesc_find_type since YMM isn't described in target description. */
2511 static struct type
*
2512 i386_ymm_type (struct gdbarch
*gdbarch
)
2514 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2516 if (!tdep
->i386_ymm_type
)
2518 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2520 /* The type we're building is this: */
2522 union __gdb_builtin_type_vec256i
2524 int128_t uint128
[2];
2525 int64_t v2_int64
[4];
2526 int32_t v4_int32
[8];
2527 int16_t v8_int16
[16];
2528 int8_t v16_int8
[32];
2529 double v2_double
[4];
2536 t
= arch_composite_type (gdbarch
,
2537 "__gdb_builtin_type_vec256i", TYPE_CODE_UNION
);
2538 append_composite_type_field (t
, "v8_float",
2539 init_vector_type (bt
->builtin_float
, 8));
2540 append_composite_type_field (t
, "v4_double",
2541 init_vector_type (bt
->builtin_double
, 4));
2542 append_composite_type_field (t
, "v32_int8",
2543 init_vector_type (bt
->builtin_int8
, 32));
2544 append_composite_type_field (t
, "v16_int16",
2545 init_vector_type (bt
->builtin_int16
, 16));
2546 append_composite_type_field (t
, "v8_int32",
2547 init_vector_type (bt
->builtin_int32
, 8));
2548 append_composite_type_field (t
, "v4_int64",
2549 init_vector_type (bt
->builtin_int64
, 4));
2550 append_composite_type_field (t
, "v2_int128",
2551 init_vector_type (bt
->builtin_int128
, 2));
2553 TYPE_VECTOR (t
) = 1;
2554 TYPE_NAME (t
) = "builtin_type_vec256i";
2555 tdep
->i386_ymm_type
= t
;
2558 return tdep
->i386_ymm_type
;
2561 /* Construct vector type for MMX registers. */
2562 static struct type
*
2563 i386_mmx_type (struct gdbarch
*gdbarch
)
2565 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2567 if (!tdep
->i386_mmx_type
)
2569 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2571 /* The type we're building is this: */
2573 union __gdb_builtin_type_vec64i
2576 int32_t v2_int32
[2];
2577 int16_t v4_int16
[4];
2584 t
= arch_composite_type (gdbarch
,
2585 "__gdb_builtin_type_vec64i", TYPE_CODE_UNION
);
2587 append_composite_type_field (t
, "uint64", bt
->builtin_int64
);
2588 append_composite_type_field (t
, "v2_int32",
2589 init_vector_type (bt
->builtin_int32
, 2));
2590 append_composite_type_field (t
, "v4_int16",
2591 init_vector_type (bt
->builtin_int16
, 4));
2592 append_composite_type_field (t
, "v8_int8",
2593 init_vector_type (bt
->builtin_int8
, 8));
2595 TYPE_VECTOR (t
) = 1;
2596 TYPE_NAME (t
) = "builtin_type_vec64i";
2597 tdep
->i386_mmx_type
= t
;
2600 return tdep
->i386_mmx_type
;
2603 /* Return the GDB type object for the "standard" data type of data in
2606 static struct type
*
2607 i386_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
2609 if (i386_mmx_regnum_p (gdbarch
, regnum
))
2610 return i386_mmx_type (gdbarch
);
2611 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
2612 return i386_ymm_type (gdbarch
);
2615 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2616 if (i386_byte_regnum_p (gdbarch
, regnum
))
2617 return bt
->builtin_int8
;
2618 else if (i386_word_regnum_p (gdbarch
, regnum
))
2619 return bt
->builtin_int16
;
2620 else if (i386_dword_regnum_p (gdbarch
, regnum
))
2621 return bt
->builtin_int32
;
2624 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
2627 /* Map a cooked register onto a raw register or memory. For the i386,
2628 the MMX registers need to be mapped onto floating point registers. */
2631 i386_mmx_regnum_to_fp_regnum (struct regcache
*regcache
, int regnum
)
2633 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_regcache_arch (regcache
));
2638 mmxreg
= regnum
- tdep
->mm0_regnum
;
2639 regcache_raw_read_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), &fstat
);
2640 tos
= (fstat
>> 11) & 0x7;
2641 fpreg
= (mmxreg
+ tos
) % 8;
2643 return (I387_ST0_REGNUM (tdep
) + fpreg
);
2646 enum register_status
2647 i386_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2648 int regnum
, gdb_byte
*buf
)
2650 gdb_byte raw_buf
[MAX_REGISTER_SIZE
];
2651 enum register_status status
;
2653 if (i386_mmx_regnum_p (gdbarch
, regnum
))
2655 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
2657 /* Extract (always little endian). */
2658 status
= regcache_raw_read (regcache
, fpnum
, raw_buf
);
2659 if (status
!= REG_VALID
)
2661 memcpy (buf
, raw_buf
, register_size (gdbarch
, regnum
));
2665 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2667 if (i386_ymm_regnum_p (gdbarch
, regnum
))
2669 regnum
-= tdep
->ymm0_regnum
;
2671 /* Extract (always little endian). Read lower 128bits. */
2672 status
= regcache_raw_read (regcache
,
2673 I387_XMM0_REGNUM (tdep
) + regnum
,
2675 if (status
!= REG_VALID
)
2677 memcpy (buf
, raw_buf
, 16);
2678 /* Read upper 128bits. */
2679 status
= regcache_raw_read (regcache
,
2680 tdep
->ymm0h_regnum
+ regnum
,
2682 if (status
!= REG_VALID
)
2684 memcpy (buf
+ 16, raw_buf
, 16);
2686 else if (i386_word_regnum_p (gdbarch
, regnum
))
2688 int gpnum
= regnum
- tdep
->ax_regnum
;
2690 /* Extract (always little endian). */
2691 status
= regcache_raw_read (regcache
, gpnum
, raw_buf
);
2692 if (status
!= REG_VALID
)
2694 memcpy (buf
, raw_buf
, 2);
2696 else if (i386_byte_regnum_p (gdbarch
, regnum
))
2698 /* Check byte pseudo registers last since this function will
2699 be called from amd64_pseudo_register_read, which handles
2700 byte pseudo registers differently. */
2701 int gpnum
= regnum
- tdep
->al_regnum
;
2703 /* Extract (always little endian). We read both lower and
2705 status
= regcache_raw_read (regcache
, gpnum
% 4, raw_buf
);
2706 if (status
!= REG_VALID
)
2709 memcpy (buf
, raw_buf
+ 1, 1);
2711 memcpy (buf
, raw_buf
, 1);
2714 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
2721 i386_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2722 int regnum
, const gdb_byte
*buf
)
2724 gdb_byte raw_buf
[MAX_REGISTER_SIZE
];
2726 if (i386_mmx_regnum_p (gdbarch
, regnum
))
2728 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
2731 regcache_raw_read (regcache
, fpnum
, raw_buf
);
2732 /* ... Modify ... (always little endian). */
2733 memcpy (raw_buf
, buf
, register_size (gdbarch
, regnum
));
2735 regcache_raw_write (regcache
, fpnum
, raw_buf
);
2739 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2741 if (i386_ymm_regnum_p (gdbarch
, regnum
))
2743 regnum
-= tdep
->ymm0_regnum
;
2745 /* ... Write lower 128bits. */
2746 regcache_raw_write (regcache
,
2747 I387_XMM0_REGNUM (tdep
) + regnum
,
2749 /* ... Write upper 128bits. */
2750 regcache_raw_write (regcache
,
2751 tdep
->ymm0h_regnum
+ regnum
,
2754 else if (i386_word_regnum_p (gdbarch
, regnum
))
2756 int gpnum
= regnum
- tdep
->ax_regnum
;
2759 regcache_raw_read (regcache
, gpnum
, raw_buf
);
2760 /* ... Modify ... (always little endian). */
2761 memcpy (raw_buf
, buf
, 2);
2763 regcache_raw_write (regcache
, gpnum
, raw_buf
);
2765 else if (i386_byte_regnum_p (gdbarch
, regnum
))
2767 /* Check byte pseudo registers last since this function will
2768 be called from amd64_pseudo_register_read, which handles
2769 byte pseudo registers differently. */
2770 int gpnum
= regnum
- tdep
->al_regnum
;
2772 /* Read ... We read both lower and upper registers. */
2773 regcache_raw_read (regcache
, gpnum
% 4, raw_buf
);
2774 /* ... Modify ... (always little endian). */
2776 memcpy (raw_buf
+ 1, buf
, 1);
2778 memcpy (raw_buf
, buf
, 1);
2780 regcache_raw_write (regcache
, gpnum
% 4, raw_buf
);
2783 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
2788 /* Return the register number of the register allocated by GCC after
2789 REGNUM, or -1 if there is no such register. */
2792 i386_next_regnum (int regnum
)
2794 /* GCC allocates the registers in the order:
2796 %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ...
2798 Since storing a variable in %esp doesn't make any sense we return
2799 -1 for %ebp and for %esp itself. */
2800 static int next_regnum
[] =
2802 I386_EDX_REGNUM
, /* Slot for %eax. */
2803 I386_EBX_REGNUM
, /* Slot for %ecx. */
2804 I386_ECX_REGNUM
, /* Slot for %edx. */
2805 I386_ESI_REGNUM
, /* Slot for %ebx. */
2806 -1, -1, /* Slots for %esp and %ebp. */
2807 I386_EDI_REGNUM
, /* Slot for %esi. */
2808 I386_EBP_REGNUM
/* Slot for %edi. */
2811 if (regnum
>= 0 && regnum
< sizeof (next_regnum
) / sizeof (next_regnum
[0]))
2812 return next_regnum
[regnum
];
2817 /* Return nonzero if a value of type TYPE stored in register REGNUM
2818 needs any special handling. */
2821 i386_convert_register_p (struct gdbarch
*gdbarch
,
2822 int regnum
, struct type
*type
)
2824 int len
= TYPE_LENGTH (type
);
2826 /* Values may be spread across multiple registers. Most debugging
2827 formats aren't expressive enough to specify the locations, so
2828 some heuristics is involved. Right now we only handle types that
2829 have a length that is a multiple of the word size, since GCC
2830 doesn't seem to put any other types into registers. */
2831 if (len
> 4 && len
% 4 == 0)
2833 int last_regnum
= regnum
;
2837 last_regnum
= i386_next_regnum (last_regnum
);
2841 if (last_regnum
!= -1)
2845 return i387_convert_register_p (gdbarch
, regnum
, type
);
2848 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
2849 return its contents in TO. */
2852 i386_register_to_value (struct frame_info
*frame
, int regnum
,
2853 struct type
*type
, gdb_byte
*to
,
2854 int *optimizedp
, int *unavailablep
)
2856 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2857 int len
= TYPE_LENGTH (type
);
2859 if (i386_fp_regnum_p (gdbarch
, regnum
))
2860 return i387_register_to_value (frame
, regnum
, type
, to
,
2861 optimizedp
, unavailablep
);
2863 /* Read a value spread across multiple registers. */
2865 gdb_assert (len
> 4 && len
% 4 == 0);
2869 gdb_assert (regnum
!= -1);
2870 gdb_assert (register_size (gdbarch
, regnum
) == 4);
2872 if (!get_frame_register_bytes (frame
, regnum
, 0,
2873 register_size (gdbarch
, regnum
),
2874 to
, optimizedp
, unavailablep
))
2877 regnum
= i386_next_regnum (regnum
);
2882 *optimizedp
= *unavailablep
= 0;
2886 /* Write the contents FROM of a value of type TYPE into register
2887 REGNUM in frame FRAME. */
2890 i386_value_to_register (struct frame_info
*frame
, int regnum
,
2891 struct type
*type
, const gdb_byte
*from
)
2893 int len
= TYPE_LENGTH (type
);
2895 if (i386_fp_regnum_p (get_frame_arch (frame
), regnum
))
2897 i387_value_to_register (frame
, regnum
, type
, from
);
2901 /* Write a value spread across multiple registers. */
2903 gdb_assert (len
> 4 && len
% 4 == 0);
2907 gdb_assert (regnum
!= -1);
2908 gdb_assert (register_size (get_frame_arch (frame
), regnum
) == 4);
2910 put_frame_register (frame
, regnum
, from
);
2911 regnum
= i386_next_regnum (regnum
);
2917 /* Supply register REGNUM from the buffer specified by GREGS and LEN
2918 in the general-purpose register set REGSET to register cache
2919 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
2922 i386_supply_gregset (const struct regset
*regset
, struct regcache
*regcache
,
2923 int regnum
, const void *gregs
, size_t len
)
2925 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
2926 const gdb_byte
*regs
= gregs
;
2929 gdb_assert (len
== tdep
->sizeof_gregset
);
2931 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
2933 if ((regnum
== i
|| regnum
== -1)
2934 && tdep
->gregset_reg_offset
[i
] != -1)
2935 regcache_raw_supply (regcache
, i
, regs
+ tdep
->gregset_reg_offset
[i
]);
2939 /* Collect register REGNUM from the register cache REGCACHE and store
2940 it in the buffer specified by GREGS and LEN as described by the
2941 general-purpose register set REGSET. If REGNUM is -1, do this for
2942 all registers in REGSET. */
2945 i386_collect_gregset (const struct regset
*regset
,
2946 const struct regcache
*regcache
,
2947 int regnum
, void *gregs
, size_t len
)
2949 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
2950 gdb_byte
*regs
= gregs
;
2953 gdb_assert (len
== tdep
->sizeof_gregset
);
2955 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
2957 if ((regnum
== i
|| regnum
== -1)
2958 && tdep
->gregset_reg_offset
[i
] != -1)
2959 regcache_raw_collect (regcache
, i
, regs
+ tdep
->gregset_reg_offset
[i
]);
2963 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
2964 in the floating-point register set REGSET to register cache
2965 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
2968 i386_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
2969 int regnum
, const void *fpregs
, size_t len
)
2971 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
2973 if (len
== I387_SIZEOF_FXSAVE
)
2975 i387_supply_fxsave (regcache
, regnum
, fpregs
);
2979 gdb_assert (len
== tdep
->sizeof_fpregset
);
2980 i387_supply_fsave (regcache
, regnum
, fpregs
);
2983 /* Collect register REGNUM from the register cache REGCACHE and store
2984 it in the buffer specified by FPREGS and LEN as described by the
2985 floating-point register set REGSET. If REGNUM is -1, do this for
2986 all registers in REGSET. */
2989 i386_collect_fpregset (const struct regset
*regset
,
2990 const struct regcache
*regcache
,
2991 int regnum
, void *fpregs
, size_t len
)
2993 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
2995 if (len
== I387_SIZEOF_FXSAVE
)
2997 i387_collect_fxsave (regcache
, regnum
, fpregs
);
3001 gdb_assert (len
== tdep
->sizeof_fpregset
);
3002 i387_collect_fsave (regcache
, regnum
, fpregs
);
3005 /* Similar to i386_supply_fpregset, but use XSAVE extended state. */
3008 i386_supply_xstateregset (const struct regset
*regset
,
3009 struct regcache
*regcache
, int regnum
,
3010 const void *xstateregs
, size_t len
)
3012 i387_supply_xsave (regcache
, regnum
, xstateregs
);
3015 /* Similar to i386_collect_fpregset , but use XSAVE extended state. */
3018 i386_collect_xstateregset (const struct regset
*regset
,
3019 const struct regcache
*regcache
,
3020 int regnum
, void *xstateregs
, size_t len
)
3022 i387_collect_xsave (regcache
, regnum
, xstateregs
, 1);
3025 /* Return the appropriate register set for the core section identified
3026 by SECT_NAME and SECT_SIZE. */
3028 const struct regset
*
3029 i386_regset_from_core_section (struct gdbarch
*gdbarch
,
3030 const char *sect_name
, size_t sect_size
)
3032 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3034 if (strcmp (sect_name
, ".reg") == 0 && sect_size
== tdep
->sizeof_gregset
)
3036 if (tdep
->gregset
== NULL
)
3037 tdep
->gregset
= regset_alloc (gdbarch
, i386_supply_gregset
,
3038 i386_collect_gregset
);
3039 return tdep
->gregset
;
3042 if ((strcmp (sect_name
, ".reg2") == 0 && sect_size
== tdep
->sizeof_fpregset
)
3043 || (strcmp (sect_name
, ".reg-xfp") == 0
3044 && sect_size
== I387_SIZEOF_FXSAVE
))
3046 if (tdep
->fpregset
== NULL
)
3047 tdep
->fpregset
= regset_alloc (gdbarch
, i386_supply_fpregset
,
3048 i386_collect_fpregset
);
3049 return tdep
->fpregset
;
3052 if (strcmp (sect_name
, ".reg-xstate") == 0)
3054 if (tdep
->xstateregset
== NULL
)
3055 tdep
->xstateregset
= regset_alloc (gdbarch
,
3056 i386_supply_xstateregset
,
3057 i386_collect_xstateregset
);
3059 return tdep
->xstateregset
;
3066 /* Stuff for WIN32 PE style DLL's but is pretty generic really. */
3069 i386_pe_skip_trampoline_code (struct frame_info
*frame
,
3070 CORE_ADDR pc
, char *name
)
3072 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3073 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3076 if (pc
&& read_memory_unsigned_integer (pc
, 2, byte_order
) == 0x25ff)
3078 unsigned long indirect
=
3079 read_memory_unsigned_integer (pc
+ 2, 4, byte_order
);
3080 struct minimal_symbol
*indsym
=
3081 indirect
? lookup_minimal_symbol_by_pc (indirect
) : 0;
3082 char *symname
= indsym
? SYMBOL_LINKAGE_NAME (indsym
) : 0;
3086 if (strncmp (symname
, "__imp_", 6) == 0
3087 || strncmp (symname
, "_imp_", 5) == 0)
3089 read_memory_unsigned_integer (indirect
, 4, byte_order
);
3092 return 0; /* Not a trampoline. */
3096 /* Return whether the THIS_FRAME corresponds to a sigtramp
3100 i386_sigtramp_p (struct frame_info
*this_frame
)
3102 CORE_ADDR pc
= get_frame_pc (this_frame
);
3105 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
3106 return (name
&& strcmp ("_sigtramp", name
) == 0);
3110 /* We have two flavours of disassembly. The machinery on this page
3111 deals with switching between those. */
3114 i386_print_insn (bfd_vma pc
, struct disassemble_info
*info
)
3116 gdb_assert (disassembly_flavor
== att_flavor
3117 || disassembly_flavor
== intel_flavor
);
3119 /* FIXME: kettenis/20020915: Until disassembler_options is properly
3120 constified, cast to prevent a compiler warning. */
3121 info
->disassembler_options
= (char *) disassembly_flavor
;
3123 return print_insn_i386 (pc
, info
);
3127 /* There are a few i386 architecture variants that differ only
3128 slightly from the generic i386 target. For now, we don't give them
3129 their own source file, but include them here. As a consequence,
3130 they'll always be included. */
3132 /* System V Release 4 (SVR4). */
3134 /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp
3138 i386_svr4_sigtramp_p (struct frame_info
*this_frame
)
3140 CORE_ADDR pc
= get_frame_pc (this_frame
);
3143 /* UnixWare uses _sigacthandler. The origin of the other symbols is
3144 currently unknown. */
3145 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
3146 return (name
&& (strcmp ("_sigreturn", name
) == 0
3147 || strcmp ("_sigacthandler", name
) == 0
3148 || strcmp ("sigvechandler", name
) == 0));
3151 /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the
3152 address of the associated sigcontext (ucontext) structure. */
3155 i386_svr4_sigcontext_addr (struct frame_info
*this_frame
)
3157 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3158 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3162 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
3163 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
3165 return read_memory_unsigned_integer (sp
+ 8, 4, byte_order
);
3172 i386_elf_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
3174 /* We typically use stabs-in-ELF with the SVR4 register numbering. */
3175 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
3178 /* System V Release 4 (SVR4). */
3181 i386_svr4_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
3183 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3185 /* System V Release 4 uses ELF. */
3186 i386_elf_init_abi (info
, gdbarch
);
3188 /* System V Release 4 has shared libraries. */
3189 set_gdbarch_skip_trampoline_code (gdbarch
, find_solib_trampoline_target
);
3191 tdep
->sigtramp_p
= i386_svr4_sigtramp_p
;
3192 tdep
->sigcontext_addr
= i386_svr4_sigcontext_addr
;
3193 tdep
->sc_pc_offset
= 36 + 14 * 4;
3194 tdep
->sc_sp_offset
= 36 + 17 * 4;
3196 tdep
->jb_pc_offset
= 20;
3202 i386_go32_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
3204 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3206 /* DJGPP doesn't have any special frames for signal handlers. */
3207 tdep
->sigtramp_p
= NULL
;
3209 tdep
->jb_pc_offset
= 36;
3211 /* DJGPP does not support the SSE registers. */
3212 if (! tdesc_has_registers (info
.target_desc
))
3213 tdep
->tdesc
= tdesc_i386_mmx
;
3215 /* Native compiler is GCC, which uses the SVR4 register numbering
3216 even in COFF and STABS. See the comment in i386_gdbarch_init,
3217 before the calls to set_gdbarch_stab_reg_to_regnum and
3218 set_gdbarch_sdb_reg_to_regnum. */
3219 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
3220 set_gdbarch_sdb_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
3222 set_gdbarch_has_dos_based_file_system (gdbarch
, 1);
3226 /* i386 register groups. In addition to the normal groups, add "mmx"
3229 static struct reggroup
*i386_sse_reggroup
;
3230 static struct reggroup
*i386_mmx_reggroup
;
3233 i386_init_reggroups (void)
3235 i386_sse_reggroup
= reggroup_new ("sse", USER_REGGROUP
);
3236 i386_mmx_reggroup
= reggroup_new ("mmx", USER_REGGROUP
);
3240 i386_add_reggroups (struct gdbarch
*gdbarch
)
3242 reggroup_add (gdbarch
, i386_sse_reggroup
);
3243 reggroup_add (gdbarch
, i386_mmx_reggroup
);
3244 reggroup_add (gdbarch
, general_reggroup
);
3245 reggroup_add (gdbarch
, float_reggroup
);
3246 reggroup_add (gdbarch
, all_reggroup
);
3247 reggroup_add (gdbarch
, save_reggroup
);
3248 reggroup_add (gdbarch
, restore_reggroup
);
3249 reggroup_add (gdbarch
, vector_reggroup
);
3250 reggroup_add (gdbarch
, system_reggroup
);
3254 i386_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
3255 struct reggroup
*group
)
3257 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3258 int fp_regnum_p
, mmx_regnum_p
, xmm_regnum_p
, mxcsr_regnum_p
,
3259 ymm_regnum_p
, ymmh_regnum_p
;
3261 /* Don't include pseudo registers, except for MMX, in any register
3263 if (i386_byte_regnum_p (gdbarch
, regnum
))
3266 if (i386_word_regnum_p (gdbarch
, regnum
))
3269 if (i386_dword_regnum_p (gdbarch
, regnum
))
3272 mmx_regnum_p
= i386_mmx_regnum_p (gdbarch
, regnum
);
3273 if (group
== i386_mmx_reggroup
)
3274 return mmx_regnum_p
;
3276 xmm_regnum_p
= i386_xmm_regnum_p (gdbarch
, regnum
);
3277 mxcsr_regnum_p
= i386_mxcsr_regnum_p (gdbarch
, regnum
);
3278 if (group
== i386_sse_reggroup
)
3279 return xmm_regnum_p
|| mxcsr_regnum_p
;
3281 ymm_regnum_p
= i386_ymm_regnum_p (gdbarch
, regnum
);
3282 if (group
== vector_reggroup
)
3283 return (mmx_regnum_p
3287 && ((tdep
->xcr0
& I386_XSTATE_AVX_MASK
)
3288 == I386_XSTATE_SSE_MASK
)));
3290 fp_regnum_p
= (i386_fp_regnum_p (gdbarch
, regnum
)
3291 || i386_fpc_regnum_p (gdbarch
, regnum
));
3292 if (group
== float_reggroup
)
3295 /* For "info reg all", don't include upper YMM registers nor XMM
3296 registers when AVX is supported. */
3297 ymmh_regnum_p
= i386_ymmh_regnum_p (gdbarch
, regnum
);
3298 if (group
== all_reggroup
3300 && (tdep
->xcr0
& I386_XSTATE_AVX
))
3304 if (group
== general_reggroup
)
3305 return (!fp_regnum_p
3312 return default_register_reggroup_p (gdbarch
, regnum
, group
);
3316 /* Get the ARGIth function argument for the current function. */
3319 i386_fetch_pointer_argument (struct frame_info
*frame
, int argi
,
3322 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3323 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3324 CORE_ADDR sp
= get_frame_register_unsigned (frame
, I386_ESP_REGNUM
);
3325 return read_memory_unsigned_integer (sp
+ (4 * (argi
+ 1)), 4, byte_order
);
3329 i386_skip_permanent_breakpoint (struct regcache
*regcache
)
3331 CORE_ADDR current_pc
= regcache_read_pc (regcache
);
3333 /* On i386, breakpoint is exactly 1 byte long, so we just
3334 adjust the PC in the regcache. */
3336 regcache_write_pc (regcache
, current_pc
);
3340 #define PREFIX_REPZ 0x01
3341 #define PREFIX_REPNZ 0x02
3342 #define PREFIX_LOCK 0x04
3343 #define PREFIX_DATA 0x08
3344 #define PREFIX_ADDR 0x10
3356 /* i386 arith/logic operations */
3369 struct i386_record_s
3371 struct gdbarch
*gdbarch
;
3372 struct regcache
*regcache
;
3373 CORE_ADDR orig_addr
;
3379 uint8_t mod
, reg
, rm
;
3388 /* Parse "modrm" part in current memory address that irp->addr point to
3389 Return -1 if something wrong. */
3392 i386_record_modrm (struct i386_record_s
*irp
)
3394 struct gdbarch
*gdbarch
= irp
->gdbarch
;
3396 if (target_read_memory (irp
->addr
, &irp
->modrm
, 1))
3399 printf_unfiltered (_("Process record: error reading memory at "
3400 "addr %s len = 1.\n"),
3401 paddress (gdbarch
, irp
->addr
));
3405 irp
->mod
= (irp
->modrm
>> 6) & 3;
3406 irp
->reg
= (irp
->modrm
>> 3) & 7;
3407 irp
->rm
= irp
->modrm
& 7;
3412 /* Get the memory address that current instruction write to and set it to
3413 the argument "addr".
3414 Return -1 if something wrong. */
3417 i386_record_lea_modrm_addr (struct i386_record_s
*irp
, uint64_t *addr
)
3419 struct gdbarch
*gdbarch
= irp
->gdbarch
;
3420 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3432 uint8_t base
= irp
->rm
;
3437 if (target_read_memory (irp
->addr
, &byte
, 1))
3440 printf_unfiltered (_("Process record: error reading memory "
3441 "at addr %s len = 1.\n"),
3442 paddress (gdbarch
, irp
->addr
));
3446 scale
= (byte
>> 6) & 3;
3447 index
= ((byte
>> 3) & 7) | irp
->rex_x
;
3455 if ((base
& 7) == 5)
3458 if (target_read_memory (irp
->addr
, buf
, 4))
3461 printf_unfiltered (_("Process record: error reading "
3462 "memory at addr %s len = 4.\n"),
3463 paddress (gdbarch
, irp
->addr
));
3467 *addr
= extract_signed_integer (buf
, 4, byte_order
);
3468 if (irp
->regmap
[X86_RECORD_R8_REGNUM
] && !havesib
)
3469 *addr
+= irp
->addr
+ irp
->rip_offset
;
3473 if (target_read_memory (irp
->addr
, buf
, 1))
3476 printf_unfiltered (_("Process record: error reading memory "
3477 "at addr %s len = 1.\n"),
3478 paddress (gdbarch
, irp
->addr
));
3482 *addr
= (int8_t) buf
[0];
3485 if (target_read_memory (irp
->addr
, buf
, 4))
3488 printf_unfiltered (_("Process record: error reading memory "
3489 "at addr %s len = 4.\n"),
3490 paddress (gdbarch
, irp
->addr
));
3493 *addr
= extract_signed_integer (buf
, 4, byte_order
);
3501 if (base
== 4 && irp
->popl_esp_hack
)
3502 *addr
+= irp
->popl_esp_hack
;
3503 regcache_raw_read_unsigned (irp
->regcache
, irp
->regmap
[base
],
3506 if (irp
->aflag
== 2)
3511 *addr
= (uint32_t) (offset64
+ *addr
);
3513 if (havesib
&& (index
!= 4 || scale
!= 0))
3515 regcache_raw_read_unsigned (irp
->regcache
, irp
->regmap
[index
],
3517 if (irp
->aflag
== 2)
3518 *addr
+= offset64
<< scale
;
3520 *addr
= (uint32_t) (*addr
+ (offset64
<< scale
));
3531 if (target_read_memory (irp
->addr
, buf
, 2))
3534 printf_unfiltered (_("Process record: error reading "
3535 "memory at addr %s len = 2.\n"),
3536 paddress (gdbarch
, irp
->addr
));
3540 *addr
= extract_signed_integer (buf
, 2, byte_order
);
3546 if (target_read_memory (irp
->addr
, buf
, 1))
3549 printf_unfiltered (_("Process record: error reading memory "
3550 "at addr %s len = 1.\n"),
3551 paddress (gdbarch
, irp
->addr
));
3555 *addr
= (int8_t) buf
[0];
3558 if (target_read_memory (irp
->addr
, buf
, 2))
3561 printf_unfiltered (_("Process record: error reading memory "
3562 "at addr %s len = 2.\n"),
3563 paddress (gdbarch
, irp
->addr
));
3567 *addr
= extract_signed_integer (buf
, 2, byte_order
);
3574 regcache_raw_read_unsigned (irp
->regcache
,
3575 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
3577 *addr
= (uint32_t) (*addr
+ offset64
);
3578 regcache_raw_read_unsigned (irp
->regcache
,
3579 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
3581 *addr
= (uint32_t) (*addr
+ offset64
);
3584 regcache_raw_read_unsigned (irp
->regcache
,
3585 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
3587 *addr
= (uint32_t) (*addr
+ offset64
);
3588 regcache_raw_read_unsigned (irp
->regcache
,
3589 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
3591 *addr
= (uint32_t) (*addr
+ offset64
);
3594 regcache_raw_read_unsigned (irp
->regcache
,
3595 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
3597 *addr
= (uint32_t) (*addr
+ offset64
);
3598 regcache_raw_read_unsigned (irp
->regcache
,
3599 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
3601 *addr
= (uint32_t) (*addr
+ offset64
);
3604 regcache_raw_read_unsigned (irp
->regcache
,
3605 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
3607 *addr
= (uint32_t) (*addr
+ offset64
);
3608 regcache_raw_read_unsigned (irp
->regcache
,
3609 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
3611 *addr
= (uint32_t) (*addr
+ offset64
);
3614 regcache_raw_read_unsigned (irp
->regcache
,
3615 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
3617 *addr
= (uint32_t) (*addr
+ offset64
);
3620 regcache_raw_read_unsigned (irp
->regcache
,
3621 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
3623 *addr
= (uint32_t) (*addr
+ offset64
);
3626 regcache_raw_read_unsigned (irp
->regcache
,
3627 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
3629 *addr
= (uint32_t) (*addr
+ offset64
);
3632 regcache_raw_read_unsigned (irp
->regcache
,
3633 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
3635 *addr
= (uint32_t) (*addr
+ offset64
);
3645 /* Record the value of the memory that willbe changed in current instruction
3646 to "record_arch_list".
3647 Return -1 if something wrong. */
3650 i386_record_lea_modrm (struct i386_record_s
*irp
)
3652 struct gdbarch
*gdbarch
= irp
->gdbarch
;
3655 if (irp
->override
>= 0)
3657 if (record_memory_query
)
3661 target_terminal_ours ();
3663 Process record ignores the memory change of instruction at address %s\n\
3664 because it can't get the value of the segment register.\n\
3665 Do you want to stop the program?"),
3666 paddress (gdbarch
, irp
->orig_addr
));
3667 target_terminal_inferior ();
3675 if (i386_record_lea_modrm_addr (irp
, &addr
))
3678 if (record_arch_list_add_mem (addr
, 1 << irp
->ot
))
3684 /* Record the push operation to "record_arch_list".
3685 Return -1 if something wrong. */
3688 i386_record_push (struct i386_record_s
*irp
, int size
)
3692 if (record_arch_list_add_reg (irp
->regcache
,
3693 irp
->regmap
[X86_RECORD_RESP_REGNUM
]))
3695 regcache_raw_read_unsigned (irp
->regcache
,
3696 irp
->regmap
[X86_RECORD_RESP_REGNUM
],
3698 if (record_arch_list_add_mem ((CORE_ADDR
) addr
- size
, size
))
3705 /* Defines contents to record. */
3706 #define I386_SAVE_FPU_REGS 0xfffd
3707 #define I386_SAVE_FPU_ENV 0xfffe
3708 #define I386_SAVE_FPU_ENV_REG_STACK 0xffff
3710 /* Record the value of floating point registers which will be changed
3711 by the current instruction to "record_arch_list". Return -1 if
3712 something is wrong. */
3714 static int i386_record_floats (struct gdbarch
*gdbarch
,
3715 struct i386_record_s
*ir
,
3718 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3721 /* Oza: Because of floating point insn push/pop of fpu stack is going to
3722 happen. Currently we store st0-st7 registers, but we need not store all
3723 registers all the time, in future we use ftag register and record only
3724 those who are not marked as an empty. */
3726 if (I386_SAVE_FPU_REGS
== iregnum
)
3728 for (i
= I387_ST0_REGNUM (tdep
); i
<= I387_ST0_REGNUM (tdep
) + 7; i
++)
3730 if (record_arch_list_add_reg (ir
->regcache
, i
))
3734 else if (I386_SAVE_FPU_ENV
== iregnum
)
3736 for (i
= I387_FCTRL_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
3738 if (record_arch_list_add_reg (ir
->regcache
, i
))
3742 else if (I386_SAVE_FPU_ENV_REG_STACK
== iregnum
)
3744 for (i
= I387_ST0_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
3746 if (record_arch_list_add_reg (ir
->regcache
, i
))
3750 else if ((iregnum
>= I387_ST0_REGNUM (tdep
)) &&
3751 (iregnum
<= I387_FOP_REGNUM (tdep
)))
3753 if (record_arch_list_add_reg (ir
->regcache
,iregnum
))
3758 /* Parameter error. */
3761 if(I386_SAVE_FPU_ENV
!= iregnum
)
3763 for (i
= I387_FCTRL_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
3765 if (record_arch_list_add_reg (ir
->regcache
, i
))
3772 /* Parse the current instruction and record the values of the registers and
3773 memory that will be changed in current instruction to "record_arch_list".
3774 Return -1 if something wrong. */
3776 #define I386_RECORD_ARCH_LIST_ADD_REG(regnum) \
3777 record_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)])
3780 i386_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
3781 CORE_ADDR input_addr
)
3783 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3789 gdb_byte buf
[MAX_REGISTER_SIZE
];
3790 struct i386_record_s ir
;
3791 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3796 memset (&ir
, 0, sizeof (struct i386_record_s
));
3797 ir
.regcache
= regcache
;
3798 ir
.addr
= input_addr
;
3799 ir
.orig_addr
= input_addr
;
3803 ir
.popl_esp_hack
= 0;
3804 ir
.regmap
= tdep
->record_regmap
;
3805 ir
.gdbarch
= gdbarch
;
3807 if (record_debug
> 1)
3808 fprintf_unfiltered (gdb_stdlog
, "Process record: i386_process_record "
3810 paddress (gdbarch
, ir
.addr
));
3815 if (target_read_memory (ir
.addr
, &opcode8
, 1))
3818 printf_unfiltered (_("Process record: error reading memory at "
3819 "addr %s len = 1.\n"),
3820 paddress (gdbarch
, ir
.addr
));
3824 switch (opcode8
) /* Instruction prefixes */
3826 case REPE_PREFIX_OPCODE
:
3827 prefixes
|= PREFIX_REPZ
;
3829 case REPNE_PREFIX_OPCODE
:
3830 prefixes
|= PREFIX_REPNZ
;
3832 case LOCK_PREFIX_OPCODE
:
3833 prefixes
|= PREFIX_LOCK
;
3835 case CS_PREFIX_OPCODE
:
3836 ir
.override
= X86_RECORD_CS_REGNUM
;
3838 case SS_PREFIX_OPCODE
:
3839 ir
.override
= X86_RECORD_SS_REGNUM
;
3841 case DS_PREFIX_OPCODE
:
3842 ir
.override
= X86_RECORD_DS_REGNUM
;
3844 case ES_PREFIX_OPCODE
:
3845 ir
.override
= X86_RECORD_ES_REGNUM
;
3847 case FS_PREFIX_OPCODE
:
3848 ir
.override
= X86_RECORD_FS_REGNUM
;
3850 case GS_PREFIX_OPCODE
:
3851 ir
.override
= X86_RECORD_GS_REGNUM
;
3853 case DATA_PREFIX_OPCODE
:
3854 prefixes
|= PREFIX_DATA
;
3856 case ADDR_PREFIX_OPCODE
:
3857 prefixes
|= PREFIX_ADDR
;
3859 case 0x40: /* i386 inc %eax */
3860 case 0x41: /* i386 inc %ecx */
3861 case 0x42: /* i386 inc %edx */
3862 case 0x43: /* i386 inc %ebx */
3863 case 0x44: /* i386 inc %esp */
3864 case 0x45: /* i386 inc %ebp */
3865 case 0x46: /* i386 inc %esi */
3866 case 0x47: /* i386 inc %edi */
3867 case 0x48: /* i386 dec %eax */
3868 case 0x49: /* i386 dec %ecx */
3869 case 0x4a: /* i386 dec %edx */
3870 case 0x4b: /* i386 dec %ebx */
3871 case 0x4c: /* i386 dec %esp */
3872 case 0x4d: /* i386 dec %ebp */
3873 case 0x4e: /* i386 dec %esi */
3874 case 0x4f: /* i386 dec %edi */
3875 if (ir
.regmap
[X86_RECORD_R8_REGNUM
]) /* 64 bit target */
3879 rex_w
= (opcode8
>> 3) & 1;
3880 rex_r
= (opcode8
& 0x4) << 1;
3881 ir
.rex_x
= (opcode8
& 0x2) << 2;
3882 ir
.rex_b
= (opcode8
& 0x1) << 3;
3884 else /* 32 bit target */
3893 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && rex_w
== 1)
3899 if (prefixes
& PREFIX_DATA
)
3902 if (prefixes
& PREFIX_ADDR
)
3904 else if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
3907 /* Now check op code. */
3908 opcode
= (uint32_t) opcode8
;
3913 if (target_read_memory (ir
.addr
, &opcode8
, 1))
3916 printf_unfiltered (_("Process record: error reading memory at "
3917 "addr %s len = 1.\n"),
3918 paddress (gdbarch
, ir
.addr
));
3922 opcode
= (uint32_t) opcode8
| 0x0f00;
3926 case 0x00: /* arith & logic */
3974 if (((opcode
>> 3) & 7) != OP_CMPL
)
3976 if ((opcode
& 1) == 0)
3979 ir
.ot
= ir
.dflag
+ OT_WORD
;
3981 switch ((opcode
>> 1) & 3)
3983 case 0: /* OP Ev, Gv */
3984 if (i386_record_modrm (&ir
))
3988 if (i386_record_lea_modrm (&ir
))
3994 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3996 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
3999 case 1: /* OP Gv, Ev */
4000 if (i386_record_modrm (&ir
))
4003 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4005 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4007 case 2: /* OP A, Iv */
4008 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4012 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4015 case 0x80: /* GRP1 */
4019 if (i386_record_modrm (&ir
))
4022 if (ir
.reg
!= OP_CMPL
)
4024 if ((opcode
& 1) == 0)
4027 ir
.ot
= ir
.dflag
+ OT_WORD
;
4034 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
4035 if (i386_record_lea_modrm (&ir
))
4039 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
4041 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4044 case 0x40: /* inc */
4053 case 0x48: /* dec */
4062 I386_RECORD_ARCH_LIST_ADD_REG (opcode
& 7);
4063 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4066 case 0xf6: /* GRP3 */
4068 if ((opcode
& 1) == 0)
4071 ir
.ot
= ir
.dflag
+ OT_WORD
;
4072 if (i386_record_modrm (&ir
))
4075 if (ir
.mod
!= 3 && ir
.reg
== 0)
4076 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
4081 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4087 if (i386_record_lea_modrm (&ir
))
4093 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4095 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4097 if (ir
.reg
== 3) /* neg */
4098 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4104 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4105 if (ir
.ot
!= OT_BYTE
)
4106 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
4107 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4111 opcode
= opcode
<< 8 | ir
.modrm
;
4117 case 0xfe: /* GRP4 */
4118 case 0xff: /* GRP5 */
4119 if (i386_record_modrm (&ir
))
4121 if (ir
.reg
>= 2 && opcode
== 0xfe)
4124 opcode
= opcode
<< 8 | ir
.modrm
;
4131 if ((opcode
& 1) == 0)
4134 ir
.ot
= ir
.dflag
+ OT_WORD
;
4137 if (i386_record_lea_modrm (&ir
))
4143 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4145 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4147 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4150 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4152 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4154 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4157 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
4158 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4160 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4164 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4167 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4169 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4174 opcode
= opcode
<< 8 | ir
.modrm
;
4180 case 0x84: /* test */
4184 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4187 case 0x98: /* CWDE/CBW */
4188 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4191 case 0x99: /* CDQ/CWD */
4192 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4193 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
4196 case 0x0faf: /* imul */
4199 ir
.ot
= ir
.dflag
+ OT_WORD
;
4200 if (i386_record_modrm (&ir
))
4203 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
4204 else if (opcode
== 0x6b)
4207 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4209 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4210 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4213 case 0x0fc0: /* xadd */
4215 if ((opcode
& 1) == 0)
4218 ir
.ot
= ir
.dflag
+ OT_WORD
;
4219 if (i386_record_modrm (&ir
))
4224 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4226 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4227 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4229 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4233 if (i386_record_lea_modrm (&ir
))
4235 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4237 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4239 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4242 case 0x0fb0: /* cmpxchg */
4244 if ((opcode
& 1) == 0)
4247 ir
.ot
= ir
.dflag
+ OT_WORD
;
4248 if (i386_record_modrm (&ir
))
4253 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4254 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4256 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4260 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4261 if (i386_record_lea_modrm (&ir
))
4264 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4267 case 0x0fc7: /* cmpxchg8b */
4268 if (i386_record_modrm (&ir
))
4273 opcode
= opcode
<< 8 | ir
.modrm
;
4276 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4277 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
4278 if (i386_record_lea_modrm (&ir
))
4280 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4283 case 0x50: /* push */
4293 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4295 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4299 case 0x06: /* push es */
4300 case 0x0e: /* push cs */
4301 case 0x16: /* push ss */
4302 case 0x1e: /* push ds */
4303 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4308 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4312 case 0x0fa0: /* push fs */
4313 case 0x0fa8: /* push gs */
4314 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4319 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4323 case 0x60: /* pusha */
4324 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4329 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 4)))
4333 case 0x58: /* pop */
4341 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4342 I386_RECORD_ARCH_LIST_ADD_REG ((opcode
& 0x7) | ir
.rex_b
);
4345 case 0x61: /* popa */
4346 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4351 for (regnum
= X86_RECORD_REAX_REGNUM
;
4352 regnum
<= X86_RECORD_REDI_REGNUM
;
4354 I386_RECORD_ARCH_LIST_ADD_REG (regnum
);
4357 case 0x8f: /* pop */
4358 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4359 ir
.ot
= ir
.dflag
? OT_QUAD
: OT_WORD
;
4361 ir
.ot
= ir
.dflag
+ OT_WORD
;
4362 if (i386_record_modrm (&ir
))
4365 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
4368 ir
.popl_esp_hack
= 1 << ir
.ot
;
4369 if (i386_record_lea_modrm (&ir
))
4372 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4375 case 0xc8: /* enter */
4376 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
4377 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4379 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4383 case 0xc9: /* leave */
4384 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4385 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
4388 case 0x07: /* pop es */
4389 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4394 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4395 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM
);
4396 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4399 case 0x17: /* pop ss */
4400 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4405 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4406 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM
);
4407 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4410 case 0x1f: /* pop ds */
4411 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4416 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4417 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM
);
4418 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4421 case 0x0fa1: /* pop fs */
4422 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4423 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM
);
4424 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4427 case 0x0fa9: /* pop gs */
4428 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4429 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM
);
4430 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4433 case 0x88: /* mov */
4437 if ((opcode
& 1) == 0)
4440 ir
.ot
= ir
.dflag
+ OT_WORD
;
4442 if (i386_record_modrm (&ir
))
4447 if (opcode
== 0xc6 || opcode
== 0xc7)
4448 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
4449 if (i386_record_lea_modrm (&ir
))
4454 if (opcode
== 0xc6 || opcode
== 0xc7)
4456 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4458 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4462 case 0x8a: /* mov */
4464 if ((opcode
& 1) == 0)
4467 ir
.ot
= ir
.dflag
+ OT_WORD
;
4468 if (i386_record_modrm (&ir
))
4471 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4473 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4476 case 0x8c: /* mov seg */
4477 if (i386_record_modrm (&ir
))
4482 opcode
= opcode
<< 8 | ir
.modrm
;
4487 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4491 if (i386_record_lea_modrm (&ir
))
4496 case 0x8e: /* mov seg */
4497 if (i386_record_modrm (&ir
))
4502 regnum
= X86_RECORD_ES_REGNUM
;
4505 regnum
= X86_RECORD_SS_REGNUM
;
4508 regnum
= X86_RECORD_DS_REGNUM
;
4511 regnum
= X86_RECORD_FS_REGNUM
;
4514 regnum
= X86_RECORD_GS_REGNUM
;
4518 opcode
= opcode
<< 8 | ir
.modrm
;
4522 I386_RECORD_ARCH_LIST_ADD_REG (regnum
);
4523 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4526 case 0x0fb6: /* movzbS */
4527 case 0x0fb7: /* movzwS */
4528 case 0x0fbe: /* movsbS */
4529 case 0x0fbf: /* movswS */
4530 if (i386_record_modrm (&ir
))
4532 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
4535 case 0x8d: /* lea */
4536 if (i386_record_modrm (&ir
))
4541 opcode
= opcode
<< 8 | ir
.modrm
;
4546 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4548 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4551 case 0xa0: /* mov EAX */
4554 case 0xd7: /* xlat */
4555 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4558 case 0xa2: /* mov EAX */
4560 if (ir
.override
>= 0)
4562 if (record_memory_query
)
4566 target_terminal_ours ();
4568 Process record ignores the memory change of instruction at address %s\n\
4569 because it can't get the value of the segment register.\n\
4570 Do you want to stop the program?"),
4571 paddress (gdbarch
, ir
.orig_addr
));
4572 target_terminal_inferior ();
4579 if ((opcode
& 1) == 0)
4582 ir
.ot
= ir
.dflag
+ OT_WORD
;
4585 if (target_read_memory (ir
.addr
, buf
, 8))
4588 printf_unfiltered (_("Process record: error reading "
4589 "memory at addr 0x%s len = 8.\n"),
4590 paddress (gdbarch
, ir
.addr
));
4594 addr
= extract_unsigned_integer (buf
, 8, byte_order
);
4598 if (target_read_memory (ir
.addr
, buf
, 4))
4601 printf_unfiltered (_("Process record: error reading "
4602 "memory at addr 0x%s len = 4.\n"),
4603 paddress (gdbarch
, ir
.addr
));
4607 addr
= extract_unsigned_integer (buf
, 4, byte_order
);
4611 if (target_read_memory (ir
.addr
, buf
, 2))
4614 printf_unfiltered (_("Process record: error reading "
4615 "memory at addr 0x%s len = 2.\n"),
4616 paddress (gdbarch
, ir
.addr
));
4620 addr
= extract_unsigned_integer (buf
, 2, byte_order
);
4622 if (record_arch_list_add_mem (addr
, 1 << ir
.ot
))
4627 case 0xb0: /* mov R, Ib */
4635 I386_RECORD_ARCH_LIST_ADD_REG ((ir
.regmap
[X86_RECORD_R8_REGNUM
])
4636 ? ((opcode
& 0x7) | ir
.rex_b
)
4637 : ((opcode
& 0x7) & 0x3));
4640 case 0xb8: /* mov R, Iv */
4648 I386_RECORD_ARCH_LIST_ADD_REG ((opcode
& 0x7) | ir
.rex_b
);
4651 case 0x91: /* xchg R, EAX */
4658 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4659 I386_RECORD_ARCH_LIST_ADD_REG (opcode
& 0x7);
4662 case 0x86: /* xchg Ev, Gv */
4664 if ((opcode
& 1) == 0)
4667 ir
.ot
= ir
.dflag
+ OT_WORD
;
4668 if (i386_record_modrm (&ir
))
4673 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4675 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4679 if (i386_record_lea_modrm (&ir
))
4683 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4685 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4688 case 0xc4: /* les Gv */
4689 case 0xc5: /* lds Gv */
4690 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4696 case 0x0fb2: /* lss Gv */
4697 case 0x0fb4: /* lfs Gv */
4698 case 0x0fb5: /* lgs Gv */
4699 if (i386_record_modrm (&ir
))
4707 opcode
= opcode
<< 8 | ir
.modrm
;
4712 case 0xc4: /* les Gv */
4713 regnum
= X86_RECORD_ES_REGNUM
;
4715 case 0xc5: /* lds Gv */
4716 regnum
= X86_RECORD_DS_REGNUM
;
4718 case 0x0fb2: /* lss Gv */
4719 regnum
= X86_RECORD_SS_REGNUM
;
4721 case 0x0fb4: /* lfs Gv */
4722 regnum
= X86_RECORD_FS_REGNUM
;
4724 case 0x0fb5: /* lgs Gv */
4725 regnum
= X86_RECORD_GS_REGNUM
;
4728 I386_RECORD_ARCH_LIST_ADD_REG (regnum
);
4729 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
4730 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4733 case 0xc0: /* shifts */
4739 if ((opcode
& 1) == 0)
4742 ir
.ot
= ir
.dflag
+ OT_WORD
;
4743 if (i386_record_modrm (&ir
))
4745 if (ir
.mod
!= 3 && (opcode
== 0xd2 || opcode
== 0xd3))
4747 if (i386_record_lea_modrm (&ir
))
4753 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4755 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4757 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4764 if (i386_record_modrm (&ir
))
4768 if (record_arch_list_add_reg (ir
.regcache
, ir
.rm
))
4773 if (i386_record_lea_modrm (&ir
))
4778 case 0xd8: /* Floats. */
4786 if (i386_record_modrm (&ir
))
4788 ir
.reg
|= ((opcode
& 7) << 3);
4794 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
4802 /* For fcom, ficom nothing to do. */
4808 /* For fcomp, ficomp pop FPU stack, store all. */
4809 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
4836 /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul,
4837 fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension
4838 of code, always affects st(0) register. */
4839 if (i386_record_floats (gdbarch
, &ir
, I387_ST0_REGNUM (tdep
)))
4863 /* Handling fld, fild. */
4864 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
4868 switch (ir
.reg
>> 4)
4871 if (record_arch_list_add_mem (addr64
, 4))
4875 if (record_arch_list_add_mem (addr64
, 8))
4881 if (record_arch_list_add_mem (addr64
, 2))
4887 switch (ir
.reg
>> 4)
4890 if (record_arch_list_add_mem (addr64
, 4))
4892 if (3 == (ir
.reg
& 7))
4894 /* For fstp m32fp. */
4895 if (i386_record_floats (gdbarch
, &ir
,
4896 I386_SAVE_FPU_REGS
))
4901 if (record_arch_list_add_mem (addr64
, 4))
4903 if ((3 == (ir
.reg
& 7))
4904 || (5 == (ir
.reg
& 7))
4905 || (7 == (ir
.reg
& 7)))
4907 /* For fstp insn. */
4908 if (i386_record_floats (gdbarch
, &ir
,
4909 I386_SAVE_FPU_REGS
))
4914 if (record_arch_list_add_mem (addr64
, 8))
4916 if (3 == (ir
.reg
& 7))
4918 /* For fstp m64fp. */
4919 if (i386_record_floats (gdbarch
, &ir
,
4920 I386_SAVE_FPU_REGS
))
4925 if ((3 <= (ir
.reg
& 7)) && (6 <= (ir
.reg
& 7)))
4927 /* For fistp, fbld, fild, fbstp. */
4928 if (i386_record_floats (gdbarch
, &ir
,
4929 I386_SAVE_FPU_REGS
))
4934 if (record_arch_list_add_mem (addr64
, 2))
4943 if (i386_record_floats (gdbarch
, &ir
,
4944 I386_SAVE_FPU_ENV_REG_STACK
))
4949 if (i386_record_floats (gdbarch
, &ir
, I387_FCTRL_REGNUM (tdep
)))
4954 if (i386_record_floats (gdbarch
, &ir
,
4955 I386_SAVE_FPU_ENV_REG_STACK
))
4961 if (record_arch_list_add_mem (addr64
, 28))
4966 if (record_arch_list_add_mem (addr64
, 14))
4972 if (record_arch_list_add_mem (addr64
, 2))
4974 /* Insn fstp, fbstp. */
4975 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
4980 if (record_arch_list_add_mem (addr64
, 10))
4986 if (record_arch_list_add_mem (addr64
, 28))
4992 if (record_arch_list_add_mem (addr64
, 14))
4996 if (record_arch_list_add_mem (addr64
, 80))
4999 if (i386_record_floats (gdbarch
, &ir
,
5000 I386_SAVE_FPU_ENV_REG_STACK
))
5004 if (record_arch_list_add_mem (addr64
, 8))
5007 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5012 opcode
= opcode
<< 8 | ir
.modrm
;
5017 /* Opcode is an extension of modR/M byte. */
5023 if (i386_record_floats (gdbarch
, &ir
, I387_ST0_REGNUM (tdep
)))
5027 if (0x0c == (ir
.modrm
>> 4))
5029 if ((ir
.modrm
& 0x0f) <= 7)
5031 if (i386_record_floats (gdbarch
, &ir
,
5032 I386_SAVE_FPU_REGS
))
5037 if (i386_record_floats (gdbarch
, &ir
,
5038 I387_ST0_REGNUM (tdep
)))
5040 /* If only st(0) is changing, then we have already
5042 if ((ir
.modrm
& 0x0f) - 0x08)
5044 if (i386_record_floats (gdbarch
, &ir
,
5045 I387_ST0_REGNUM (tdep
) +
5046 ((ir
.modrm
& 0x0f) - 0x08)))
5064 if (i386_record_floats (gdbarch
, &ir
,
5065 I387_ST0_REGNUM (tdep
)))
5083 if (i386_record_floats (gdbarch
, &ir
,
5084 I386_SAVE_FPU_REGS
))
5088 if (i386_record_floats (gdbarch
, &ir
,
5089 I387_ST0_REGNUM (tdep
)))
5091 if (i386_record_floats (gdbarch
, &ir
,
5092 I387_ST0_REGNUM (tdep
) + 1))
5099 if (0xe9 == ir
.modrm
)
5101 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5104 else if ((0x0c == ir
.modrm
>> 4) || (0x0d == ir
.modrm
>> 4))
5106 if (i386_record_floats (gdbarch
, &ir
,
5107 I387_ST0_REGNUM (tdep
)))
5109 if (((ir
.modrm
& 0x0f) > 0) && ((ir
.modrm
& 0x0f) <= 7))
5111 if (i386_record_floats (gdbarch
, &ir
,
5112 I387_ST0_REGNUM (tdep
) +
5116 else if ((ir
.modrm
& 0x0f) - 0x08)
5118 if (i386_record_floats (gdbarch
, &ir
,
5119 I387_ST0_REGNUM (tdep
) +
5120 ((ir
.modrm
& 0x0f) - 0x08)))
5126 if (0xe3 == ir
.modrm
)
5128 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_ENV
))
5131 else if ((0x0c == ir
.modrm
>> 4) || (0x0d == ir
.modrm
>> 4))
5133 if (i386_record_floats (gdbarch
, &ir
,
5134 I387_ST0_REGNUM (tdep
)))
5136 if (((ir
.modrm
& 0x0f) > 0) && ((ir
.modrm
& 0x0f) <= 7))
5138 if (i386_record_floats (gdbarch
, &ir
,
5139 I387_ST0_REGNUM (tdep
) +
5143 else if ((ir
.modrm
& 0x0f) - 0x08)
5145 if (i386_record_floats (gdbarch
, &ir
,
5146 I387_ST0_REGNUM (tdep
) +
5147 ((ir
.modrm
& 0x0f) - 0x08)))
5153 if ((0x0c == ir
.modrm
>> 4)
5154 || (0x0d == ir
.modrm
>> 4)
5155 || (0x0f == ir
.modrm
>> 4))
5157 if ((ir
.modrm
& 0x0f) <= 7)
5159 if (i386_record_floats (gdbarch
, &ir
,
5160 I387_ST0_REGNUM (tdep
) +
5166 if (i386_record_floats (gdbarch
, &ir
,
5167 I387_ST0_REGNUM (tdep
) +
5168 ((ir
.modrm
& 0x0f) - 0x08)))
5174 if (0x0c == ir
.modrm
>> 4)
5176 if (i386_record_floats (gdbarch
, &ir
,
5177 I387_FTAG_REGNUM (tdep
)))
5180 else if ((0x0d == ir
.modrm
>> 4) || (0x0e == ir
.modrm
>> 4))
5182 if ((ir
.modrm
& 0x0f) <= 7)
5184 if (i386_record_floats (gdbarch
, &ir
,
5185 I387_ST0_REGNUM (tdep
) +
5191 if (i386_record_floats (gdbarch
, &ir
,
5192 I386_SAVE_FPU_REGS
))
5198 if ((0x0c == ir
.modrm
>> 4)
5199 || (0x0e == ir
.modrm
>> 4)
5200 || (0x0f == ir
.modrm
>> 4)
5201 || (0xd9 == ir
.modrm
))
5203 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5208 if (0xe0 == ir
.modrm
)
5210 if (record_arch_list_add_reg (ir
.regcache
, I386_EAX_REGNUM
))
5213 else if ((0x0f == ir
.modrm
>> 4) || (0x0e == ir
.modrm
>> 4))
5215 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5223 case 0xa4: /* movsS */
5225 case 0xaa: /* stosS */
5227 case 0x6c: /* insS */
5229 regcache_raw_read_unsigned (ir
.regcache
,
5230 ir
.regmap
[X86_RECORD_RECX_REGNUM
],
5236 if ((opcode
& 1) == 0)
5239 ir
.ot
= ir
.dflag
+ OT_WORD
;
5240 regcache_raw_read_unsigned (ir
.regcache
,
5241 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
5244 regcache_raw_read_unsigned (ir
.regcache
,
5245 ir
.regmap
[X86_RECORD_ES_REGNUM
],
5247 regcache_raw_read_unsigned (ir
.regcache
,
5248 ir
.regmap
[X86_RECORD_DS_REGNUM
],
5250 if (ir
.aflag
&& (es
!= ds
))
5252 /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */
5253 if (record_memory_query
)
5257 target_terminal_ours ();
5259 Process record ignores the memory change of instruction at address %s\n\
5260 because it can't get the value of the segment register.\n\
5261 Do you want to stop the program?"),
5262 paddress (gdbarch
, ir
.orig_addr
));
5263 target_terminal_inferior ();
5270 if (record_arch_list_add_mem (addr
, 1 << ir
.ot
))
5274 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5275 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5276 if (opcode
== 0xa4 || opcode
== 0xa5)
5277 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
5278 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
5279 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5283 case 0xa6: /* cmpsS */
5285 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
5286 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
5287 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5288 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5289 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5292 case 0xac: /* lodsS */
5294 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5295 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
5296 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5297 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5298 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5301 case 0xae: /* scasS */
5303 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
5304 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5305 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5306 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5309 case 0x6e: /* outsS */
5311 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
5312 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5313 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5314 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5317 case 0xe4: /* port I/O */
5321 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5322 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5332 case 0xc2: /* ret im */
5333 case 0xc3: /* ret */
5334 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5335 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5338 case 0xca: /* lret im */
5339 case 0xcb: /* lret */
5340 case 0xcf: /* iret */
5341 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
5342 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5343 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5346 case 0xe8: /* call im */
5347 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5349 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5353 case 0x9a: /* lcall im */
5354 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5359 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
5360 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5364 case 0xe9: /* jmp im */
5365 case 0xea: /* ljmp im */
5366 case 0xeb: /* jmp Jb */
5367 case 0x70: /* jcc Jb */
5383 case 0x0f80: /* jcc Jv */
5401 case 0x0f90: /* setcc Gv */
5417 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5419 if (i386_record_modrm (&ir
))
5422 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rex_b
? (ir
.rm
| ir
.rex_b
)
5426 if (i386_record_lea_modrm (&ir
))
5431 case 0x0f40: /* cmov Gv, Ev */
5447 if (i386_record_modrm (&ir
))
5450 if (ir
.dflag
== OT_BYTE
)
5452 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
5456 case 0x9c: /* pushf */
5457 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5458 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5460 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5464 case 0x9d: /* popf */
5465 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5466 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5469 case 0x9e: /* sahf */
5470 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5476 case 0xf5: /* cmc */
5477 case 0xf8: /* clc */
5478 case 0xf9: /* stc */
5479 case 0xfc: /* cld */
5480 case 0xfd: /* std */
5481 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5484 case 0x9f: /* lahf */
5485 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5490 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5491 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5494 /* bit operations */
5495 case 0x0fba: /* bt/bts/btr/btc Gv, im */
5496 ir
.ot
= ir
.dflag
+ OT_WORD
;
5497 if (i386_record_modrm (&ir
))
5502 opcode
= opcode
<< 8 | ir
.modrm
;
5508 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5511 if (i386_record_lea_modrm (&ir
))
5515 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5518 case 0x0fa3: /* bt Gv, Ev */
5519 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5522 case 0x0fab: /* bts */
5523 case 0x0fb3: /* btr */
5524 case 0x0fbb: /* btc */
5525 ir
.ot
= ir
.dflag
+ OT_WORD
;
5526 if (i386_record_modrm (&ir
))
5529 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5533 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
5535 regcache_raw_read_unsigned (ir
.regcache
,
5536 ir
.regmap
[ir
.reg
| rex_r
],
5541 addr64
+= ((int16_t) addr
>> 4) << 4;
5544 addr64
+= ((int32_t) addr
>> 5) << 5;
5547 addr64
+= ((int64_t) addr
>> 6) << 6;
5550 if (record_arch_list_add_mem (addr64
, 1 << ir
.ot
))
5552 if (i386_record_lea_modrm (&ir
))
5555 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5558 case 0x0fbc: /* bsf */
5559 case 0x0fbd: /* bsr */
5560 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
5561 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5565 case 0x27: /* daa */
5566 case 0x2f: /* das */
5567 case 0x37: /* aaa */
5568 case 0x3f: /* aas */
5569 case 0xd4: /* aam */
5570 case 0xd5: /* aad */
5571 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5576 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5577 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5581 case 0x90: /* nop */
5582 if (prefixes
& PREFIX_LOCK
)
5589 case 0x9b: /* fwait */
5590 if (target_read_memory (ir
.addr
, &opcode8
, 1))
5593 printf_unfiltered (_("Process record: error reading memory at "
5594 "addr 0x%s len = 1.\n"),
5595 paddress (gdbarch
, ir
.addr
));
5598 opcode
= (uint32_t) opcode8
;
5604 case 0xcc: /* int3 */
5605 printf_unfiltered (_("Process record does not support instruction "
5612 case 0xcd: /* int */
5616 if (target_read_memory (ir
.addr
, &interrupt
, 1))
5619 printf_unfiltered (_("Process record: error reading memory "
5620 "at addr %s len = 1.\n"),
5621 paddress (gdbarch
, ir
.addr
));
5625 if (interrupt
!= 0x80
5626 || tdep
->i386_intx80_record
== NULL
)
5628 printf_unfiltered (_("Process record does not support "
5629 "instruction int 0x%02x.\n"),
5634 ret
= tdep
->i386_intx80_record (ir
.regcache
);
5641 case 0xce: /* into */
5642 printf_unfiltered (_("Process record does not support "
5643 "instruction into.\n"));
5648 case 0xfa: /* cli */
5649 case 0xfb: /* sti */
5652 case 0x62: /* bound */
5653 printf_unfiltered (_("Process record does not support "
5654 "instruction bound.\n"));
5659 case 0x0fc8: /* bswap reg */
5667 I386_RECORD_ARCH_LIST_ADD_REG ((opcode
& 7) | ir
.rex_b
);
5670 case 0xd6: /* salc */
5671 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5676 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5677 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5680 case 0xe0: /* loopnz */
5681 case 0xe1: /* loopz */
5682 case 0xe2: /* loop */
5683 case 0xe3: /* jecxz */
5684 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5685 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5688 case 0x0f30: /* wrmsr */
5689 printf_unfiltered (_("Process record does not support "
5690 "instruction wrmsr.\n"));
5695 case 0x0f32: /* rdmsr */
5696 printf_unfiltered (_("Process record does not support "
5697 "instruction rdmsr.\n"));
5702 case 0x0f31: /* rdtsc */
5703 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5704 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5707 case 0x0f34: /* sysenter */
5710 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5715 if (tdep
->i386_sysenter_record
== NULL
)
5717 printf_unfiltered (_("Process record does not support "
5718 "instruction sysenter.\n"));
5722 ret
= tdep
->i386_sysenter_record (ir
.regcache
);
5728 case 0x0f35: /* sysexit */
5729 printf_unfiltered (_("Process record does not support "
5730 "instruction sysexit.\n"));
5735 case 0x0f05: /* syscall */
5738 if (tdep
->i386_syscall_record
== NULL
)
5740 printf_unfiltered (_("Process record does not support "
5741 "instruction syscall.\n"));
5745 ret
= tdep
->i386_syscall_record (ir
.regcache
);
5751 case 0x0f07: /* sysret */
5752 printf_unfiltered (_("Process record does not support "
5753 "instruction sysret.\n"));
5758 case 0x0fa2: /* cpuid */
5759 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5760 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5761 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5762 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM
);
5765 case 0xf4: /* hlt */
5766 printf_unfiltered (_("Process record does not support "
5767 "instruction hlt.\n"));
5773 if (i386_record_modrm (&ir
))
5780 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5784 if (i386_record_lea_modrm (&ir
))
5793 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5797 opcode
= opcode
<< 8 | ir
.modrm
;
5804 if (i386_record_modrm (&ir
))
5815 opcode
= opcode
<< 8 | ir
.modrm
;
5818 if (ir
.override
>= 0)
5820 if (record_memory_query
)
5824 target_terminal_ours ();
5826 Process record ignores the memory change of instruction at address %s\n\
5827 because it can't get the value of the segment register.\n\
5828 Do you want to stop the program?"),
5829 paddress (gdbarch
, ir
.orig_addr
));
5830 target_terminal_inferior ();
5837 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
5839 if (record_arch_list_add_mem (addr64
, 2))
5842 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5844 if (record_arch_list_add_mem (addr64
, 8))
5849 if (record_arch_list_add_mem (addr64
, 4))
5860 case 0: /* monitor */
5863 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5867 opcode
= opcode
<< 8 | ir
.modrm
;
5875 if (ir
.override
>= 0)
5877 if (record_memory_query
)
5881 target_terminal_ours ();
5883 Process record ignores the memory change of instruction at address %s\n\
5884 because it can't get the value of the segment register.\n\
5885 Do you want to stop the program?"),
5886 paddress (gdbarch
, ir
.orig_addr
));
5887 target_terminal_inferior ();
5896 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
5898 if (record_arch_list_add_mem (addr64
, 2))
5901 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5903 if (record_arch_list_add_mem (addr64
, 8))
5908 if (record_arch_list_add_mem (addr64
, 4))
5920 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5921 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5925 else if (ir
.rm
== 1)
5932 opcode
= opcode
<< 8 | ir
.modrm
;
5939 if (record_arch_list_add_reg (ir
.regcache
, ir
.rm
| ir
.rex_b
))
5945 if (i386_record_lea_modrm (&ir
))
5948 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5951 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5953 case 7: /* invlpg */
5956 if (ir
.rm
== 0 && ir
.regmap
[X86_RECORD_R8_REGNUM
])
5957 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM
);
5961 opcode
= opcode
<< 8 | ir
.modrm
;
5966 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5970 opcode
= opcode
<< 8 | ir
.modrm
;
5976 case 0x0f08: /* invd */
5977 case 0x0f09: /* wbinvd */
5980 case 0x63: /* arpl */
5981 if (i386_record_modrm (&ir
))
5983 if (ir
.mod
== 3 || ir
.regmap
[X86_RECORD_R8_REGNUM
])
5985 I386_RECORD_ARCH_LIST_ADD_REG (ir
.regmap
[X86_RECORD_R8_REGNUM
]
5986 ? (ir
.reg
| rex_r
) : ir
.rm
);
5990 ir
.ot
= ir
.dflag
? OT_LONG
: OT_WORD
;
5991 if (i386_record_lea_modrm (&ir
))
5994 if (!ir
.regmap
[X86_RECORD_R8_REGNUM
])
5995 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5998 case 0x0f02: /* lar */
5999 case 0x0f03: /* lsl */
6000 if (i386_record_modrm (&ir
))
6002 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
6003 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6007 if (i386_record_modrm (&ir
))
6009 if (ir
.mod
== 3 && ir
.reg
== 3)
6012 opcode
= opcode
<< 8 | ir
.modrm
;
6024 /* nop (multi byte) */
6027 case 0x0f20: /* mov reg, crN */
6028 case 0x0f22: /* mov crN, reg */
6029 if (i386_record_modrm (&ir
))
6031 if ((ir
.modrm
& 0xc0) != 0xc0)
6034 opcode
= opcode
<< 8 | ir
.modrm
;
6045 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6047 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6051 opcode
= opcode
<< 8 | ir
.modrm
;
6057 case 0x0f21: /* mov reg, drN */
6058 case 0x0f23: /* mov drN, reg */
6059 if (i386_record_modrm (&ir
))
6061 if ((ir
.modrm
& 0xc0) != 0xc0 || ir
.reg
== 4
6062 || ir
.reg
== 5 || ir
.reg
>= 8)
6065 opcode
= opcode
<< 8 | ir
.modrm
;
6069 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6071 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6074 case 0x0f06: /* clts */
6075 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6078 /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */
6080 case 0x0f0d: /* 3DNow! prefetch */
6083 case 0x0f0e: /* 3DNow! femms */
6084 case 0x0f77: /* emms */
6085 if (i386_fpc_regnum_p (gdbarch
, I387_FTAG_REGNUM(tdep
)))
6087 record_arch_list_add_reg (ir
.regcache
, I387_FTAG_REGNUM(tdep
));
6090 case 0x0f0f: /* 3DNow! data */
6091 if (i386_record_modrm (&ir
))
6093 if (target_read_memory (ir
.addr
, &opcode8
, 1))
6095 printf_unfiltered (_("Process record: error reading memory at "
6096 "addr %s len = 1.\n"),
6097 paddress (gdbarch
, ir
.addr
));
6103 case 0x0c: /* 3DNow! pi2fw */
6104 case 0x0d: /* 3DNow! pi2fd */
6105 case 0x1c: /* 3DNow! pf2iw */
6106 case 0x1d: /* 3DNow! pf2id */
6107 case 0x8a: /* 3DNow! pfnacc */
6108 case 0x8e: /* 3DNow! pfpnacc */
6109 case 0x90: /* 3DNow! pfcmpge */
6110 case 0x94: /* 3DNow! pfmin */
6111 case 0x96: /* 3DNow! pfrcp */
6112 case 0x97: /* 3DNow! pfrsqrt */
6113 case 0x9a: /* 3DNow! pfsub */
6114 case 0x9e: /* 3DNow! pfadd */
6115 case 0xa0: /* 3DNow! pfcmpgt */
6116 case 0xa4: /* 3DNow! pfmax */
6117 case 0xa6: /* 3DNow! pfrcpit1 */
6118 case 0xa7: /* 3DNow! pfrsqit1 */
6119 case 0xaa: /* 3DNow! pfsubr */
6120 case 0xae: /* 3DNow! pfacc */
6121 case 0xb0: /* 3DNow! pfcmpeq */
6122 case 0xb4: /* 3DNow! pfmul */
6123 case 0xb6: /* 3DNow! pfrcpit2 */
6124 case 0xb7: /* 3DNow! pmulhrw */
6125 case 0xbb: /* 3DNow! pswapd */
6126 case 0xbf: /* 3DNow! pavgusb */
6127 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.reg
))
6128 goto no_support_3dnow_data
;
6129 record_arch_list_add_reg (ir
.regcache
, ir
.reg
);
6133 no_support_3dnow_data
:
6134 opcode
= (opcode
<< 8) | opcode8
;
6140 case 0x0faa: /* rsm */
6141 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6142 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6143 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6144 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
6145 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM
);
6146 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
6147 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
6148 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
6149 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
6153 if (i386_record_modrm (&ir
))
6157 case 0: /* fxsave */
6161 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6162 if (i386_record_lea_modrm_addr (&ir
, &tmpu64
))
6164 if (record_arch_list_add_mem (tmpu64
, 512))
6169 case 1: /* fxrstor */
6173 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6175 for (i
= I387_MM0_REGNUM (tdep
);
6176 i386_mmx_regnum_p (gdbarch
, i
); i
++)
6177 record_arch_list_add_reg (ir
.regcache
, i
);
6179 for (i
= I387_XMM0_REGNUM (tdep
);
6180 i386_xmm_regnum_p (gdbarch
, i
); i
++)
6181 record_arch_list_add_reg (ir
.regcache
, i
);
6183 if (i386_mxcsr_regnum_p (gdbarch
, I387_MXCSR_REGNUM(tdep
)))
6184 record_arch_list_add_reg (ir
.regcache
, I387_MXCSR_REGNUM(tdep
));
6186 for (i
= I387_ST0_REGNUM (tdep
);
6187 i386_fp_regnum_p (gdbarch
, i
); i
++)
6188 record_arch_list_add_reg (ir
.regcache
, i
);
6190 for (i
= I387_FCTRL_REGNUM (tdep
);
6191 i386_fpc_regnum_p (gdbarch
, i
); i
++)
6192 record_arch_list_add_reg (ir
.regcache
, i
);
6196 case 2: /* ldmxcsr */
6197 if (!i386_mxcsr_regnum_p (gdbarch
, I387_MXCSR_REGNUM(tdep
)))
6199 record_arch_list_add_reg (ir
.regcache
, I387_MXCSR_REGNUM(tdep
));
6202 case 3: /* stmxcsr */
6204 if (i386_record_lea_modrm (&ir
))
6208 case 5: /* lfence */
6209 case 6: /* mfence */
6210 case 7: /* sfence clflush */
6214 opcode
= (opcode
<< 8) | ir
.modrm
;
6220 case 0x0fc3: /* movnti */
6221 ir
.ot
= (ir
.dflag
== 2) ? OT_QUAD
: OT_LONG
;
6222 if (i386_record_modrm (&ir
))
6227 if (i386_record_lea_modrm (&ir
))
6231 /* Add prefix to opcode. */
6358 reswitch_prefix_add
:
6366 if (target_read_memory (ir
.addr
, &opcode8
, 1))
6368 printf_unfiltered (_("Process record: error reading memory at "
6369 "addr %s len = 1.\n"),
6370 paddress (gdbarch
, ir
.addr
));
6374 opcode
= (uint32_t) opcode8
| opcode
<< 8;
6375 goto reswitch_prefix_add
;
6378 case 0x0f10: /* movups */
6379 case 0x660f10: /* movupd */
6380 case 0xf30f10: /* movss */
6381 case 0xf20f10: /* movsd */
6382 case 0x0f12: /* movlps */
6383 case 0x660f12: /* movlpd */
6384 case 0xf30f12: /* movsldup */
6385 case 0xf20f12: /* movddup */
6386 case 0x0f14: /* unpcklps */
6387 case 0x660f14: /* unpcklpd */
6388 case 0x0f15: /* unpckhps */
6389 case 0x660f15: /* unpckhpd */
6390 case 0x0f16: /* movhps */
6391 case 0x660f16: /* movhpd */
6392 case 0xf30f16: /* movshdup */
6393 case 0x0f28: /* movaps */
6394 case 0x660f28: /* movapd */
6395 case 0x0f2a: /* cvtpi2ps */
6396 case 0x660f2a: /* cvtpi2pd */
6397 case 0xf30f2a: /* cvtsi2ss */
6398 case 0xf20f2a: /* cvtsi2sd */
6399 case 0x0f2c: /* cvttps2pi */
6400 case 0x660f2c: /* cvttpd2pi */
6401 case 0x0f2d: /* cvtps2pi */
6402 case 0x660f2d: /* cvtpd2pi */
6403 case 0x660f3800: /* pshufb */
6404 case 0x660f3801: /* phaddw */
6405 case 0x660f3802: /* phaddd */
6406 case 0x660f3803: /* phaddsw */
6407 case 0x660f3804: /* pmaddubsw */
6408 case 0x660f3805: /* phsubw */
6409 case 0x660f3806: /* phsubd */
6410 case 0x660f3807: /* phsubsw */
6411 case 0x660f3808: /* psignb */
6412 case 0x660f3809: /* psignw */
6413 case 0x660f380a: /* psignd */
6414 case 0x660f380b: /* pmulhrsw */
6415 case 0x660f3810: /* pblendvb */
6416 case 0x660f3814: /* blendvps */
6417 case 0x660f3815: /* blendvpd */
6418 case 0x660f381c: /* pabsb */
6419 case 0x660f381d: /* pabsw */
6420 case 0x660f381e: /* pabsd */
6421 case 0x660f3820: /* pmovsxbw */
6422 case 0x660f3821: /* pmovsxbd */
6423 case 0x660f3822: /* pmovsxbq */
6424 case 0x660f3823: /* pmovsxwd */
6425 case 0x660f3824: /* pmovsxwq */
6426 case 0x660f3825: /* pmovsxdq */
6427 case 0x660f3828: /* pmuldq */
6428 case 0x660f3829: /* pcmpeqq */
6429 case 0x660f382a: /* movntdqa */
6430 case 0x660f3a08: /* roundps */
6431 case 0x660f3a09: /* roundpd */
6432 case 0x660f3a0a: /* roundss */
6433 case 0x660f3a0b: /* roundsd */
6434 case 0x660f3a0c: /* blendps */
6435 case 0x660f3a0d: /* blendpd */
6436 case 0x660f3a0e: /* pblendw */
6437 case 0x660f3a0f: /* palignr */
6438 case 0x660f3a20: /* pinsrb */
6439 case 0x660f3a21: /* insertps */
6440 case 0x660f3a22: /* pinsrd pinsrq */
6441 case 0x660f3a40: /* dpps */
6442 case 0x660f3a41: /* dppd */
6443 case 0x660f3a42: /* mpsadbw */
6444 case 0x660f3a60: /* pcmpestrm */
6445 case 0x660f3a61: /* pcmpestri */
6446 case 0x660f3a62: /* pcmpistrm */
6447 case 0x660f3a63: /* pcmpistri */
6448 case 0x0f51: /* sqrtps */
6449 case 0x660f51: /* sqrtpd */
6450 case 0xf20f51: /* sqrtsd */
6451 case 0xf30f51: /* sqrtss */
6452 case 0x0f52: /* rsqrtps */
6453 case 0xf30f52: /* rsqrtss */
6454 case 0x0f53: /* rcpps */
6455 case 0xf30f53: /* rcpss */
6456 case 0x0f54: /* andps */
6457 case 0x660f54: /* andpd */
6458 case 0x0f55: /* andnps */
6459 case 0x660f55: /* andnpd */
6460 case 0x0f56: /* orps */
6461 case 0x660f56: /* orpd */
6462 case 0x0f57: /* xorps */
6463 case 0x660f57: /* xorpd */
6464 case 0x0f58: /* addps */
6465 case 0x660f58: /* addpd */
6466 case 0xf20f58: /* addsd */
6467 case 0xf30f58: /* addss */
6468 case 0x0f59: /* mulps */
6469 case 0x660f59: /* mulpd */
6470 case 0xf20f59: /* mulsd */
6471 case 0xf30f59: /* mulss */
6472 case 0x0f5a: /* cvtps2pd */
6473 case 0x660f5a: /* cvtpd2ps */
6474 case 0xf20f5a: /* cvtsd2ss */
6475 case 0xf30f5a: /* cvtss2sd */
6476 case 0x0f5b: /* cvtdq2ps */
6477 case 0x660f5b: /* cvtps2dq */
6478 case 0xf30f5b: /* cvttps2dq */
6479 case 0x0f5c: /* subps */
6480 case 0x660f5c: /* subpd */
6481 case 0xf20f5c: /* subsd */
6482 case 0xf30f5c: /* subss */
6483 case 0x0f5d: /* minps */
6484 case 0x660f5d: /* minpd */
6485 case 0xf20f5d: /* minsd */
6486 case 0xf30f5d: /* minss */
6487 case 0x0f5e: /* divps */
6488 case 0x660f5e: /* divpd */
6489 case 0xf20f5e: /* divsd */
6490 case 0xf30f5e: /* divss */
6491 case 0x0f5f: /* maxps */
6492 case 0x660f5f: /* maxpd */
6493 case 0xf20f5f: /* maxsd */
6494 case 0xf30f5f: /* maxss */
6495 case 0x660f60: /* punpcklbw */
6496 case 0x660f61: /* punpcklwd */
6497 case 0x660f62: /* punpckldq */
6498 case 0x660f63: /* packsswb */
6499 case 0x660f64: /* pcmpgtb */
6500 case 0x660f65: /* pcmpgtw */
6501 case 0x660f66: /* pcmpgtd */
6502 case 0x660f67: /* packuswb */
6503 case 0x660f68: /* punpckhbw */
6504 case 0x660f69: /* punpckhwd */
6505 case 0x660f6a: /* punpckhdq */
6506 case 0x660f6b: /* packssdw */
6507 case 0x660f6c: /* punpcklqdq */
6508 case 0x660f6d: /* punpckhqdq */
6509 case 0x660f6e: /* movd */
6510 case 0x660f6f: /* movdqa */
6511 case 0xf30f6f: /* movdqu */
6512 case 0x660f70: /* pshufd */
6513 case 0xf20f70: /* pshuflw */
6514 case 0xf30f70: /* pshufhw */
6515 case 0x660f74: /* pcmpeqb */
6516 case 0x660f75: /* pcmpeqw */
6517 case 0x660f76: /* pcmpeqd */
6518 case 0x660f7c: /* haddpd */
6519 case 0xf20f7c: /* haddps */
6520 case 0x660f7d: /* hsubpd */
6521 case 0xf20f7d: /* hsubps */
6522 case 0xf30f7e: /* movq */
6523 case 0x0fc2: /* cmpps */
6524 case 0x660fc2: /* cmppd */
6525 case 0xf20fc2: /* cmpsd */
6526 case 0xf30fc2: /* cmpss */
6527 case 0x660fc4: /* pinsrw */
6528 case 0x0fc6: /* shufps */
6529 case 0x660fc6: /* shufpd */
6530 case 0x660fd0: /* addsubpd */
6531 case 0xf20fd0: /* addsubps */
6532 case 0x660fd1: /* psrlw */
6533 case 0x660fd2: /* psrld */
6534 case 0x660fd3: /* psrlq */
6535 case 0x660fd4: /* paddq */
6536 case 0x660fd5: /* pmullw */
6537 case 0xf30fd6: /* movq2dq */
6538 case 0x660fd8: /* psubusb */
6539 case 0x660fd9: /* psubusw */
6540 case 0x660fda: /* pminub */
6541 case 0x660fdb: /* pand */
6542 case 0x660fdc: /* paddusb */
6543 case 0x660fdd: /* paddusw */
6544 case 0x660fde: /* pmaxub */
6545 case 0x660fdf: /* pandn */
6546 case 0x660fe0: /* pavgb */
6547 case 0x660fe1: /* psraw */
6548 case 0x660fe2: /* psrad */
6549 case 0x660fe3: /* pavgw */
6550 case 0x660fe4: /* pmulhuw */
6551 case 0x660fe5: /* pmulhw */
6552 case 0x660fe6: /* cvttpd2dq */
6553 case 0xf20fe6: /* cvtpd2dq */
6554 case 0xf30fe6: /* cvtdq2pd */
6555 case 0x660fe8: /* psubsb */
6556 case 0x660fe9: /* psubsw */
6557 case 0x660fea: /* pminsw */
6558 case 0x660feb: /* por */
6559 case 0x660fec: /* paddsb */
6560 case 0x660fed: /* paddsw */
6561 case 0x660fee: /* pmaxsw */
6562 case 0x660fef: /* pxor */
6563 case 0xf20ff0: /* lddqu */
6564 case 0x660ff1: /* psllw */
6565 case 0x660ff2: /* pslld */
6566 case 0x660ff3: /* psllq */
6567 case 0x660ff4: /* pmuludq */
6568 case 0x660ff5: /* pmaddwd */
6569 case 0x660ff6: /* psadbw */
6570 case 0x660ff8: /* psubb */
6571 case 0x660ff9: /* psubw */
6572 case 0x660ffa: /* psubd */
6573 case 0x660ffb: /* psubq */
6574 case 0x660ffc: /* paddb */
6575 case 0x660ffd: /* paddw */
6576 case 0x660ffe: /* paddd */
6577 if (i386_record_modrm (&ir
))
6580 if (!i386_xmm_regnum_p (gdbarch
, I387_XMM0_REGNUM (tdep
) + ir
.reg
))
6582 record_arch_list_add_reg (ir
.regcache
,
6583 I387_XMM0_REGNUM (tdep
) + ir
.reg
);
6584 if ((opcode
& 0xfffffffc) == 0x660f3a60)
6585 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6588 case 0x0f11: /* movups */
6589 case 0x660f11: /* movupd */
6590 case 0xf30f11: /* movss */
6591 case 0xf20f11: /* movsd */
6592 case 0x0f13: /* movlps */
6593 case 0x660f13: /* movlpd */
6594 case 0x0f17: /* movhps */
6595 case 0x660f17: /* movhpd */
6596 case 0x0f29: /* movaps */
6597 case 0x660f29: /* movapd */
6598 case 0x660f3a14: /* pextrb */
6599 case 0x660f3a15: /* pextrw */
6600 case 0x660f3a16: /* pextrd pextrq */
6601 case 0x660f3a17: /* extractps */
6602 case 0x660f7f: /* movdqa */
6603 case 0xf30f7f: /* movdqu */
6604 if (i386_record_modrm (&ir
))
6608 if (opcode
== 0x0f13 || opcode
== 0x660f13
6609 || opcode
== 0x0f17 || opcode
== 0x660f17)
6612 if (!i386_xmm_regnum_p (gdbarch
,
6613 I387_XMM0_REGNUM (tdep
) + ir
.rm
))
6615 record_arch_list_add_reg (ir
.regcache
,
6616 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
6638 if (i386_record_lea_modrm (&ir
))
6643 case 0x0f2b: /* movntps */
6644 case 0x660f2b: /* movntpd */
6645 case 0x0fe7: /* movntq */
6646 case 0x660fe7: /* movntdq */
6649 if (opcode
== 0x0fe7)
6653 if (i386_record_lea_modrm (&ir
))
6657 case 0xf30f2c: /* cvttss2si */
6658 case 0xf20f2c: /* cvttsd2si */
6659 case 0xf30f2d: /* cvtss2si */
6660 case 0xf20f2d: /* cvtsd2si */
6661 case 0xf20f38f0: /* crc32 */
6662 case 0xf20f38f1: /* crc32 */
6663 case 0x0f50: /* movmskps */
6664 case 0x660f50: /* movmskpd */
6665 case 0x0fc5: /* pextrw */
6666 case 0x660fc5: /* pextrw */
6667 case 0x0fd7: /* pmovmskb */
6668 case 0x660fd7: /* pmovmskb */
6669 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
6672 case 0x0f3800: /* pshufb */
6673 case 0x0f3801: /* phaddw */
6674 case 0x0f3802: /* phaddd */
6675 case 0x0f3803: /* phaddsw */
6676 case 0x0f3804: /* pmaddubsw */
6677 case 0x0f3805: /* phsubw */
6678 case 0x0f3806: /* phsubd */
6679 case 0x0f3807: /* phsubsw */
6680 case 0x0f3808: /* psignb */
6681 case 0x0f3809: /* psignw */
6682 case 0x0f380a: /* psignd */
6683 case 0x0f380b: /* pmulhrsw */
6684 case 0x0f381c: /* pabsb */
6685 case 0x0f381d: /* pabsw */
6686 case 0x0f381e: /* pabsd */
6687 case 0x0f382b: /* packusdw */
6688 case 0x0f3830: /* pmovzxbw */
6689 case 0x0f3831: /* pmovzxbd */
6690 case 0x0f3832: /* pmovzxbq */
6691 case 0x0f3833: /* pmovzxwd */
6692 case 0x0f3834: /* pmovzxwq */
6693 case 0x0f3835: /* pmovzxdq */
6694 case 0x0f3837: /* pcmpgtq */
6695 case 0x0f3838: /* pminsb */
6696 case 0x0f3839: /* pminsd */
6697 case 0x0f383a: /* pminuw */
6698 case 0x0f383b: /* pminud */
6699 case 0x0f383c: /* pmaxsb */
6700 case 0x0f383d: /* pmaxsd */
6701 case 0x0f383e: /* pmaxuw */
6702 case 0x0f383f: /* pmaxud */
6703 case 0x0f3840: /* pmulld */
6704 case 0x0f3841: /* phminposuw */
6705 case 0x0f3a0f: /* palignr */
6706 case 0x0f60: /* punpcklbw */
6707 case 0x0f61: /* punpcklwd */
6708 case 0x0f62: /* punpckldq */
6709 case 0x0f63: /* packsswb */
6710 case 0x0f64: /* pcmpgtb */
6711 case 0x0f65: /* pcmpgtw */
6712 case 0x0f66: /* pcmpgtd */
6713 case 0x0f67: /* packuswb */
6714 case 0x0f68: /* punpckhbw */
6715 case 0x0f69: /* punpckhwd */
6716 case 0x0f6a: /* punpckhdq */
6717 case 0x0f6b: /* packssdw */
6718 case 0x0f6e: /* movd */
6719 case 0x0f6f: /* movq */
6720 case 0x0f70: /* pshufw */
6721 case 0x0f74: /* pcmpeqb */
6722 case 0x0f75: /* pcmpeqw */
6723 case 0x0f76: /* pcmpeqd */
6724 case 0x0fc4: /* pinsrw */
6725 case 0x0fd1: /* psrlw */
6726 case 0x0fd2: /* psrld */
6727 case 0x0fd3: /* psrlq */
6728 case 0x0fd4: /* paddq */
6729 case 0x0fd5: /* pmullw */
6730 case 0xf20fd6: /* movdq2q */
6731 case 0x0fd8: /* psubusb */
6732 case 0x0fd9: /* psubusw */
6733 case 0x0fda: /* pminub */
6734 case 0x0fdb: /* pand */
6735 case 0x0fdc: /* paddusb */
6736 case 0x0fdd: /* paddusw */
6737 case 0x0fde: /* pmaxub */
6738 case 0x0fdf: /* pandn */
6739 case 0x0fe0: /* pavgb */
6740 case 0x0fe1: /* psraw */
6741 case 0x0fe2: /* psrad */
6742 case 0x0fe3: /* pavgw */
6743 case 0x0fe4: /* pmulhuw */
6744 case 0x0fe5: /* pmulhw */
6745 case 0x0fe8: /* psubsb */
6746 case 0x0fe9: /* psubsw */
6747 case 0x0fea: /* pminsw */
6748 case 0x0feb: /* por */
6749 case 0x0fec: /* paddsb */
6750 case 0x0fed: /* paddsw */
6751 case 0x0fee: /* pmaxsw */
6752 case 0x0fef: /* pxor */
6753 case 0x0ff1: /* psllw */
6754 case 0x0ff2: /* pslld */
6755 case 0x0ff3: /* psllq */
6756 case 0x0ff4: /* pmuludq */
6757 case 0x0ff5: /* pmaddwd */
6758 case 0x0ff6: /* psadbw */
6759 case 0x0ff8: /* psubb */
6760 case 0x0ff9: /* psubw */
6761 case 0x0ffa: /* psubd */
6762 case 0x0ffb: /* psubq */
6763 case 0x0ffc: /* paddb */
6764 case 0x0ffd: /* paddw */
6765 case 0x0ffe: /* paddd */
6766 if (i386_record_modrm (&ir
))
6768 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.reg
))
6770 record_arch_list_add_reg (ir
.regcache
,
6771 I387_MM0_REGNUM (tdep
) + ir
.reg
);
6774 case 0x0f71: /* psllw */
6775 case 0x0f72: /* pslld */
6776 case 0x0f73: /* psllq */
6777 if (i386_record_modrm (&ir
))
6779 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.rm
))
6781 record_arch_list_add_reg (ir
.regcache
,
6782 I387_MM0_REGNUM (tdep
) + ir
.rm
);
6785 case 0x660f71: /* psllw */
6786 case 0x660f72: /* pslld */
6787 case 0x660f73: /* psllq */
6788 if (i386_record_modrm (&ir
))
6791 if (!i386_xmm_regnum_p (gdbarch
, I387_XMM0_REGNUM (tdep
) + ir
.rm
))
6793 record_arch_list_add_reg (ir
.regcache
,
6794 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
6797 case 0x0f7e: /* movd */
6798 case 0x660f7e: /* movd */
6799 if (i386_record_modrm (&ir
))
6802 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6809 if (i386_record_lea_modrm (&ir
))
6814 case 0x0f7f: /* movq */
6815 if (i386_record_modrm (&ir
))
6819 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.rm
))
6821 record_arch_list_add_reg (ir
.regcache
,
6822 I387_MM0_REGNUM (tdep
) + ir
.rm
);
6827 if (i386_record_lea_modrm (&ir
))
6832 case 0xf30fb8: /* popcnt */
6833 if (i386_record_modrm (&ir
))
6835 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
6836 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6839 case 0x660fd6: /* movq */
6840 if (i386_record_modrm (&ir
))
6845 if (!i386_xmm_regnum_p (gdbarch
,
6846 I387_XMM0_REGNUM (tdep
) + ir
.rm
))
6848 record_arch_list_add_reg (ir
.regcache
,
6849 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
6854 if (i386_record_lea_modrm (&ir
))
6859 case 0x660f3817: /* ptest */
6860 case 0x0f2e: /* ucomiss */
6861 case 0x660f2e: /* ucomisd */
6862 case 0x0f2f: /* comiss */
6863 case 0x660f2f: /* comisd */
6864 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6867 case 0x0ff7: /* maskmovq */
6868 regcache_raw_read_unsigned (ir
.regcache
,
6869 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
6871 if (record_arch_list_add_mem (addr
, 64))
6875 case 0x660ff7: /* maskmovdqu */
6876 regcache_raw_read_unsigned (ir
.regcache
,
6877 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
6879 if (record_arch_list_add_mem (addr
, 128))
6894 /* In the future, maybe still need to deal with need_dasm. */
6895 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM
);
6896 if (record_arch_list_add_end ())
6902 printf_unfiltered (_("Process record does not support instruction 0x%02x "
6903 "at address %s.\n"),
6904 (unsigned int) (opcode
),
6905 paddress (gdbarch
, ir
.orig_addr
));
6909 static const int i386_record_regmap
[] =
6911 I386_EAX_REGNUM
, I386_ECX_REGNUM
, I386_EDX_REGNUM
, I386_EBX_REGNUM
,
6912 I386_ESP_REGNUM
, I386_EBP_REGNUM
, I386_ESI_REGNUM
, I386_EDI_REGNUM
,
6913 0, 0, 0, 0, 0, 0, 0, 0,
6914 I386_EIP_REGNUM
, I386_EFLAGS_REGNUM
, I386_CS_REGNUM
, I386_SS_REGNUM
,
6915 I386_DS_REGNUM
, I386_ES_REGNUM
, I386_FS_REGNUM
, I386_GS_REGNUM
6918 /* Check that the given address appears suitable for a fast
6919 tracepoint, which on x86 means that we need an instruction of at
6920 least 5 bytes, so that we can overwrite it with a 4-byte-offset
6921 jump and not have to worry about program jumps to an address in the
6922 middle of the tracepoint jump. Returns 1 if OK, and writes a size
6923 of instruction to replace, and 0 if not, plus an explanatory
6927 i386_fast_tracepoint_valid_at (struct gdbarch
*gdbarch
,
6928 CORE_ADDR addr
, int *isize
, char **msg
)
6931 static struct ui_file
*gdb_null
= NULL
;
6933 /* This is based on the target agent using a 4-byte relative jump.
6934 Alternate future possibilities include 8-byte offset for x86-84,
6935 or 3-byte jumps if the program has trampoline space close by. */
6938 /* Dummy file descriptor for the disassembler. */
6940 gdb_null
= ui_file_new ();
6942 /* Check for fit. */
6943 len
= gdb_print_insn (gdbarch
, addr
, gdb_null
, NULL
);
6946 /* Return a bit of target-specific detail to add to the caller's
6947 generic failure message. */
6949 *msg
= xstrprintf (_("; instruction is only %d bytes long, "
6950 "need at least %d bytes for the jump"),
6963 i386_validate_tdesc_p (struct gdbarch_tdep
*tdep
,
6964 struct tdesc_arch_data
*tdesc_data
)
6966 const struct target_desc
*tdesc
= tdep
->tdesc
;
6967 const struct tdesc_feature
*feature_core
;
6968 const struct tdesc_feature
*feature_sse
, *feature_avx
;
6969 int i
, num_regs
, valid_p
;
6971 if (! tdesc_has_registers (tdesc
))
6974 /* Get core registers. */
6975 feature_core
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.core");
6976 if (feature_core
== NULL
)
6979 /* Get SSE registers. */
6980 feature_sse
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.sse");
6982 /* Try AVX registers. */
6983 feature_avx
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx");
6987 /* The XCR0 bits. */
6990 /* AVX register description requires SSE register description. */
6994 tdep
->xcr0
= I386_XSTATE_AVX_MASK
;
6996 /* It may have been set by OSABI initialization function. */
6997 if (tdep
->num_ymm_regs
== 0)
6999 tdep
->ymmh_register_names
= i386_ymmh_names
;
7000 tdep
->num_ymm_regs
= 8;
7001 tdep
->ymm0h_regnum
= I386_YMM0H_REGNUM
;
7004 for (i
= 0; i
< tdep
->num_ymm_regs
; i
++)
7005 valid_p
&= tdesc_numbered_register (feature_avx
, tdesc_data
,
7006 tdep
->ymm0h_regnum
+ i
,
7007 tdep
->ymmh_register_names
[i
]);
7009 else if (feature_sse
)
7010 tdep
->xcr0
= I386_XSTATE_SSE_MASK
;
7013 tdep
->xcr0
= I386_XSTATE_X87_MASK
;
7014 tdep
->num_xmm_regs
= 0;
7017 num_regs
= tdep
->num_core_regs
;
7018 for (i
= 0; i
< num_regs
; i
++)
7019 valid_p
&= tdesc_numbered_register (feature_core
, tdesc_data
, i
,
7020 tdep
->register_names
[i
]);
7024 /* Need to include %mxcsr, so add one. */
7025 num_regs
+= tdep
->num_xmm_regs
+ 1;
7026 for (; i
< num_regs
; i
++)
7027 valid_p
&= tdesc_numbered_register (feature_sse
, tdesc_data
, i
,
7028 tdep
->register_names
[i
]);
7035 static struct gdbarch
*
7036 i386_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
7038 struct gdbarch_tdep
*tdep
;
7039 struct gdbarch
*gdbarch
;
7040 struct tdesc_arch_data
*tdesc_data
;
7041 const struct target_desc
*tdesc
;
7045 /* If there is already a candidate, use it. */
7046 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
7048 return arches
->gdbarch
;
7050 /* Allocate space for the new architecture. */
7051 tdep
= XCALLOC (1, struct gdbarch_tdep
);
7052 gdbarch
= gdbarch_alloc (&info
, tdep
);
7054 /* General-purpose registers. */
7055 tdep
->gregset
= NULL
;
7056 tdep
->gregset_reg_offset
= NULL
;
7057 tdep
->gregset_num_regs
= I386_NUM_GREGS
;
7058 tdep
->sizeof_gregset
= 0;
7060 /* Floating-point registers. */
7061 tdep
->fpregset
= NULL
;
7062 tdep
->sizeof_fpregset
= I387_SIZEOF_FSAVE
;
7064 tdep
->xstateregset
= NULL
;
7066 /* The default settings include the FPU registers, the MMX registers
7067 and the SSE registers. This can be overridden for a specific ABI
7068 by adjusting the members `st0_regnum', `mm0_regnum' and
7069 `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers
7070 will show up in the output of "info all-registers". */
7072 tdep
->st0_regnum
= I386_ST0_REGNUM
;
7074 /* I386_NUM_XREGS includes %mxcsr, so substract one. */
7075 tdep
->num_xmm_regs
= I386_NUM_XREGS
- 1;
7077 tdep
->jb_pc_offset
= -1;
7078 tdep
->struct_return
= pcc_struct_return
;
7079 tdep
->sigtramp_start
= 0;
7080 tdep
->sigtramp_end
= 0;
7081 tdep
->sigtramp_p
= i386_sigtramp_p
;
7082 tdep
->sigcontext_addr
= NULL
;
7083 tdep
->sc_reg_offset
= NULL
;
7084 tdep
->sc_pc_offset
= -1;
7085 tdep
->sc_sp_offset
= -1;
7087 tdep
->xsave_xcr0_offset
= -1;
7089 tdep
->record_regmap
= i386_record_regmap
;
7091 /* The format used for `long double' on almost all i386 targets is
7092 the i387 extended floating-point format. In fact, of all targets
7093 in the GCC 2.95 tree, only OSF/1 does it different, and insists
7094 on having a `long double' that's not `long' at all. */
7095 set_gdbarch_long_double_format (gdbarch
, floatformats_i387_ext
);
7097 /* Although the i387 extended floating-point has only 80 significant
7098 bits, a `long double' actually takes up 96, probably to enforce
7100 set_gdbarch_long_double_bit (gdbarch
, 96);
7102 /* Register numbers of various important registers. */
7103 set_gdbarch_sp_regnum (gdbarch
, I386_ESP_REGNUM
); /* %esp */
7104 set_gdbarch_pc_regnum (gdbarch
, I386_EIP_REGNUM
); /* %eip */
7105 set_gdbarch_ps_regnum (gdbarch
, I386_EFLAGS_REGNUM
); /* %eflags */
7106 set_gdbarch_fp0_regnum (gdbarch
, I386_ST0_REGNUM
); /* %st(0) */
7108 /* NOTE: kettenis/20040418: GCC does have two possible register
7109 numbering schemes on the i386: dbx and SVR4. These schemes
7110 differ in how they number %ebp, %esp, %eflags, and the
7111 floating-point registers, and are implemented by the arrays
7112 dbx_register_map[] and svr4_dbx_register_map in
7113 gcc/config/i386.c. GCC also defines a third numbering scheme in
7114 gcc/config/i386.c, which it designates as the "default" register
7115 map used in 64bit mode. This last register numbering scheme is
7116 implemented in dbx64_register_map, and is used for AMD64; see
7119 Currently, each GCC i386 target always uses the same register
7120 numbering scheme across all its supported debugging formats
7121 i.e. SDB (COFF), stabs and DWARF 2. This is because
7122 gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the
7123 DBX_REGISTER_NUMBER macro which is defined by each target's
7124 respective config header in a manner independent of the requested
7125 output debugging format.
7127 This does not match the arrangement below, which presumes that
7128 the SDB and stabs numbering schemes differ from the DWARF and
7129 DWARF 2 ones. The reason for this arrangement is that it is
7130 likely to get the numbering scheme for the target's
7131 default/native debug format right. For targets where GCC is the
7132 native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for
7133 targets where the native toolchain uses a different numbering
7134 scheme for a particular debug format (stabs-in-ELF on Solaris)
7135 the defaults below will have to be overridden, like
7136 i386_elf_init_abi() does. */
7138 /* Use the dbx register numbering scheme for stabs and COFF. */
7139 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
7140 set_gdbarch_sdb_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
7142 /* Use the SVR4 register numbering scheme for DWARF 2. */
7143 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
7145 /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to
7146 be in use on any of the supported i386 targets. */
7148 set_gdbarch_print_float_info (gdbarch
, i387_print_float_info
);
7150 set_gdbarch_get_longjmp_target (gdbarch
, i386_get_longjmp_target
);
7152 /* Call dummy code. */
7153 set_gdbarch_push_dummy_call (gdbarch
, i386_push_dummy_call
);
7155 set_gdbarch_convert_register_p (gdbarch
, i386_convert_register_p
);
7156 set_gdbarch_register_to_value (gdbarch
, i386_register_to_value
);
7157 set_gdbarch_value_to_register (gdbarch
, i386_value_to_register
);
7159 set_gdbarch_return_value (gdbarch
, i386_return_value
);
7161 set_gdbarch_skip_prologue (gdbarch
, i386_skip_prologue
);
7163 /* Stack grows downward. */
7164 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
7166 set_gdbarch_breakpoint_from_pc (gdbarch
, i386_breakpoint_from_pc
);
7167 set_gdbarch_decr_pc_after_break (gdbarch
, 1);
7168 set_gdbarch_max_insn_length (gdbarch
, I386_MAX_INSN_LEN
);
7170 set_gdbarch_frame_args_skip (gdbarch
, 8);
7172 set_gdbarch_print_insn (gdbarch
, i386_print_insn
);
7174 set_gdbarch_dummy_id (gdbarch
, i386_dummy_id
);
7176 set_gdbarch_unwind_pc (gdbarch
, i386_unwind_pc
);
7178 /* Add the i386 register groups. */
7179 i386_add_reggroups (gdbarch
);
7180 tdep
->register_reggroup_p
= i386_register_reggroup_p
;
7182 /* Helper for function argument information. */
7183 set_gdbarch_fetch_pointer_argument (gdbarch
, i386_fetch_pointer_argument
);
7185 /* Hook the function epilogue frame unwinder. This unwinder is
7186 appended to the list first, so that it supercedes the Dwarf
7187 unwinder in function epilogues (where the Dwarf unwinder
7188 currently fails). */
7189 frame_unwind_append_unwinder (gdbarch
, &i386_epilogue_frame_unwind
);
7191 /* Hook in the DWARF CFI frame unwinder. This unwinder is appended
7192 to the list before the prologue-based unwinders, so that Dwarf
7193 CFI info will be used if it is available. */
7194 dwarf2_append_unwinders (gdbarch
);
7196 frame_base_set_default (gdbarch
, &i386_frame_base
);
7198 /* Pseudo registers may be changed by amd64_init_abi. */
7199 set_gdbarch_pseudo_register_read (gdbarch
, i386_pseudo_register_read
);
7200 set_gdbarch_pseudo_register_write (gdbarch
, i386_pseudo_register_write
);
7202 set_tdesc_pseudo_register_type (gdbarch
, i386_pseudo_register_type
);
7203 set_tdesc_pseudo_register_name (gdbarch
, i386_pseudo_register_name
);
7205 /* Override the normal target description method to make the AVX
7206 upper halves anonymous. */
7207 set_gdbarch_register_name (gdbarch
, i386_register_name
);
7209 /* Even though the default ABI only includes general-purpose registers,
7210 floating-point registers and the SSE registers, we have to leave a
7211 gap for the upper AVX registers. */
7212 set_gdbarch_num_regs (gdbarch
, I386_AVX_NUM_REGS
);
7214 /* Get the x86 target description from INFO. */
7215 tdesc
= info
.target_desc
;
7216 if (! tdesc_has_registers (tdesc
))
7218 tdep
->tdesc
= tdesc
;
7220 tdep
->num_core_regs
= I386_NUM_GREGS
+ I387_NUM_REGS
;
7221 tdep
->register_names
= i386_register_names
;
7223 /* No upper YMM registers. */
7224 tdep
->ymmh_register_names
= NULL
;
7225 tdep
->ymm0h_regnum
= -1;
7227 tdep
->num_byte_regs
= 8;
7228 tdep
->num_word_regs
= 8;
7229 tdep
->num_dword_regs
= 0;
7230 tdep
->num_mmx_regs
= 8;
7231 tdep
->num_ymm_regs
= 0;
7233 tdesc_data
= tdesc_data_alloc ();
7235 set_gdbarch_relocate_instruction (gdbarch
, i386_relocate_instruction
);
7237 /* Hook in ABI-specific overrides, if they have been registered. */
7238 info
.tdep_info
= (void *) tdesc_data
;
7239 gdbarch_init_osabi (info
, gdbarch
);
7241 if (!i386_validate_tdesc_p (tdep
, tdesc_data
))
7243 tdesc_data_cleanup (tdesc_data
);
7245 gdbarch_free (gdbarch
);
7249 /* Wire in pseudo registers. Number of pseudo registers may be
7251 set_gdbarch_num_pseudo_regs (gdbarch
, (tdep
->num_byte_regs
7252 + tdep
->num_word_regs
7253 + tdep
->num_dword_regs
7254 + tdep
->num_mmx_regs
7255 + tdep
->num_ymm_regs
));
7257 /* Target description may be changed. */
7258 tdesc
= tdep
->tdesc
;
7260 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
7262 /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */
7263 set_gdbarch_register_reggroup_p (gdbarch
, tdep
->register_reggroup_p
);
7265 /* Make %al the first pseudo-register. */
7266 tdep
->al_regnum
= gdbarch_num_regs (gdbarch
);
7267 tdep
->ax_regnum
= tdep
->al_regnum
+ tdep
->num_byte_regs
;
7269 ymm0_regnum
= tdep
->ax_regnum
+ tdep
->num_word_regs
;
7270 if (tdep
->num_dword_regs
)
7272 /* Support dword pseudo-register if it hasn't been disabled. */
7273 tdep
->eax_regnum
= ymm0_regnum
;
7274 ymm0_regnum
+= tdep
->num_dword_regs
;
7277 tdep
->eax_regnum
= -1;
7279 mm0_regnum
= ymm0_regnum
;
7280 if (tdep
->num_ymm_regs
)
7282 /* Support YMM pseudo-register if it is available. */
7283 tdep
->ymm0_regnum
= ymm0_regnum
;
7284 mm0_regnum
+= tdep
->num_ymm_regs
;
7287 tdep
->ymm0_regnum
= -1;
7289 if (tdep
->num_mmx_regs
!= 0)
7291 /* Support MMX pseudo-register if MMX hasn't been disabled. */
7292 tdep
->mm0_regnum
= mm0_regnum
;
7295 tdep
->mm0_regnum
= -1;
7297 /* Hook in the legacy prologue-based unwinders last (fallback). */
7298 frame_unwind_append_unwinder (gdbarch
, &i386_sigtramp_frame_unwind
);
7299 frame_unwind_append_unwinder (gdbarch
, &i386_frame_unwind
);
7301 /* If we have a register mapping, enable the generic core file
7302 support, unless it has already been enabled. */
7303 if (tdep
->gregset_reg_offset
7304 && !gdbarch_regset_from_core_section_p (gdbarch
))
7305 set_gdbarch_regset_from_core_section (gdbarch
,
7306 i386_regset_from_core_section
);
7308 set_gdbarch_skip_permanent_breakpoint (gdbarch
,
7309 i386_skip_permanent_breakpoint
);
7311 set_gdbarch_fast_tracepoint_valid_at (gdbarch
,
7312 i386_fast_tracepoint_valid_at
);
7317 static enum gdb_osabi
7318 i386_coff_osabi_sniffer (bfd
*abfd
)
7320 if (strcmp (bfd_get_target (abfd
), "coff-go32-exe") == 0
7321 || strcmp (bfd_get_target (abfd
), "coff-go32") == 0)
7322 return GDB_OSABI_GO32
;
7324 return GDB_OSABI_UNKNOWN
;
7328 /* Provide a prototype to silence -Wmissing-prototypes. */
7329 void _initialize_i386_tdep (void);
7332 _initialize_i386_tdep (void)
7334 register_gdbarch_init (bfd_arch_i386
, i386_gdbarch_init
);
7336 /* Add the variable that controls the disassembly flavor. */
7337 add_setshow_enum_cmd ("disassembly-flavor", no_class
, valid_flavors
,
7338 &disassembly_flavor
, _("\
7339 Set the disassembly flavor."), _("\
7340 Show the disassembly flavor."), _("\
7341 The valid values are \"att\" and \"intel\", and the default value is \"att\"."),
7343 NULL
, /* FIXME: i18n: */
7344 &setlist
, &showlist
);
7346 /* Add the variable that controls the convention for returning
7348 add_setshow_enum_cmd ("struct-convention", no_class
, valid_conventions
,
7349 &struct_convention
, _("\
7350 Set the convention for returning small structs."), _("\
7351 Show the convention for returning small structs."), _("\
7352 Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\
7355 NULL
, /* FIXME: i18n: */
7356 &setlist
, &showlist
);
7358 gdbarch_register_osabi_sniffer (bfd_arch_i386
, bfd_target_coff_flavour
,
7359 i386_coff_osabi_sniffer
);
7361 gdbarch_register_osabi (bfd_arch_i386
, 0, GDB_OSABI_SVR4
,
7362 i386_svr4_init_abi
);
7363 gdbarch_register_osabi (bfd_arch_i386
, 0, GDB_OSABI_GO32
,
7364 i386_go32_init_abi
);
7366 /* Initialize the i386-specific register groups. */
7367 i386_init_reggroups ();
7369 /* Initialize the standard target descriptions. */
7370 initialize_tdesc_i386 ();
7371 initialize_tdesc_i386_mmx ();
7372 initialize_tdesc_i386_avx ();
7374 /* Tell remote stub that we support XML target description. */
7375 register_remote_support_xml ("i386");