1 /* Intel 386 target-dependent stuff.
3 Copyright (C) 1988-2012 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "opcode/i386.h"
22 #include "arch-utils.h"
24 #include "dummy-frame.h"
25 #include "dwarf2-frame.h"
28 #include "frame-base.h"
29 #include "frame-unwind.h"
37 #include "reggroups.h"
46 #include "exceptions.h"
47 #include "gdb_assert.h"
48 #include "gdb_string.h"
50 #include "i386-tdep.h"
51 #include "i387-tdep.h"
52 #include "i386-xstate.h"
57 #include "features/i386/i386.c"
58 #include "features/i386/i386-avx.c"
59 #include "features/i386/i386-mmx.c"
64 #include "stap-probe.h"
65 #include "user-regs.h"
66 #include "cli/cli-utils.h"
67 #include "expression.h"
68 #include "parser-defs.h"
73 static const char *i386_register_names
[] =
75 "eax", "ecx", "edx", "ebx",
76 "esp", "ebp", "esi", "edi",
77 "eip", "eflags", "cs", "ss",
78 "ds", "es", "fs", "gs",
79 "st0", "st1", "st2", "st3",
80 "st4", "st5", "st6", "st7",
81 "fctrl", "fstat", "ftag", "fiseg",
82 "fioff", "foseg", "fooff", "fop",
83 "xmm0", "xmm1", "xmm2", "xmm3",
84 "xmm4", "xmm5", "xmm6", "xmm7",
88 static const char *i386_ymm_names
[] =
90 "ymm0", "ymm1", "ymm2", "ymm3",
91 "ymm4", "ymm5", "ymm6", "ymm7",
94 static const char *i386_ymmh_names
[] =
96 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
97 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
100 /* Register names for MMX pseudo-registers. */
102 static const char *i386_mmx_names
[] =
104 "mm0", "mm1", "mm2", "mm3",
105 "mm4", "mm5", "mm6", "mm7"
108 /* Register names for byte pseudo-registers. */
110 static const char *i386_byte_names
[] =
112 "al", "cl", "dl", "bl",
113 "ah", "ch", "dh", "bh"
116 /* Register names for word pseudo-registers. */
118 static const char *i386_word_names
[] =
120 "ax", "cx", "dx", "bx",
127 i386_mmx_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
129 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
130 int mm0_regnum
= tdep
->mm0_regnum
;
135 regnum
-= mm0_regnum
;
136 return regnum
>= 0 && regnum
< tdep
->num_mmx_regs
;
142 i386_byte_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
144 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
146 regnum
-= tdep
->al_regnum
;
147 return regnum
>= 0 && regnum
< tdep
->num_byte_regs
;
153 i386_word_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
155 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
157 regnum
-= tdep
->ax_regnum
;
158 return regnum
>= 0 && regnum
< tdep
->num_word_regs
;
161 /* Dword register? */
164 i386_dword_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
166 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
167 int eax_regnum
= tdep
->eax_regnum
;
172 regnum
-= eax_regnum
;
173 return regnum
>= 0 && regnum
< tdep
->num_dword_regs
;
177 i386_ymmh_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
179 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
180 int ymm0h_regnum
= tdep
->ymm0h_regnum
;
182 if (ymm0h_regnum
< 0)
185 regnum
-= ymm0h_regnum
;
186 return regnum
>= 0 && regnum
< tdep
->num_ymm_regs
;
192 i386_ymm_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
194 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
195 int ymm0_regnum
= tdep
->ymm0_regnum
;
200 regnum
-= ymm0_regnum
;
201 return regnum
>= 0 && regnum
< tdep
->num_ymm_regs
;
207 i386_xmm_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
209 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
210 int num_xmm_regs
= I387_NUM_XMM_REGS (tdep
);
212 if (num_xmm_regs
== 0)
215 regnum
-= I387_XMM0_REGNUM (tdep
);
216 return regnum
>= 0 && regnum
< num_xmm_regs
;
220 i386_mxcsr_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
222 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
224 if (I387_NUM_XMM_REGS (tdep
) == 0)
227 return (regnum
== I387_MXCSR_REGNUM (tdep
));
233 i386_fp_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
235 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
237 if (I387_ST0_REGNUM (tdep
) < 0)
240 return (I387_ST0_REGNUM (tdep
) <= regnum
241 && regnum
< I387_FCTRL_REGNUM (tdep
));
245 i386_fpc_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
247 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
249 if (I387_ST0_REGNUM (tdep
) < 0)
252 return (I387_FCTRL_REGNUM (tdep
) <= regnum
253 && regnum
< I387_XMM0_REGNUM (tdep
));
256 /* Return the name of register REGNUM, or the empty string if it is
257 an anonymous register. */
260 i386_register_name (struct gdbarch
*gdbarch
, int regnum
)
262 /* Hide the upper YMM registers. */
263 if (i386_ymmh_regnum_p (gdbarch
, regnum
))
266 return tdesc_register_name (gdbarch
, regnum
);
269 /* Return the name of register REGNUM. */
272 i386_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
274 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
275 if (i386_mmx_regnum_p (gdbarch
, regnum
))
276 return i386_mmx_names
[regnum
- I387_MM0_REGNUM (tdep
)];
277 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
278 return i386_ymm_names
[regnum
- tdep
->ymm0_regnum
];
279 else if (i386_byte_regnum_p (gdbarch
, regnum
))
280 return i386_byte_names
[regnum
- tdep
->al_regnum
];
281 else if (i386_word_regnum_p (gdbarch
, regnum
))
282 return i386_word_names
[regnum
- tdep
->ax_regnum
];
284 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
287 /* Convert a dbx register number REG to the appropriate register
288 number used by GDB. */
291 i386_dbx_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
293 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
295 /* This implements what GCC calls the "default" register map
296 (dbx_register_map[]). */
298 if (reg
>= 0 && reg
<= 7)
300 /* General-purpose registers. The debug info calls %ebp
301 register 4, and %esp register 5. */
308 else if (reg
>= 12 && reg
<= 19)
310 /* Floating-point registers. */
311 return reg
- 12 + I387_ST0_REGNUM (tdep
);
313 else if (reg
>= 21 && reg
<= 28)
316 int ymm0_regnum
= tdep
->ymm0_regnum
;
319 && i386_xmm_regnum_p (gdbarch
, reg
))
320 return reg
- 21 + ymm0_regnum
;
322 return reg
- 21 + I387_XMM0_REGNUM (tdep
);
324 else if (reg
>= 29 && reg
<= 36)
327 return reg
- 29 + I387_MM0_REGNUM (tdep
);
330 /* This will hopefully provoke a warning. */
331 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
334 /* Convert SVR4 register number REG to the appropriate register number
338 i386_svr4_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
340 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
342 /* This implements the GCC register map that tries to be compatible
343 with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */
345 /* The SVR4 register numbering includes %eip and %eflags, and
346 numbers the floating point registers differently. */
347 if (reg
>= 0 && reg
<= 9)
349 /* General-purpose registers. */
352 else if (reg
>= 11 && reg
<= 18)
354 /* Floating-point registers. */
355 return reg
- 11 + I387_ST0_REGNUM (tdep
);
357 else if (reg
>= 21 && reg
<= 36)
359 /* The SSE and MMX registers have the same numbers as with dbx. */
360 return i386_dbx_reg_to_regnum (gdbarch
, reg
);
365 case 37: return I387_FCTRL_REGNUM (tdep
);
366 case 38: return I387_FSTAT_REGNUM (tdep
);
367 case 39: return I387_MXCSR_REGNUM (tdep
);
368 case 40: return I386_ES_REGNUM
;
369 case 41: return I386_CS_REGNUM
;
370 case 42: return I386_SS_REGNUM
;
371 case 43: return I386_DS_REGNUM
;
372 case 44: return I386_FS_REGNUM
;
373 case 45: return I386_GS_REGNUM
;
376 /* This will hopefully provoke a warning. */
377 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
382 /* This is the variable that is set with "set disassembly-flavor", and
383 its legitimate values. */
384 static const char att_flavor
[] = "att";
385 static const char intel_flavor
[] = "intel";
386 static const char *const valid_flavors
[] =
392 static const char *disassembly_flavor
= att_flavor
;
395 /* Use the program counter to determine the contents and size of a
396 breakpoint instruction. Return a pointer to a string of bytes that
397 encode a breakpoint instruction, store the length of the string in
398 *LEN and optionally adjust *PC to point to the correct memory
399 location for inserting the breakpoint.
401 On the i386 we have a single breakpoint that fits in a single byte
402 and can be inserted anywhere.
404 This function is 64-bit safe. */
406 static const gdb_byte
*
407 i386_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pc
, int *len
)
409 static gdb_byte break_insn
[] = { 0xcc }; /* int 3 */
411 *len
= sizeof (break_insn
);
415 /* Displaced instruction handling. */
417 /* Skip the legacy instruction prefixes in INSN.
418 Not all prefixes are valid for any particular insn
419 but we needn't care, the insn will fault if it's invalid.
420 The result is a pointer to the first opcode byte,
421 or NULL if we run off the end of the buffer. */
424 i386_skip_prefixes (gdb_byte
*insn
, size_t max_len
)
426 gdb_byte
*end
= insn
+ max_len
;
432 case DATA_PREFIX_OPCODE
:
433 case ADDR_PREFIX_OPCODE
:
434 case CS_PREFIX_OPCODE
:
435 case DS_PREFIX_OPCODE
:
436 case ES_PREFIX_OPCODE
:
437 case FS_PREFIX_OPCODE
:
438 case GS_PREFIX_OPCODE
:
439 case SS_PREFIX_OPCODE
:
440 case LOCK_PREFIX_OPCODE
:
441 case REPE_PREFIX_OPCODE
:
442 case REPNE_PREFIX_OPCODE
:
454 i386_absolute_jmp_p (const gdb_byte
*insn
)
456 /* jmp far (absolute address in operand). */
462 /* jump near, absolute indirect (/4). */
463 if ((insn
[1] & 0x38) == 0x20)
466 /* jump far, absolute indirect (/5). */
467 if ((insn
[1] & 0x38) == 0x28)
475 i386_absolute_call_p (const gdb_byte
*insn
)
477 /* call far, absolute. */
483 /* Call near, absolute indirect (/2). */
484 if ((insn
[1] & 0x38) == 0x10)
487 /* Call far, absolute indirect (/3). */
488 if ((insn
[1] & 0x38) == 0x18)
496 i386_ret_p (const gdb_byte
*insn
)
500 case 0xc2: /* ret near, pop N bytes. */
501 case 0xc3: /* ret near */
502 case 0xca: /* ret far, pop N bytes. */
503 case 0xcb: /* ret far */
504 case 0xcf: /* iret */
513 i386_call_p (const gdb_byte
*insn
)
515 if (i386_absolute_call_p (insn
))
518 /* call near, relative. */
525 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
526 length in bytes. Otherwise, return zero. */
529 i386_syscall_p (const gdb_byte
*insn
, int *lengthp
)
531 /* Is it 'int $0x80'? */
532 if ((insn
[0] == 0xcd && insn
[1] == 0x80)
533 /* Or is it 'sysenter'? */
534 || (insn
[0] == 0x0f && insn
[1] == 0x34)
535 /* Or is it 'syscall'? */
536 || (insn
[0] == 0x0f && insn
[1] == 0x05))
545 /* Some kernels may run one past a syscall insn, so we have to cope.
546 Otherwise this is just simple_displaced_step_copy_insn. */
548 struct displaced_step_closure
*
549 i386_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
550 CORE_ADDR from
, CORE_ADDR to
,
551 struct regcache
*regs
)
553 size_t len
= gdbarch_max_insn_length (gdbarch
);
554 gdb_byte
*buf
= xmalloc (len
);
556 read_memory (from
, buf
, len
);
558 /* GDB may get control back after the insn after the syscall.
559 Presumably this is a kernel bug.
560 If this is a syscall, make sure there's a nop afterwards. */
565 insn
= i386_skip_prefixes (buf
, len
);
566 if (insn
!= NULL
&& i386_syscall_p (insn
, &syscall_length
))
567 insn
[syscall_length
] = NOP_OPCODE
;
570 write_memory (to
, buf
, len
);
574 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
575 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
576 displaced_step_dump_bytes (gdb_stdlog
, buf
, len
);
579 return (struct displaced_step_closure
*) buf
;
582 /* Fix up the state of registers and memory after having single-stepped
583 a displaced instruction. */
586 i386_displaced_step_fixup (struct gdbarch
*gdbarch
,
587 struct displaced_step_closure
*closure
,
588 CORE_ADDR from
, CORE_ADDR to
,
589 struct regcache
*regs
)
591 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
593 /* The offset we applied to the instruction's address.
594 This could well be negative (when viewed as a signed 32-bit
595 value), but ULONGEST won't reflect that, so take care when
597 ULONGEST insn_offset
= to
- from
;
599 /* Since we use simple_displaced_step_copy_insn, our closure is a
600 copy of the instruction. */
601 gdb_byte
*insn
= (gdb_byte
*) closure
;
602 /* The start of the insn, needed in case we see some prefixes. */
603 gdb_byte
*insn_start
= insn
;
606 fprintf_unfiltered (gdb_stdlog
,
607 "displaced: fixup (%s, %s), "
608 "insn = 0x%02x 0x%02x ...\n",
609 paddress (gdbarch
, from
), paddress (gdbarch
, to
),
612 /* The list of issues to contend with here is taken from
613 resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20.
614 Yay for Free Software! */
616 /* Relocate the %eip, if necessary. */
618 /* The instruction recognizers we use assume any leading prefixes
619 have been skipped. */
621 /* This is the size of the buffer in closure. */
622 size_t max_insn_len
= gdbarch_max_insn_length (gdbarch
);
623 gdb_byte
*opcode
= i386_skip_prefixes (insn
, max_insn_len
);
624 /* If there are too many prefixes, just ignore the insn.
625 It will fault when run. */
630 /* Except in the case of absolute or indirect jump or call
631 instructions, or a return instruction, the new eip is relative to
632 the displaced instruction; make it relative. Well, signal
633 handler returns don't need relocation either, but we use the
634 value of %eip to recognize those; see below. */
635 if (! i386_absolute_jmp_p (insn
)
636 && ! i386_absolute_call_p (insn
)
637 && ! i386_ret_p (insn
))
642 regcache_cooked_read_unsigned (regs
, I386_EIP_REGNUM
, &orig_eip
);
644 /* A signal trampoline system call changes the %eip, resuming
645 execution of the main program after the signal handler has
646 returned. That makes them like 'return' instructions; we
647 shouldn't relocate %eip.
649 But most system calls don't, and we do need to relocate %eip.
651 Our heuristic for distinguishing these cases: if stepping
652 over the system call instruction left control directly after
653 the instruction, the we relocate --- control almost certainly
654 doesn't belong in the displaced copy. Otherwise, we assume
655 the instruction has put control where it belongs, and leave
656 it unrelocated. Goodness help us if there are PC-relative
658 if (i386_syscall_p (insn
, &insn_len
)
659 && orig_eip
!= to
+ (insn
- insn_start
) + insn_len
660 /* GDB can get control back after the insn after the syscall.
661 Presumably this is a kernel bug.
662 i386_displaced_step_copy_insn ensures its a nop,
663 we add one to the length for it. */
664 && orig_eip
!= to
+ (insn
- insn_start
) + insn_len
+ 1)
667 fprintf_unfiltered (gdb_stdlog
,
668 "displaced: syscall changed %%eip; "
673 ULONGEST eip
= (orig_eip
- insn_offset
) & 0xffffffffUL
;
675 /* If we just stepped over a breakpoint insn, we don't backup
676 the pc on purpose; this is to match behaviour without
679 regcache_cooked_write_unsigned (regs
, I386_EIP_REGNUM
, eip
);
682 fprintf_unfiltered (gdb_stdlog
,
684 "relocated %%eip from %s to %s\n",
685 paddress (gdbarch
, orig_eip
),
686 paddress (gdbarch
, eip
));
690 /* If the instruction was PUSHFL, then the TF bit will be set in the
691 pushed value, and should be cleared. We'll leave this for later,
692 since GDB already messes up the TF flag when stepping over a
695 /* If the instruction was a call, the return address now atop the
696 stack is the address following the copied instruction. We need
697 to make it the address following the original instruction. */
698 if (i386_call_p (insn
))
702 const ULONGEST retaddr_len
= 4;
704 regcache_cooked_read_unsigned (regs
, I386_ESP_REGNUM
, &esp
);
705 retaddr
= read_memory_unsigned_integer (esp
, retaddr_len
, byte_order
);
706 retaddr
= (retaddr
- insn_offset
) & 0xffffffffUL
;
707 write_memory_unsigned_integer (esp
, retaddr_len
, byte_order
, retaddr
);
710 fprintf_unfiltered (gdb_stdlog
,
711 "displaced: relocated return addr at %s to %s\n",
712 paddress (gdbarch
, esp
),
713 paddress (gdbarch
, retaddr
));
718 append_insns (CORE_ADDR
*to
, ULONGEST len
, const gdb_byte
*buf
)
720 target_write_memory (*to
, buf
, len
);
725 i386_relocate_instruction (struct gdbarch
*gdbarch
,
726 CORE_ADDR
*to
, CORE_ADDR oldloc
)
728 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
729 gdb_byte buf
[I386_MAX_INSN_LEN
];
730 int offset
= 0, rel32
, newrel
;
732 gdb_byte
*insn
= buf
;
734 read_memory (oldloc
, buf
, I386_MAX_INSN_LEN
);
736 insn_length
= gdb_buffered_insn_length (gdbarch
, insn
,
737 I386_MAX_INSN_LEN
, oldloc
);
739 /* Get past the prefixes. */
740 insn
= i386_skip_prefixes (insn
, I386_MAX_INSN_LEN
);
742 /* Adjust calls with 32-bit relative addresses as push/jump, with
743 the address pushed being the location where the original call in
744 the user program would return to. */
747 gdb_byte push_buf
[16];
748 unsigned int ret_addr
;
750 /* Where "ret" in the original code will return to. */
751 ret_addr
= oldloc
+ insn_length
;
752 push_buf
[0] = 0x68; /* pushq $... */
753 memcpy (&push_buf
[1], &ret_addr
, 4);
755 append_insns (to
, 5, push_buf
);
757 /* Convert the relative call to a relative jump. */
760 /* Adjust the destination offset. */
761 rel32
= extract_signed_integer (insn
+ 1, 4, byte_order
);
762 newrel
= (oldloc
- *to
) + rel32
;
763 store_signed_integer (insn
+ 1, 4, byte_order
, newrel
);
766 fprintf_unfiltered (gdb_stdlog
,
767 "Adjusted insn rel32=%s at %s to"
769 hex_string (rel32
), paddress (gdbarch
, oldloc
),
770 hex_string (newrel
), paddress (gdbarch
, *to
));
772 /* Write the adjusted jump into its displaced location. */
773 append_insns (to
, 5, insn
);
777 /* Adjust jumps with 32-bit relative addresses. Calls are already
781 /* Adjust conditional jumps. */
782 else if (insn
[0] == 0x0f && (insn
[1] & 0xf0) == 0x80)
787 rel32
= extract_signed_integer (insn
+ offset
, 4, byte_order
);
788 newrel
= (oldloc
- *to
) + rel32
;
789 store_signed_integer (insn
+ offset
, 4, byte_order
, newrel
);
791 fprintf_unfiltered (gdb_stdlog
,
792 "Adjusted insn rel32=%s at %s to"
794 hex_string (rel32
), paddress (gdbarch
, oldloc
),
795 hex_string (newrel
), paddress (gdbarch
, *to
));
798 /* Write the adjusted instructions into their displaced
800 append_insns (to
, insn_length
, buf
);
804 #ifdef I386_REGNO_TO_SYMMETRY
805 #error "The Sequent Symmetry is no longer supported."
808 /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi
809 and %esp "belong" to the calling function. Therefore these
810 registers should be saved if they're going to be modified. */
812 /* The maximum number of saved registers. This should include all
813 registers mentioned above, and %eip. */
814 #define I386_NUM_SAVED_REGS I386_NUM_GREGS
816 struct i386_frame_cache
824 /* Saved registers. */
825 CORE_ADDR saved_regs
[I386_NUM_SAVED_REGS
];
830 /* Stack space reserved for local variables. */
834 /* Allocate and initialize a frame cache. */
836 static struct i386_frame_cache
*
837 i386_alloc_frame_cache (void)
839 struct i386_frame_cache
*cache
;
842 cache
= FRAME_OBSTACK_ZALLOC (struct i386_frame_cache
);
847 cache
->sp_offset
= -4;
850 /* Saved registers. We initialize these to -1 since zero is a valid
851 offset (that's where %ebp is supposed to be stored). */
852 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
853 cache
->saved_regs
[i
] = -1;
855 cache
->saved_sp_reg
= -1;
856 cache
->pc_in_eax
= 0;
858 /* Frameless until proven otherwise. */
864 /* If the instruction at PC is a jump, return the address of its
865 target. Otherwise, return PC. */
868 i386_follow_jump (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
870 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
875 if (target_read_memory (pc
, &op
, 1))
881 op
= read_memory_unsigned_integer (pc
+ 1, 1, byte_order
);
887 /* Relative jump: if data16 == 0, disp32, else disp16. */
890 delta
= read_memory_integer (pc
+ 2, 2, byte_order
);
892 /* Include the size of the jmp instruction (including the
898 delta
= read_memory_integer (pc
+ 1, 4, byte_order
);
900 /* Include the size of the jmp instruction. */
905 /* Relative jump, disp8 (ignore data16). */
906 delta
= read_memory_integer (pc
+ data16
+ 1, 1, byte_order
);
915 /* Check whether PC points at a prologue for a function returning a
916 structure or union. If so, it updates CACHE and returns the
917 address of the first instruction after the code sequence that
918 removes the "hidden" argument from the stack or CURRENT_PC,
919 whichever is smaller. Otherwise, return PC. */
922 i386_analyze_struct_return (CORE_ADDR pc
, CORE_ADDR current_pc
,
923 struct i386_frame_cache
*cache
)
925 /* Functions that return a structure or union start with:
928 xchgl %eax, (%esp) 0x87 0x04 0x24
929 or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00
931 (the System V compiler puts out the second `xchg' instruction,
932 and the assembler doesn't try to optimize it, so the 'sib' form
933 gets generated). This sequence is used to get the address of the
934 return buffer for a function that returns a structure. */
935 static gdb_byte proto1
[3] = { 0x87, 0x04, 0x24 };
936 static gdb_byte proto2
[4] = { 0x87, 0x44, 0x24, 0x00 };
940 if (current_pc
<= pc
)
943 if (target_read_memory (pc
, &op
, 1))
946 if (op
!= 0x58) /* popl %eax */
949 if (target_read_memory (pc
+ 1, buf
, 4))
952 if (memcmp (buf
, proto1
, 3) != 0 && memcmp (buf
, proto2
, 4) != 0)
955 if (current_pc
== pc
)
957 cache
->sp_offset
+= 4;
961 if (current_pc
== pc
+ 1)
963 cache
->pc_in_eax
= 1;
967 if (buf
[1] == proto1
[1])
974 i386_skip_probe (CORE_ADDR pc
)
976 /* A function may start with
990 if (target_read_memory (pc
, &op
, 1))
993 if (op
== 0x68 || op
== 0x6a)
997 /* Skip past the `pushl' instruction; it has either a one-byte or a
998 four-byte operand, depending on the opcode. */
1004 /* Read the following 8 bytes, which should be `call _probe' (6
1005 bytes) followed by `addl $4,%esp' (2 bytes). */
1006 read_memory (pc
+ delta
, buf
, sizeof (buf
));
1007 if (buf
[0] == 0xe8 && buf
[6] == 0xc4 && buf
[7] == 0x4)
1008 pc
+= delta
+ sizeof (buf
);
1014 /* GCC 4.1 and later, can put code in the prologue to realign the
1015 stack pointer. Check whether PC points to such code, and update
1016 CACHE accordingly. Return the first instruction after the code
1017 sequence or CURRENT_PC, whichever is smaller. If we don't
1018 recognize the code, return PC. */
1021 i386_analyze_stack_align (CORE_ADDR pc
, CORE_ADDR current_pc
,
1022 struct i386_frame_cache
*cache
)
1024 /* There are 2 code sequences to re-align stack before the frame
1027 1. Use a caller-saved saved register:
1033 2. Use a callee-saved saved register:
1040 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
1042 0x83 0xe4 0xf0 andl $-16, %esp
1043 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
1048 int offset
, offset_and
;
1049 static int regnums
[8] = {
1050 I386_EAX_REGNUM
, /* %eax */
1051 I386_ECX_REGNUM
, /* %ecx */
1052 I386_EDX_REGNUM
, /* %edx */
1053 I386_EBX_REGNUM
, /* %ebx */
1054 I386_ESP_REGNUM
, /* %esp */
1055 I386_EBP_REGNUM
, /* %ebp */
1056 I386_ESI_REGNUM
, /* %esi */
1057 I386_EDI_REGNUM
/* %edi */
1060 if (target_read_memory (pc
, buf
, sizeof buf
))
1063 /* Check caller-saved saved register. The first instruction has
1064 to be "leal 4(%esp), %reg". */
1065 if (buf
[0] == 0x8d && buf
[2] == 0x24 && buf
[3] == 0x4)
1067 /* MOD must be binary 10 and R/M must be binary 100. */
1068 if ((buf
[1] & 0xc7) != 0x44)
1071 /* REG has register number. */
1072 reg
= (buf
[1] >> 3) & 7;
1077 /* Check callee-saved saved register. The first instruction
1078 has to be "pushl %reg". */
1079 if ((buf
[0] & 0xf8) != 0x50)
1085 /* The next instruction has to be "leal 8(%esp), %reg". */
1086 if (buf
[1] != 0x8d || buf
[3] != 0x24 || buf
[4] != 0x8)
1089 /* MOD must be binary 10 and R/M must be binary 100. */
1090 if ((buf
[2] & 0xc7) != 0x44)
1093 /* REG has register number. Registers in pushl and leal have to
1095 if (reg
!= ((buf
[2] >> 3) & 7))
1101 /* Rigister can't be %esp nor %ebp. */
1102 if (reg
== 4 || reg
== 5)
1105 /* The next instruction has to be "andl $-XXX, %esp". */
1106 if (buf
[offset
+ 1] != 0xe4
1107 || (buf
[offset
] != 0x81 && buf
[offset
] != 0x83))
1110 offset_and
= offset
;
1111 offset
+= buf
[offset
] == 0x81 ? 6 : 3;
1113 /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is
1114 0xfc. REG must be binary 110 and MOD must be binary 01. */
1115 if (buf
[offset
] != 0xff
1116 || buf
[offset
+ 2] != 0xfc
1117 || (buf
[offset
+ 1] & 0xf8) != 0x70)
1120 /* R/M has register. Registers in leal and pushl have to be the
1122 if (reg
!= (buf
[offset
+ 1] & 7))
1125 if (current_pc
> pc
+ offset_and
)
1126 cache
->saved_sp_reg
= regnums
[reg
];
1128 return min (pc
+ offset
+ 3, current_pc
);
1131 /* Maximum instruction length we need to handle. */
1132 #define I386_MAX_MATCHED_INSN_LEN 6
1134 /* Instruction description. */
1138 gdb_byte insn
[I386_MAX_MATCHED_INSN_LEN
];
1139 gdb_byte mask
[I386_MAX_MATCHED_INSN_LEN
];
1142 /* Return whether instruction at PC matches PATTERN. */
1145 i386_match_pattern (CORE_ADDR pc
, struct i386_insn pattern
)
1149 if (target_read_memory (pc
, &op
, 1))
1152 if ((op
& pattern
.mask
[0]) == pattern
.insn
[0])
1154 gdb_byte buf
[I386_MAX_MATCHED_INSN_LEN
- 1];
1155 int insn_matched
= 1;
1158 gdb_assert (pattern
.len
> 1);
1159 gdb_assert (pattern
.len
<= I386_MAX_MATCHED_INSN_LEN
);
1161 if (target_read_memory (pc
+ 1, buf
, pattern
.len
- 1))
1164 for (i
= 1; i
< pattern
.len
; i
++)
1166 if ((buf
[i
- 1] & pattern
.mask
[i
]) != pattern
.insn
[i
])
1169 return insn_matched
;
1174 /* Search for the instruction at PC in the list INSN_PATTERNS. Return
1175 the first instruction description that matches. Otherwise, return
1178 static struct i386_insn
*
1179 i386_match_insn (CORE_ADDR pc
, struct i386_insn
*insn_patterns
)
1181 struct i386_insn
*pattern
;
1183 for (pattern
= insn_patterns
; pattern
->len
> 0; pattern
++)
1185 if (i386_match_pattern (pc
, *pattern
))
1192 /* Return whether PC points inside a sequence of instructions that
1193 matches INSN_PATTERNS. */
1196 i386_match_insn_block (CORE_ADDR pc
, struct i386_insn
*insn_patterns
)
1198 CORE_ADDR current_pc
;
1200 struct i386_insn
*insn
;
1202 insn
= i386_match_insn (pc
, insn_patterns
);
1207 ix
= insn
- insn_patterns
;
1208 for (i
= ix
- 1; i
>= 0; i
--)
1210 current_pc
-= insn_patterns
[i
].len
;
1212 if (!i386_match_pattern (current_pc
, insn_patterns
[i
]))
1216 current_pc
= pc
+ insn
->len
;
1217 for (insn
= insn_patterns
+ ix
+ 1; insn
->len
> 0; insn
++)
1219 if (!i386_match_pattern (current_pc
, *insn
))
1222 current_pc
+= insn
->len
;
1228 /* Some special instructions that might be migrated by GCC into the
1229 part of the prologue that sets up the new stack frame. Because the
1230 stack frame hasn't been setup yet, no registers have been saved
1231 yet, and only the scratch registers %eax, %ecx and %edx can be
1234 struct i386_insn i386_frame_setup_skip_insns
[] =
1236 /* Check for `movb imm8, r' and `movl imm32, r'.
1238 ??? Should we handle 16-bit operand-sizes here? */
1240 /* `movb imm8, %al' and `movb imm8, %ah' */
1241 /* `movb imm8, %cl' and `movb imm8, %ch' */
1242 { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } },
1243 /* `movb imm8, %dl' and `movb imm8, %dh' */
1244 { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } },
1245 /* `movl imm32, %eax' and `movl imm32, %ecx' */
1246 { 5, { 0xb8 }, { 0xfe } },
1247 /* `movl imm32, %edx' */
1248 { 5, { 0xba }, { 0xff } },
1250 /* Check for `mov imm32, r32'. Note that there is an alternative
1251 encoding for `mov m32, %eax'.
1253 ??? Should we handle SIB adressing here?
1254 ??? Should we handle 16-bit operand-sizes here? */
1256 /* `movl m32, %eax' */
1257 { 5, { 0xa1 }, { 0xff } },
1258 /* `movl m32, %eax' and `mov; m32, %ecx' */
1259 { 6, { 0x89, 0x05 }, {0xff, 0xf7 } },
1260 /* `movl m32, %edx' */
1261 { 6, { 0x89, 0x15 }, {0xff, 0xff } },
1263 /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'.
1264 Because of the symmetry, there are actually two ways to encode
1265 these instructions; opcode bytes 0x29 and 0x2b for `subl' and
1266 opcode bytes 0x31 and 0x33 for `xorl'. */
1268 /* `subl %eax, %eax' */
1269 { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } },
1270 /* `subl %ecx, %ecx' */
1271 { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } },
1272 /* `subl %edx, %edx' */
1273 { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } },
1274 /* `xorl %eax, %eax' */
1275 { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } },
1276 /* `xorl %ecx, %ecx' */
1277 { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } },
1278 /* `xorl %edx, %edx' */
1279 { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } },
1284 /* Check whether PC points to a no-op instruction. */
1286 i386_skip_noop (CORE_ADDR pc
)
1291 if (target_read_memory (pc
, &op
, 1))
1297 /* Ignore `nop' instruction. */
1301 if (target_read_memory (pc
, &op
, 1))
1305 /* Ignore no-op instruction `mov %edi, %edi'.
1306 Microsoft system dlls often start with
1307 a `mov %edi,%edi' instruction.
1308 The 5 bytes before the function start are
1309 filled with `nop' instructions.
1310 This pattern can be used for hot-patching:
1311 The `mov %edi, %edi' instruction can be replaced by a
1312 near jump to the location of the 5 `nop' instructions
1313 which can be replaced by a 32-bit jump to anywhere
1314 in the 32-bit address space. */
1316 else if (op
== 0x8b)
1318 if (target_read_memory (pc
+ 1, &op
, 1))
1324 if (target_read_memory (pc
, &op
, 1))
1334 /* Check whether PC points at a code that sets up a new stack frame.
1335 If so, it updates CACHE and returns the address of the first
1336 instruction after the sequence that sets up the frame or LIMIT,
1337 whichever is smaller. If we don't recognize the code, return PC. */
1340 i386_analyze_frame_setup (struct gdbarch
*gdbarch
,
1341 CORE_ADDR pc
, CORE_ADDR limit
,
1342 struct i386_frame_cache
*cache
)
1344 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1345 struct i386_insn
*insn
;
1352 if (target_read_memory (pc
, &op
, 1))
1355 if (op
== 0x55) /* pushl %ebp */
1357 /* Take into account that we've executed the `pushl %ebp' that
1358 starts this instruction sequence. */
1359 cache
->saved_regs
[I386_EBP_REGNUM
] = 0;
1360 cache
->sp_offset
+= 4;
1363 /* If that's all, return now. */
1367 /* Check for some special instructions that might be migrated by
1368 GCC into the prologue and skip them. At this point in the
1369 prologue, code should only touch the scratch registers %eax,
1370 %ecx and %edx, so while the number of posibilities is sheer,
1373 Make sure we only skip these instructions if we later see the
1374 `movl %esp, %ebp' that actually sets up the frame. */
1375 while (pc
+ skip
< limit
)
1377 insn
= i386_match_insn (pc
+ skip
, i386_frame_setup_skip_insns
);
1384 /* If that's all, return now. */
1385 if (limit
<= pc
+ skip
)
1388 if (target_read_memory (pc
+ skip
, &op
, 1))
1391 /* Check for `movl %esp, %ebp' -- can be written in two ways. */
1395 if (read_memory_unsigned_integer (pc
+ skip
+ 1, 1, byte_order
)
1400 if (read_memory_unsigned_integer (pc
+ skip
+ 1, 1, byte_order
)
1408 /* OK, we actually have a frame. We just don't know how large
1409 it is yet. Set its size to zero. We'll adjust it if
1410 necessary. We also now commit to skipping the special
1411 instructions mentioned before. */
1415 /* If that's all, return now. */
1419 /* Check for stack adjustment
1423 NOTE: You can't subtract a 16-bit immediate from a 32-bit
1424 reg, so we don't have to worry about a data16 prefix. */
1425 if (target_read_memory (pc
, &op
, 1))
1429 /* `subl' with 8-bit immediate. */
1430 if (read_memory_unsigned_integer (pc
+ 1, 1, byte_order
) != 0xec)
1431 /* Some instruction starting with 0x83 other than `subl'. */
1434 /* `subl' with signed 8-bit immediate (though it wouldn't
1435 make sense to be negative). */
1436 cache
->locals
= read_memory_integer (pc
+ 2, 1, byte_order
);
1439 else if (op
== 0x81)
1441 /* Maybe it is `subl' with a 32-bit immediate. */
1442 if (read_memory_unsigned_integer (pc
+ 1, 1, byte_order
) != 0xec)
1443 /* Some instruction starting with 0x81 other than `subl'. */
1446 /* It is `subl' with a 32-bit immediate. */
1447 cache
->locals
= read_memory_integer (pc
+ 2, 4, byte_order
);
1452 /* Some instruction other than `subl'. */
1456 else if (op
== 0xc8) /* enter */
1458 cache
->locals
= read_memory_unsigned_integer (pc
+ 1, 2, byte_order
);
1465 /* Check whether PC points at code that saves registers on the stack.
1466 If so, it updates CACHE and returns the address of the first
1467 instruction after the register saves or CURRENT_PC, whichever is
1468 smaller. Otherwise, return PC. */
1471 i386_analyze_register_saves (CORE_ADDR pc
, CORE_ADDR current_pc
,
1472 struct i386_frame_cache
*cache
)
1474 CORE_ADDR offset
= 0;
1478 if (cache
->locals
> 0)
1479 offset
-= cache
->locals
;
1480 for (i
= 0; i
< 8 && pc
< current_pc
; i
++)
1482 if (target_read_memory (pc
, &op
, 1))
1484 if (op
< 0x50 || op
> 0x57)
1488 cache
->saved_regs
[op
- 0x50] = offset
;
1489 cache
->sp_offset
+= 4;
1496 /* Do a full analysis of the prologue at PC and update CACHE
1497 accordingly. Bail out early if CURRENT_PC is reached. Return the
1498 address where the analysis stopped.
1500 We handle these cases:
1502 The startup sequence can be at the start of the function, or the
1503 function can start with a branch to startup code at the end.
1505 %ebp can be set up with either the 'enter' instruction, or "pushl
1506 %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was
1507 once used in the System V compiler).
1509 Local space is allocated just below the saved %ebp by either the
1510 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a
1511 16-bit unsigned argument for space to allocate, and the 'addl'
1512 instruction could have either a signed byte, or 32-bit immediate.
1514 Next, the registers used by this function are pushed. With the
1515 System V compiler they will always be in the order: %edi, %esi,
1516 %ebx (and sometimes a harmless bug causes it to also save but not
1517 restore %eax); however, the code below is willing to see the pushes
1518 in any order, and will handle up to 8 of them.
1520 If the setup sequence is at the end of the function, then the next
1521 instruction will be a branch back to the start. */
1524 i386_analyze_prologue (struct gdbarch
*gdbarch
,
1525 CORE_ADDR pc
, CORE_ADDR current_pc
,
1526 struct i386_frame_cache
*cache
)
1528 pc
= i386_skip_noop (pc
);
1529 pc
= i386_follow_jump (gdbarch
, pc
);
1530 pc
= i386_analyze_struct_return (pc
, current_pc
, cache
);
1531 pc
= i386_skip_probe (pc
);
1532 pc
= i386_analyze_stack_align (pc
, current_pc
, cache
);
1533 pc
= i386_analyze_frame_setup (gdbarch
, pc
, current_pc
, cache
);
1534 return i386_analyze_register_saves (pc
, current_pc
, cache
);
1537 /* Return PC of first real instruction. */
1540 i386_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
1542 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1544 static gdb_byte pic_pat
[6] =
1546 0xe8, 0, 0, 0, 0, /* call 0x0 */
1547 0x5b, /* popl %ebx */
1549 struct i386_frame_cache cache
;
1555 pc
= i386_analyze_prologue (gdbarch
, start_pc
, 0xffffffff, &cache
);
1556 if (cache
.locals
< 0)
1559 /* Found valid frame setup. */
1561 /* The native cc on SVR4 in -K PIC mode inserts the following code
1562 to get the address of the global offset table (GOT) into register
1567 movl %ebx,x(%ebp) (optional)
1570 This code is with the rest of the prologue (at the end of the
1571 function), so we have to skip it to get to the first real
1572 instruction at the start of the function. */
1574 for (i
= 0; i
< 6; i
++)
1576 if (target_read_memory (pc
+ i
, &op
, 1))
1579 if (pic_pat
[i
] != op
)
1586 if (target_read_memory (pc
+ delta
, &op
, 1))
1589 if (op
== 0x89) /* movl %ebx, x(%ebp) */
1591 op
= read_memory_unsigned_integer (pc
+ delta
+ 1, 1, byte_order
);
1593 if (op
== 0x5d) /* One byte offset from %ebp. */
1595 else if (op
== 0x9d) /* Four byte offset from %ebp. */
1597 else /* Unexpected instruction. */
1600 if (target_read_memory (pc
+ delta
, &op
, 1))
1605 if (delta
> 0 && op
== 0x81
1606 && read_memory_unsigned_integer (pc
+ delta
+ 1, 1, byte_order
)
1613 /* If the function starts with a branch (to startup code at the end)
1614 the last instruction should bring us back to the first
1615 instruction of the real code. */
1616 if (i386_follow_jump (gdbarch
, start_pc
) != start_pc
)
1617 pc
= i386_follow_jump (gdbarch
, pc
);
1622 /* Check that the code pointed to by PC corresponds to a call to
1623 __main, skip it if so. Return PC otherwise. */
1626 i386_skip_main_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1628 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1631 if (target_read_memory (pc
, &op
, 1))
1637 if (target_read_memory (pc
+ 1, buf
, sizeof buf
) == 0)
1639 /* Make sure address is computed correctly as a 32bit
1640 integer even if CORE_ADDR is 64 bit wide. */
1641 struct minimal_symbol
*s
;
1642 CORE_ADDR call_dest
;
1644 call_dest
= pc
+ 5 + extract_signed_integer (buf
, 4, byte_order
);
1645 call_dest
= call_dest
& 0xffffffffU
;
1646 s
= lookup_minimal_symbol_by_pc (call_dest
);
1648 && SYMBOL_LINKAGE_NAME (s
) != NULL
1649 && strcmp (SYMBOL_LINKAGE_NAME (s
), "__main") == 0)
1657 /* This function is 64-bit safe. */
1660 i386_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1664 frame_unwind_register (next_frame
, gdbarch_pc_regnum (gdbarch
), buf
);
1665 return extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
1669 /* Normal frames. */
1672 i386_frame_cache_1 (struct frame_info
*this_frame
,
1673 struct i386_frame_cache
*cache
)
1675 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1676 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1680 cache
->pc
= get_frame_func (this_frame
);
1682 /* In principle, for normal frames, %ebp holds the frame pointer,
1683 which holds the base address for the current stack frame.
1684 However, for functions that don't need it, the frame pointer is
1685 optional. For these "frameless" functions the frame pointer is
1686 actually the frame pointer of the calling frame. Signal
1687 trampolines are just a special case of a "frameless" function.
1688 They (usually) share their frame pointer with the frame that was
1689 in progress when the signal occurred. */
1691 get_frame_register (this_frame
, I386_EBP_REGNUM
, buf
);
1692 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
);
1693 if (cache
->base
== 0)
1699 /* For normal frames, %eip is stored at 4(%ebp). */
1700 cache
->saved_regs
[I386_EIP_REGNUM
] = 4;
1703 i386_analyze_prologue (gdbarch
, cache
->pc
, get_frame_pc (this_frame
),
1706 if (cache
->locals
< 0)
1708 /* We didn't find a valid frame, which means that CACHE->base
1709 currently holds the frame pointer for our calling frame. If
1710 we're at the start of a function, or somewhere half-way its
1711 prologue, the function's frame probably hasn't been fully
1712 setup yet. Try to reconstruct the base address for the stack
1713 frame by looking at the stack pointer. For truly "frameless"
1714 functions this might work too. */
1716 if (cache
->saved_sp_reg
!= -1)
1718 /* Saved stack pointer has been saved. */
1719 get_frame_register (this_frame
, cache
->saved_sp_reg
, buf
);
1720 cache
->saved_sp
= extract_unsigned_integer (buf
, 4, byte_order
);
1722 /* We're halfway aligning the stack. */
1723 cache
->base
= ((cache
->saved_sp
- 4) & 0xfffffff0) - 4;
1724 cache
->saved_regs
[I386_EIP_REGNUM
] = cache
->saved_sp
- 4;
1726 /* This will be added back below. */
1727 cache
->saved_regs
[I386_EIP_REGNUM
] -= cache
->base
;
1729 else if (cache
->pc
!= 0
1730 || target_read_memory (get_frame_pc (this_frame
), buf
, 1))
1732 /* We're in a known function, but did not find a frame
1733 setup. Assume that the function does not use %ebp.
1734 Alternatively, we may have jumped to an invalid
1735 address; in that case there is definitely no new
1737 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
1738 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
)
1742 /* We're in an unknown function. We could not find the start
1743 of the function to analyze the prologue; our best option is
1744 to assume a typical frame layout with the caller's %ebp
1746 cache
->saved_regs
[I386_EBP_REGNUM
] = 0;
1749 if (cache
->saved_sp_reg
!= -1)
1751 /* Saved stack pointer has been saved (but the SAVED_SP_REG
1752 register may be unavailable). */
1753 if (cache
->saved_sp
== 0
1754 && frame_register_read (this_frame
, cache
->saved_sp_reg
, buf
))
1755 cache
->saved_sp
= extract_unsigned_integer (buf
, 4, byte_order
);
1757 /* Now that we have the base address for the stack frame we can
1758 calculate the value of %esp in the calling frame. */
1759 else if (cache
->saved_sp
== 0)
1760 cache
->saved_sp
= cache
->base
+ 8;
1762 /* Adjust all the saved registers such that they contain addresses
1763 instead of offsets. */
1764 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
1765 if (cache
->saved_regs
[i
] != -1)
1766 cache
->saved_regs
[i
] += cache
->base
;
1771 static struct i386_frame_cache
*
1772 i386_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1774 volatile struct gdb_exception ex
;
1775 struct i386_frame_cache
*cache
;
1780 cache
= i386_alloc_frame_cache ();
1781 *this_cache
= cache
;
1783 TRY_CATCH (ex
, RETURN_MASK_ERROR
)
1785 i386_frame_cache_1 (this_frame
, cache
);
1787 if (ex
.reason
< 0 && ex
.error
!= NOT_AVAILABLE_ERROR
)
1788 throw_exception (ex
);
1794 i386_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
1795 struct frame_id
*this_id
)
1797 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1799 /* This marks the outermost frame. */
1800 if (cache
->base
== 0)
1803 /* See the end of i386_push_dummy_call. */
1804 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
1807 static enum unwind_stop_reason
1808 i386_frame_unwind_stop_reason (struct frame_info
*this_frame
,
1811 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1814 return UNWIND_UNAVAILABLE
;
1816 /* This marks the outermost frame. */
1817 if (cache
->base
== 0)
1818 return UNWIND_OUTERMOST
;
1820 return UNWIND_NO_REASON
;
1823 static struct value
*
1824 i386_frame_prev_register (struct frame_info
*this_frame
, void **this_cache
,
1827 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1829 gdb_assert (regnum
>= 0);
1831 /* The System V ABI says that:
1833 "The flags register contains the system flags, such as the
1834 direction flag and the carry flag. The direction flag must be
1835 set to the forward (that is, zero) direction before entry and
1836 upon exit from a function. Other user flags have no specified
1837 role in the standard calling sequence and are not preserved."
1839 To guarantee the "upon exit" part of that statement we fake a
1840 saved flags register that has its direction flag cleared.
1842 Note that GCC doesn't seem to rely on the fact that the direction
1843 flag is cleared after a function return; it always explicitly
1844 clears the flag before operations where it matters.
1846 FIXME: kettenis/20030316: I'm not quite sure whether this is the
1847 right thing to do. The way we fake the flags register here makes
1848 it impossible to change it. */
1850 if (regnum
== I386_EFLAGS_REGNUM
)
1854 val
= get_frame_register_unsigned (this_frame
, regnum
);
1856 return frame_unwind_got_constant (this_frame
, regnum
, val
);
1859 if (regnum
== I386_EIP_REGNUM
&& cache
->pc_in_eax
)
1860 return frame_unwind_got_register (this_frame
, regnum
, I386_EAX_REGNUM
);
1862 if (regnum
== I386_ESP_REGNUM
1863 && (cache
->saved_sp
!= 0 || cache
->saved_sp_reg
!= -1))
1865 /* If the SP has been saved, but we don't know where, then this
1866 means that SAVED_SP_REG register was found unavailable back
1867 when we built the cache. */
1868 if (cache
->saved_sp
== 0)
1869 return frame_unwind_got_register (this_frame
, regnum
,
1870 cache
->saved_sp_reg
);
1872 return frame_unwind_got_constant (this_frame
, regnum
,
1876 if (regnum
< I386_NUM_SAVED_REGS
&& cache
->saved_regs
[regnum
] != -1)
1877 return frame_unwind_got_memory (this_frame
, regnum
,
1878 cache
->saved_regs
[regnum
]);
1880 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
1883 static const struct frame_unwind i386_frame_unwind
=
1886 i386_frame_unwind_stop_reason
,
1888 i386_frame_prev_register
,
1890 default_frame_sniffer
1893 /* Normal frames, but in a function epilogue. */
1895 /* The epilogue is defined here as the 'ret' instruction, which will
1896 follow any instruction such as 'leave' or 'pop %ebp' that destroys
1897 the function's stack frame. */
1900 i386_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1903 struct symtab
*symtab
;
1905 symtab
= find_pc_symtab (pc
);
1906 if (symtab
&& symtab
->epilogue_unwind_valid
)
1909 if (target_read_memory (pc
, &insn
, 1))
1910 return 0; /* Can't read memory at pc. */
1912 if (insn
!= 0xc3) /* 'ret' instruction. */
1919 i386_epilogue_frame_sniffer (const struct frame_unwind
*self
,
1920 struct frame_info
*this_frame
,
1921 void **this_prologue_cache
)
1923 if (frame_relative_level (this_frame
) == 0)
1924 return i386_in_function_epilogue_p (get_frame_arch (this_frame
),
1925 get_frame_pc (this_frame
));
1930 static struct i386_frame_cache
*
1931 i386_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1933 volatile struct gdb_exception ex
;
1934 struct i386_frame_cache
*cache
;
1940 cache
= i386_alloc_frame_cache ();
1941 *this_cache
= cache
;
1943 TRY_CATCH (ex
, RETURN_MASK_ERROR
)
1945 cache
->pc
= get_frame_func (this_frame
);
1947 /* At this point the stack looks as if we just entered the
1948 function, with the return address at the top of the
1950 sp
= get_frame_register_unsigned (this_frame
, I386_ESP_REGNUM
);
1951 cache
->base
= sp
+ cache
->sp_offset
;
1952 cache
->saved_sp
= cache
->base
+ 8;
1953 cache
->saved_regs
[I386_EIP_REGNUM
] = cache
->base
+ 4;
1957 if (ex
.reason
< 0 && ex
.error
!= NOT_AVAILABLE_ERROR
)
1958 throw_exception (ex
);
1963 static enum unwind_stop_reason
1964 i386_epilogue_frame_unwind_stop_reason (struct frame_info
*this_frame
,
1967 struct i386_frame_cache
*cache
=
1968 i386_epilogue_frame_cache (this_frame
, this_cache
);
1971 return UNWIND_UNAVAILABLE
;
1973 return UNWIND_NO_REASON
;
1977 i386_epilogue_frame_this_id (struct frame_info
*this_frame
,
1979 struct frame_id
*this_id
)
1981 struct i386_frame_cache
*cache
=
1982 i386_epilogue_frame_cache (this_frame
, this_cache
);
1987 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
1990 static struct value
*
1991 i386_epilogue_frame_prev_register (struct frame_info
*this_frame
,
1992 void **this_cache
, int regnum
)
1994 /* Make sure we've initialized the cache. */
1995 i386_epilogue_frame_cache (this_frame
, this_cache
);
1997 return i386_frame_prev_register (this_frame
, this_cache
, regnum
);
2000 static const struct frame_unwind i386_epilogue_frame_unwind
=
2003 i386_epilogue_frame_unwind_stop_reason
,
2004 i386_epilogue_frame_this_id
,
2005 i386_epilogue_frame_prev_register
,
2007 i386_epilogue_frame_sniffer
2011 /* Stack-based trampolines. */
2013 /* These trampolines are used on cross x86 targets, when taking the
2014 address of a nested function. When executing these trampolines,
2015 no stack frame is set up, so we are in a similar situation as in
2016 epilogues and i386_epilogue_frame_this_id can be re-used. */
2018 /* Static chain passed in register. */
2020 struct i386_insn i386_tramp_chain_in_reg_insns
[] =
2022 /* `movl imm32, %eax' and `movl imm32, %ecx' */
2023 { 5, { 0xb8 }, { 0xfe } },
2026 { 5, { 0xe9 }, { 0xff } },
2031 /* Static chain passed on stack (when regparm=3). */
2033 struct i386_insn i386_tramp_chain_on_stack_insns
[] =
2036 { 5, { 0x68 }, { 0xff } },
2039 { 5, { 0xe9 }, { 0xff } },
2044 /* Return whether PC points inside a stack trampoline. */
2047 i386_in_stack_tramp_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2052 /* A stack trampoline is detected if no name is associated
2053 to the current pc and if it points inside a trampoline
2056 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
2060 if (target_read_memory (pc
, &insn
, 1))
2063 if (!i386_match_insn_block (pc
, i386_tramp_chain_in_reg_insns
)
2064 && !i386_match_insn_block (pc
, i386_tramp_chain_on_stack_insns
))
2071 i386_stack_tramp_frame_sniffer (const struct frame_unwind
*self
,
2072 struct frame_info
*this_frame
,
2075 if (frame_relative_level (this_frame
) == 0)
2076 return i386_in_stack_tramp_p (get_frame_arch (this_frame
),
2077 get_frame_pc (this_frame
));
2082 static const struct frame_unwind i386_stack_tramp_frame_unwind
=
2085 i386_epilogue_frame_unwind_stop_reason
,
2086 i386_epilogue_frame_this_id
,
2087 i386_epilogue_frame_prev_register
,
2089 i386_stack_tramp_frame_sniffer
2092 /* Generate a bytecode expression to get the value of the saved PC. */
2095 i386_gen_return_address (struct gdbarch
*gdbarch
,
2096 struct agent_expr
*ax
, struct axs_value
*value
,
2099 /* The following sequence assumes the traditional use of the base
2101 ax_reg (ax
, I386_EBP_REGNUM
);
2103 ax_simple (ax
, aop_add
);
2104 value
->type
= register_type (gdbarch
, I386_EIP_REGNUM
);
2105 value
->kind
= axs_lvalue_memory
;
2109 /* Signal trampolines. */
2111 static struct i386_frame_cache
*
2112 i386_sigtramp_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2114 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2115 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2116 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2117 volatile struct gdb_exception ex
;
2118 struct i386_frame_cache
*cache
;
2125 cache
= i386_alloc_frame_cache ();
2127 TRY_CATCH (ex
, RETURN_MASK_ERROR
)
2129 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
2130 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
) - 4;
2132 addr
= tdep
->sigcontext_addr (this_frame
);
2133 if (tdep
->sc_reg_offset
)
2137 gdb_assert (tdep
->sc_num_regs
<= I386_NUM_SAVED_REGS
);
2139 for (i
= 0; i
< tdep
->sc_num_regs
; i
++)
2140 if (tdep
->sc_reg_offset
[i
] != -1)
2141 cache
->saved_regs
[i
] = addr
+ tdep
->sc_reg_offset
[i
];
2145 cache
->saved_regs
[I386_EIP_REGNUM
] = addr
+ tdep
->sc_pc_offset
;
2146 cache
->saved_regs
[I386_ESP_REGNUM
] = addr
+ tdep
->sc_sp_offset
;
2151 if (ex
.reason
< 0 && ex
.error
!= NOT_AVAILABLE_ERROR
)
2152 throw_exception (ex
);
2154 *this_cache
= cache
;
2158 static enum unwind_stop_reason
2159 i386_sigtramp_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2162 struct i386_frame_cache
*cache
=
2163 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2166 return UNWIND_UNAVAILABLE
;
2168 return UNWIND_NO_REASON
;
2172 i386_sigtramp_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2173 struct frame_id
*this_id
)
2175 struct i386_frame_cache
*cache
=
2176 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2181 /* See the end of i386_push_dummy_call. */
2182 (*this_id
) = frame_id_build (cache
->base
+ 8, get_frame_pc (this_frame
));
2185 static struct value
*
2186 i386_sigtramp_frame_prev_register (struct frame_info
*this_frame
,
2187 void **this_cache
, int regnum
)
2189 /* Make sure we've initialized the cache. */
2190 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2192 return i386_frame_prev_register (this_frame
, this_cache
, regnum
);
2196 i386_sigtramp_frame_sniffer (const struct frame_unwind
*self
,
2197 struct frame_info
*this_frame
,
2198 void **this_prologue_cache
)
2200 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (this_frame
));
2202 /* We shouldn't even bother if we don't have a sigcontext_addr
2204 if (tdep
->sigcontext_addr
== NULL
)
2207 if (tdep
->sigtramp_p
!= NULL
)
2209 if (tdep
->sigtramp_p (this_frame
))
2213 if (tdep
->sigtramp_start
!= 0)
2215 CORE_ADDR pc
= get_frame_pc (this_frame
);
2217 gdb_assert (tdep
->sigtramp_end
!= 0);
2218 if (pc
>= tdep
->sigtramp_start
&& pc
< tdep
->sigtramp_end
)
2225 static const struct frame_unwind i386_sigtramp_frame_unwind
=
2228 i386_sigtramp_frame_unwind_stop_reason
,
2229 i386_sigtramp_frame_this_id
,
2230 i386_sigtramp_frame_prev_register
,
2232 i386_sigtramp_frame_sniffer
2237 i386_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
2239 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
2244 static const struct frame_base i386_frame_base
=
2247 i386_frame_base_address
,
2248 i386_frame_base_address
,
2249 i386_frame_base_address
2252 static struct frame_id
2253 i386_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
2257 fp
= get_frame_register_unsigned (this_frame
, I386_EBP_REGNUM
);
2259 /* See the end of i386_push_dummy_call. */
2260 return frame_id_build (fp
+ 8, get_frame_pc (this_frame
));
2263 /* _Decimal128 function return values need 16-byte alignment on the
2267 i386_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
2269 return sp
& -(CORE_ADDR
)16;
2273 /* Figure out where the longjmp will land. Slurp the args out of the
2274 stack. We expect the first arg to be a pointer to the jmp_buf
2275 structure from which we extract the address that we will land at.
2276 This address is copied into PC. This routine returns non-zero on
2280 i386_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
2283 CORE_ADDR sp
, jb_addr
;
2284 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2285 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2286 int jb_pc_offset
= gdbarch_tdep (gdbarch
)->jb_pc_offset
;
2288 /* If JB_PC_OFFSET is -1, we have no way to find out where the
2289 longjmp will land. */
2290 if (jb_pc_offset
== -1)
2293 get_frame_register (frame
, I386_ESP_REGNUM
, buf
);
2294 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
2295 if (target_read_memory (sp
+ 4, buf
, 4))
2298 jb_addr
= extract_unsigned_integer (buf
, 4, byte_order
);
2299 if (target_read_memory (jb_addr
+ jb_pc_offset
, buf
, 4))
2302 *pc
= extract_unsigned_integer (buf
, 4, byte_order
);
2307 /* Check whether TYPE must be 16-byte-aligned when passed as a
2308 function argument. 16-byte vectors, _Decimal128 and structures or
2309 unions containing such types must be 16-byte-aligned; other
2310 arguments are 4-byte-aligned. */
2313 i386_16_byte_align_p (struct type
*type
)
2315 type
= check_typedef (type
);
2316 if ((TYPE_CODE (type
) == TYPE_CODE_DECFLOAT
2317 || (TYPE_CODE (type
) == TYPE_CODE_ARRAY
&& TYPE_VECTOR (type
)))
2318 && TYPE_LENGTH (type
) == 16)
2320 if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
2321 return i386_16_byte_align_p (TYPE_TARGET_TYPE (type
));
2322 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
2323 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
2326 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
2328 if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type
, i
)))
2335 /* Implementation for set_gdbarch_push_dummy_code. */
2338 i386_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
, CORE_ADDR funaddr
,
2339 struct value
**args
, int nargs
, struct type
*value_type
,
2340 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
,
2341 struct regcache
*regcache
)
2343 /* Use 0xcc breakpoint - 1 byte. */
2347 /* Keep the stack aligned. */
2352 i386_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2353 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
2354 struct value
**args
, CORE_ADDR sp
, int struct_return
,
2355 CORE_ADDR struct_addr
)
2357 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2363 /* Determine the total space required for arguments and struct
2364 return address in a first pass (allowing for 16-byte-aligned
2365 arguments), then push arguments in a second pass. */
2367 for (write_pass
= 0; write_pass
< 2; write_pass
++)
2369 int args_space_used
= 0;
2375 /* Push value address. */
2376 store_unsigned_integer (buf
, 4, byte_order
, struct_addr
);
2377 write_memory (sp
, buf
, 4);
2378 args_space_used
+= 4;
2384 for (i
= 0; i
< nargs
; i
++)
2386 int len
= TYPE_LENGTH (value_enclosing_type (args
[i
]));
2390 if (i386_16_byte_align_p (value_enclosing_type (args
[i
])))
2391 args_space_used
= align_up (args_space_used
, 16);
2393 write_memory (sp
+ args_space_used
,
2394 value_contents_all (args
[i
]), len
);
2395 /* The System V ABI says that:
2397 "An argument's size is increased, if necessary, to make it a
2398 multiple of [32-bit] words. This may require tail padding,
2399 depending on the size of the argument."
2401 This makes sure the stack stays word-aligned. */
2402 args_space_used
+= align_up (len
, 4);
2406 if (i386_16_byte_align_p (value_enclosing_type (args
[i
])))
2407 args_space
= align_up (args_space
, 16);
2408 args_space
+= align_up (len
, 4);
2416 /* The original System V ABI only requires word alignment,
2417 but modern incarnations need 16-byte alignment in order
2418 to support SSE. Since wasting a few bytes here isn't
2419 harmful we unconditionally enforce 16-byte alignment. */
2424 /* Store return address. */
2426 store_unsigned_integer (buf
, 4, byte_order
, bp_addr
);
2427 write_memory (sp
, buf
, 4);
2429 /* Finally, update the stack pointer... */
2430 store_unsigned_integer (buf
, 4, byte_order
, sp
);
2431 regcache_cooked_write (regcache
, I386_ESP_REGNUM
, buf
);
2433 /* ...and fake a frame pointer. */
2434 regcache_cooked_write (regcache
, I386_EBP_REGNUM
, buf
);
2436 /* MarkK wrote: This "+ 8" is all over the place:
2437 (i386_frame_this_id, i386_sigtramp_frame_this_id,
2438 i386_dummy_id). It's there, since all frame unwinders for
2439 a given target have to agree (within a certain margin) on the
2440 definition of the stack address of a frame. Otherwise frame id
2441 comparison might not work correctly. Since DWARF2/GCC uses the
2442 stack address *before* the function call as a frame's CFA. On
2443 the i386, when %ebp is used as a frame pointer, the offset
2444 between the contents %ebp and the CFA as defined by GCC. */
2448 /* These registers are used for returning integers (and on some
2449 targets also for returning `struct' and `union' values when their
2450 size and alignment match an integer type). */
2451 #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */
2452 #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */
2454 /* Read, for architecture GDBARCH, a function return value of TYPE
2455 from REGCACHE, and copy that into VALBUF. */
2458 i386_extract_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
2459 struct regcache
*regcache
, gdb_byte
*valbuf
)
2461 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2462 int len
= TYPE_LENGTH (type
);
2463 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
2465 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2467 if (tdep
->st0_regnum
< 0)
2469 warning (_("Cannot find floating-point return value."));
2470 memset (valbuf
, 0, len
);
2474 /* Floating-point return values can be found in %st(0). Convert
2475 its contents to the desired type. This is probably not
2476 exactly how it would happen on the target itself, but it is
2477 the best we can do. */
2478 regcache_raw_read (regcache
, I386_ST0_REGNUM
, buf
);
2479 convert_typed_floating (buf
, i387_ext_type (gdbarch
), valbuf
, type
);
2483 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
2484 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
2486 if (len
<= low_size
)
2488 regcache_raw_read (regcache
, LOW_RETURN_REGNUM
, buf
);
2489 memcpy (valbuf
, buf
, len
);
2491 else if (len
<= (low_size
+ high_size
))
2493 regcache_raw_read (regcache
, LOW_RETURN_REGNUM
, buf
);
2494 memcpy (valbuf
, buf
, low_size
);
2495 regcache_raw_read (regcache
, HIGH_RETURN_REGNUM
, buf
);
2496 memcpy (valbuf
+ low_size
, buf
, len
- low_size
);
2499 internal_error (__FILE__
, __LINE__
,
2500 _("Cannot extract return value of %d bytes long."),
2505 /* Write, for architecture GDBARCH, a function return value of TYPE
2506 from VALBUF into REGCACHE. */
2509 i386_store_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
2510 struct regcache
*regcache
, const gdb_byte
*valbuf
)
2512 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2513 int len
= TYPE_LENGTH (type
);
2515 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2518 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
2520 if (tdep
->st0_regnum
< 0)
2522 warning (_("Cannot set floating-point return value."));
2526 /* Returning floating-point values is a bit tricky. Apart from
2527 storing the return value in %st(0), we have to simulate the
2528 state of the FPU at function return point. */
2530 /* Convert the value found in VALBUF to the extended
2531 floating-point format used by the FPU. This is probably
2532 not exactly how it would happen on the target itself, but
2533 it is the best we can do. */
2534 convert_typed_floating (valbuf
, type
, buf
, i387_ext_type (gdbarch
));
2535 regcache_raw_write (regcache
, I386_ST0_REGNUM
, buf
);
2537 /* Set the top of the floating-point register stack to 7. The
2538 actual value doesn't really matter, but 7 is what a normal
2539 function return would end up with if the program started out
2540 with a freshly initialized FPU. */
2541 regcache_raw_read_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), &fstat
);
2543 regcache_raw_write_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), fstat
);
2545 /* Mark %st(1) through %st(7) as empty. Since we set the top of
2546 the floating-point register stack to 7, the appropriate value
2547 for the tag word is 0x3fff. */
2548 regcache_raw_write_unsigned (regcache
, I387_FTAG_REGNUM (tdep
), 0x3fff);
2552 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
2553 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
2555 if (len
<= low_size
)
2556 regcache_raw_write_part (regcache
, LOW_RETURN_REGNUM
, 0, len
, valbuf
);
2557 else if (len
<= (low_size
+ high_size
))
2559 regcache_raw_write (regcache
, LOW_RETURN_REGNUM
, valbuf
);
2560 regcache_raw_write_part (regcache
, HIGH_RETURN_REGNUM
, 0,
2561 len
- low_size
, valbuf
+ low_size
);
2564 internal_error (__FILE__
, __LINE__
,
2565 _("Cannot store return value of %d bytes long."), len
);
2570 /* This is the variable that is set with "set struct-convention", and
2571 its legitimate values. */
2572 static const char default_struct_convention
[] = "default";
2573 static const char pcc_struct_convention
[] = "pcc";
2574 static const char reg_struct_convention
[] = "reg";
2575 static const char *const valid_conventions
[] =
2577 default_struct_convention
,
2578 pcc_struct_convention
,
2579 reg_struct_convention
,
2582 static const char *struct_convention
= default_struct_convention
;
2584 /* Return non-zero if TYPE, which is assumed to be a structure,
2585 a union type, or an array type, should be returned in registers
2586 for architecture GDBARCH. */
2589 i386_reg_struct_return_p (struct gdbarch
*gdbarch
, struct type
*type
)
2591 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2592 enum type_code code
= TYPE_CODE (type
);
2593 int len
= TYPE_LENGTH (type
);
2595 gdb_assert (code
== TYPE_CODE_STRUCT
2596 || code
== TYPE_CODE_UNION
2597 || code
== TYPE_CODE_ARRAY
);
2599 if (struct_convention
== pcc_struct_convention
2600 || (struct_convention
== default_struct_convention
2601 && tdep
->struct_return
== pcc_struct_return
))
2604 /* Structures consisting of a single `float', `double' or 'long
2605 double' member are returned in %st(0). */
2606 if (code
== TYPE_CODE_STRUCT
&& TYPE_NFIELDS (type
) == 1)
2608 type
= check_typedef (TYPE_FIELD_TYPE (type
, 0));
2609 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2610 return (len
== 4 || len
== 8 || len
== 12);
2613 return (len
== 1 || len
== 2 || len
== 4 || len
== 8);
2616 /* Determine, for architecture GDBARCH, how a return value of TYPE
2617 should be returned. If it is supposed to be returned in registers,
2618 and READBUF is non-zero, read the appropriate value from REGCACHE,
2619 and copy it into READBUF. If WRITEBUF is non-zero, write the value
2620 from WRITEBUF into REGCACHE. */
2622 static enum return_value_convention
2623 i386_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
2624 struct type
*type
, struct regcache
*regcache
,
2625 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2627 enum type_code code
= TYPE_CODE (type
);
2629 if (((code
== TYPE_CODE_STRUCT
2630 || code
== TYPE_CODE_UNION
2631 || code
== TYPE_CODE_ARRAY
)
2632 && !i386_reg_struct_return_p (gdbarch
, type
))
2633 /* 128-bit decimal float uses the struct return convention. */
2634 || (code
== TYPE_CODE_DECFLOAT
&& TYPE_LENGTH (type
) == 16))
2636 /* The System V ABI says that:
2638 "A function that returns a structure or union also sets %eax
2639 to the value of the original address of the caller's area
2640 before it returns. Thus when the caller receives control
2641 again, the address of the returned object resides in register
2642 %eax and can be used to access the object."
2644 So the ABI guarantees that we can always find the return
2645 value just after the function has returned. */
2647 /* Note that the ABI doesn't mention functions returning arrays,
2648 which is something possible in certain languages such as Ada.
2649 In this case, the value is returned as if it was wrapped in
2650 a record, so the convention applied to records also applies
2657 regcache_raw_read_unsigned (regcache
, I386_EAX_REGNUM
, &addr
);
2658 read_memory (addr
, readbuf
, TYPE_LENGTH (type
));
2661 return RETURN_VALUE_ABI_RETURNS_ADDRESS
;
2664 /* This special case is for structures consisting of a single
2665 `float', `double' or 'long double' member. These structures are
2666 returned in %st(0). For these structures, we call ourselves
2667 recursively, changing TYPE into the type of the first member of
2668 the structure. Since that should work for all structures that
2669 have only one member, we don't bother to check the member's type
2671 if (code
== TYPE_CODE_STRUCT
&& TYPE_NFIELDS (type
) == 1)
2673 type
= check_typedef (TYPE_FIELD_TYPE (type
, 0));
2674 return i386_return_value (gdbarch
, function
, type
, regcache
,
2679 i386_extract_return_value (gdbarch
, type
, regcache
, readbuf
);
2681 i386_store_return_value (gdbarch
, type
, regcache
, writebuf
);
2683 return RETURN_VALUE_REGISTER_CONVENTION
;
2688 i387_ext_type (struct gdbarch
*gdbarch
)
2690 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2692 if (!tdep
->i387_ext_type
)
2694 tdep
->i387_ext_type
= tdesc_find_type (gdbarch
, "i387_ext");
2695 gdb_assert (tdep
->i387_ext_type
!= NULL
);
2698 return tdep
->i387_ext_type
;
2701 /* Construct vector type for pseudo YMM registers. We can't use
2702 tdesc_find_type since YMM isn't described in target description. */
2704 static struct type
*
2705 i386_ymm_type (struct gdbarch
*gdbarch
)
2707 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2709 if (!tdep
->i386_ymm_type
)
2711 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2713 /* The type we're building is this: */
2715 union __gdb_builtin_type_vec256i
2717 int128_t uint128
[2];
2718 int64_t v2_int64
[4];
2719 int32_t v4_int32
[8];
2720 int16_t v8_int16
[16];
2721 int8_t v16_int8
[32];
2722 double v2_double
[4];
2729 t
= arch_composite_type (gdbarch
,
2730 "__gdb_builtin_type_vec256i", TYPE_CODE_UNION
);
2731 append_composite_type_field (t
, "v8_float",
2732 init_vector_type (bt
->builtin_float
, 8));
2733 append_composite_type_field (t
, "v4_double",
2734 init_vector_type (bt
->builtin_double
, 4));
2735 append_composite_type_field (t
, "v32_int8",
2736 init_vector_type (bt
->builtin_int8
, 32));
2737 append_composite_type_field (t
, "v16_int16",
2738 init_vector_type (bt
->builtin_int16
, 16));
2739 append_composite_type_field (t
, "v8_int32",
2740 init_vector_type (bt
->builtin_int32
, 8));
2741 append_composite_type_field (t
, "v4_int64",
2742 init_vector_type (bt
->builtin_int64
, 4));
2743 append_composite_type_field (t
, "v2_int128",
2744 init_vector_type (bt
->builtin_int128
, 2));
2746 TYPE_VECTOR (t
) = 1;
2747 TYPE_NAME (t
) = "builtin_type_vec256i";
2748 tdep
->i386_ymm_type
= t
;
2751 return tdep
->i386_ymm_type
;
2754 /* Construct vector type for MMX registers. */
2755 static struct type
*
2756 i386_mmx_type (struct gdbarch
*gdbarch
)
2758 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2760 if (!tdep
->i386_mmx_type
)
2762 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2764 /* The type we're building is this: */
2766 union __gdb_builtin_type_vec64i
2769 int32_t v2_int32
[2];
2770 int16_t v4_int16
[4];
2777 t
= arch_composite_type (gdbarch
,
2778 "__gdb_builtin_type_vec64i", TYPE_CODE_UNION
);
2780 append_composite_type_field (t
, "uint64", bt
->builtin_int64
);
2781 append_composite_type_field (t
, "v2_int32",
2782 init_vector_type (bt
->builtin_int32
, 2));
2783 append_composite_type_field (t
, "v4_int16",
2784 init_vector_type (bt
->builtin_int16
, 4));
2785 append_composite_type_field (t
, "v8_int8",
2786 init_vector_type (bt
->builtin_int8
, 8));
2788 TYPE_VECTOR (t
) = 1;
2789 TYPE_NAME (t
) = "builtin_type_vec64i";
2790 tdep
->i386_mmx_type
= t
;
2793 return tdep
->i386_mmx_type
;
2796 /* Return the GDB type object for the "standard" data type of data in
2800 i386_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
2802 if (i386_mmx_regnum_p (gdbarch
, regnum
))
2803 return i386_mmx_type (gdbarch
);
2804 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
2805 return i386_ymm_type (gdbarch
);
2808 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2809 if (i386_byte_regnum_p (gdbarch
, regnum
))
2810 return bt
->builtin_int8
;
2811 else if (i386_word_regnum_p (gdbarch
, regnum
))
2812 return bt
->builtin_int16
;
2813 else if (i386_dword_regnum_p (gdbarch
, regnum
))
2814 return bt
->builtin_int32
;
2817 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
2820 /* Map a cooked register onto a raw register or memory. For the i386,
2821 the MMX registers need to be mapped onto floating point registers. */
2824 i386_mmx_regnum_to_fp_regnum (struct regcache
*regcache
, int regnum
)
2826 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_regcache_arch (regcache
));
2831 mmxreg
= regnum
- tdep
->mm0_regnum
;
2832 regcache_raw_read_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), &fstat
);
2833 tos
= (fstat
>> 11) & 0x7;
2834 fpreg
= (mmxreg
+ tos
) % 8;
2836 return (I387_ST0_REGNUM (tdep
) + fpreg
);
2839 /* A helper function for us by i386_pseudo_register_read_value and
2840 amd64_pseudo_register_read_value. It does all the work but reads
2841 the data into an already-allocated value. */
2844 i386_pseudo_register_read_into_value (struct gdbarch
*gdbarch
,
2845 struct regcache
*regcache
,
2847 struct value
*result_value
)
2849 gdb_byte raw_buf
[MAX_REGISTER_SIZE
];
2850 enum register_status status
;
2851 gdb_byte
*buf
= value_contents_raw (result_value
);
2853 if (i386_mmx_regnum_p (gdbarch
, regnum
))
2855 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
2857 /* Extract (always little endian). */
2858 status
= regcache_raw_read (regcache
, fpnum
, raw_buf
);
2859 if (status
!= REG_VALID
)
2860 mark_value_bytes_unavailable (result_value
, 0,
2861 TYPE_LENGTH (value_type (result_value
)));
2863 memcpy (buf
, raw_buf
, register_size (gdbarch
, regnum
));
2867 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2869 if (i386_ymm_regnum_p (gdbarch
, regnum
))
2871 regnum
-= tdep
->ymm0_regnum
;
2873 /* Extract (always little endian). Read lower 128bits. */
2874 status
= regcache_raw_read (regcache
,
2875 I387_XMM0_REGNUM (tdep
) + regnum
,
2877 if (status
!= REG_VALID
)
2878 mark_value_bytes_unavailable (result_value
, 0, 16);
2880 memcpy (buf
, raw_buf
, 16);
2881 /* Read upper 128bits. */
2882 status
= regcache_raw_read (regcache
,
2883 tdep
->ymm0h_regnum
+ regnum
,
2885 if (status
!= REG_VALID
)
2886 mark_value_bytes_unavailable (result_value
, 16, 32);
2888 memcpy (buf
+ 16, raw_buf
, 16);
2890 else if (i386_word_regnum_p (gdbarch
, regnum
))
2892 int gpnum
= regnum
- tdep
->ax_regnum
;
2894 /* Extract (always little endian). */
2895 status
= regcache_raw_read (regcache
, gpnum
, raw_buf
);
2896 if (status
!= REG_VALID
)
2897 mark_value_bytes_unavailable (result_value
, 0,
2898 TYPE_LENGTH (value_type (result_value
)));
2900 memcpy (buf
, raw_buf
, 2);
2902 else if (i386_byte_regnum_p (gdbarch
, regnum
))
2904 /* Check byte pseudo registers last since this function will
2905 be called from amd64_pseudo_register_read, which handles
2906 byte pseudo registers differently. */
2907 int gpnum
= regnum
- tdep
->al_regnum
;
2909 /* Extract (always little endian). We read both lower and
2911 status
= regcache_raw_read (regcache
, gpnum
% 4, raw_buf
);
2912 if (status
!= REG_VALID
)
2913 mark_value_bytes_unavailable (result_value
, 0,
2914 TYPE_LENGTH (value_type (result_value
)));
2915 else if (gpnum
>= 4)
2916 memcpy (buf
, raw_buf
+ 1, 1);
2918 memcpy (buf
, raw_buf
, 1);
2921 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
2925 static struct value
*
2926 i386_pseudo_register_read_value (struct gdbarch
*gdbarch
,
2927 struct regcache
*regcache
,
2930 struct value
*result
;
2932 result
= allocate_value (register_type (gdbarch
, regnum
));
2933 VALUE_LVAL (result
) = lval_register
;
2934 VALUE_REGNUM (result
) = regnum
;
2936 i386_pseudo_register_read_into_value (gdbarch
, regcache
, regnum
, result
);
2942 i386_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2943 int regnum
, const gdb_byte
*buf
)
2945 gdb_byte raw_buf
[MAX_REGISTER_SIZE
];
2947 if (i386_mmx_regnum_p (gdbarch
, regnum
))
2949 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
2952 regcache_raw_read (regcache
, fpnum
, raw_buf
);
2953 /* ... Modify ... (always little endian). */
2954 memcpy (raw_buf
, buf
, register_size (gdbarch
, regnum
));
2956 regcache_raw_write (regcache
, fpnum
, raw_buf
);
2960 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2962 if (i386_ymm_regnum_p (gdbarch
, regnum
))
2964 regnum
-= tdep
->ymm0_regnum
;
2966 /* ... Write lower 128bits. */
2967 regcache_raw_write (regcache
,
2968 I387_XMM0_REGNUM (tdep
) + regnum
,
2970 /* ... Write upper 128bits. */
2971 regcache_raw_write (regcache
,
2972 tdep
->ymm0h_regnum
+ regnum
,
2975 else if (i386_word_regnum_p (gdbarch
, regnum
))
2977 int gpnum
= regnum
- tdep
->ax_regnum
;
2980 regcache_raw_read (regcache
, gpnum
, raw_buf
);
2981 /* ... Modify ... (always little endian). */
2982 memcpy (raw_buf
, buf
, 2);
2984 regcache_raw_write (regcache
, gpnum
, raw_buf
);
2986 else if (i386_byte_regnum_p (gdbarch
, regnum
))
2988 /* Check byte pseudo registers last since this function will
2989 be called from amd64_pseudo_register_read, which handles
2990 byte pseudo registers differently. */
2991 int gpnum
= regnum
- tdep
->al_regnum
;
2993 /* Read ... We read both lower and upper registers. */
2994 regcache_raw_read (regcache
, gpnum
% 4, raw_buf
);
2995 /* ... Modify ... (always little endian). */
2997 memcpy (raw_buf
+ 1, buf
, 1);
2999 memcpy (raw_buf
, buf
, 1);
3001 regcache_raw_write (regcache
, gpnum
% 4, raw_buf
);
3004 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
3009 /* Return the register number of the register allocated by GCC after
3010 REGNUM, or -1 if there is no such register. */
3013 i386_next_regnum (int regnum
)
3015 /* GCC allocates the registers in the order:
3017 %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ...
3019 Since storing a variable in %esp doesn't make any sense we return
3020 -1 for %ebp and for %esp itself. */
3021 static int next_regnum
[] =
3023 I386_EDX_REGNUM
, /* Slot for %eax. */
3024 I386_EBX_REGNUM
, /* Slot for %ecx. */
3025 I386_ECX_REGNUM
, /* Slot for %edx. */
3026 I386_ESI_REGNUM
, /* Slot for %ebx. */
3027 -1, -1, /* Slots for %esp and %ebp. */
3028 I386_EDI_REGNUM
, /* Slot for %esi. */
3029 I386_EBP_REGNUM
/* Slot for %edi. */
3032 if (regnum
>= 0 && regnum
< sizeof (next_regnum
) / sizeof (next_regnum
[0]))
3033 return next_regnum
[regnum
];
3038 /* Return nonzero if a value of type TYPE stored in register REGNUM
3039 needs any special handling. */
3042 i386_convert_register_p (struct gdbarch
*gdbarch
,
3043 int regnum
, struct type
*type
)
3045 int len
= TYPE_LENGTH (type
);
3047 /* Values may be spread across multiple registers. Most debugging
3048 formats aren't expressive enough to specify the locations, so
3049 some heuristics is involved. Right now we only handle types that
3050 have a length that is a multiple of the word size, since GCC
3051 doesn't seem to put any other types into registers. */
3052 if (len
> 4 && len
% 4 == 0)
3054 int last_regnum
= regnum
;
3058 last_regnum
= i386_next_regnum (last_regnum
);
3062 if (last_regnum
!= -1)
3066 return i387_convert_register_p (gdbarch
, regnum
, type
);
3069 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
3070 return its contents in TO. */
3073 i386_register_to_value (struct frame_info
*frame
, int regnum
,
3074 struct type
*type
, gdb_byte
*to
,
3075 int *optimizedp
, int *unavailablep
)
3077 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3078 int len
= TYPE_LENGTH (type
);
3080 if (i386_fp_regnum_p (gdbarch
, regnum
))
3081 return i387_register_to_value (frame
, regnum
, type
, to
,
3082 optimizedp
, unavailablep
);
3084 /* Read a value spread across multiple registers. */
3086 gdb_assert (len
> 4 && len
% 4 == 0);
3090 gdb_assert (regnum
!= -1);
3091 gdb_assert (register_size (gdbarch
, regnum
) == 4);
3093 if (!get_frame_register_bytes (frame
, regnum
, 0,
3094 register_size (gdbarch
, regnum
),
3095 to
, optimizedp
, unavailablep
))
3098 regnum
= i386_next_regnum (regnum
);
3103 *optimizedp
= *unavailablep
= 0;
3107 /* Write the contents FROM of a value of type TYPE into register
3108 REGNUM in frame FRAME. */
3111 i386_value_to_register (struct frame_info
*frame
, int regnum
,
3112 struct type
*type
, const gdb_byte
*from
)
3114 int len
= TYPE_LENGTH (type
);
3116 if (i386_fp_regnum_p (get_frame_arch (frame
), regnum
))
3118 i387_value_to_register (frame
, regnum
, type
, from
);
3122 /* Write a value spread across multiple registers. */
3124 gdb_assert (len
> 4 && len
% 4 == 0);
3128 gdb_assert (regnum
!= -1);
3129 gdb_assert (register_size (get_frame_arch (frame
), regnum
) == 4);
3131 put_frame_register (frame
, regnum
, from
);
3132 regnum
= i386_next_regnum (regnum
);
3138 /* Supply register REGNUM from the buffer specified by GREGS and LEN
3139 in the general-purpose register set REGSET to register cache
3140 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3143 i386_supply_gregset (const struct regset
*regset
, struct regcache
*regcache
,
3144 int regnum
, const void *gregs
, size_t len
)
3146 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
3147 const gdb_byte
*regs
= gregs
;
3150 gdb_assert (len
== tdep
->sizeof_gregset
);
3152 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
3154 if ((regnum
== i
|| regnum
== -1)
3155 && tdep
->gregset_reg_offset
[i
] != -1)
3156 regcache_raw_supply (regcache
, i
, regs
+ tdep
->gregset_reg_offset
[i
]);
3160 /* Collect register REGNUM from the register cache REGCACHE and store
3161 it in the buffer specified by GREGS and LEN as described by the
3162 general-purpose register set REGSET. If REGNUM is -1, do this for
3163 all registers in REGSET. */
3166 i386_collect_gregset (const struct regset
*regset
,
3167 const struct regcache
*regcache
,
3168 int regnum
, void *gregs
, size_t len
)
3170 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
3171 gdb_byte
*regs
= gregs
;
3174 gdb_assert (len
== tdep
->sizeof_gregset
);
3176 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
3178 if ((regnum
== i
|| regnum
== -1)
3179 && tdep
->gregset_reg_offset
[i
] != -1)
3180 regcache_raw_collect (regcache
, i
, regs
+ tdep
->gregset_reg_offset
[i
]);
3184 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
3185 in the floating-point register set REGSET to register cache
3186 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3189 i386_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
3190 int regnum
, const void *fpregs
, size_t len
)
3192 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
3194 if (len
== I387_SIZEOF_FXSAVE
)
3196 i387_supply_fxsave (regcache
, regnum
, fpregs
);
3200 gdb_assert (len
== tdep
->sizeof_fpregset
);
3201 i387_supply_fsave (regcache
, regnum
, fpregs
);
3204 /* Collect register REGNUM from the register cache REGCACHE and store
3205 it in the buffer specified by FPREGS and LEN as described by the
3206 floating-point register set REGSET. If REGNUM is -1, do this for
3207 all registers in REGSET. */
3210 i386_collect_fpregset (const struct regset
*regset
,
3211 const struct regcache
*regcache
,
3212 int regnum
, void *fpregs
, size_t len
)
3214 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
3216 if (len
== I387_SIZEOF_FXSAVE
)
3218 i387_collect_fxsave (regcache
, regnum
, fpregs
);
3222 gdb_assert (len
== tdep
->sizeof_fpregset
);
3223 i387_collect_fsave (regcache
, regnum
, fpregs
);
3226 /* Similar to i386_supply_fpregset, but use XSAVE extended state. */
3229 i386_supply_xstateregset (const struct regset
*regset
,
3230 struct regcache
*regcache
, int regnum
,
3231 const void *xstateregs
, size_t len
)
3233 i387_supply_xsave (regcache
, regnum
, xstateregs
);
3236 /* Similar to i386_collect_fpregset , but use XSAVE extended state. */
3239 i386_collect_xstateregset (const struct regset
*regset
,
3240 const struct regcache
*regcache
,
3241 int regnum
, void *xstateregs
, size_t len
)
3243 i387_collect_xsave (regcache
, regnum
, xstateregs
, 1);
3246 /* Return the appropriate register set for the core section identified
3247 by SECT_NAME and SECT_SIZE. */
3249 const struct regset
*
3250 i386_regset_from_core_section (struct gdbarch
*gdbarch
,
3251 const char *sect_name
, size_t sect_size
)
3253 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3255 if (strcmp (sect_name
, ".reg") == 0 && sect_size
== tdep
->sizeof_gregset
)
3257 if (tdep
->gregset
== NULL
)
3258 tdep
->gregset
= regset_alloc (gdbarch
, i386_supply_gregset
,
3259 i386_collect_gregset
);
3260 return tdep
->gregset
;
3263 if ((strcmp (sect_name
, ".reg2") == 0 && sect_size
== tdep
->sizeof_fpregset
)
3264 || (strcmp (sect_name
, ".reg-xfp") == 0
3265 && sect_size
== I387_SIZEOF_FXSAVE
))
3267 if (tdep
->fpregset
== NULL
)
3268 tdep
->fpregset
= regset_alloc (gdbarch
, i386_supply_fpregset
,
3269 i386_collect_fpregset
);
3270 return tdep
->fpregset
;
3273 if (strcmp (sect_name
, ".reg-xstate") == 0)
3275 if (tdep
->xstateregset
== NULL
)
3276 tdep
->xstateregset
= regset_alloc (gdbarch
,
3277 i386_supply_xstateregset
,
3278 i386_collect_xstateregset
);
3280 return tdep
->xstateregset
;
3287 /* Stuff for WIN32 PE style DLL's but is pretty generic really. */
3290 i386_pe_skip_trampoline_code (struct frame_info
*frame
,
3291 CORE_ADDR pc
, char *name
)
3293 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3294 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3297 if (pc
&& read_memory_unsigned_integer (pc
, 2, byte_order
) == 0x25ff)
3299 unsigned long indirect
=
3300 read_memory_unsigned_integer (pc
+ 2, 4, byte_order
);
3301 struct minimal_symbol
*indsym
=
3302 indirect
? lookup_minimal_symbol_by_pc (indirect
) : 0;
3303 const char *symname
= indsym
? SYMBOL_LINKAGE_NAME (indsym
) : 0;
3307 if (strncmp (symname
, "__imp_", 6) == 0
3308 || strncmp (symname
, "_imp_", 5) == 0)
3310 read_memory_unsigned_integer (indirect
, 4, byte_order
);
3313 return 0; /* Not a trampoline. */
3317 /* Return whether the THIS_FRAME corresponds to a sigtramp
3321 i386_sigtramp_p (struct frame_info
*this_frame
)
3323 CORE_ADDR pc
= get_frame_pc (this_frame
);
3326 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
3327 return (name
&& strcmp ("_sigtramp", name
) == 0);
3331 /* We have two flavours of disassembly. The machinery on this page
3332 deals with switching between those. */
3335 i386_print_insn (bfd_vma pc
, struct disassemble_info
*info
)
3337 gdb_assert (disassembly_flavor
== att_flavor
3338 || disassembly_flavor
== intel_flavor
);
3340 /* FIXME: kettenis/20020915: Until disassembler_options is properly
3341 constified, cast to prevent a compiler warning. */
3342 info
->disassembler_options
= (char *) disassembly_flavor
;
3344 return print_insn_i386 (pc
, info
);
3348 /* There are a few i386 architecture variants that differ only
3349 slightly from the generic i386 target. For now, we don't give them
3350 their own source file, but include them here. As a consequence,
3351 they'll always be included. */
3353 /* System V Release 4 (SVR4). */
3355 /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp
3359 i386_svr4_sigtramp_p (struct frame_info
*this_frame
)
3361 CORE_ADDR pc
= get_frame_pc (this_frame
);
3364 /* UnixWare uses _sigacthandler. The origin of the other symbols is
3365 currently unknown. */
3366 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
3367 return (name
&& (strcmp ("_sigreturn", name
) == 0
3368 || strcmp ("_sigacthandler", name
) == 0
3369 || strcmp ("sigvechandler", name
) == 0));
3372 /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the
3373 address of the associated sigcontext (ucontext) structure. */
3376 i386_svr4_sigcontext_addr (struct frame_info
*this_frame
)
3378 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3379 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3383 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
3384 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
3386 return read_memory_unsigned_integer (sp
+ 8, 4, byte_order
);
3391 /* Implementation of `gdbarch_stap_is_single_operand', as defined in
3395 i386_stap_is_single_operand (struct gdbarch
*gdbarch
, const char *s
)
3397 return (*s
== '$' /* Literal number. */
3398 || (isdigit (*s
) && s
[1] == '(' && s
[2] == '%') /* Displacement. */
3399 || (*s
== '(' && s
[1] == '%') /* Register indirection. */
3400 || (*s
== '%' && isalpha (s
[1]))); /* Register access. */
3403 /* Implementation of `gdbarch_stap_parse_special_token', as defined in
3407 i386_stap_parse_special_token (struct gdbarch
*gdbarch
,
3408 struct stap_parse_info
*p
)
3410 /* In order to parse special tokens, we use a state-machine that go
3411 through every known token and try to get a match. */
3415 THREE_ARG_DISPLACEMENT
,
3419 current_state
= TRIPLET
;
3421 /* The special tokens to be parsed here are:
3423 - `register base + (register index * size) + offset', as represented
3424 in `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'.
3426 - Operands of the form `-8+3+1(%rbp)', which must be interpreted as
3427 `*(-8 + 3 - 1 + (void *) $eax)'. */
3429 while (current_state
!= DONE
)
3431 const char *s
= p
->arg
;
3433 switch (current_state
)
3437 if (isdigit (*s
) || *s
== '-' || *s
== '+')
3441 long displacements
[3];
3456 displacements
[0] = strtol (s
, (char **) &s
, 10);
3458 if (*s
!= '+' && *s
!= '-')
3460 /* We are not dealing with a triplet. */
3473 displacements
[1] = strtol (s
, (char **) &s
, 10);
3475 if (*s
!= '+' && *s
!= '-')
3477 /* We are not dealing with a triplet. */
3490 displacements
[2] = strtol (s
, (char **) &s
, 10);
3492 if (*s
!= '(' || s
[1] != '%')
3498 while (isalnum (*s
))
3505 regname
= alloca (len
+ 1);
3507 strncpy (regname
, start
, len
);
3508 regname
[len
] = '\0';
3510 if (user_reg_map_name_to_regnum (gdbarch
,
3511 regname
, len
) == -1)
3512 error (_("Invalid register name `%s' "
3513 "on expression `%s'."),
3514 regname
, p
->saved_arg
);
3516 for (i
= 0; i
< 3; i
++)
3518 write_exp_elt_opcode (OP_LONG
);
3520 (builtin_type (gdbarch
)->builtin_long
);
3521 write_exp_elt_longcst (displacements
[i
]);
3522 write_exp_elt_opcode (OP_LONG
);
3524 write_exp_elt_opcode (UNOP_NEG
);
3527 write_exp_elt_opcode (OP_REGISTER
);
3530 write_exp_string (str
);
3531 write_exp_elt_opcode (OP_REGISTER
);
3533 write_exp_elt_opcode (UNOP_CAST
);
3534 write_exp_elt_type (builtin_type (gdbarch
)->builtin_data_ptr
);
3535 write_exp_elt_opcode (UNOP_CAST
);
3537 write_exp_elt_opcode (BINOP_ADD
);
3538 write_exp_elt_opcode (BINOP_ADD
);
3539 write_exp_elt_opcode (BINOP_ADD
);
3541 write_exp_elt_opcode (UNOP_CAST
);
3542 write_exp_elt_type (lookup_pointer_type (p
->arg_type
));
3543 write_exp_elt_opcode (UNOP_CAST
);
3545 write_exp_elt_opcode (UNOP_IND
);
3553 case THREE_ARG_DISPLACEMENT
:
3555 if (isdigit (*s
) || *s
== '(' || *s
== '-' || *s
== '+')
3557 int offset_minus
= 0;
3566 struct stoken base_token
, index_token
;
3576 if (offset_minus
&& !isdigit (*s
))
3580 offset
= strtol (s
, (char **) &s
, 10);
3582 if (*s
!= '(' || s
[1] != '%')
3588 while (isalnum (*s
))
3591 if (*s
!= ',' || s
[1] != '%')
3594 len_base
= s
- start
;
3595 base
= alloca (len_base
+ 1);
3596 strncpy (base
, start
, len_base
);
3597 base
[len_base
] = '\0';
3599 if (user_reg_map_name_to_regnum (gdbarch
,
3600 base
, len_base
) == -1)
3601 error (_("Invalid register name `%s' "
3602 "on expression `%s'."),
3603 base
, p
->saved_arg
);
3608 while (isalnum (*s
))
3611 len_index
= s
- start
;
3612 index
= alloca (len_index
+ 1);
3613 strncpy (index
, start
, len_index
);
3614 index
[len_index
] = '\0';
3616 if (user_reg_map_name_to_regnum (gdbarch
,
3617 index
, len_index
) == -1)
3618 error (_("Invalid register name `%s' "
3619 "on expression `%s'."),
3620 index
, p
->saved_arg
);
3622 if (*s
!= ',' && *s
!= ')')
3636 size
= strtol (s
, (char **) &s
, 10);
3646 write_exp_elt_opcode (OP_LONG
);
3648 (builtin_type (gdbarch
)->builtin_long
);
3649 write_exp_elt_longcst (offset
);
3650 write_exp_elt_opcode (OP_LONG
);
3652 write_exp_elt_opcode (UNOP_NEG
);
3655 write_exp_elt_opcode (OP_REGISTER
);
3656 base_token
.ptr
= base
;
3657 base_token
.length
= len_base
;
3658 write_exp_string (base_token
);
3659 write_exp_elt_opcode (OP_REGISTER
);
3662 write_exp_elt_opcode (BINOP_ADD
);
3664 write_exp_elt_opcode (OP_REGISTER
);
3665 index_token
.ptr
= index
;
3666 index_token
.length
= len_index
;
3667 write_exp_string (index_token
);
3668 write_exp_elt_opcode (OP_REGISTER
);
3672 write_exp_elt_opcode (OP_LONG
);
3674 (builtin_type (gdbarch
)->builtin_long
);
3675 write_exp_elt_longcst (size
);
3676 write_exp_elt_opcode (OP_LONG
);
3678 write_exp_elt_opcode (UNOP_NEG
);
3679 write_exp_elt_opcode (BINOP_MUL
);
3682 write_exp_elt_opcode (BINOP_ADD
);
3684 write_exp_elt_opcode (UNOP_CAST
);
3685 write_exp_elt_type (lookup_pointer_type (p
->arg_type
));
3686 write_exp_elt_opcode (UNOP_CAST
);
3688 write_exp_elt_opcode (UNOP_IND
);
3698 /* Advancing to the next state. */
3710 i386_elf_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
3712 /* We typically use stabs-in-ELF with the SVR4 register numbering. */
3713 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
3715 /* Registering SystemTap handlers. */
3716 set_gdbarch_stap_integer_prefix (gdbarch
, "$");
3717 set_gdbarch_stap_register_prefix (gdbarch
, "%");
3718 set_gdbarch_stap_register_indirection_prefix (gdbarch
, "(");
3719 set_gdbarch_stap_register_indirection_suffix (gdbarch
, ")");
3720 set_gdbarch_stap_is_single_operand (gdbarch
,
3721 i386_stap_is_single_operand
);
3722 set_gdbarch_stap_parse_special_token (gdbarch
,
3723 i386_stap_parse_special_token
);
3726 /* System V Release 4 (SVR4). */
3729 i386_svr4_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
3731 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3733 /* System V Release 4 uses ELF. */
3734 i386_elf_init_abi (info
, gdbarch
);
3736 /* System V Release 4 has shared libraries. */
3737 set_gdbarch_skip_trampoline_code (gdbarch
, find_solib_trampoline_target
);
3739 tdep
->sigtramp_p
= i386_svr4_sigtramp_p
;
3740 tdep
->sigcontext_addr
= i386_svr4_sigcontext_addr
;
3741 tdep
->sc_pc_offset
= 36 + 14 * 4;
3742 tdep
->sc_sp_offset
= 36 + 17 * 4;
3744 tdep
->jb_pc_offset
= 20;
3750 i386_go32_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
3752 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3754 /* DJGPP doesn't have any special frames for signal handlers. */
3755 tdep
->sigtramp_p
= NULL
;
3757 tdep
->jb_pc_offset
= 36;
3759 /* DJGPP does not support the SSE registers. */
3760 if (! tdesc_has_registers (info
.target_desc
))
3761 tdep
->tdesc
= tdesc_i386_mmx
;
3763 /* Native compiler is GCC, which uses the SVR4 register numbering
3764 even in COFF and STABS. See the comment in i386_gdbarch_init,
3765 before the calls to set_gdbarch_stab_reg_to_regnum and
3766 set_gdbarch_sdb_reg_to_regnum. */
3767 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
3768 set_gdbarch_sdb_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
3770 set_gdbarch_has_dos_based_file_system (gdbarch
, 1);
3774 /* i386 register groups. In addition to the normal groups, add "mmx"
3777 static struct reggroup
*i386_sse_reggroup
;
3778 static struct reggroup
*i386_mmx_reggroup
;
3781 i386_init_reggroups (void)
3783 i386_sse_reggroup
= reggroup_new ("sse", USER_REGGROUP
);
3784 i386_mmx_reggroup
= reggroup_new ("mmx", USER_REGGROUP
);
3788 i386_add_reggroups (struct gdbarch
*gdbarch
)
3790 reggroup_add (gdbarch
, i386_sse_reggroup
);
3791 reggroup_add (gdbarch
, i386_mmx_reggroup
);
3792 reggroup_add (gdbarch
, general_reggroup
);
3793 reggroup_add (gdbarch
, float_reggroup
);
3794 reggroup_add (gdbarch
, all_reggroup
);
3795 reggroup_add (gdbarch
, save_reggroup
);
3796 reggroup_add (gdbarch
, restore_reggroup
);
3797 reggroup_add (gdbarch
, vector_reggroup
);
3798 reggroup_add (gdbarch
, system_reggroup
);
3802 i386_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
3803 struct reggroup
*group
)
3805 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3806 int fp_regnum_p
, mmx_regnum_p
, xmm_regnum_p
, mxcsr_regnum_p
,
3807 ymm_regnum_p
, ymmh_regnum_p
;
3809 /* Don't include pseudo registers, except for MMX, in any register
3811 if (i386_byte_regnum_p (gdbarch
, regnum
))
3814 if (i386_word_regnum_p (gdbarch
, regnum
))
3817 if (i386_dword_regnum_p (gdbarch
, regnum
))
3820 mmx_regnum_p
= i386_mmx_regnum_p (gdbarch
, regnum
);
3821 if (group
== i386_mmx_reggroup
)
3822 return mmx_regnum_p
;
3824 xmm_regnum_p
= i386_xmm_regnum_p (gdbarch
, regnum
);
3825 mxcsr_regnum_p
= i386_mxcsr_regnum_p (gdbarch
, regnum
);
3826 if (group
== i386_sse_reggroup
)
3827 return xmm_regnum_p
|| mxcsr_regnum_p
;
3829 ymm_regnum_p
= i386_ymm_regnum_p (gdbarch
, regnum
);
3830 if (group
== vector_reggroup
)
3831 return (mmx_regnum_p
3835 && ((tdep
->xcr0
& I386_XSTATE_AVX_MASK
)
3836 == I386_XSTATE_SSE_MASK
)));
3838 fp_regnum_p
= (i386_fp_regnum_p (gdbarch
, regnum
)
3839 || i386_fpc_regnum_p (gdbarch
, regnum
));
3840 if (group
== float_reggroup
)
3843 /* For "info reg all", don't include upper YMM registers nor XMM
3844 registers when AVX is supported. */
3845 ymmh_regnum_p
= i386_ymmh_regnum_p (gdbarch
, regnum
);
3846 if (group
== all_reggroup
3848 && (tdep
->xcr0
& I386_XSTATE_AVX
))
3852 if (group
== general_reggroup
)
3853 return (!fp_regnum_p
3860 return default_register_reggroup_p (gdbarch
, regnum
, group
);
3864 /* Get the ARGIth function argument for the current function. */
3867 i386_fetch_pointer_argument (struct frame_info
*frame
, int argi
,
3870 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3871 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3872 CORE_ADDR sp
= get_frame_register_unsigned (frame
, I386_ESP_REGNUM
);
3873 return read_memory_unsigned_integer (sp
+ (4 * (argi
+ 1)), 4, byte_order
);
3877 i386_skip_permanent_breakpoint (struct regcache
*regcache
)
3879 CORE_ADDR current_pc
= regcache_read_pc (regcache
);
3881 /* On i386, breakpoint is exactly 1 byte long, so we just
3882 adjust the PC in the regcache. */
3884 regcache_write_pc (regcache
, current_pc
);
3888 #define PREFIX_REPZ 0x01
3889 #define PREFIX_REPNZ 0x02
3890 #define PREFIX_LOCK 0x04
3891 #define PREFIX_DATA 0x08
3892 #define PREFIX_ADDR 0x10
3904 /* i386 arith/logic operations */
3917 struct i386_record_s
3919 struct gdbarch
*gdbarch
;
3920 struct regcache
*regcache
;
3921 CORE_ADDR orig_addr
;
3927 uint8_t mod
, reg
, rm
;
3936 /* Parse the "modrm" part of the memory address irp->addr points at.
3937 Returns -1 if something goes wrong, 0 otherwise. */
3940 i386_record_modrm (struct i386_record_s
*irp
)
3942 struct gdbarch
*gdbarch
= irp
->gdbarch
;
3944 if (record_read_memory (gdbarch
, irp
->addr
, &irp
->modrm
, 1))
3948 irp
->mod
= (irp
->modrm
>> 6) & 3;
3949 irp
->reg
= (irp
->modrm
>> 3) & 7;
3950 irp
->rm
= irp
->modrm
& 7;
3955 /* Extract the memory address that the current instruction writes to,
3956 and return it in *ADDR. Return -1 if something goes wrong. */
3959 i386_record_lea_modrm_addr (struct i386_record_s
*irp
, uint64_t *addr
)
3961 struct gdbarch
*gdbarch
= irp
->gdbarch
;
3962 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3974 uint8_t base
= irp
->rm
;
3979 if (record_read_memory (gdbarch
, irp
->addr
, &byte
, 1))
3982 scale
= (byte
>> 6) & 3;
3983 index
= ((byte
>> 3) & 7) | irp
->rex_x
;
3991 if ((base
& 7) == 5)
3994 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 4))
3997 *addr
= extract_signed_integer (buf
, 4, byte_order
);
3998 if (irp
->regmap
[X86_RECORD_R8_REGNUM
] && !havesib
)
3999 *addr
+= irp
->addr
+ irp
->rip_offset
;
4003 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 1))
4006 *addr
= (int8_t) buf
[0];
4009 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 4))
4011 *addr
= extract_signed_integer (buf
, 4, byte_order
);
4019 if (base
== 4 && irp
->popl_esp_hack
)
4020 *addr
+= irp
->popl_esp_hack
;
4021 regcache_raw_read_unsigned (irp
->regcache
, irp
->regmap
[base
],
4024 if (irp
->aflag
== 2)
4029 *addr
= (uint32_t) (offset64
+ *addr
);
4031 if (havesib
&& (index
!= 4 || scale
!= 0))
4033 regcache_raw_read_unsigned (irp
->regcache
, irp
->regmap
[index
],
4035 if (irp
->aflag
== 2)
4036 *addr
+= offset64
<< scale
;
4038 *addr
= (uint32_t) (*addr
+ (offset64
<< scale
));
4049 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 2))
4052 *addr
= extract_signed_integer (buf
, 2, byte_order
);
4058 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 1))
4061 *addr
= (int8_t) buf
[0];
4064 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 2))
4067 *addr
= extract_signed_integer (buf
, 2, byte_order
);
4074 regcache_raw_read_unsigned (irp
->regcache
,
4075 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
4077 *addr
= (uint32_t) (*addr
+ offset64
);
4078 regcache_raw_read_unsigned (irp
->regcache
,
4079 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
4081 *addr
= (uint32_t) (*addr
+ offset64
);
4084 regcache_raw_read_unsigned (irp
->regcache
,
4085 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
4087 *addr
= (uint32_t) (*addr
+ offset64
);
4088 regcache_raw_read_unsigned (irp
->regcache
,
4089 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
4091 *addr
= (uint32_t) (*addr
+ offset64
);
4094 regcache_raw_read_unsigned (irp
->regcache
,
4095 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
4097 *addr
= (uint32_t) (*addr
+ offset64
);
4098 regcache_raw_read_unsigned (irp
->regcache
,
4099 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
4101 *addr
= (uint32_t) (*addr
+ offset64
);
4104 regcache_raw_read_unsigned (irp
->regcache
,
4105 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
4107 *addr
= (uint32_t) (*addr
+ offset64
);
4108 regcache_raw_read_unsigned (irp
->regcache
,
4109 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
4111 *addr
= (uint32_t) (*addr
+ offset64
);
4114 regcache_raw_read_unsigned (irp
->regcache
,
4115 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
4117 *addr
= (uint32_t) (*addr
+ offset64
);
4120 regcache_raw_read_unsigned (irp
->regcache
,
4121 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
4123 *addr
= (uint32_t) (*addr
+ offset64
);
4126 regcache_raw_read_unsigned (irp
->regcache
,
4127 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
4129 *addr
= (uint32_t) (*addr
+ offset64
);
4132 regcache_raw_read_unsigned (irp
->regcache
,
4133 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
4135 *addr
= (uint32_t) (*addr
+ offset64
);
4145 /* Record the address and contents of the memory that will be changed
4146 by the current instruction. Return -1 if something goes wrong, 0
4150 i386_record_lea_modrm (struct i386_record_s
*irp
)
4152 struct gdbarch
*gdbarch
= irp
->gdbarch
;
4155 if (irp
->override
>= 0)
4157 if (record_memory_query
)
4161 target_terminal_ours ();
4163 Process record ignores the memory change of instruction at address %s\n\
4164 because it can't get the value of the segment register.\n\
4165 Do you want to stop the program?"),
4166 paddress (gdbarch
, irp
->orig_addr
));
4167 target_terminal_inferior ();
4175 if (i386_record_lea_modrm_addr (irp
, &addr
))
4178 if (record_arch_list_add_mem (addr
, 1 << irp
->ot
))
4184 /* Record the effects of a push operation. Return -1 if something
4185 goes wrong, 0 otherwise. */
4188 i386_record_push (struct i386_record_s
*irp
, int size
)
4192 if (record_arch_list_add_reg (irp
->regcache
,
4193 irp
->regmap
[X86_RECORD_RESP_REGNUM
]))
4195 regcache_raw_read_unsigned (irp
->regcache
,
4196 irp
->regmap
[X86_RECORD_RESP_REGNUM
],
4198 if (record_arch_list_add_mem ((CORE_ADDR
) addr
- size
, size
))
4205 /* Defines contents to record. */
4206 #define I386_SAVE_FPU_REGS 0xfffd
4207 #define I386_SAVE_FPU_ENV 0xfffe
4208 #define I386_SAVE_FPU_ENV_REG_STACK 0xffff
4210 /* Record the values of the floating point registers which will be
4211 changed by the current instruction. Returns -1 if something is
4212 wrong, 0 otherwise. */
4214 static int i386_record_floats (struct gdbarch
*gdbarch
,
4215 struct i386_record_s
*ir
,
4218 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4221 /* Oza: Because of floating point insn push/pop of fpu stack is going to
4222 happen. Currently we store st0-st7 registers, but we need not store all
4223 registers all the time, in future we use ftag register and record only
4224 those who are not marked as an empty. */
4226 if (I386_SAVE_FPU_REGS
== iregnum
)
4228 for (i
= I387_ST0_REGNUM (tdep
); i
<= I387_ST0_REGNUM (tdep
) + 7; i
++)
4230 if (record_arch_list_add_reg (ir
->regcache
, i
))
4234 else if (I386_SAVE_FPU_ENV
== iregnum
)
4236 for (i
= I387_FCTRL_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
4238 if (record_arch_list_add_reg (ir
->regcache
, i
))
4242 else if (I386_SAVE_FPU_ENV_REG_STACK
== iregnum
)
4244 for (i
= I387_ST0_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
4246 if (record_arch_list_add_reg (ir
->regcache
, i
))
4250 else if ((iregnum
>= I387_ST0_REGNUM (tdep
)) &&
4251 (iregnum
<= I387_FOP_REGNUM (tdep
)))
4253 if (record_arch_list_add_reg (ir
->regcache
,iregnum
))
4258 /* Parameter error. */
4261 if(I386_SAVE_FPU_ENV
!= iregnum
)
4263 for (i
= I387_FCTRL_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
4265 if (record_arch_list_add_reg (ir
->regcache
, i
))
4272 /* Parse the current instruction, and record the values of the
4273 registers and memory that will be changed by the current
4274 instruction. Returns -1 if something goes wrong, 0 otherwise. */
4276 #define I386_RECORD_ARCH_LIST_ADD_REG(regnum) \
4277 record_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)])
4280 i386_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4281 CORE_ADDR input_addr
)
4283 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4289 gdb_byte buf
[MAX_REGISTER_SIZE
];
4290 struct i386_record_s ir
;
4291 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4296 memset (&ir
, 0, sizeof (struct i386_record_s
));
4297 ir
.regcache
= regcache
;
4298 ir
.addr
= input_addr
;
4299 ir
.orig_addr
= input_addr
;
4303 ir
.popl_esp_hack
= 0;
4304 ir
.regmap
= tdep
->record_regmap
;
4305 ir
.gdbarch
= gdbarch
;
4307 if (record_debug
> 1)
4308 fprintf_unfiltered (gdb_stdlog
, "Process record: i386_process_record "
4310 paddress (gdbarch
, ir
.addr
));
4315 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
4318 switch (opcode8
) /* Instruction prefixes */
4320 case REPE_PREFIX_OPCODE
:
4321 prefixes
|= PREFIX_REPZ
;
4323 case REPNE_PREFIX_OPCODE
:
4324 prefixes
|= PREFIX_REPNZ
;
4326 case LOCK_PREFIX_OPCODE
:
4327 prefixes
|= PREFIX_LOCK
;
4329 case CS_PREFIX_OPCODE
:
4330 ir
.override
= X86_RECORD_CS_REGNUM
;
4332 case SS_PREFIX_OPCODE
:
4333 ir
.override
= X86_RECORD_SS_REGNUM
;
4335 case DS_PREFIX_OPCODE
:
4336 ir
.override
= X86_RECORD_DS_REGNUM
;
4338 case ES_PREFIX_OPCODE
:
4339 ir
.override
= X86_RECORD_ES_REGNUM
;
4341 case FS_PREFIX_OPCODE
:
4342 ir
.override
= X86_RECORD_FS_REGNUM
;
4344 case GS_PREFIX_OPCODE
:
4345 ir
.override
= X86_RECORD_GS_REGNUM
;
4347 case DATA_PREFIX_OPCODE
:
4348 prefixes
|= PREFIX_DATA
;
4350 case ADDR_PREFIX_OPCODE
:
4351 prefixes
|= PREFIX_ADDR
;
4353 case 0x40: /* i386 inc %eax */
4354 case 0x41: /* i386 inc %ecx */
4355 case 0x42: /* i386 inc %edx */
4356 case 0x43: /* i386 inc %ebx */
4357 case 0x44: /* i386 inc %esp */
4358 case 0x45: /* i386 inc %ebp */
4359 case 0x46: /* i386 inc %esi */
4360 case 0x47: /* i386 inc %edi */
4361 case 0x48: /* i386 dec %eax */
4362 case 0x49: /* i386 dec %ecx */
4363 case 0x4a: /* i386 dec %edx */
4364 case 0x4b: /* i386 dec %ebx */
4365 case 0x4c: /* i386 dec %esp */
4366 case 0x4d: /* i386 dec %ebp */
4367 case 0x4e: /* i386 dec %esi */
4368 case 0x4f: /* i386 dec %edi */
4369 if (ir
.regmap
[X86_RECORD_R8_REGNUM
]) /* 64 bit target */
4373 rex_w
= (opcode8
>> 3) & 1;
4374 rex_r
= (opcode8
& 0x4) << 1;
4375 ir
.rex_x
= (opcode8
& 0x2) << 2;
4376 ir
.rex_b
= (opcode8
& 0x1) << 3;
4378 else /* 32 bit target */
4387 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && rex_w
== 1)
4393 if (prefixes
& PREFIX_DATA
)
4396 if (prefixes
& PREFIX_ADDR
)
4398 else if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4401 /* Now check op code. */
4402 opcode
= (uint32_t) opcode8
;
4407 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
4410 opcode
= (uint32_t) opcode8
| 0x0f00;
4414 case 0x00: /* arith & logic */
4462 if (((opcode
>> 3) & 7) != OP_CMPL
)
4464 if ((opcode
& 1) == 0)
4467 ir
.ot
= ir
.dflag
+ OT_WORD
;
4469 switch ((opcode
>> 1) & 3)
4471 case 0: /* OP Ev, Gv */
4472 if (i386_record_modrm (&ir
))
4476 if (i386_record_lea_modrm (&ir
))
4482 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4484 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4487 case 1: /* OP Gv, Ev */
4488 if (i386_record_modrm (&ir
))
4491 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4493 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4495 case 2: /* OP A, Iv */
4496 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4500 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4503 case 0x80: /* GRP1 */
4507 if (i386_record_modrm (&ir
))
4510 if (ir
.reg
!= OP_CMPL
)
4512 if ((opcode
& 1) == 0)
4515 ir
.ot
= ir
.dflag
+ OT_WORD
;
4522 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
4523 if (i386_record_lea_modrm (&ir
))
4527 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
4529 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4532 case 0x40: /* inc */
4541 case 0x48: /* dec */
4550 I386_RECORD_ARCH_LIST_ADD_REG (opcode
& 7);
4551 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4554 case 0xf6: /* GRP3 */
4556 if ((opcode
& 1) == 0)
4559 ir
.ot
= ir
.dflag
+ OT_WORD
;
4560 if (i386_record_modrm (&ir
))
4563 if (ir
.mod
!= 3 && ir
.reg
== 0)
4564 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
4569 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4575 if (i386_record_lea_modrm (&ir
))
4581 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4583 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4585 if (ir
.reg
== 3) /* neg */
4586 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4592 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4593 if (ir
.ot
!= OT_BYTE
)
4594 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
4595 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4599 opcode
= opcode
<< 8 | ir
.modrm
;
4605 case 0xfe: /* GRP4 */
4606 case 0xff: /* GRP5 */
4607 if (i386_record_modrm (&ir
))
4609 if (ir
.reg
>= 2 && opcode
== 0xfe)
4612 opcode
= opcode
<< 8 | ir
.modrm
;
4619 if ((opcode
& 1) == 0)
4622 ir
.ot
= ir
.dflag
+ OT_WORD
;
4625 if (i386_record_lea_modrm (&ir
))
4631 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4633 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4635 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4638 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4640 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4642 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4645 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
4646 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4648 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4652 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4655 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4657 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4662 opcode
= opcode
<< 8 | ir
.modrm
;
4668 case 0x84: /* test */
4672 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4675 case 0x98: /* CWDE/CBW */
4676 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4679 case 0x99: /* CDQ/CWD */
4680 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4681 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
4684 case 0x0faf: /* imul */
4687 ir
.ot
= ir
.dflag
+ OT_WORD
;
4688 if (i386_record_modrm (&ir
))
4691 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
4692 else if (opcode
== 0x6b)
4695 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4697 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4698 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4701 case 0x0fc0: /* xadd */
4703 if ((opcode
& 1) == 0)
4706 ir
.ot
= ir
.dflag
+ OT_WORD
;
4707 if (i386_record_modrm (&ir
))
4712 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4714 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4715 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4717 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4721 if (i386_record_lea_modrm (&ir
))
4723 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4725 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4727 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4730 case 0x0fb0: /* cmpxchg */
4732 if ((opcode
& 1) == 0)
4735 ir
.ot
= ir
.dflag
+ OT_WORD
;
4736 if (i386_record_modrm (&ir
))
4741 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4742 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4744 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4748 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4749 if (i386_record_lea_modrm (&ir
))
4752 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4755 case 0x0fc7: /* cmpxchg8b */
4756 if (i386_record_modrm (&ir
))
4761 opcode
= opcode
<< 8 | ir
.modrm
;
4764 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4765 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
4766 if (i386_record_lea_modrm (&ir
))
4768 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4771 case 0x50: /* push */
4781 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4783 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4787 case 0x06: /* push es */
4788 case 0x0e: /* push cs */
4789 case 0x16: /* push ss */
4790 case 0x1e: /* push ds */
4791 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4796 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4800 case 0x0fa0: /* push fs */
4801 case 0x0fa8: /* push gs */
4802 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4807 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4811 case 0x60: /* pusha */
4812 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4817 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 4)))
4821 case 0x58: /* pop */
4829 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4830 I386_RECORD_ARCH_LIST_ADD_REG ((opcode
& 0x7) | ir
.rex_b
);
4833 case 0x61: /* popa */
4834 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4839 for (regnum
= X86_RECORD_REAX_REGNUM
;
4840 regnum
<= X86_RECORD_REDI_REGNUM
;
4842 I386_RECORD_ARCH_LIST_ADD_REG (regnum
);
4845 case 0x8f: /* pop */
4846 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4847 ir
.ot
= ir
.dflag
? OT_QUAD
: OT_WORD
;
4849 ir
.ot
= ir
.dflag
+ OT_WORD
;
4850 if (i386_record_modrm (&ir
))
4853 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
4856 ir
.popl_esp_hack
= 1 << ir
.ot
;
4857 if (i386_record_lea_modrm (&ir
))
4860 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4863 case 0xc8: /* enter */
4864 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
4865 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4867 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4871 case 0xc9: /* leave */
4872 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4873 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
4876 case 0x07: /* pop es */
4877 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4882 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4883 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM
);
4884 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4887 case 0x17: /* pop ss */
4888 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4893 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4894 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM
);
4895 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4898 case 0x1f: /* pop ds */
4899 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4904 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4905 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM
);
4906 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4909 case 0x0fa1: /* pop fs */
4910 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4911 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM
);
4912 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4915 case 0x0fa9: /* pop gs */
4916 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4917 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM
);
4918 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4921 case 0x88: /* mov */
4925 if ((opcode
& 1) == 0)
4928 ir
.ot
= ir
.dflag
+ OT_WORD
;
4930 if (i386_record_modrm (&ir
))
4935 if (opcode
== 0xc6 || opcode
== 0xc7)
4936 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
4937 if (i386_record_lea_modrm (&ir
))
4942 if (opcode
== 0xc6 || opcode
== 0xc7)
4944 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4946 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4950 case 0x8a: /* mov */
4952 if ((opcode
& 1) == 0)
4955 ir
.ot
= ir
.dflag
+ OT_WORD
;
4956 if (i386_record_modrm (&ir
))
4959 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4961 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4964 case 0x8c: /* mov seg */
4965 if (i386_record_modrm (&ir
))
4970 opcode
= opcode
<< 8 | ir
.modrm
;
4975 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4979 if (i386_record_lea_modrm (&ir
))
4984 case 0x8e: /* mov seg */
4985 if (i386_record_modrm (&ir
))
4990 regnum
= X86_RECORD_ES_REGNUM
;
4993 regnum
= X86_RECORD_SS_REGNUM
;
4996 regnum
= X86_RECORD_DS_REGNUM
;
4999 regnum
= X86_RECORD_FS_REGNUM
;
5002 regnum
= X86_RECORD_GS_REGNUM
;
5006 opcode
= opcode
<< 8 | ir
.modrm
;
5010 I386_RECORD_ARCH_LIST_ADD_REG (regnum
);
5011 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5014 case 0x0fb6: /* movzbS */
5015 case 0x0fb7: /* movzwS */
5016 case 0x0fbe: /* movsbS */
5017 case 0x0fbf: /* movswS */
5018 if (i386_record_modrm (&ir
))
5020 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
5023 case 0x8d: /* lea */
5024 if (i386_record_modrm (&ir
))
5029 opcode
= opcode
<< 8 | ir
.modrm
;
5034 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5036 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
5039 case 0xa0: /* mov EAX */
5042 case 0xd7: /* xlat */
5043 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5046 case 0xa2: /* mov EAX */
5048 if (ir
.override
>= 0)
5050 if (record_memory_query
)
5054 target_terminal_ours ();
5056 Process record ignores the memory change of instruction at address %s\n\
5057 because it can't get the value of the segment register.\n\
5058 Do you want to stop the program?"),
5059 paddress (gdbarch
, ir
.orig_addr
));
5060 target_terminal_inferior ();
5067 if ((opcode
& 1) == 0)
5070 ir
.ot
= ir
.dflag
+ OT_WORD
;
5073 if (record_read_memory (gdbarch
, ir
.addr
, buf
, 8))
5076 addr
= extract_unsigned_integer (buf
, 8, byte_order
);
5080 if (record_read_memory (gdbarch
, ir
.addr
, buf
, 4))
5083 addr
= extract_unsigned_integer (buf
, 4, byte_order
);
5087 if (record_read_memory (gdbarch
, ir
.addr
, buf
, 2))
5090 addr
= extract_unsigned_integer (buf
, 2, byte_order
);
5092 if (record_arch_list_add_mem (addr
, 1 << ir
.ot
))
5097 case 0xb0: /* mov R, Ib */
5105 I386_RECORD_ARCH_LIST_ADD_REG ((ir
.regmap
[X86_RECORD_R8_REGNUM
])
5106 ? ((opcode
& 0x7) | ir
.rex_b
)
5107 : ((opcode
& 0x7) & 0x3));
5110 case 0xb8: /* mov R, Iv */
5118 I386_RECORD_ARCH_LIST_ADD_REG ((opcode
& 0x7) | ir
.rex_b
);
5121 case 0x91: /* xchg R, EAX */
5128 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5129 I386_RECORD_ARCH_LIST_ADD_REG (opcode
& 0x7);
5132 case 0x86: /* xchg Ev, Gv */
5134 if ((opcode
& 1) == 0)
5137 ir
.ot
= ir
.dflag
+ OT_WORD
;
5138 if (i386_record_modrm (&ir
))
5143 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5145 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
5149 if (i386_record_lea_modrm (&ir
))
5153 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5155 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
5158 case 0xc4: /* les Gv */
5159 case 0xc5: /* lds Gv */
5160 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5166 case 0x0fb2: /* lss Gv */
5167 case 0x0fb4: /* lfs Gv */
5168 case 0x0fb5: /* lgs Gv */
5169 if (i386_record_modrm (&ir
))
5177 opcode
= opcode
<< 8 | ir
.modrm
;
5182 case 0xc4: /* les Gv */
5183 regnum
= X86_RECORD_ES_REGNUM
;
5185 case 0xc5: /* lds Gv */
5186 regnum
= X86_RECORD_DS_REGNUM
;
5188 case 0x0fb2: /* lss Gv */
5189 regnum
= X86_RECORD_SS_REGNUM
;
5191 case 0x0fb4: /* lfs Gv */
5192 regnum
= X86_RECORD_FS_REGNUM
;
5194 case 0x0fb5: /* lgs Gv */
5195 regnum
= X86_RECORD_GS_REGNUM
;
5198 I386_RECORD_ARCH_LIST_ADD_REG (regnum
);
5199 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
5200 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5203 case 0xc0: /* shifts */
5209 if ((opcode
& 1) == 0)
5212 ir
.ot
= ir
.dflag
+ OT_WORD
;
5213 if (i386_record_modrm (&ir
))
5215 if (ir
.mod
!= 3 && (opcode
== 0xd2 || opcode
== 0xd3))
5217 if (i386_record_lea_modrm (&ir
))
5223 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5225 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
5227 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5234 if (i386_record_modrm (&ir
))
5238 if (record_arch_list_add_reg (ir
.regcache
, ir
.rm
))
5243 if (i386_record_lea_modrm (&ir
))
5248 case 0xd8: /* Floats. */
5256 if (i386_record_modrm (&ir
))
5258 ir
.reg
|= ((opcode
& 7) << 3);
5264 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
5272 /* For fcom, ficom nothing to do. */
5278 /* For fcomp, ficomp pop FPU stack, store all. */
5279 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5306 /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul,
5307 fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension
5308 of code, always affects st(0) register. */
5309 if (i386_record_floats (gdbarch
, &ir
, I387_ST0_REGNUM (tdep
)))
5333 /* Handling fld, fild. */
5334 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5338 switch (ir
.reg
>> 4)
5341 if (record_arch_list_add_mem (addr64
, 4))
5345 if (record_arch_list_add_mem (addr64
, 8))
5351 if (record_arch_list_add_mem (addr64
, 2))
5357 switch (ir
.reg
>> 4)
5360 if (record_arch_list_add_mem (addr64
, 4))
5362 if (3 == (ir
.reg
& 7))
5364 /* For fstp m32fp. */
5365 if (i386_record_floats (gdbarch
, &ir
,
5366 I386_SAVE_FPU_REGS
))
5371 if (record_arch_list_add_mem (addr64
, 4))
5373 if ((3 == (ir
.reg
& 7))
5374 || (5 == (ir
.reg
& 7))
5375 || (7 == (ir
.reg
& 7)))
5377 /* For fstp insn. */
5378 if (i386_record_floats (gdbarch
, &ir
,
5379 I386_SAVE_FPU_REGS
))
5384 if (record_arch_list_add_mem (addr64
, 8))
5386 if (3 == (ir
.reg
& 7))
5388 /* For fstp m64fp. */
5389 if (i386_record_floats (gdbarch
, &ir
,
5390 I386_SAVE_FPU_REGS
))
5395 if ((3 <= (ir
.reg
& 7)) && (6 <= (ir
.reg
& 7)))
5397 /* For fistp, fbld, fild, fbstp. */
5398 if (i386_record_floats (gdbarch
, &ir
,
5399 I386_SAVE_FPU_REGS
))
5404 if (record_arch_list_add_mem (addr64
, 2))
5413 if (i386_record_floats (gdbarch
, &ir
,
5414 I386_SAVE_FPU_ENV_REG_STACK
))
5419 if (i386_record_floats (gdbarch
, &ir
, I387_FCTRL_REGNUM (tdep
)))
5424 if (i386_record_floats (gdbarch
, &ir
,
5425 I386_SAVE_FPU_ENV_REG_STACK
))
5431 if (record_arch_list_add_mem (addr64
, 28))
5436 if (record_arch_list_add_mem (addr64
, 14))
5442 if (record_arch_list_add_mem (addr64
, 2))
5444 /* Insn fstp, fbstp. */
5445 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5450 if (record_arch_list_add_mem (addr64
, 10))
5456 if (record_arch_list_add_mem (addr64
, 28))
5462 if (record_arch_list_add_mem (addr64
, 14))
5466 if (record_arch_list_add_mem (addr64
, 80))
5469 if (i386_record_floats (gdbarch
, &ir
,
5470 I386_SAVE_FPU_ENV_REG_STACK
))
5474 if (record_arch_list_add_mem (addr64
, 8))
5477 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5482 opcode
= opcode
<< 8 | ir
.modrm
;
5487 /* Opcode is an extension of modR/M byte. */
5493 if (i386_record_floats (gdbarch
, &ir
, I387_ST0_REGNUM (tdep
)))
5497 if (0x0c == (ir
.modrm
>> 4))
5499 if ((ir
.modrm
& 0x0f) <= 7)
5501 if (i386_record_floats (gdbarch
, &ir
,
5502 I386_SAVE_FPU_REGS
))
5507 if (i386_record_floats (gdbarch
, &ir
,
5508 I387_ST0_REGNUM (tdep
)))
5510 /* If only st(0) is changing, then we have already
5512 if ((ir
.modrm
& 0x0f) - 0x08)
5514 if (i386_record_floats (gdbarch
, &ir
,
5515 I387_ST0_REGNUM (tdep
) +
5516 ((ir
.modrm
& 0x0f) - 0x08)))
5534 if (i386_record_floats (gdbarch
, &ir
,
5535 I387_ST0_REGNUM (tdep
)))
5553 if (i386_record_floats (gdbarch
, &ir
,
5554 I386_SAVE_FPU_REGS
))
5558 if (i386_record_floats (gdbarch
, &ir
,
5559 I387_ST0_REGNUM (tdep
)))
5561 if (i386_record_floats (gdbarch
, &ir
,
5562 I387_ST0_REGNUM (tdep
) + 1))
5569 if (0xe9 == ir
.modrm
)
5571 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5574 else if ((0x0c == ir
.modrm
>> 4) || (0x0d == ir
.modrm
>> 4))
5576 if (i386_record_floats (gdbarch
, &ir
,
5577 I387_ST0_REGNUM (tdep
)))
5579 if (((ir
.modrm
& 0x0f) > 0) && ((ir
.modrm
& 0x0f) <= 7))
5581 if (i386_record_floats (gdbarch
, &ir
,
5582 I387_ST0_REGNUM (tdep
) +
5586 else if ((ir
.modrm
& 0x0f) - 0x08)
5588 if (i386_record_floats (gdbarch
, &ir
,
5589 I387_ST0_REGNUM (tdep
) +
5590 ((ir
.modrm
& 0x0f) - 0x08)))
5596 if (0xe3 == ir
.modrm
)
5598 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_ENV
))
5601 else if ((0x0c == ir
.modrm
>> 4) || (0x0d == ir
.modrm
>> 4))
5603 if (i386_record_floats (gdbarch
, &ir
,
5604 I387_ST0_REGNUM (tdep
)))
5606 if (((ir
.modrm
& 0x0f) > 0) && ((ir
.modrm
& 0x0f) <= 7))
5608 if (i386_record_floats (gdbarch
, &ir
,
5609 I387_ST0_REGNUM (tdep
) +
5613 else if ((ir
.modrm
& 0x0f) - 0x08)
5615 if (i386_record_floats (gdbarch
, &ir
,
5616 I387_ST0_REGNUM (tdep
) +
5617 ((ir
.modrm
& 0x0f) - 0x08)))
5623 if ((0x0c == ir
.modrm
>> 4)
5624 || (0x0d == ir
.modrm
>> 4)
5625 || (0x0f == ir
.modrm
>> 4))
5627 if ((ir
.modrm
& 0x0f) <= 7)
5629 if (i386_record_floats (gdbarch
, &ir
,
5630 I387_ST0_REGNUM (tdep
) +
5636 if (i386_record_floats (gdbarch
, &ir
,
5637 I387_ST0_REGNUM (tdep
) +
5638 ((ir
.modrm
& 0x0f) - 0x08)))
5644 if (0x0c == ir
.modrm
>> 4)
5646 if (i386_record_floats (gdbarch
, &ir
,
5647 I387_FTAG_REGNUM (tdep
)))
5650 else if ((0x0d == ir
.modrm
>> 4) || (0x0e == ir
.modrm
>> 4))
5652 if ((ir
.modrm
& 0x0f) <= 7)
5654 if (i386_record_floats (gdbarch
, &ir
,
5655 I387_ST0_REGNUM (tdep
) +
5661 if (i386_record_floats (gdbarch
, &ir
,
5662 I386_SAVE_FPU_REGS
))
5668 if ((0x0c == ir
.modrm
>> 4)
5669 || (0x0e == ir
.modrm
>> 4)
5670 || (0x0f == ir
.modrm
>> 4)
5671 || (0xd9 == ir
.modrm
))
5673 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5678 if (0xe0 == ir
.modrm
)
5680 if (record_arch_list_add_reg (ir
.regcache
, I386_EAX_REGNUM
))
5683 else if ((0x0f == ir
.modrm
>> 4) || (0x0e == ir
.modrm
>> 4))
5685 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5693 case 0xa4: /* movsS */
5695 case 0xaa: /* stosS */
5697 case 0x6c: /* insS */
5699 regcache_raw_read_unsigned (ir
.regcache
,
5700 ir
.regmap
[X86_RECORD_RECX_REGNUM
],
5706 if ((opcode
& 1) == 0)
5709 ir
.ot
= ir
.dflag
+ OT_WORD
;
5710 regcache_raw_read_unsigned (ir
.regcache
,
5711 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
5714 regcache_raw_read_unsigned (ir
.regcache
,
5715 ir
.regmap
[X86_RECORD_ES_REGNUM
],
5717 regcache_raw_read_unsigned (ir
.regcache
,
5718 ir
.regmap
[X86_RECORD_DS_REGNUM
],
5720 if (ir
.aflag
&& (es
!= ds
))
5722 /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */
5723 if (record_memory_query
)
5727 target_terminal_ours ();
5729 Process record ignores the memory change of instruction at address %s\n\
5730 because it can't get the value of the segment register.\n\
5731 Do you want to stop the program?"),
5732 paddress (gdbarch
, ir
.orig_addr
));
5733 target_terminal_inferior ();
5740 if (record_arch_list_add_mem (addr
, 1 << ir
.ot
))
5744 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5745 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5746 if (opcode
== 0xa4 || opcode
== 0xa5)
5747 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
5748 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
5749 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5753 case 0xa6: /* cmpsS */
5755 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
5756 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
5757 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5758 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5759 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5762 case 0xac: /* lodsS */
5764 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5765 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
5766 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5767 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5768 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5771 case 0xae: /* scasS */
5773 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
5774 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5775 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5776 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5779 case 0x6e: /* outsS */
5781 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
5782 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5783 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5784 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5787 case 0xe4: /* port I/O */
5791 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5792 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5802 case 0xc2: /* ret im */
5803 case 0xc3: /* ret */
5804 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5805 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5808 case 0xca: /* lret im */
5809 case 0xcb: /* lret */
5810 case 0xcf: /* iret */
5811 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
5812 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5813 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5816 case 0xe8: /* call im */
5817 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5819 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5823 case 0x9a: /* lcall im */
5824 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5829 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
5830 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5834 case 0xe9: /* jmp im */
5835 case 0xea: /* ljmp im */
5836 case 0xeb: /* jmp Jb */
5837 case 0x70: /* jcc Jb */
5853 case 0x0f80: /* jcc Jv */
5871 case 0x0f90: /* setcc Gv */
5887 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5889 if (i386_record_modrm (&ir
))
5892 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rex_b
? (ir
.rm
| ir
.rex_b
)
5896 if (i386_record_lea_modrm (&ir
))
5901 case 0x0f40: /* cmov Gv, Ev */
5917 if (i386_record_modrm (&ir
))
5920 if (ir
.dflag
== OT_BYTE
)
5922 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
5926 case 0x9c: /* pushf */
5927 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5928 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5930 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5934 case 0x9d: /* popf */
5935 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5936 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5939 case 0x9e: /* sahf */
5940 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5946 case 0xf5: /* cmc */
5947 case 0xf8: /* clc */
5948 case 0xf9: /* stc */
5949 case 0xfc: /* cld */
5950 case 0xfd: /* std */
5951 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5954 case 0x9f: /* lahf */
5955 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5960 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5961 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5964 /* bit operations */
5965 case 0x0fba: /* bt/bts/btr/btc Gv, im */
5966 ir
.ot
= ir
.dflag
+ OT_WORD
;
5967 if (i386_record_modrm (&ir
))
5972 opcode
= opcode
<< 8 | ir
.modrm
;
5978 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5981 if (i386_record_lea_modrm (&ir
))
5985 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5988 case 0x0fa3: /* bt Gv, Ev */
5989 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5992 case 0x0fab: /* bts */
5993 case 0x0fb3: /* btr */
5994 case 0x0fbb: /* btc */
5995 ir
.ot
= ir
.dflag
+ OT_WORD
;
5996 if (i386_record_modrm (&ir
))
5999 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6003 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
6005 regcache_raw_read_unsigned (ir
.regcache
,
6006 ir
.regmap
[ir
.reg
| rex_r
],
6011 addr64
+= ((int16_t) addr
>> 4) << 4;
6014 addr64
+= ((int32_t) addr
>> 5) << 5;
6017 addr64
+= ((int64_t) addr
>> 6) << 6;
6020 if (record_arch_list_add_mem (addr64
, 1 << ir
.ot
))
6022 if (i386_record_lea_modrm (&ir
))
6025 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6028 case 0x0fbc: /* bsf */
6029 case 0x0fbd: /* bsr */
6030 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
6031 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6035 case 0x27: /* daa */
6036 case 0x2f: /* das */
6037 case 0x37: /* aaa */
6038 case 0x3f: /* aas */
6039 case 0xd4: /* aam */
6040 case 0xd5: /* aad */
6041 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6046 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6047 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6051 case 0x90: /* nop */
6052 if (prefixes
& PREFIX_LOCK
)
6059 case 0x9b: /* fwait */
6060 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
6062 opcode
= (uint32_t) opcode8
;
6068 case 0xcc: /* int3 */
6069 printf_unfiltered (_("Process record does not support instruction "
6076 case 0xcd: /* int */
6080 if (record_read_memory (gdbarch
, ir
.addr
, &interrupt
, 1))
6083 if (interrupt
!= 0x80
6084 || tdep
->i386_intx80_record
== NULL
)
6086 printf_unfiltered (_("Process record does not support "
6087 "instruction int 0x%02x.\n"),
6092 ret
= tdep
->i386_intx80_record (ir
.regcache
);
6099 case 0xce: /* into */
6100 printf_unfiltered (_("Process record does not support "
6101 "instruction into.\n"));
6106 case 0xfa: /* cli */
6107 case 0xfb: /* sti */
6110 case 0x62: /* bound */
6111 printf_unfiltered (_("Process record does not support "
6112 "instruction bound.\n"));
6117 case 0x0fc8: /* bswap reg */
6125 I386_RECORD_ARCH_LIST_ADD_REG ((opcode
& 7) | ir
.rex_b
);
6128 case 0xd6: /* salc */
6129 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6134 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6135 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6138 case 0xe0: /* loopnz */
6139 case 0xe1: /* loopz */
6140 case 0xe2: /* loop */
6141 case 0xe3: /* jecxz */
6142 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6143 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6146 case 0x0f30: /* wrmsr */
6147 printf_unfiltered (_("Process record does not support "
6148 "instruction wrmsr.\n"));
6153 case 0x0f32: /* rdmsr */
6154 printf_unfiltered (_("Process record does not support "
6155 "instruction rdmsr.\n"));
6160 case 0x0f31: /* rdtsc */
6161 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6162 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
6165 case 0x0f34: /* sysenter */
6168 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6173 if (tdep
->i386_sysenter_record
== NULL
)
6175 printf_unfiltered (_("Process record does not support "
6176 "instruction sysenter.\n"));
6180 ret
= tdep
->i386_sysenter_record (ir
.regcache
);
6186 case 0x0f35: /* sysexit */
6187 printf_unfiltered (_("Process record does not support "
6188 "instruction sysexit.\n"));
6193 case 0x0f05: /* syscall */
6196 if (tdep
->i386_syscall_record
== NULL
)
6198 printf_unfiltered (_("Process record does not support "
6199 "instruction syscall.\n"));
6203 ret
= tdep
->i386_syscall_record (ir
.regcache
);
6209 case 0x0f07: /* sysret */
6210 printf_unfiltered (_("Process record does not support "
6211 "instruction sysret.\n"));
6216 case 0x0fa2: /* cpuid */
6217 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6218 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6219 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
6220 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM
);
6223 case 0xf4: /* hlt */
6224 printf_unfiltered (_("Process record does not support "
6225 "instruction hlt.\n"));
6231 if (i386_record_modrm (&ir
))
6238 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6242 if (i386_record_lea_modrm (&ir
))
6251 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6255 opcode
= opcode
<< 8 | ir
.modrm
;
6262 if (i386_record_modrm (&ir
))
6273 opcode
= opcode
<< 8 | ir
.modrm
;
6276 if (ir
.override
>= 0)
6278 if (record_memory_query
)
6282 target_terminal_ours ();
6284 Process record ignores the memory change of instruction at address %s\n\
6285 because it can't get the value of the segment register.\n\
6286 Do you want to stop the program?"),
6287 paddress (gdbarch
, ir
.orig_addr
));
6288 target_terminal_inferior ();
6295 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
6297 if (record_arch_list_add_mem (addr64
, 2))
6300 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6302 if (record_arch_list_add_mem (addr64
, 8))
6307 if (record_arch_list_add_mem (addr64
, 4))
6318 case 0: /* monitor */
6321 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6325 opcode
= opcode
<< 8 | ir
.modrm
;
6333 if (ir
.override
>= 0)
6335 if (record_memory_query
)
6339 target_terminal_ours ();
6341 Process record ignores the memory change of instruction at address %s\n\
6342 because it can't get the value of the segment register.\n\
6343 Do you want to stop the program?"),
6344 paddress (gdbarch
, ir
.orig_addr
));
6345 target_terminal_inferior ();
6354 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
6356 if (record_arch_list_add_mem (addr64
, 2))
6359 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6361 if (record_arch_list_add_mem (addr64
, 8))
6366 if (record_arch_list_add_mem (addr64
, 4))
6378 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6379 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
6383 else if (ir
.rm
== 1)
6390 opcode
= opcode
<< 8 | ir
.modrm
;
6397 if (record_arch_list_add_reg (ir
.regcache
, ir
.rm
| ir
.rex_b
))
6403 if (i386_record_lea_modrm (&ir
))
6406 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6409 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6411 case 7: /* invlpg */
6414 if (ir
.rm
== 0 && ir
.regmap
[X86_RECORD_R8_REGNUM
])
6415 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM
);
6419 opcode
= opcode
<< 8 | ir
.modrm
;
6424 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6428 opcode
= opcode
<< 8 | ir
.modrm
;
6434 case 0x0f08: /* invd */
6435 case 0x0f09: /* wbinvd */
6438 case 0x63: /* arpl */
6439 if (i386_record_modrm (&ir
))
6441 if (ir
.mod
== 3 || ir
.regmap
[X86_RECORD_R8_REGNUM
])
6443 I386_RECORD_ARCH_LIST_ADD_REG (ir
.regmap
[X86_RECORD_R8_REGNUM
]
6444 ? (ir
.reg
| rex_r
) : ir
.rm
);
6448 ir
.ot
= ir
.dflag
? OT_LONG
: OT_WORD
;
6449 if (i386_record_lea_modrm (&ir
))
6452 if (!ir
.regmap
[X86_RECORD_R8_REGNUM
])
6453 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6456 case 0x0f02: /* lar */
6457 case 0x0f03: /* lsl */
6458 if (i386_record_modrm (&ir
))
6460 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
6461 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6465 if (i386_record_modrm (&ir
))
6467 if (ir
.mod
== 3 && ir
.reg
== 3)
6470 opcode
= opcode
<< 8 | ir
.modrm
;
6482 /* nop (multi byte) */
6485 case 0x0f20: /* mov reg, crN */
6486 case 0x0f22: /* mov crN, reg */
6487 if (i386_record_modrm (&ir
))
6489 if ((ir
.modrm
& 0xc0) != 0xc0)
6492 opcode
= opcode
<< 8 | ir
.modrm
;
6503 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6505 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6509 opcode
= opcode
<< 8 | ir
.modrm
;
6515 case 0x0f21: /* mov reg, drN */
6516 case 0x0f23: /* mov drN, reg */
6517 if (i386_record_modrm (&ir
))
6519 if ((ir
.modrm
& 0xc0) != 0xc0 || ir
.reg
== 4
6520 || ir
.reg
== 5 || ir
.reg
>= 8)
6523 opcode
= opcode
<< 8 | ir
.modrm
;
6527 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6529 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6532 case 0x0f06: /* clts */
6533 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6536 /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */
6538 case 0x0f0d: /* 3DNow! prefetch */
6541 case 0x0f0e: /* 3DNow! femms */
6542 case 0x0f77: /* emms */
6543 if (i386_fpc_regnum_p (gdbarch
, I387_FTAG_REGNUM(tdep
)))
6545 record_arch_list_add_reg (ir
.regcache
, I387_FTAG_REGNUM(tdep
));
6548 case 0x0f0f: /* 3DNow! data */
6549 if (i386_record_modrm (&ir
))
6551 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
6556 case 0x0c: /* 3DNow! pi2fw */
6557 case 0x0d: /* 3DNow! pi2fd */
6558 case 0x1c: /* 3DNow! pf2iw */
6559 case 0x1d: /* 3DNow! pf2id */
6560 case 0x8a: /* 3DNow! pfnacc */
6561 case 0x8e: /* 3DNow! pfpnacc */
6562 case 0x90: /* 3DNow! pfcmpge */
6563 case 0x94: /* 3DNow! pfmin */
6564 case 0x96: /* 3DNow! pfrcp */
6565 case 0x97: /* 3DNow! pfrsqrt */
6566 case 0x9a: /* 3DNow! pfsub */
6567 case 0x9e: /* 3DNow! pfadd */
6568 case 0xa0: /* 3DNow! pfcmpgt */
6569 case 0xa4: /* 3DNow! pfmax */
6570 case 0xa6: /* 3DNow! pfrcpit1 */
6571 case 0xa7: /* 3DNow! pfrsqit1 */
6572 case 0xaa: /* 3DNow! pfsubr */
6573 case 0xae: /* 3DNow! pfacc */
6574 case 0xb0: /* 3DNow! pfcmpeq */
6575 case 0xb4: /* 3DNow! pfmul */
6576 case 0xb6: /* 3DNow! pfrcpit2 */
6577 case 0xb7: /* 3DNow! pmulhrw */
6578 case 0xbb: /* 3DNow! pswapd */
6579 case 0xbf: /* 3DNow! pavgusb */
6580 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.reg
))
6581 goto no_support_3dnow_data
;
6582 record_arch_list_add_reg (ir
.regcache
, ir
.reg
);
6586 no_support_3dnow_data
:
6587 opcode
= (opcode
<< 8) | opcode8
;
6593 case 0x0faa: /* rsm */
6594 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6595 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6596 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6597 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
6598 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM
);
6599 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
6600 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
6601 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
6602 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
6606 if (i386_record_modrm (&ir
))
6610 case 0: /* fxsave */
6614 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6615 if (i386_record_lea_modrm_addr (&ir
, &tmpu64
))
6617 if (record_arch_list_add_mem (tmpu64
, 512))
6622 case 1: /* fxrstor */
6626 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6628 for (i
= I387_MM0_REGNUM (tdep
);
6629 i386_mmx_regnum_p (gdbarch
, i
); i
++)
6630 record_arch_list_add_reg (ir
.regcache
, i
);
6632 for (i
= I387_XMM0_REGNUM (tdep
);
6633 i386_xmm_regnum_p (gdbarch
, i
); i
++)
6634 record_arch_list_add_reg (ir
.regcache
, i
);
6636 if (i386_mxcsr_regnum_p (gdbarch
, I387_MXCSR_REGNUM(tdep
)))
6637 record_arch_list_add_reg (ir
.regcache
, I387_MXCSR_REGNUM(tdep
));
6639 for (i
= I387_ST0_REGNUM (tdep
);
6640 i386_fp_regnum_p (gdbarch
, i
); i
++)
6641 record_arch_list_add_reg (ir
.regcache
, i
);
6643 for (i
= I387_FCTRL_REGNUM (tdep
);
6644 i386_fpc_regnum_p (gdbarch
, i
); i
++)
6645 record_arch_list_add_reg (ir
.regcache
, i
);
6649 case 2: /* ldmxcsr */
6650 if (!i386_mxcsr_regnum_p (gdbarch
, I387_MXCSR_REGNUM(tdep
)))
6652 record_arch_list_add_reg (ir
.regcache
, I387_MXCSR_REGNUM(tdep
));
6655 case 3: /* stmxcsr */
6657 if (i386_record_lea_modrm (&ir
))
6661 case 5: /* lfence */
6662 case 6: /* mfence */
6663 case 7: /* sfence clflush */
6667 opcode
= (opcode
<< 8) | ir
.modrm
;
6673 case 0x0fc3: /* movnti */
6674 ir
.ot
= (ir
.dflag
== 2) ? OT_QUAD
: OT_LONG
;
6675 if (i386_record_modrm (&ir
))
6680 if (i386_record_lea_modrm (&ir
))
6684 /* Add prefix to opcode. */
6811 reswitch_prefix_add
:
6819 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
6822 opcode
= (uint32_t) opcode8
| opcode
<< 8;
6823 goto reswitch_prefix_add
;
6826 case 0x0f10: /* movups */
6827 case 0x660f10: /* movupd */
6828 case 0xf30f10: /* movss */
6829 case 0xf20f10: /* movsd */
6830 case 0x0f12: /* movlps */
6831 case 0x660f12: /* movlpd */
6832 case 0xf30f12: /* movsldup */
6833 case 0xf20f12: /* movddup */
6834 case 0x0f14: /* unpcklps */
6835 case 0x660f14: /* unpcklpd */
6836 case 0x0f15: /* unpckhps */
6837 case 0x660f15: /* unpckhpd */
6838 case 0x0f16: /* movhps */
6839 case 0x660f16: /* movhpd */
6840 case 0xf30f16: /* movshdup */
6841 case 0x0f28: /* movaps */
6842 case 0x660f28: /* movapd */
6843 case 0x0f2a: /* cvtpi2ps */
6844 case 0x660f2a: /* cvtpi2pd */
6845 case 0xf30f2a: /* cvtsi2ss */
6846 case 0xf20f2a: /* cvtsi2sd */
6847 case 0x0f2c: /* cvttps2pi */
6848 case 0x660f2c: /* cvttpd2pi */
6849 case 0x0f2d: /* cvtps2pi */
6850 case 0x660f2d: /* cvtpd2pi */
6851 case 0x660f3800: /* pshufb */
6852 case 0x660f3801: /* phaddw */
6853 case 0x660f3802: /* phaddd */
6854 case 0x660f3803: /* phaddsw */
6855 case 0x660f3804: /* pmaddubsw */
6856 case 0x660f3805: /* phsubw */
6857 case 0x660f3806: /* phsubd */
6858 case 0x660f3807: /* phsubsw */
6859 case 0x660f3808: /* psignb */
6860 case 0x660f3809: /* psignw */
6861 case 0x660f380a: /* psignd */
6862 case 0x660f380b: /* pmulhrsw */
6863 case 0x660f3810: /* pblendvb */
6864 case 0x660f3814: /* blendvps */
6865 case 0x660f3815: /* blendvpd */
6866 case 0x660f381c: /* pabsb */
6867 case 0x660f381d: /* pabsw */
6868 case 0x660f381e: /* pabsd */
6869 case 0x660f3820: /* pmovsxbw */
6870 case 0x660f3821: /* pmovsxbd */
6871 case 0x660f3822: /* pmovsxbq */
6872 case 0x660f3823: /* pmovsxwd */
6873 case 0x660f3824: /* pmovsxwq */
6874 case 0x660f3825: /* pmovsxdq */
6875 case 0x660f3828: /* pmuldq */
6876 case 0x660f3829: /* pcmpeqq */
6877 case 0x660f382a: /* movntdqa */
6878 case 0x660f3a08: /* roundps */
6879 case 0x660f3a09: /* roundpd */
6880 case 0x660f3a0a: /* roundss */
6881 case 0x660f3a0b: /* roundsd */
6882 case 0x660f3a0c: /* blendps */
6883 case 0x660f3a0d: /* blendpd */
6884 case 0x660f3a0e: /* pblendw */
6885 case 0x660f3a0f: /* palignr */
6886 case 0x660f3a20: /* pinsrb */
6887 case 0x660f3a21: /* insertps */
6888 case 0x660f3a22: /* pinsrd pinsrq */
6889 case 0x660f3a40: /* dpps */
6890 case 0x660f3a41: /* dppd */
6891 case 0x660f3a42: /* mpsadbw */
6892 case 0x660f3a60: /* pcmpestrm */
6893 case 0x660f3a61: /* pcmpestri */
6894 case 0x660f3a62: /* pcmpistrm */
6895 case 0x660f3a63: /* pcmpistri */
6896 case 0x0f51: /* sqrtps */
6897 case 0x660f51: /* sqrtpd */
6898 case 0xf20f51: /* sqrtsd */
6899 case 0xf30f51: /* sqrtss */
6900 case 0x0f52: /* rsqrtps */
6901 case 0xf30f52: /* rsqrtss */
6902 case 0x0f53: /* rcpps */
6903 case 0xf30f53: /* rcpss */
6904 case 0x0f54: /* andps */
6905 case 0x660f54: /* andpd */
6906 case 0x0f55: /* andnps */
6907 case 0x660f55: /* andnpd */
6908 case 0x0f56: /* orps */
6909 case 0x660f56: /* orpd */
6910 case 0x0f57: /* xorps */
6911 case 0x660f57: /* xorpd */
6912 case 0x0f58: /* addps */
6913 case 0x660f58: /* addpd */
6914 case 0xf20f58: /* addsd */
6915 case 0xf30f58: /* addss */
6916 case 0x0f59: /* mulps */
6917 case 0x660f59: /* mulpd */
6918 case 0xf20f59: /* mulsd */
6919 case 0xf30f59: /* mulss */
6920 case 0x0f5a: /* cvtps2pd */
6921 case 0x660f5a: /* cvtpd2ps */
6922 case 0xf20f5a: /* cvtsd2ss */
6923 case 0xf30f5a: /* cvtss2sd */
6924 case 0x0f5b: /* cvtdq2ps */
6925 case 0x660f5b: /* cvtps2dq */
6926 case 0xf30f5b: /* cvttps2dq */
6927 case 0x0f5c: /* subps */
6928 case 0x660f5c: /* subpd */
6929 case 0xf20f5c: /* subsd */
6930 case 0xf30f5c: /* subss */
6931 case 0x0f5d: /* minps */
6932 case 0x660f5d: /* minpd */
6933 case 0xf20f5d: /* minsd */
6934 case 0xf30f5d: /* minss */
6935 case 0x0f5e: /* divps */
6936 case 0x660f5e: /* divpd */
6937 case 0xf20f5e: /* divsd */
6938 case 0xf30f5e: /* divss */
6939 case 0x0f5f: /* maxps */
6940 case 0x660f5f: /* maxpd */
6941 case 0xf20f5f: /* maxsd */
6942 case 0xf30f5f: /* maxss */
6943 case 0x660f60: /* punpcklbw */
6944 case 0x660f61: /* punpcklwd */
6945 case 0x660f62: /* punpckldq */
6946 case 0x660f63: /* packsswb */
6947 case 0x660f64: /* pcmpgtb */
6948 case 0x660f65: /* pcmpgtw */
6949 case 0x660f66: /* pcmpgtd */
6950 case 0x660f67: /* packuswb */
6951 case 0x660f68: /* punpckhbw */
6952 case 0x660f69: /* punpckhwd */
6953 case 0x660f6a: /* punpckhdq */
6954 case 0x660f6b: /* packssdw */
6955 case 0x660f6c: /* punpcklqdq */
6956 case 0x660f6d: /* punpckhqdq */
6957 case 0x660f6e: /* movd */
6958 case 0x660f6f: /* movdqa */
6959 case 0xf30f6f: /* movdqu */
6960 case 0x660f70: /* pshufd */
6961 case 0xf20f70: /* pshuflw */
6962 case 0xf30f70: /* pshufhw */
6963 case 0x660f74: /* pcmpeqb */
6964 case 0x660f75: /* pcmpeqw */
6965 case 0x660f76: /* pcmpeqd */
6966 case 0x660f7c: /* haddpd */
6967 case 0xf20f7c: /* haddps */
6968 case 0x660f7d: /* hsubpd */
6969 case 0xf20f7d: /* hsubps */
6970 case 0xf30f7e: /* movq */
6971 case 0x0fc2: /* cmpps */
6972 case 0x660fc2: /* cmppd */
6973 case 0xf20fc2: /* cmpsd */
6974 case 0xf30fc2: /* cmpss */
6975 case 0x660fc4: /* pinsrw */
6976 case 0x0fc6: /* shufps */
6977 case 0x660fc6: /* shufpd */
6978 case 0x660fd0: /* addsubpd */
6979 case 0xf20fd0: /* addsubps */
6980 case 0x660fd1: /* psrlw */
6981 case 0x660fd2: /* psrld */
6982 case 0x660fd3: /* psrlq */
6983 case 0x660fd4: /* paddq */
6984 case 0x660fd5: /* pmullw */
6985 case 0xf30fd6: /* movq2dq */
6986 case 0x660fd8: /* psubusb */
6987 case 0x660fd9: /* psubusw */
6988 case 0x660fda: /* pminub */
6989 case 0x660fdb: /* pand */
6990 case 0x660fdc: /* paddusb */
6991 case 0x660fdd: /* paddusw */
6992 case 0x660fde: /* pmaxub */
6993 case 0x660fdf: /* pandn */
6994 case 0x660fe0: /* pavgb */
6995 case 0x660fe1: /* psraw */
6996 case 0x660fe2: /* psrad */
6997 case 0x660fe3: /* pavgw */
6998 case 0x660fe4: /* pmulhuw */
6999 case 0x660fe5: /* pmulhw */
7000 case 0x660fe6: /* cvttpd2dq */
7001 case 0xf20fe6: /* cvtpd2dq */
7002 case 0xf30fe6: /* cvtdq2pd */
7003 case 0x660fe8: /* psubsb */
7004 case 0x660fe9: /* psubsw */
7005 case 0x660fea: /* pminsw */
7006 case 0x660feb: /* por */
7007 case 0x660fec: /* paddsb */
7008 case 0x660fed: /* paddsw */
7009 case 0x660fee: /* pmaxsw */
7010 case 0x660fef: /* pxor */
7011 case 0xf20ff0: /* lddqu */
7012 case 0x660ff1: /* psllw */
7013 case 0x660ff2: /* pslld */
7014 case 0x660ff3: /* psllq */
7015 case 0x660ff4: /* pmuludq */
7016 case 0x660ff5: /* pmaddwd */
7017 case 0x660ff6: /* psadbw */
7018 case 0x660ff8: /* psubb */
7019 case 0x660ff9: /* psubw */
7020 case 0x660ffa: /* psubd */
7021 case 0x660ffb: /* psubq */
7022 case 0x660ffc: /* paddb */
7023 case 0x660ffd: /* paddw */
7024 case 0x660ffe: /* paddd */
7025 if (i386_record_modrm (&ir
))
7028 if (!i386_xmm_regnum_p (gdbarch
, I387_XMM0_REGNUM (tdep
) + ir
.reg
))
7030 record_arch_list_add_reg (ir
.regcache
,
7031 I387_XMM0_REGNUM (tdep
) + ir
.reg
);
7032 if ((opcode
& 0xfffffffc) == 0x660f3a60)
7033 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7036 case 0x0f11: /* movups */
7037 case 0x660f11: /* movupd */
7038 case 0xf30f11: /* movss */
7039 case 0xf20f11: /* movsd */
7040 case 0x0f13: /* movlps */
7041 case 0x660f13: /* movlpd */
7042 case 0x0f17: /* movhps */
7043 case 0x660f17: /* movhpd */
7044 case 0x0f29: /* movaps */
7045 case 0x660f29: /* movapd */
7046 case 0x660f3a14: /* pextrb */
7047 case 0x660f3a15: /* pextrw */
7048 case 0x660f3a16: /* pextrd pextrq */
7049 case 0x660f3a17: /* extractps */
7050 case 0x660f7f: /* movdqa */
7051 case 0xf30f7f: /* movdqu */
7052 if (i386_record_modrm (&ir
))
7056 if (opcode
== 0x0f13 || opcode
== 0x660f13
7057 || opcode
== 0x0f17 || opcode
== 0x660f17)
7060 if (!i386_xmm_regnum_p (gdbarch
,
7061 I387_XMM0_REGNUM (tdep
) + ir
.rm
))
7063 record_arch_list_add_reg (ir
.regcache
,
7064 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
7086 if (i386_record_lea_modrm (&ir
))
7091 case 0x0f2b: /* movntps */
7092 case 0x660f2b: /* movntpd */
7093 case 0x0fe7: /* movntq */
7094 case 0x660fe7: /* movntdq */
7097 if (opcode
== 0x0fe7)
7101 if (i386_record_lea_modrm (&ir
))
7105 case 0xf30f2c: /* cvttss2si */
7106 case 0xf20f2c: /* cvttsd2si */
7107 case 0xf30f2d: /* cvtss2si */
7108 case 0xf20f2d: /* cvtsd2si */
7109 case 0xf20f38f0: /* crc32 */
7110 case 0xf20f38f1: /* crc32 */
7111 case 0x0f50: /* movmskps */
7112 case 0x660f50: /* movmskpd */
7113 case 0x0fc5: /* pextrw */
7114 case 0x660fc5: /* pextrw */
7115 case 0x0fd7: /* pmovmskb */
7116 case 0x660fd7: /* pmovmskb */
7117 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
7120 case 0x0f3800: /* pshufb */
7121 case 0x0f3801: /* phaddw */
7122 case 0x0f3802: /* phaddd */
7123 case 0x0f3803: /* phaddsw */
7124 case 0x0f3804: /* pmaddubsw */
7125 case 0x0f3805: /* phsubw */
7126 case 0x0f3806: /* phsubd */
7127 case 0x0f3807: /* phsubsw */
7128 case 0x0f3808: /* psignb */
7129 case 0x0f3809: /* psignw */
7130 case 0x0f380a: /* psignd */
7131 case 0x0f380b: /* pmulhrsw */
7132 case 0x0f381c: /* pabsb */
7133 case 0x0f381d: /* pabsw */
7134 case 0x0f381e: /* pabsd */
7135 case 0x0f382b: /* packusdw */
7136 case 0x0f3830: /* pmovzxbw */
7137 case 0x0f3831: /* pmovzxbd */
7138 case 0x0f3832: /* pmovzxbq */
7139 case 0x0f3833: /* pmovzxwd */
7140 case 0x0f3834: /* pmovzxwq */
7141 case 0x0f3835: /* pmovzxdq */
7142 case 0x0f3837: /* pcmpgtq */
7143 case 0x0f3838: /* pminsb */
7144 case 0x0f3839: /* pminsd */
7145 case 0x0f383a: /* pminuw */
7146 case 0x0f383b: /* pminud */
7147 case 0x0f383c: /* pmaxsb */
7148 case 0x0f383d: /* pmaxsd */
7149 case 0x0f383e: /* pmaxuw */
7150 case 0x0f383f: /* pmaxud */
7151 case 0x0f3840: /* pmulld */
7152 case 0x0f3841: /* phminposuw */
7153 case 0x0f3a0f: /* palignr */
7154 case 0x0f60: /* punpcklbw */
7155 case 0x0f61: /* punpcklwd */
7156 case 0x0f62: /* punpckldq */
7157 case 0x0f63: /* packsswb */
7158 case 0x0f64: /* pcmpgtb */
7159 case 0x0f65: /* pcmpgtw */
7160 case 0x0f66: /* pcmpgtd */
7161 case 0x0f67: /* packuswb */
7162 case 0x0f68: /* punpckhbw */
7163 case 0x0f69: /* punpckhwd */
7164 case 0x0f6a: /* punpckhdq */
7165 case 0x0f6b: /* packssdw */
7166 case 0x0f6e: /* movd */
7167 case 0x0f6f: /* movq */
7168 case 0x0f70: /* pshufw */
7169 case 0x0f74: /* pcmpeqb */
7170 case 0x0f75: /* pcmpeqw */
7171 case 0x0f76: /* pcmpeqd */
7172 case 0x0fc4: /* pinsrw */
7173 case 0x0fd1: /* psrlw */
7174 case 0x0fd2: /* psrld */
7175 case 0x0fd3: /* psrlq */
7176 case 0x0fd4: /* paddq */
7177 case 0x0fd5: /* pmullw */
7178 case 0xf20fd6: /* movdq2q */
7179 case 0x0fd8: /* psubusb */
7180 case 0x0fd9: /* psubusw */
7181 case 0x0fda: /* pminub */
7182 case 0x0fdb: /* pand */
7183 case 0x0fdc: /* paddusb */
7184 case 0x0fdd: /* paddusw */
7185 case 0x0fde: /* pmaxub */
7186 case 0x0fdf: /* pandn */
7187 case 0x0fe0: /* pavgb */
7188 case 0x0fe1: /* psraw */
7189 case 0x0fe2: /* psrad */
7190 case 0x0fe3: /* pavgw */
7191 case 0x0fe4: /* pmulhuw */
7192 case 0x0fe5: /* pmulhw */
7193 case 0x0fe8: /* psubsb */
7194 case 0x0fe9: /* psubsw */
7195 case 0x0fea: /* pminsw */
7196 case 0x0feb: /* por */
7197 case 0x0fec: /* paddsb */
7198 case 0x0fed: /* paddsw */
7199 case 0x0fee: /* pmaxsw */
7200 case 0x0fef: /* pxor */
7201 case 0x0ff1: /* psllw */
7202 case 0x0ff2: /* pslld */
7203 case 0x0ff3: /* psllq */
7204 case 0x0ff4: /* pmuludq */
7205 case 0x0ff5: /* pmaddwd */
7206 case 0x0ff6: /* psadbw */
7207 case 0x0ff8: /* psubb */
7208 case 0x0ff9: /* psubw */
7209 case 0x0ffa: /* psubd */
7210 case 0x0ffb: /* psubq */
7211 case 0x0ffc: /* paddb */
7212 case 0x0ffd: /* paddw */
7213 case 0x0ffe: /* paddd */
7214 if (i386_record_modrm (&ir
))
7216 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.reg
))
7218 record_arch_list_add_reg (ir
.regcache
,
7219 I387_MM0_REGNUM (tdep
) + ir
.reg
);
7222 case 0x0f71: /* psllw */
7223 case 0x0f72: /* pslld */
7224 case 0x0f73: /* psllq */
7225 if (i386_record_modrm (&ir
))
7227 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.rm
))
7229 record_arch_list_add_reg (ir
.regcache
,
7230 I387_MM0_REGNUM (tdep
) + ir
.rm
);
7233 case 0x660f71: /* psllw */
7234 case 0x660f72: /* pslld */
7235 case 0x660f73: /* psllq */
7236 if (i386_record_modrm (&ir
))
7239 if (!i386_xmm_regnum_p (gdbarch
, I387_XMM0_REGNUM (tdep
) + ir
.rm
))
7241 record_arch_list_add_reg (ir
.regcache
,
7242 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
7245 case 0x0f7e: /* movd */
7246 case 0x660f7e: /* movd */
7247 if (i386_record_modrm (&ir
))
7250 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
7257 if (i386_record_lea_modrm (&ir
))
7262 case 0x0f7f: /* movq */
7263 if (i386_record_modrm (&ir
))
7267 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.rm
))
7269 record_arch_list_add_reg (ir
.regcache
,
7270 I387_MM0_REGNUM (tdep
) + ir
.rm
);
7275 if (i386_record_lea_modrm (&ir
))
7280 case 0xf30fb8: /* popcnt */
7281 if (i386_record_modrm (&ir
))
7283 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
7284 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7287 case 0x660fd6: /* movq */
7288 if (i386_record_modrm (&ir
))
7293 if (!i386_xmm_regnum_p (gdbarch
,
7294 I387_XMM0_REGNUM (tdep
) + ir
.rm
))
7296 record_arch_list_add_reg (ir
.regcache
,
7297 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
7302 if (i386_record_lea_modrm (&ir
))
7307 case 0x660f3817: /* ptest */
7308 case 0x0f2e: /* ucomiss */
7309 case 0x660f2e: /* ucomisd */
7310 case 0x0f2f: /* comiss */
7311 case 0x660f2f: /* comisd */
7312 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7315 case 0x0ff7: /* maskmovq */
7316 regcache_raw_read_unsigned (ir
.regcache
,
7317 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
7319 if (record_arch_list_add_mem (addr
, 64))
7323 case 0x660ff7: /* maskmovdqu */
7324 regcache_raw_read_unsigned (ir
.regcache
,
7325 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
7327 if (record_arch_list_add_mem (addr
, 128))
7342 /* In the future, maybe still need to deal with need_dasm. */
7343 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM
);
7344 if (record_arch_list_add_end ())
7350 printf_unfiltered (_("Process record does not support instruction 0x%02x "
7351 "at address %s.\n"),
7352 (unsigned int) (opcode
),
7353 paddress (gdbarch
, ir
.orig_addr
));
7357 static const int i386_record_regmap
[] =
7359 I386_EAX_REGNUM
, I386_ECX_REGNUM
, I386_EDX_REGNUM
, I386_EBX_REGNUM
,
7360 I386_ESP_REGNUM
, I386_EBP_REGNUM
, I386_ESI_REGNUM
, I386_EDI_REGNUM
,
7361 0, 0, 0, 0, 0, 0, 0, 0,
7362 I386_EIP_REGNUM
, I386_EFLAGS_REGNUM
, I386_CS_REGNUM
, I386_SS_REGNUM
,
7363 I386_DS_REGNUM
, I386_ES_REGNUM
, I386_FS_REGNUM
, I386_GS_REGNUM
7366 /* Check that the given address appears suitable for a fast
7367 tracepoint, which on x86-64 means that we need an instruction of at
7368 least 5 bytes, so that we can overwrite it with a 4-byte-offset
7369 jump and not have to worry about program jumps to an address in the
7370 middle of the tracepoint jump. On x86, it may be possible to use
7371 4-byte jumps with a 2-byte offset to a trampoline located in the
7372 bottom 64 KiB of memory. Returns 1 if OK, and writes a size
7373 of instruction to replace, and 0 if not, plus an explanatory
7377 i386_fast_tracepoint_valid_at (struct gdbarch
*gdbarch
,
7378 CORE_ADDR addr
, int *isize
, char **msg
)
7381 static struct ui_file
*gdb_null
= NULL
;
7383 /* Ask the target for the minimum instruction length supported. */
7384 jumplen
= target_get_min_fast_tracepoint_insn_len ();
7388 /* If the target does not support the get_min_fast_tracepoint_insn_len
7389 operation, assume that fast tracepoints will always be implemented
7390 using 4-byte relative jumps on both x86 and x86-64. */
7393 else if (jumplen
== 0)
7395 /* If the target does support get_min_fast_tracepoint_insn_len but
7396 returns zero, then the IPA has not loaded yet. In this case,
7397 we optimistically assume that truncated 2-byte relative jumps
7398 will be available on x86, and compensate later if this assumption
7399 turns out to be incorrect. On x86-64 architectures, 4-byte relative
7400 jumps will always be used. */
7401 jumplen
= (register_size (gdbarch
, 0) == 8) ? 5 : 4;
7404 /* Dummy file descriptor for the disassembler. */
7406 gdb_null
= ui_file_new ();
7408 /* Check for fit. */
7409 len
= gdb_print_insn (gdbarch
, addr
, gdb_null
, NULL
);
7415 /* Return a bit of target-specific detail to add to the caller's
7416 generic failure message. */
7418 *msg
= xstrprintf (_("; instruction is only %d bytes long, "
7419 "need at least %d bytes for the jump"),
7432 i386_validate_tdesc_p (struct gdbarch_tdep
*tdep
,
7433 struct tdesc_arch_data
*tdesc_data
)
7435 const struct target_desc
*tdesc
= tdep
->tdesc
;
7436 const struct tdesc_feature
*feature_core
;
7437 const struct tdesc_feature
*feature_sse
, *feature_avx
;
7438 int i
, num_regs
, valid_p
;
7440 if (! tdesc_has_registers (tdesc
))
7443 /* Get core registers. */
7444 feature_core
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.core");
7445 if (feature_core
== NULL
)
7448 /* Get SSE registers. */
7449 feature_sse
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.sse");
7451 /* Try AVX registers. */
7452 feature_avx
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx");
7456 /* The XCR0 bits. */
7459 /* AVX register description requires SSE register description. */
7463 tdep
->xcr0
= I386_XSTATE_AVX_MASK
;
7465 /* It may have been set by OSABI initialization function. */
7466 if (tdep
->num_ymm_regs
== 0)
7468 tdep
->ymmh_register_names
= i386_ymmh_names
;
7469 tdep
->num_ymm_regs
= 8;
7470 tdep
->ymm0h_regnum
= I386_YMM0H_REGNUM
;
7473 for (i
= 0; i
< tdep
->num_ymm_regs
; i
++)
7474 valid_p
&= tdesc_numbered_register (feature_avx
, tdesc_data
,
7475 tdep
->ymm0h_regnum
+ i
,
7476 tdep
->ymmh_register_names
[i
]);
7478 else if (feature_sse
)
7479 tdep
->xcr0
= I386_XSTATE_SSE_MASK
;
7482 tdep
->xcr0
= I386_XSTATE_X87_MASK
;
7483 tdep
->num_xmm_regs
= 0;
7486 num_regs
= tdep
->num_core_regs
;
7487 for (i
= 0; i
< num_regs
; i
++)
7488 valid_p
&= tdesc_numbered_register (feature_core
, tdesc_data
, i
,
7489 tdep
->register_names
[i
]);
7493 /* Need to include %mxcsr, so add one. */
7494 num_regs
+= tdep
->num_xmm_regs
+ 1;
7495 for (; i
< num_regs
; i
++)
7496 valid_p
&= tdesc_numbered_register (feature_sse
, tdesc_data
, i
,
7497 tdep
->register_names
[i
]);
7504 static struct gdbarch
*
7505 i386_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
7507 struct gdbarch_tdep
*tdep
;
7508 struct gdbarch
*gdbarch
;
7509 struct tdesc_arch_data
*tdesc_data
;
7510 const struct target_desc
*tdesc
;
7514 /* If there is already a candidate, use it. */
7515 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
7517 return arches
->gdbarch
;
7519 /* Allocate space for the new architecture. */
7520 tdep
= XCALLOC (1, struct gdbarch_tdep
);
7521 gdbarch
= gdbarch_alloc (&info
, tdep
);
7523 /* General-purpose registers. */
7524 tdep
->gregset
= NULL
;
7525 tdep
->gregset_reg_offset
= NULL
;
7526 tdep
->gregset_num_regs
= I386_NUM_GREGS
;
7527 tdep
->sizeof_gregset
= 0;
7529 /* Floating-point registers. */
7530 tdep
->fpregset
= NULL
;
7531 tdep
->sizeof_fpregset
= I387_SIZEOF_FSAVE
;
7533 tdep
->xstateregset
= NULL
;
7535 /* The default settings include the FPU registers, the MMX registers
7536 and the SSE registers. This can be overridden for a specific ABI
7537 by adjusting the members `st0_regnum', `mm0_regnum' and
7538 `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers
7539 will show up in the output of "info all-registers". */
7541 tdep
->st0_regnum
= I386_ST0_REGNUM
;
7543 /* I386_NUM_XREGS includes %mxcsr, so substract one. */
7544 tdep
->num_xmm_regs
= I386_NUM_XREGS
- 1;
7546 tdep
->jb_pc_offset
= -1;
7547 tdep
->struct_return
= pcc_struct_return
;
7548 tdep
->sigtramp_start
= 0;
7549 tdep
->sigtramp_end
= 0;
7550 tdep
->sigtramp_p
= i386_sigtramp_p
;
7551 tdep
->sigcontext_addr
= NULL
;
7552 tdep
->sc_reg_offset
= NULL
;
7553 tdep
->sc_pc_offset
= -1;
7554 tdep
->sc_sp_offset
= -1;
7556 tdep
->xsave_xcr0_offset
= -1;
7558 tdep
->record_regmap
= i386_record_regmap
;
7560 set_gdbarch_long_long_align_bit (gdbarch
, 32);
7562 /* The format used for `long double' on almost all i386 targets is
7563 the i387 extended floating-point format. In fact, of all targets
7564 in the GCC 2.95 tree, only OSF/1 does it different, and insists
7565 on having a `long double' that's not `long' at all. */
7566 set_gdbarch_long_double_format (gdbarch
, floatformats_i387_ext
);
7568 /* Although the i387 extended floating-point has only 80 significant
7569 bits, a `long double' actually takes up 96, probably to enforce
7571 set_gdbarch_long_double_bit (gdbarch
, 96);
7573 /* Register numbers of various important registers. */
7574 set_gdbarch_sp_regnum (gdbarch
, I386_ESP_REGNUM
); /* %esp */
7575 set_gdbarch_pc_regnum (gdbarch
, I386_EIP_REGNUM
); /* %eip */
7576 set_gdbarch_ps_regnum (gdbarch
, I386_EFLAGS_REGNUM
); /* %eflags */
7577 set_gdbarch_fp0_regnum (gdbarch
, I386_ST0_REGNUM
); /* %st(0) */
7579 /* NOTE: kettenis/20040418: GCC does have two possible register
7580 numbering schemes on the i386: dbx and SVR4. These schemes
7581 differ in how they number %ebp, %esp, %eflags, and the
7582 floating-point registers, and are implemented by the arrays
7583 dbx_register_map[] and svr4_dbx_register_map in
7584 gcc/config/i386.c. GCC also defines a third numbering scheme in
7585 gcc/config/i386.c, which it designates as the "default" register
7586 map used in 64bit mode. This last register numbering scheme is
7587 implemented in dbx64_register_map, and is used for AMD64; see
7590 Currently, each GCC i386 target always uses the same register
7591 numbering scheme across all its supported debugging formats
7592 i.e. SDB (COFF), stabs and DWARF 2. This is because
7593 gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the
7594 DBX_REGISTER_NUMBER macro which is defined by each target's
7595 respective config header in a manner independent of the requested
7596 output debugging format.
7598 This does not match the arrangement below, which presumes that
7599 the SDB and stabs numbering schemes differ from the DWARF and
7600 DWARF 2 ones. The reason for this arrangement is that it is
7601 likely to get the numbering scheme for the target's
7602 default/native debug format right. For targets where GCC is the
7603 native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for
7604 targets where the native toolchain uses a different numbering
7605 scheme for a particular debug format (stabs-in-ELF on Solaris)
7606 the defaults below will have to be overridden, like
7607 i386_elf_init_abi() does. */
7609 /* Use the dbx register numbering scheme for stabs and COFF. */
7610 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
7611 set_gdbarch_sdb_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
7613 /* Use the SVR4 register numbering scheme for DWARF 2. */
7614 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
7616 /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to
7617 be in use on any of the supported i386 targets. */
7619 set_gdbarch_print_float_info (gdbarch
, i387_print_float_info
);
7621 set_gdbarch_get_longjmp_target (gdbarch
, i386_get_longjmp_target
);
7623 /* Call dummy code. */
7624 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
7625 set_gdbarch_push_dummy_code (gdbarch
, i386_push_dummy_code
);
7626 set_gdbarch_push_dummy_call (gdbarch
, i386_push_dummy_call
);
7627 set_gdbarch_frame_align (gdbarch
, i386_frame_align
);
7629 set_gdbarch_convert_register_p (gdbarch
, i386_convert_register_p
);
7630 set_gdbarch_register_to_value (gdbarch
, i386_register_to_value
);
7631 set_gdbarch_value_to_register (gdbarch
, i386_value_to_register
);
7633 set_gdbarch_return_value (gdbarch
, i386_return_value
);
7635 set_gdbarch_skip_prologue (gdbarch
, i386_skip_prologue
);
7637 /* Stack grows downward. */
7638 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
7640 set_gdbarch_breakpoint_from_pc (gdbarch
, i386_breakpoint_from_pc
);
7641 set_gdbarch_decr_pc_after_break (gdbarch
, 1);
7642 set_gdbarch_max_insn_length (gdbarch
, I386_MAX_INSN_LEN
);
7644 set_gdbarch_frame_args_skip (gdbarch
, 8);
7646 set_gdbarch_print_insn (gdbarch
, i386_print_insn
);
7648 set_gdbarch_dummy_id (gdbarch
, i386_dummy_id
);
7650 set_gdbarch_unwind_pc (gdbarch
, i386_unwind_pc
);
7652 /* Add the i386 register groups. */
7653 i386_add_reggroups (gdbarch
);
7654 tdep
->register_reggroup_p
= i386_register_reggroup_p
;
7656 /* Helper for function argument information. */
7657 set_gdbarch_fetch_pointer_argument (gdbarch
, i386_fetch_pointer_argument
);
7659 /* Hook the function epilogue frame unwinder. This unwinder is
7660 appended to the list first, so that it supercedes the DWARF
7661 unwinder in function epilogues (where the DWARF unwinder
7662 currently fails). */
7663 frame_unwind_append_unwinder (gdbarch
, &i386_epilogue_frame_unwind
);
7665 /* Hook in the DWARF CFI frame unwinder. This unwinder is appended
7666 to the list before the prologue-based unwinders, so that DWARF
7667 CFI info will be used if it is available. */
7668 dwarf2_append_unwinders (gdbarch
);
7670 frame_base_set_default (gdbarch
, &i386_frame_base
);
7672 /* Pseudo registers may be changed by amd64_init_abi. */
7673 set_gdbarch_pseudo_register_read_value (gdbarch
,
7674 i386_pseudo_register_read_value
);
7675 set_gdbarch_pseudo_register_write (gdbarch
, i386_pseudo_register_write
);
7677 set_tdesc_pseudo_register_type (gdbarch
, i386_pseudo_register_type
);
7678 set_tdesc_pseudo_register_name (gdbarch
, i386_pseudo_register_name
);
7680 /* Override the normal target description method to make the AVX
7681 upper halves anonymous. */
7682 set_gdbarch_register_name (gdbarch
, i386_register_name
);
7684 /* Even though the default ABI only includes general-purpose registers,
7685 floating-point registers and the SSE registers, we have to leave a
7686 gap for the upper AVX registers. */
7687 set_gdbarch_num_regs (gdbarch
, I386_AVX_NUM_REGS
);
7689 /* Get the x86 target description from INFO. */
7690 tdesc
= info
.target_desc
;
7691 if (! tdesc_has_registers (tdesc
))
7693 tdep
->tdesc
= tdesc
;
7695 tdep
->num_core_regs
= I386_NUM_GREGS
+ I387_NUM_REGS
;
7696 tdep
->register_names
= i386_register_names
;
7698 /* No upper YMM registers. */
7699 tdep
->ymmh_register_names
= NULL
;
7700 tdep
->ymm0h_regnum
= -1;
7702 tdep
->num_byte_regs
= 8;
7703 tdep
->num_word_regs
= 8;
7704 tdep
->num_dword_regs
= 0;
7705 tdep
->num_mmx_regs
= 8;
7706 tdep
->num_ymm_regs
= 0;
7708 tdep
->sp_regnum_from_eax
= -1;
7709 tdep
->pc_regnum_from_eax
= -1;
7711 tdesc_data
= tdesc_data_alloc ();
7713 set_gdbarch_relocate_instruction (gdbarch
, i386_relocate_instruction
);
7715 set_gdbarch_gen_return_address (gdbarch
, i386_gen_return_address
);
7717 /* Hook in ABI-specific overrides, if they have been registered. */
7718 info
.tdep_info
= (void *) tdesc_data
;
7719 gdbarch_init_osabi (info
, gdbarch
);
7721 if (!i386_validate_tdesc_p (tdep
, tdesc_data
))
7723 tdesc_data_cleanup (tdesc_data
);
7725 gdbarch_free (gdbarch
);
7729 /* Wire in pseudo registers. Number of pseudo registers may be
7731 set_gdbarch_num_pseudo_regs (gdbarch
, (tdep
->num_byte_regs
7732 + tdep
->num_word_regs
7733 + tdep
->num_dword_regs
7734 + tdep
->num_mmx_regs
7735 + tdep
->num_ymm_regs
));
7737 /* Target description may be changed. */
7738 tdesc
= tdep
->tdesc
;
7740 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
7742 /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */
7743 set_gdbarch_register_reggroup_p (gdbarch
, tdep
->register_reggroup_p
);
7745 /* Make %al the first pseudo-register. */
7746 tdep
->al_regnum
= gdbarch_num_regs (gdbarch
);
7747 tdep
->ax_regnum
= tdep
->al_regnum
+ tdep
->num_byte_regs
;
7749 ymm0_regnum
= tdep
->ax_regnum
+ tdep
->num_word_regs
;
7750 if (tdep
->num_dword_regs
)
7752 /* Support dword pseudo-register if it hasn't been disabled. */
7753 tdep
->eax_regnum
= ymm0_regnum
;
7754 ymm0_regnum
+= tdep
->num_dword_regs
;
7755 if (tdep
->sp_regnum_from_eax
!= -1)
7756 set_gdbarch_sp_regnum (gdbarch
,
7758 + tdep
->sp_regnum_from_eax
));
7759 if (tdep
->pc_regnum_from_eax
!= -1)
7760 set_gdbarch_pc_regnum (gdbarch
,
7762 + tdep
->pc_regnum_from_eax
));
7765 tdep
->eax_regnum
= -1;
7767 mm0_regnum
= ymm0_regnum
;
7768 if (tdep
->num_ymm_regs
)
7770 /* Support YMM pseudo-register if it is available. */
7771 tdep
->ymm0_regnum
= ymm0_regnum
;
7772 mm0_regnum
+= tdep
->num_ymm_regs
;
7775 tdep
->ymm0_regnum
= -1;
7777 if (tdep
->num_mmx_regs
!= 0)
7779 /* Support MMX pseudo-register if MMX hasn't been disabled. */
7780 tdep
->mm0_regnum
= mm0_regnum
;
7783 tdep
->mm0_regnum
= -1;
7785 /* Hook in the legacy prologue-based unwinders last (fallback). */
7786 frame_unwind_append_unwinder (gdbarch
, &i386_stack_tramp_frame_unwind
);
7787 frame_unwind_append_unwinder (gdbarch
, &i386_sigtramp_frame_unwind
);
7788 frame_unwind_append_unwinder (gdbarch
, &i386_frame_unwind
);
7790 /* If we have a register mapping, enable the generic core file
7791 support, unless it has already been enabled. */
7792 if (tdep
->gregset_reg_offset
7793 && !gdbarch_regset_from_core_section_p (gdbarch
))
7794 set_gdbarch_regset_from_core_section (gdbarch
,
7795 i386_regset_from_core_section
);
7797 set_gdbarch_skip_permanent_breakpoint (gdbarch
,
7798 i386_skip_permanent_breakpoint
);
7800 set_gdbarch_fast_tracepoint_valid_at (gdbarch
,
7801 i386_fast_tracepoint_valid_at
);
7806 static enum gdb_osabi
7807 i386_coff_osabi_sniffer (bfd
*abfd
)
7809 if (strcmp (bfd_get_target (abfd
), "coff-go32-exe") == 0
7810 || strcmp (bfd_get_target (abfd
), "coff-go32") == 0)
7811 return GDB_OSABI_GO32
;
7813 return GDB_OSABI_UNKNOWN
;
7817 /* Provide a prototype to silence -Wmissing-prototypes. */
7818 void _initialize_i386_tdep (void);
7821 _initialize_i386_tdep (void)
7823 register_gdbarch_init (bfd_arch_i386
, i386_gdbarch_init
);
7825 /* Add the variable that controls the disassembly flavor. */
7826 add_setshow_enum_cmd ("disassembly-flavor", no_class
, valid_flavors
,
7827 &disassembly_flavor
, _("\
7828 Set the disassembly flavor."), _("\
7829 Show the disassembly flavor."), _("\
7830 The valid values are \"att\" and \"intel\", and the default value is \"att\"."),
7832 NULL
, /* FIXME: i18n: */
7833 &setlist
, &showlist
);
7835 /* Add the variable that controls the convention for returning
7837 add_setshow_enum_cmd ("struct-convention", no_class
, valid_conventions
,
7838 &struct_convention
, _("\
7839 Set the convention for returning small structs."), _("\
7840 Show the convention for returning small structs."), _("\
7841 Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\
7844 NULL
, /* FIXME: i18n: */
7845 &setlist
, &showlist
);
7847 gdbarch_register_osabi_sniffer (bfd_arch_i386
, bfd_target_coff_flavour
,
7848 i386_coff_osabi_sniffer
);
7850 gdbarch_register_osabi (bfd_arch_i386
, 0, GDB_OSABI_SVR4
,
7851 i386_svr4_init_abi
);
7852 gdbarch_register_osabi (bfd_arch_i386
, 0, GDB_OSABI_GO32
,
7853 i386_go32_init_abi
);
7855 /* Initialize the i386-specific register groups. */
7856 i386_init_reggroups ();
7858 /* Initialize the standard target descriptions. */
7859 initialize_tdesc_i386 ();
7860 initialize_tdesc_i386_mmx ();
7861 initialize_tdesc_i386_avx ();
7863 /* Tell remote stub that we support XML target description. */
7864 register_remote_support_xml ("i386");