1 /* Intel 386 target-dependent stuff.
3 Copyright (C) 1988-2013 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "opcode/i386.h"
22 #include "arch-utils.h"
24 #include "dummy-frame.h"
25 #include "dwarf2-frame.h"
28 #include "frame-base.h"
29 #include "frame-unwind.h"
37 #include "reggroups.h"
46 #include "exceptions.h"
47 #include "gdb_assert.h"
48 #include "gdb_string.h"
50 #include "i386-tdep.h"
51 #include "i387-tdep.h"
52 #include "i386-xstate.h"
55 #include "record-full.h"
58 #include "features/i386/i386.c"
59 #include "features/i386/i386-avx.c"
60 #include "features/i386/i386-mmx.c"
65 #include "stap-probe.h"
66 #include "user-regs.h"
67 #include "cli/cli-utils.h"
68 #include "expression.h"
69 #include "parser-defs.h"
74 static const char *i386_register_names
[] =
76 "eax", "ecx", "edx", "ebx",
77 "esp", "ebp", "esi", "edi",
78 "eip", "eflags", "cs", "ss",
79 "ds", "es", "fs", "gs",
80 "st0", "st1", "st2", "st3",
81 "st4", "st5", "st6", "st7",
82 "fctrl", "fstat", "ftag", "fiseg",
83 "fioff", "foseg", "fooff", "fop",
84 "xmm0", "xmm1", "xmm2", "xmm3",
85 "xmm4", "xmm5", "xmm6", "xmm7",
89 static const char *i386_ymm_names
[] =
91 "ymm0", "ymm1", "ymm2", "ymm3",
92 "ymm4", "ymm5", "ymm6", "ymm7",
95 static const char *i386_ymmh_names
[] =
97 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
98 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
101 /* Register names for MMX pseudo-registers. */
103 static const char *i386_mmx_names
[] =
105 "mm0", "mm1", "mm2", "mm3",
106 "mm4", "mm5", "mm6", "mm7"
109 /* Register names for byte pseudo-registers. */
111 static const char *i386_byte_names
[] =
113 "al", "cl", "dl", "bl",
114 "ah", "ch", "dh", "bh"
117 /* Register names for word pseudo-registers. */
119 static const char *i386_word_names
[] =
121 "ax", "cx", "dx", "bx",
128 i386_mmx_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
130 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
131 int mm0_regnum
= tdep
->mm0_regnum
;
136 regnum
-= mm0_regnum
;
137 return regnum
>= 0 && regnum
< tdep
->num_mmx_regs
;
143 i386_byte_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
145 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
147 regnum
-= tdep
->al_regnum
;
148 return regnum
>= 0 && regnum
< tdep
->num_byte_regs
;
154 i386_word_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
156 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
158 regnum
-= tdep
->ax_regnum
;
159 return regnum
>= 0 && regnum
< tdep
->num_word_regs
;
162 /* Dword register? */
165 i386_dword_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
167 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
168 int eax_regnum
= tdep
->eax_regnum
;
173 regnum
-= eax_regnum
;
174 return regnum
>= 0 && regnum
< tdep
->num_dword_regs
;
178 i386_ymmh_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
180 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
181 int ymm0h_regnum
= tdep
->ymm0h_regnum
;
183 if (ymm0h_regnum
< 0)
186 regnum
-= ymm0h_regnum
;
187 return regnum
>= 0 && regnum
< tdep
->num_ymm_regs
;
193 i386_ymm_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
195 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
196 int ymm0_regnum
= tdep
->ymm0_regnum
;
201 regnum
-= ymm0_regnum
;
202 return regnum
>= 0 && regnum
< tdep
->num_ymm_regs
;
208 i386_xmm_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
210 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
211 int num_xmm_regs
= I387_NUM_XMM_REGS (tdep
);
213 if (num_xmm_regs
== 0)
216 regnum
-= I387_XMM0_REGNUM (tdep
);
217 return regnum
>= 0 && regnum
< num_xmm_regs
;
221 i386_mxcsr_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
223 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
225 if (I387_NUM_XMM_REGS (tdep
) == 0)
228 return (regnum
== I387_MXCSR_REGNUM (tdep
));
234 i386_fp_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
236 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
238 if (I387_ST0_REGNUM (tdep
) < 0)
241 return (I387_ST0_REGNUM (tdep
) <= regnum
242 && regnum
< I387_FCTRL_REGNUM (tdep
));
246 i386_fpc_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
248 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
250 if (I387_ST0_REGNUM (tdep
) < 0)
253 return (I387_FCTRL_REGNUM (tdep
) <= regnum
254 && regnum
< I387_XMM0_REGNUM (tdep
));
257 /* Return the name of register REGNUM, or the empty string if it is
258 an anonymous register. */
261 i386_register_name (struct gdbarch
*gdbarch
, int regnum
)
263 /* Hide the upper YMM registers. */
264 if (i386_ymmh_regnum_p (gdbarch
, regnum
))
267 return tdesc_register_name (gdbarch
, regnum
);
270 /* Return the name of register REGNUM. */
273 i386_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
275 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
276 if (i386_mmx_regnum_p (gdbarch
, regnum
))
277 return i386_mmx_names
[regnum
- I387_MM0_REGNUM (tdep
)];
278 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
279 return i386_ymm_names
[regnum
- tdep
->ymm0_regnum
];
280 else if (i386_byte_regnum_p (gdbarch
, regnum
))
281 return i386_byte_names
[regnum
- tdep
->al_regnum
];
282 else if (i386_word_regnum_p (gdbarch
, regnum
))
283 return i386_word_names
[regnum
- tdep
->ax_regnum
];
285 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
288 /* Convert a dbx register number REG to the appropriate register
289 number used by GDB. */
292 i386_dbx_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
294 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
296 /* This implements what GCC calls the "default" register map
297 (dbx_register_map[]). */
299 if (reg
>= 0 && reg
<= 7)
301 /* General-purpose registers. The debug info calls %ebp
302 register 4, and %esp register 5. */
309 else if (reg
>= 12 && reg
<= 19)
311 /* Floating-point registers. */
312 return reg
- 12 + I387_ST0_REGNUM (tdep
);
314 else if (reg
>= 21 && reg
<= 28)
317 int ymm0_regnum
= tdep
->ymm0_regnum
;
320 && i386_xmm_regnum_p (gdbarch
, reg
))
321 return reg
- 21 + ymm0_regnum
;
323 return reg
- 21 + I387_XMM0_REGNUM (tdep
);
325 else if (reg
>= 29 && reg
<= 36)
328 return reg
- 29 + I387_MM0_REGNUM (tdep
);
331 /* This will hopefully provoke a warning. */
332 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
335 /* Convert SVR4 register number REG to the appropriate register number
339 i386_svr4_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
341 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
343 /* This implements the GCC register map that tries to be compatible
344 with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */
346 /* The SVR4 register numbering includes %eip and %eflags, and
347 numbers the floating point registers differently. */
348 if (reg
>= 0 && reg
<= 9)
350 /* General-purpose registers. */
353 else if (reg
>= 11 && reg
<= 18)
355 /* Floating-point registers. */
356 return reg
- 11 + I387_ST0_REGNUM (tdep
);
358 else if (reg
>= 21 && reg
<= 36)
360 /* The SSE and MMX registers have the same numbers as with dbx. */
361 return i386_dbx_reg_to_regnum (gdbarch
, reg
);
366 case 37: return I387_FCTRL_REGNUM (tdep
);
367 case 38: return I387_FSTAT_REGNUM (tdep
);
368 case 39: return I387_MXCSR_REGNUM (tdep
);
369 case 40: return I386_ES_REGNUM
;
370 case 41: return I386_CS_REGNUM
;
371 case 42: return I386_SS_REGNUM
;
372 case 43: return I386_DS_REGNUM
;
373 case 44: return I386_FS_REGNUM
;
374 case 45: return I386_GS_REGNUM
;
377 /* This will hopefully provoke a warning. */
378 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
383 /* This is the variable that is set with "set disassembly-flavor", and
384 its legitimate values. */
385 static const char att_flavor
[] = "att";
386 static const char intel_flavor
[] = "intel";
387 static const char *const valid_flavors
[] =
393 static const char *disassembly_flavor
= att_flavor
;
396 /* Use the program counter to determine the contents and size of a
397 breakpoint instruction. Return a pointer to a string of bytes that
398 encode a breakpoint instruction, store the length of the string in
399 *LEN and optionally adjust *PC to point to the correct memory
400 location for inserting the breakpoint.
402 On the i386 we have a single breakpoint that fits in a single byte
403 and can be inserted anywhere.
405 This function is 64-bit safe. */
407 static const gdb_byte
*
408 i386_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pc
, int *len
)
410 static gdb_byte break_insn
[] = { 0xcc }; /* int 3 */
412 *len
= sizeof (break_insn
);
416 /* Displaced instruction handling. */
418 /* Skip the legacy instruction prefixes in INSN.
419 Not all prefixes are valid for any particular insn
420 but we needn't care, the insn will fault if it's invalid.
421 The result is a pointer to the first opcode byte,
422 or NULL if we run off the end of the buffer. */
425 i386_skip_prefixes (gdb_byte
*insn
, size_t max_len
)
427 gdb_byte
*end
= insn
+ max_len
;
433 case DATA_PREFIX_OPCODE
:
434 case ADDR_PREFIX_OPCODE
:
435 case CS_PREFIX_OPCODE
:
436 case DS_PREFIX_OPCODE
:
437 case ES_PREFIX_OPCODE
:
438 case FS_PREFIX_OPCODE
:
439 case GS_PREFIX_OPCODE
:
440 case SS_PREFIX_OPCODE
:
441 case LOCK_PREFIX_OPCODE
:
442 case REPE_PREFIX_OPCODE
:
443 case REPNE_PREFIX_OPCODE
:
455 i386_absolute_jmp_p (const gdb_byte
*insn
)
457 /* jmp far (absolute address in operand). */
463 /* jump near, absolute indirect (/4). */
464 if ((insn
[1] & 0x38) == 0x20)
467 /* jump far, absolute indirect (/5). */
468 if ((insn
[1] & 0x38) == 0x28)
476 i386_absolute_call_p (const gdb_byte
*insn
)
478 /* call far, absolute. */
484 /* Call near, absolute indirect (/2). */
485 if ((insn
[1] & 0x38) == 0x10)
488 /* Call far, absolute indirect (/3). */
489 if ((insn
[1] & 0x38) == 0x18)
497 i386_ret_p (const gdb_byte
*insn
)
501 case 0xc2: /* ret near, pop N bytes. */
502 case 0xc3: /* ret near */
503 case 0xca: /* ret far, pop N bytes. */
504 case 0xcb: /* ret far */
505 case 0xcf: /* iret */
514 i386_call_p (const gdb_byte
*insn
)
516 if (i386_absolute_call_p (insn
))
519 /* call near, relative. */
526 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
527 length in bytes. Otherwise, return zero. */
530 i386_syscall_p (const gdb_byte
*insn
, int *lengthp
)
532 /* Is it 'int $0x80'? */
533 if ((insn
[0] == 0xcd && insn
[1] == 0x80)
534 /* Or is it 'sysenter'? */
535 || (insn
[0] == 0x0f && insn
[1] == 0x34)
536 /* Or is it 'syscall'? */
537 || (insn
[0] == 0x0f && insn
[1] == 0x05))
546 /* Some kernels may run one past a syscall insn, so we have to cope.
547 Otherwise this is just simple_displaced_step_copy_insn. */
549 struct displaced_step_closure
*
550 i386_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
551 CORE_ADDR from
, CORE_ADDR to
,
552 struct regcache
*regs
)
554 size_t len
= gdbarch_max_insn_length (gdbarch
);
555 gdb_byte
*buf
= xmalloc (len
);
557 read_memory (from
, buf
, len
);
559 /* GDB may get control back after the insn after the syscall.
560 Presumably this is a kernel bug.
561 If this is a syscall, make sure there's a nop afterwards. */
566 insn
= i386_skip_prefixes (buf
, len
);
567 if (insn
!= NULL
&& i386_syscall_p (insn
, &syscall_length
))
568 insn
[syscall_length
] = NOP_OPCODE
;
571 write_memory (to
, buf
, len
);
575 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
576 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
577 displaced_step_dump_bytes (gdb_stdlog
, buf
, len
);
580 return (struct displaced_step_closure
*) buf
;
583 /* Fix up the state of registers and memory after having single-stepped
584 a displaced instruction. */
587 i386_displaced_step_fixup (struct gdbarch
*gdbarch
,
588 struct displaced_step_closure
*closure
,
589 CORE_ADDR from
, CORE_ADDR to
,
590 struct regcache
*regs
)
592 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
594 /* The offset we applied to the instruction's address.
595 This could well be negative (when viewed as a signed 32-bit
596 value), but ULONGEST won't reflect that, so take care when
598 ULONGEST insn_offset
= to
- from
;
600 /* Since we use simple_displaced_step_copy_insn, our closure is a
601 copy of the instruction. */
602 gdb_byte
*insn
= (gdb_byte
*) closure
;
603 /* The start of the insn, needed in case we see some prefixes. */
604 gdb_byte
*insn_start
= insn
;
607 fprintf_unfiltered (gdb_stdlog
,
608 "displaced: fixup (%s, %s), "
609 "insn = 0x%02x 0x%02x ...\n",
610 paddress (gdbarch
, from
), paddress (gdbarch
, to
),
613 /* The list of issues to contend with here is taken from
614 resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20.
615 Yay for Free Software! */
617 /* Relocate the %eip, if necessary. */
619 /* The instruction recognizers we use assume any leading prefixes
620 have been skipped. */
622 /* This is the size of the buffer in closure. */
623 size_t max_insn_len
= gdbarch_max_insn_length (gdbarch
);
624 gdb_byte
*opcode
= i386_skip_prefixes (insn
, max_insn_len
);
625 /* If there are too many prefixes, just ignore the insn.
626 It will fault when run. */
631 /* Except in the case of absolute or indirect jump or call
632 instructions, or a return instruction, the new eip is relative to
633 the displaced instruction; make it relative. Well, signal
634 handler returns don't need relocation either, but we use the
635 value of %eip to recognize those; see below. */
636 if (! i386_absolute_jmp_p (insn
)
637 && ! i386_absolute_call_p (insn
)
638 && ! i386_ret_p (insn
))
643 regcache_cooked_read_unsigned (regs
, I386_EIP_REGNUM
, &orig_eip
);
645 /* A signal trampoline system call changes the %eip, resuming
646 execution of the main program after the signal handler has
647 returned. That makes them like 'return' instructions; we
648 shouldn't relocate %eip.
650 But most system calls don't, and we do need to relocate %eip.
652 Our heuristic for distinguishing these cases: if stepping
653 over the system call instruction left control directly after
654 the instruction, the we relocate --- control almost certainly
655 doesn't belong in the displaced copy. Otherwise, we assume
656 the instruction has put control where it belongs, and leave
657 it unrelocated. Goodness help us if there are PC-relative
659 if (i386_syscall_p (insn
, &insn_len
)
660 && orig_eip
!= to
+ (insn
- insn_start
) + insn_len
661 /* GDB can get control back after the insn after the syscall.
662 Presumably this is a kernel bug.
663 i386_displaced_step_copy_insn ensures its a nop,
664 we add one to the length for it. */
665 && orig_eip
!= to
+ (insn
- insn_start
) + insn_len
+ 1)
668 fprintf_unfiltered (gdb_stdlog
,
669 "displaced: syscall changed %%eip; "
674 ULONGEST eip
= (orig_eip
- insn_offset
) & 0xffffffffUL
;
676 /* If we just stepped over a breakpoint insn, we don't backup
677 the pc on purpose; this is to match behaviour without
680 regcache_cooked_write_unsigned (regs
, I386_EIP_REGNUM
, eip
);
683 fprintf_unfiltered (gdb_stdlog
,
685 "relocated %%eip from %s to %s\n",
686 paddress (gdbarch
, orig_eip
),
687 paddress (gdbarch
, eip
));
691 /* If the instruction was PUSHFL, then the TF bit will be set in the
692 pushed value, and should be cleared. We'll leave this for later,
693 since GDB already messes up the TF flag when stepping over a
696 /* If the instruction was a call, the return address now atop the
697 stack is the address following the copied instruction. We need
698 to make it the address following the original instruction. */
699 if (i386_call_p (insn
))
703 const ULONGEST retaddr_len
= 4;
705 regcache_cooked_read_unsigned (regs
, I386_ESP_REGNUM
, &esp
);
706 retaddr
= read_memory_unsigned_integer (esp
, retaddr_len
, byte_order
);
707 retaddr
= (retaddr
- insn_offset
) & 0xffffffffUL
;
708 write_memory_unsigned_integer (esp
, retaddr_len
, byte_order
, retaddr
);
711 fprintf_unfiltered (gdb_stdlog
,
712 "displaced: relocated return addr at %s to %s\n",
713 paddress (gdbarch
, esp
),
714 paddress (gdbarch
, retaddr
));
719 append_insns (CORE_ADDR
*to
, ULONGEST len
, const gdb_byte
*buf
)
721 target_write_memory (*to
, buf
, len
);
726 i386_relocate_instruction (struct gdbarch
*gdbarch
,
727 CORE_ADDR
*to
, CORE_ADDR oldloc
)
729 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
730 gdb_byte buf
[I386_MAX_INSN_LEN
];
731 int offset
= 0, rel32
, newrel
;
733 gdb_byte
*insn
= buf
;
735 read_memory (oldloc
, buf
, I386_MAX_INSN_LEN
);
737 insn_length
= gdb_buffered_insn_length (gdbarch
, insn
,
738 I386_MAX_INSN_LEN
, oldloc
);
740 /* Get past the prefixes. */
741 insn
= i386_skip_prefixes (insn
, I386_MAX_INSN_LEN
);
743 /* Adjust calls with 32-bit relative addresses as push/jump, with
744 the address pushed being the location where the original call in
745 the user program would return to. */
748 gdb_byte push_buf
[16];
749 unsigned int ret_addr
;
751 /* Where "ret" in the original code will return to. */
752 ret_addr
= oldloc
+ insn_length
;
753 push_buf
[0] = 0x68; /* pushq $... */
754 store_unsigned_integer (&push_buf
[1], 4, byte_order
, ret_addr
);
756 append_insns (to
, 5, push_buf
);
758 /* Convert the relative call to a relative jump. */
761 /* Adjust the destination offset. */
762 rel32
= extract_signed_integer (insn
+ 1, 4, byte_order
);
763 newrel
= (oldloc
- *to
) + rel32
;
764 store_signed_integer (insn
+ 1, 4, byte_order
, newrel
);
767 fprintf_unfiltered (gdb_stdlog
,
768 "Adjusted insn rel32=%s at %s to"
770 hex_string (rel32
), paddress (gdbarch
, oldloc
),
771 hex_string (newrel
), paddress (gdbarch
, *to
));
773 /* Write the adjusted jump into its displaced location. */
774 append_insns (to
, 5, insn
);
778 /* Adjust jumps with 32-bit relative addresses. Calls are already
782 /* Adjust conditional jumps. */
783 else if (insn
[0] == 0x0f && (insn
[1] & 0xf0) == 0x80)
788 rel32
= extract_signed_integer (insn
+ offset
, 4, byte_order
);
789 newrel
= (oldloc
- *to
) + rel32
;
790 store_signed_integer (insn
+ offset
, 4, byte_order
, newrel
);
792 fprintf_unfiltered (gdb_stdlog
,
793 "Adjusted insn rel32=%s at %s to"
795 hex_string (rel32
), paddress (gdbarch
, oldloc
),
796 hex_string (newrel
), paddress (gdbarch
, *to
));
799 /* Write the adjusted instructions into their displaced
801 append_insns (to
, insn_length
, buf
);
805 #ifdef I386_REGNO_TO_SYMMETRY
806 #error "The Sequent Symmetry is no longer supported."
809 /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi
810 and %esp "belong" to the calling function. Therefore these
811 registers should be saved if they're going to be modified. */
813 /* The maximum number of saved registers. This should include all
814 registers mentioned above, and %eip. */
815 #define I386_NUM_SAVED_REGS I386_NUM_GREGS
817 struct i386_frame_cache
825 /* Saved registers. */
826 CORE_ADDR saved_regs
[I386_NUM_SAVED_REGS
];
831 /* Stack space reserved for local variables. */
835 /* Allocate and initialize a frame cache. */
837 static struct i386_frame_cache
*
838 i386_alloc_frame_cache (void)
840 struct i386_frame_cache
*cache
;
843 cache
= FRAME_OBSTACK_ZALLOC (struct i386_frame_cache
);
848 cache
->sp_offset
= -4;
851 /* Saved registers. We initialize these to -1 since zero is a valid
852 offset (that's where %ebp is supposed to be stored). */
853 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
854 cache
->saved_regs
[i
] = -1;
856 cache
->saved_sp_reg
= -1;
857 cache
->pc_in_eax
= 0;
859 /* Frameless until proven otherwise. */
865 /* If the instruction at PC is a jump, return the address of its
866 target. Otherwise, return PC. */
869 i386_follow_jump (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
871 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
876 if (target_read_memory (pc
, &op
, 1))
882 op
= read_memory_unsigned_integer (pc
+ 1, 1, byte_order
);
888 /* Relative jump: if data16 == 0, disp32, else disp16. */
891 delta
= read_memory_integer (pc
+ 2, 2, byte_order
);
893 /* Include the size of the jmp instruction (including the
899 delta
= read_memory_integer (pc
+ 1, 4, byte_order
);
901 /* Include the size of the jmp instruction. */
906 /* Relative jump, disp8 (ignore data16). */
907 delta
= read_memory_integer (pc
+ data16
+ 1, 1, byte_order
);
916 /* Check whether PC points at a prologue for a function returning a
917 structure or union. If so, it updates CACHE and returns the
918 address of the first instruction after the code sequence that
919 removes the "hidden" argument from the stack or CURRENT_PC,
920 whichever is smaller. Otherwise, return PC. */
923 i386_analyze_struct_return (CORE_ADDR pc
, CORE_ADDR current_pc
,
924 struct i386_frame_cache
*cache
)
926 /* Functions that return a structure or union start with:
929 xchgl %eax, (%esp) 0x87 0x04 0x24
930 or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00
932 (the System V compiler puts out the second `xchg' instruction,
933 and the assembler doesn't try to optimize it, so the 'sib' form
934 gets generated). This sequence is used to get the address of the
935 return buffer for a function that returns a structure. */
936 static gdb_byte proto1
[3] = { 0x87, 0x04, 0x24 };
937 static gdb_byte proto2
[4] = { 0x87, 0x44, 0x24, 0x00 };
941 if (current_pc
<= pc
)
944 if (target_read_memory (pc
, &op
, 1))
947 if (op
!= 0x58) /* popl %eax */
950 if (target_read_memory (pc
+ 1, buf
, 4))
953 if (memcmp (buf
, proto1
, 3) != 0 && memcmp (buf
, proto2
, 4) != 0)
956 if (current_pc
== pc
)
958 cache
->sp_offset
+= 4;
962 if (current_pc
== pc
+ 1)
964 cache
->pc_in_eax
= 1;
968 if (buf
[1] == proto1
[1])
975 i386_skip_probe (CORE_ADDR pc
)
977 /* A function may start with
991 if (target_read_memory (pc
, &op
, 1))
994 if (op
== 0x68 || op
== 0x6a)
998 /* Skip past the `pushl' instruction; it has either a one-byte or a
999 four-byte operand, depending on the opcode. */
1005 /* Read the following 8 bytes, which should be `call _probe' (6
1006 bytes) followed by `addl $4,%esp' (2 bytes). */
1007 read_memory (pc
+ delta
, buf
, sizeof (buf
));
1008 if (buf
[0] == 0xe8 && buf
[6] == 0xc4 && buf
[7] == 0x4)
1009 pc
+= delta
+ sizeof (buf
);
1015 /* GCC 4.1 and later, can put code in the prologue to realign the
1016 stack pointer. Check whether PC points to such code, and update
1017 CACHE accordingly. Return the first instruction after the code
1018 sequence or CURRENT_PC, whichever is smaller. If we don't
1019 recognize the code, return PC. */
1022 i386_analyze_stack_align (CORE_ADDR pc
, CORE_ADDR current_pc
,
1023 struct i386_frame_cache
*cache
)
1025 /* There are 2 code sequences to re-align stack before the frame
1028 1. Use a caller-saved saved register:
1034 2. Use a callee-saved saved register:
1041 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
1043 0x83 0xe4 0xf0 andl $-16, %esp
1044 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
1049 int offset
, offset_and
;
1050 static int regnums
[8] = {
1051 I386_EAX_REGNUM
, /* %eax */
1052 I386_ECX_REGNUM
, /* %ecx */
1053 I386_EDX_REGNUM
, /* %edx */
1054 I386_EBX_REGNUM
, /* %ebx */
1055 I386_ESP_REGNUM
, /* %esp */
1056 I386_EBP_REGNUM
, /* %ebp */
1057 I386_ESI_REGNUM
, /* %esi */
1058 I386_EDI_REGNUM
/* %edi */
1061 if (target_read_memory (pc
, buf
, sizeof buf
))
1064 /* Check caller-saved saved register. The first instruction has
1065 to be "leal 4(%esp), %reg". */
1066 if (buf
[0] == 0x8d && buf
[2] == 0x24 && buf
[3] == 0x4)
1068 /* MOD must be binary 10 and R/M must be binary 100. */
1069 if ((buf
[1] & 0xc7) != 0x44)
1072 /* REG has register number. */
1073 reg
= (buf
[1] >> 3) & 7;
1078 /* Check callee-saved saved register. The first instruction
1079 has to be "pushl %reg". */
1080 if ((buf
[0] & 0xf8) != 0x50)
1086 /* The next instruction has to be "leal 8(%esp), %reg". */
1087 if (buf
[1] != 0x8d || buf
[3] != 0x24 || buf
[4] != 0x8)
1090 /* MOD must be binary 10 and R/M must be binary 100. */
1091 if ((buf
[2] & 0xc7) != 0x44)
1094 /* REG has register number. Registers in pushl and leal have to
1096 if (reg
!= ((buf
[2] >> 3) & 7))
1102 /* Rigister can't be %esp nor %ebp. */
1103 if (reg
== 4 || reg
== 5)
1106 /* The next instruction has to be "andl $-XXX, %esp". */
1107 if (buf
[offset
+ 1] != 0xe4
1108 || (buf
[offset
] != 0x81 && buf
[offset
] != 0x83))
1111 offset_and
= offset
;
1112 offset
+= buf
[offset
] == 0x81 ? 6 : 3;
1114 /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is
1115 0xfc. REG must be binary 110 and MOD must be binary 01. */
1116 if (buf
[offset
] != 0xff
1117 || buf
[offset
+ 2] != 0xfc
1118 || (buf
[offset
+ 1] & 0xf8) != 0x70)
1121 /* R/M has register. Registers in leal and pushl have to be the
1123 if (reg
!= (buf
[offset
+ 1] & 7))
1126 if (current_pc
> pc
+ offset_and
)
1127 cache
->saved_sp_reg
= regnums
[reg
];
1129 return min (pc
+ offset
+ 3, current_pc
);
1132 /* Maximum instruction length we need to handle. */
1133 #define I386_MAX_MATCHED_INSN_LEN 6
1135 /* Instruction description. */
1139 gdb_byte insn
[I386_MAX_MATCHED_INSN_LEN
];
1140 gdb_byte mask
[I386_MAX_MATCHED_INSN_LEN
];
1143 /* Return whether instruction at PC matches PATTERN. */
1146 i386_match_pattern (CORE_ADDR pc
, struct i386_insn pattern
)
1150 if (target_read_memory (pc
, &op
, 1))
1153 if ((op
& pattern
.mask
[0]) == pattern
.insn
[0])
1155 gdb_byte buf
[I386_MAX_MATCHED_INSN_LEN
- 1];
1156 int insn_matched
= 1;
1159 gdb_assert (pattern
.len
> 1);
1160 gdb_assert (pattern
.len
<= I386_MAX_MATCHED_INSN_LEN
);
1162 if (target_read_memory (pc
+ 1, buf
, pattern
.len
- 1))
1165 for (i
= 1; i
< pattern
.len
; i
++)
1167 if ((buf
[i
- 1] & pattern
.mask
[i
]) != pattern
.insn
[i
])
1170 return insn_matched
;
1175 /* Search for the instruction at PC in the list INSN_PATTERNS. Return
1176 the first instruction description that matches. Otherwise, return
1179 static struct i386_insn
*
1180 i386_match_insn (CORE_ADDR pc
, struct i386_insn
*insn_patterns
)
1182 struct i386_insn
*pattern
;
1184 for (pattern
= insn_patterns
; pattern
->len
> 0; pattern
++)
1186 if (i386_match_pattern (pc
, *pattern
))
1193 /* Return whether PC points inside a sequence of instructions that
1194 matches INSN_PATTERNS. */
1197 i386_match_insn_block (CORE_ADDR pc
, struct i386_insn
*insn_patterns
)
1199 CORE_ADDR current_pc
;
1201 struct i386_insn
*insn
;
1203 insn
= i386_match_insn (pc
, insn_patterns
);
1208 ix
= insn
- insn_patterns
;
1209 for (i
= ix
- 1; i
>= 0; i
--)
1211 current_pc
-= insn_patterns
[i
].len
;
1213 if (!i386_match_pattern (current_pc
, insn_patterns
[i
]))
1217 current_pc
= pc
+ insn
->len
;
1218 for (insn
= insn_patterns
+ ix
+ 1; insn
->len
> 0; insn
++)
1220 if (!i386_match_pattern (current_pc
, *insn
))
1223 current_pc
+= insn
->len
;
1229 /* Some special instructions that might be migrated by GCC into the
1230 part of the prologue that sets up the new stack frame. Because the
1231 stack frame hasn't been setup yet, no registers have been saved
1232 yet, and only the scratch registers %eax, %ecx and %edx can be
1235 struct i386_insn i386_frame_setup_skip_insns
[] =
1237 /* Check for `movb imm8, r' and `movl imm32, r'.
1239 ??? Should we handle 16-bit operand-sizes here? */
1241 /* `movb imm8, %al' and `movb imm8, %ah' */
1242 /* `movb imm8, %cl' and `movb imm8, %ch' */
1243 { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } },
1244 /* `movb imm8, %dl' and `movb imm8, %dh' */
1245 { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } },
1246 /* `movl imm32, %eax' and `movl imm32, %ecx' */
1247 { 5, { 0xb8 }, { 0xfe } },
1248 /* `movl imm32, %edx' */
1249 { 5, { 0xba }, { 0xff } },
1251 /* Check for `mov imm32, r32'. Note that there is an alternative
1252 encoding for `mov m32, %eax'.
1254 ??? Should we handle SIB adressing here?
1255 ??? Should we handle 16-bit operand-sizes here? */
1257 /* `movl m32, %eax' */
1258 { 5, { 0xa1 }, { 0xff } },
1259 /* `movl m32, %eax' and `mov; m32, %ecx' */
1260 { 6, { 0x89, 0x05 }, {0xff, 0xf7 } },
1261 /* `movl m32, %edx' */
1262 { 6, { 0x89, 0x15 }, {0xff, 0xff } },
1264 /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'.
1265 Because of the symmetry, there are actually two ways to encode
1266 these instructions; opcode bytes 0x29 and 0x2b for `subl' and
1267 opcode bytes 0x31 and 0x33 for `xorl'. */
1269 /* `subl %eax, %eax' */
1270 { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } },
1271 /* `subl %ecx, %ecx' */
1272 { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } },
1273 /* `subl %edx, %edx' */
1274 { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } },
1275 /* `xorl %eax, %eax' */
1276 { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } },
1277 /* `xorl %ecx, %ecx' */
1278 { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } },
1279 /* `xorl %edx, %edx' */
1280 { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } },
1285 /* Check whether PC points to a no-op instruction. */
1287 i386_skip_noop (CORE_ADDR pc
)
1292 if (target_read_memory (pc
, &op
, 1))
1298 /* Ignore `nop' instruction. */
1302 if (target_read_memory (pc
, &op
, 1))
1306 /* Ignore no-op instruction `mov %edi, %edi'.
1307 Microsoft system dlls often start with
1308 a `mov %edi,%edi' instruction.
1309 The 5 bytes before the function start are
1310 filled with `nop' instructions.
1311 This pattern can be used for hot-patching:
1312 The `mov %edi, %edi' instruction can be replaced by a
1313 near jump to the location of the 5 `nop' instructions
1314 which can be replaced by a 32-bit jump to anywhere
1315 in the 32-bit address space. */
1317 else if (op
== 0x8b)
1319 if (target_read_memory (pc
+ 1, &op
, 1))
1325 if (target_read_memory (pc
, &op
, 1))
1335 /* Check whether PC points at a code that sets up a new stack frame.
1336 If so, it updates CACHE and returns the address of the first
1337 instruction after the sequence that sets up the frame or LIMIT,
1338 whichever is smaller. If we don't recognize the code, return PC. */
1341 i386_analyze_frame_setup (struct gdbarch
*gdbarch
,
1342 CORE_ADDR pc
, CORE_ADDR limit
,
1343 struct i386_frame_cache
*cache
)
1345 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1346 struct i386_insn
*insn
;
1353 if (target_read_memory (pc
, &op
, 1))
1356 if (op
== 0x55) /* pushl %ebp */
1358 /* Take into account that we've executed the `pushl %ebp' that
1359 starts this instruction sequence. */
1360 cache
->saved_regs
[I386_EBP_REGNUM
] = 0;
1361 cache
->sp_offset
+= 4;
1364 /* If that's all, return now. */
1368 /* Check for some special instructions that might be migrated by
1369 GCC into the prologue and skip them. At this point in the
1370 prologue, code should only touch the scratch registers %eax,
1371 %ecx and %edx, so while the number of posibilities is sheer,
1374 Make sure we only skip these instructions if we later see the
1375 `movl %esp, %ebp' that actually sets up the frame. */
1376 while (pc
+ skip
< limit
)
1378 insn
= i386_match_insn (pc
+ skip
, i386_frame_setup_skip_insns
);
1385 /* If that's all, return now. */
1386 if (limit
<= pc
+ skip
)
1389 if (target_read_memory (pc
+ skip
, &op
, 1))
1392 /* The i386 prologue looks like
1398 and a different prologue can be generated for atom.
1402 lea -0x10(%esp),%esp
1404 We handle both of them here. */
1408 /* Check for `movl %esp, %ebp' -- can be written in two ways. */
1410 if (read_memory_unsigned_integer (pc
+ skip
+ 1, 1, byte_order
)
1416 if (read_memory_unsigned_integer (pc
+ skip
+ 1, 1, byte_order
)
1421 case 0x8d: /* Check for 'lea (%ebp), %ebp'. */
1422 if (read_memory_unsigned_integer (pc
+ skip
+ 1, 2, byte_order
)
1431 /* OK, we actually have a frame. We just don't know how large
1432 it is yet. Set its size to zero. We'll adjust it if
1433 necessary. We also now commit to skipping the special
1434 instructions mentioned before. */
1437 /* If that's all, return now. */
1441 /* Check for stack adjustment
1447 NOTE: You can't subtract a 16-bit immediate from a 32-bit
1448 reg, so we don't have to worry about a data16 prefix. */
1449 if (target_read_memory (pc
, &op
, 1))
1453 /* `subl' with 8-bit immediate. */
1454 if (read_memory_unsigned_integer (pc
+ 1, 1, byte_order
) != 0xec)
1455 /* Some instruction starting with 0x83 other than `subl'. */
1458 /* `subl' with signed 8-bit immediate (though it wouldn't
1459 make sense to be negative). */
1460 cache
->locals
= read_memory_integer (pc
+ 2, 1, byte_order
);
1463 else if (op
== 0x81)
1465 /* Maybe it is `subl' with a 32-bit immediate. */
1466 if (read_memory_unsigned_integer (pc
+ 1, 1, byte_order
) != 0xec)
1467 /* Some instruction starting with 0x81 other than `subl'. */
1470 /* It is `subl' with a 32-bit immediate. */
1471 cache
->locals
= read_memory_integer (pc
+ 2, 4, byte_order
);
1474 else if (op
== 0x8d)
1476 /* The ModR/M byte is 0x64. */
1477 if (read_memory_unsigned_integer (pc
+ 1, 1, byte_order
) != 0x64)
1479 /* 'lea' with 8-bit displacement. */
1480 cache
->locals
= -1 * read_memory_integer (pc
+ 3, 1, byte_order
);
1485 /* Some instruction other than `subl' nor 'lea'. */
1489 else if (op
== 0xc8) /* enter */
1491 cache
->locals
= read_memory_unsigned_integer (pc
+ 1, 2, byte_order
);
1498 /* Check whether PC points at code that saves registers on the stack.
1499 If so, it updates CACHE and returns the address of the first
1500 instruction after the register saves or CURRENT_PC, whichever is
1501 smaller. Otherwise, return PC. */
1504 i386_analyze_register_saves (CORE_ADDR pc
, CORE_ADDR current_pc
,
1505 struct i386_frame_cache
*cache
)
1507 CORE_ADDR offset
= 0;
1511 if (cache
->locals
> 0)
1512 offset
-= cache
->locals
;
1513 for (i
= 0; i
< 8 && pc
< current_pc
; i
++)
1515 if (target_read_memory (pc
, &op
, 1))
1517 if (op
< 0x50 || op
> 0x57)
1521 cache
->saved_regs
[op
- 0x50] = offset
;
1522 cache
->sp_offset
+= 4;
1529 /* Do a full analysis of the prologue at PC and update CACHE
1530 accordingly. Bail out early if CURRENT_PC is reached. Return the
1531 address where the analysis stopped.
1533 We handle these cases:
1535 The startup sequence can be at the start of the function, or the
1536 function can start with a branch to startup code at the end.
1538 %ebp can be set up with either the 'enter' instruction, or "pushl
1539 %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was
1540 once used in the System V compiler).
1542 Local space is allocated just below the saved %ebp by either the
1543 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a
1544 16-bit unsigned argument for space to allocate, and the 'addl'
1545 instruction could have either a signed byte, or 32-bit immediate.
1547 Next, the registers used by this function are pushed. With the
1548 System V compiler they will always be in the order: %edi, %esi,
1549 %ebx (and sometimes a harmless bug causes it to also save but not
1550 restore %eax); however, the code below is willing to see the pushes
1551 in any order, and will handle up to 8 of them.
1553 If the setup sequence is at the end of the function, then the next
1554 instruction will be a branch back to the start. */
1557 i386_analyze_prologue (struct gdbarch
*gdbarch
,
1558 CORE_ADDR pc
, CORE_ADDR current_pc
,
1559 struct i386_frame_cache
*cache
)
1561 pc
= i386_skip_noop (pc
);
1562 pc
= i386_follow_jump (gdbarch
, pc
);
1563 pc
= i386_analyze_struct_return (pc
, current_pc
, cache
);
1564 pc
= i386_skip_probe (pc
);
1565 pc
= i386_analyze_stack_align (pc
, current_pc
, cache
);
1566 pc
= i386_analyze_frame_setup (gdbarch
, pc
, current_pc
, cache
);
1567 return i386_analyze_register_saves (pc
, current_pc
, cache
);
1570 /* Return PC of first real instruction. */
1573 i386_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
1575 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1577 static gdb_byte pic_pat
[6] =
1579 0xe8, 0, 0, 0, 0, /* call 0x0 */
1580 0x5b, /* popl %ebx */
1582 struct i386_frame_cache cache
;
1586 CORE_ADDR func_addr
;
1588 if (find_pc_partial_function (start_pc
, NULL
, &func_addr
, NULL
))
1590 CORE_ADDR post_prologue_pc
1591 = skip_prologue_using_sal (gdbarch
, func_addr
);
1592 struct symtab
*s
= find_pc_symtab (func_addr
);
1594 /* Clang always emits a line note before the prologue and another
1595 one after. We trust clang to emit usable line notes. */
1596 if (post_prologue_pc
1598 && s
->producer
!= NULL
1599 && strncmp (s
->producer
, "clang ", sizeof ("clang ") - 1) == 0))
1600 return max (start_pc
, post_prologue_pc
);
1604 pc
= i386_analyze_prologue (gdbarch
, start_pc
, 0xffffffff, &cache
);
1605 if (cache
.locals
< 0)
1608 /* Found valid frame setup. */
1610 /* The native cc on SVR4 in -K PIC mode inserts the following code
1611 to get the address of the global offset table (GOT) into register
1616 movl %ebx,x(%ebp) (optional)
1619 This code is with the rest of the prologue (at the end of the
1620 function), so we have to skip it to get to the first real
1621 instruction at the start of the function. */
1623 for (i
= 0; i
< 6; i
++)
1625 if (target_read_memory (pc
+ i
, &op
, 1))
1628 if (pic_pat
[i
] != op
)
1635 if (target_read_memory (pc
+ delta
, &op
, 1))
1638 if (op
== 0x89) /* movl %ebx, x(%ebp) */
1640 op
= read_memory_unsigned_integer (pc
+ delta
+ 1, 1, byte_order
);
1642 if (op
== 0x5d) /* One byte offset from %ebp. */
1644 else if (op
== 0x9d) /* Four byte offset from %ebp. */
1646 else /* Unexpected instruction. */
1649 if (target_read_memory (pc
+ delta
, &op
, 1))
1654 if (delta
> 0 && op
== 0x81
1655 && read_memory_unsigned_integer (pc
+ delta
+ 1, 1, byte_order
)
1662 /* If the function starts with a branch (to startup code at the end)
1663 the last instruction should bring us back to the first
1664 instruction of the real code. */
1665 if (i386_follow_jump (gdbarch
, start_pc
) != start_pc
)
1666 pc
= i386_follow_jump (gdbarch
, pc
);
1671 /* Check that the code pointed to by PC corresponds to a call to
1672 __main, skip it if so. Return PC otherwise. */
1675 i386_skip_main_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1677 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1680 if (target_read_memory (pc
, &op
, 1))
1686 if (target_read_memory (pc
+ 1, buf
, sizeof buf
) == 0)
1688 /* Make sure address is computed correctly as a 32bit
1689 integer even if CORE_ADDR is 64 bit wide. */
1690 struct bound_minimal_symbol s
;
1691 CORE_ADDR call_dest
;
1693 call_dest
= pc
+ 5 + extract_signed_integer (buf
, 4, byte_order
);
1694 call_dest
= call_dest
& 0xffffffffU
;
1695 s
= lookup_minimal_symbol_by_pc (call_dest
);
1696 if (s
.minsym
!= NULL
1697 && SYMBOL_LINKAGE_NAME (s
.minsym
) != NULL
1698 && strcmp (SYMBOL_LINKAGE_NAME (s
.minsym
), "__main") == 0)
1706 /* This function is 64-bit safe. */
1709 i386_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1713 frame_unwind_register (next_frame
, gdbarch_pc_regnum (gdbarch
), buf
);
1714 return extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
1718 /* Normal frames. */
1721 i386_frame_cache_1 (struct frame_info
*this_frame
,
1722 struct i386_frame_cache
*cache
)
1724 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1725 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1729 cache
->pc
= get_frame_func (this_frame
);
1731 /* In principle, for normal frames, %ebp holds the frame pointer,
1732 which holds the base address for the current stack frame.
1733 However, for functions that don't need it, the frame pointer is
1734 optional. For these "frameless" functions the frame pointer is
1735 actually the frame pointer of the calling frame. Signal
1736 trampolines are just a special case of a "frameless" function.
1737 They (usually) share their frame pointer with the frame that was
1738 in progress when the signal occurred. */
1740 get_frame_register (this_frame
, I386_EBP_REGNUM
, buf
);
1741 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
);
1742 if (cache
->base
== 0)
1748 /* For normal frames, %eip is stored at 4(%ebp). */
1749 cache
->saved_regs
[I386_EIP_REGNUM
] = 4;
1752 i386_analyze_prologue (gdbarch
, cache
->pc
, get_frame_pc (this_frame
),
1755 if (cache
->locals
< 0)
1757 /* We didn't find a valid frame, which means that CACHE->base
1758 currently holds the frame pointer for our calling frame. If
1759 we're at the start of a function, or somewhere half-way its
1760 prologue, the function's frame probably hasn't been fully
1761 setup yet. Try to reconstruct the base address for the stack
1762 frame by looking at the stack pointer. For truly "frameless"
1763 functions this might work too. */
1765 if (cache
->saved_sp_reg
!= -1)
1767 /* Saved stack pointer has been saved. */
1768 get_frame_register (this_frame
, cache
->saved_sp_reg
, buf
);
1769 cache
->saved_sp
= extract_unsigned_integer (buf
, 4, byte_order
);
1771 /* We're halfway aligning the stack. */
1772 cache
->base
= ((cache
->saved_sp
- 4) & 0xfffffff0) - 4;
1773 cache
->saved_regs
[I386_EIP_REGNUM
] = cache
->saved_sp
- 4;
1775 /* This will be added back below. */
1776 cache
->saved_regs
[I386_EIP_REGNUM
] -= cache
->base
;
1778 else if (cache
->pc
!= 0
1779 || target_read_memory (get_frame_pc (this_frame
), buf
, 1))
1781 /* We're in a known function, but did not find a frame
1782 setup. Assume that the function does not use %ebp.
1783 Alternatively, we may have jumped to an invalid
1784 address; in that case there is definitely no new
1786 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
1787 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
)
1791 /* We're in an unknown function. We could not find the start
1792 of the function to analyze the prologue; our best option is
1793 to assume a typical frame layout with the caller's %ebp
1795 cache
->saved_regs
[I386_EBP_REGNUM
] = 0;
1798 if (cache
->saved_sp_reg
!= -1)
1800 /* Saved stack pointer has been saved (but the SAVED_SP_REG
1801 register may be unavailable). */
1802 if (cache
->saved_sp
== 0
1803 && deprecated_frame_register_read (this_frame
,
1804 cache
->saved_sp_reg
, buf
))
1805 cache
->saved_sp
= extract_unsigned_integer (buf
, 4, byte_order
);
1807 /* Now that we have the base address for the stack frame we can
1808 calculate the value of %esp in the calling frame. */
1809 else if (cache
->saved_sp
== 0)
1810 cache
->saved_sp
= cache
->base
+ 8;
1812 /* Adjust all the saved registers such that they contain addresses
1813 instead of offsets. */
1814 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
1815 if (cache
->saved_regs
[i
] != -1)
1816 cache
->saved_regs
[i
] += cache
->base
;
1821 static struct i386_frame_cache
*
1822 i386_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1824 volatile struct gdb_exception ex
;
1825 struct i386_frame_cache
*cache
;
1830 cache
= i386_alloc_frame_cache ();
1831 *this_cache
= cache
;
1833 TRY_CATCH (ex
, RETURN_MASK_ERROR
)
1835 i386_frame_cache_1 (this_frame
, cache
);
1837 if (ex
.reason
< 0 && ex
.error
!= NOT_AVAILABLE_ERROR
)
1838 throw_exception (ex
);
1844 i386_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
1845 struct frame_id
*this_id
)
1847 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1849 /* This marks the outermost frame. */
1850 if (cache
->base
== 0)
1853 /* See the end of i386_push_dummy_call. */
1854 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
1857 static enum unwind_stop_reason
1858 i386_frame_unwind_stop_reason (struct frame_info
*this_frame
,
1861 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1864 return UNWIND_UNAVAILABLE
;
1866 /* This marks the outermost frame. */
1867 if (cache
->base
== 0)
1868 return UNWIND_OUTERMOST
;
1870 return UNWIND_NO_REASON
;
1873 static struct value
*
1874 i386_frame_prev_register (struct frame_info
*this_frame
, void **this_cache
,
1877 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1879 gdb_assert (regnum
>= 0);
1881 /* The System V ABI says that:
1883 "The flags register contains the system flags, such as the
1884 direction flag and the carry flag. The direction flag must be
1885 set to the forward (that is, zero) direction before entry and
1886 upon exit from a function. Other user flags have no specified
1887 role in the standard calling sequence and are not preserved."
1889 To guarantee the "upon exit" part of that statement we fake a
1890 saved flags register that has its direction flag cleared.
1892 Note that GCC doesn't seem to rely on the fact that the direction
1893 flag is cleared after a function return; it always explicitly
1894 clears the flag before operations where it matters.
1896 FIXME: kettenis/20030316: I'm not quite sure whether this is the
1897 right thing to do. The way we fake the flags register here makes
1898 it impossible to change it. */
1900 if (regnum
== I386_EFLAGS_REGNUM
)
1904 val
= get_frame_register_unsigned (this_frame
, regnum
);
1906 return frame_unwind_got_constant (this_frame
, regnum
, val
);
1909 if (regnum
== I386_EIP_REGNUM
&& cache
->pc_in_eax
)
1910 return frame_unwind_got_register (this_frame
, regnum
, I386_EAX_REGNUM
);
1912 if (regnum
== I386_ESP_REGNUM
1913 && (cache
->saved_sp
!= 0 || cache
->saved_sp_reg
!= -1))
1915 /* If the SP has been saved, but we don't know where, then this
1916 means that SAVED_SP_REG register was found unavailable back
1917 when we built the cache. */
1918 if (cache
->saved_sp
== 0)
1919 return frame_unwind_got_register (this_frame
, regnum
,
1920 cache
->saved_sp_reg
);
1922 return frame_unwind_got_constant (this_frame
, regnum
,
1926 if (regnum
< I386_NUM_SAVED_REGS
&& cache
->saved_regs
[regnum
] != -1)
1927 return frame_unwind_got_memory (this_frame
, regnum
,
1928 cache
->saved_regs
[regnum
]);
1930 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
1933 static const struct frame_unwind i386_frame_unwind
=
1936 i386_frame_unwind_stop_reason
,
1938 i386_frame_prev_register
,
1940 default_frame_sniffer
1943 /* Normal frames, but in a function epilogue. */
1945 /* The epilogue is defined here as the 'ret' instruction, which will
1946 follow any instruction such as 'leave' or 'pop %ebp' that destroys
1947 the function's stack frame. */
1950 i386_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1953 struct symtab
*symtab
;
1955 symtab
= find_pc_symtab (pc
);
1956 if (symtab
&& symtab
->epilogue_unwind_valid
)
1959 if (target_read_memory (pc
, &insn
, 1))
1960 return 0; /* Can't read memory at pc. */
1962 if (insn
!= 0xc3) /* 'ret' instruction. */
1969 i386_epilogue_frame_sniffer (const struct frame_unwind
*self
,
1970 struct frame_info
*this_frame
,
1971 void **this_prologue_cache
)
1973 if (frame_relative_level (this_frame
) == 0)
1974 return i386_in_function_epilogue_p (get_frame_arch (this_frame
),
1975 get_frame_pc (this_frame
));
1980 static struct i386_frame_cache
*
1981 i386_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1983 volatile struct gdb_exception ex
;
1984 struct i386_frame_cache
*cache
;
1990 cache
= i386_alloc_frame_cache ();
1991 *this_cache
= cache
;
1993 TRY_CATCH (ex
, RETURN_MASK_ERROR
)
1995 cache
->pc
= get_frame_func (this_frame
);
1997 /* At this point the stack looks as if we just entered the
1998 function, with the return address at the top of the
2000 sp
= get_frame_register_unsigned (this_frame
, I386_ESP_REGNUM
);
2001 cache
->base
= sp
+ cache
->sp_offset
;
2002 cache
->saved_sp
= cache
->base
+ 8;
2003 cache
->saved_regs
[I386_EIP_REGNUM
] = cache
->base
+ 4;
2007 if (ex
.reason
< 0 && ex
.error
!= NOT_AVAILABLE_ERROR
)
2008 throw_exception (ex
);
2013 static enum unwind_stop_reason
2014 i386_epilogue_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2017 struct i386_frame_cache
*cache
=
2018 i386_epilogue_frame_cache (this_frame
, this_cache
);
2021 return UNWIND_UNAVAILABLE
;
2023 return UNWIND_NO_REASON
;
2027 i386_epilogue_frame_this_id (struct frame_info
*this_frame
,
2029 struct frame_id
*this_id
)
2031 struct i386_frame_cache
*cache
=
2032 i386_epilogue_frame_cache (this_frame
, this_cache
);
2037 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
2040 static struct value
*
2041 i386_epilogue_frame_prev_register (struct frame_info
*this_frame
,
2042 void **this_cache
, int regnum
)
2044 /* Make sure we've initialized the cache. */
2045 i386_epilogue_frame_cache (this_frame
, this_cache
);
2047 return i386_frame_prev_register (this_frame
, this_cache
, regnum
);
2050 static const struct frame_unwind i386_epilogue_frame_unwind
=
2053 i386_epilogue_frame_unwind_stop_reason
,
2054 i386_epilogue_frame_this_id
,
2055 i386_epilogue_frame_prev_register
,
2057 i386_epilogue_frame_sniffer
2061 /* Stack-based trampolines. */
2063 /* These trampolines are used on cross x86 targets, when taking the
2064 address of a nested function. When executing these trampolines,
2065 no stack frame is set up, so we are in a similar situation as in
2066 epilogues and i386_epilogue_frame_this_id can be re-used. */
2068 /* Static chain passed in register. */
2070 struct i386_insn i386_tramp_chain_in_reg_insns
[] =
2072 /* `movl imm32, %eax' and `movl imm32, %ecx' */
2073 { 5, { 0xb8 }, { 0xfe } },
2076 { 5, { 0xe9 }, { 0xff } },
2081 /* Static chain passed on stack (when regparm=3). */
2083 struct i386_insn i386_tramp_chain_on_stack_insns
[] =
2086 { 5, { 0x68 }, { 0xff } },
2089 { 5, { 0xe9 }, { 0xff } },
2094 /* Return whether PC points inside a stack trampoline. */
2097 i386_in_stack_tramp_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2102 /* A stack trampoline is detected if no name is associated
2103 to the current pc and if it points inside a trampoline
2106 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
2110 if (target_read_memory (pc
, &insn
, 1))
2113 if (!i386_match_insn_block (pc
, i386_tramp_chain_in_reg_insns
)
2114 && !i386_match_insn_block (pc
, i386_tramp_chain_on_stack_insns
))
2121 i386_stack_tramp_frame_sniffer (const struct frame_unwind
*self
,
2122 struct frame_info
*this_frame
,
2125 if (frame_relative_level (this_frame
) == 0)
2126 return i386_in_stack_tramp_p (get_frame_arch (this_frame
),
2127 get_frame_pc (this_frame
));
2132 static const struct frame_unwind i386_stack_tramp_frame_unwind
=
2135 i386_epilogue_frame_unwind_stop_reason
,
2136 i386_epilogue_frame_this_id
,
2137 i386_epilogue_frame_prev_register
,
2139 i386_stack_tramp_frame_sniffer
2142 /* Generate a bytecode expression to get the value of the saved PC. */
2145 i386_gen_return_address (struct gdbarch
*gdbarch
,
2146 struct agent_expr
*ax
, struct axs_value
*value
,
2149 /* The following sequence assumes the traditional use of the base
2151 ax_reg (ax
, I386_EBP_REGNUM
);
2153 ax_simple (ax
, aop_add
);
2154 value
->type
= register_type (gdbarch
, I386_EIP_REGNUM
);
2155 value
->kind
= axs_lvalue_memory
;
2159 /* Signal trampolines. */
2161 static struct i386_frame_cache
*
2162 i386_sigtramp_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2164 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2165 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2166 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2167 volatile struct gdb_exception ex
;
2168 struct i386_frame_cache
*cache
;
2175 cache
= i386_alloc_frame_cache ();
2177 TRY_CATCH (ex
, RETURN_MASK_ERROR
)
2179 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
2180 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
) - 4;
2182 addr
= tdep
->sigcontext_addr (this_frame
);
2183 if (tdep
->sc_reg_offset
)
2187 gdb_assert (tdep
->sc_num_regs
<= I386_NUM_SAVED_REGS
);
2189 for (i
= 0; i
< tdep
->sc_num_regs
; i
++)
2190 if (tdep
->sc_reg_offset
[i
] != -1)
2191 cache
->saved_regs
[i
] = addr
+ tdep
->sc_reg_offset
[i
];
2195 cache
->saved_regs
[I386_EIP_REGNUM
] = addr
+ tdep
->sc_pc_offset
;
2196 cache
->saved_regs
[I386_ESP_REGNUM
] = addr
+ tdep
->sc_sp_offset
;
2201 if (ex
.reason
< 0 && ex
.error
!= NOT_AVAILABLE_ERROR
)
2202 throw_exception (ex
);
2204 *this_cache
= cache
;
2208 static enum unwind_stop_reason
2209 i386_sigtramp_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2212 struct i386_frame_cache
*cache
=
2213 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2216 return UNWIND_UNAVAILABLE
;
2218 return UNWIND_NO_REASON
;
2222 i386_sigtramp_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2223 struct frame_id
*this_id
)
2225 struct i386_frame_cache
*cache
=
2226 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2231 /* See the end of i386_push_dummy_call. */
2232 (*this_id
) = frame_id_build (cache
->base
+ 8, get_frame_pc (this_frame
));
2235 static struct value
*
2236 i386_sigtramp_frame_prev_register (struct frame_info
*this_frame
,
2237 void **this_cache
, int regnum
)
2239 /* Make sure we've initialized the cache. */
2240 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2242 return i386_frame_prev_register (this_frame
, this_cache
, regnum
);
2246 i386_sigtramp_frame_sniffer (const struct frame_unwind
*self
,
2247 struct frame_info
*this_frame
,
2248 void **this_prologue_cache
)
2250 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (this_frame
));
2252 /* We shouldn't even bother if we don't have a sigcontext_addr
2254 if (tdep
->sigcontext_addr
== NULL
)
2257 if (tdep
->sigtramp_p
!= NULL
)
2259 if (tdep
->sigtramp_p (this_frame
))
2263 if (tdep
->sigtramp_start
!= 0)
2265 CORE_ADDR pc
= get_frame_pc (this_frame
);
2267 gdb_assert (tdep
->sigtramp_end
!= 0);
2268 if (pc
>= tdep
->sigtramp_start
&& pc
< tdep
->sigtramp_end
)
2275 static const struct frame_unwind i386_sigtramp_frame_unwind
=
2278 i386_sigtramp_frame_unwind_stop_reason
,
2279 i386_sigtramp_frame_this_id
,
2280 i386_sigtramp_frame_prev_register
,
2282 i386_sigtramp_frame_sniffer
2287 i386_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
2289 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
2294 static const struct frame_base i386_frame_base
=
2297 i386_frame_base_address
,
2298 i386_frame_base_address
,
2299 i386_frame_base_address
2302 static struct frame_id
2303 i386_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
2307 fp
= get_frame_register_unsigned (this_frame
, I386_EBP_REGNUM
);
2309 /* See the end of i386_push_dummy_call. */
2310 return frame_id_build (fp
+ 8, get_frame_pc (this_frame
));
2313 /* _Decimal128 function return values need 16-byte alignment on the
2317 i386_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
2319 return sp
& -(CORE_ADDR
)16;
2323 /* Figure out where the longjmp will land. Slurp the args out of the
2324 stack. We expect the first arg to be a pointer to the jmp_buf
2325 structure from which we extract the address that we will land at.
2326 This address is copied into PC. This routine returns non-zero on
2330 i386_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
2333 CORE_ADDR sp
, jb_addr
;
2334 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2335 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2336 int jb_pc_offset
= gdbarch_tdep (gdbarch
)->jb_pc_offset
;
2338 /* If JB_PC_OFFSET is -1, we have no way to find out where the
2339 longjmp will land. */
2340 if (jb_pc_offset
== -1)
2343 get_frame_register (frame
, I386_ESP_REGNUM
, buf
);
2344 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
2345 if (target_read_memory (sp
+ 4, buf
, 4))
2348 jb_addr
= extract_unsigned_integer (buf
, 4, byte_order
);
2349 if (target_read_memory (jb_addr
+ jb_pc_offset
, buf
, 4))
2352 *pc
= extract_unsigned_integer (buf
, 4, byte_order
);
2357 /* Check whether TYPE must be 16-byte-aligned when passed as a
2358 function argument. 16-byte vectors, _Decimal128 and structures or
2359 unions containing such types must be 16-byte-aligned; other
2360 arguments are 4-byte-aligned. */
2363 i386_16_byte_align_p (struct type
*type
)
2365 type
= check_typedef (type
);
2366 if ((TYPE_CODE (type
) == TYPE_CODE_DECFLOAT
2367 || (TYPE_CODE (type
) == TYPE_CODE_ARRAY
&& TYPE_VECTOR (type
)))
2368 && TYPE_LENGTH (type
) == 16)
2370 if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
2371 return i386_16_byte_align_p (TYPE_TARGET_TYPE (type
));
2372 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
2373 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
2376 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
2378 if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type
, i
)))
2385 /* Implementation for set_gdbarch_push_dummy_code. */
2388 i386_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
, CORE_ADDR funaddr
,
2389 struct value
**args
, int nargs
, struct type
*value_type
,
2390 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
,
2391 struct regcache
*regcache
)
2393 /* Use 0xcc breakpoint - 1 byte. */
2397 /* Keep the stack aligned. */
2402 i386_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2403 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
2404 struct value
**args
, CORE_ADDR sp
, int struct_return
,
2405 CORE_ADDR struct_addr
)
2407 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2413 /* Determine the total space required for arguments and struct
2414 return address in a first pass (allowing for 16-byte-aligned
2415 arguments), then push arguments in a second pass. */
2417 for (write_pass
= 0; write_pass
< 2; write_pass
++)
2419 int args_space_used
= 0;
2425 /* Push value address. */
2426 store_unsigned_integer (buf
, 4, byte_order
, struct_addr
);
2427 write_memory (sp
, buf
, 4);
2428 args_space_used
+= 4;
2434 for (i
= 0; i
< nargs
; i
++)
2436 int len
= TYPE_LENGTH (value_enclosing_type (args
[i
]));
2440 if (i386_16_byte_align_p (value_enclosing_type (args
[i
])))
2441 args_space_used
= align_up (args_space_used
, 16);
2443 write_memory (sp
+ args_space_used
,
2444 value_contents_all (args
[i
]), len
);
2445 /* The System V ABI says that:
2447 "An argument's size is increased, if necessary, to make it a
2448 multiple of [32-bit] words. This may require tail padding,
2449 depending on the size of the argument."
2451 This makes sure the stack stays word-aligned. */
2452 args_space_used
+= align_up (len
, 4);
2456 if (i386_16_byte_align_p (value_enclosing_type (args
[i
])))
2457 args_space
= align_up (args_space
, 16);
2458 args_space
+= align_up (len
, 4);
2466 /* The original System V ABI only requires word alignment,
2467 but modern incarnations need 16-byte alignment in order
2468 to support SSE. Since wasting a few bytes here isn't
2469 harmful we unconditionally enforce 16-byte alignment. */
2474 /* Store return address. */
2476 store_unsigned_integer (buf
, 4, byte_order
, bp_addr
);
2477 write_memory (sp
, buf
, 4);
2479 /* Finally, update the stack pointer... */
2480 store_unsigned_integer (buf
, 4, byte_order
, sp
);
2481 regcache_cooked_write (regcache
, I386_ESP_REGNUM
, buf
);
2483 /* ...and fake a frame pointer. */
2484 regcache_cooked_write (regcache
, I386_EBP_REGNUM
, buf
);
2486 /* MarkK wrote: This "+ 8" is all over the place:
2487 (i386_frame_this_id, i386_sigtramp_frame_this_id,
2488 i386_dummy_id). It's there, since all frame unwinders for
2489 a given target have to agree (within a certain margin) on the
2490 definition of the stack address of a frame. Otherwise frame id
2491 comparison might not work correctly. Since DWARF2/GCC uses the
2492 stack address *before* the function call as a frame's CFA. On
2493 the i386, when %ebp is used as a frame pointer, the offset
2494 between the contents %ebp and the CFA as defined by GCC. */
2498 /* These registers are used for returning integers (and on some
2499 targets also for returning `struct' and `union' values when their
2500 size and alignment match an integer type). */
2501 #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */
2502 #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */
2504 /* Read, for architecture GDBARCH, a function return value of TYPE
2505 from REGCACHE, and copy that into VALBUF. */
2508 i386_extract_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
2509 struct regcache
*regcache
, gdb_byte
*valbuf
)
2511 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2512 int len
= TYPE_LENGTH (type
);
2513 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
2515 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2517 if (tdep
->st0_regnum
< 0)
2519 warning (_("Cannot find floating-point return value."));
2520 memset (valbuf
, 0, len
);
2524 /* Floating-point return values can be found in %st(0). Convert
2525 its contents to the desired type. This is probably not
2526 exactly how it would happen on the target itself, but it is
2527 the best we can do. */
2528 regcache_raw_read (regcache
, I386_ST0_REGNUM
, buf
);
2529 convert_typed_floating (buf
, i387_ext_type (gdbarch
), valbuf
, type
);
2533 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
2534 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
2536 if (len
<= low_size
)
2538 regcache_raw_read (regcache
, LOW_RETURN_REGNUM
, buf
);
2539 memcpy (valbuf
, buf
, len
);
2541 else if (len
<= (low_size
+ high_size
))
2543 regcache_raw_read (regcache
, LOW_RETURN_REGNUM
, buf
);
2544 memcpy (valbuf
, buf
, low_size
);
2545 regcache_raw_read (regcache
, HIGH_RETURN_REGNUM
, buf
);
2546 memcpy (valbuf
+ low_size
, buf
, len
- low_size
);
2549 internal_error (__FILE__
, __LINE__
,
2550 _("Cannot extract return value of %d bytes long."),
2555 /* Write, for architecture GDBARCH, a function return value of TYPE
2556 from VALBUF into REGCACHE. */
2559 i386_store_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
2560 struct regcache
*regcache
, const gdb_byte
*valbuf
)
2562 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2563 int len
= TYPE_LENGTH (type
);
2565 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2568 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
2570 if (tdep
->st0_regnum
< 0)
2572 warning (_("Cannot set floating-point return value."));
2576 /* Returning floating-point values is a bit tricky. Apart from
2577 storing the return value in %st(0), we have to simulate the
2578 state of the FPU at function return point. */
2580 /* Convert the value found in VALBUF to the extended
2581 floating-point format used by the FPU. This is probably
2582 not exactly how it would happen on the target itself, but
2583 it is the best we can do. */
2584 convert_typed_floating (valbuf
, type
, buf
, i387_ext_type (gdbarch
));
2585 regcache_raw_write (regcache
, I386_ST0_REGNUM
, buf
);
2587 /* Set the top of the floating-point register stack to 7. The
2588 actual value doesn't really matter, but 7 is what a normal
2589 function return would end up with if the program started out
2590 with a freshly initialized FPU. */
2591 regcache_raw_read_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), &fstat
);
2593 regcache_raw_write_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), fstat
);
2595 /* Mark %st(1) through %st(7) as empty. Since we set the top of
2596 the floating-point register stack to 7, the appropriate value
2597 for the tag word is 0x3fff. */
2598 regcache_raw_write_unsigned (regcache
, I387_FTAG_REGNUM (tdep
), 0x3fff);
2602 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
2603 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
2605 if (len
<= low_size
)
2606 regcache_raw_write_part (regcache
, LOW_RETURN_REGNUM
, 0, len
, valbuf
);
2607 else if (len
<= (low_size
+ high_size
))
2609 regcache_raw_write (regcache
, LOW_RETURN_REGNUM
, valbuf
);
2610 regcache_raw_write_part (regcache
, HIGH_RETURN_REGNUM
, 0,
2611 len
- low_size
, valbuf
+ low_size
);
2614 internal_error (__FILE__
, __LINE__
,
2615 _("Cannot store return value of %d bytes long."), len
);
2620 /* This is the variable that is set with "set struct-convention", and
2621 its legitimate values. */
2622 static const char default_struct_convention
[] = "default";
2623 static const char pcc_struct_convention
[] = "pcc";
2624 static const char reg_struct_convention
[] = "reg";
2625 static const char *const valid_conventions
[] =
2627 default_struct_convention
,
2628 pcc_struct_convention
,
2629 reg_struct_convention
,
2632 static const char *struct_convention
= default_struct_convention
;
2634 /* Return non-zero if TYPE, which is assumed to be a structure,
2635 a union type, or an array type, should be returned in registers
2636 for architecture GDBARCH. */
2639 i386_reg_struct_return_p (struct gdbarch
*gdbarch
, struct type
*type
)
2641 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2642 enum type_code code
= TYPE_CODE (type
);
2643 int len
= TYPE_LENGTH (type
);
2645 gdb_assert (code
== TYPE_CODE_STRUCT
2646 || code
== TYPE_CODE_UNION
2647 || code
== TYPE_CODE_ARRAY
);
2649 if (struct_convention
== pcc_struct_convention
2650 || (struct_convention
== default_struct_convention
2651 && tdep
->struct_return
== pcc_struct_return
))
2654 /* Structures consisting of a single `float', `double' or 'long
2655 double' member are returned in %st(0). */
2656 if (code
== TYPE_CODE_STRUCT
&& TYPE_NFIELDS (type
) == 1)
2658 type
= check_typedef (TYPE_FIELD_TYPE (type
, 0));
2659 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2660 return (len
== 4 || len
== 8 || len
== 12);
2663 return (len
== 1 || len
== 2 || len
== 4 || len
== 8);
2666 /* Determine, for architecture GDBARCH, how a return value of TYPE
2667 should be returned. If it is supposed to be returned in registers,
2668 and READBUF is non-zero, read the appropriate value from REGCACHE,
2669 and copy it into READBUF. If WRITEBUF is non-zero, write the value
2670 from WRITEBUF into REGCACHE. */
2672 static enum return_value_convention
2673 i386_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
2674 struct type
*type
, struct regcache
*regcache
,
2675 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2677 enum type_code code
= TYPE_CODE (type
);
2679 if (((code
== TYPE_CODE_STRUCT
2680 || code
== TYPE_CODE_UNION
2681 || code
== TYPE_CODE_ARRAY
)
2682 && !i386_reg_struct_return_p (gdbarch
, type
))
2683 /* Complex double and long double uses the struct return covention. */
2684 || (code
== TYPE_CODE_COMPLEX
&& TYPE_LENGTH (type
) == 16)
2685 || (code
== TYPE_CODE_COMPLEX
&& TYPE_LENGTH (type
) == 24)
2686 /* 128-bit decimal float uses the struct return convention. */
2687 || (code
== TYPE_CODE_DECFLOAT
&& TYPE_LENGTH (type
) == 16))
2689 /* The System V ABI says that:
2691 "A function that returns a structure or union also sets %eax
2692 to the value of the original address of the caller's area
2693 before it returns. Thus when the caller receives control
2694 again, the address of the returned object resides in register
2695 %eax and can be used to access the object."
2697 So the ABI guarantees that we can always find the return
2698 value just after the function has returned. */
2700 /* Note that the ABI doesn't mention functions returning arrays,
2701 which is something possible in certain languages such as Ada.
2702 In this case, the value is returned as if it was wrapped in
2703 a record, so the convention applied to records also applies
2710 regcache_raw_read_unsigned (regcache
, I386_EAX_REGNUM
, &addr
);
2711 read_memory (addr
, readbuf
, TYPE_LENGTH (type
));
2714 return RETURN_VALUE_ABI_RETURNS_ADDRESS
;
2717 /* This special case is for structures consisting of a single
2718 `float', `double' or 'long double' member. These structures are
2719 returned in %st(0). For these structures, we call ourselves
2720 recursively, changing TYPE into the type of the first member of
2721 the structure. Since that should work for all structures that
2722 have only one member, we don't bother to check the member's type
2724 if (code
== TYPE_CODE_STRUCT
&& TYPE_NFIELDS (type
) == 1)
2726 type
= check_typedef (TYPE_FIELD_TYPE (type
, 0));
2727 return i386_return_value (gdbarch
, function
, type
, regcache
,
2732 i386_extract_return_value (gdbarch
, type
, regcache
, readbuf
);
2734 i386_store_return_value (gdbarch
, type
, regcache
, writebuf
);
2736 return RETURN_VALUE_REGISTER_CONVENTION
;
2741 i387_ext_type (struct gdbarch
*gdbarch
)
2743 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2745 if (!tdep
->i387_ext_type
)
2747 tdep
->i387_ext_type
= tdesc_find_type (gdbarch
, "i387_ext");
2748 gdb_assert (tdep
->i387_ext_type
!= NULL
);
2751 return tdep
->i387_ext_type
;
2754 /* Construct vector type for pseudo YMM registers. We can't use
2755 tdesc_find_type since YMM isn't described in target description. */
2757 static struct type
*
2758 i386_ymm_type (struct gdbarch
*gdbarch
)
2760 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2762 if (!tdep
->i386_ymm_type
)
2764 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2766 /* The type we're building is this: */
2768 union __gdb_builtin_type_vec256i
2770 int128_t uint128
[2];
2771 int64_t v2_int64
[4];
2772 int32_t v4_int32
[8];
2773 int16_t v8_int16
[16];
2774 int8_t v16_int8
[32];
2775 double v2_double
[4];
2782 t
= arch_composite_type (gdbarch
,
2783 "__gdb_builtin_type_vec256i", TYPE_CODE_UNION
);
2784 append_composite_type_field (t
, "v8_float",
2785 init_vector_type (bt
->builtin_float
, 8));
2786 append_composite_type_field (t
, "v4_double",
2787 init_vector_type (bt
->builtin_double
, 4));
2788 append_composite_type_field (t
, "v32_int8",
2789 init_vector_type (bt
->builtin_int8
, 32));
2790 append_composite_type_field (t
, "v16_int16",
2791 init_vector_type (bt
->builtin_int16
, 16));
2792 append_composite_type_field (t
, "v8_int32",
2793 init_vector_type (bt
->builtin_int32
, 8));
2794 append_composite_type_field (t
, "v4_int64",
2795 init_vector_type (bt
->builtin_int64
, 4));
2796 append_composite_type_field (t
, "v2_int128",
2797 init_vector_type (bt
->builtin_int128
, 2));
2799 TYPE_VECTOR (t
) = 1;
2800 TYPE_NAME (t
) = "builtin_type_vec256i";
2801 tdep
->i386_ymm_type
= t
;
2804 return tdep
->i386_ymm_type
;
2807 /* Construct vector type for MMX registers. */
2808 static struct type
*
2809 i386_mmx_type (struct gdbarch
*gdbarch
)
2811 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2813 if (!tdep
->i386_mmx_type
)
2815 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2817 /* The type we're building is this: */
2819 union __gdb_builtin_type_vec64i
2822 int32_t v2_int32
[2];
2823 int16_t v4_int16
[4];
2830 t
= arch_composite_type (gdbarch
,
2831 "__gdb_builtin_type_vec64i", TYPE_CODE_UNION
);
2833 append_composite_type_field (t
, "uint64", bt
->builtin_int64
);
2834 append_composite_type_field (t
, "v2_int32",
2835 init_vector_type (bt
->builtin_int32
, 2));
2836 append_composite_type_field (t
, "v4_int16",
2837 init_vector_type (bt
->builtin_int16
, 4));
2838 append_composite_type_field (t
, "v8_int8",
2839 init_vector_type (bt
->builtin_int8
, 8));
2841 TYPE_VECTOR (t
) = 1;
2842 TYPE_NAME (t
) = "builtin_type_vec64i";
2843 tdep
->i386_mmx_type
= t
;
2846 return tdep
->i386_mmx_type
;
2849 /* Return the GDB type object for the "standard" data type of data in
2853 i386_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
2855 if (i386_mmx_regnum_p (gdbarch
, regnum
))
2856 return i386_mmx_type (gdbarch
);
2857 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
2858 return i386_ymm_type (gdbarch
);
2861 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2862 if (i386_byte_regnum_p (gdbarch
, regnum
))
2863 return bt
->builtin_int8
;
2864 else if (i386_word_regnum_p (gdbarch
, regnum
))
2865 return bt
->builtin_int16
;
2866 else if (i386_dword_regnum_p (gdbarch
, regnum
))
2867 return bt
->builtin_int32
;
2870 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
2873 /* Map a cooked register onto a raw register or memory. For the i386,
2874 the MMX registers need to be mapped onto floating point registers. */
2877 i386_mmx_regnum_to_fp_regnum (struct regcache
*regcache
, int regnum
)
2879 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_regcache_arch (regcache
));
2884 mmxreg
= regnum
- tdep
->mm0_regnum
;
2885 regcache_raw_read_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), &fstat
);
2886 tos
= (fstat
>> 11) & 0x7;
2887 fpreg
= (mmxreg
+ tos
) % 8;
2889 return (I387_ST0_REGNUM (tdep
) + fpreg
);
2892 /* A helper function for us by i386_pseudo_register_read_value and
2893 amd64_pseudo_register_read_value. It does all the work but reads
2894 the data into an already-allocated value. */
2897 i386_pseudo_register_read_into_value (struct gdbarch
*gdbarch
,
2898 struct regcache
*regcache
,
2900 struct value
*result_value
)
2902 gdb_byte raw_buf
[MAX_REGISTER_SIZE
];
2903 enum register_status status
;
2904 gdb_byte
*buf
= value_contents_raw (result_value
);
2906 if (i386_mmx_regnum_p (gdbarch
, regnum
))
2908 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
2910 /* Extract (always little endian). */
2911 status
= regcache_raw_read (regcache
, fpnum
, raw_buf
);
2912 if (status
!= REG_VALID
)
2913 mark_value_bytes_unavailable (result_value
, 0,
2914 TYPE_LENGTH (value_type (result_value
)));
2916 memcpy (buf
, raw_buf
, register_size (gdbarch
, regnum
));
2920 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2922 if (i386_ymm_regnum_p (gdbarch
, regnum
))
2924 regnum
-= tdep
->ymm0_regnum
;
2926 /* Extract (always little endian). Read lower 128bits. */
2927 status
= regcache_raw_read (regcache
,
2928 I387_XMM0_REGNUM (tdep
) + regnum
,
2930 if (status
!= REG_VALID
)
2931 mark_value_bytes_unavailable (result_value
, 0, 16);
2933 memcpy (buf
, raw_buf
, 16);
2934 /* Read upper 128bits. */
2935 status
= regcache_raw_read (regcache
,
2936 tdep
->ymm0h_regnum
+ regnum
,
2938 if (status
!= REG_VALID
)
2939 mark_value_bytes_unavailable (result_value
, 16, 32);
2941 memcpy (buf
+ 16, raw_buf
, 16);
2943 else if (i386_word_regnum_p (gdbarch
, regnum
))
2945 int gpnum
= regnum
- tdep
->ax_regnum
;
2947 /* Extract (always little endian). */
2948 status
= regcache_raw_read (regcache
, gpnum
, raw_buf
);
2949 if (status
!= REG_VALID
)
2950 mark_value_bytes_unavailable (result_value
, 0,
2951 TYPE_LENGTH (value_type (result_value
)));
2953 memcpy (buf
, raw_buf
, 2);
2955 else if (i386_byte_regnum_p (gdbarch
, regnum
))
2957 /* Check byte pseudo registers last since this function will
2958 be called from amd64_pseudo_register_read, which handles
2959 byte pseudo registers differently. */
2960 int gpnum
= regnum
- tdep
->al_regnum
;
2962 /* Extract (always little endian). We read both lower and
2964 status
= regcache_raw_read (regcache
, gpnum
% 4, raw_buf
);
2965 if (status
!= REG_VALID
)
2966 mark_value_bytes_unavailable (result_value
, 0,
2967 TYPE_LENGTH (value_type (result_value
)));
2968 else if (gpnum
>= 4)
2969 memcpy (buf
, raw_buf
+ 1, 1);
2971 memcpy (buf
, raw_buf
, 1);
2974 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
2978 static struct value
*
2979 i386_pseudo_register_read_value (struct gdbarch
*gdbarch
,
2980 struct regcache
*regcache
,
2983 struct value
*result
;
2985 result
= allocate_value (register_type (gdbarch
, regnum
));
2986 VALUE_LVAL (result
) = lval_register
;
2987 VALUE_REGNUM (result
) = regnum
;
2989 i386_pseudo_register_read_into_value (gdbarch
, regcache
, regnum
, result
);
2995 i386_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2996 int regnum
, const gdb_byte
*buf
)
2998 gdb_byte raw_buf
[MAX_REGISTER_SIZE
];
3000 if (i386_mmx_regnum_p (gdbarch
, regnum
))
3002 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
3005 regcache_raw_read (regcache
, fpnum
, raw_buf
);
3006 /* ... Modify ... (always little endian). */
3007 memcpy (raw_buf
, buf
, register_size (gdbarch
, regnum
));
3009 regcache_raw_write (regcache
, fpnum
, raw_buf
);
3013 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3015 if (i386_ymm_regnum_p (gdbarch
, regnum
))
3017 regnum
-= tdep
->ymm0_regnum
;
3019 /* ... Write lower 128bits. */
3020 regcache_raw_write (regcache
,
3021 I387_XMM0_REGNUM (tdep
) + regnum
,
3023 /* ... Write upper 128bits. */
3024 regcache_raw_write (regcache
,
3025 tdep
->ymm0h_regnum
+ regnum
,
3028 else if (i386_word_regnum_p (gdbarch
, regnum
))
3030 int gpnum
= regnum
- tdep
->ax_regnum
;
3033 regcache_raw_read (regcache
, gpnum
, raw_buf
);
3034 /* ... Modify ... (always little endian). */
3035 memcpy (raw_buf
, buf
, 2);
3037 regcache_raw_write (regcache
, gpnum
, raw_buf
);
3039 else if (i386_byte_regnum_p (gdbarch
, regnum
))
3041 /* Check byte pseudo registers last since this function will
3042 be called from amd64_pseudo_register_read, which handles
3043 byte pseudo registers differently. */
3044 int gpnum
= regnum
- tdep
->al_regnum
;
3046 /* Read ... We read both lower and upper registers. */
3047 regcache_raw_read (regcache
, gpnum
% 4, raw_buf
);
3048 /* ... Modify ... (always little endian). */
3050 memcpy (raw_buf
+ 1, buf
, 1);
3052 memcpy (raw_buf
, buf
, 1);
3054 regcache_raw_write (regcache
, gpnum
% 4, raw_buf
);
3057 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
3062 /* Return the register number of the register allocated by GCC after
3063 REGNUM, or -1 if there is no such register. */
3066 i386_next_regnum (int regnum
)
3068 /* GCC allocates the registers in the order:
3070 %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ...
3072 Since storing a variable in %esp doesn't make any sense we return
3073 -1 for %ebp and for %esp itself. */
3074 static int next_regnum
[] =
3076 I386_EDX_REGNUM
, /* Slot for %eax. */
3077 I386_EBX_REGNUM
, /* Slot for %ecx. */
3078 I386_ECX_REGNUM
, /* Slot for %edx. */
3079 I386_ESI_REGNUM
, /* Slot for %ebx. */
3080 -1, -1, /* Slots for %esp and %ebp. */
3081 I386_EDI_REGNUM
, /* Slot for %esi. */
3082 I386_EBP_REGNUM
/* Slot for %edi. */
3085 if (regnum
>= 0 && regnum
< sizeof (next_regnum
) / sizeof (next_regnum
[0]))
3086 return next_regnum
[regnum
];
3091 /* Return nonzero if a value of type TYPE stored in register REGNUM
3092 needs any special handling. */
3095 i386_convert_register_p (struct gdbarch
*gdbarch
,
3096 int regnum
, struct type
*type
)
3098 int len
= TYPE_LENGTH (type
);
3100 /* Values may be spread across multiple registers. Most debugging
3101 formats aren't expressive enough to specify the locations, so
3102 some heuristics is involved. Right now we only handle types that
3103 have a length that is a multiple of the word size, since GCC
3104 doesn't seem to put any other types into registers. */
3105 if (len
> 4 && len
% 4 == 0)
3107 int last_regnum
= regnum
;
3111 last_regnum
= i386_next_regnum (last_regnum
);
3115 if (last_regnum
!= -1)
3119 return i387_convert_register_p (gdbarch
, regnum
, type
);
3122 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
3123 return its contents in TO. */
3126 i386_register_to_value (struct frame_info
*frame
, int regnum
,
3127 struct type
*type
, gdb_byte
*to
,
3128 int *optimizedp
, int *unavailablep
)
3130 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3131 int len
= TYPE_LENGTH (type
);
3133 if (i386_fp_regnum_p (gdbarch
, regnum
))
3134 return i387_register_to_value (frame
, regnum
, type
, to
,
3135 optimizedp
, unavailablep
);
3137 /* Read a value spread across multiple registers. */
3139 gdb_assert (len
> 4 && len
% 4 == 0);
3143 gdb_assert (regnum
!= -1);
3144 gdb_assert (register_size (gdbarch
, regnum
) == 4);
3146 if (!get_frame_register_bytes (frame
, regnum
, 0,
3147 register_size (gdbarch
, regnum
),
3148 to
, optimizedp
, unavailablep
))
3151 regnum
= i386_next_regnum (regnum
);
3156 *optimizedp
= *unavailablep
= 0;
3160 /* Write the contents FROM of a value of type TYPE into register
3161 REGNUM in frame FRAME. */
3164 i386_value_to_register (struct frame_info
*frame
, int regnum
,
3165 struct type
*type
, const gdb_byte
*from
)
3167 int len
= TYPE_LENGTH (type
);
3169 if (i386_fp_regnum_p (get_frame_arch (frame
), regnum
))
3171 i387_value_to_register (frame
, regnum
, type
, from
);
3175 /* Write a value spread across multiple registers. */
3177 gdb_assert (len
> 4 && len
% 4 == 0);
3181 gdb_assert (regnum
!= -1);
3182 gdb_assert (register_size (get_frame_arch (frame
), regnum
) == 4);
3184 put_frame_register (frame
, regnum
, from
);
3185 regnum
= i386_next_regnum (regnum
);
3191 /* Supply register REGNUM from the buffer specified by GREGS and LEN
3192 in the general-purpose register set REGSET to register cache
3193 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3196 i386_supply_gregset (const struct regset
*regset
, struct regcache
*regcache
,
3197 int regnum
, const void *gregs
, size_t len
)
3199 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
3200 const gdb_byte
*regs
= gregs
;
3203 gdb_assert (len
== tdep
->sizeof_gregset
);
3205 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
3207 if ((regnum
== i
|| regnum
== -1)
3208 && tdep
->gregset_reg_offset
[i
] != -1)
3209 regcache_raw_supply (regcache
, i
, regs
+ tdep
->gregset_reg_offset
[i
]);
3213 /* Collect register REGNUM from the register cache REGCACHE and store
3214 it in the buffer specified by GREGS and LEN as described by the
3215 general-purpose register set REGSET. If REGNUM is -1, do this for
3216 all registers in REGSET. */
3219 i386_collect_gregset (const struct regset
*regset
,
3220 const struct regcache
*regcache
,
3221 int regnum
, void *gregs
, size_t len
)
3223 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
3224 gdb_byte
*regs
= gregs
;
3227 gdb_assert (len
== tdep
->sizeof_gregset
);
3229 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
3231 if ((regnum
== i
|| regnum
== -1)
3232 && tdep
->gregset_reg_offset
[i
] != -1)
3233 regcache_raw_collect (regcache
, i
, regs
+ tdep
->gregset_reg_offset
[i
]);
3237 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
3238 in the floating-point register set REGSET to register cache
3239 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3242 i386_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
3243 int regnum
, const void *fpregs
, size_t len
)
3245 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
3247 if (len
== I387_SIZEOF_FXSAVE
)
3249 i387_supply_fxsave (regcache
, regnum
, fpregs
);
3253 gdb_assert (len
== tdep
->sizeof_fpregset
);
3254 i387_supply_fsave (regcache
, regnum
, fpregs
);
3257 /* Collect register REGNUM from the register cache REGCACHE and store
3258 it in the buffer specified by FPREGS and LEN as described by the
3259 floating-point register set REGSET. If REGNUM is -1, do this for
3260 all registers in REGSET. */
3263 i386_collect_fpregset (const struct regset
*regset
,
3264 const struct regcache
*regcache
,
3265 int regnum
, void *fpregs
, size_t len
)
3267 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
3269 if (len
== I387_SIZEOF_FXSAVE
)
3271 i387_collect_fxsave (regcache
, regnum
, fpregs
);
3275 gdb_assert (len
== tdep
->sizeof_fpregset
);
3276 i387_collect_fsave (regcache
, regnum
, fpregs
);
3279 /* Similar to i386_supply_fpregset, but use XSAVE extended state. */
3282 i386_supply_xstateregset (const struct regset
*regset
,
3283 struct regcache
*regcache
, int regnum
,
3284 const void *xstateregs
, size_t len
)
3286 i387_supply_xsave (regcache
, regnum
, xstateregs
);
3289 /* Similar to i386_collect_fpregset , but use XSAVE extended state. */
3292 i386_collect_xstateregset (const struct regset
*regset
,
3293 const struct regcache
*regcache
,
3294 int regnum
, void *xstateregs
, size_t len
)
3296 i387_collect_xsave (regcache
, regnum
, xstateregs
, 1);
3299 /* Return the appropriate register set for the core section identified
3300 by SECT_NAME and SECT_SIZE. */
3302 const struct regset
*
3303 i386_regset_from_core_section (struct gdbarch
*gdbarch
,
3304 const char *sect_name
, size_t sect_size
)
3306 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3308 if (strcmp (sect_name
, ".reg") == 0 && sect_size
== tdep
->sizeof_gregset
)
3310 if (tdep
->gregset
== NULL
)
3311 tdep
->gregset
= regset_alloc (gdbarch
, i386_supply_gregset
,
3312 i386_collect_gregset
);
3313 return tdep
->gregset
;
3316 if ((strcmp (sect_name
, ".reg2") == 0 && sect_size
== tdep
->sizeof_fpregset
)
3317 || (strcmp (sect_name
, ".reg-xfp") == 0
3318 && sect_size
== I387_SIZEOF_FXSAVE
))
3320 if (tdep
->fpregset
== NULL
)
3321 tdep
->fpregset
= regset_alloc (gdbarch
, i386_supply_fpregset
,
3322 i386_collect_fpregset
);
3323 return tdep
->fpregset
;
3326 if (strcmp (sect_name
, ".reg-xstate") == 0)
3328 if (tdep
->xstateregset
== NULL
)
3329 tdep
->xstateregset
= regset_alloc (gdbarch
,
3330 i386_supply_xstateregset
,
3331 i386_collect_xstateregset
);
3333 return tdep
->xstateregset
;
3340 /* Stuff for WIN32 PE style DLL's but is pretty generic really. */
3343 i386_pe_skip_trampoline_code (struct frame_info
*frame
,
3344 CORE_ADDR pc
, char *name
)
3346 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3347 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3350 if (pc
&& read_memory_unsigned_integer (pc
, 2, byte_order
) == 0x25ff)
3352 unsigned long indirect
=
3353 read_memory_unsigned_integer (pc
+ 2, 4, byte_order
);
3354 struct minimal_symbol
*indsym
=
3355 indirect
? lookup_minimal_symbol_by_pc (indirect
).minsym
: 0;
3356 const char *symname
= indsym
? SYMBOL_LINKAGE_NAME (indsym
) : 0;
3360 if (strncmp (symname
, "__imp_", 6) == 0
3361 || strncmp (symname
, "_imp_", 5) == 0)
3363 read_memory_unsigned_integer (indirect
, 4, byte_order
);
3366 return 0; /* Not a trampoline. */
3370 /* Return whether the THIS_FRAME corresponds to a sigtramp
3374 i386_sigtramp_p (struct frame_info
*this_frame
)
3376 CORE_ADDR pc
= get_frame_pc (this_frame
);
3379 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
3380 return (name
&& strcmp ("_sigtramp", name
) == 0);
3384 /* We have two flavours of disassembly. The machinery on this page
3385 deals with switching between those. */
3388 i386_print_insn (bfd_vma pc
, struct disassemble_info
*info
)
3390 gdb_assert (disassembly_flavor
== att_flavor
3391 || disassembly_flavor
== intel_flavor
);
3393 /* FIXME: kettenis/20020915: Until disassembler_options is properly
3394 constified, cast to prevent a compiler warning. */
3395 info
->disassembler_options
= (char *) disassembly_flavor
;
3397 return print_insn_i386 (pc
, info
);
3401 /* There are a few i386 architecture variants that differ only
3402 slightly from the generic i386 target. For now, we don't give them
3403 their own source file, but include them here. As a consequence,
3404 they'll always be included. */
3406 /* System V Release 4 (SVR4). */
3408 /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp
3412 i386_svr4_sigtramp_p (struct frame_info
*this_frame
)
3414 CORE_ADDR pc
= get_frame_pc (this_frame
);
3417 /* The origin of these symbols is currently unknown. */
3418 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
3419 return (name
&& (strcmp ("_sigreturn", name
) == 0
3420 || strcmp ("sigvechandler", name
) == 0));
3423 /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the
3424 address of the associated sigcontext (ucontext) structure. */
3427 i386_svr4_sigcontext_addr (struct frame_info
*this_frame
)
3429 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3430 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3434 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
3435 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
3437 return read_memory_unsigned_integer (sp
+ 8, 4, byte_order
);
3442 /* Implementation of `gdbarch_stap_is_single_operand', as defined in
3446 i386_stap_is_single_operand (struct gdbarch
*gdbarch
, const char *s
)
3448 return (*s
== '$' /* Literal number. */
3449 || (isdigit (*s
) && s
[1] == '(' && s
[2] == '%') /* Displacement. */
3450 || (*s
== '(' && s
[1] == '%') /* Register indirection. */
3451 || (*s
== '%' && isalpha (s
[1]))); /* Register access. */
3454 /* Implementation of `gdbarch_stap_parse_special_token', as defined in
3458 i386_stap_parse_special_token (struct gdbarch
*gdbarch
,
3459 struct stap_parse_info
*p
)
3461 /* In order to parse special tokens, we use a state-machine that go
3462 through every known token and try to get a match. */
3466 THREE_ARG_DISPLACEMENT
,
3470 current_state
= TRIPLET
;
3472 /* The special tokens to be parsed here are:
3474 - `register base + (register index * size) + offset', as represented
3475 in `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'.
3477 - Operands of the form `-8+3+1(%rbp)', which must be interpreted as
3478 `*(-8 + 3 - 1 + (void *) $eax)'. */
3480 while (current_state
!= DONE
)
3482 const char *s
= p
->arg
;
3484 switch (current_state
)
3488 if (isdigit (*s
) || *s
== '-' || *s
== '+')
3492 long displacements
[3];
3508 displacements
[0] = strtol (s
, &endp
, 10);
3511 if (*s
!= '+' && *s
!= '-')
3513 /* We are not dealing with a triplet. */
3526 displacements
[1] = strtol (s
, &endp
, 10);
3529 if (*s
!= '+' && *s
!= '-')
3531 /* We are not dealing with a triplet. */
3544 displacements
[2] = strtol (s
, &endp
, 10);
3547 if (*s
!= '(' || s
[1] != '%')
3553 while (isalnum (*s
))
3560 regname
= alloca (len
+ 1);
3562 strncpy (regname
, start
, len
);
3563 regname
[len
] = '\0';
3565 if (user_reg_map_name_to_regnum (gdbarch
,
3566 regname
, len
) == -1)
3567 error (_("Invalid register name `%s' "
3568 "on expression `%s'."),
3569 regname
, p
->saved_arg
);
3571 for (i
= 0; i
< 3; i
++)
3573 write_exp_elt_opcode (OP_LONG
);
3575 (builtin_type (gdbarch
)->builtin_long
);
3576 write_exp_elt_longcst (displacements
[i
]);
3577 write_exp_elt_opcode (OP_LONG
);
3579 write_exp_elt_opcode (UNOP_NEG
);
3582 write_exp_elt_opcode (OP_REGISTER
);
3585 write_exp_string (str
);
3586 write_exp_elt_opcode (OP_REGISTER
);
3588 write_exp_elt_opcode (UNOP_CAST
);
3589 write_exp_elt_type (builtin_type (gdbarch
)->builtin_data_ptr
);
3590 write_exp_elt_opcode (UNOP_CAST
);
3592 write_exp_elt_opcode (BINOP_ADD
);
3593 write_exp_elt_opcode (BINOP_ADD
);
3594 write_exp_elt_opcode (BINOP_ADD
);
3596 write_exp_elt_opcode (UNOP_CAST
);
3597 write_exp_elt_type (lookup_pointer_type (p
->arg_type
));
3598 write_exp_elt_opcode (UNOP_CAST
);
3600 write_exp_elt_opcode (UNOP_IND
);
3608 case THREE_ARG_DISPLACEMENT
:
3610 if (isdigit (*s
) || *s
== '(' || *s
== '-' || *s
== '+')
3612 int offset_minus
= 0;
3621 struct stoken base_token
, index_token
;
3631 if (offset_minus
&& !isdigit (*s
))
3638 offset
= strtol (s
, &endp
, 10);
3642 if (*s
!= '(' || s
[1] != '%')
3648 while (isalnum (*s
))
3651 if (*s
!= ',' || s
[1] != '%')
3654 len_base
= s
- start
;
3655 base
= alloca (len_base
+ 1);
3656 strncpy (base
, start
, len_base
);
3657 base
[len_base
] = '\0';
3659 if (user_reg_map_name_to_regnum (gdbarch
,
3660 base
, len_base
) == -1)
3661 error (_("Invalid register name `%s' "
3662 "on expression `%s'."),
3663 base
, p
->saved_arg
);
3668 while (isalnum (*s
))
3671 len_index
= s
- start
;
3672 index
= alloca (len_index
+ 1);
3673 strncpy (index
, start
, len_index
);
3674 index
[len_index
] = '\0';
3676 if (user_reg_map_name_to_regnum (gdbarch
,
3677 index
, len_index
) == -1)
3678 error (_("Invalid register name `%s' "
3679 "on expression `%s'."),
3680 index
, p
->saved_arg
);
3682 if (*s
!= ',' && *s
!= ')')
3698 size
= strtol (s
, &endp
, 10);
3709 write_exp_elt_opcode (OP_LONG
);
3711 (builtin_type (gdbarch
)->builtin_long
);
3712 write_exp_elt_longcst (offset
);
3713 write_exp_elt_opcode (OP_LONG
);
3715 write_exp_elt_opcode (UNOP_NEG
);
3718 write_exp_elt_opcode (OP_REGISTER
);
3719 base_token
.ptr
= base
;
3720 base_token
.length
= len_base
;
3721 write_exp_string (base_token
);
3722 write_exp_elt_opcode (OP_REGISTER
);
3725 write_exp_elt_opcode (BINOP_ADD
);
3727 write_exp_elt_opcode (OP_REGISTER
);
3728 index_token
.ptr
= index
;
3729 index_token
.length
= len_index
;
3730 write_exp_string (index_token
);
3731 write_exp_elt_opcode (OP_REGISTER
);
3735 write_exp_elt_opcode (OP_LONG
);
3737 (builtin_type (gdbarch
)->builtin_long
);
3738 write_exp_elt_longcst (size
);
3739 write_exp_elt_opcode (OP_LONG
);
3741 write_exp_elt_opcode (UNOP_NEG
);
3742 write_exp_elt_opcode (BINOP_MUL
);
3745 write_exp_elt_opcode (BINOP_ADD
);
3747 write_exp_elt_opcode (UNOP_CAST
);
3748 write_exp_elt_type (lookup_pointer_type (p
->arg_type
));
3749 write_exp_elt_opcode (UNOP_CAST
);
3751 write_exp_elt_opcode (UNOP_IND
);
3761 /* Advancing to the next state. */
3773 i386_elf_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
3775 /* We typically use stabs-in-ELF with the SVR4 register numbering. */
3776 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
3778 /* Registering SystemTap handlers. */
3779 set_gdbarch_stap_integer_prefix (gdbarch
, "$");
3780 set_gdbarch_stap_register_prefix (gdbarch
, "%");
3781 set_gdbarch_stap_register_indirection_prefix (gdbarch
, "(");
3782 set_gdbarch_stap_register_indirection_suffix (gdbarch
, ")");
3783 set_gdbarch_stap_is_single_operand (gdbarch
,
3784 i386_stap_is_single_operand
);
3785 set_gdbarch_stap_parse_special_token (gdbarch
,
3786 i386_stap_parse_special_token
);
3789 /* System V Release 4 (SVR4). */
3792 i386_svr4_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
3794 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3796 /* System V Release 4 uses ELF. */
3797 i386_elf_init_abi (info
, gdbarch
);
3799 /* System V Release 4 has shared libraries. */
3800 set_gdbarch_skip_trampoline_code (gdbarch
, find_solib_trampoline_target
);
3802 tdep
->sigtramp_p
= i386_svr4_sigtramp_p
;
3803 tdep
->sigcontext_addr
= i386_svr4_sigcontext_addr
;
3804 tdep
->sc_pc_offset
= 36 + 14 * 4;
3805 tdep
->sc_sp_offset
= 36 + 17 * 4;
3807 tdep
->jb_pc_offset
= 20;
3813 i386_go32_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
3815 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3817 /* DJGPP doesn't have any special frames for signal handlers. */
3818 tdep
->sigtramp_p
= NULL
;
3820 tdep
->jb_pc_offset
= 36;
3822 /* DJGPP does not support the SSE registers. */
3823 if (! tdesc_has_registers (info
.target_desc
))
3824 tdep
->tdesc
= tdesc_i386_mmx
;
3826 /* Native compiler is GCC, which uses the SVR4 register numbering
3827 even in COFF and STABS. See the comment in i386_gdbarch_init,
3828 before the calls to set_gdbarch_stab_reg_to_regnum and
3829 set_gdbarch_sdb_reg_to_regnum. */
3830 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
3831 set_gdbarch_sdb_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
3833 set_gdbarch_has_dos_based_file_system (gdbarch
, 1);
3837 /* i386 register groups. In addition to the normal groups, add "mmx"
3840 static struct reggroup
*i386_sse_reggroup
;
3841 static struct reggroup
*i386_mmx_reggroup
;
3844 i386_init_reggroups (void)
3846 i386_sse_reggroup
= reggroup_new ("sse", USER_REGGROUP
);
3847 i386_mmx_reggroup
= reggroup_new ("mmx", USER_REGGROUP
);
3851 i386_add_reggroups (struct gdbarch
*gdbarch
)
3853 reggroup_add (gdbarch
, i386_sse_reggroup
);
3854 reggroup_add (gdbarch
, i386_mmx_reggroup
);
3855 reggroup_add (gdbarch
, general_reggroup
);
3856 reggroup_add (gdbarch
, float_reggroup
);
3857 reggroup_add (gdbarch
, all_reggroup
);
3858 reggroup_add (gdbarch
, save_reggroup
);
3859 reggroup_add (gdbarch
, restore_reggroup
);
3860 reggroup_add (gdbarch
, vector_reggroup
);
3861 reggroup_add (gdbarch
, system_reggroup
);
3865 i386_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
3866 struct reggroup
*group
)
3868 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3869 int fp_regnum_p
, mmx_regnum_p
, xmm_regnum_p
, mxcsr_regnum_p
,
3870 ymm_regnum_p
, ymmh_regnum_p
;
3872 /* Don't include pseudo registers, except for MMX, in any register
3874 if (i386_byte_regnum_p (gdbarch
, regnum
))
3877 if (i386_word_regnum_p (gdbarch
, regnum
))
3880 if (i386_dword_regnum_p (gdbarch
, regnum
))
3883 mmx_regnum_p
= i386_mmx_regnum_p (gdbarch
, regnum
);
3884 if (group
== i386_mmx_reggroup
)
3885 return mmx_regnum_p
;
3887 xmm_regnum_p
= i386_xmm_regnum_p (gdbarch
, regnum
);
3888 mxcsr_regnum_p
= i386_mxcsr_regnum_p (gdbarch
, regnum
);
3889 if (group
== i386_sse_reggroup
)
3890 return xmm_regnum_p
|| mxcsr_regnum_p
;
3892 ymm_regnum_p
= i386_ymm_regnum_p (gdbarch
, regnum
);
3893 if (group
== vector_reggroup
)
3894 return (mmx_regnum_p
3898 && ((tdep
->xcr0
& I386_XSTATE_AVX_MASK
)
3899 == I386_XSTATE_SSE_MASK
)));
3901 fp_regnum_p
= (i386_fp_regnum_p (gdbarch
, regnum
)
3902 || i386_fpc_regnum_p (gdbarch
, regnum
));
3903 if (group
== float_reggroup
)
3906 /* For "info reg all", don't include upper YMM registers nor XMM
3907 registers when AVX is supported. */
3908 ymmh_regnum_p
= i386_ymmh_regnum_p (gdbarch
, regnum
);
3909 if (group
== all_reggroup
3911 && (tdep
->xcr0
& I386_XSTATE_AVX
))
3915 if (group
== general_reggroup
)
3916 return (!fp_regnum_p
3923 return default_register_reggroup_p (gdbarch
, regnum
, group
);
3927 /* Get the ARGIth function argument for the current function. */
3930 i386_fetch_pointer_argument (struct frame_info
*frame
, int argi
,
3933 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3934 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3935 CORE_ADDR sp
= get_frame_register_unsigned (frame
, I386_ESP_REGNUM
);
3936 return read_memory_unsigned_integer (sp
+ (4 * (argi
+ 1)), 4, byte_order
);
3940 i386_skip_permanent_breakpoint (struct regcache
*regcache
)
3942 CORE_ADDR current_pc
= regcache_read_pc (regcache
);
3944 /* On i386, breakpoint is exactly 1 byte long, so we just
3945 adjust the PC in the regcache. */
3947 regcache_write_pc (regcache
, current_pc
);
3951 #define PREFIX_REPZ 0x01
3952 #define PREFIX_REPNZ 0x02
3953 #define PREFIX_LOCK 0x04
3954 #define PREFIX_DATA 0x08
3955 #define PREFIX_ADDR 0x10
3967 /* i386 arith/logic operations */
3980 struct i386_record_s
3982 struct gdbarch
*gdbarch
;
3983 struct regcache
*regcache
;
3984 CORE_ADDR orig_addr
;
3990 uint8_t mod
, reg
, rm
;
3999 /* Parse the "modrm" part of the memory address irp->addr points at.
4000 Returns -1 if something goes wrong, 0 otherwise. */
4003 i386_record_modrm (struct i386_record_s
*irp
)
4005 struct gdbarch
*gdbarch
= irp
->gdbarch
;
4007 if (record_read_memory (gdbarch
, irp
->addr
, &irp
->modrm
, 1))
4011 irp
->mod
= (irp
->modrm
>> 6) & 3;
4012 irp
->reg
= (irp
->modrm
>> 3) & 7;
4013 irp
->rm
= irp
->modrm
& 7;
4018 /* Extract the memory address that the current instruction writes to,
4019 and return it in *ADDR. Return -1 if something goes wrong. */
4022 i386_record_lea_modrm_addr (struct i386_record_s
*irp
, uint64_t *addr
)
4024 struct gdbarch
*gdbarch
= irp
->gdbarch
;
4025 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4037 uint8_t base
= irp
->rm
;
4042 if (record_read_memory (gdbarch
, irp
->addr
, &byte
, 1))
4045 scale
= (byte
>> 6) & 3;
4046 index
= ((byte
>> 3) & 7) | irp
->rex_x
;
4054 if ((base
& 7) == 5)
4057 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 4))
4060 *addr
= extract_signed_integer (buf
, 4, byte_order
);
4061 if (irp
->regmap
[X86_RECORD_R8_REGNUM
] && !havesib
)
4062 *addr
+= irp
->addr
+ irp
->rip_offset
;
4066 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 1))
4069 *addr
= (int8_t) buf
[0];
4072 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 4))
4074 *addr
= extract_signed_integer (buf
, 4, byte_order
);
4082 if (base
== 4 && irp
->popl_esp_hack
)
4083 *addr
+= irp
->popl_esp_hack
;
4084 regcache_raw_read_unsigned (irp
->regcache
, irp
->regmap
[base
],
4087 if (irp
->aflag
== 2)
4092 *addr
= (uint32_t) (offset64
+ *addr
);
4094 if (havesib
&& (index
!= 4 || scale
!= 0))
4096 regcache_raw_read_unsigned (irp
->regcache
, irp
->regmap
[index
],
4098 if (irp
->aflag
== 2)
4099 *addr
+= offset64
<< scale
;
4101 *addr
= (uint32_t) (*addr
+ (offset64
<< scale
));
4112 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 2))
4115 *addr
= extract_signed_integer (buf
, 2, byte_order
);
4121 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 1))
4124 *addr
= (int8_t) buf
[0];
4127 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 2))
4130 *addr
= extract_signed_integer (buf
, 2, byte_order
);
4137 regcache_raw_read_unsigned (irp
->regcache
,
4138 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
4140 *addr
= (uint32_t) (*addr
+ offset64
);
4141 regcache_raw_read_unsigned (irp
->regcache
,
4142 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
4144 *addr
= (uint32_t) (*addr
+ offset64
);
4147 regcache_raw_read_unsigned (irp
->regcache
,
4148 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
4150 *addr
= (uint32_t) (*addr
+ offset64
);
4151 regcache_raw_read_unsigned (irp
->regcache
,
4152 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
4154 *addr
= (uint32_t) (*addr
+ offset64
);
4157 regcache_raw_read_unsigned (irp
->regcache
,
4158 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
4160 *addr
= (uint32_t) (*addr
+ offset64
);
4161 regcache_raw_read_unsigned (irp
->regcache
,
4162 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
4164 *addr
= (uint32_t) (*addr
+ offset64
);
4167 regcache_raw_read_unsigned (irp
->regcache
,
4168 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
4170 *addr
= (uint32_t) (*addr
+ offset64
);
4171 regcache_raw_read_unsigned (irp
->regcache
,
4172 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
4174 *addr
= (uint32_t) (*addr
+ offset64
);
4177 regcache_raw_read_unsigned (irp
->regcache
,
4178 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
4180 *addr
= (uint32_t) (*addr
+ offset64
);
4183 regcache_raw_read_unsigned (irp
->regcache
,
4184 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
4186 *addr
= (uint32_t) (*addr
+ offset64
);
4189 regcache_raw_read_unsigned (irp
->regcache
,
4190 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
4192 *addr
= (uint32_t) (*addr
+ offset64
);
4195 regcache_raw_read_unsigned (irp
->regcache
,
4196 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
4198 *addr
= (uint32_t) (*addr
+ offset64
);
4208 /* Record the address and contents of the memory that will be changed
4209 by the current instruction. Return -1 if something goes wrong, 0
4213 i386_record_lea_modrm (struct i386_record_s
*irp
)
4215 struct gdbarch
*gdbarch
= irp
->gdbarch
;
4218 if (irp
->override
>= 0)
4220 if (record_full_memory_query
)
4224 target_terminal_ours ();
4226 Process record ignores the memory change of instruction at address %s\n\
4227 because it can't get the value of the segment register.\n\
4228 Do you want to stop the program?"),
4229 paddress (gdbarch
, irp
->orig_addr
));
4230 target_terminal_inferior ();
4238 if (i386_record_lea_modrm_addr (irp
, &addr
))
4241 if (record_full_arch_list_add_mem (addr
, 1 << irp
->ot
))
4247 /* Record the effects of a push operation. Return -1 if something
4248 goes wrong, 0 otherwise. */
4251 i386_record_push (struct i386_record_s
*irp
, int size
)
4255 if (record_full_arch_list_add_reg (irp
->regcache
,
4256 irp
->regmap
[X86_RECORD_RESP_REGNUM
]))
4258 regcache_raw_read_unsigned (irp
->regcache
,
4259 irp
->regmap
[X86_RECORD_RESP_REGNUM
],
4261 if (record_full_arch_list_add_mem ((CORE_ADDR
) addr
- size
, size
))
4268 /* Defines contents to record. */
4269 #define I386_SAVE_FPU_REGS 0xfffd
4270 #define I386_SAVE_FPU_ENV 0xfffe
4271 #define I386_SAVE_FPU_ENV_REG_STACK 0xffff
4273 /* Record the values of the floating point registers which will be
4274 changed by the current instruction. Returns -1 if something is
4275 wrong, 0 otherwise. */
4277 static int i386_record_floats (struct gdbarch
*gdbarch
,
4278 struct i386_record_s
*ir
,
4281 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4284 /* Oza: Because of floating point insn push/pop of fpu stack is going to
4285 happen. Currently we store st0-st7 registers, but we need not store all
4286 registers all the time, in future we use ftag register and record only
4287 those who are not marked as an empty. */
4289 if (I386_SAVE_FPU_REGS
== iregnum
)
4291 for (i
= I387_ST0_REGNUM (tdep
); i
<= I387_ST0_REGNUM (tdep
) + 7; i
++)
4293 if (record_full_arch_list_add_reg (ir
->regcache
, i
))
4297 else if (I386_SAVE_FPU_ENV
== iregnum
)
4299 for (i
= I387_FCTRL_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
4301 if (record_full_arch_list_add_reg (ir
->regcache
, i
))
4305 else if (I386_SAVE_FPU_ENV_REG_STACK
== iregnum
)
4307 for (i
= I387_ST0_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
4309 if (record_full_arch_list_add_reg (ir
->regcache
, i
))
4313 else if ((iregnum
>= I387_ST0_REGNUM (tdep
)) &&
4314 (iregnum
<= I387_FOP_REGNUM (tdep
)))
4316 if (record_full_arch_list_add_reg (ir
->regcache
,iregnum
))
4321 /* Parameter error. */
4324 if(I386_SAVE_FPU_ENV
!= iregnum
)
4326 for (i
= I387_FCTRL_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
4328 if (record_full_arch_list_add_reg (ir
->regcache
, i
))
4335 /* Parse the current instruction, and record the values of the
4336 registers and memory that will be changed by the current
4337 instruction. Returns -1 if something goes wrong, 0 otherwise. */
4339 #define I386_RECORD_FULL_ARCH_LIST_ADD_REG(regnum) \
4340 record_full_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)])
4343 i386_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4344 CORE_ADDR input_addr
)
4346 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4352 gdb_byte buf
[MAX_REGISTER_SIZE
];
4353 struct i386_record_s ir
;
4354 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4358 memset (&ir
, 0, sizeof (struct i386_record_s
));
4359 ir
.regcache
= regcache
;
4360 ir
.addr
= input_addr
;
4361 ir
.orig_addr
= input_addr
;
4365 ir
.popl_esp_hack
= 0;
4366 ir
.regmap
= tdep
->record_regmap
;
4367 ir
.gdbarch
= gdbarch
;
4369 if (record_debug
> 1)
4370 fprintf_unfiltered (gdb_stdlog
, "Process record: i386_process_record "
4372 paddress (gdbarch
, ir
.addr
));
4377 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
4380 switch (opcode8
) /* Instruction prefixes */
4382 case REPE_PREFIX_OPCODE
:
4383 prefixes
|= PREFIX_REPZ
;
4385 case REPNE_PREFIX_OPCODE
:
4386 prefixes
|= PREFIX_REPNZ
;
4388 case LOCK_PREFIX_OPCODE
:
4389 prefixes
|= PREFIX_LOCK
;
4391 case CS_PREFIX_OPCODE
:
4392 ir
.override
= X86_RECORD_CS_REGNUM
;
4394 case SS_PREFIX_OPCODE
:
4395 ir
.override
= X86_RECORD_SS_REGNUM
;
4397 case DS_PREFIX_OPCODE
:
4398 ir
.override
= X86_RECORD_DS_REGNUM
;
4400 case ES_PREFIX_OPCODE
:
4401 ir
.override
= X86_RECORD_ES_REGNUM
;
4403 case FS_PREFIX_OPCODE
:
4404 ir
.override
= X86_RECORD_FS_REGNUM
;
4406 case GS_PREFIX_OPCODE
:
4407 ir
.override
= X86_RECORD_GS_REGNUM
;
4409 case DATA_PREFIX_OPCODE
:
4410 prefixes
|= PREFIX_DATA
;
4412 case ADDR_PREFIX_OPCODE
:
4413 prefixes
|= PREFIX_ADDR
;
4415 case 0x40: /* i386 inc %eax */
4416 case 0x41: /* i386 inc %ecx */
4417 case 0x42: /* i386 inc %edx */
4418 case 0x43: /* i386 inc %ebx */
4419 case 0x44: /* i386 inc %esp */
4420 case 0x45: /* i386 inc %ebp */
4421 case 0x46: /* i386 inc %esi */
4422 case 0x47: /* i386 inc %edi */
4423 case 0x48: /* i386 dec %eax */
4424 case 0x49: /* i386 dec %ecx */
4425 case 0x4a: /* i386 dec %edx */
4426 case 0x4b: /* i386 dec %ebx */
4427 case 0x4c: /* i386 dec %esp */
4428 case 0x4d: /* i386 dec %ebp */
4429 case 0x4e: /* i386 dec %esi */
4430 case 0x4f: /* i386 dec %edi */
4431 if (ir
.regmap
[X86_RECORD_R8_REGNUM
]) /* 64 bit target */
4434 rex_w
= (opcode8
>> 3) & 1;
4435 rex_r
= (opcode8
& 0x4) << 1;
4436 ir
.rex_x
= (opcode8
& 0x2) << 2;
4437 ir
.rex_b
= (opcode8
& 0x1) << 3;
4439 else /* 32 bit target */
4448 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && rex_w
== 1)
4454 if (prefixes
& PREFIX_DATA
)
4457 if (prefixes
& PREFIX_ADDR
)
4459 else if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4462 /* Now check op code. */
4463 opcode
= (uint32_t) opcode8
;
4468 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
4471 opcode
= (uint32_t) opcode8
| 0x0f00;
4475 case 0x00: /* arith & logic */
4523 if (((opcode
>> 3) & 7) != OP_CMPL
)
4525 if ((opcode
& 1) == 0)
4528 ir
.ot
= ir
.dflag
+ OT_WORD
;
4530 switch ((opcode
>> 1) & 3)
4532 case 0: /* OP Ev, Gv */
4533 if (i386_record_modrm (&ir
))
4537 if (i386_record_lea_modrm (&ir
))
4543 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4545 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
4548 case 1: /* OP Gv, Ev */
4549 if (i386_record_modrm (&ir
))
4552 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4554 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
4556 case 2: /* OP A, Iv */
4557 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4561 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4564 case 0x80: /* GRP1 */
4568 if (i386_record_modrm (&ir
))
4571 if (ir
.reg
!= OP_CMPL
)
4573 if ((opcode
& 1) == 0)
4576 ir
.ot
= ir
.dflag
+ OT_WORD
;
4583 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
4584 if (i386_record_lea_modrm (&ir
))
4588 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
4590 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4593 case 0x40: /* inc */
4602 case 0x48: /* dec */
4611 I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode
& 7);
4612 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4615 case 0xf6: /* GRP3 */
4617 if ((opcode
& 1) == 0)
4620 ir
.ot
= ir
.dflag
+ OT_WORD
;
4621 if (i386_record_modrm (&ir
))
4624 if (ir
.mod
!= 3 && ir
.reg
== 0)
4625 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
4630 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4636 if (i386_record_lea_modrm (&ir
))
4642 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4644 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
4646 if (ir
.reg
== 3) /* neg */
4647 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4653 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4654 if (ir
.ot
!= OT_BYTE
)
4655 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
4656 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4660 opcode
= opcode
<< 8 | ir
.modrm
;
4666 case 0xfe: /* GRP4 */
4667 case 0xff: /* GRP5 */
4668 if (i386_record_modrm (&ir
))
4670 if (ir
.reg
>= 2 && opcode
== 0xfe)
4673 opcode
= opcode
<< 8 | ir
.modrm
;
4680 if ((opcode
& 1) == 0)
4683 ir
.ot
= ir
.dflag
+ OT_WORD
;
4686 if (i386_record_lea_modrm (&ir
))
4692 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4694 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
4696 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4699 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4701 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4703 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4706 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
4707 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4709 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4713 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4716 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4718 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4723 opcode
= opcode
<< 8 | ir
.modrm
;
4729 case 0x84: /* test */
4733 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4736 case 0x98: /* CWDE/CBW */
4737 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4740 case 0x99: /* CDQ/CWD */
4741 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4742 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
4745 case 0x0faf: /* imul */
4748 ir
.ot
= ir
.dflag
+ OT_WORD
;
4749 if (i386_record_modrm (&ir
))
4752 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
4753 else if (opcode
== 0x6b)
4756 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4758 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
4759 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4762 case 0x0fc0: /* xadd */
4764 if ((opcode
& 1) == 0)
4767 ir
.ot
= ir
.dflag
+ OT_WORD
;
4768 if (i386_record_modrm (&ir
))
4773 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4775 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
4776 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4778 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
4782 if (i386_record_lea_modrm (&ir
))
4784 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4786 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
4788 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4791 case 0x0fb0: /* cmpxchg */
4793 if ((opcode
& 1) == 0)
4796 ir
.ot
= ir
.dflag
+ OT_WORD
;
4797 if (i386_record_modrm (&ir
))
4802 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4803 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4805 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
4809 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4810 if (i386_record_lea_modrm (&ir
))
4813 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4816 case 0x0fc7: /* cmpxchg8b */
4817 if (i386_record_modrm (&ir
))
4822 opcode
= opcode
<< 8 | ir
.modrm
;
4825 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4826 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
4827 if (i386_record_lea_modrm (&ir
))
4829 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4832 case 0x50: /* push */
4842 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4844 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4848 case 0x06: /* push es */
4849 case 0x0e: /* push cs */
4850 case 0x16: /* push ss */
4851 case 0x1e: /* push ds */
4852 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4857 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4861 case 0x0fa0: /* push fs */
4862 case 0x0fa8: /* push gs */
4863 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4868 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4872 case 0x60: /* pusha */
4873 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4878 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 4)))
4882 case 0x58: /* pop */
4890 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4891 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode
& 0x7) | ir
.rex_b
);
4894 case 0x61: /* popa */
4895 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4900 for (regnum
= X86_RECORD_REAX_REGNUM
;
4901 regnum
<= X86_RECORD_REDI_REGNUM
;
4903 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum
);
4906 case 0x8f: /* pop */
4907 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4908 ir
.ot
= ir
.dflag
? OT_QUAD
: OT_WORD
;
4910 ir
.ot
= ir
.dflag
+ OT_WORD
;
4911 if (i386_record_modrm (&ir
))
4914 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
4917 ir
.popl_esp_hack
= 1 << ir
.ot
;
4918 if (i386_record_lea_modrm (&ir
))
4921 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4924 case 0xc8: /* enter */
4925 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
4926 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4928 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4932 case 0xc9: /* leave */
4933 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4934 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
4937 case 0x07: /* pop es */
4938 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4943 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4944 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM
);
4945 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4948 case 0x17: /* pop ss */
4949 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4954 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4955 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM
);
4956 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4959 case 0x1f: /* pop ds */
4960 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4965 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4966 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM
);
4967 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4970 case 0x0fa1: /* pop fs */
4971 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4972 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM
);
4973 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4976 case 0x0fa9: /* pop gs */
4977 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4978 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM
);
4979 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4982 case 0x88: /* mov */
4986 if ((opcode
& 1) == 0)
4989 ir
.ot
= ir
.dflag
+ OT_WORD
;
4991 if (i386_record_modrm (&ir
))
4996 if (opcode
== 0xc6 || opcode
== 0xc7)
4997 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
4998 if (i386_record_lea_modrm (&ir
))
5003 if (opcode
== 0xc6 || opcode
== 0xc7)
5005 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5007 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5011 case 0x8a: /* mov */
5013 if ((opcode
& 1) == 0)
5016 ir
.ot
= ir
.dflag
+ OT_WORD
;
5017 if (i386_record_modrm (&ir
))
5020 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5022 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5025 case 0x8c: /* mov seg */
5026 if (i386_record_modrm (&ir
))
5031 opcode
= opcode
<< 8 | ir
.modrm
;
5036 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5040 if (i386_record_lea_modrm (&ir
))
5045 case 0x8e: /* mov seg */
5046 if (i386_record_modrm (&ir
))
5051 regnum
= X86_RECORD_ES_REGNUM
;
5054 regnum
= X86_RECORD_SS_REGNUM
;
5057 regnum
= X86_RECORD_DS_REGNUM
;
5060 regnum
= X86_RECORD_FS_REGNUM
;
5063 regnum
= X86_RECORD_GS_REGNUM
;
5067 opcode
= opcode
<< 8 | ir
.modrm
;
5071 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum
);
5072 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5075 case 0x0fb6: /* movzbS */
5076 case 0x0fb7: /* movzwS */
5077 case 0x0fbe: /* movsbS */
5078 case 0x0fbf: /* movswS */
5079 if (i386_record_modrm (&ir
))
5081 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
5084 case 0x8d: /* lea */
5085 if (i386_record_modrm (&ir
))
5090 opcode
= opcode
<< 8 | ir
.modrm
;
5095 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5097 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5100 case 0xa0: /* mov EAX */
5103 case 0xd7: /* xlat */
5104 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5107 case 0xa2: /* mov EAX */
5109 if (ir
.override
>= 0)
5111 if (record_full_memory_query
)
5115 target_terminal_ours ();
5117 Process record ignores the memory change of instruction at address %s\n\
5118 because it can't get the value of the segment register.\n\
5119 Do you want to stop the program?"),
5120 paddress (gdbarch
, ir
.orig_addr
));
5121 target_terminal_inferior ();
5128 if ((opcode
& 1) == 0)
5131 ir
.ot
= ir
.dflag
+ OT_WORD
;
5134 if (record_read_memory (gdbarch
, ir
.addr
, buf
, 8))
5137 addr
= extract_unsigned_integer (buf
, 8, byte_order
);
5141 if (record_read_memory (gdbarch
, ir
.addr
, buf
, 4))
5144 addr
= extract_unsigned_integer (buf
, 4, byte_order
);
5148 if (record_read_memory (gdbarch
, ir
.addr
, buf
, 2))
5151 addr
= extract_unsigned_integer (buf
, 2, byte_order
);
5153 if (record_full_arch_list_add_mem (addr
, 1 << ir
.ot
))
5158 case 0xb0: /* mov R, Ib */
5166 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((ir
.regmap
[X86_RECORD_R8_REGNUM
])
5167 ? ((opcode
& 0x7) | ir
.rex_b
)
5168 : ((opcode
& 0x7) & 0x3));
5171 case 0xb8: /* mov R, Iv */
5179 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode
& 0x7) | ir
.rex_b
);
5182 case 0x91: /* xchg R, EAX */
5189 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5190 I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode
& 0x7);
5193 case 0x86: /* xchg Ev, Gv */
5195 if ((opcode
& 1) == 0)
5198 ir
.ot
= ir
.dflag
+ OT_WORD
;
5199 if (i386_record_modrm (&ir
))
5204 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5206 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5210 if (i386_record_lea_modrm (&ir
))
5214 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5216 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5219 case 0xc4: /* les Gv */
5220 case 0xc5: /* lds Gv */
5221 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5227 case 0x0fb2: /* lss Gv */
5228 case 0x0fb4: /* lfs Gv */
5229 case 0x0fb5: /* lgs Gv */
5230 if (i386_record_modrm (&ir
))
5238 opcode
= opcode
<< 8 | ir
.modrm
;
5243 case 0xc4: /* les Gv */
5244 regnum
= X86_RECORD_ES_REGNUM
;
5246 case 0xc5: /* lds Gv */
5247 regnum
= X86_RECORD_DS_REGNUM
;
5249 case 0x0fb2: /* lss Gv */
5250 regnum
= X86_RECORD_SS_REGNUM
;
5252 case 0x0fb4: /* lfs Gv */
5253 regnum
= X86_RECORD_FS_REGNUM
;
5255 case 0x0fb5: /* lgs Gv */
5256 regnum
= X86_RECORD_GS_REGNUM
;
5259 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum
);
5260 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
5261 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5264 case 0xc0: /* shifts */
5270 if ((opcode
& 1) == 0)
5273 ir
.ot
= ir
.dflag
+ OT_WORD
;
5274 if (i386_record_modrm (&ir
))
5276 if (ir
.mod
!= 3 && (opcode
== 0xd2 || opcode
== 0xd3))
5278 if (i386_record_lea_modrm (&ir
))
5284 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5286 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5288 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5295 if (i386_record_modrm (&ir
))
5299 if (record_full_arch_list_add_reg (ir
.regcache
, ir
.rm
))
5304 if (i386_record_lea_modrm (&ir
))
5309 case 0xd8: /* Floats. */
5317 if (i386_record_modrm (&ir
))
5319 ir
.reg
|= ((opcode
& 7) << 3);
5325 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
5333 /* For fcom, ficom nothing to do. */
5339 /* For fcomp, ficomp pop FPU stack, store all. */
5340 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5367 /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul,
5368 fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension
5369 of code, always affects st(0) register. */
5370 if (i386_record_floats (gdbarch
, &ir
, I387_ST0_REGNUM (tdep
)))
5394 /* Handling fld, fild. */
5395 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5399 switch (ir
.reg
>> 4)
5402 if (record_full_arch_list_add_mem (addr64
, 4))
5406 if (record_full_arch_list_add_mem (addr64
, 8))
5412 if (record_full_arch_list_add_mem (addr64
, 2))
5418 switch (ir
.reg
>> 4)
5421 if (record_full_arch_list_add_mem (addr64
, 4))
5423 if (3 == (ir
.reg
& 7))
5425 /* For fstp m32fp. */
5426 if (i386_record_floats (gdbarch
, &ir
,
5427 I386_SAVE_FPU_REGS
))
5432 if (record_full_arch_list_add_mem (addr64
, 4))
5434 if ((3 == (ir
.reg
& 7))
5435 || (5 == (ir
.reg
& 7))
5436 || (7 == (ir
.reg
& 7)))
5438 /* For fstp insn. */
5439 if (i386_record_floats (gdbarch
, &ir
,
5440 I386_SAVE_FPU_REGS
))
5445 if (record_full_arch_list_add_mem (addr64
, 8))
5447 if (3 == (ir
.reg
& 7))
5449 /* For fstp m64fp. */
5450 if (i386_record_floats (gdbarch
, &ir
,
5451 I386_SAVE_FPU_REGS
))
5456 if ((3 <= (ir
.reg
& 7)) && (6 <= (ir
.reg
& 7)))
5458 /* For fistp, fbld, fild, fbstp. */
5459 if (i386_record_floats (gdbarch
, &ir
,
5460 I386_SAVE_FPU_REGS
))
5465 if (record_full_arch_list_add_mem (addr64
, 2))
5474 if (i386_record_floats (gdbarch
, &ir
,
5475 I386_SAVE_FPU_ENV_REG_STACK
))
5480 if (i386_record_floats (gdbarch
, &ir
, I387_FCTRL_REGNUM (tdep
)))
5485 if (i386_record_floats (gdbarch
, &ir
,
5486 I386_SAVE_FPU_ENV_REG_STACK
))
5492 if (record_full_arch_list_add_mem (addr64
, 28))
5497 if (record_full_arch_list_add_mem (addr64
, 14))
5503 if (record_full_arch_list_add_mem (addr64
, 2))
5505 /* Insn fstp, fbstp. */
5506 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5511 if (record_full_arch_list_add_mem (addr64
, 10))
5517 if (record_full_arch_list_add_mem (addr64
, 28))
5523 if (record_full_arch_list_add_mem (addr64
, 14))
5527 if (record_full_arch_list_add_mem (addr64
, 80))
5530 if (i386_record_floats (gdbarch
, &ir
,
5531 I386_SAVE_FPU_ENV_REG_STACK
))
5535 if (record_full_arch_list_add_mem (addr64
, 8))
5538 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5543 opcode
= opcode
<< 8 | ir
.modrm
;
5548 /* Opcode is an extension of modR/M byte. */
5554 if (i386_record_floats (gdbarch
, &ir
, I387_ST0_REGNUM (tdep
)))
5558 if (0x0c == (ir
.modrm
>> 4))
5560 if ((ir
.modrm
& 0x0f) <= 7)
5562 if (i386_record_floats (gdbarch
, &ir
,
5563 I386_SAVE_FPU_REGS
))
5568 if (i386_record_floats (gdbarch
, &ir
,
5569 I387_ST0_REGNUM (tdep
)))
5571 /* If only st(0) is changing, then we have already
5573 if ((ir
.modrm
& 0x0f) - 0x08)
5575 if (i386_record_floats (gdbarch
, &ir
,
5576 I387_ST0_REGNUM (tdep
) +
5577 ((ir
.modrm
& 0x0f) - 0x08)))
5595 if (i386_record_floats (gdbarch
, &ir
,
5596 I387_ST0_REGNUM (tdep
)))
5614 if (i386_record_floats (gdbarch
, &ir
,
5615 I386_SAVE_FPU_REGS
))
5619 if (i386_record_floats (gdbarch
, &ir
,
5620 I387_ST0_REGNUM (tdep
)))
5622 if (i386_record_floats (gdbarch
, &ir
,
5623 I387_ST0_REGNUM (tdep
) + 1))
5630 if (0xe9 == ir
.modrm
)
5632 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5635 else if ((0x0c == ir
.modrm
>> 4) || (0x0d == ir
.modrm
>> 4))
5637 if (i386_record_floats (gdbarch
, &ir
,
5638 I387_ST0_REGNUM (tdep
)))
5640 if (((ir
.modrm
& 0x0f) > 0) && ((ir
.modrm
& 0x0f) <= 7))
5642 if (i386_record_floats (gdbarch
, &ir
,
5643 I387_ST0_REGNUM (tdep
) +
5647 else if ((ir
.modrm
& 0x0f) - 0x08)
5649 if (i386_record_floats (gdbarch
, &ir
,
5650 I387_ST0_REGNUM (tdep
) +
5651 ((ir
.modrm
& 0x0f) - 0x08)))
5657 if (0xe3 == ir
.modrm
)
5659 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_ENV
))
5662 else if ((0x0c == ir
.modrm
>> 4) || (0x0d == ir
.modrm
>> 4))
5664 if (i386_record_floats (gdbarch
, &ir
,
5665 I387_ST0_REGNUM (tdep
)))
5667 if (((ir
.modrm
& 0x0f) > 0) && ((ir
.modrm
& 0x0f) <= 7))
5669 if (i386_record_floats (gdbarch
, &ir
,
5670 I387_ST0_REGNUM (tdep
) +
5674 else if ((ir
.modrm
& 0x0f) - 0x08)
5676 if (i386_record_floats (gdbarch
, &ir
,
5677 I387_ST0_REGNUM (tdep
) +
5678 ((ir
.modrm
& 0x0f) - 0x08)))
5684 if ((0x0c == ir
.modrm
>> 4)
5685 || (0x0d == ir
.modrm
>> 4)
5686 || (0x0f == ir
.modrm
>> 4))
5688 if ((ir
.modrm
& 0x0f) <= 7)
5690 if (i386_record_floats (gdbarch
, &ir
,
5691 I387_ST0_REGNUM (tdep
) +
5697 if (i386_record_floats (gdbarch
, &ir
,
5698 I387_ST0_REGNUM (tdep
) +
5699 ((ir
.modrm
& 0x0f) - 0x08)))
5705 if (0x0c == ir
.modrm
>> 4)
5707 if (i386_record_floats (gdbarch
, &ir
,
5708 I387_FTAG_REGNUM (tdep
)))
5711 else if ((0x0d == ir
.modrm
>> 4) || (0x0e == ir
.modrm
>> 4))
5713 if ((ir
.modrm
& 0x0f) <= 7)
5715 if (i386_record_floats (gdbarch
, &ir
,
5716 I387_ST0_REGNUM (tdep
) +
5722 if (i386_record_floats (gdbarch
, &ir
,
5723 I386_SAVE_FPU_REGS
))
5729 if ((0x0c == ir
.modrm
>> 4)
5730 || (0x0e == ir
.modrm
>> 4)
5731 || (0x0f == ir
.modrm
>> 4)
5732 || (0xd9 == ir
.modrm
))
5734 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5739 if (0xe0 == ir
.modrm
)
5741 if (record_full_arch_list_add_reg (ir
.regcache
,
5745 else if ((0x0f == ir
.modrm
>> 4) || (0x0e == ir
.modrm
>> 4))
5747 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5755 case 0xa4: /* movsS */
5757 case 0xaa: /* stosS */
5759 case 0x6c: /* insS */
5761 regcache_raw_read_unsigned (ir
.regcache
,
5762 ir
.regmap
[X86_RECORD_RECX_REGNUM
],
5768 if ((opcode
& 1) == 0)
5771 ir
.ot
= ir
.dflag
+ OT_WORD
;
5772 regcache_raw_read_unsigned (ir
.regcache
,
5773 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
5776 regcache_raw_read_unsigned (ir
.regcache
,
5777 ir
.regmap
[X86_RECORD_ES_REGNUM
],
5779 regcache_raw_read_unsigned (ir
.regcache
,
5780 ir
.regmap
[X86_RECORD_DS_REGNUM
],
5782 if (ir
.aflag
&& (es
!= ds
))
5784 /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */
5785 if (record_full_memory_query
)
5789 target_terminal_ours ();
5791 Process record ignores the memory change of instruction at address %s\n\
5792 because it can't get the value of the segment register.\n\
5793 Do you want to stop the program?"),
5794 paddress (gdbarch
, ir
.orig_addr
));
5795 target_terminal_inferior ();
5802 if (record_full_arch_list_add_mem (addr
, 1 << ir
.ot
))
5806 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5807 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5808 if (opcode
== 0xa4 || opcode
== 0xa5)
5809 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
5810 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
5811 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5815 case 0xa6: /* cmpsS */
5817 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
5818 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
5819 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5820 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5821 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5824 case 0xac: /* lodsS */
5826 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5827 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
5828 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5829 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5830 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5833 case 0xae: /* scasS */
5835 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
5836 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5837 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5838 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5841 case 0x6e: /* outsS */
5843 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
5844 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5845 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5846 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5849 case 0xe4: /* port I/O */
5853 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5854 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5864 case 0xc2: /* ret im */
5865 case 0xc3: /* ret */
5866 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5867 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5870 case 0xca: /* lret im */
5871 case 0xcb: /* lret */
5872 case 0xcf: /* iret */
5873 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
5874 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5875 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5878 case 0xe8: /* call im */
5879 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5881 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5885 case 0x9a: /* lcall im */
5886 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5891 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
5892 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5896 case 0xe9: /* jmp im */
5897 case 0xea: /* ljmp im */
5898 case 0xeb: /* jmp Jb */
5899 case 0x70: /* jcc Jb */
5915 case 0x0f80: /* jcc Jv */
5933 case 0x0f90: /* setcc Gv */
5949 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5951 if (i386_record_modrm (&ir
))
5954 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rex_b
? (ir
.rm
| ir
.rex_b
)
5958 if (i386_record_lea_modrm (&ir
))
5963 case 0x0f40: /* cmov Gv, Ev */
5979 if (i386_record_modrm (&ir
))
5982 if (ir
.dflag
== OT_BYTE
)
5984 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5988 case 0x9c: /* pushf */
5989 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5990 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5992 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5996 case 0x9d: /* popf */
5997 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5998 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6001 case 0x9e: /* sahf */
6002 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6008 case 0xf5: /* cmc */
6009 case 0xf8: /* clc */
6010 case 0xf9: /* stc */
6011 case 0xfc: /* cld */
6012 case 0xfd: /* std */
6013 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6016 case 0x9f: /* lahf */
6017 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6022 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6023 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6026 /* bit operations */
6027 case 0x0fba: /* bt/bts/btr/btc Gv, im */
6028 ir
.ot
= ir
.dflag
+ OT_WORD
;
6029 if (i386_record_modrm (&ir
))
6034 opcode
= opcode
<< 8 | ir
.modrm
;
6040 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6043 if (i386_record_lea_modrm (&ir
))
6047 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6050 case 0x0fa3: /* bt Gv, Ev */
6051 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6054 case 0x0fab: /* bts */
6055 case 0x0fb3: /* btr */
6056 case 0x0fbb: /* btc */
6057 ir
.ot
= ir
.dflag
+ OT_WORD
;
6058 if (i386_record_modrm (&ir
))
6061 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6065 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
6067 regcache_raw_read_unsigned (ir
.regcache
,
6068 ir
.regmap
[ir
.reg
| rex_r
],
6073 addr64
+= ((int16_t) addr
>> 4) << 4;
6076 addr64
+= ((int32_t) addr
>> 5) << 5;
6079 addr64
+= ((int64_t) addr
>> 6) << 6;
6082 if (record_full_arch_list_add_mem (addr64
, 1 << ir
.ot
))
6084 if (i386_record_lea_modrm (&ir
))
6087 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6090 case 0x0fbc: /* bsf */
6091 case 0x0fbd: /* bsr */
6092 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
6093 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6097 case 0x27: /* daa */
6098 case 0x2f: /* das */
6099 case 0x37: /* aaa */
6100 case 0x3f: /* aas */
6101 case 0xd4: /* aam */
6102 case 0xd5: /* aad */
6103 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6108 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6109 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6113 case 0x90: /* nop */
6114 if (prefixes
& PREFIX_LOCK
)
6121 case 0x9b: /* fwait */
6122 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
6124 opcode
= (uint32_t) opcode8
;
6130 case 0xcc: /* int3 */
6131 printf_unfiltered (_("Process record does not support instruction "
6138 case 0xcd: /* int */
6142 if (record_read_memory (gdbarch
, ir
.addr
, &interrupt
, 1))
6145 if (interrupt
!= 0x80
6146 || tdep
->i386_intx80_record
== NULL
)
6148 printf_unfiltered (_("Process record does not support "
6149 "instruction int 0x%02x.\n"),
6154 ret
= tdep
->i386_intx80_record (ir
.regcache
);
6161 case 0xce: /* into */
6162 printf_unfiltered (_("Process record does not support "
6163 "instruction into.\n"));
6168 case 0xfa: /* cli */
6169 case 0xfb: /* sti */
6172 case 0x62: /* bound */
6173 printf_unfiltered (_("Process record does not support "
6174 "instruction bound.\n"));
6179 case 0x0fc8: /* bswap reg */
6187 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode
& 7) | ir
.rex_b
);
6190 case 0xd6: /* salc */
6191 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6196 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6197 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6200 case 0xe0: /* loopnz */
6201 case 0xe1: /* loopz */
6202 case 0xe2: /* loop */
6203 case 0xe3: /* jecxz */
6204 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6205 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6208 case 0x0f30: /* wrmsr */
6209 printf_unfiltered (_("Process record does not support "
6210 "instruction wrmsr.\n"));
6215 case 0x0f32: /* rdmsr */
6216 printf_unfiltered (_("Process record does not support "
6217 "instruction rdmsr.\n"));
6222 case 0x0f31: /* rdtsc */
6223 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6224 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
6227 case 0x0f34: /* sysenter */
6230 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6235 if (tdep
->i386_sysenter_record
== NULL
)
6237 printf_unfiltered (_("Process record does not support "
6238 "instruction sysenter.\n"));
6242 ret
= tdep
->i386_sysenter_record (ir
.regcache
);
6248 case 0x0f35: /* sysexit */
6249 printf_unfiltered (_("Process record does not support "
6250 "instruction sysexit.\n"));
6255 case 0x0f05: /* syscall */
6258 if (tdep
->i386_syscall_record
== NULL
)
6260 printf_unfiltered (_("Process record does not support "
6261 "instruction syscall.\n"));
6265 ret
= tdep
->i386_syscall_record (ir
.regcache
);
6271 case 0x0f07: /* sysret */
6272 printf_unfiltered (_("Process record does not support "
6273 "instruction sysret.\n"));
6278 case 0x0fa2: /* cpuid */
6279 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6280 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6281 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
6282 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM
);
6285 case 0xf4: /* hlt */
6286 printf_unfiltered (_("Process record does not support "
6287 "instruction hlt.\n"));
6293 if (i386_record_modrm (&ir
))
6300 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6304 if (i386_record_lea_modrm (&ir
))
6313 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6317 opcode
= opcode
<< 8 | ir
.modrm
;
6324 if (i386_record_modrm (&ir
))
6335 opcode
= opcode
<< 8 | ir
.modrm
;
6338 if (ir
.override
>= 0)
6340 if (record_full_memory_query
)
6344 target_terminal_ours ();
6346 Process record ignores the memory change of instruction at address %s\n\
6347 because it can't get the value of the segment register.\n\
6348 Do you want to stop the program?"),
6349 paddress (gdbarch
, ir
.orig_addr
));
6350 target_terminal_inferior ();
6357 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
6359 if (record_full_arch_list_add_mem (addr64
, 2))
6362 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6364 if (record_full_arch_list_add_mem (addr64
, 8))
6369 if (record_full_arch_list_add_mem (addr64
, 4))
6380 case 0: /* monitor */
6383 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6387 opcode
= opcode
<< 8 | ir
.modrm
;
6395 if (ir
.override
>= 0)
6397 if (record_full_memory_query
)
6401 target_terminal_ours ();
6403 Process record ignores the memory change of instruction at address %s\n\
6404 because it can't get the value of the segment register.\n\
6405 Do you want to stop the program?"),
6406 paddress (gdbarch
, ir
.orig_addr
));
6407 target_terminal_inferior ();
6416 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
6418 if (record_full_arch_list_add_mem (addr64
, 2))
6421 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6423 if (record_full_arch_list_add_mem (addr64
, 8))
6428 if (record_full_arch_list_add_mem (addr64
, 4))
6440 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6441 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
6445 else if (ir
.rm
== 1)
6452 opcode
= opcode
<< 8 | ir
.modrm
;
6459 if (record_full_arch_list_add_reg (ir
.regcache
, ir
.rm
| ir
.rex_b
))
6465 if (i386_record_lea_modrm (&ir
))
6468 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6471 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6473 case 7: /* invlpg */
6476 if (ir
.rm
== 0 && ir
.regmap
[X86_RECORD_R8_REGNUM
])
6477 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM
);
6481 opcode
= opcode
<< 8 | ir
.modrm
;
6486 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6490 opcode
= opcode
<< 8 | ir
.modrm
;
6496 case 0x0f08: /* invd */
6497 case 0x0f09: /* wbinvd */
6500 case 0x63: /* arpl */
6501 if (i386_record_modrm (&ir
))
6503 if (ir
.mod
== 3 || ir
.regmap
[X86_RECORD_R8_REGNUM
])
6505 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.regmap
[X86_RECORD_R8_REGNUM
]
6506 ? (ir
.reg
| rex_r
) : ir
.rm
);
6510 ir
.ot
= ir
.dflag
? OT_LONG
: OT_WORD
;
6511 if (i386_record_lea_modrm (&ir
))
6514 if (!ir
.regmap
[X86_RECORD_R8_REGNUM
])
6515 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6518 case 0x0f02: /* lar */
6519 case 0x0f03: /* lsl */
6520 if (i386_record_modrm (&ir
))
6522 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
6523 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6527 if (i386_record_modrm (&ir
))
6529 if (ir
.mod
== 3 && ir
.reg
== 3)
6532 opcode
= opcode
<< 8 | ir
.modrm
;
6544 /* nop (multi byte) */
6547 case 0x0f20: /* mov reg, crN */
6548 case 0x0f22: /* mov crN, reg */
6549 if (i386_record_modrm (&ir
))
6551 if ((ir
.modrm
& 0xc0) != 0xc0)
6554 opcode
= opcode
<< 8 | ir
.modrm
;
6565 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6567 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6571 opcode
= opcode
<< 8 | ir
.modrm
;
6577 case 0x0f21: /* mov reg, drN */
6578 case 0x0f23: /* mov drN, reg */
6579 if (i386_record_modrm (&ir
))
6581 if ((ir
.modrm
& 0xc0) != 0xc0 || ir
.reg
== 4
6582 || ir
.reg
== 5 || ir
.reg
>= 8)
6585 opcode
= opcode
<< 8 | ir
.modrm
;
6589 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6591 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6594 case 0x0f06: /* clts */
6595 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6598 /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */
6600 case 0x0f0d: /* 3DNow! prefetch */
6603 case 0x0f0e: /* 3DNow! femms */
6604 case 0x0f77: /* emms */
6605 if (i386_fpc_regnum_p (gdbarch
, I387_FTAG_REGNUM(tdep
)))
6607 record_full_arch_list_add_reg (ir
.regcache
, I387_FTAG_REGNUM(tdep
));
6610 case 0x0f0f: /* 3DNow! data */
6611 if (i386_record_modrm (&ir
))
6613 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
6618 case 0x0c: /* 3DNow! pi2fw */
6619 case 0x0d: /* 3DNow! pi2fd */
6620 case 0x1c: /* 3DNow! pf2iw */
6621 case 0x1d: /* 3DNow! pf2id */
6622 case 0x8a: /* 3DNow! pfnacc */
6623 case 0x8e: /* 3DNow! pfpnacc */
6624 case 0x90: /* 3DNow! pfcmpge */
6625 case 0x94: /* 3DNow! pfmin */
6626 case 0x96: /* 3DNow! pfrcp */
6627 case 0x97: /* 3DNow! pfrsqrt */
6628 case 0x9a: /* 3DNow! pfsub */
6629 case 0x9e: /* 3DNow! pfadd */
6630 case 0xa0: /* 3DNow! pfcmpgt */
6631 case 0xa4: /* 3DNow! pfmax */
6632 case 0xa6: /* 3DNow! pfrcpit1 */
6633 case 0xa7: /* 3DNow! pfrsqit1 */
6634 case 0xaa: /* 3DNow! pfsubr */
6635 case 0xae: /* 3DNow! pfacc */
6636 case 0xb0: /* 3DNow! pfcmpeq */
6637 case 0xb4: /* 3DNow! pfmul */
6638 case 0xb6: /* 3DNow! pfrcpit2 */
6639 case 0xb7: /* 3DNow! pmulhrw */
6640 case 0xbb: /* 3DNow! pswapd */
6641 case 0xbf: /* 3DNow! pavgusb */
6642 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.reg
))
6643 goto no_support_3dnow_data
;
6644 record_full_arch_list_add_reg (ir
.regcache
, ir
.reg
);
6648 no_support_3dnow_data
:
6649 opcode
= (opcode
<< 8) | opcode8
;
6655 case 0x0faa: /* rsm */
6656 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6657 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6658 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6659 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
6660 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM
);
6661 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
6662 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
6663 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
6664 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
6668 if (i386_record_modrm (&ir
))
6672 case 0: /* fxsave */
6676 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6677 if (i386_record_lea_modrm_addr (&ir
, &tmpu64
))
6679 if (record_full_arch_list_add_mem (tmpu64
, 512))
6684 case 1: /* fxrstor */
6688 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6690 for (i
= I387_MM0_REGNUM (tdep
);
6691 i386_mmx_regnum_p (gdbarch
, i
); i
++)
6692 record_full_arch_list_add_reg (ir
.regcache
, i
);
6694 for (i
= I387_XMM0_REGNUM (tdep
);
6695 i386_xmm_regnum_p (gdbarch
, i
); i
++)
6696 record_full_arch_list_add_reg (ir
.regcache
, i
);
6698 if (i386_mxcsr_regnum_p (gdbarch
, I387_MXCSR_REGNUM(tdep
)))
6699 record_full_arch_list_add_reg (ir
.regcache
,
6700 I387_MXCSR_REGNUM(tdep
));
6702 for (i
= I387_ST0_REGNUM (tdep
);
6703 i386_fp_regnum_p (gdbarch
, i
); i
++)
6704 record_full_arch_list_add_reg (ir
.regcache
, i
);
6706 for (i
= I387_FCTRL_REGNUM (tdep
);
6707 i386_fpc_regnum_p (gdbarch
, i
); i
++)
6708 record_full_arch_list_add_reg (ir
.regcache
, i
);
6712 case 2: /* ldmxcsr */
6713 if (!i386_mxcsr_regnum_p (gdbarch
, I387_MXCSR_REGNUM(tdep
)))
6715 record_full_arch_list_add_reg (ir
.regcache
, I387_MXCSR_REGNUM(tdep
));
6718 case 3: /* stmxcsr */
6720 if (i386_record_lea_modrm (&ir
))
6724 case 5: /* lfence */
6725 case 6: /* mfence */
6726 case 7: /* sfence clflush */
6730 opcode
= (opcode
<< 8) | ir
.modrm
;
6736 case 0x0fc3: /* movnti */
6737 ir
.ot
= (ir
.dflag
== 2) ? OT_QUAD
: OT_LONG
;
6738 if (i386_record_modrm (&ir
))
6743 if (i386_record_lea_modrm (&ir
))
6747 /* Add prefix to opcode. */
6874 reswitch_prefix_add
:
6882 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
6885 opcode
= (uint32_t) opcode8
| opcode
<< 8;
6886 goto reswitch_prefix_add
;
6889 case 0x0f10: /* movups */
6890 case 0x660f10: /* movupd */
6891 case 0xf30f10: /* movss */
6892 case 0xf20f10: /* movsd */
6893 case 0x0f12: /* movlps */
6894 case 0x660f12: /* movlpd */
6895 case 0xf30f12: /* movsldup */
6896 case 0xf20f12: /* movddup */
6897 case 0x0f14: /* unpcklps */
6898 case 0x660f14: /* unpcklpd */
6899 case 0x0f15: /* unpckhps */
6900 case 0x660f15: /* unpckhpd */
6901 case 0x0f16: /* movhps */
6902 case 0x660f16: /* movhpd */
6903 case 0xf30f16: /* movshdup */
6904 case 0x0f28: /* movaps */
6905 case 0x660f28: /* movapd */
6906 case 0x0f2a: /* cvtpi2ps */
6907 case 0x660f2a: /* cvtpi2pd */
6908 case 0xf30f2a: /* cvtsi2ss */
6909 case 0xf20f2a: /* cvtsi2sd */
6910 case 0x0f2c: /* cvttps2pi */
6911 case 0x660f2c: /* cvttpd2pi */
6912 case 0x0f2d: /* cvtps2pi */
6913 case 0x660f2d: /* cvtpd2pi */
6914 case 0x660f3800: /* pshufb */
6915 case 0x660f3801: /* phaddw */
6916 case 0x660f3802: /* phaddd */
6917 case 0x660f3803: /* phaddsw */
6918 case 0x660f3804: /* pmaddubsw */
6919 case 0x660f3805: /* phsubw */
6920 case 0x660f3806: /* phsubd */
6921 case 0x660f3807: /* phsubsw */
6922 case 0x660f3808: /* psignb */
6923 case 0x660f3809: /* psignw */
6924 case 0x660f380a: /* psignd */
6925 case 0x660f380b: /* pmulhrsw */
6926 case 0x660f3810: /* pblendvb */
6927 case 0x660f3814: /* blendvps */
6928 case 0x660f3815: /* blendvpd */
6929 case 0x660f381c: /* pabsb */
6930 case 0x660f381d: /* pabsw */
6931 case 0x660f381e: /* pabsd */
6932 case 0x660f3820: /* pmovsxbw */
6933 case 0x660f3821: /* pmovsxbd */
6934 case 0x660f3822: /* pmovsxbq */
6935 case 0x660f3823: /* pmovsxwd */
6936 case 0x660f3824: /* pmovsxwq */
6937 case 0x660f3825: /* pmovsxdq */
6938 case 0x660f3828: /* pmuldq */
6939 case 0x660f3829: /* pcmpeqq */
6940 case 0x660f382a: /* movntdqa */
6941 case 0x660f3a08: /* roundps */
6942 case 0x660f3a09: /* roundpd */
6943 case 0x660f3a0a: /* roundss */
6944 case 0x660f3a0b: /* roundsd */
6945 case 0x660f3a0c: /* blendps */
6946 case 0x660f3a0d: /* blendpd */
6947 case 0x660f3a0e: /* pblendw */
6948 case 0x660f3a0f: /* palignr */
6949 case 0x660f3a20: /* pinsrb */
6950 case 0x660f3a21: /* insertps */
6951 case 0x660f3a22: /* pinsrd pinsrq */
6952 case 0x660f3a40: /* dpps */
6953 case 0x660f3a41: /* dppd */
6954 case 0x660f3a42: /* mpsadbw */
6955 case 0x660f3a60: /* pcmpestrm */
6956 case 0x660f3a61: /* pcmpestri */
6957 case 0x660f3a62: /* pcmpistrm */
6958 case 0x660f3a63: /* pcmpistri */
6959 case 0x0f51: /* sqrtps */
6960 case 0x660f51: /* sqrtpd */
6961 case 0xf20f51: /* sqrtsd */
6962 case 0xf30f51: /* sqrtss */
6963 case 0x0f52: /* rsqrtps */
6964 case 0xf30f52: /* rsqrtss */
6965 case 0x0f53: /* rcpps */
6966 case 0xf30f53: /* rcpss */
6967 case 0x0f54: /* andps */
6968 case 0x660f54: /* andpd */
6969 case 0x0f55: /* andnps */
6970 case 0x660f55: /* andnpd */
6971 case 0x0f56: /* orps */
6972 case 0x660f56: /* orpd */
6973 case 0x0f57: /* xorps */
6974 case 0x660f57: /* xorpd */
6975 case 0x0f58: /* addps */
6976 case 0x660f58: /* addpd */
6977 case 0xf20f58: /* addsd */
6978 case 0xf30f58: /* addss */
6979 case 0x0f59: /* mulps */
6980 case 0x660f59: /* mulpd */
6981 case 0xf20f59: /* mulsd */
6982 case 0xf30f59: /* mulss */
6983 case 0x0f5a: /* cvtps2pd */
6984 case 0x660f5a: /* cvtpd2ps */
6985 case 0xf20f5a: /* cvtsd2ss */
6986 case 0xf30f5a: /* cvtss2sd */
6987 case 0x0f5b: /* cvtdq2ps */
6988 case 0x660f5b: /* cvtps2dq */
6989 case 0xf30f5b: /* cvttps2dq */
6990 case 0x0f5c: /* subps */
6991 case 0x660f5c: /* subpd */
6992 case 0xf20f5c: /* subsd */
6993 case 0xf30f5c: /* subss */
6994 case 0x0f5d: /* minps */
6995 case 0x660f5d: /* minpd */
6996 case 0xf20f5d: /* minsd */
6997 case 0xf30f5d: /* minss */
6998 case 0x0f5e: /* divps */
6999 case 0x660f5e: /* divpd */
7000 case 0xf20f5e: /* divsd */
7001 case 0xf30f5e: /* divss */
7002 case 0x0f5f: /* maxps */
7003 case 0x660f5f: /* maxpd */
7004 case 0xf20f5f: /* maxsd */
7005 case 0xf30f5f: /* maxss */
7006 case 0x660f60: /* punpcklbw */
7007 case 0x660f61: /* punpcklwd */
7008 case 0x660f62: /* punpckldq */
7009 case 0x660f63: /* packsswb */
7010 case 0x660f64: /* pcmpgtb */
7011 case 0x660f65: /* pcmpgtw */
7012 case 0x660f66: /* pcmpgtd */
7013 case 0x660f67: /* packuswb */
7014 case 0x660f68: /* punpckhbw */
7015 case 0x660f69: /* punpckhwd */
7016 case 0x660f6a: /* punpckhdq */
7017 case 0x660f6b: /* packssdw */
7018 case 0x660f6c: /* punpcklqdq */
7019 case 0x660f6d: /* punpckhqdq */
7020 case 0x660f6e: /* movd */
7021 case 0x660f6f: /* movdqa */
7022 case 0xf30f6f: /* movdqu */
7023 case 0x660f70: /* pshufd */
7024 case 0xf20f70: /* pshuflw */
7025 case 0xf30f70: /* pshufhw */
7026 case 0x660f74: /* pcmpeqb */
7027 case 0x660f75: /* pcmpeqw */
7028 case 0x660f76: /* pcmpeqd */
7029 case 0x660f7c: /* haddpd */
7030 case 0xf20f7c: /* haddps */
7031 case 0x660f7d: /* hsubpd */
7032 case 0xf20f7d: /* hsubps */
7033 case 0xf30f7e: /* movq */
7034 case 0x0fc2: /* cmpps */
7035 case 0x660fc2: /* cmppd */
7036 case 0xf20fc2: /* cmpsd */
7037 case 0xf30fc2: /* cmpss */
7038 case 0x660fc4: /* pinsrw */
7039 case 0x0fc6: /* shufps */
7040 case 0x660fc6: /* shufpd */
7041 case 0x660fd0: /* addsubpd */
7042 case 0xf20fd0: /* addsubps */
7043 case 0x660fd1: /* psrlw */
7044 case 0x660fd2: /* psrld */
7045 case 0x660fd3: /* psrlq */
7046 case 0x660fd4: /* paddq */
7047 case 0x660fd5: /* pmullw */
7048 case 0xf30fd6: /* movq2dq */
7049 case 0x660fd8: /* psubusb */
7050 case 0x660fd9: /* psubusw */
7051 case 0x660fda: /* pminub */
7052 case 0x660fdb: /* pand */
7053 case 0x660fdc: /* paddusb */
7054 case 0x660fdd: /* paddusw */
7055 case 0x660fde: /* pmaxub */
7056 case 0x660fdf: /* pandn */
7057 case 0x660fe0: /* pavgb */
7058 case 0x660fe1: /* psraw */
7059 case 0x660fe2: /* psrad */
7060 case 0x660fe3: /* pavgw */
7061 case 0x660fe4: /* pmulhuw */
7062 case 0x660fe5: /* pmulhw */
7063 case 0x660fe6: /* cvttpd2dq */
7064 case 0xf20fe6: /* cvtpd2dq */
7065 case 0xf30fe6: /* cvtdq2pd */
7066 case 0x660fe8: /* psubsb */
7067 case 0x660fe9: /* psubsw */
7068 case 0x660fea: /* pminsw */
7069 case 0x660feb: /* por */
7070 case 0x660fec: /* paddsb */
7071 case 0x660fed: /* paddsw */
7072 case 0x660fee: /* pmaxsw */
7073 case 0x660fef: /* pxor */
7074 case 0xf20ff0: /* lddqu */
7075 case 0x660ff1: /* psllw */
7076 case 0x660ff2: /* pslld */
7077 case 0x660ff3: /* psllq */
7078 case 0x660ff4: /* pmuludq */
7079 case 0x660ff5: /* pmaddwd */
7080 case 0x660ff6: /* psadbw */
7081 case 0x660ff8: /* psubb */
7082 case 0x660ff9: /* psubw */
7083 case 0x660ffa: /* psubd */
7084 case 0x660ffb: /* psubq */
7085 case 0x660ffc: /* paddb */
7086 case 0x660ffd: /* paddw */
7087 case 0x660ffe: /* paddd */
7088 if (i386_record_modrm (&ir
))
7091 if (!i386_xmm_regnum_p (gdbarch
, I387_XMM0_REGNUM (tdep
) + ir
.reg
))
7093 record_full_arch_list_add_reg (ir
.regcache
,
7094 I387_XMM0_REGNUM (tdep
) + ir
.reg
);
7095 if ((opcode
& 0xfffffffc) == 0x660f3a60)
7096 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7099 case 0x0f11: /* movups */
7100 case 0x660f11: /* movupd */
7101 case 0xf30f11: /* movss */
7102 case 0xf20f11: /* movsd */
7103 case 0x0f13: /* movlps */
7104 case 0x660f13: /* movlpd */
7105 case 0x0f17: /* movhps */
7106 case 0x660f17: /* movhpd */
7107 case 0x0f29: /* movaps */
7108 case 0x660f29: /* movapd */
7109 case 0x660f3a14: /* pextrb */
7110 case 0x660f3a15: /* pextrw */
7111 case 0x660f3a16: /* pextrd pextrq */
7112 case 0x660f3a17: /* extractps */
7113 case 0x660f7f: /* movdqa */
7114 case 0xf30f7f: /* movdqu */
7115 if (i386_record_modrm (&ir
))
7119 if (opcode
== 0x0f13 || opcode
== 0x660f13
7120 || opcode
== 0x0f17 || opcode
== 0x660f17)
7123 if (!i386_xmm_regnum_p (gdbarch
,
7124 I387_XMM0_REGNUM (tdep
) + ir
.rm
))
7126 record_full_arch_list_add_reg (ir
.regcache
,
7127 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
7149 if (i386_record_lea_modrm (&ir
))
7154 case 0x0f2b: /* movntps */
7155 case 0x660f2b: /* movntpd */
7156 case 0x0fe7: /* movntq */
7157 case 0x660fe7: /* movntdq */
7160 if (opcode
== 0x0fe7)
7164 if (i386_record_lea_modrm (&ir
))
7168 case 0xf30f2c: /* cvttss2si */
7169 case 0xf20f2c: /* cvttsd2si */
7170 case 0xf30f2d: /* cvtss2si */
7171 case 0xf20f2d: /* cvtsd2si */
7172 case 0xf20f38f0: /* crc32 */
7173 case 0xf20f38f1: /* crc32 */
7174 case 0x0f50: /* movmskps */
7175 case 0x660f50: /* movmskpd */
7176 case 0x0fc5: /* pextrw */
7177 case 0x660fc5: /* pextrw */
7178 case 0x0fd7: /* pmovmskb */
7179 case 0x660fd7: /* pmovmskb */
7180 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
7183 case 0x0f3800: /* pshufb */
7184 case 0x0f3801: /* phaddw */
7185 case 0x0f3802: /* phaddd */
7186 case 0x0f3803: /* phaddsw */
7187 case 0x0f3804: /* pmaddubsw */
7188 case 0x0f3805: /* phsubw */
7189 case 0x0f3806: /* phsubd */
7190 case 0x0f3807: /* phsubsw */
7191 case 0x0f3808: /* psignb */
7192 case 0x0f3809: /* psignw */
7193 case 0x0f380a: /* psignd */
7194 case 0x0f380b: /* pmulhrsw */
7195 case 0x0f381c: /* pabsb */
7196 case 0x0f381d: /* pabsw */
7197 case 0x0f381e: /* pabsd */
7198 case 0x0f382b: /* packusdw */
7199 case 0x0f3830: /* pmovzxbw */
7200 case 0x0f3831: /* pmovzxbd */
7201 case 0x0f3832: /* pmovzxbq */
7202 case 0x0f3833: /* pmovzxwd */
7203 case 0x0f3834: /* pmovzxwq */
7204 case 0x0f3835: /* pmovzxdq */
7205 case 0x0f3837: /* pcmpgtq */
7206 case 0x0f3838: /* pminsb */
7207 case 0x0f3839: /* pminsd */
7208 case 0x0f383a: /* pminuw */
7209 case 0x0f383b: /* pminud */
7210 case 0x0f383c: /* pmaxsb */
7211 case 0x0f383d: /* pmaxsd */
7212 case 0x0f383e: /* pmaxuw */
7213 case 0x0f383f: /* pmaxud */
7214 case 0x0f3840: /* pmulld */
7215 case 0x0f3841: /* phminposuw */
7216 case 0x0f3a0f: /* palignr */
7217 case 0x0f60: /* punpcklbw */
7218 case 0x0f61: /* punpcklwd */
7219 case 0x0f62: /* punpckldq */
7220 case 0x0f63: /* packsswb */
7221 case 0x0f64: /* pcmpgtb */
7222 case 0x0f65: /* pcmpgtw */
7223 case 0x0f66: /* pcmpgtd */
7224 case 0x0f67: /* packuswb */
7225 case 0x0f68: /* punpckhbw */
7226 case 0x0f69: /* punpckhwd */
7227 case 0x0f6a: /* punpckhdq */
7228 case 0x0f6b: /* packssdw */
7229 case 0x0f6e: /* movd */
7230 case 0x0f6f: /* movq */
7231 case 0x0f70: /* pshufw */
7232 case 0x0f74: /* pcmpeqb */
7233 case 0x0f75: /* pcmpeqw */
7234 case 0x0f76: /* pcmpeqd */
7235 case 0x0fc4: /* pinsrw */
7236 case 0x0fd1: /* psrlw */
7237 case 0x0fd2: /* psrld */
7238 case 0x0fd3: /* psrlq */
7239 case 0x0fd4: /* paddq */
7240 case 0x0fd5: /* pmullw */
7241 case 0xf20fd6: /* movdq2q */
7242 case 0x0fd8: /* psubusb */
7243 case 0x0fd9: /* psubusw */
7244 case 0x0fda: /* pminub */
7245 case 0x0fdb: /* pand */
7246 case 0x0fdc: /* paddusb */
7247 case 0x0fdd: /* paddusw */
7248 case 0x0fde: /* pmaxub */
7249 case 0x0fdf: /* pandn */
7250 case 0x0fe0: /* pavgb */
7251 case 0x0fe1: /* psraw */
7252 case 0x0fe2: /* psrad */
7253 case 0x0fe3: /* pavgw */
7254 case 0x0fe4: /* pmulhuw */
7255 case 0x0fe5: /* pmulhw */
7256 case 0x0fe8: /* psubsb */
7257 case 0x0fe9: /* psubsw */
7258 case 0x0fea: /* pminsw */
7259 case 0x0feb: /* por */
7260 case 0x0fec: /* paddsb */
7261 case 0x0fed: /* paddsw */
7262 case 0x0fee: /* pmaxsw */
7263 case 0x0fef: /* pxor */
7264 case 0x0ff1: /* psllw */
7265 case 0x0ff2: /* pslld */
7266 case 0x0ff3: /* psllq */
7267 case 0x0ff4: /* pmuludq */
7268 case 0x0ff5: /* pmaddwd */
7269 case 0x0ff6: /* psadbw */
7270 case 0x0ff8: /* psubb */
7271 case 0x0ff9: /* psubw */
7272 case 0x0ffa: /* psubd */
7273 case 0x0ffb: /* psubq */
7274 case 0x0ffc: /* paddb */
7275 case 0x0ffd: /* paddw */
7276 case 0x0ffe: /* paddd */
7277 if (i386_record_modrm (&ir
))
7279 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.reg
))
7281 record_full_arch_list_add_reg (ir
.regcache
,
7282 I387_MM0_REGNUM (tdep
) + ir
.reg
);
7285 case 0x0f71: /* psllw */
7286 case 0x0f72: /* pslld */
7287 case 0x0f73: /* psllq */
7288 if (i386_record_modrm (&ir
))
7290 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.rm
))
7292 record_full_arch_list_add_reg (ir
.regcache
,
7293 I387_MM0_REGNUM (tdep
) + ir
.rm
);
7296 case 0x660f71: /* psllw */
7297 case 0x660f72: /* pslld */
7298 case 0x660f73: /* psllq */
7299 if (i386_record_modrm (&ir
))
7302 if (!i386_xmm_regnum_p (gdbarch
, I387_XMM0_REGNUM (tdep
) + ir
.rm
))
7304 record_full_arch_list_add_reg (ir
.regcache
,
7305 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
7308 case 0x0f7e: /* movd */
7309 case 0x660f7e: /* movd */
7310 if (i386_record_modrm (&ir
))
7313 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
7320 if (i386_record_lea_modrm (&ir
))
7325 case 0x0f7f: /* movq */
7326 if (i386_record_modrm (&ir
))
7330 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.rm
))
7332 record_full_arch_list_add_reg (ir
.regcache
,
7333 I387_MM0_REGNUM (tdep
) + ir
.rm
);
7338 if (i386_record_lea_modrm (&ir
))
7343 case 0xf30fb8: /* popcnt */
7344 if (i386_record_modrm (&ir
))
7346 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
7347 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7350 case 0x660fd6: /* movq */
7351 if (i386_record_modrm (&ir
))
7356 if (!i386_xmm_regnum_p (gdbarch
,
7357 I387_XMM0_REGNUM (tdep
) + ir
.rm
))
7359 record_full_arch_list_add_reg (ir
.regcache
,
7360 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
7365 if (i386_record_lea_modrm (&ir
))
7370 case 0x660f3817: /* ptest */
7371 case 0x0f2e: /* ucomiss */
7372 case 0x660f2e: /* ucomisd */
7373 case 0x0f2f: /* comiss */
7374 case 0x660f2f: /* comisd */
7375 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7378 case 0x0ff7: /* maskmovq */
7379 regcache_raw_read_unsigned (ir
.regcache
,
7380 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
7382 if (record_full_arch_list_add_mem (addr
, 64))
7386 case 0x660ff7: /* maskmovdqu */
7387 regcache_raw_read_unsigned (ir
.regcache
,
7388 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
7390 if (record_full_arch_list_add_mem (addr
, 128))
7405 /* In the future, maybe still need to deal with need_dasm. */
7406 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM
);
7407 if (record_full_arch_list_add_end ())
7413 printf_unfiltered (_("Process record does not support instruction 0x%02x "
7414 "at address %s.\n"),
7415 (unsigned int) (opcode
),
7416 paddress (gdbarch
, ir
.orig_addr
));
7420 static const int i386_record_regmap
[] =
7422 I386_EAX_REGNUM
, I386_ECX_REGNUM
, I386_EDX_REGNUM
, I386_EBX_REGNUM
,
7423 I386_ESP_REGNUM
, I386_EBP_REGNUM
, I386_ESI_REGNUM
, I386_EDI_REGNUM
,
7424 0, 0, 0, 0, 0, 0, 0, 0,
7425 I386_EIP_REGNUM
, I386_EFLAGS_REGNUM
, I386_CS_REGNUM
, I386_SS_REGNUM
,
7426 I386_DS_REGNUM
, I386_ES_REGNUM
, I386_FS_REGNUM
, I386_GS_REGNUM
7429 /* Check that the given address appears suitable for a fast
7430 tracepoint, which on x86-64 means that we need an instruction of at
7431 least 5 bytes, so that we can overwrite it with a 4-byte-offset
7432 jump and not have to worry about program jumps to an address in the
7433 middle of the tracepoint jump. On x86, it may be possible to use
7434 4-byte jumps with a 2-byte offset to a trampoline located in the
7435 bottom 64 KiB of memory. Returns 1 if OK, and writes a size
7436 of instruction to replace, and 0 if not, plus an explanatory
7440 i386_fast_tracepoint_valid_at (struct gdbarch
*gdbarch
,
7441 CORE_ADDR addr
, int *isize
, char **msg
)
7444 static struct ui_file
*gdb_null
= NULL
;
7446 /* Ask the target for the minimum instruction length supported. */
7447 jumplen
= target_get_min_fast_tracepoint_insn_len ();
7451 /* If the target does not support the get_min_fast_tracepoint_insn_len
7452 operation, assume that fast tracepoints will always be implemented
7453 using 4-byte relative jumps on both x86 and x86-64. */
7456 else if (jumplen
== 0)
7458 /* If the target does support get_min_fast_tracepoint_insn_len but
7459 returns zero, then the IPA has not loaded yet. In this case,
7460 we optimistically assume that truncated 2-byte relative jumps
7461 will be available on x86, and compensate later if this assumption
7462 turns out to be incorrect. On x86-64 architectures, 4-byte relative
7463 jumps will always be used. */
7464 jumplen
= (register_size (gdbarch
, 0) == 8) ? 5 : 4;
7467 /* Dummy file descriptor for the disassembler. */
7469 gdb_null
= ui_file_new ();
7471 /* Check for fit. */
7472 len
= gdb_print_insn (gdbarch
, addr
, gdb_null
, NULL
);
7478 /* Return a bit of target-specific detail to add to the caller's
7479 generic failure message. */
7481 *msg
= xstrprintf (_("; instruction is only %d bytes long, "
7482 "need at least %d bytes for the jump"),
7495 i386_validate_tdesc_p (struct gdbarch_tdep
*tdep
,
7496 struct tdesc_arch_data
*tdesc_data
)
7498 const struct target_desc
*tdesc
= tdep
->tdesc
;
7499 const struct tdesc_feature
*feature_core
;
7500 const struct tdesc_feature
*feature_sse
, *feature_avx
;
7501 int i
, num_regs
, valid_p
;
7503 if (! tdesc_has_registers (tdesc
))
7506 /* Get core registers. */
7507 feature_core
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.core");
7508 if (feature_core
== NULL
)
7511 /* Get SSE registers. */
7512 feature_sse
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.sse");
7514 /* Try AVX registers. */
7515 feature_avx
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx");
7519 /* The XCR0 bits. */
7522 /* AVX register description requires SSE register description. */
7526 tdep
->xcr0
= I386_XSTATE_AVX_MASK
;
7528 /* It may have been set by OSABI initialization function. */
7529 if (tdep
->num_ymm_regs
== 0)
7531 tdep
->ymmh_register_names
= i386_ymmh_names
;
7532 tdep
->num_ymm_regs
= 8;
7533 tdep
->ymm0h_regnum
= I386_YMM0H_REGNUM
;
7536 for (i
= 0; i
< tdep
->num_ymm_regs
; i
++)
7537 valid_p
&= tdesc_numbered_register (feature_avx
, tdesc_data
,
7538 tdep
->ymm0h_regnum
+ i
,
7539 tdep
->ymmh_register_names
[i
]);
7541 else if (feature_sse
)
7542 tdep
->xcr0
= I386_XSTATE_SSE_MASK
;
7545 tdep
->xcr0
= I386_XSTATE_X87_MASK
;
7546 tdep
->num_xmm_regs
= 0;
7549 num_regs
= tdep
->num_core_regs
;
7550 for (i
= 0; i
< num_regs
; i
++)
7551 valid_p
&= tdesc_numbered_register (feature_core
, tdesc_data
, i
,
7552 tdep
->register_names
[i
]);
7556 /* Need to include %mxcsr, so add one. */
7557 num_regs
+= tdep
->num_xmm_regs
+ 1;
7558 for (; i
< num_regs
; i
++)
7559 valid_p
&= tdesc_numbered_register (feature_sse
, tdesc_data
, i
,
7560 tdep
->register_names
[i
]);
7567 static struct gdbarch
*
7568 i386_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
7570 struct gdbarch_tdep
*tdep
;
7571 struct gdbarch
*gdbarch
;
7572 struct tdesc_arch_data
*tdesc_data
;
7573 const struct target_desc
*tdesc
;
7577 /* If there is already a candidate, use it. */
7578 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
7580 return arches
->gdbarch
;
7582 /* Allocate space for the new architecture. */
7583 tdep
= XCALLOC (1, struct gdbarch_tdep
);
7584 gdbarch
= gdbarch_alloc (&info
, tdep
);
7586 /* General-purpose registers. */
7587 tdep
->gregset
= NULL
;
7588 tdep
->gregset_reg_offset
= NULL
;
7589 tdep
->gregset_num_regs
= I386_NUM_GREGS
;
7590 tdep
->sizeof_gregset
= 0;
7592 /* Floating-point registers. */
7593 tdep
->fpregset
= NULL
;
7594 tdep
->sizeof_fpregset
= I387_SIZEOF_FSAVE
;
7596 tdep
->xstateregset
= NULL
;
7598 /* The default settings include the FPU registers, the MMX registers
7599 and the SSE registers. This can be overridden for a specific ABI
7600 by adjusting the members `st0_regnum', `mm0_regnum' and
7601 `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers
7602 will show up in the output of "info all-registers". */
7604 tdep
->st0_regnum
= I386_ST0_REGNUM
;
7606 /* I386_NUM_XREGS includes %mxcsr, so substract one. */
7607 tdep
->num_xmm_regs
= I386_NUM_XREGS
- 1;
7609 tdep
->jb_pc_offset
= -1;
7610 tdep
->struct_return
= pcc_struct_return
;
7611 tdep
->sigtramp_start
= 0;
7612 tdep
->sigtramp_end
= 0;
7613 tdep
->sigtramp_p
= i386_sigtramp_p
;
7614 tdep
->sigcontext_addr
= NULL
;
7615 tdep
->sc_reg_offset
= NULL
;
7616 tdep
->sc_pc_offset
= -1;
7617 tdep
->sc_sp_offset
= -1;
7619 tdep
->xsave_xcr0_offset
= -1;
7621 tdep
->record_regmap
= i386_record_regmap
;
7623 set_gdbarch_long_long_align_bit (gdbarch
, 32);
7625 /* The format used for `long double' on almost all i386 targets is
7626 the i387 extended floating-point format. In fact, of all targets
7627 in the GCC 2.95 tree, only OSF/1 does it different, and insists
7628 on having a `long double' that's not `long' at all. */
7629 set_gdbarch_long_double_format (gdbarch
, floatformats_i387_ext
);
7631 /* Although the i387 extended floating-point has only 80 significant
7632 bits, a `long double' actually takes up 96, probably to enforce
7634 set_gdbarch_long_double_bit (gdbarch
, 96);
7636 /* Register numbers of various important registers. */
7637 set_gdbarch_sp_regnum (gdbarch
, I386_ESP_REGNUM
); /* %esp */
7638 set_gdbarch_pc_regnum (gdbarch
, I386_EIP_REGNUM
); /* %eip */
7639 set_gdbarch_ps_regnum (gdbarch
, I386_EFLAGS_REGNUM
); /* %eflags */
7640 set_gdbarch_fp0_regnum (gdbarch
, I386_ST0_REGNUM
); /* %st(0) */
7642 /* NOTE: kettenis/20040418: GCC does have two possible register
7643 numbering schemes on the i386: dbx and SVR4. These schemes
7644 differ in how they number %ebp, %esp, %eflags, and the
7645 floating-point registers, and are implemented by the arrays
7646 dbx_register_map[] and svr4_dbx_register_map in
7647 gcc/config/i386.c. GCC also defines a third numbering scheme in
7648 gcc/config/i386.c, which it designates as the "default" register
7649 map used in 64bit mode. This last register numbering scheme is
7650 implemented in dbx64_register_map, and is used for AMD64; see
7653 Currently, each GCC i386 target always uses the same register
7654 numbering scheme across all its supported debugging formats
7655 i.e. SDB (COFF), stabs and DWARF 2. This is because
7656 gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the
7657 DBX_REGISTER_NUMBER macro which is defined by each target's
7658 respective config header in a manner independent of the requested
7659 output debugging format.
7661 This does not match the arrangement below, which presumes that
7662 the SDB and stabs numbering schemes differ from the DWARF and
7663 DWARF 2 ones. The reason for this arrangement is that it is
7664 likely to get the numbering scheme for the target's
7665 default/native debug format right. For targets where GCC is the
7666 native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for
7667 targets where the native toolchain uses a different numbering
7668 scheme for a particular debug format (stabs-in-ELF on Solaris)
7669 the defaults below will have to be overridden, like
7670 i386_elf_init_abi() does. */
7672 /* Use the dbx register numbering scheme for stabs and COFF. */
7673 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
7674 set_gdbarch_sdb_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
7676 /* Use the SVR4 register numbering scheme for DWARF 2. */
7677 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
7679 /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to
7680 be in use on any of the supported i386 targets. */
7682 set_gdbarch_print_float_info (gdbarch
, i387_print_float_info
);
7684 set_gdbarch_get_longjmp_target (gdbarch
, i386_get_longjmp_target
);
7686 /* Call dummy code. */
7687 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
7688 set_gdbarch_push_dummy_code (gdbarch
, i386_push_dummy_code
);
7689 set_gdbarch_push_dummy_call (gdbarch
, i386_push_dummy_call
);
7690 set_gdbarch_frame_align (gdbarch
, i386_frame_align
);
7692 set_gdbarch_convert_register_p (gdbarch
, i386_convert_register_p
);
7693 set_gdbarch_register_to_value (gdbarch
, i386_register_to_value
);
7694 set_gdbarch_value_to_register (gdbarch
, i386_value_to_register
);
7696 set_gdbarch_return_value (gdbarch
, i386_return_value
);
7698 set_gdbarch_skip_prologue (gdbarch
, i386_skip_prologue
);
7700 /* Stack grows downward. */
7701 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
7703 set_gdbarch_breakpoint_from_pc (gdbarch
, i386_breakpoint_from_pc
);
7704 set_gdbarch_decr_pc_after_break (gdbarch
, 1);
7705 set_gdbarch_max_insn_length (gdbarch
, I386_MAX_INSN_LEN
);
7707 set_gdbarch_frame_args_skip (gdbarch
, 8);
7709 set_gdbarch_print_insn (gdbarch
, i386_print_insn
);
7711 set_gdbarch_dummy_id (gdbarch
, i386_dummy_id
);
7713 set_gdbarch_unwind_pc (gdbarch
, i386_unwind_pc
);
7715 /* Add the i386 register groups. */
7716 i386_add_reggroups (gdbarch
);
7717 tdep
->register_reggroup_p
= i386_register_reggroup_p
;
7719 /* Helper for function argument information. */
7720 set_gdbarch_fetch_pointer_argument (gdbarch
, i386_fetch_pointer_argument
);
7722 /* Hook the function epilogue frame unwinder. This unwinder is
7723 appended to the list first, so that it supercedes the DWARF
7724 unwinder in function epilogues (where the DWARF unwinder
7725 currently fails). */
7726 frame_unwind_append_unwinder (gdbarch
, &i386_epilogue_frame_unwind
);
7728 /* Hook in the DWARF CFI frame unwinder. This unwinder is appended
7729 to the list before the prologue-based unwinders, so that DWARF
7730 CFI info will be used if it is available. */
7731 dwarf2_append_unwinders (gdbarch
);
7733 frame_base_set_default (gdbarch
, &i386_frame_base
);
7735 /* Pseudo registers may be changed by amd64_init_abi. */
7736 set_gdbarch_pseudo_register_read_value (gdbarch
,
7737 i386_pseudo_register_read_value
);
7738 set_gdbarch_pseudo_register_write (gdbarch
, i386_pseudo_register_write
);
7740 set_tdesc_pseudo_register_type (gdbarch
, i386_pseudo_register_type
);
7741 set_tdesc_pseudo_register_name (gdbarch
, i386_pseudo_register_name
);
7743 /* Override the normal target description method to make the AVX
7744 upper halves anonymous. */
7745 set_gdbarch_register_name (gdbarch
, i386_register_name
);
7747 /* Even though the default ABI only includes general-purpose registers,
7748 floating-point registers and the SSE registers, we have to leave a
7749 gap for the upper AVX registers. */
7750 set_gdbarch_num_regs (gdbarch
, I386_AVX_NUM_REGS
);
7752 /* Get the x86 target description from INFO. */
7753 tdesc
= info
.target_desc
;
7754 if (! tdesc_has_registers (tdesc
))
7756 tdep
->tdesc
= tdesc
;
7758 tdep
->num_core_regs
= I386_NUM_GREGS
+ I387_NUM_REGS
;
7759 tdep
->register_names
= i386_register_names
;
7761 /* No upper YMM registers. */
7762 tdep
->ymmh_register_names
= NULL
;
7763 tdep
->ymm0h_regnum
= -1;
7765 tdep
->num_byte_regs
= 8;
7766 tdep
->num_word_regs
= 8;
7767 tdep
->num_dword_regs
= 0;
7768 tdep
->num_mmx_regs
= 8;
7769 tdep
->num_ymm_regs
= 0;
7771 tdesc_data
= tdesc_data_alloc ();
7773 set_gdbarch_relocate_instruction (gdbarch
, i386_relocate_instruction
);
7775 set_gdbarch_gen_return_address (gdbarch
, i386_gen_return_address
);
7777 /* Hook in ABI-specific overrides, if they have been registered. */
7778 info
.tdep_info
= (void *) tdesc_data
;
7779 gdbarch_init_osabi (info
, gdbarch
);
7781 if (!i386_validate_tdesc_p (tdep
, tdesc_data
))
7783 tdesc_data_cleanup (tdesc_data
);
7785 gdbarch_free (gdbarch
);
7789 /* Wire in pseudo registers. Number of pseudo registers may be
7791 set_gdbarch_num_pseudo_regs (gdbarch
, (tdep
->num_byte_regs
7792 + tdep
->num_word_regs
7793 + tdep
->num_dword_regs
7794 + tdep
->num_mmx_regs
7795 + tdep
->num_ymm_regs
));
7797 /* Target description may be changed. */
7798 tdesc
= tdep
->tdesc
;
7800 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
7802 /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */
7803 set_gdbarch_register_reggroup_p (gdbarch
, tdep
->register_reggroup_p
);
7805 /* Make %al the first pseudo-register. */
7806 tdep
->al_regnum
= gdbarch_num_regs (gdbarch
);
7807 tdep
->ax_regnum
= tdep
->al_regnum
+ tdep
->num_byte_regs
;
7809 ymm0_regnum
= tdep
->ax_regnum
+ tdep
->num_word_regs
;
7810 if (tdep
->num_dword_regs
)
7812 /* Support dword pseudo-register if it hasn't been disabled. */
7813 tdep
->eax_regnum
= ymm0_regnum
;
7814 ymm0_regnum
+= tdep
->num_dword_regs
;
7817 tdep
->eax_regnum
= -1;
7819 mm0_regnum
= ymm0_regnum
;
7820 if (tdep
->num_ymm_regs
)
7822 /* Support YMM pseudo-register if it is available. */
7823 tdep
->ymm0_regnum
= ymm0_regnum
;
7824 mm0_regnum
+= tdep
->num_ymm_regs
;
7827 tdep
->ymm0_regnum
= -1;
7829 if (tdep
->num_mmx_regs
!= 0)
7831 /* Support MMX pseudo-register if MMX hasn't been disabled. */
7832 tdep
->mm0_regnum
= mm0_regnum
;
7835 tdep
->mm0_regnum
= -1;
7837 /* Hook in the legacy prologue-based unwinders last (fallback). */
7838 frame_unwind_append_unwinder (gdbarch
, &i386_stack_tramp_frame_unwind
);
7839 frame_unwind_append_unwinder (gdbarch
, &i386_sigtramp_frame_unwind
);
7840 frame_unwind_append_unwinder (gdbarch
, &i386_frame_unwind
);
7842 /* If we have a register mapping, enable the generic core file
7843 support, unless it has already been enabled. */
7844 if (tdep
->gregset_reg_offset
7845 && !gdbarch_regset_from_core_section_p (gdbarch
))
7846 set_gdbarch_regset_from_core_section (gdbarch
,
7847 i386_regset_from_core_section
);
7849 set_gdbarch_skip_permanent_breakpoint (gdbarch
,
7850 i386_skip_permanent_breakpoint
);
7852 set_gdbarch_fast_tracepoint_valid_at (gdbarch
,
7853 i386_fast_tracepoint_valid_at
);
7858 static enum gdb_osabi
7859 i386_coff_osabi_sniffer (bfd
*abfd
)
7861 if (strcmp (bfd_get_target (abfd
), "coff-go32-exe") == 0
7862 || strcmp (bfd_get_target (abfd
), "coff-go32") == 0)
7863 return GDB_OSABI_GO32
;
7865 return GDB_OSABI_UNKNOWN
;
7869 /* Provide a prototype to silence -Wmissing-prototypes. */
7870 void _initialize_i386_tdep (void);
7873 _initialize_i386_tdep (void)
7875 register_gdbarch_init (bfd_arch_i386
, i386_gdbarch_init
);
7877 /* Add the variable that controls the disassembly flavor. */
7878 add_setshow_enum_cmd ("disassembly-flavor", no_class
, valid_flavors
,
7879 &disassembly_flavor
, _("\
7880 Set the disassembly flavor."), _("\
7881 Show the disassembly flavor."), _("\
7882 The valid values are \"att\" and \"intel\", and the default value is \"att\"."),
7884 NULL
, /* FIXME: i18n: */
7885 &setlist
, &showlist
);
7887 /* Add the variable that controls the convention for returning
7889 add_setshow_enum_cmd ("struct-convention", no_class
, valid_conventions
,
7890 &struct_convention
, _("\
7891 Set the convention for returning small structs."), _("\
7892 Show the convention for returning small structs."), _("\
7893 Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\
7896 NULL
, /* FIXME: i18n: */
7897 &setlist
, &showlist
);
7899 gdbarch_register_osabi_sniffer (bfd_arch_i386
, bfd_target_coff_flavour
,
7900 i386_coff_osabi_sniffer
);
7902 gdbarch_register_osabi (bfd_arch_i386
, 0, GDB_OSABI_SVR4
,
7903 i386_svr4_init_abi
);
7904 gdbarch_register_osabi (bfd_arch_i386
, 0, GDB_OSABI_GO32
,
7905 i386_go32_init_abi
);
7907 /* Initialize the i386-specific register groups. */
7908 i386_init_reggroups ();
7910 /* Initialize the standard target descriptions. */
7911 initialize_tdesc_i386 ();
7912 initialize_tdesc_i386_mmx ();
7913 initialize_tdesc_i386_avx ();
7915 /* Tell remote stub that we support XML target description. */
7916 register_remote_support_xml ("i386");