1 /* Intel 386 target-dependent stuff.
3 Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009,
5 2010 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "opcode/i386.h"
24 #include "arch-utils.h"
26 #include "dummy-frame.h"
27 #include "dwarf2-frame.h"
30 #include "frame-base.h"
31 #include "frame-unwind.h"
39 #include "reggroups.h"
49 #include "gdb_assert.h"
50 #include "gdb_string.h"
52 #include "i386-tdep.h"
53 #include "i387-tdep.h"
58 #include "features/i386/i386.c"
62 static const char *i386_register_names
[] =
64 "eax", "ecx", "edx", "ebx",
65 "esp", "ebp", "esi", "edi",
66 "eip", "eflags", "cs", "ss",
67 "ds", "es", "fs", "gs",
68 "st0", "st1", "st2", "st3",
69 "st4", "st5", "st6", "st7",
70 "fctrl", "fstat", "ftag", "fiseg",
71 "fioff", "foseg", "fooff", "fop",
72 "xmm0", "xmm1", "xmm2", "xmm3",
73 "xmm4", "xmm5", "xmm6", "xmm7",
77 /* Register names for MMX pseudo-registers. */
79 static const char *i386_mmx_names
[] =
81 "mm0", "mm1", "mm2", "mm3",
82 "mm4", "mm5", "mm6", "mm7"
85 /* Register names for byte pseudo-registers. */
87 static const char *i386_byte_names
[] =
89 "al", "cl", "dl", "bl",
90 "ah", "ch", "dh", "bh"
93 /* Register names for word pseudo-registers. */
95 static const char *i386_word_names
[] =
97 "ax", "cx", "dx", "bx",
104 i386_mmx_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
106 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
107 int mm0_regnum
= tdep
->mm0_regnum
;
112 regnum
-= mm0_regnum
;
113 return regnum
>= 0 && regnum
< tdep
->num_mmx_regs
;
119 i386_byte_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
121 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
123 regnum
-= tdep
->al_regnum
;
124 return regnum
>= 0 && regnum
< tdep
->num_byte_regs
;
130 i386_word_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
132 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
134 regnum
-= tdep
->ax_regnum
;
135 return regnum
>= 0 && regnum
< tdep
->num_word_regs
;
138 /* Dword register? */
141 i386_dword_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
143 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
144 int eax_regnum
= tdep
->eax_regnum
;
149 regnum
-= eax_regnum
;
150 return regnum
>= 0 && regnum
< tdep
->num_dword_regs
;
156 i386_sse_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
158 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
160 if (I387_NUM_XMM_REGS (tdep
) == 0)
163 return (I387_XMM0_REGNUM (tdep
) <= regnum
164 && regnum
< I387_MXCSR_REGNUM (tdep
));
168 i386_mxcsr_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
170 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
172 if (I387_NUM_XMM_REGS (tdep
) == 0)
175 return (regnum
== I387_MXCSR_REGNUM (tdep
));
181 i386_fp_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
183 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
185 if (I387_ST0_REGNUM (tdep
) < 0)
188 return (I387_ST0_REGNUM (tdep
) <= regnum
189 && regnum
< I387_FCTRL_REGNUM (tdep
));
193 i386_fpc_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
195 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
197 if (I387_ST0_REGNUM (tdep
) < 0)
200 return (I387_FCTRL_REGNUM (tdep
) <= regnum
201 && regnum
< I387_XMM0_REGNUM (tdep
));
204 /* Return the name of register REGNUM. */
207 i386_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
209 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
210 if (i386_mmx_regnum_p (gdbarch
, regnum
))
211 return i386_mmx_names
[regnum
- I387_MM0_REGNUM (tdep
)];
212 else if (i386_byte_regnum_p (gdbarch
, regnum
))
213 return i386_byte_names
[regnum
- tdep
->al_regnum
];
214 else if (i386_word_regnum_p (gdbarch
, regnum
))
215 return i386_word_names
[regnum
- tdep
->ax_regnum
];
217 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
220 /* Convert a dbx register number REG to the appropriate register
221 number used by GDB. */
224 i386_dbx_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
226 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
228 /* This implements what GCC calls the "default" register map
229 (dbx_register_map[]). */
231 if (reg
>= 0 && reg
<= 7)
233 /* General-purpose registers. The debug info calls %ebp
234 register 4, and %esp register 5. */
241 else if (reg
>= 12 && reg
<= 19)
243 /* Floating-point registers. */
244 return reg
- 12 + I387_ST0_REGNUM (tdep
);
246 else if (reg
>= 21 && reg
<= 28)
249 return reg
- 21 + I387_XMM0_REGNUM (tdep
);
251 else if (reg
>= 29 && reg
<= 36)
254 return reg
- 29 + I387_MM0_REGNUM (tdep
);
257 /* This will hopefully provoke a warning. */
258 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
261 /* Convert SVR4 register number REG to the appropriate register number
265 i386_svr4_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
267 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
269 /* This implements the GCC register map that tries to be compatible
270 with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */
272 /* The SVR4 register numbering includes %eip and %eflags, and
273 numbers the floating point registers differently. */
274 if (reg
>= 0 && reg
<= 9)
276 /* General-purpose registers. */
279 else if (reg
>= 11 && reg
<= 18)
281 /* Floating-point registers. */
282 return reg
- 11 + I387_ST0_REGNUM (tdep
);
284 else if (reg
>= 21 && reg
<= 36)
286 /* The SSE and MMX registers have the same numbers as with dbx. */
287 return i386_dbx_reg_to_regnum (gdbarch
, reg
);
292 case 37: return I387_FCTRL_REGNUM (tdep
);
293 case 38: return I387_FSTAT_REGNUM (tdep
);
294 case 39: return I387_MXCSR_REGNUM (tdep
);
295 case 40: return I386_ES_REGNUM
;
296 case 41: return I386_CS_REGNUM
;
297 case 42: return I386_SS_REGNUM
;
298 case 43: return I386_DS_REGNUM
;
299 case 44: return I386_FS_REGNUM
;
300 case 45: return I386_GS_REGNUM
;
303 /* This will hopefully provoke a warning. */
304 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
309 /* This is the variable that is set with "set disassembly-flavor", and
310 its legitimate values. */
311 static const char att_flavor
[] = "att";
312 static const char intel_flavor
[] = "intel";
313 static const char *valid_flavors
[] =
319 static const char *disassembly_flavor
= att_flavor
;
322 /* Use the program counter to determine the contents and size of a
323 breakpoint instruction. Return a pointer to a string of bytes that
324 encode a breakpoint instruction, store the length of the string in
325 *LEN and optionally adjust *PC to point to the correct memory
326 location for inserting the breakpoint.
328 On the i386 we have a single breakpoint that fits in a single byte
329 and can be inserted anywhere.
331 This function is 64-bit safe. */
333 static const gdb_byte
*
334 i386_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pc
, int *len
)
336 static gdb_byte break_insn
[] = { 0xcc }; /* int 3 */
338 *len
= sizeof (break_insn
);
342 /* Displaced instruction handling. */
344 /* Skip the legacy instruction prefixes in INSN.
345 Not all prefixes are valid for any particular insn
346 but we needn't care, the insn will fault if it's invalid.
347 The result is a pointer to the first opcode byte,
348 or NULL if we run off the end of the buffer. */
351 i386_skip_prefixes (gdb_byte
*insn
, size_t max_len
)
353 gdb_byte
*end
= insn
+ max_len
;
359 case DATA_PREFIX_OPCODE
:
360 case ADDR_PREFIX_OPCODE
:
361 case CS_PREFIX_OPCODE
:
362 case DS_PREFIX_OPCODE
:
363 case ES_PREFIX_OPCODE
:
364 case FS_PREFIX_OPCODE
:
365 case GS_PREFIX_OPCODE
:
366 case SS_PREFIX_OPCODE
:
367 case LOCK_PREFIX_OPCODE
:
368 case REPE_PREFIX_OPCODE
:
369 case REPNE_PREFIX_OPCODE
:
381 i386_absolute_jmp_p (const gdb_byte
*insn
)
383 /* jmp far (absolute address in operand) */
389 /* jump near, absolute indirect (/4) */
390 if ((insn
[1] & 0x38) == 0x20)
393 /* jump far, absolute indirect (/5) */
394 if ((insn
[1] & 0x38) == 0x28)
402 i386_absolute_call_p (const gdb_byte
*insn
)
404 /* call far, absolute */
410 /* Call near, absolute indirect (/2) */
411 if ((insn
[1] & 0x38) == 0x10)
414 /* Call far, absolute indirect (/3) */
415 if ((insn
[1] & 0x38) == 0x18)
423 i386_ret_p (const gdb_byte
*insn
)
427 case 0xc2: /* ret near, pop N bytes */
428 case 0xc3: /* ret near */
429 case 0xca: /* ret far, pop N bytes */
430 case 0xcb: /* ret far */
431 case 0xcf: /* iret */
440 i386_call_p (const gdb_byte
*insn
)
442 if (i386_absolute_call_p (insn
))
445 /* call near, relative */
452 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
453 length in bytes. Otherwise, return zero. */
456 i386_syscall_p (const gdb_byte
*insn
, ULONGEST
*lengthp
)
467 /* Fix up the state of registers and memory after having single-stepped
468 a displaced instruction. */
471 i386_displaced_step_fixup (struct gdbarch
*gdbarch
,
472 struct displaced_step_closure
*closure
,
473 CORE_ADDR from
, CORE_ADDR to
,
474 struct regcache
*regs
)
476 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
478 /* The offset we applied to the instruction's address.
479 This could well be negative (when viewed as a signed 32-bit
480 value), but ULONGEST won't reflect that, so take care when
482 ULONGEST insn_offset
= to
- from
;
484 /* Since we use simple_displaced_step_copy_insn, our closure is a
485 copy of the instruction. */
486 gdb_byte
*insn
= (gdb_byte
*) closure
;
487 /* The start of the insn, needed in case we see some prefixes. */
488 gdb_byte
*insn_start
= insn
;
491 fprintf_unfiltered (gdb_stdlog
,
492 "displaced: fixup (%s, %s), "
493 "insn = 0x%02x 0x%02x ...\n",
494 paddress (gdbarch
, from
), paddress (gdbarch
, to
),
497 /* The list of issues to contend with here is taken from
498 resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20.
499 Yay for Free Software! */
501 /* Relocate the %eip, if necessary. */
503 /* The instruction recognizers we use assume any leading prefixes
504 have been skipped. */
506 /* This is the size of the buffer in closure. */
507 size_t max_insn_len
= gdbarch_max_insn_length (gdbarch
);
508 gdb_byte
*opcode
= i386_skip_prefixes (insn
, max_insn_len
);
509 /* If there are too many prefixes, just ignore the insn.
510 It will fault when run. */
515 /* Except in the case of absolute or indirect jump or call
516 instructions, or a return instruction, the new eip is relative to
517 the displaced instruction; make it relative. Well, signal
518 handler returns don't need relocation either, but we use the
519 value of %eip to recognize those; see below. */
520 if (! i386_absolute_jmp_p (insn
)
521 && ! i386_absolute_call_p (insn
)
522 && ! i386_ret_p (insn
))
527 regcache_cooked_read_unsigned (regs
, I386_EIP_REGNUM
, &orig_eip
);
529 /* A signal trampoline system call changes the %eip, resuming
530 execution of the main program after the signal handler has
531 returned. That makes them like 'return' instructions; we
532 shouldn't relocate %eip.
534 But most system calls don't, and we do need to relocate %eip.
536 Our heuristic for distinguishing these cases: if stepping
537 over the system call instruction left control directly after
538 the instruction, the we relocate --- control almost certainly
539 doesn't belong in the displaced copy. Otherwise, we assume
540 the instruction has put control where it belongs, and leave
541 it unrelocated. Goodness help us if there are PC-relative
543 if (i386_syscall_p (insn
, &insn_len
)
544 && orig_eip
!= to
+ (insn
- insn_start
) + insn_len
)
547 fprintf_unfiltered (gdb_stdlog
,
548 "displaced: syscall changed %%eip; "
553 ULONGEST eip
= (orig_eip
- insn_offset
) & 0xffffffffUL
;
555 /* If we just stepped over a breakpoint insn, we don't backup
556 the pc on purpose; this is to match behaviour without
559 regcache_cooked_write_unsigned (regs
, I386_EIP_REGNUM
, eip
);
562 fprintf_unfiltered (gdb_stdlog
,
564 "relocated %%eip from %s to %s\n",
565 paddress (gdbarch
, orig_eip
),
566 paddress (gdbarch
, eip
));
570 /* If the instruction was PUSHFL, then the TF bit will be set in the
571 pushed value, and should be cleared. We'll leave this for later,
572 since GDB already messes up the TF flag when stepping over a
575 /* If the instruction was a call, the return address now atop the
576 stack is the address following the copied instruction. We need
577 to make it the address following the original instruction. */
578 if (i386_call_p (insn
))
582 const ULONGEST retaddr_len
= 4;
584 regcache_cooked_read_unsigned (regs
, I386_ESP_REGNUM
, &esp
);
585 retaddr
= read_memory_unsigned_integer (esp
, retaddr_len
, byte_order
);
586 retaddr
= (retaddr
- insn_offset
) & 0xffffffffUL
;
587 write_memory_unsigned_integer (esp
, retaddr_len
, byte_order
, retaddr
);
590 fprintf_unfiltered (gdb_stdlog
,
591 "displaced: relocated return addr at %s to %s\n",
592 paddress (gdbarch
, esp
),
593 paddress (gdbarch
, retaddr
));
597 #ifdef I386_REGNO_TO_SYMMETRY
598 #error "The Sequent Symmetry is no longer supported."
601 /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi
602 and %esp "belong" to the calling function. Therefore these
603 registers should be saved if they're going to be modified. */
605 /* The maximum number of saved registers. This should include all
606 registers mentioned above, and %eip. */
607 #define I386_NUM_SAVED_REGS I386_NUM_GREGS
609 struct i386_frame_cache
616 /* Saved registers. */
617 CORE_ADDR saved_regs
[I386_NUM_SAVED_REGS
];
622 /* Stack space reserved for local variables. */
626 /* Allocate and initialize a frame cache. */
628 static struct i386_frame_cache
*
629 i386_alloc_frame_cache (void)
631 struct i386_frame_cache
*cache
;
634 cache
= FRAME_OBSTACK_ZALLOC (struct i386_frame_cache
);
638 cache
->sp_offset
= -4;
641 /* Saved registers. We initialize these to -1 since zero is a valid
642 offset (that's where %ebp is supposed to be stored). */
643 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
644 cache
->saved_regs
[i
] = -1;
646 cache
->saved_sp_reg
= -1;
647 cache
->pc_in_eax
= 0;
649 /* Frameless until proven otherwise. */
655 /* If the instruction at PC is a jump, return the address of its
656 target. Otherwise, return PC. */
659 i386_follow_jump (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
661 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
666 target_read_memory (pc
, &op
, 1);
670 op
= read_memory_unsigned_integer (pc
+ 1, 1, byte_order
);
676 /* Relative jump: if data16 == 0, disp32, else disp16. */
679 delta
= read_memory_integer (pc
+ 2, 2, byte_order
);
681 /* Include the size of the jmp instruction (including the
687 delta
= read_memory_integer (pc
+ 1, 4, byte_order
);
689 /* Include the size of the jmp instruction. */
694 /* Relative jump, disp8 (ignore data16). */
695 delta
= read_memory_integer (pc
+ data16
+ 1, 1, byte_order
);
704 /* Check whether PC points at a prologue for a function returning a
705 structure or union. If so, it updates CACHE and returns the
706 address of the first instruction after the code sequence that
707 removes the "hidden" argument from the stack or CURRENT_PC,
708 whichever is smaller. Otherwise, return PC. */
711 i386_analyze_struct_return (CORE_ADDR pc
, CORE_ADDR current_pc
,
712 struct i386_frame_cache
*cache
)
714 /* Functions that return a structure or union start with:
717 xchgl %eax, (%esp) 0x87 0x04 0x24
718 or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00
720 (the System V compiler puts out the second `xchg' instruction,
721 and the assembler doesn't try to optimize it, so the 'sib' form
722 gets generated). This sequence is used to get the address of the
723 return buffer for a function that returns a structure. */
724 static gdb_byte proto1
[3] = { 0x87, 0x04, 0x24 };
725 static gdb_byte proto2
[4] = { 0x87, 0x44, 0x24, 0x00 };
729 if (current_pc
<= pc
)
732 target_read_memory (pc
, &op
, 1);
734 if (op
!= 0x58) /* popl %eax */
737 target_read_memory (pc
+ 1, buf
, 4);
738 if (memcmp (buf
, proto1
, 3) != 0 && memcmp (buf
, proto2
, 4) != 0)
741 if (current_pc
== pc
)
743 cache
->sp_offset
+= 4;
747 if (current_pc
== pc
+ 1)
749 cache
->pc_in_eax
= 1;
753 if (buf
[1] == proto1
[1])
760 i386_skip_probe (CORE_ADDR pc
)
762 /* A function may start with
776 target_read_memory (pc
, &op
, 1);
778 if (op
== 0x68 || op
== 0x6a)
782 /* Skip past the `pushl' instruction; it has either a one-byte or a
783 four-byte operand, depending on the opcode. */
789 /* Read the following 8 bytes, which should be `call _probe' (6
790 bytes) followed by `addl $4,%esp' (2 bytes). */
791 read_memory (pc
+ delta
, buf
, sizeof (buf
));
792 if (buf
[0] == 0xe8 && buf
[6] == 0xc4 && buf
[7] == 0x4)
793 pc
+= delta
+ sizeof (buf
);
799 /* GCC 4.1 and later, can put code in the prologue to realign the
800 stack pointer. Check whether PC points to such code, and update
801 CACHE accordingly. Return the first instruction after the code
802 sequence or CURRENT_PC, whichever is smaller. If we don't
803 recognize the code, return PC. */
806 i386_analyze_stack_align (CORE_ADDR pc
, CORE_ADDR current_pc
,
807 struct i386_frame_cache
*cache
)
809 /* There are 2 code sequences to re-align stack before the frame
812 1. Use a caller-saved saved register:
818 2. Use a callee-saved saved register:
825 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
827 0x83 0xe4 0xf0 andl $-16, %esp
828 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
833 int offset
, offset_and
;
834 static int regnums
[8] = {
835 I386_EAX_REGNUM
, /* %eax */
836 I386_ECX_REGNUM
, /* %ecx */
837 I386_EDX_REGNUM
, /* %edx */
838 I386_EBX_REGNUM
, /* %ebx */
839 I386_ESP_REGNUM
, /* %esp */
840 I386_EBP_REGNUM
, /* %ebp */
841 I386_ESI_REGNUM
, /* %esi */
842 I386_EDI_REGNUM
/* %edi */
845 if (target_read_memory (pc
, buf
, sizeof buf
))
848 /* Check caller-saved saved register. The first instruction has
849 to be "leal 4(%esp), %reg". */
850 if (buf
[0] == 0x8d && buf
[2] == 0x24 && buf
[3] == 0x4)
852 /* MOD must be binary 10 and R/M must be binary 100. */
853 if ((buf
[1] & 0xc7) != 0x44)
856 /* REG has register number. */
857 reg
= (buf
[1] >> 3) & 7;
862 /* Check callee-saved saved register. The first instruction
863 has to be "pushl %reg". */
864 if ((buf
[0] & 0xf8) != 0x50)
870 /* The next instruction has to be "leal 8(%esp), %reg". */
871 if (buf
[1] != 0x8d || buf
[3] != 0x24 || buf
[4] != 0x8)
874 /* MOD must be binary 10 and R/M must be binary 100. */
875 if ((buf
[2] & 0xc7) != 0x44)
878 /* REG has register number. Registers in pushl and leal have to
880 if (reg
!= ((buf
[2] >> 3) & 7))
886 /* Rigister can't be %esp nor %ebp. */
887 if (reg
== 4 || reg
== 5)
890 /* The next instruction has to be "andl $-XXX, %esp". */
891 if (buf
[offset
+ 1] != 0xe4
892 || (buf
[offset
] != 0x81 && buf
[offset
] != 0x83))
896 offset
+= buf
[offset
] == 0x81 ? 6 : 3;
898 /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is
899 0xfc. REG must be binary 110 and MOD must be binary 01. */
900 if (buf
[offset
] != 0xff
901 || buf
[offset
+ 2] != 0xfc
902 || (buf
[offset
+ 1] & 0xf8) != 0x70)
905 /* R/M has register. Registers in leal and pushl have to be the
907 if (reg
!= (buf
[offset
+ 1] & 7))
910 if (current_pc
> pc
+ offset_and
)
911 cache
->saved_sp_reg
= regnums
[reg
];
913 return min (pc
+ offset
+ 3, current_pc
);
916 /* Maximum instruction length we need to handle. */
917 #define I386_MAX_MATCHED_INSN_LEN 6
919 /* Instruction description. */
923 gdb_byte insn
[I386_MAX_MATCHED_INSN_LEN
];
924 gdb_byte mask
[I386_MAX_MATCHED_INSN_LEN
];
927 /* Search for the instruction at PC in the list SKIP_INSNS. Return
928 the first instruction description that matches. Otherwise, return
931 static struct i386_insn
*
932 i386_match_insn (CORE_ADDR pc
, struct i386_insn
*skip_insns
)
934 struct i386_insn
*insn
;
937 target_read_memory (pc
, &op
, 1);
939 for (insn
= skip_insns
; insn
->len
> 0; insn
++)
941 if ((op
& insn
->mask
[0]) == insn
->insn
[0])
943 gdb_byte buf
[I386_MAX_MATCHED_INSN_LEN
- 1];
944 int insn_matched
= 1;
947 gdb_assert (insn
->len
> 1);
948 gdb_assert (insn
->len
<= I386_MAX_MATCHED_INSN_LEN
);
950 target_read_memory (pc
+ 1, buf
, insn
->len
- 1);
951 for (i
= 1; i
< insn
->len
; i
++)
953 if ((buf
[i
- 1] & insn
->mask
[i
]) != insn
->insn
[i
])
965 /* Some special instructions that might be migrated by GCC into the
966 part of the prologue that sets up the new stack frame. Because the
967 stack frame hasn't been setup yet, no registers have been saved
968 yet, and only the scratch registers %eax, %ecx and %edx can be
971 struct i386_insn i386_frame_setup_skip_insns
[] =
973 /* Check for `movb imm8, r' and `movl imm32, r'.
975 ??? Should we handle 16-bit operand-sizes here? */
977 /* `movb imm8, %al' and `movb imm8, %ah' */
978 /* `movb imm8, %cl' and `movb imm8, %ch' */
979 { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } },
980 /* `movb imm8, %dl' and `movb imm8, %dh' */
981 { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } },
982 /* `movl imm32, %eax' and `movl imm32, %ecx' */
983 { 5, { 0xb8 }, { 0xfe } },
984 /* `movl imm32, %edx' */
985 { 5, { 0xba }, { 0xff } },
987 /* Check for `mov imm32, r32'. Note that there is an alternative
988 encoding for `mov m32, %eax'.
990 ??? Should we handle SIB adressing here?
991 ??? Should we handle 16-bit operand-sizes here? */
993 /* `movl m32, %eax' */
994 { 5, { 0xa1 }, { 0xff } },
995 /* `movl m32, %eax' and `mov; m32, %ecx' */
996 { 6, { 0x89, 0x05 }, {0xff, 0xf7 } },
997 /* `movl m32, %edx' */
998 { 6, { 0x89, 0x15 }, {0xff, 0xff } },
1000 /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'.
1001 Because of the symmetry, there are actually two ways to encode
1002 these instructions; opcode bytes 0x29 and 0x2b for `subl' and
1003 opcode bytes 0x31 and 0x33 for `xorl'. */
1005 /* `subl %eax, %eax' */
1006 { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } },
1007 /* `subl %ecx, %ecx' */
1008 { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } },
1009 /* `subl %edx, %edx' */
1010 { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } },
1011 /* `xorl %eax, %eax' */
1012 { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } },
1013 /* `xorl %ecx, %ecx' */
1014 { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } },
1015 /* `xorl %edx, %edx' */
1016 { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } },
1021 /* Check whether PC points to a no-op instruction. */
1023 i386_skip_noop (CORE_ADDR pc
)
1028 target_read_memory (pc
, &op
, 1);
1033 /* Ignore `nop' instruction. */
1037 target_read_memory (pc
, &op
, 1);
1040 /* Ignore no-op instruction `mov %edi, %edi'.
1041 Microsoft system dlls often start with
1042 a `mov %edi,%edi' instruction.
1043 The 5 bytes before the function start are
1044 filled with `nop' instructions.
1045 This pattern can be used for hot-patching:
1046 The `mov %edi, %edi' instruction can be replaced by a
1047 near jump to the location of the 5 `nop' instructions
1048 which can be replaced by a 32-bit jump to anywhere
1049 in the 32-bit address space. */
1051 else if (op
== 0x8b)
1053 target_read_memory (pc
+ 1, &op
, 1);
1057 target_read_memory (pc
, &op
, 1);
1065 /* Check whether PC points at a code that sets up a new stack frame.
1066 If so, it updates CACHE and returns the address of the first
1067 instruction after the sequence that sets up the frame or LIMIT,
1068 whichever is smaller. If we don't recognize the code, return PC. */
1071 i386_analyze_frame_setup (struct gdbarch
*gdbarch
,
1072 CORE_ADDR pc
, CORE_ADDR limit
,
1073 struct i386_frame_cache
*cache
)
1075 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1076 struct i386_insn
*insn
;
1083 target_read_memory (pc
, &op
, 1);
1085 if (op
== 0x55) /* pushl %ebp */
1087 /* Take into account that we've executed the `pushl %ebp' that
1088 starts this instruction sequence. */
1089 cache
->saved_regs
[I386_EBP_REGNUM
] = 0;
1090 cache
->sp_offset
+= 4;
1093 /* If that's all, return now. */
1097 /* Check for some special instructions that might be migrated by
1098 GCC into the prologue and skip them. At this point in the
1099 prologue, code should only touch the scratch registers %eax,
1100 %ecx and %edx, so while the number of posibilities is sheer,
1103 Make sure we only skip these instructions if we later see the
1104 `movl %esp, %ebp' that actually sets up the frame. */
1105 while (pc
+ skip
< limit
)
1107 insn
= i386_match_insn (pc
+ skip
, i386_frame_setup_skip_insns
);
1114 /* If that's all, return now. */
1115 if (limit
<= pc
+ skip
)
1118 target_read_memory (pc
+ skip
, &op
, 1);
1120 /* Check for `movl %esp, %ebp' -- can be written in two ways. */
1124 if (read_memory_unsigned_integer (pc
+ skip
+ 1, 1, byte_order
)
1129 if (read_memory_unsigned_integer (pc
+ skip
+ 1, 1, byte_order
)
1137 /* OK, we actually have a frame. We just don't know how large
1138 it is yet. Set its size to zero. We'll adjust it if
1139 necessary. We also now commit to skipping the special
1140 instructions mentioned before. */
1144 /* If that's all, return now. */
1148 /* Check for stack adjustment
1152 NOTE: You can't subtract a 16-bit immediate from a 32-bit
1153 reg, so we don't have to worry about a data16 prefix. */
1154 target_read_memory (pc
, &op
, 1);
1157 /* `subl' with 8-bit immediate. */
1158 if (read_memory_unsigned_integer (pc
+ 1, 1, byte_order
) != 0xec)
1159 /* Some instruction starting with 0x83 other than `subl'. */
1162 /* `subl' with signed 8-bit immediate (though it wouldn't
1163 make sense to be negative). */
1164 cache
->locals
= read_memory_integer (pc
+ 2, 1, byte_order
);
1167 else if (op
== 0x81)
1169 /* Maybe it is `subl' with a 32-bit immediate. */
1170 if (read_memory_unsigned_integer (pc
+ 1, 1, byte_order
) != 0xec)
1171 /* Some instruction starting with 0x81 other than `subl'. */
1174 /* It is `subl' with a 32-bit immediate. */
1175 cache
->locals
= read_memory_integer (pc
+ 2, 4, byte_order
);
1180 /* Some instruction other than `subl'. */
1184 else if (op
== 0xc8) /* enter */
1186 cache
->locals
= read_memory_unsigned_integer (pc
+ 1, 2, byte_order
);
1193 /* Check whether PC points at code that saves registers on the stack.
1194 If so, it updates CACHE and returns the address of the first
1195 instruction after the register saves or CURRENT_PC, whichever is
1196 smaller. Otherwise, return PC. */
1199 i386_analyze_register_saves (CORE_ADDR pc
, CORE_ADDR current_pc
,
1200 struct i386_frame_cache
*cache
)
1202 CORE_ADDR offset
= 0;
1206 if (cache
->locals
> 0)
1207 offset
-= cache
->locals
;
1208 for (i
= 0; i
< 8 && pc
< current_pc
; i
++)
1210 target_read_memory (pc
, &op
, 1);
1211 if (op
< 0x50 || op
> 0x57)
1215 cache
->saved_regs
[op
- 0x50] = offset
;
1216 cache
->sp_offset
+= 4;
1223 /* Do a full analysis of the prologue at PC and update CACHE
1224 accordingly. Bail out early if CURRENT_PC is reached. Return the
1225 address where the analysis stopped.
1227 We handle these cases:
1229 The startup sequence can be at the start of the function, or the
1230 function can start with a branch to startup code at the end.
1232 %ebp can be set up with either the 'enter' instruction, or "pushl
1233 %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was
1234 once used in the System V compiler).
1236 Local space is allocated just below the saved %ebp by either the
1237 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a
1238 16-bit unsigned argument for space to allocate, and the 'addl'
1239 instruction could have either a signed byte, or 32-bit immediate.
1241 Next, the registers used by this function are pushed. With the
1242 System V compiler they will always be in the order: %edi, %esi,
1243 %ebx (and sometimes a harmless bug causes it to also save but not
1244 restore %eax); however, the code below is willing to see the pushes
1245 in any order, and will handle up to 8 of them.
1247 If the setup sequence is at the end of the function, then the next
1248 instruction will be a branch back to the start. */
1251 i386_analyze_prologue (struct gdbarch
*gdbarch
,
1252 CORE_ADDR pc
, CORE_ADDR current_pc
,
1253 struct i386_frame_cache
*cache
)
1255 pc
= i386_skip_noop (pc
);
1256 pc
= i386_follow_jump (gdbarch
, pc
);
1257 pc
= i386_analyze_struct_return (pc
, current_pc
, cache
);
1258 pc
= i386_skip_probe (pc
);
1259 pc
= i386_analyze_stack_align (pc
, current_pc
, cache
);
1260 pc
= i386_analyze_frame_setup (gdbarch
, pc
, current_pc
, cache
);
1261 return i386_analyze_register_saves (pc
, current_pc
, cache
);
1264 /* Return PC of first real instruction. */
1267 i386_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
1269 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1271 static gdb_byte pic_pat
[6] =
1273 0xe8, 0, 0, 0, 0, /* call 0x0 */
1274 0x5b, /* popl %ebx */
1276 struct i386_frame_cache cache
;
1282 pc
= i386_analyze_prologue (gdbarch
, start_pc
, 0xffffffff, &cache
);
1283 if (cache
.locals
< 0)
1286 /* Found valid frame setup. */
1288 /* The native cc on SVR4 in -K PIC mode inserts the following code
1289 to get the address of the global offset table (GOT) into register
1294 movl %ebx,x(%ebp) (optional)
1297 This code is with the rest of the prologue (at the end of the
1298 function), so we have to skip it to get to the first real
1299 instruction at the start of the function. */
1301 for (i
= 0; i
< 6; i
++)
1303 target_read_memory (pc
+ i
, &op
, 1);
1304 if (pic_pat
[i
] != op
)
1311 target_read_memory (pc
+ delta
, &op
, 1);
1313 if (op
== 0x89) /* movl %ebx, x(%ebp) */
1315 op
= read_memory_unsigned_integer (pc
+ delta
+ 1, 1, byte_order
);
1317 if (op
== 0x5d) /* One byte offset from %ebp. */
1319 else if (op
== 0x9d) /* Four byte offset from %ebp. */
1321 else /* Unexpected instruction. */
1324 target_read_memory (pc
+ delta
, &op
, 1);
1328 if (delta
> 0 && op
== 0x81
1329 && read_memory_unsigned_integer (pc
+ delta
+ 1, 1, byte_order
)
1336 /* If the function starts with a branch (to startup code at the end)
1337 the last instruction should bring us back to the first
1338 instruction of the real code. */
1339 if (i386_follow_jump (gdbarch
, start_pc
) != start_pc
)
1340 pc
= i386_follow_jump (gdbarch
, pc
);
1345 /* Check that the code pointed to by PC corresponds to a call to
1346 __main, skip it if so. Return PC otherwise. */
1349 i386_skip_main_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1351 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1354 target_read_memory (pc
, &op
, 1);
1359 if (target_read_memory (pc
+ 1, buf
, sizeof buf
) == 0)
1361 /* Make sure address is computed correctly as a 32bit
1362 integer even if CORE_ADDR is 64 bit wide. */
1363 struct minimal_symbol
*s
;
1364 CORE_ADDR call_dest
;
1366 call_dest
= pc
+ 5 + extract_signed_integer (buf
, 4, byte_order
);
1367 call_dest
= call_dest
& 0xffffffffU
;
1368 s
= lookup_minimal_symbol_by_pc (call_dest
);
1370 && SYMBOL_LINKAGE_NAME (s
) != NULL
1371 && strcmp (SYMBOL_LINKAGE_NAME (s
), "__main") == 0)
1379 /* This function is 64-bit safe. */
1382 i386_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1386 frame_unwind_register (next_frame
, gdbarch_pc_regnum (gdbarch
), buf
);
1387 return extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
1391 /* Normal frames. */
1393 static struct i386_frame_cache
*
1394 i386_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1396 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1397 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1398 struct i386_frame_cache
*cache
;
1405 cache
= i386_alloc_frame_cache ();
1406 *this_cache
= cache
;
1408 /* In principle, for normal frames, %ebp holds the frame pointer,
1409 which holds the base address for the current stack frame.
1410 However, for functions that don't need it, the frame pointer is
1411 optional. For these "frameless" functions the frame pointer is
1412 actually the frame pointer of the calling frame. Signal
1413 trampolines are just a special case of a "frameless" function.
1414 They (usually) share their frame pointer with the frame that was
1415 in progress when the signal occurred. */
1417 get_frame_register (this_frame
, I386_EBP_REGNUM
, buf
);
1418 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
);
1419 if (cache
->base
== 0)
1422 /* For normal frames, %eip is stored at 4(%ebp). */
1423 cache
->saved_regs
[I386_EIP_REGNUM
] = 4;
1425 cache
->pc
= get_frame_func (this_frame
);
1427 i386_analyze_prologue (gdbarch
, cache
->pc
, get_frame_pc (this_frame
),
1430 if (cache
->saved_sp_reg
!= -1)
1432 /* Saved stack pointer has been saved. */
1433 get_frame_register (this_frame
, cache
->saved_sp_reg
, buf
);
1434 cache
->saved_sp
= extract_unsigned_integer (buf
, 4, byte_order
);
1437 if (cache
->locals
< 0)
1439 /* We didn't find a valid frame, which means that CACHE->base
1440 currently holds the frame pointer for our calling frame. If
1441 we're at the start of a function, or somewhere half-way its
1442 prologue, the function's frame probably hasn't been fully
1443 setup yet. Try to reconstruct the base address for the stack
1444 frame by looking at the stack pointer. For truly "frameless"
1445 functions this might work too. */
1447 if (cache
->saved_sp_reg
!= -1)
1449 /* We're halfway aligning the stack. */
1450 cache
->base
= ((cache
->saved_sp
- 4) & 0xfffffff0) - 4;
1451 cache
->saved_regs
[I386_EIP_REGNUM
] = cache
->saved_sp
- 4;
1453 /* This will be added back below. */
1454 cache
->saved_regs
[I386_EIP_REGNUM
] -= cache
->base
;
1456 else if (cache
->pc
!= 0
1457 || target_read_memory (get_frame_pc (this_frame
), buf
, 1))
1459 /* We're in a known function, but did not find a frame
1460 setup. Assume that the function does not use %ebp.
1461 Alternatively, we may have jumped to an invalid
1462 address; in that case there is definitely no new
1464 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
1465 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
)
1469 /* We're in an unknown function. We could not find the start
1470 of the function to analyze the prologue; our best option is
1471 to assume a typical frame layout with the caller's %ebp
1473 cache
->saved_regs
[I386_EBP_REGNUM
] = 0;
1476 /* Now that we have the base address for the stack frame we can
1477 calculate the value of %esp in the calling frame. */
1478 if (cache
->saved_sp
== 0)
1479 cache
->saved_sp
= cache
->base
+ 8;
1481 /* Adjust all the saved registers such that they contain addresses
1482 instead of offsets. */
1483 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
1484 if (cache
->saved_regs
[i
] != -1)
1485 cache
->saved_regs
[i
] += cache
->base
;
1491 i386_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
1492 struct frame_id
*this_id
)
1494 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1496 /* This marks the outermost frame. */
1497 if (cache
->base
== 0)
1500 /* See the end of i386_push_dummy_call. */
1501 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
1504 static struct value
*
1505 i386_frame_prev_register (struct frame_info
*this_frame
, void **this_cache
,
1508 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1510 gdb_assert (regnum
>= 0);
1512 /* The System V ABI says that:
1514 "The flags register contains the system flags, such as the
1515 direction flag and the carry flag. The direction flag must be
1516 set to the forward (that is, zero) direction before entry and
1517 upon exit from a function. Other user flags have no specified
1518 role in the standard calling sequence and are not preserved."
1520 To guarantee the "upon exit" part of that statement we fake a
1521 saved flags register that has its direction flag cleared.
1523 Note that GCC doesn't seem to rely on the fact that the direction
1524 flag is cleared after a function return; it always explicitly
1525 clears the flag before operations where it matters.
1527 FIXME: kettenis/20030316: I'm not quite sure whether this is the
1528 right thing to do. The way we fake the flags register here makes
1529 it impossible to change it. */
1531 if (regnum
== I386_EFLAGS_REGNUM
)
1535 val
= get_frame_register_unsigned (this_frame
, regnum
);
1537 return frame_unwind_got_constant (this_frame
, regnum
, val
);
1540 if (regnum
== I386_EIP_REGNUM
&& cache
->pc_in_eax
)
1541 return frame_unwind_got_register (this_frame
, regnum
, I386_EAX_REGNUM
);
1543 if (regnum
== I386_ESP_REGNUM
&& cache
->saved_sp
)
1544 return frame_unwind_got_constant (this_frame
, regnum
, cache
->saved_sp
);
1546 if (regnum
< I386_NUM_SAVED_REGS
&& cache
->saved_regs
[regnum
] != -1)
1547 return frame_unwind_got_memory (this_frame
, regnum
,
1548 cache
->saved_regs
[regnum
]);
1550 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
1553 static const struct frame_unwind i386_frame_unwind
=
1557 i386_frame_prev_register
,
1559 default_frame_sniffer
1562 /* Normal frames, but in a function epilogue. */
1564 /* The epilogue is defined here as the 'ret' instruction, which will
1565 follow any instruction such as 'leave' or 'pop %ebp' that destroys
1566 the function's stack frame. */
1569 i386_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1573 if (target_read_memory (pc
, &insn
, 1))
1574 return 0; /* Can't read memory at pc. */
1576 if (insn
!= 0xc3) /* 'ret' instruction. */
1583 i386_epilogue_frame_sniffer (const struct frame_unwind
*self
,
1584 struct frame_info
*this_frame
,
1585 void **this_prologue_cache
)
1587 if (frame_relative_level (this_frame
) == 0)
1588 return i386_in_function_epilogue_p (get_frame_arch (this_frame
),
1589 get_frame_pc (this_frame
));
1594 static struct i386_frame_cache
*
1595 i386_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1597 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1598 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1599 struct i386_frame_cache
*cache
;
1605 cache
= i386_alloc_frame_cache ();
1606 *this_cache
= cache
;
1608 /* Cache base will be %esp plus cache->sp_offset (-4). */
1609 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
1610 cache
->base
= extract_unsigned_integer (buf
, 4,
1611 byte_order
) + cache
->sp_offset
;
1613 /* Cache pc will be the frame func. */
1614 cache
->pc
= get_frame_pc (this_frame
);
1616 /* The saved %esp will be at cache->base plus 8. */
1617 cache
->saved_sp
= cache
->base
+ 8;
1619 /* The saved %eip will be at cache->base plus 4. */
1620 cache
->saved_regs
[I386_EIP_REGNUM
] = cache
->base
+ 4;
1626 i386_epilogue_frame_this_id (struct frame_info
*this_frame
,
1628 struct frame_id
*this_id
)
1630 struct i386_frame_cache
*cache
= i386_epilogue_frame_cache (this_frame
,
1633 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
1636 static const struct frame_unwind i386_epilogue_frame_unwind
=
1639 i386_epilogue_frame_this_id
,
1640 i386_frame_prev_register
,
1642 i386_epilogue_frame_sniffer
1646 /* Signal trampolines. */
1648 static struct i386_frame_cache
*
1649 i386_sigtramp_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1651 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1652 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1653 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1654 struct i386_frame_cache
*cache
;
1661 cache
= i386_alloc_frame_cache ();
1663 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
1664 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
) - 4;
1666 addr
= tdep
->sigcontext_addr (this_frame
);
1667 if (tdep
->sc_reg_offset
)
1671 gdb_assert (tdep
->sc_num_regs
<= I386_NUM_SAVED_REGS
);
1673 for (i
= 0; i
< tdep
->sc_num_regs
; i
++)
1674 if (tdep
->sc_reg_offset
[i
] != -1)
1675 cache
->saved_regs
[i
] = addr
+ tdep
->sc_reg_offset
[i
];
1679 cache
->saved_regs
[I386_EIP_REGNUM
] = addr
+ tdep
->sc_pc_offset
;
1680 cache
->saved_regs
[I386_ESP_REGNUM
] = addr
+ tdep
->sc_sp_offset
;
1683 *this_cache
= cache
;
1688 i386_sigtramp_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
1689 struct frame_id
*this_id
)
1691 struct i386_frame_cache
*cache
=
1692 i386_sigtramp_frame_cache (this_frame
, this_cache
);
1694 /* See the end of i386_push_dummy_call. */
1695 (*this_id
) = frame_id_build (cache
->base
+ 8, get_frame_pc (this_frame
));
1698 static struct value
*
1699 i386_sigtramp_frame_prev_register (struct frame_info
*this_frame
,
1700 void **this_cache
, int regnum
)
1702 /* Make sure we've initialized the cache. */
1703 i386_sigtramp_frame_cache (this_frame
, this_cache
);
1705 return i386_frame_prev_register (this_frame
, this_cache
, regnum
);
1709 i386_sigtramp_frame_sniffer (const struct frame_unwind
*self
,
1710 struct frame_info
*this_frame
,
1711 void **this_prologue_cache
)
1713 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (this_frame
));
1715 /* We shouldn't even bother if we don't have a sigcontext_addr
1717 if (tdep
->sigcontext_addr
== NULL
)
1720 if (tdep
->sigtramp_p
!= NULL
)
1722 if (tdep
->sigtramp_p (this_frame
))
1726 if (tdep
->sigtramp_start
!= 0)
1728 CORE_ADDR pc
= get_frame_pc (this_frame
);
1730 gdb_assert (tdep
->sigtramp_end
!= 0);
1731 if (pc
>= tdep
->sigtramp_start
&& pc
< tdep
->sigtramp_end
)
1738 static const struct frame_unwind i386_sigtramp_frame_unwind
=
1741 i386_sigtramp_frame_this_id
,
1742 i386_sigtramp_frame_prev_register
,
1744 i386_sigtramp_frame_sniffer
1749 i386_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
1751 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1756 static const struct frame_base i386_frame_base
=
1759 i386_frame_base_address
,
1760 i386_frame_base_address
,
1761 i386_frame_base_address
1764 static struct frame_id
1765 i386_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1769 fp
= get_frame_register_unsigned (this_frame
, I386_EBP_REGNUM
);
1771 /* See the end of i386_push_dummy_call. */
1772 return frame_id_build (fp
+ 8, get_frame_pc (this_frame
));
1776 /* Figure out where the longjmp will land. Slurp the args out of the
1777 stack. We expect the first arg to be a pointer to the jmp_buf
1778 structure from which we extract the address that we will land at.
1779 This address is copied into PC. This routine returns non-zero on
1783 i386_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
1786 CORE_ADDR sp
, jb_addr
;
1787 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1788 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1789 int jb_pc_offset
= gdbarch_tdep (gdbarch
)->jb_pc_offset
;
1791 /* If JB_PC_OFFSET is -1, we have no way to find out where the
1792 longjmp will land. */
1793 if (jb_pc_offset
== -1)
1796 get_frame_register (frame
, I386_ESP_REGNUM
, buf
);
1797 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
1798 if (target_read_memory (sp
+ 4, buf
, 4))
1801 jb_addr
= extract_unsigned_integer (buf
, 4, byte_order
);
1802 if (target_read_memory (jb_addr
+ jb_pc_offset
, buf
, 4))
1805 *pc
= extract_unsigned_integer (buf
, 4, byte_order
);
1810 /* Check whether TYPE must be 16-byte-aligned when passed as a
1811 function argument. 16-byte vectors, _Decimal128 and structures or
1812 unions containing such types must be 16-byte-aligned; other
1813 arguments are 4-byte-aligned. */
1816 i386_16_byte_align_p (struct type
*type
)
1818 type
= check_typedef (type
);
1819 if ((TYPE_CODE (type
) == TYPE_CODE_DECFLOAT
1820 || (TYPE_CODE (type
) == TYPE_CODE_ARRAY
&& TYPE_VECTOR (type
)))
1821 && TYPE_LENGTH (type
) == 16)
1823 if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
1824 return i386_16_byte_align_p (TYPE_TARGET_TYPE (type
));
1825 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
1826 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
1829 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
1831 if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type
, i
)))
1839 i386_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
1840 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
1841 struct value
**args
, CORE_ADDR sp
, int struct_return
,
1842 CORE_ADDR struct_addr
)
1844 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1850 /* Determine the total space required for arguments and struct
1851 return address in a first pass (allowing for 16-byte-aligned
1852 arguments), then push arguments in a second pass. */
1854 for (write_pass
= 0; write_pass
< 2; write_pass
++)
1856 int args_space_used
= 0;
1857 int have_16_byte_aligned_arg
= 0;
1863 /* Push value address. */
1864 store_unsigned_integer (buf
, 4, byte_order
, struct_addr
);
1865 write_memory (sp
, buf
, 4);
1866 args_space_used
+= 4;
1872 for (i
= 0; i
< nargs
; i
++)
1874 int len
= TYPE_LENGTH (value_enclosing_type (args
[i
]));
1878 if (i386_16_byte_align_p (value_enclosing_type (args
[i
])))
1879 args_space_used
= align_up (args_space_used
, 16);
1881 write_memory (sp
+ args_space_used
,
1882 value_contents_all (args
[i
]), len
);
1883 /* The System V ABI says that:
1885 "An argument's size is increased, if necessary, to make it a
1886 multiple of [32-bit] words. This may require tail padding,
1887 depending on the size of the argument."
1889 This makes sure the stack stays word-aligned. */
1890 args_space_used
+= align_up (len
, 4);
1894 if (i386_16_byte_align_p (value_enclosing_type (args
[i
])))
1896 args_space
= align_up (args_space
, 16);
1897 have_16_byte_aligned_arg
= 1;
1899 args_space
+= align_up (len
, 4);
1905 if (have_16_byte_aligned_arg
)
1906 args_space
= align_up (args_space
, 16);
1911 /* Store return address. */
1913 store_unsigned_integer (buf
, 4, byte_order
, bp_addr
);
1914 write_memory (sp
, buf
, 4);
1916 /* Finally, update the stack pointer... */
1917 store_unsigned_integer (buf
, 4, byte_order
, sp
);
1918 regcache_cooked_write (regcache
, I386_ESP_REGNUM
, buf
);
1920 /* ...and fake a frame pointer. */
1921 regcache_cooked_write (regcache
, I386_EBP_REGNUM
, buf
);
1923 /* MarkK wrote: This "+ 8" is all over the place:
1924 (i386_frame_this_id, i386_sigtramp_frame_this_id,
1925 i386_dummy_id). It's there, since all frame unwinders for
1926 a given target have to agree (within a certain margin) on the
1927 definition of the stack address of a frame. Otherwise frame id
1928 comparison might not work correctly. Since DWARF2/GCC uses the
1929 stack address *before* the function call as a frame's CFA. On
1930 the i386, when %ebp is used as a frame pointer, the offset
1931 between the contents %ebp and the CFA as defined by GCC. */
1935 /* These registers are used for returning integers (and on some
1936 targets also for returning `struct' and `union' values when their
1937 size and alignment match an integer type). */
1938 #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */
1939 #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */
1941 /* Read, for architecture GDBARCH, a function return value of TYPE
1942 from REGCACHE, and copy that into VALBUF. */
1945 i386_extract_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
1946 struct regcache
*regcache
, gdb_byte
*valbuf
)
1948 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1949 int len
= TYPE_LENGTH (type
);
1950 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
1952 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
1954 if (tdep
->st0_regnum
< 0)
1956 warning (_("Cannot find floating-point return value."));
1957 memset (valbuf
, 0, len
);
1961 /* Floating-point return values can be found in %st(0). Convert
1962 its contents to the desired type. This is probably not
1963 exactly how it would happen on the target itself, but it is
1964 the best we can do. */
1965 regcache_raw_read (regcache
, I386_ST0_REGNUM
, buf
);
1966 convert_typed_floating (buf
, i387_ext_type (gdbarch
), valbuf
, type
);
1970 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
1971 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
1973 if (len
<= low_size
)
1975 regcache_raw_read (regcache
, LOW_RETURN_REGNUM
, buf
);
1976 memcpy (valbuf
, buf
, len
);
1978 else if (len
<= (low_size
+ high_size
))
1980 regcache_raw_read (regcache
, LOW_RETURN_REGNUM
, buf
);
1981 memcpy (valbuf
, buf
, low_size
);
1982 regcache_raw_read (regcache
, HIGH_RETURN_REGNUM
, buf
);
1983 memcpy (valbuf
+ low_size
, buf
, len
- low_size
);
1986 internal_error (__FILE__
, __LINE__
,
1987 _("Cannot extract return value of %d bytes long."), len
);
1991 /* Write, for architecture GDBARCH, a function return value of TYPE
1992 from VALBUF into REGCACHE. */
1995 i386_store_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
1996 struct regcache
*regcache
, const gdb_byte
*valbuf
)
1998 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1999 int len
= TYPE_LENGTH (type
);
2001 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2004 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
2006 if (tdep
->st0_regnum
< 0)
2008 warning (_("Cannot set floating-point return value."));
2012 /* Returning floating-point values is a bit tricky. Apart from
2013 storing the return value in %st(0), we have to simulate the
2014 state of the FPU at function return point. */
2016 /* Convert the value found in VALBUF to the extended
2017 floating-point format used by the FPU. This is probably
2018 not exactly how it would happen on the target itself, but
2019 it is the best we can do. */
2020 convert_typed_floating (valbuf
, type
, buf
, i387_ext_type (gdbarch
));
2021 regcache_raw_write (regcache
, I386_ST0_REGNUM
, buf
);
2023 /* Set the top of the floating-point register stack to 7. The
2024 actual value doesn't really matter, but 7 is what a normal
2025 function return would end up with if the program started out
2026 with a freshly initialized FPU. */
2027 regcache_raw_read_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), &fstat
);
2029 regcache_raw_write_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), fstat
);
2031 /* Mark %st(1) through %st(7) as empty. Since we set the top of
2032 the floating-point register stack to 7, the appropriate value
2033 for the tag word is 0x3fff. */
2034 regcache_raw_write_unsigned (regcache
, I387_FTAG_REGNUM (tdep
), 0x3fff);
2038 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
2039 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
2041 if (len
<= low_size
)
2042 regcache_raw_write_part (regcache
, LOW_RETURN_REGNUM
, 0, len
, valbuf
);
2043 else if (len
<= (low_size
+ high_size
))
2045 regcache_raw_write (regcache
, LOW_RETURN_REGNUM
, valbuf
);
2046 regcache_raw_write_part (regcache
, HIGH_RETURN_REGNUM
, 0,
2047 len
- low_size
, valbuf
+ low_size
);
2050 internal_error (__FILE__
, __LINE__
,
2051 _("Cannot store return value of %d bytes long."), len
);
2056 /* This is the variable that is set with "set struct-convention", and
2057 its legitimate values. */
2058 static const char default_struct_convention
[] = "default";
2059 static const char pcc_struct_convention
[] = "pcc";
2060 static const char reg_struct_convention
[] = "reg";
2061 static const char *valid_conventions
[] =
2063 default_struct_convention
,
2064 pcc_struct_convention
,
2065 reg_struct_convention
,
2068 static const char *struct_convention
= default_struct_convention
;
2070 /* Return non-zero if TYPE, which is assumed to be a structure,
2071 a union type, or an array type, should be returned in registers
2072 for architecture GDBARCH. */
2075 i386_reg_struct_return_p (struct gdbarch
*gdbarch
, struct type
*type
)
2077 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2078 enum type_code code
= TYPE_CODE (type
);
2079 int len
= TYPE_LENGTH (type
);
2081 gdb_assert (code
== TYPE_CODE_STRUCT
2082 || code
== TYPE_CODE_UNION
2083 || code
== TYPE_CODE_ARRAY
);
2085 if (struct_convention
== pcc_struct_convention
2086 || (struct_convention
== default_struct_convention
2087 && tdep
->struct_return
== pcc_struct_return
))
2090 /* Structures consisting of a single `float', `double' or 'long
2091 double' member are returned in %st(0). */
2092 if (code
== TYPE_CODE_STRUCT
&& TYPE_NFIELDS (type
) == 1)
2094 type
= check_typedef (TYPE_FIELD_TYPE (type
, 0));
2095 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2096 return (len
== 4 || len
== 8 || len
== 12);
2099 return (len
== 1 || len
== 2 || len
== 4 || len
== 8);
2102 /* Determine, for architecture GDBARCH, how a return value of TYPE
2103 should be returned. If it is supposed to be returned in registers,
2104 and READBUF is non-zero, read the appropriate value from REGCACHE,
2105 and copy it into READBUF. If WRITEBUF is non-zero, write the value
2106 from WRITEBUF into REGCACHE. */
2108 static enum return_value_convention
2109 i386_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
2110 struct type
*type
, struct regcache
*regcache
,
2111 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2113 enum type_code code
= TYPE_CODE (type
);
2115 if (((code
== TYPE_CODE_STRUCT
2116 || code
== TYPE_CODE_UNION
2117 || code
== TYPE_CODE_ARRAY
)
2118 && !i386_reg_struct_return_p (gdbarch
, type
))
2119 /* 128-bit decimal float uses the struct return convention. */
2120 || (code
== TYPE_CODE_DECFLOAT
&& TYPE_LENGTH (type
) == 16))
2122 /* The System V ABI says that:
2124 "A function that returns a structure or union also sets %eax
2125 to the value of the original address of the caller's area
2126 before it returns. Thus when the caller receives control
2127 again, the address of the returned object resides in register
2128 %eax and can be used to access the object."
2130 So the ABI guarantees that we can always find the return
2131 value just after the function has returned. */
2133 /* Note that the ABI doesn't mention functions returning arrays,
2134 which is something possible in certain languages such as Ada.
2135 In this case, the value is returned as if it was wrapped in
2136 a record, so the convention applied to records also applies
2143 regcache_raw_read_unsigned (regcache
, I386_EAX_REGNUM
, &addr
);
2144 read_memory (addr
, readbuf
, TYPE_LENGTH (type
));
2147 return RETURN_VALUE_ABI_RETURNS_ADDRESS
;
2150 /* This special case is for structures consisting of a single
2151 `float', `double' or 'long double' member. These structures are
2152 returned in %st(0). For these structures, we call ourselves
2153 recursively, changing TYPE into the type of the first member of
2154 the structure. Since that should work for all structures that
2155 have only one member, we don't bother to check the member's type
2157 if (code
== TYPE_CODE_STRUCT
&& TYPE_NFIELDS (type
) == 1)
2159 type
= check_typedef (TYPE_FIELD_TYPE (type
, 0));
2160 return i386_return_value (gdbarch
, func_type
, type
, regcache
,
2165 i386_extract_return_value (gdbarch
, type
, regcache
, readbuf
);
2167 i386_store_return_value (gdbarch
, type
, regcache
, writebuf
);
2169 return RETURN_VALUE_REGISTER_CONVENTION
;
2174 i387_ext_type (struct gdbarch
*gdbarch
)
2176 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2178 if (!tdep
->i387_ext_type
)
2180 tdep
->i387_ext_type
= tdesc_find_type (gdbarch
, "i387_ext");
2181 gdb_assert (tdep
->i387_ext_type
!= NULL
);
2184 return tdep
->i387_ext_type
;
2187 /* Construct vector type for MMX registers. */
2188 static struct type
*
2189 i386_mmx_type (struct gdbarch
*gdbarch
)
2191 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2193 if (!tdep
->i386_mmx_type
)
2195 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2197 /* The type we're building is this: */
2199 union __gdb_builtin_type_vec64i
2202 int32_t v2_int32
[2];
2203 int16_t v4_int16
[4];
2210 t
= arch_composite_type (gdbarch
,
2211 "__gdb_builtin_type_vec64i", TYPE_CODE_UNION
);
2213 append_composite_type_field (t
, "uint64", bt
->builtin_int64
);
2214 append_composite_type_field (t
, "v2_int32",
2215 init_vector_type (bt
->builtin_int32
, 2));
2216 append_composite_type_field (t
, "v4_int16",
2217 init_vector_type (bt
->builtin_int16
, 4));
2218 append_composite_type_field (t
, "v8_int8",
2219 init_vector_type (bt
->builtin_int8
, 8));
2221 TYPE_VECTOR (t
) = 1;
2222 TYPE_NAME (t
) = "builtin_type_vec64i";
2223 tdep
->i386_mmx_type
= t
;
2226 return tdep
->i386_mmx_type
;
2229 /* Return the GDB type object for the "standard" data type of data in
2232 static struct type
*
2233 i386_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
2235 if (i386_mmx_regnum_p (gdbarch
, regnum
))
2236 return i386_mmx_type (gdbarch
);
2239 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2240 if (i386_byte_regnum_p (gdbarch
, regnum
))
2241 return bt
->builtin_int8
;
2242 else if (i386_word_regnum_p (gdbarch
, regnum
))
2243 return bt
->builtin_int16
;
2244 else if (i386_dword_regnum_p (gdbarch
, regnum
))
2245 return bt
->builtin_int32
;
2248 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
2251 /* Map a cooked register onto a raw register or memory. For the i386,
2252 the MMX registers need to be mapped onto floating point registers. */
2255 i386_mmx_regnum_to_fp_regnum (struct regcache
*regcache
, int regnum
)
2257 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_regcache_arch (regcache
));
2262 mmxreg
= regnum
- tdep
->mm0_regnum
;
2263 regcache_raw_read_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), &fstat
);
2264 tos
= (fstat
>> 11) & 0x7;
2265 fpreg
= (mmxreg
+ tos
) % 8;
2267 return (I387_ST0_REGNUM (tdep
) + fpreg
);
2271 i386_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2272 int regnum
, gdb_byte
*buf
)
2274 gdb_byte raw_buf
[MAX_REGISTER_SIZE
];
2276 if (i386_mmx_regnum_p (gdbarch
, regnum
))
2278 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
2280 /* Extract (always little endian). */
2281 regcache_raw_read (regcache
, fpnum
, raw_buf
);
2282 memcpy (buf
, raw_buf
, register_size (gdbarch
, regnum
));
2286 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2288 if (i386_word_regnum_p (gdbarch
, regnum
))
2290 int gpnum
= regnum
- tdep
->ax_regnum
;
2292 /* Extract (always little endian). */
2293 regcache_raw_read (regcache
, gpnum
, raw_buf
);
2294 memcpy (buf
, raw_buf
, 2);
2296 else if (i386_byte_regnum_p (gdbarch
, regnum
))
2298 /* Check byte pseudo registers last since this function will
2299 be called from amd64_pseudo_register_read, which handles
2300 byte pseudo registers differently. */
2301 int gpnum
= regnum
- tdep
->al_regnum
;
2303 /* Extract (always little endian). We read both lower and
2305 regcache_raw_read (regcache
, gpnum
% 4, raw_buf
);
2307 memcpy (buf
, raw_buf
+ 1, 1);
2309 memcpy (buf
, raw_buf
, 1);
2312 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
2317 i386_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2318 int regnum
, const gdb_byte
*buf
)
2320 gdb_byte raw_buf
[MAX_REGISTER_SIZE
];
2322 if (i386_mmx_regnum_p (gdbarch
, regnum
))
2324 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
2327 regcache_raw_read (regcache
, fpnum
, raw_buf
);
2328 /* ... Modify ... (always little endian). */
2329 memcpy (raw_buf
, buf
, register_size (gdbarch
, regnum
));
2331 regcache_raw_write (regcache
, fpnum
, raw_buf
);
2335 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2337 if (i386_word_regnum_p (gdbarch
, regnum
))
2339 int gpnum
= regnum
- tdep
->ax_regnum
;
2342 regcache_raw_read (regcache
, gpnum
, raw_buf
);
2343 /* ... Modify ... (always little endian). */
2344 memcpy (raw_buf
, buf
, 2);
2346 regcache_raw_write (regcache
, gpnum
, raw_buf
);
2348 else if (i386_byte_regnum_p (gdbarch
, regnum
))
2350 /* Check byte pseudo registers last since this function will
2351 be called from amd64_pseudo_register_read, which handles
2352 byte pseudo registers differently. */
2353 int gpnum
= regnum
- tdep
->al_regnum
;
2355 /* Read ... We read both lower and upper registers. */
2356 regcache_raw_read (regcache
, gpnum
% 4, raw_buf
);
2357 /* ... Modify ... (always little endian). */
2359 memcpy (raw_buf
+ 1, buf
, 1);
2361 memcpy (raw_buf
, buf
, 1);
2363 regcache_raw_write (regcache
, gpnum
% 4, raw_buf
);
2366 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
2371 /* Return the register number of the register allocated by GCC after
2372 REGNUM, or -1 if there is no such register. */
2375 i386_next_regnum (int regnum
)
2377 /* GCC allocates the registers in the order:
2379 %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ...
2381 Since storing a variable in %esp doesn't make any sense we return
2382 -1 for %ebp and for %esp itself. */
2383 static int next_regnum
[] =
2385 I386_EDX_REGNUM
, /* Slot for %eax. */
2386 I386_EBX_REGNUM
, /* Slot for %ecx. */
2387 I386_ECX_REGNUM
, /* Slot for %edx. */
2388 I386_ESI_REGNUM
, /* Slot for %ebx. */
2389 -1, -1, /* Slots for %esp and %ebp. */
2390 I386_EDI_REGNUM
, /* Slot for %esi. */
2391 I386_EBP_REGNUM
/* Slot for %edi. */
2394 if (regnum
>= 0 && regnum
< sizeof (next_regnum
) / sizeof (next_regnum
[0]))
2395 return next_regnum
[regnum
];
2400 /* Return nonzero if a value of type TYPE stored in register REGNUM
2401 needs any special handling. */
2404 i386_convert_register_p (struct gdbarch
*gdbarch
, int regnum
, struct type
*type
)
2406 int len
= TYPE_LENGTH (type
);
2408 /* Values may be spread across multiple registers. Most debugging
2409 formats aren't expressive enough to specify the locations, so
2410 some heuristics is involved. Right now we only handle types that
2411 have a length that is a multiple of the word size, since GCC
2412 doesn't seem to put any other types into registers. */
2413 if (len
> 4 && len
% 4 == 0)
2415 int last_regnum
= regnum
;
2419 last_regnum
= i386_next_regnum (last_regnum
);
2423 if (last_regnum
!= -1)
2427 return i387_convert_register_p (gdbarch
, regnum
, type
);
2430 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
2431 return its contents in TO. */
2434 i386_register_to_value (struct frame_info
*frame
, int regnum
,
2435 struct type
*type
, gdb_byte
*to
)
2437 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2438 int len
= TYPE_LENGTH (type
);
2440 /* FIXME: kettenis/20030609: What should we do if REGNUM isn't
2441 available in FRAME (i.e. if it wasn't saved)? */
2443 if (i386_fp_regnum_p (gdbarch
, regnum
))
2445 i387_register_to_value (frame
, regnum
, type
, to
);
2449 /* Read a value spread across multiple registers. */
2451 gdb_assert (len
> 4 && len
% 4 == 0);
2455 gdb_assert (regnum
!= -1);
2456 gdb_assert (register_size (gdbarch
, regnum
) == 4);
2458 get_frame_register (frame
, regnum
, to
);
2459 regnum
= i386_next_regnum (regnum
);
2465 /* Write the contents FROM of a value of type TYPE into register
2466 REGNUM in frame FRAME. */
2469 i386_value_to_register (struct frame_info
*frame
, int regnum
,
2470 struct type
*type
, const gdb_byte
*from
)
2472 int len
= TYPE_LENGTH (type
);
2474 if (i386_fp_regnum_p (get_frame_arch (frame
), regnum
))
2476 i387_value_to_register (frame
, regnum
, type
, from
);
2480 /* Write a value spread across multiple registers. */
2482 gdb_assert (len
> 4 && len
% 4 == 0);
2486 gdb_assert (regnum
!= -1);
2487 gdb_assert (register_size (get_frame_arch (frame
), regnum
) == 4);
2489 put_frame_register (frame
, regnum
, from
);
2490 regnum
= i386_next_regnum (regnum
);
2496 /* Supply register REGNUM from the buffer specified by GREGS and LEN
2497 in the general-purpose register set REGSET to register cache
2498 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
2501 i386_supply_gregset (const struct regset
*regset
, struct regcache
*regcache
,
2502 int regnum
, const void *gregs
, size_t len
)
2504 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
2505 const gdb_byte
*regs
= gregs
;
2508 gdb_assert (len
== tdep
->sizeof_gregset
);
2510 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
2512 if ((regnum
== i
|| regnum
== -1)
2513 && tdep
->gregset_reg_offset
[i
] != -1)
2514 regcache_raw_supply (regcache
, i
, regs
+ tdep
->gregset_reg_offset
[i
]);
2518 /* Collect register REGNUM from the register cache REGCACHE and store
2519 it in the buffer specified by GREGS and LEN as described by the
2520 general-purpose register set REGSET. If REGNUM is -1, do this for
2521 all registers in REGSET. */
2524 i386_collect_gregset (const struct regset
*regset
,
2525 const struct regcache
*regcache
,
2526 int regnum
, void *gregs
, size_t len
)
2528 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
2529 gdb_byte
*regs
= gregs
;
2532 gdb_assert (len
== tdep
->sizeof_gregset
);
2534 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
2536 if ((regnum
== i
|| regnum
== -1)
2537 && tdep
->gregset_reg_offset
[i
] != -1)
2538 regcache_raw_collect (regcache
, i
, regs
+ tdep
->gregset_reg_offset
[i
]);
2542 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
2543 in the floating-point register set REGSET to register cache
2544 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
2547 i386_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
2548 int regnum
, const void *fpregs
, size_t len
)
2550 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
2552 if (len
== I387_SIZEOF_FXSAVE
)
2554 i387_supply_fxsave (regcache
, regnum
, fpregs
);
2558 gdb_assert (len
== tdep
->sizeof_fpregset
);
2559 i387_supply_fsave (regcache
, regnum
, fpregs
);
2562 /* Collect register REGNUM from the register cache REGCACHE and store
2563 it in the buffer specified by FPREGS and LEN as described by the
2564 floating-point register set REGSET. If REGNUM is -1, do this for
2565 all registers in REGSET. */
2568 i386_collect_fpregset (const struct regset
*regset
,
2569 const struct regcache
*regcache
,
2570 int regnum
, void *fpregs
, size_t len
)
2572 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
2574 if (len
== I387_SIZEOF_FXSAVE
)
2576 i387_collect_fxsave (regcache
, regnum
, fpregs
);
2580 gdb_assert (len
== tdep
->sizeof_fpregset
);
2581 i387_collect_fsave (regcache
, regnum
, fpregs
);
2584 /* Return the appropriate register set for the core section identified
2585 by SECT_NAME and SECT_SIZE. */
2587 const struct regset
*
2588 i386_regset_from_core_section (struct gdbarch
*gdbarch
,
2589 const char *sect_name
, size_t sect_size
)
2591 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2593 if (strcmp (sect_name
, ".reg") == 0 && sect_size
== tdep
->sizeof_gregset
)
2595 if (tdep
->gregset
== NULL
)
2596 tdep
->gregset
= regset_alloc (gdbarch
, i386_supply_gregset
,
2597 i386_collect_gregset
);
2598 return tdep
->gregset
;
2601 if ((strcmp (sect_name
, ".reg2") == 0 && sect_size
== tdep
->sizeof_fpregset
)
2602 || (strcmp (sect_name
, ".reg-xfp") == 0
2603 && sect_size
== I387_SIZEOF_FXSAVE
))
2605 if (tdep
->fpregset
== NULL
)
2606 tdep
->fpregset
= regset_alloc (gdbarch
, i386_supply_fpregset
,
2607 i386_collect_fpregset
);
2608 return tdep
->fpregset
;
2615 /* Stuff for WIN32 PE style DLL's but is pretty generic really. */
2618 i386_pe_skip_trampoline_code (struct frame_info
*frame
,
2619 CORE_ADDR pc
, char *name
)
2621 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2622 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2625 if (pc
&& read_memory_unsigned_integer (pc
, 2, byte_order
) == 0x25ff)
2627 unsigned long indirect
=
2628 read_memory_unsigned_integer (pc
+ 2, 4, byte_order
);
2629 struct minimal_symbol
*indsym
=
2630 indirect
? lookup_minimal_symbol_by_pc (indirect
) : 0;
2631 char *symname
= indsym
? SYMBOL_LINKAGE_NAME (indsym
) : 0;
2635 if (strncmp (symname
, "__imp_", 6) == 0
2636 || strncmp (symname
, "_imp_", 5) == 0)
2638 read_memory_unsigned_integer (indirect
, 4, byte_order
);
2641 return 0; /* Not a trampoline. */
2645 /* Return whether the THIS_FRAME corresponds to a sigtramp
2649 i386_sigtramp_p (struct frame_info
*this_frame
)
2651 CORE_ADDR pc
= get_frame_pc (this_frame
);
2654 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
2655 return (name
&& strcmp ("_sigtramp", name
) == 0);
2659 /* We have two flavours of disassembly. The machinery on this page
2660 deals with switching between those. */
2663 i386_print_insn (bfd_vma pc
, struct disassemble_info
*info
)
2665 gdb_assert (disassembly_flavor
== att_flavor
2666 || disassembly_flavor
== intel_flavor
);
2668 /* FIXME: kettenis/20020915: Until disassembler_options is properly
2669 constified, cast to prevent a compiler warning. */
2670 info
->disassembler_options
= (char *) disassembly_flavor
;
2672 return print_insn_i386 (pc
, info
);
2676 /* There are a few i386 architecture variants that differ only
2677 slightly from the generic i386 target. For now, we don't give them
2678 their own source file, but include them here. As a consequence,
2679 they'll always be included. */
2681 /* System V Release 4 (SVR4). */
2683 /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp
2687 i386_svr4_sigtramp_p (struct frame_info
*this_frame
)
2689 CORE_ADDR pc
= get_frame_pc (this_frame
);
2692 /* UnixWare uses _sigacthandler. The origin of the other symbols is
2693 currently unknown. */
2694 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
2695 return (name
&& (strcmp ("_sigreturn", name
) == 0
2696 || strcmp ("_sigacthandler", name
) == 0
2697 || strcmp ("sigvechandler", name
) == 0));
2700 /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the
2701 address of the associated sigcontext (ucontext) structure. */
2704 i386_svr4_sigcontext_addr (struct frame_info
*this_frame
)
2706 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2707 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2711 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
2712 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
2714 return read_memory_unsigned_integer (sp
+ 8, 4, byte_order
);
2721 i386_elf_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
2723 /* We typically use stabs-in-ELF with the SVR4 register numbering. */
2724 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
2727 /* System V Release 4 (SVR4). */
2730 i386_svr4_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
2732 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2734 /* System V Release 4 uses ELF. */
2735 i386_elf_init_abi (info
, gdbarch
);
2737 /* System V Release 4 has shared libraries. */
2738 set_gdbarch_skip_trampoline_code (gdbarch
, find_solib_trampoline_target
);
2740 tdep
->sigtramp_p
= i386_svr4_sigtramp_p
;
2741 tdep
->sigcontext_addr
= i386_svr4_sigcontext_addr
;
2742 tdep
->sc_pc_offset
= 36 + 14 * 4;
2743 tdep
->sc_sp_offset
= 36 + 17 * 4;
2745 tdep
->jb_pc_offset
= 20;
2751 i386_go32_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
2753 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2755 /* DJGPP doesn't have any special frames for signal handlers. */
2756 tdep
->sigtramp_p
= NULL
;
2758 tdep
->jb_pc_offset
= 36;
2760 /* DJGPP does not support the SSE registers. */
2761 tdep
->num_xmm_regs
= 0;
2762 set_gdbarch_num_regs (gdbarch
, I386_NUM_GREGS
+ I387_NUM_REGS
);
2764 /* Native compiler is GCC, which uses the SVR4 register numbering
2765 even in COFF and STABS. See the comment in i386_gdbarch_init,
2766 before the calls to set_gdbarch_stab_reg_to_regnum and
2767 set_gdbarch_sdb_reg_to_regnum. */
2768 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
2769 set_gdbarch_sdb_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
2773 /* i386 register groups. In addition to the normal groups, add "mmx"
2776 static struct reggroup
*i386_sse_reggroup
;
2777 static struct reggroup
*i386_mmx_reggroup
;
2780 i386_init_reggroups (void)
2782 i386_sse_reggroup
= reggroup_new ("sse", USER_REGGROUP
);
2783 i386_mmx_reggroup
= reggroup_new ("mmx", USER_REGGROUP
);
2787 i386_add_reggroups (struct gdbarch
*gdbarch
)
2789 reggroup_add (gdbarch
, i386_sse_reggroup
);
2790 reggroup_add (gdbarch
, i386_mmx_reggroup
);
2791 reggroup_add (gdbarch
, general_reggroup
);
2792 reggroup_add (gdbarch
, float_reggroup
);
2793 reggroup_add (gdbarch
, all_reggroup
);
2794 reggroup_add (gdbarch
, save_reggroup
);
2795 reggroup_add (gdbarch
, restore_reggroup
);
2796 reggroup_add (gdbarch
, vector_reggroup
);
2797 reggroup_add (gdbarch
, system_reggroup
);
2801 i386_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
2802 struct reggroup
*group
)
2804 int sse_regnum_p
, fp_regnum_p
, mmx_regnum_p
, byte_regnum_p
,
2805 word_regnum_p
, dword_regnum_p
;
2807 /* Don't include pseudo registers, except for MMX, in any register
2809 byte_regnum_p
= i386_byte_regnum_p (gdbarch
, regnum
);
2813 word_regnum_p
= i386_word_regnum_p (gdbarch
, regnum
);
2817 dword_regnum_p
= i386_dword_regnum_p (gdbarch
, regnum
);
2821 mmx_regnum_p
= i386_mmx_regnum_p (gdbarch
, regnum
);
2822 if (group
== i386_mmx_reggroup
)
2823 return mmx_regnum_p
;
2825 sse_regnum_p
= (i386_sse_regnum_p (gdbarch
, regnum
)
2826 || i386_mxcsr_regnum_p (gdbarch
, regnum
));
2827 if (group
== i386_sse_reggroup
)
2828 return sse_regnum_p
;
2829 if (group
== vector_reggroup
)
2830 return mmx_regnum_p
|| sse_regnum_p
;
2832 fp_regnum_p
= (i386_fp_regnum_p (gdbarch
, regnum
)
2833 || i386_fpc_regnum_p (gdbarch
, regnum
));
2834 if (group
== float_reggroup
)
2837 if (group
== general_reggroup
)
2838 return (!fp_regnum_p
2843 && !dword_regnum_p
);
2845 return default_register_reggroup_p (gdbarch
, regnum
, group
);
2849 /* Get the ARGIth function argument for the current function. */
2852 i386_fetch_pointer_argument (struct frame_info
*frame
, int argi
,
2855 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2856 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2857 CORE_ADDR sp
= get_frame_register_unsigned (frame
, I386_ESP_REGNUM
);
2858 return read_memory_unsigned_integer (sp
+ (4 * (argi
+ 1)), 4, byte_order
);
2862 i386_skip_permanent_breakpoint (struct regcache
*regcache
)
2864 CORE_ADDR current_pc
= regcache_read_pc (regcache
);
2866 /* On i386, breakpoint is exactly 1 byte long, so we just
2867 adjust the PC in the regcache. */
2869 regcache_write_pc (regcache
, current_pc
);
2873 #define PREFIX_REPZ 0x01
2874 #define PREFIX_REPNZ 0x02
2875 #define PREFIX_LOCK 0x04
2876 #define PREFIX_DATA 0x08
2877 #define PREFIX_ADDR 0x10
2888 /* i386 arith/logic operations */
2901 struct i386_record_s
2903 struct gdbarch
*gdbarch
;
2904 struct regcache
*regcache
;
2905 CORE_ADDR orig_addr
;
2911 uint8_t mod
, reg
, rm
;
2920 /* Parse "modrm" part in current memory address that irp->addr point to
2921 Return -1 if something wrong. */
2924 i386_record_modrm (struct i386_record_s
*irp
)
2926 struct gdbarch
*gdbarch
= irp
->gdbarch
;
2928 if (target_read_memory (irp
->addr
, &irp
->modrm
, 1))
2931 printf_unfiltered (_("Process record: error reading memory at "
2932 "addr %s len = 1.\n"),
2933 paddress (gdbarch
, irp
->addr
));
2937 irp
->mod
= (irp
->modrm
>> 6) & 3;
2938 irp
->reg
= (irp
->modrm
>> 3) & 7;
2939 irp
->rm
= irp
->modrm
& 7;
2944 /* Get the memory address that current instruction write to and set it to
2945 the argument "addr".
2946 Return -1 if something wrong. */
2949 i386_record_lea_modrm_addr (struct i386_record_s
*irp
, uint64_t *addr
)
2951 struct gdbarch
*gdbarch
= irp
->gdbarch
;
2952 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2964 uint8_t base
= irp
->rm
;
2969 if (target_read_memory (irp
->addr
, &byte
, 1))
2972 printf_unfiltered (_("Process record: error reading memory "
2973 "at addr %s len = 1.\n"),
2974 paddress (gdbarch
, irp
->addr
));
2978 scale
= (byte
>> 6) & 3;
2979 index
= ((byte
>> 3) & 7) | irp
->rex_x
;
2987 if ((base
& 7) == 5)
2990 if (target_read_memory (irp
->addr
, buf
, 4))
2993 printf_unfiltered (_("Process record: error reading "
2994 "memory at addr %s len = 4.\n"),
2995 paddress (gdbarch
, irp
->addr
));
2999 *addr
= extract_signed_integer (buf
, 4, byte_order
);
3000 if (irp
->regmap
[X86_RECORD_R8_REGNUM
] && !havesib
)
3001 *addr
+= irp
->addr
+ irp
->rip_offset
;
3009 if (target_read_memory (irp
->addr
, buf
, 1))
3012 printf_unfiltered (_("Process record: error reading memory "
3013 "at addr %s len = 1.\n"),
3014 paddress (gdbarch
, irp
->addr
));
3018 *addr
= (int8_t) buf
[0];
3021 if (target_read_memory (irp
->addr
, buf
, 4))
3024 printf_unfiltered (_("Process record: error reading memory "
3025 "at addr %s len = 4.\n"),
3026 paddress (gdbarch
, irp
->addr
));
3029 *addr
= extract_signed_integer (buf
, 4, byte_order
);
3037 if (base
== 4 && irp
->popl_esp_hack
)
3038 *addr
+= irp
->popl_esp_hack
;
3039 regcache_raw_read_unsigned (irp
->regcache
, irp
->regmap
[base
],
3042 if (irp
->aflag
== 2)
3047 *addr
= (uint32_t) (offset64
+ *addr
);
3049 if (havesib
&& (index
!= 4 || scale
!= 0))
3051 regcache_raw_read_unsigned (irp
->regcache
, irp
->regmap
[index
],
3053 if (irp
->aflag
== 2)
3054 *addr
+= offset64
<< scale
;
3056 *addr
= (uint32_t) (*addr
+ (offset64
<< scale
));
3067 if (target_read_memory (irp
->addr
, buf
, 2))
3070 printf_unfiltered (_("Process record: error reading "
3071 "memory at addr %s len = 2.\n"),
3072 paddress (gdbarch
, irp
->addr
));
3076 *addr
= extract_signed_integer (buf
, 2, byte_order
);
3086 if (target_read_memory (irp
->addr
, buf
, 1))
3089 printf_unfiltered (_("Process record: error reading memory "
3090 "at addr %s len = 1.\n"),
3091 paddress (gdbarch
, irp
->addr
));
3095 *addr
= (int8_t) buf
[0];
3098 if (target_read_memory (irp
->addr
, buf
, 2))
3101 printf_unfiltered (_("Process record: error reading memory "
3102 "at addr %s len = 2.\n"),
3103 paddress (gdbarch
, irp
->addr
));
3107 *addr
= extract_signed_integer (buf
, 2, byte_order
);
3114 regcache_raw_read_unsigned (irp
->regcache
,
3115 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
3117 *addr
= (uint32_t) (*addr
+ offset64
);
3118 regcache_raw_read_unsigned (irp
->regcache
,
3119 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
3121 *addr
= (uint32_t) (*addr
+ offset64
);
3124 regcache_raw_read_unsigned (irp
->regcache
,
3125 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
3127 *addr
= (uint32_t) (*addr
+ offset64
);
3128 regcache_raw_read_unsigned (irp
->regcache
,
3129 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
3131 *addr
= (uint32_t) (*addr
+ offset64
);
3134 regcache_raw_read_unsigned (irp
->regcache
,
3135 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
3137 *addr
= (uint32_t) (*addr
+ offset64
);
3138 regcache_raw_read_unsigned (irp
->regcache
,
3139 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
3141 *addr
= (uint32_t) (*addr
+ offset64
);
3144 regcache_raw_read_unsigned (irp
->regcache
,
3145 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
3147 *addr
= (uint32_t) (*addr
+ offset64
);
3148 regcache_raw_read_unsigned (irp
->regcache
,
3149 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
3151 *addr
= (uint32_t) (*addr
+ offset64
);
3154 regcache_raw_read_unsigned (irp
->regcache
,
3155 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
3157 *addr
= (uint32_t) (*addr
+ offset64
);
3160 regcache_raw_read_unsigned (irp
->regcache
,
3161 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
3163 *addr
= (uint32_t) (*addr
+ offset64
);
3166 regcache_raw_read_unsigned (irp
->regcache
,
3167 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
3169 *addr
= (uint32_t) (*addr
+ offset64
);
3172 regcache_raw_read_unsigned (irp
->regcache
,
3173 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
3175 *addr
= (uint32_t) (*addr
+ offset64
);
3185 /* Record the value of the memory that willbe changed in current instruction
3186 to "record_arch_list".
3187 Return -1 if something wrong. */
3190 i386_record_lea_modrm (struct i386_record_s
*irp
)
3192 struct gdbarch
*gdbarch
= irp
->gdbarch
;
3195 if (irp
->override
>= 0)
3197 warning (_("Process record ignores the memory change "
3198 "of instruction at address %s because it "
3199 "can't get the value of the segment register."),
3200 paddress (gdbarch
, irp
->orig_addr
));
3204 if (i386_record_lea_modrm_addr (irp
, &addr
))
3207 if (record_arch_list_add_mem (addr
, 1 << irp
->ot
))
3213 /* Record the push operation to "record_arch_list".
3214 Return -1 if something wrong. */
3217 i386_record_push (struct i386_record_s
*irp
, int size
)
3221 if (record_arch_list_add_reg (irp
->regcache
,
3222 irp
->regmap
[X86_RECORD_RESP_REGNUM
]))
3224 regcache_raw_read_unsigned (irp
->regcache
,
3225 irp
->regmap
[X86_RECORD_RESP_REGNUM
],
3227 if (record_arch_list_add_mem ((CORE_ADDR
) addr
- size
, size
))
3234 /* Defines contents to record. */
3235 #define I386_SAVE_FPU_REGS 0xfffd
3236 #define I386_SAVE_FPU_ENV 0xfffe
3237 #define I386_SAVE_FPU_ENV_REG_STACK 0xffff
3239 /* Record the value of floating point registers which will be changed by the
3240 current instruction to "record_arch_list". Return -1 if something is wrong.
3243 static int i386_record_floats (struct gdbarch
*gdbarch
,
3244 struct i386_record_s
*ir
,
3247 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3250 /* Oza: Because of floating point insn push/pop of fpu stack is going to
3251 happen. Currently we store st0-st7 registers, but we need not store all
3252 registers all the time, in future we use ftag register and record only
3253 those who are not marked as an empty. */
3255 if (I386_SAVE_FPU_REGS
== iregnum
)
3257 for (i
= I387_ST0_REGNUM (tdep
); i
<= I387_ST0_REGNUM (tdep
) + 7; i
++)
3259 if (record_arch_list_add_reg (ir
->regcache
, i
))
3263 else if (I386_SAVE_FPU_ENV
== iregnum
)
3265 for (i
= I387_FCTRL_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
3267 if (record_arch_list_add_reg (ir
->regcache
, i
))
3271 else if (I386_SAVE_FPU_ENV_REG_STACK
== iregnum
)
3273 for (i
= I387_ST0_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
3275 if (record_arch_list_add_reg (ir
->regcache
, i
))
3279 else if ((iregnum
>= I387_ST0_REGNUM (tdep
)) &&
3280 (iregnum
<= I387_FOP_REGNUM (tdep
)))
3282 if (record_arch_list_add_reg (ir
->regcache
,iregnum
))
3287 /* Parameter error. */
3290 if(I386_SAVE_FPU_ENV
!= iregnum
)
3292 for (i
= I387_FCTRL_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
3294 if (record_arch_list_add_reg (ir
->regcache
, i
))
3301 /* Parse the current instruction and record the values of the registers and
3302 memory that will be changed in current instruction to "record_arch_list".
3303 Return -1 if something wrong. */
3305 #define I386_RECORD_ARCH_LIST_ADD_REG(regnum) \
3306 record_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)])
3309 i386_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
3310 CORE_ADDR input_addr
)
3312 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3318 gdb_byte buf
[MAX_REGISTER_SIZE
];
3319 struct i386_record_s ir
;
3320 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3325 memset (&ir
, 0, sizeof (struct i386_record_s
));
3326 ir
.regcache
= regcache
;
3327 ir
.addr
= input_addr
;
3328 ir
.orig_addr
= input_addr
;
3332 ir
.popl_esp_hack
= 0;
3333 ir
.regmap
= gdbarch_tdep (gdbarch
)->record_regmap
;
3334 ir
.gdbarch
= gdbarch
;
3336 if (record_debug
> 1)
3337 fprintf_unfiltered (gdb_stdlog
, "Process record: i386_process_record "
3339 paddress (gdbarch
, ir
.addr
));
3344 if (target_read_memory (ir
.addr
, &opcode8
, 1))
3347 printf_unfiltered (_("Process record: error reading memory at "
3348 "addr %s len = 1.\n"),
3349 paddress (gdbarch
, ir
.addr
));
3353 switch (opcode8
) /* Instruction prefixes */
3355 case REPE_PREFIX_OPCODE
:
3356 prefixes
|= PREFIX_REPZ
;
3358 case REPNE_PREFIX_OPCODE
:
3359 prefixes
|= PREFIX_REPNZ
;
3361 case LOCK_PREFIX_OPCODE
:
3362 prefixes
|= PREFIX_LOCK
;
3364 case CS_PREFIX_OPCODE
:
3365 ir
.override
= X86_RECORD_CS_REGNUM
;
3367 case SS_PREFIX_OPCODE
:
3368 ir
.override
= X86_RECORD_SS_REGNUM
;
3370 case DS_PREFIX_OPCODE
:
3371 ir
.override
= X86_RECORD_DS_REGNUM
;
3373 case ES_PREFIX_OPCODE
:
3374 ir
.override
= X86_RECORD_ES_REGNUM
;
3376 case FS_PREFIX_OPCODE
:
3377 ir
.override
= X86_RECORD_FS_REGNUM
;
3379 case GS_PREFIX_OPCODE
:
3380 ir
.override
= X86_RECORD_GS_REGNUM
;
3382 case DATA_PREFIX_OPCODE
:
3383 prefixes
|= PREFIX_DATA
;
3385 case ADDR_PREFIX_OPCODE
:
3386 prefixes
|= PREFIX_ADDR
;
3388 case 0x40: /* i386 inc %eax */
3389 case 0x41: /* i386 inc %ecx */
3390 case 0x42: /* i386 inc %edx */
3391 case 0x43: /* i386 inc %ebx */
3392 case 0x44: /* i386 inc %esp */
3393 case 0x45: /* i386 inc %ebp */
3394 case 0x46: /* i386 inc %esi */
3395 case 0x47: /* i386 inc %edi */
3396 case 0x48: /* i386 dec %eax */
3397 case 0x49: /* i386 dec %ecx */
3398 case 0x4a: /* i386 dec %edx */
3399 case 0x4b: /* i386 dec %ebx */
3400 case 0x4c: /* i386 dec %esp */
3401 case 0x4d: /* i386 dec %ebp */
3402 case 0x4e: /* i386 dec %esi */
3403 case 0x4f: /* i386 dec %edi */
3404 if (ir
.regmap
[X86_RECORD_R8_REGNUM
]) /* 64 bit target */
3408 rex_w
= (opcode8
>> 3) & 1;
3409 rex_r
= (opcode8
& 0x4) << 1;
3410 ir
.rex_x
= (opcode8
& 0x2) << 2;
3411 ir
.rex_b
= (opcode8
& 0x1) << 3;
3413 else /* 32 bit target */
3422 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && rex_w
== 1)
3428 if (prefixes
& PREFIX_DATA
)
3431 if (prefixes
& PREFIX_ADDR
)
3433 else if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
3436 /* now check op code */
3437 opcode
= (uint32_t) opcode8
;
3442 if (target_read_memory (ir
.addr
, &opcode8
, 1))
3445 printf_unfiltered (_("Process record: error reading memory at "
3446 "addr %s len = 1.\n"),
3447 paddress (gdbarch
, ir
.addr
));
3451 opcode
= (uint16_t) opcode8
| 0x0f00;
3455 case 0x00: /* arith & logic */
3503 if (((opcode
>> 3) & 7) != OP_CMPL
)
3505 if ((opcode
& 1) == 0)
3508 ir
.ot
= ir
.dflag
+ OT_WORD
;
3510 switch ((opcode
>> 1) & 3)
3512 case 0: /* OP Ev, Gv */
3513 if (i386_record_modrm (&ir
))
3517 if (i386_record_lea_modrm (&ir
))
3523 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3525 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
3528 case 1: /* OP Gv, Ev */
3529 if (i386_record_modrm (&ir
))
3532 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3534 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
3536 case 2: /* OP A, Iv */
3537 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
3541 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3544 case 0x80: /* GRP1 */
3548 if (i386_record_modrm (&ir
))
3551 if (ir
.reg
!= OP_CMPL
)
3553 if ((opcode
& 1) == 0)
3556 ir
.ot
= ir
.dflag
+ OT_WORD
;
3563 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
3564 if (i386_record_lea_modrm (&ir
))
3568 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
3570 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3573 case 0x40: /* inc */
3582 case 0x48: /* dec */
3591 I386_RECORD_ARCH_LIST_ADD_REG (opcode
& 7);
3592 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3595 case 0xf6: /* GRP3 */
3597 if ((opcode
& 1) == 0)
3600 ir
.ot
= ir
.dflag
+ OT_WORD
;
3601 if (i386_record_modrm (&ir
))
3604 if (ir
.mod
!= 3 && ir
.reg
== 0)
3605 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
3610 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3616 if (i386_record_lea_modrm (&ir
))
3622 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3624 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
3626 if (ir
.reg
== 3) /* neg */
3627 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3633 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
3634 if (ir
.ot
!= OT_BYTE
)
3635 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
3636 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3640 opcode
= opcode
<< 8 | ir
.modrm
;
3646 case 0xfe: /* GRP4 */
3647 case 0xff: /* GRP5 */
3648 if (i386_record_modrm (&ir
))
3650 if (ir
.reg
>= 2 && opcode
== 0xfe)
3653 opcode
= opcode
<< 8 | ir
.modrm
;
3660 if ((opcode
& 1) == 0)
3663 ir
.ot
= ir
.dflag
+ OT_WORD
;
3666 if (i386_record_lea_modrm (&ir
))
3672 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3674 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
3676 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3679 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
3681 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
3683 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3686 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
3687 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
3689 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3693 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3696 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
3698 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
3703 opcode
= opcode
<< 8 | ir
.modrm
;
3709 case 0x84: /* test */
3713 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3716 case 0x98: /* CWDE/CBW */
3717 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
3720 case 0x99: /* CDQ/CWD */
3721 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
3722 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
3725 case 0x0faf: /* imul */
3728 ir
.ot
= ir
.dflag
+ OT_WORD
;
3729 if (i386_record_modrm (&ir
))
3732 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
3733 else if (opcode
== 0x6b)
3736 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3738 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
3739 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3742 case 0x0fc0: /* xadd */
3744 if ((opcode
& 1) == 0)
3747 ir
.ot
= ir
.dflag
+ OT_WORD
;
3748 if (i386_record_modrm (&ir
))
3753 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3755 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
3756 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3758 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
3762 if (i386_record_lea_modrm (&ir
))
3764 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3766 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
3768 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3771 case 0x0fb0: /* cmpxchg */
3773 if ((opcode
& 1) == 0)
3776 ir
.ot
= ir
.dflag
+ OT_WORD
;
3777 if (i386_record_modrm (&ir
))
3782 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
3783 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3785 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
3789 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
3790 if (i386_record_lea_modrm (&ir
))
3793 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3796 case 0x0fc7: /* cmpxchg8b */
3797 if (i386_record_modrm (&ir
))
3802 opcode
= opcode
<< 8 | ir
.modrm
;
3805 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
3806 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
3807 if (i386_record_lea_modrm (&ir
))
3809 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3812 case 0x50: /* push */
3822 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
3824 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
3828 case 0x06: /* push es */
3829 case 0x0e: /* push cs */
3830 case 0x16: /* push ss */
3831 case 0x1e: /* push ds */
3832 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
3837 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
3841 case 0x0fa0: /* push fs */
3842 case 0x0fa8: /* push gs */
3843 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
3848 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
3852 case 0x60: /* pusha */
3853 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
3858 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 4)))
3862 case 0x58: /* pop */
3870 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
3871 I386_RECORD_ARCH_LIST_ADD_REG ((opcode
& 0x7) | ir
.rex_b
);
3874 case 0x61: /* popa */
3875 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
3880 for (regnum
= X86_RECORD_REAX_REGNUM
;
3881 regnum
<= X86_RECORD_REDI_REGNUM
;
3883 I386_RECORD_ARCH_LIST_ADD_REG (regnum
);
3886 case 0x8f: /* pop */
3887 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
3888 ir
.ot
= ir
.dflag
? OT_QUAD
: OT_WORD
;
3890 ir
.ot
= ir
.dflag
+ OT_WORD
;
3891 if (i386_record_modrm (&ir
))
3894 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
3897 ir
.popl_esp_hack
= 1 << ir
.ot
;
3898 if (i386_record_lea_modrm (&ir
))
3901 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
3904 case 0xc8: /* enter */
3905 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
3906 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
3908 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
3912 case 0xc9: /* leave */
3913 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
3914 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
3917 case 0x07: /* pop es */
3918 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
3923 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
3924 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM
);
3925 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3928 case 0x17: /* pop ss */
3929 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
3934 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
3935 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM
);
3936 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3939 case 0x1f: /* pop ds */
3940 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
3945 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
3946 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM
);
3947 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3950 case 0x0fa1: /* pop fs */
3951 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
3952 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM
);
3953 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3956 case 0x0fa9: /* pop gs */
3957 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
3958 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM
);
3959 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3962 case 0x88: /* mov */
3966 if ((opcode
& 1) == 0)
3969 ir
.ot
= ir
.dflag
+ OT_WORD
;
3971 if (i386_record_modrm (&ir
))
3976 if (opcode
== 0xc6 || opcode
== 0xc7)
3977 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
3978 if (i386_record_lea_modrm (&ir
))
3983 if (opcode
== 0xc6 || opcode
== 0xc7)
3985 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3987 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
3991 case 0x8a: /* mov */
3993 if ((opcode
& 1) == 0)
3996 ir
.ot
= ir
.dflag
+ OT_WORD
;
3997 if (i386_record_modrm (&ir
))
4000 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4002 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4005 case 0x8c: /* mov seg */
4006 if (i386_record_modrm (&ir
))
4011 opcode
= opcode
<< 8 | ir
.modrm
;
4016 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4020 if (i386_record_lea_modrm (&ir
))
4025 case 0x8e: /* mov seg */
4026 if (i386_record_modrm (&ir
))
4031 regnum
= X86_RECORD_ES_REGNUM
;
4034 regnum
= X86_RECORD_SS_REGNUM
;
4037 regnum
= X86_RECORD_DS_REGNUM
;
4040 regnum
= X86_RECORD_FS_REGNUM
;
4043 regnum
= X86_RECORD_GS_REGNUM
;
4047 opcode
= opcode
<< 8 | ir
.modrm
;
4051 I386_RECORD_ARCH_LIST_ADD_REG (regnum
);
4052 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4055 case 0x0fb6: /* movzbS */
4056 case 0x0fb7: /* movzwS */
4057 case 0x0fbe: /* movsbS */
4058 case 0x0fbf: /* movswS */
4059 if (i386_record_modrm (&ir
))
4061 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
4064 case 0x8d: /* lea */
4065 if (i386_record_modrm (&ir
))
4070 opcode
= opcode
<< 8 | ir
.modrm
;
4075 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4077 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4080 case 0xa0: /* mov EAX */
4083 case 0xd7: /* xlat */
4084 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4087 case 0xa2: /* mov EAX */
4089 if (ir
.override
>= 0)
4091 warning (_("Process record ignores the memory change "
4092 "of instruction at address %s because "
4093 "it can't get the value of the segment "
4095 paddress (gdbarch
, ir
.orig_addr
));
4099 if ((opcode
& 1) == 0)
4102 ir
.ot
= ir
.dflag
+ OT_WORD
;
4105 if (target_read_memory (ir
.addr
, buf
, 8))
4108 printf_unfiltered (_("Process record: error reading "
4109 "memory at addr 0x%s len = 8.\n"),
4110 paddress (gdbarch
, ir
.addr
));
4114 addr
= extract_unsigned_integer (buf
, 8, byte_order
);
4118 if (target_read_memory (ir
.addr
, buf
, 4))
4121 printf_unfiltered (_("Process record: error reading "
4122 "memory at addr 0x%s len = 4.\n"),
4123 paddress (gdbarch
, ir
.addr
));
4127 addr
= extract_unsigned_integer (buf
, 4, byte_order
);
4131 if (target_read_memory (ir
.addr
, buf
, 2))
4134 printf_unfiltered (_("Process record: error reading "
4135 "memory at addr 0x%s len = 2.\n"),
4136 paddress (gdbarch
, ir
.addr
));
4140 addr
= extract_unsigned_integer (buf
, 2, byte_order
);
4142 if (record_arch_list_add_mem (addr
, 1 << ir
.ot
))
4147 case 0xb0: /* mov R, Ib */
4155 I386_RECORD_ARCH_LIST_ADD_REG ((ir
.regmap
[X86_RECORD_R8_REGNUM
])
4156 ? ((opcode
& 0x7) | ir
.rex_b
)
4157 : ((opcode
& 0x7) & 0x3));
4160 case 0xb8: /* mov R, Iv */
4168 I386_RECORD_ARCH_LIST_ADD_REG ((opcode
& 0x7) | ir
.rex_b
);
4171 case 0x91: /* xchg R, EAX */
4178 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4179 I386_RECORD_ARCH_LIST_ADD_REG (opcode
& 0x7);
4182 case 0x86: /* xchg Ev, Gv */
4184 if ((opcode
& 1) == 0)
4187 ir
.ot
= ir
.dflag
+ OT_WORD
;
4188 if (i386_record_modrm (&ir
))
4193 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4195 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4199 if (i386_record_lea_modrm (&ir
))
4203 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4205 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4208 case 0xc4: /* les Gv */
4209 case 0xc5: /* lds Gv */
4210 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4215 case 0x0fb2: /* lss Gv */
4216 case 0x0fb4: /* lfs Gv */
4217 case 0x0fb5: /* lgs Gv */
4218 if (i386_record_modrm (&ir
))
4226 opcode
= opcode
<< 8 | ir
.modrm
;
4231 case 0xc4: /* les Gv */
4232 regnum
= X86_RECORD_ES_REGNUM
;
4234 case 0xc5: /* lds Gv */
4235 regnum
= X86_RECORD_DS_REGNUM
;
4237 case 0x0fb2: /* lss Gv */
4238 regnum
= X86_RECORD_SS_REGNUM
;
4240 case 0x0fb4: /* lfs Gv */
4241 regnum
= X86_RECORD_FS_REGNUM
;
4243 case 0x0fb5: /* lgs Gv */
4244 regnum
= X86_RECORD_GS_REGNUM
;
4247 I386_RECORD_ARCH_LIST_ADD_REG (regnum
);
4248 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
4249 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4252 case 0xc0: /* shifts */
4258 if ((opcode
& 1) == 0)
4261 ir
.ot
= ir
.dflag
+ OT_WORD
;
4262 if (i386_record_modrm (&ir
))
4264 if (ir
.mod
!= 3 && (opcode
== 0xd2 || opcode
== 0xd3))
4266 if (i386_record_lea_modrm (&ir
))
4272 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4274 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4276 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4283 if (i386_record_modrm (&ir
))
4287 if (record_arch_list_add_reg (ir
.regcache
, ir
.rm
))
4292 if (i386_record_lea_modrm (&ir
))
4297 case 0xd8: /* Floats. */
4305 if (i386_record_modrm (&ir
))
4307 ir
.reg
|= ((opcode
& 7) << 3);
4313 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
4321 /* For fcom, ficom nothing to do. */
4327 /* For fcomp, ficomp pop FPU stack, store all. */
4328 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
4355 /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul,
4356 fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension
4357 of code, always affects st(0) register. */
4358 if (i386_record_floats (gdbarch
, &ir
, I387_ST0_REGNUM (tdep
)))
4382 /* Handling fld, fild. */
4383 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
4387 switch (ir
.reg
>> 4)
4390 if (record_arch_list_add_mem (addr64
, 4))
4394 if (record_arch_list_add_mem (addr64
, 8))
4400 if (record_arch_list_add_mem (addr64
, 2))
4406 switch (ir
.reg
>> 4)
4409 if (record_arch_list_add_mem (addr64
, 4))
4411 if (3 == (ir
.reg
& 7))
4413 /* For fstp m32fp. */
4414 if (i386_record_floats (gdbarch
, &ir
,
4415 I386_SAVE_FPU_REGS
))
4420 if (record_arch_list_add_mem (addr64
, 4))
4422 if ((3 == (ir
.reg
& 7))
4423 || (5 == (ir
.reg
& 7))
4424 || (7 == (ir
.reg
& 7)))
4426 /* For fstp insn. */
4427 if (i386_record_floats (gdbarch
, &ir
,
4428 I386_SAVE_FPU_REGS
))
4433 if (record_arch_list_add_mem (addr64
, 8))
4435 if (3 == (ir
.reg
& 7))
4437 /* For fstp m64fp. */
4438 if (i386_record_floats (gdbarch
, &ir
,
4439 I386_SAVE_FPU_REGS
))
4444 if ((3 <= (ir
.reg
& 7)) && (6 <= (ir
.reg
& 7)))
4446 /* For fistp, fbld, fild, fbstp. */
4447 if (i386_record_floats (gdbarch
, &ir
,
4448 I386_SAVE_FPU_REGS
))
4453 if (record_arch_list_add_mem (addr64
, 2))
4462 if (i386_record_floats (gdbarch
, &ir
,
4463 I386_SAVE_FPU_ENV_REG_STACK
))
4468 if (i386_record_floats (gdbarch
, &ir
, I387_FCTRL_REGNUM (tdep
)))
4473 if (i386_record_floats (gdbarch
, &ir
,
4474 I386_SAVE_FPU_ENV_REG_STACK
))
4480 if (record_arch_list_add_mem (addr64
, 28))
4485 if (record_arch_list_add_mem (addr64
, 14))
4491 if (record_arch_list_add_mem (addr64
, 2))
4493 /* Insn fstp, fbstp. */
4494 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
4499 if (record_arch_list_add_mem (addr64
, 10))
4505 if (record_arch_list_add_mem (addr64
, 28))
4511 if (record_arch_list_add_mem (addr64
, 14))
4515 if (record_arch_list_add_mem (addr64
, 80))
4518 if (i386_record_floats (gdbarch
, &ir
,
4519 I386_SAVE_FPU_ENV_REG_STACK
))
4523 if (record_arch_list_add_mem (addr64
, 8))
4526 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
4531 opcode
= opcode
<< 8 | ir
.modrm
;
4536 /* Opcode is an extension of modR/M byte. */
4542 if (i386_record_floats (gdbarch
, &ir
, I387_ST0_REGNUM (tdep
)))
4546 if (0x0c == (ir
.modrm
>> 4))
4548 if ((ir
.modrm
& 0x0f) <= 7)
4550 if (i386_record_floats (gdbarch
, &ir
,
4551 I386_SAVE_FPU_REGS
))
4556 if (i386_record_floats (gdbarch
, &ir
,
4557 I387_ST0_REGNUM (tdep
)))
4559 /* If only st(0) is changing, then we have already
4561 if ((ir
.modrm
& 0x0f) - 0x08)
4563 if (i386_record_floats (gdbarch
, &ir
,
4564 I387_ST0_REGNUM (tdep
) +
4565 ((ir
.modrm
& 0x0f) - 0x08)))
4583 if (i386_record_floats (gdbarch
, &ir
,
4584 I387_ST0_REGNUM (tdep
)))
4602 if (i386_record_floats (gdbarch
, &ir
,
4603 I386_SAVE_FPU_REGS
))
4607 if (i386_record_floats (gdbarch
, &ir
,
4608 I387_ST0_REGNUM (tdep
)))
4610 if (i386_record_floats (gdbarch
, &ir
,
4611 I387_ST0_REGNUM (tdep
) + 1))
4618 if (0xe9 == ir
.modrm
)
4620 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
4623 else if ((0x0c == ir
.modrm
>> 4) || (0x0d == ir
.modrm
>> 4))
4625 if (i386_record_floats (gdbarch
, &ir
,
4626 I387_ST0_REGNUM (tdep
)))
4628 if (((ir
.modrm
& 0x0f) > 0) && ((ir
.modrm
& 0x0f) <= 7))
4630 if (i386_record_floats (gdbarch
, &ir
,
4631 I387_ST0_REGNUM (tdep
) +
4635 else if ((ir
.modrm
& 0x0f) - 0x08)
4637 if (i386_record_floats (gdbarch
, &ir
,
4638 I387_ST0_REGNUM (tdep
) +
4639 ((ir
.modrm
& 0x0f) - 0x08)))
4645 if (0xe3 == ir
.modrm
)
4647 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_ENV
))
4650 else if ((0x0c == ir
.modrm
>> 4) || (0x0d == ir
.modrm
>> 4))
4652 if (i386_record_floats (gdbarch
, &ir
,
4653 I387_ST0_REGNUM (tdep
)))
4655 if (((ir
.modrm
& 0x0f) > 0) && ((ir
.modrm
& 0x0f) <= 7))
4657 if (i386_record_floats (gdbarch
, &ir
,
4658 I387_ST0_REGNUM (tdep
) +
4662 else if ((ir
.modrm
& 0x0f) - 0x08)
4664 if (i386_record_floats (gdbarch
, &ir
,
4665 I387_ST0_REGNUM (tdep
) +
4666 ((ir
.modrm
& 0x0f) - 0x08)))
4672 if ((0x0c == ir
.modrm
>> 4)
4673 || (0x0d == ir
.modrm
>> 4)
4674 || (0x0f == ir
.modrm
>> 4))
4676 if ((ir
.modrm
& 0x0f) <= 7)
4678 if (i386_record_floats (gdbarch
, &ir
,
4679 I387_ST0_REGNUM (tdep
) +
4685 if (i386_record_floats (gdbarch
, &ir
,
4686 I387_ST0_REGNUM (tdep
) +
4687 ((ir
.modrm
& 0x0f) - 0x08)))
4693 if (0x0c == ir
.modrm
>> 4)
4695 if (i386_record_floats (gdbarch
, &ir
,
4696 I387_FTAG_REGNUM (tdep
)))
4699 else if ((0x0d == ir
.modrm
>> 4) || (0x0e == ir
.modrm
>> 4))
4701 if ((ir
.modrm
& 0x0f) <= 7)
4703 if (i386_record_floats (gdbarch
, &ir
,
4704 I387_ST0_REGNUM (tdep
) +
4710 if (i386_record_floats (gdbarch
, &ir
,
4711 I386_SAVE_FPU_REGS
))
4717 if ((0x0c == ir
.modrm
>> 4)
4718 || (0x0e == ir
.modrm
>> 4)
4719 || (0x0f == ir
.modrm
>> 4)
4720 || (0xd9 == ir
.modrm
))
4722 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
4727 if (0xe0 == ir
.modrm
)
4729 if (record_arch_list_add_reg (ir
.regcache
, I386_EAX_REGNUM
))
4732 else if ((0x0f == ir
.modrm
>> 4) || (0x0e == ir
.modrm
>> 4))
4734 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
4742 case 0xa4: /* movsS */
4744 case 0xaa: /* stosS */
4746 case 0x6c: /* insS */
4748 regcache_raw_read_unsigned (ir
.regcache
,
4749 ir
.regmap
[X86_RECORD_RECX_REGNUM
],
4755 if ((opcode
& 1) == 0)
4758 ir
.ot
= ir
.dflag
+ OT_WORD
;
4759 regcache_raw_read_unsigned (ir
.regcache
,
4760 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
4763 regcache_raw_read_unsigned (ir
.regcache
,
4764 ir
.regmap
[X86_RECORD_ES_REGNUM
],
4766 regcache_raw_read_unsigned (ir
.regcache
,
4767 ir
.regmap
[X86_RECORD_DS_REGNUM
],
4769 if (ir
.aflag
&& (es
!= ds
))
4771 /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */
4772 warning (_("Process record ignores the memory "
4773 "change of instruction at address %s "
4774 "because it can't get the value of the "
4775 "ES segment register."),
4776 paddress (gdbarch
, ir
.orig_addr
));
4780 if (record_arch_list_add_mem (addr
, 1 << ir
.ot
))
4784 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
4785 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
4786 if (opcode
== 0xa4 || opcode
== 0xa5)
4787 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
4788 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
4789 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4793 case 0xa6: /* cmpsS */
4795 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
4796 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
4797 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
4798 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
4799 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4802 case 0xac: /* lodsS */
4804 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4805 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
4806 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
4807 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
4808 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4811 case 0xae: /* scasS */
4813 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
4814 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
4815 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
4816 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4819 case 0x6e: /* outsS */
4821 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
4822 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
4823 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
4824 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4827 case 0xe4: /* port I/O */
4831 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4832 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4842 case 0xc2: /* ret im */
4843 case 0xc3: /* ret */
4844 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4845 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4848 case 0xca: /* lret im */
4849 case 0xcb: /* lret */
4850 case 0xcf: /* iret */
4851 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
4852 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4853 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4856 case 0xe8: /* call im */
4857 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4859 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4863 case 0x9a: /* lcall im */
4864 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4869 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
4870 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4874 case 0xe9: /* jmp im */
4875 case 0xea: /* ljmp im */
4876 case 0xeb: /* jmp Jb */
4877 case 0x70: /* jcc Jb */
4893 case 0x0f80: /* jcc Jv */
4911 case 0x0f90: /* setcc Gv */
4927 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4929 if (i386_record_modrm (&ir
))
4932 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rex_b
? (ir
.rm
| ir
.rex_b
)
4936 if (i386_record_lea_modrm (&ir
))
4941 case 0x0f40: /* cmov Gv, Ev */
4957 if (i386_record_modrm (&ir
))
4960 if (ir
.dflag
== OT_BYTE
)
4962 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4966 case 0x9c: /* pushf */
4967 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4968 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4970 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4974 case 0x9d: /* popf */
4975 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4976 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4979 case 0x9e: /* sahf */
4980 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4985 case 0xf5: /* cmc */
4986 case 0xf8: /* clc */
4987 case 0xf9: /* stc */
4988 case 0xfc: /* cld */
4989 case 0xfd: /* std */
4990 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4993 case 0x9f: /* lahf */
4994 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4999 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5000 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5003 /* bit operations */
5004 case 0x0fba: /* bt/bts/btr/btc Gv, im */
5005 ir
.ot
= ir
.dflag
+ OT_WORD
;
5006 if (i386_record_modrm (&ir
))
5011 opcode
= opcode
<< 8 | ir
.modrm
;
5017 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5020 if (i386_record_lea_modrm (&ir
))
5024 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5027 case 0x0fa3: /* bt Gv, Ev */
5028 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5031 case 0x0fab: /* bts */
5032 case 0x0fb3: /* btr */
5033 case 0x0fbb: /* btc */
5034 ir
.ot
= ir
.dflag
+ OT_WORD
;
5035 if (i386_record_modrm (&ir
))
5038 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5042 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
5044 regcache_raw_read_unsigned (ir
.regcache
,
5045 ir
.regmap
[ir
.reg
| rex_r
],
5050 addr64
+= ((int16_t) addr
>> 4) << 4;
5053 addr64
+= ((int32_t) addr
>> 5) << 5;
5056 addr64
+= ((int64_t) addr
>> 6) << 6;
5059 if (record_arch_list_add_mem (addr64
, 1 << ir
.ot
))
5061 if (i386_record_lea_modrm (&ir
))
5064 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5067 case 0x0fbc: /* bsf */
5068 case 0x0fbd: /* bsr */
5069 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
5070 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5074 case 0x27: /* daa */
5075 case 0x2f: /* das */
5076 case 0x37: /* aaa */
5077 case 0x3f: /* aas */
5078 case 0xd4: /* aam */
5079 case 0xd5: /* aad */
5080 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5085 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5086 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5090 case 0x90: /* nop */
5091 if (prefixes
& PREFIX_LOCK
)
5098 case 0x9b: /* fwait */
5099 if (target_read_memory (ir
.addr
, &opcode8
, 1))
5102 printf_unfiltered (_("Process record: error reading memory at "
5103 "addr 0x%s len = 1.\n"),
5104 paddress (gdbarch
, ir
.addr
));
5107 opcode
= (uint32_t) opcode8
;
5113 case 0xcc: /* int3 */
5114 printf_unfiltered (_("Process record doesn't support instruction "
5121 case 0xcd: /* int */
5125 if (target_read_memory (ir
.addr
, &interrupt
, 1))
5128 printf_unfiltered (_("Process record: error reading memory "
5129 "at addr %s len = 1.\n"),
5130 paddress (gdbarch
, ir
.addr
));
5134 if (interrupt
!= 0x80
5135 || gdbarch_tdep (gdbarch
)->i386_intx80_record
== NULL
)
5137 printf_unfiltered (_("Process record doesn't support "
5138 "instruction int 0x%02x.\n"),
5143 ret
= gdbarch_tdep (gdbarch
)->i386_intx80_record (ir
.regcache
);
5150 case 0xce: /* into */
5151 printf_unfiltered (_("Process record doesn't support "
5152 "instruction into.\n"));
5157 case 0xfa: /* cli */
5158 case 0xfb: /* sti */
5161 case 0x62: /* bound */
5162 printf_unfiltered (_("Process record doesn't support "
5163 "instruction bound.\n"));
5168 case 0x0fc8: /* bswap reg */
5176 I386_RECORD_ARCH_LIST_ADD_REG ((opcode
& 7) | ir
.rex_b
);
5179 case 0xd6: /* salc */
5180 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5185 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5186 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5189 case 0xe0: /* loopnz */
5190 case 0xe1: /* loopz */
5191 case 0xe2: /* loop */
5192 case 0xe3: /* jecxz */
5193 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5194 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5197 case 0x0f30: /* wrmsr */
5198 printf_unfiltered (_("Process record doesn't support "
5199 "instruction wrmsr.\n"));
5204 case 0x0f32: /* rdmsr */
5205 printf_unfiltered (_("Process record doesn't support "
5206 "instruction rdmsr.\n"));
5211 case 0x0f31: /* rdtsc */
5212 printf_unfiltered (_("Process record doesn't support "
5213 "instruction rdtsc.\n"));
5218 case 0x0f34: /* sysenter */
5221 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5226 if (gdbarch_tdep (gdbarch
)->i386_sysenter_record
== NULL
)
5228 printf_unfiltered (_("Process record doesn't support "
5229 "instruction sysenter.\n"));
5233 ret
= gdbarch_tdep (gdbarch
)->i386_sysenter_record (ir
.regcache
);
5239 case 0x0f35: /* sysexit */
5240 printf_unfiltered (_("Process record doesn't support "
5241 "instruction sysexit.\n"));
5246 case 0x0f05: /* syscall */
5249 if (gdbarch_tdep (gdbarch
)->i386_syscall_record
== NULL
)
5251 printf_unfiltered (_("Process record doesn't support "
5252 "instruction syscall.\n"));
5256 ret
= gdbarch_tdep (gdbarch
)->i386_syscall_record (ir
.regcache
);
5262 case 0x0f07: /* sysret */
5263 printf_unfiltered (_("Process record doesn't support "
5264 "instruction sysret.\n"));
5269 case 0x0fa2: /* cpuid */
5270 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5271 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5272 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5273 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM
);
5276 case 0xf4: /* hlt */
5277 printf_unfiltered (_("Process record doesn't support "
5278 "instruction hlt.\n"));
5284 if (i386_record_modrm (&ir
))
5291 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5295 if (i386_record_lea_modrm (&ir
))
5304 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5308 opcode
= opcode
<< 8 | ir
.modrm
;
5315 if (i386_record_modrm (&ir
))
5326 opcode
= opcode
<< 8 | ir
.modrm
;
5329 if (ir
.override
>= 0)
5331 warning (_("Process record ignores the memory "
5332 "change of instruction at "
5333 "address %s because it can't get "
5334 "the value of the segment "
5336 paddress (gdbarch
, ir
.orig_addr
));
5340 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
5342 if (record_arch_list_add_mem (addr64
, 2))
5345 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5347 if (record_arch_list_add_mem (addr64
, 8))
5352 if (record_arch_list_add_mem (addr64
, 4))
5363 case 0: /* monitor */
5366 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5370 opcode
= opcode
<< 8 | ir
.modrm
;
5378 if (ir
.override
>= 0)
5380 warning (_("Process record ignores the memory "
5381 "change of instruction at "
5382 "address %s because it can't get "
5383 "the value of the segment "
5385 paddress (gdbarch
, ir
.orig_addr
));
5391 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
5393 if (record_arch_list_add_mem (addr64
, 2))
5396 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5398 if (record_arch_list_add_mem (addr64
, 8))
5403 if (record_arch_list_add_mem (addr64
, 4))
5415 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5416 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5420 else if (ir
.rm
== 1)
5427 opcode
= opcode
<< 8 | ir
.modrm
;
5434 if (record_arch_list_add_reg (ir
.regcache
, ir
.rm
| ir
.rex_b
))
5440 if (i386_record_lea_modrm (&ir
))
5443 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5446 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5448 case 7: /* invlpg */
5451 if (ir
.rm
== 0 && ir
.regmap
[X86_RECORD_R8_REGNUM
])
5452 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM
);
5456 opcode
= opcode
<< 8 | ir
.modrm
;
5461 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5465 opcode
= opcode
<< 8 | ir
.modrm
;
5471 case 0x0f08: /* invd */
5472 case 0x0f09: /* wbinvd */
5475 case 0x63: /* arpl */
5476 if (i386_record_modrm (&ir
))
5478 if (ir
.mod
== 3 || ir
.regmap
[X86_RECORD_R8_REGNUM
])
5480 I386_RECORD_ARCH_LIST_ADD_REG (ir
.regmap
[X86_RECORD_R8_REGNUM
]
5481 ? (ir
.reg
| rex_r
) : ir
.rm
);
5485 ir
.ot
= ir
.dflag
? OT_LONG
: OT_WORD
;
5486 if (i386_record_lea_modrm (&ir
))
5489 if (!ir
.regmap
[X86_RECORD_R8_REGNUM
])
5490 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5493 case 0x0f02: /* lar */
5494 case 0x0f03: /* lsl */
5495 if (i386_record_modrm (&ir
))
5497 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
5498 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5502 if (i386_record_modrm (&ir
))
5504 if (ir
.mod
== 3 && ir
.reg
== 3)
5507 opcode
= opcode
<< 8 | ir
.modrm
;
5519 /* nop (multi byte) */
5522 case 0x0f20: /* mov reg, crN */
5523 case 0x0f22: /* mov crN, reg */
5524 if (i386_record_modrm (&ir
))
5526 if ((ir
.modrm
& 0xc0) != 0xc0)
5529 opcode
= opcode
<< 8 | ir
.modrm
;
5540 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5542 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5546 opcode
= opcode
<< 8 | ir
.modrm
;
5552 case 0x0f21: /* mov reg, drN */
5553 case 0x0f23: /* mov drN, reg */
5554 if (i386_record_modrm (&ir
))
5556 if ((ir
.modrm
& 0xc0) != 0xc0 || ir
.reg
== 4
5557 || ir
.reg
== 5 || ir
.reg
>= 8)
5560 opcode
= opcode
<< 8 | ir
.modrm
;
5564 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5566 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5569 case 0x0f06: /* clts */
5570 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5573 /* MMX/SSE/SSE2/PNI support */
5585 /* In the future, maybe still need to deal with need_dasm. */
5586 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM
);
5587 if (record_arch_list_add_end ())
5593 printf_unfiltered (_("Process record doesn't support instruction 0x%02x "
5594 "at address %s.\n"),
5595 (unsigned int) (opcode
), paddress (gdbarch
, ir
.addr
));
5599 static const int i386_record_regmap
[] =
5601 I386_EAX_REGNUM
, I386_ECX_REGNUM
, I386_EDX_REGNUM
, I386_EBX_REGNUM
,
5602 I386_ESP_REGNUM
, I386_EBP_REGNUM
, I386_ESI_REGNUM
, I386_EDI_REGNUM
,
5603 0, 0, 0, 0, 0, 0, 0, 0,
5604 I386_EIP_REGNUM
, I386_EFLAGS_REGNUM
, I386_CS_REGNUM
, I386_SS_REGNUM
,
5605 I386_DS_REGNUM
, I386_ES_REGNUM
, I386_FS_REGNUM
, I386_GS_REGNUM
5608 /* Check that the given address appears suitable for a fast
5609 tracepoint, which on x86 means that we need an instruction of at
5610 least 5 bytes, so that we can overwrite it with a 4-byte-offset
5611 jump and not have to worry about program jumps to an address in the
5612 middle of the tracepoint jump. Returns 1 if OK, and writes a size
5613 of instruction to replace, and 0 if not, plus an explanatory
5617 i386_fast_tracepoint_valid_at (struct gdbarch
*gdbarch
,
5618 CORE_ADDR addr
, int *isize
, char **msg
)
5621 static struct ui_file
*gdb_null
= NULL
;
5623 /* This is based on the target agent using a 4-byte relative jump.
5624 Alternate future possibilities include 8-byte offset for x86-84,
5625 or 3-byte jumps if the program has trampoline space close by. */
5628 /* Dummy file descriptor for the disassembler. */
5630 gdb_null
= ui_file_new ();
5632 /* Check for fit. */
5633 len
= gdb_print_insn (gdbarch
, addr
, gdb_null
, NULL
);
5636 /* Return a bit of target-specific detail to add to the caller's
5637 generic failure message. */
5639 *msg
= xstrprintf (_("; instruction is only %d bytes long, need at least %d bytes for the jump"),
5652 i386_validate_tdesc_p (struct gdbarch_tdep
*tdep
,
5653 struct tdesc_arch_data
*tdesc_data
)
5655 const struct target_desc
*tdesc
= tdep
->tdesc
;
5656 const struct tdesc_feature
*feature_core
, *feature_vector
;
5657 int i
, num_regs
, valid_p
;
5659 if (! tdesc_has_registers (tdesc
))
5662 /* Get core registers. */
5663 feature_core
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.core");
5665 /* Get SSE registers. */
5666 feature_vector
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.sse");
5668 if (feature_core
== NULL
|| feature_vector
== NULL
)
5673 num_regs
= tdep
->num_core_regs
;
5674 for (i
= 0; i
< num_regs
; i
++)
5675 valid_p
&= tdesc_numbered_register (feature_core
, tdesc_data
, i
,
5676 tdep
->register_names
[i
]);
5678 /* Need to include %mxcsr, so add one. */
5679 num_regs
+= tdep
->num_xmm_regs
+ 1;
5680 for (; i
< num_regs
; i
++)
5681 valid_p
&= tdesc_numbered_register (feature_vector
, tdesc_data
, i
,
5682 tdep
->register_names
[i
]);
5688 static struct gdbarch
*
5689 i386_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
5691 struct gdbarch_tdep
*tdep
;
5692 struct gdbarch
*gdbarch
;
5693 struct tdesc_arch_data
*tdesc_data
;
5694 const struct target_desc
*tdesc
;
5697 /* If there is already a candidate, use it. */
5698 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
5700 return arches
->gdbarch
;
5702 /* Allocate space for the new architecture. */
5703 tdep
= XCALLOC (1, struct gdbarch_tdep
);
5704 gdbarch
= gdbarch_alloc (&info
, tdep
);
5706 /* General-purpose registers. */
5707 tdep
->gregset
= NULL
;
5708 tdep
->gregset_reg_offset
= NULL
;
5709 tdep
->gregset_num_regs
= I386_NUM_GREGS
;
5710 tdep
->sizeof_gregset
= 0;
5712 /* Floating-point registers. */
5713 tdep
->fpregset
= NULL
;
5714 tdep
->sizeof_fpregset
= I387_SIZEOF_FSAVE
;
5716 /* The default settings include the FPU registers, the MMX registers
5717 and the SSE registers. This can be overridden for a specific ABI
5718 by adjusting the members `st0_regnum', `mm0_regnum' and
5719 `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers
5720 will show up in the output of "info all-registers". Ideally we
5721 should try to autodetect whether they are available, such that we
5722 can prevent "info all-registers" from displaying registers that
5725 NOTE: kevinb/2003-07-13: ... if it's a choice between printing
5726 [the SSE registers] always (even when they don't exist) or never
5727 showing them to the user (even when they do exist), I prefer the
5728 former over the latter. */
5730 tdep
->st0_regnum
= I386_ST0_REGNUM
;
5732 /* I386_NUM_XREGS includes %mxcsr, so substract one. */
5733 tdep
->num_xmm_regs
= I386_NUM_XREGS
- 1;
5735 tdep
->jb_pc_offset
= -1;
5736 tdep
->struct_return
= pcc_struct_return
;
5737 tdep
->sigtramp_start
= 0;
5738 tdep
->sigtramp_end
= 0;
5739 tdep
->sigtramp_p
= i386_sigtramp_p
;
5740 tdep
->sigcontext_addr
= NULL
;
5741 tdep
->sc_reg_offset
= NULL
;
5742 tdep
->sc_pc_offset
= -1;
5743 tdep
->sc_sp_offset
= -1;
5745 tdep
->record_regmap
= i386_record_regmap
;
5747 /* The format used for `long double' on almost all i386 targets is
5748 the i387 extended floating-point format. In fact, of all targets
5749 in the GCC 2.95 tree, only OSF/1 does it different, and insists
5750 on having a `long double' that's not `long' at all. */
5751 set_gdbarch_long_double_format (gdbarch
, floatformats_i387_ext
);
5753 /* Although the i387 extended floating-point has only 80 significant
5754 bits, a `long double' actually takes up 96, probably to enforce
5756 set_gdbarch_long_double_bit (gdbarch
, 96);
5758 /* Register numbers of various important registers. */
5759 set_gdbarch_sp_regnum (gdbarch
, I386_ESP_REGNUM
); /* %esp */
5760 set_gdbarch_pc_regnum (gdbarch
, I386_EIP_REGNUM
); /* %eip */
5761 set_gdbarch_ps_regnum (gdbarch
, I386_EFLAGS_REGNUM
); /* %eflags */
5762 set_gdbarch_fp0_regnum (gdbarch
, I386_ST0_REGNUM
); /* %st(0) */
5764 /* NOTE: kettenis/20040418: GCC does have two possible register
5765 numbering schemes on the i386: dbx and SVR4. These schemes
5766 differ in how they number %ebp, %esp, %eflags, and the
5767 floating-point registers, and are implemented by the arrays
5768 dbx_register_map[] and svr4_dbx_register_map in
5769 gcc/config/i386.c. GCC also defines a third numbering scheme in
5770 gcc/config/i386.c, which it designates as the "default" register
5771 map used in 64bit mode. This last register numbering scheme is
5772 implemented in dbx64_register_map, and is used for AMD64; see
5775 Currently, each GCC i386 target always uses the same register
5776 numbering scheme across all its supported debugging formats
5777 i.e. SDB (COFF), stabs and DWARF 2. This is because
5778 gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the
5779 DBX_REGISTER_NUMBER macro which is defined by each target's
5780 respective config header in a manner independent of the requested
5781 output debugging format.
5783 This does not match the arrangement below, which presumes that
5784 the SDB and stabs numbering schemes differ from the DWARF and
5785 DWARF 2 ones. The reason for this arrangement is that it is
5786 likely to get the numbering scheme for the target's
5787 default/native debug format right. For targets where GCC is the
5788 native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for
5789 targets where the native toolchain uses a different numbering
5790 scheme for a particular debug format (stabs-in-ELF on Solaris)
5791 the defaults below will have to be overridden, like
5792 i386_elf_init_abi() does. */
5794 /* Use the dbx register numbering scheme for stabs and COFF. */
5795 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
5796 set_gdbarch_sdb_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
5798 /* Use the SVR4 register numbering scheme for DWARF 2. */
5799 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
5801 /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to
5802 be in use on any of the supported i386 targets. */
5804 set_gdbarch_print_float_info (gdbarch
, i387_print_float_info
);
5806 set_gdbarch_get_longjmp_target (gdbarch
, i386_get_longjmp_target
);
5808 /* Call dummy code. */
5809 set_gdbarch_push_dummy_call (gdbarch
, i386_push_dummy_call
);
5811 set_gdbarch_convert_register_p (gdbarch
, i386_convert_register_p
);
5812 set_gdbarch_register_to_value (gdbarch
, i386_register_to_value
);
5813 set_gdbarch_value_to_register (gdbarch
, i386_value_to_register
);
5815 set_gdbarch_return_value (gdbarch
, i386_return_value
);
5817 set_gdbarch_skip_prologue (gdbarch
, i386_skip_prologue
);
5819 /* Stack grows downward. */
5820 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
5822 set_gdbarch_breakpoint_from_pc (gdbarch
, i386_breakpoint_from_pc
);
5823 set_gdbarch_decr_pc_after_break (gdbarch
, 1);
5824 set_gdbarch_max_insn_length (gdbarch
, I386_MAX_INSN_LEN
);
5826 set_gdbarch_frame_args_skip (gdbarch
, 8);
5828 set_gdbarch_print_insn (gdbarch
, i386_print_insn
);
5830 set_gdbarch_dummy_id (gdbarch
, i386_dummy_id
);
5832 set_gdbarch_unwind_pc (gdbarch
, i386_unwind_pc
);
5834 /* Add the i386 register groups. */
5835 i386_add_reggroups (gdbarch
);
5836 tdep
->register_reggroup_p
= i386_register_reggroup_p
;
5838 /* Helper for function argument information. */
5839 set_gdbarch_fetch_pointer_argument (gdbarch
, i386_fetch_pointer_argument
);
5841 /* Hook the function epilogue frame unwinder. This unwinder is
5842 appended to the list first, so that it supercedes the Dwarf
5843 unwinder in function epilogues (where the Dwarf unwinder
5844 currently fails). */
5845 frame_unwind_append_unwinder (gdbarch
, &i386_epilogue_frame_unwind
);
5847 /* Hook in the DWARF CFI frame unwinder. This unwinder is appended
5848 to the list before the prologue-based unwinders, so that Dwarf
5849 CFI info will be used if it is available. */
5850 dwarf2_append_unwinders (gdbarch
);
5852 frame_base_set_default (gdbarch
, &i386_frame_base
);
5854 /* Pseudo registers may be changed by amd64_init_abi. */
5855 set_gdbarch_pseudo_register_read (gdbarch
, i386_pseudo_register_read
);
5856 set_gdbarch_pseudo_register_write (gdbarch
, i386_pseudo_register_write
);
5858 set_tdesc_pseudo_register_type (gdbarch
, i386_pseudo_register_type
);
5859 set_tdesc_pseudo_register_name (gdbarch
, i386_pseudo_register_name
);
5861 /* The default ABI includes general-purpose registers,
5862 floating-point registers, and the SSE registers. */
5863 set_gdbarch_num_regs (gdbarch
, I386_SSE_NUM_REGS
);
5865 /* Get the x86 target description from INFO. */
5866 tdesc
= info
.target_desc
;
5867 if (! tdesc_has_registers (tdesc
))
5869 tdep
->tdesc
= tdesc
;
5871 tdep
->num_core_regs
= I386_NUM_GREGS
+ I387_NUM_REGS
;
5872 tdep
->register_names
= i386_register_names
;
5874 tdep
->num_byte_regs
= 8;
5875 tdep
->num_word_regs
= 8;
5876 tdep
->num_dword_regs
= 0;
5877 tdep
->num_mmx_regs
= 8;
5879 tdesc_data
= tdesc_data_alloc ();
5881 /* Hook in ABI-specific overrides, if they have been registered. */
5882 info
.tdep_info
= (void *) tdesc_data
;
5883 gdbarch_init_osabi (info
, gdbarch
);
5885 /* Wire in pseudo registers. Number of pseudo registers may be
5887 set_gdbarch_num_pseudo_regs (gdbarch
, (tdep
->num_byte_regs
5888 + tdep
->num_word_regs
5889 + tdep
->num_dword_regs
5890 + tdep
->num_mmx_regs
));
5892 /* Target description may be changed. */
5893 tdesc
= tdep
->tdesc
;
5895 if (!i386_validate_tdesc_p (tdep
, tdesc_data
))
5897 tdesc_data_cleanup (tdesc_data
);
5899 gdbarch_free (gdbarch
);
5903 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
5905 /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */
5906 set_gdbarch_register_reggroup_p (gdbarch
, tdep
->register_reggroup_p
);
5908 /* Make %al the first pseudo-register. */
5909 tdep
->al_regnum
= gdbarch_num_regs (gdbarch
);
5910 tdep
->ax_regnum
= tdep
->al_regnum
+ tdep
->num_byte_regs
;
5912 mm0_regnum
= tdep
->ax_regnum
+ tdep
->num_word_regs
;
5913 if (tdep
->num_dword_regs
)
5915 /* Support dword pseudo-registesr if it hasn't been disabled, */
5916 tdep
->eax_regnum
= mm0_regnum
;
5917 mm0_regnum
= tdep
->eax_regnum
+ tdep
->num_dword_regs
;
5920 tdep
->eax_regnum
= -1;
5922 if (tdep
->num_mmx_regs
!= 0)
5924 /* Support MMX pseudo-registesr if MMX hasn't been disabled, */
5925 tdep
->mm0_regnum
= mm0_regnum
;
5928 tdep
->mm0_regnum
= -1;
5930 /* Hook in the legacy prologue-based unwinders last (fallback). */
5931 frame_unwind_append_unwinder (gdbarch
, &i386_sigtramp_frame_unwind
);
5932 frame_unwind_append_unwinder (gdbarch
, &i386_frame_unwind
);
5934 /* If we have a register mapping, enable the generic core file
5935 support, unless it has already been enabled. */
5936 if (tdep
->gregset_reg_offset
5937 && !gdbarch_regset_from_core_section_p (gdbarch
))
5938 set_gdbarch_regset_from_core_section (gdbarch
,
5939 i386_regset_from_core_section
);
5941 set_gdbarch_skip_permanent_breakpoint (gdbarch
,
5942 i386_skip_permanent_breakpoint
);
5944 set_gdbarch_fast_tracepoint_valid_at (gdbarch
,
5945 i386_fast_tracepoint_valid_at
);
5950 static enum gdb_osabi
5951 i386_coff_osabi_sniffer (bfd
*abfd
)
5953 if (strcmp (bfd_get_target (abfd
), "coff-go32-exe") == 0
5954 || strcmp (bfd_get_target (abfd
), "coff-go32") == 0)
5955 return GDB_OSABI_GO32
;
5957 return GDB_OSABI_UNKNOWN
;
5961 /* Provide a prototype to silence -Wmissing-prototypes. */
5962 void _initialize_i386_tdep (void);
5965 _initialize_i386_tdep (void)
5967 register_gdbarch_init (bfd_arch_i386
, i386_gdbarch_init
);
5969 /* Add the variable that controls the disassembly flavor. */
5970 add_setshow_enum_cmd ("disassembly-flavor", no_class
, valid_flavors
,
5971 &disassembly_flavor
, _("\
5972 Set the disassembly flavor."), _("\
5973 Show the disassembly flavor."), _("\
5974 The valid values are \"att\" and \"intel\", and the default value is \"att\"."),
5976 NULL
, /* FIXME: i18n: */
5977 &setlist
, &showlist
);
5979 /* Add the variable that controls the convention for returning
5981 add_setshow_enum_cmd ("struct-convention", no_class
, valid_conventions
,
5982 &struct_convention
, _("\
5983 Set the convention for returning small structs."), _("\
5984 Show the convention for returning small structs."), _("\
5985 Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\
5988 NULL
, /* FIXME: i18n: */
5989 &setlist
, &showlist
);
5991 gdbarch_register_osabi_sniffer (bfd_arch_i386
, bfd_target_coff_flavour
,
5992 i386_coff_osabi_sniffer
);
5994 gdbarch_register_osabi (bfd_arch_i386
, 0, GDB_OSABI_SVR4
,
5995 i386_svr4_init_abi
);
5996 gdbarch_register_osabi (bfd_arch_i386
, 0, GDB_OSABI_GO32
,
5997 i386_go32_init_abi
);
5999 /* Initialize the i386-specific register groups. */
6000 i386_init_reggroups ();
6002 /* Initialize the standard target descriptions. */
6003 initialize_tdesc_i386 ();
6005 /* Tell remote stub that we support XML target description. */
6006 register_remote_support_xml ("i386");