1 /* Intel 386 target-dependent stuff.
3 Copyright (C) 1988-2018 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "opcode/i386.h"
22 #include "arch-utils.h"
24 #include "dummy-frame.h"
25 #include "dwarf2-frame.h"
27 #include "frame-base.h"
28 #include "frame-unwind.h"
37 #include "reggroups.h"
42 #include "target-float.h"
47 #include "i386-tdep.h"
48 #include "i387-tdep.h"
49 #include "x86-xstate.h"
53 #include "record-full.h"
54 #include "target-descriptions.h"
55 #include "arch/i386.h"
60 #include "stap-probe.h"
61 #include "user-regs.h"
62 #include "cli/cli-utils.h"
63 #include "expression.h"
64 #include "parser-defs.h"
70 static const char *i386_register_names
[] =
72 "eax", "ecx", "edx", "ebx",
73 "esp", "ebp", "esi", "edi",
74 "eip", "eflags", "cs", "ss",
75 "ds", "es", "fs", "gs",
76 "st0", "st1", "st2", "st3",
77 "st4", "st5", "st6", "st7",
78 "fctrl", "fstat", "ftag", "fiseg",
79 "fioff", "foseg", "fooff", "fop",
80 "xmm0", "xmm1", "xmm2", "xmm3",
81 "xmm4", "xmm5", "xmm6", "xmm7",
85 static const char *i386_zmm_names
[] =
87 "zmm0", "zmm1", "zmm2", "zmm3",
88 "zmm4", "zmm5", "zmm6", "zmm7"
91 static const char *i386_zmmh_names
[] =
93 "zmm0h", "zmm1h", "zmm2h", "zmm3h",
94 "zmm4h", "zmm5h", "zmm6h", "zmm7h"
97 static const char *i386_k_names
[] =
99 "k0", "k1", "k2", "k3",
100 "k4", "k5", "k6", "k7"
103 static const char *i386_ymm_names
[] =
105 "ymm0", "ymm1", "ymm2", "ymm3",
106 "ymm4", "ymm5", "ymm6", "ymm7",
109 static const char *i386_ymmh_names
[] =
111 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
112 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
115 static const char *i386_mpx_names
[] =
117 "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus"
120 static const char* i386_pkeys_names
[] =
125 /* Register names for MPX pseudo-registers. */
127 static const char *i386_bnd_names
[] =
129 "bnd0", "bnd1", "bnd2", "bnd3"
132 /* Register names for MMX pseudo-registers. */
134 static const char *i386_mmx_names
[] =
136 "mm0", "mm1", "mm2", "mm3",
137 "mm4", "mm5", "mm6", "mm7"
140 /* Register names for byte pseudo-registers. */
142 static const char *i386_byte_names
[] =
144 "al", "cl", "dl", "bl",
145 "ah", "ch", "dh", "bh"
148 /* Register names for word pseudo-registers. */
150 static const char *i386_word_names
[] =
152 "ax", "cx", "dx", "bx",
156 /* Constant used for reading/writing pseudo registers. In 64-bit mode, we have
157 16 lower ZMM regs that extend corresponding xmm/ymm registers. In addition,
158 we have 16 upper ZMM regs that have to be handled differently. */
160 const int num_lower_zmm_regs
= 16;
165 i386_mmx_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
167 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
168 int mm0_regnum
= tdep
->mm0_regnum
;
173 regnum
-= mm0_regnum
;
174 return regnum
>= 0 && regnum
< tdep
->num_mmx_regs
;
180 i386_byte_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
182 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
184 regnum
-= tdep
->al_regnum
;
185 return regnum
>= 0 && regnum
< tdep
->num_byte_regs
;
191 i386_word_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
193 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
195 regnum
-= tdep
->ax_regnum
;
196 return regnum
>= 0 && regnum
< tdep
->num_word_regs
;
199 /* Dword register? */
202 i386_dword_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
204 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
205 int eax_regnum
= tdep
->eax_regnum
;
210 regnum
-= eax_regnum
;
211 return regnum
>= 0 && regnum
< tdep
->num_dword_regs
;
214 /* AVX512 register? */
217 i386_zmmh_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
219 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
220 int zmm0h_regnum
= tdep
->zmm0h_regnum
;
222 if (zmm0h_regnum
< 0)
225 regnum
-= zmm0h_regnum
;
226 return regnum
>= 0 && regnum
< tdep
->num_zmm_regs
;
230 i386_zmm_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
232 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
233 int zmm0_regnum
= tdep
->zmm0_regnum
;
238 regnum
-= zmm0_regnum
;
239 return regnum
>= 0 && regnum
< tdep
->num_zmm_regs
;
243 i386_k_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
245 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
246 int k0_regnum
= tdep
->k0_regnum
;
252 return regnum
>= 0 && regnum
< I387_NUM_K_REGS
;
256 i386_ymmh_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
258 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
259 int ymm0h_regnum
= tdep
->ymm0h_regnum
;
261 if (ymm0h_regnum
< 0)
264 regnum
-= ymm0h_regnum
;
265 return regnum
>= 0 && regnum
< tdep
->num_ymm_regs
;
271 i386_ymm_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
273 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
274 int ymm0_regnum
= tdep
->ymm0_regnum
;
279 regnum
-= ymm0_regnum
;
280 return regnum
>= 0 && regnum
< tdep
->num_ymm_regs
;
284 i386_ymmh_avx512_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
286 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
287 int ymm16h_regnum
= tdep
->ymm16h_regnum
;
289 if (ymm16h_regnum
< 0)
292 regnum
-= ymm16h_regnum
;
293 return regnum
>= 0 && regnum
< tdep
->num_ymm_avx512_regs
;
297 i386_ymm_avx512_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
299 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
300 int ymm16_regnum
= tdep
->ymm16_regnum
;
302 if (ymm16_regnum
< 0)
305 regnum
-= ymm16_regnum
;
306 return regnum
>= 0 && regnum
< tdep
->num_ymm_avx512_regs
;
312 i386_bnd_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
314 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
315 int bnd0_regnum
= tdep
->bnd0_regnum
;
320 regnum
-= bnd0_regnum
;
321 return regnum
>= 0 && regnum
< I387_NUM_BND_REGS
;
327 i386_xmm_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
329 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
330 int num_xmm_regs
= I387_NUM_XMM_REGS (tdep
);
332 if (num_xmm_regs
== 0)
335 regnum
-= I387_XMM0_REGNUM (tdep
);
336 return regnum
>= 0 && regnum
< num_xmm_regs
;
339 /* XMM_512 register? */
342 i386_xmm_avx512_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
344 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
345 int num_xmm_avx512_regs
= I387_NUM_XMM_AVX512_REGS (tdep
);
347 if (num_xmm_avx512_regs
== 0)
350 regnum
-= I387_XMM16_REGNUM (tdep
);
351 return regnum
>= 0 && regnum
< num_xmm_avx512_regs
;
355 i386_mxcsr_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
357 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
359 if (I387_NUM_XMM_REGS (tdep
) == 0)
362 return (regnum
== I387_MXCSR_REGNUM (tdep
));
368 i386_fp_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
370 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
372 if (I387_ST0_REGNUM (tdep
) < 0)
375 return (I387_ST0_REGNUM (tdep
) <= regnum
376 && regnum
< I387_FCTRL_REGNUM (tdep
));
380 i386_fpc_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
382 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
384 if (I387_ST0_REGNUM (tdep
) < 0)
387 return (I387_FCTRL_REGNUM (tdep
) <= regnum
388 && regnum
< I387_XMM0_REGNUM (tdep
));
391 /* BNDr (raw) register? */
394 i386_bndr_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
396 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
398 if (I387_BND0R_REGNUM (tdep
) < 0)
401 regnum
-= tdep
->bnd0r_regnum
;
402 return regnum
>= 0 && regnum
< I387_NUM_BND_REGS
;
405 /* BND control register? */
408 i386_mpx_ctrl_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
410 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
412 if (I387_BNDCFGU_REGNUM (tdep
) < 0)
415 regnum
-= I387_BNDCFGU_REGNUM (tdep
);
416 return regnum
>= 0 && regnum
< I387_NUM_MPX_CTRL_REGS
;
422 i386_pkru_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
424 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
425 int pkru_regnum
= tdep
->pkru_regnum
;
430 regnum
-= pkru_regnum
;
431 return regnum
>= 0 && regnum
< I387_NUM_PKEYS_REGS
;
434 /* Return the name of register REGNUM, or the empty string if it is
435 an anonymous register. */
438 i386_register_name (struct gdbarch
*gdbarch
, int regnum
)
440 /* Hide the upper YMM registers. */
441 if (i386_ymmh_regnum_p (gdbarch
, regnum
))
444 /* Hide the upper YMM16-31 registers. */
445 if (i386_ymmh_avx512_regnum_p (gdbarch
, regnum
))
448 /* Hide the upper ZMM registers. */
449 if (i386_zmmh_regnum_p (gdbarch
, regnum
))
452 return tdesc_register_name (gdbarch
, regnum
);
455 /* Return the name of register REGNUM. */
458 i386_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
460 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
461 if (i386_bnd_regnum_p (gdbarch
, regnum
))
462 return i386_bnd_names
[regnum
- tdep
->bnd0_regnum
];
463 if (i386_mmx_regnum_p (gdbarch
, regnum
))
464 return i386_mmx_names
[regnum
- I387_MM0_REGNUM (tdep
)];
465 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
466 return i386_ymm_names
[regnum
- tdep
->ymm0_regnum
];
467 else if (i386_zmm_regnum_p (gdbarch
, regnum
))
468 return i386_zmm_names
[regnum
- tdep
->zmm0_regnum
];
469 else if (i386_byte_regnum_p (gdbarch
, regnum
))
470 return i386_byte_names
[regnum
- tdep
->al_regnum
];
471 else if (i386_word_regnum_p (gdbarch
, regnum
))
472 return i386_word_names
[regnum
- tdep
->ax_regnum
];
474 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
477 /* Convert a dbx register number REG to the appropriate register
478 number used by GDB. */
481 i386_dbx_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
483 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
485 /* This implements what GCC calls the "default" register map
486 (dbx_register_map[]). */
488 if (reg
>= 0 && reg
<= 7)
490 /* General-purpose registers. The debug info calls %ebp
491 register 4, and %esp register 5. */
498 else if (reg
>= 12 && reg
<= 19)
500 /* Floating-point registers. */
501 return reg
- 12 + I387_ST0_REGNUM (tdep
);
503 else if (reg
>= 21 && reg
<= 28)
506 int ymm0_regnum
= tdep
->ymm0_regnum
;
509 && i386_xmm_regnum_p (gdbarch
, reg
))
510 return reg
- 21 + ymm0_regnum
;
512 return reg
- 21 + I387_XMM0_REGNUM (tdep
);
514 else if (reg
>= 29 && reg
<= 36)
517 return reg
- 29 + I387_MM0_REGNUM (tdep
);
520 /* This will hopefully provoke a warning. */
521 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
524 /* Convert SVR4 DWARF register number REG to the appropriate register number
528 i386_svr4_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
530 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
532 /* This implements the GCC register map that tries to be compatible
533 with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */
535 /* The SVR4 register numbering includes %eip and %eflags, and
536 numbers the floating point registers differently. */
537 if (reg
>= 0 && reg
<= 9)
539 /* General-purpose registers. */
542 else if (reg
>= 11 && reg
<= 18)
544 /* Floating-point registers. */
545 return reg
- 11 + I387_ST0_REGNUM (tdep
);
547 else if (reg
>= 21 && reg
<= 36)
549 /* The SSE and MMX registers have the same numbers as with dbx. */
550 return i386_dbx_reg_to_regnum (gdbarch
, reg
);
555 case 37: return I387_FCTRL_REGNUM (tdep
);
556 case 38: return I387_FSTAT_REGNUM (tdep
);
557 case 39: return I387_MXCSR_REGNUM (tdep
);
558 case 40: return I386_ES_REGNUM
;
559 case 41: return I386_CS_REGNUM
;
560 case 42: return I386_SS_REGNUM
;
561 case 43: return I386_DS_REGNUM
;
562 case 44: return I386_FS_REGNUM
;
563 case 45: return I386_GS_REGNUM
;
569 /* Wrapper on i386_svr4_dwarf_reg_to_regnum to return
570 num_regs + num_pseudo_regs for other debug formats. */
573 i386_svr4_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
575 int regnum
= i386_svr4_dwarf_reg_to_regnum (gdbarch
, reg
);
578 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
584 /* This is the variable that is set with "set disassembly-flavor", and
585 its legitimate values. */
586 static const char att_flavor
[] = "att";
587 static const char intel_flavor
[] = "intel";
588 static const char *const valid_flavors
[] =
594 static const char *disassembly_flavor
= att_flavor
;
597 /* Use the program counter to determine the contents and size of a
598 breakpoint instruction. Return a pointer to a string of bytes that
599 encode a breakpoint instruction, store the length of the string in
600 *LEN and optionally adjust *PC to point to the correct memory
601 location for inserting the breakpoint.
603 On the i386 we have a single breakpoint that fits in a single byte
604 and can be inserted anywhere.
606 This function is 64-bit safe. */
608 constexpr gdb_byte i386_break_insn
[] = { 0xcc }; /* int 3 */
610 typedef BP_MANIPULATION (i386_break_insn
) i386_breakpoint
;
613 /* Displaced instruction handling. */
615 /* Skip the legacy instruction prefixes in INSN.
616 Not all prefixes are valid for any particular insn
617 but we needn't care, the insn will fault if it's invalid.
618 The result is a pointer to the first opcode byte,
619 or NULL if we run off the end of the buffer. */
622 i386_skip_prefixes (gdb_byte
*insn
, size_t max_len
)
624 gdb_byte
*end
= insn
+ max_len
;
630 case DATA_PREFIX_OPCODE
:
631 case ADDR_PREFIX_OPCODE
:
632 case CS_PREFIX_OPCODE
:
633 case DS_PREFIX_OPCODE
:
634 case ES_PREFIX_OPCODE
:
635 case FS_PREFIX_OPCODE
:
636 case GS_PREFIX_OPCODE
:
637 case SS_PREFIX_OPCODE
:
638 case LOCK_PREFIX_OPCODE
:
639 case REPE_PREFIX_OPCODE
:
640 case REPNE_PREFIX_OPCODE
:
652 i386_absolute_jmp_p (const gdb_byte
*insn
)
654 /* jmp far (absolute address in operand). */
660 /* jump near, absolute indirect (/4). */
661 if ((insn
[1] & 0x38) == 0x20)
664 /* jump far, absolute indirect (/5). */
665 if ((insn
[1] & 0x38) == 0x28)
672 /* Return non-zero if INSN is a jump, zero otherwise. */
675 i386_jmp_p (const gdb_byte
*insn
)
677 /* jump short, relative. */
681 /* jump near, relative. */
685 return i386_absolute_jmp_p (insn
);
689 i386_absolute_call_p (const gdb_byte
*insn
)
691 /* call far, absolute. */
697 /* Call near, absolute indirect (/2). */
698 if ((insn
[1] & 0x38) == 0x10)
701 /* Call far, absolute indirect (/3). */
702 if ((insn
[1] & 0x38) == 0x18)
710 i386_ret_p (const gdb_byte
*insn
)
714 case 0xc2: /* ret near, pop N bytes. */
715 case 0xc3: /* ret near */
716 case 0xca: /* ret far, pop N bytes. */
717 case 0xcb: /* ret far */
718 case 0xcf: /* iret */
727 i386_call_p (const gdb_byte
*insn
)
729 if (i386_absolute_call_p (insn
))
732 /* call near, relative. */
739 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
740 length in bytes. Otherwise, return zero. */
743 i386_syscall_p (const gdb_byte
*insn
, int *lengthp
)
745 /* Is it 'int $0x80'? */
746 if ((insn
[0] == 0xcd && insn
[1] == 0x80)
747 /* Or is it 'sysenter'? */
748 || (insn
[0] == 0x0f && insn
[1] == 0x34)
749 /* Or is it 'syscall'? */
750 || (insn
[0] == 0x0f && insn
[1] == 0x05))
759 /* The gdbarch insn_is_call method. */
762 i386_insn_is_call (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
764 gdb_byte buf
[I386_MAX_INSN_LEN
], *insn
;
766 read_code (addr
, buf
, I386_MAX_INSN_LEN
);
767 insn
= i386_skip_prefixes (buf
, I386_MAX_INSN_LEN
);
769 return i386_call_p (insn
);
772 /* The gdbarch insn_is_ret method. */
775 i386_insn_is_ret (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
777 gdb_byte buf
[I386_MAX_INSN_LEN
], *insn
;
779 read_code (addr
, buf
, I386_MAX_INSN_LEN
);
780 insn
= i386_skip_prefixes (buf
, I386_MAX_INSN_LEN
);
782 return i386_ret_p (insn
);
785 /* The gdbarch insn_is_jump method. */
788 i386_insn_is_jump (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
790 gdb_byte buf
[I386_MAX_INSN_LEN
], *insn
;
792 read_code (addr
, buf
, I386_MAX_INSN_LEN
);
793 insn
= i386_skip_prefixes (buf
, I386_MAX_INSN_LEN
);
795 return i386_jmp_p (insn
);
798 /* Some kernels may run one past a syscall insn, so we have to cope. */
800 struct displaced_step_closure
*
801 i386_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
802 CORE_ADDR from
, CORE_ADDR to
,
803 struct regcache
*regs
)
805 size_t len
= gdbarch_max_insn_length (gdbarch
);
806 i386_displaced_step_closure
*closure
= new i386_displaced_step_closure (len
);
807 gdb_byte
*buf
= closure
->buf
.data ();
809 read_memory (from
, buf
, len
);
811 /* GDB may get control back after the insn after the syscall.
812 Presumably this is a kernel bug.
813 If this is a syscall, make sure there's a nop afterwards. */
818 insn
= i386_skip_prefixes (buf
, len
);
819 if (insn
!= NULL
&& i386_syscall_p (insn
, &syscall_length
))
820 insn
[syscall_length
] = NOP_OPCODE
;
823 write_memory (to
, buf
, len
);
827 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
828 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
829 displaced_step_dump_bytes (gdb_stdlog
, buf
, len
);
835 /* Fix up the state of registers and memory after having single-stepped
836 a displaced instruction. */
839 i386_displaced_step_fixup (struct gdbarch
*gdbarch
,
840 struct displaced_step_closure
*closure_
,
841 CORE_ADDR from
, CORE_ADDR to
,
842 struct regcache
*regs
)
844 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
846 /* The offset we applied to the instruction's address.
847 This could well be negative (when viewed as a signed 32-bit
848 value), but ULONGEST won't reflect that, so take care when
850 ULONGEST insn_offset
= to
- from
;
852 i386_displaced_step_closure
*closure
853 = (i386_displaced_step_closure
*) closure_
;
854 gdb_byte
*insn
= closure
->buf
.data ();
855 /* The start of the insn, needed in case we see some prefixes. */
856 gdb_byte
*insn_start
= insn
;
859 fprintf_unfiltered (gdb_stdlog
,
860 "displaced: fixup (%s, %s), "
861 "insn = 0x%02x 0x%02x ...\n",
862 paddress (gdbarch
, from
), paddress (gdbarch
, to
),
865 /* The list of issues to contend with here is taken from
866 resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20.
867 Yay for Free Software! */
869 /* Relocate the %eip, if necessary. */
871 /* The instruction recognizers we use assume any leading prefixes
872 have been skipped. */
874 /* This is the size of the buffer in closure. */
875 size_t max_insn_len
= gdbarch_max_insn_length (gdbarch
);
876 gdb_byte
*opcode
= i386_skip_prefixes (insn
, max_insn_len
);
877 /* If there are too many prefixes, just ignore the insn.
878 It will fault when run. */
883 /* Except in the case of absolute or indirect jump or call
884 instructions, or a return instruction, the new eip is relative to
885 the displaced instruction; make it relative. Well, signal
886 handler returns don't need relocation either, but we use the
887 value of %eip to recognize those; see below. */
888 if (! i386_absolute_jmp_p (insn
)
889 && ! i386_absolute_call_p (insn
)
890 && ! i386_ret_p (insn
))
895 regcache_cooked_read_unsigned (regs
, I386_EIP_REGNUM
, &orig_eip
);
897 /* A signal trampoline system call changes the %eip, resuming
898 execution of the main program after the signal handler has
899 returned. That makes them like 'return' instructions; we
900 shouldn't relocate %eip.
902 But most system calls don't, and we do need to relocate %eip.
904 Our heuristic for distinguishing these cases: if stepping
905 over the system call instruction left control directly after
906 the instruction, the we relocate --- control almost certainly
907 doesn't belong in the displaced copy. Otherwise, we assume
908 the instruction has put control where it belongs, and leave
909 it unrelocated. Goodness help us if there are PC-relative
911 if (i386_syscall_p (insn
, &insn_len
)
912 && orig_eip
!= to
+ (insn
- insn_start
) + insn_len
913 /* GDB can get control back after the insn after the syscall.
914 Presumably this is a kernel bug.
915 i386_displaced_step_copy_insn ensures its a nop,
916 we add one to the length for it. */
917 && orig_eip
!= to
+ (insn
- insn_start
) + insn_len
+ 1)
920 fprintf_unfiltered (gdb_stdlog
,
921 "displaced: syscall changed %%eip; "
926 ULONGEST eip
= (orig_eip
- insn_offset
) & 0xffffffffUL
;
928 /* If we just stepped over a breakpoint insn, we don't backup
929 the pc on purpose; this is to match behaviour without
932 regcache_cooked_write_unsigned (regs
, I386_EIP_REGNUM
, eip
);
935 fprintf_unfiltered (gdb_stdlog
,
937 "relocated %%eip from %s to %s\n",
938 paddress (gdbarch
, orig_eip
),
939 paddress (gdbarch
, eip
));
943 /* If the instruction was PUSHFL, then the TF bit will be set in the
944 pushed value, and should be cleared. We'll leave this for later,
945 since GDB already messes up the TF flag when stepping over a
948 /* If the instruction was a call, the return address now atop the
949 stack is the address following the copied instruction. We need
950 to make it the address following the original instruction. */
951 if (i386_call_p (insn
))
955 const ULONGEST retaddr_len
= 4;
957 regcache_cooked_read_unsigned (regs
, I386_ESP_REGNUM
, &esp
);
958 retaddr
= read_memory_unsigned_integer (esp
, retaddr_len
, byte_order
);
959 retaddr
= (retaddr
- insn_offset
) & 0xffffffffUL
;
960 write_memory_unsigned_integer (esp
, retaddr_len
, byte_order
, retaddr
);
963 fprintf_unfiltered (gdb_stdlog
,
964 "displaced: relocated return addr at %s to %s\n",
965 paddress (gdbarch
, esp
),
966 paddress (gdbarch
, retaddr
));
971 append_insns (CORE_ADDR
*to
, ULONGEST len
, const gdb_byte
*buf
)
973 target_write_memory (*to
, buf
, len
);
978 i386_relocate_instruction (struct gdbarch
*gdbarch
,
979 CORE_ADDR
*to
, CORE_ADDR oldloc
)
981 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
982 gdb_byte buf
[I386_MAX_INSN_LEN
];
983 int offset
= 0, rel32
, newrel
;
985 gdb_byte
*insn
= buf
;
987 read_memory (oldloc
, buf
, I386_MAX_INSN_LEN
);
989 insn_length
= gdb_buffered_insn_length (gdbarch
, insn
,
990 I386_MAX_INSN_LEN
, oldloc
);
992 /* Get past the prefixes. */
993 insn
= i386_skip_prefixes (insn
, I386_MAX_INSN_LEN
);
995 /* Adjust calls with 32-bit relative addresses as push/jump, with
996 the address pushed being the location where the original call in
997 the user program would return to. */
1000 gdb_byte push_buf
[16];
1001 unsigned int ret_addr
;
1003 /* Where "ret" in the original code will return to. */
1004 ret_addr
= oldloc
+ insn_length
;
1005 push_buf
[0] = 0x68; /* pushq $... */
1006 store_unsigned_integer (&push_buf
[1], 4, byte_order
, ret_addr
);
1007 /* Push the push. */
1008 append_insns (to
, 5, push_buf
);
1010 /* Convert the relative call to a relative jump. */
1013 /* Adjust the destination offset. */
1014 rel32
= extract_signed_integer (insn
+ 1, 4, byte_order
);
1015 newrel
= (oldloc
- *to
) + rel32
;
1016 store_signed_integer (insn
+ 1, 4, byte_order
, newrel
);
1018 if (debug_displaced
)
1019 fprintf_unfiltered (gdb_stdlog
,
1020 "Adjusted insn rel32=%s at %s to"
1021 " rel32=%s at %s\n",
1022 hex_string (rel32
), paddress (gdbarch
, oldloc
),
1023 hex_string (newrel
), paddress (gdbarch
, *to
));
1025 /* Write the adjusted jump into its displaced location. */
1026 append_insns (to
, 5, insn
);
1030 /* Adjust jumps with 32-bit relative addresses. Calls are already
1032 if (insn
[0] == 0xe9)
1034 /* Adjust conditional jumps. */
1035 else if (insn
[0] == 0x0f && (insn
[1] & 0xf0) == 0x80)
1040 rel32
= extract_signed_integer (insn
+ offset
, 4, byte_order
);
1041 newrel
= (oldloc
- *to
) + rel32
;
1042 store_signed_integer (insn
+ offset
, 4, byte_order
, newrel
);
1043 if (debug_displaced
)
1044 fprintf_unfiltered (gdb_stdlog
,
1045 "Adjusted insn rel32=%s at %s to"
1046 " rel32=%s at %s\n",
1047 hex_string (rel32
), paddress (gdbarch
, oldloc
),
1048 hex_string (newrel
), paddress (gdbarch
, *to
));
1051 /* Write the adjusted instructions into their displaced
1053 append_insns (to
, insn_length
, buf
);
1057 #ifdef I386_REGNO_TO_SYMMETRY
1058 #error "The Sequent Symmetry is no longer supported."
1061 /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi
1062 and %esp "belong" to the calling function. Therefore these
1063 registers should be saved if they're going to be modified. */
1065 /* The maximum number of saved registers. This should include all
1066 registers mentioned above, and %eip. */
1067 #define I386_NUM_SAVED_REGS I386_NUM_GREGS
1069 struct i386_frame_cache
1077 /* Saved registers. */
1078 CORE_ADDR saved_regs
[I386_NUM_SAVED_REGS
];
1083 /* Stack space reserved for local variables. */
1087 /* Allocate and initialize a frame cache. */
1089 static struct i386_frame_cache
*
1090 i386_alloc_frame_cache (void)
1092 struct i386_frame_cache
*cache
;
1095 cache
= FRAME_OBSTACK_ZALLOC (struct i386_frame_cache
);
1100 cache
->sp_offset
= -4;
1103 /* Saved registers. We initialize these to -1 since zero is a valid
1104 offset (that's where %ebp is supposed to be stored). */
1105 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
1106 cache
->saved_regs
[i
] = -1;
1107 cache
->saved_sp
= 0;
1108 cache
->saved_sp_reg
= -1;
1109 cache
->pc_in_eax
= 0;
1111 /* Frameless until proven otherwise. */
1117 /* If the instruction at PC is a jump, return the address of its
1118 target. Otherwise, return PC. */
1121 i386_follow_jump (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1123 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1128 if (target_read_code (pc
, &op
, 1))
1135 op
= read_code_unsigned_integer (pc
+ 1, 1, byte_order
);
1141 /* Relative jump: if data16 == 0, disp32, else disp16. */
1144 delta
= read_memory_integer (pc
+ 2, 2, byte_order
);
1146 /* Include the size of the jmp instruction (including the
1152 delta
= read_memory_integer (pc
+ 1, 4, byte_order
);
1154 /* Include the size of the jmp instruction. */
1159 /* Relative jump, disp8 (ignore data16). */
1160 delta
= read_memory_integer (pc
+ data16
+ 1, 1, byte_order
);
1162 delta
+= data16
+ 2;
1169 /* Check whether PC points at a prologue for a function returning a
1170 structure or union. If so, it updates CACHE and returns the
1171 address of the first instruction after the code sequence that
1172 removes the "hidden" argument from the stack or CURRENT_PC,
1173 whichever is smaller. Otherwise, return PC. */
1176 i386_analyze_struct_return (CORE_ADDR pc
, CORE_ADDR current_pc
,
1177 struct i386_frame_cache
*cache
)
1179 /* Functions that return a structure or union start with:
1182 xchgl %eax, (%esp) 0x87 0x04 0x24
1183 or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00
1185 (the System V compiler puts out the second `xchg' instruction,
1186 and the assembler doesn't try to optimize it, so the 'sib' form
1187 gets generated). This sequence is used to get the address of the
1188 return buffer for a function that returns a structure. */
1189 static gdb_byte proto1
[3] = { 0x87, 0x04, 0x24 };
1190 static gdb_byte proto2
[4] = { 0x87, 0x44, 0x24, 0x00 };
1194 if (current_pc
<= pc
)
1197 if (target_read_code (pc
, &op
, 1))
1200 if (op
!= 0x58) /* popl %eax */
1203 if (target_read_code (pc
+ 1, buf
, 4))
1206 if (memcmp (buf
, proto1
, 3) != 0 && memcmp (buf
, proto2
, 4) != 0)
1209 if (current_pc
== pc
)
1211 cache
->sp_offset
+= 4;
1215 if (current_pc
== pc
+ 1)
1217 cache
->pc_in_eax
= 1;
1221 if (buf
[1] == proto1
[1])
1228 i386_skip_probe (CORE_ADDR pc
)
1230 /* A function may start with
1244 if (target_read_code (pc
, &op
, 1))
1247 if (op
== 0x68 || op
== 0x6a)
1251 /* Skip past the `pushl' instruction; it has either a one-byte or a
1252 four-byte operand, depending on the opcode. */
1258 /* Read the following 8 bytes, which should be `call _probe' (6
1259 bytes) followed by `addl $4,%esp' (2 bytes). */
1260 read_memory (pc
+ delta
, buf
, sizeof (buf
));
1261 if (buf
[0] == 0xe8 && buf
[6] == 0xc4 && buf
[7] == 0x4)
1262 pc
+= delta
+ sizeof (buf
);
1268 /* GCC 4.1 and later, can put code in the prologue to realign the
1269 stack pointer. Check whether PC points to such code, and update
1270 CACHE accordingly. Return the first instruction after the code
1271 sequence or CURRENT_PC, whichever is smaller. If we don't
1272 recognize the code, return PC. */
1275 i386_analyze_stack_align (CORE_ADDR pc
, CORE_ADDR current_pc
,
1276 struct i386_frame_cache
*cache
)
1278 /* There are 2 code sequences to re-align stack before the frame
1281 1. Use a caller-saved saved register:
1287 2. Use a callee-saved saved register:
1294 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
1296 0x83 0xe4 0xf0 andl $-16, %esp
1297 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
1302 int offset
, offset_and
;
1303 static int regnums
[8] = {
1304 I386_EAX_REGNUM
, /* %eax */
1305 I386_ECX_REGNUM
, /* %ecx */
1306 I386_EDX_REGNUM
, /* %edx */
1307 I386_EBX_REGNUM
, /* %ebx */
1308 I386_ESP_REGNUM
, /* %esp */
1309 I386_EBP_REGNUM
, /* %ebp */
1310 I386_ESI_REGNUM
, /* %esi */
1311 I386_EDI_REGNUM
/* %edi */
1314 if (target_read_code (pc
, buf
, sizeof buf
))
1317 /* Check caller-saved saved register. The first instruction has
1318 to be "leal 4(%esp), %reg". */
1319 if (buf
[0] == 0x8d && buf
[2] == 0x24 && buf
[3] == 0x4)
1321 /* MOD must be binary 10 and R/M must be binary 100. */
1322 if ((buf
[1] & 0xc7) != 0x44)
1325 /* REG has register number. */
1326 reg
= (buf
[1] >> 3) & 7;
1331 /* Check callee-saved saved register. The first instruction
1332 has to be "pushl %reg". */
1333 if ((buf
[0] & 0xf8) != 0x50)
1339 /* The next instruction has to be "leal 8(%esp), %reg". */
1340 if (buf
[1] != 0x8d || buf
[3] != 0x24 || buf
[4] != 0x8)
1343 /* MOD must be binary 10 and R/M must be binary 100. */
1344 if ((buf
[2] & 0xc7) != 0x44)
1347 /* REG has register number. Registers in pushl and leal have to
1349 if (reg
!= ((buf
[2] >> 3) & 7))
1355 /* Rigister can't be %esp nor %ebp. */
1356 if (reg
== 4 || reg
== 5)
1359 /* The next instruction has to be "andl $-XXX, %esp". */
1360 if (buf
[offset
+ 1] != 0xe4
1361 || (buf
[offset
] != 0x81 && buf
[offset
] != 0x83))
1364 offset_and
= offset
;
1365 offset
+= buf
[offset
] == 0x81 ? 6 : 3;
1367 /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is
1368 0xfc. REG must be binary 110 and MOD must be binary 01. */
1369 if (buf
[offset
] != 0xff
1370 || buf
[offset
+ 2] != 0xfc
1371 || (buf
[offset
+ 1] & 0xf8) != 0x70)
1374 /* R/M has register. Registers in leal and pushl have to be the
1376 if (reg
!= (buf
[offset
+ 1] & 7))
1379 if (current_pc
> pc
+ offset_and
)
1380 cache
->saved_sp_reg
= regnums
[reg
];
1382 return std::min (pc
+ offset
+ 3, current_pc
);
1385 /* Maximum instruction length we need to handle. */
1386 #define I386_MAX_MATCHED_INSN_LEN 6
1388 /* Instruction description. */
1392 gdb_byte insn
[I386_MAX_MATCHED_INSN_LEN
];
1393 gdb_byte mask
[I386_MAX_MATCHED_INSN_LEN
];
1396 /* Return whether instruction at PC matches PATTERN. */
1399 i386_match_pattern (CORE_ADDR pc
, struct i386_insn pattern
)
1403 if (target_read_code (pc
, &op
, 1))
1406 if ((op
& pattern
.mask
[0]) == pattern
.insn
[0])
1408 gdb_byte buf
[I386_MAX_MATCHED_INSN_LEN
- 1];
1409 int insn_matched
= 1;
1412 gdb_assert (pattern
.len
> 1);
1413 gdb_assert (pattern
.len
<= I386_MAX_MATCHED_INSN_LEN
);
1415 if (target_read_code (pc
+ 1, buf
, pattern
.len
- 1))
1418 for (i
= 1; i
< pattern
.len
; i
++)
1420 if ((buf
[i
- 1] & pattern
.mask
[i
]) != pattern
.insn
[i
])
1423 return insn_matched
;
1428 /* Search for the instruction at PC in the list INSN_PATTERNS. Return
1429 the first instruction description that matches. Otherwise, return
1432 static struct i386_insn
*
1433 i386_match_insn (CORE_ADDR pc
, struct i386_insn
*insn_patterns
)
1435 struct i386_insn
*pattern
;
1437 for (pattern
= insn_patterns
; pattern
->len
> 0; pattern
++)
1439 if (i386_match_pattern (pc
, *pattern
))
1446 /* Return whether PC points inside a sequence of instructions that
1447 matches INSN_PATTERNS. */
1450 i386_match_insn_block (CORE_ADDR pc
, struct i386_insn
*insn_patterns
)
1452 CORE_ADDR current_pc
;
1454 struct i386_insn
*insn
;
1456 insn
= i386_match_insn (pc
, insn_patterns
);
1461 ix
= insn
- insn_patterns
;
1462 for (i
= ix
- 1; i
>= 0; i
--)
1464 current_pc
-= insn_patterns
[i
].len
;
1466 if (!i386_match_pattern (current_pc
, insn_patterns
[i
]))
1470 current_pc
= pc
+ insn
->len
;
1471 for (insn
= insn_patterns
+ ix
+ 1; insn
->len
> 0; insn
++)
1473 if (!i386_match_pattern (current_pc
, *insn
))
1476 current_pc
+= insn
->len
;
1482 /* Some special instructions that might be migrated by GCC into the
1483 part of the prologue that sets up the new stack frame. Because the
1484 stack frame hasn't been setup yet, no registers have been saved
1485 yet, and only the scratch registers %eax, %ecx and %edx can be
1488 struct i386_insn i386_frame_setup_skip_insns
[] =
1490 /* Check for `movb imm8, r' and `movl imm32, r'.
1492 ??? Should we handle 16-bit operand-sizes here? */
1494 /* `movb imm8, %al' and `movb imm8, %ah' */
1495 /* `movb imm8, %cl' and `movb imm8, %ch' */
1496 { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } },
1497 /* `movb imm8, %dl' and `movb imm8, %dh' */
1498 { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } },
1499 /* `movl imm32, %eax' and `movl imm32, %ecx' */
1500 { 5, { 0xb8 }, { 0xfe } },
1501 /* `movl imm32, %edx' */
1502 { 5, { 0xba }, { 0xff } },
1504 /* Check for `mov imm32, r32'. Note that there is an alternative
1505 encoding for `mov m32, %eax'.
1507 ??? Should we handle SIB adressing here?
1508 ??? Should we handle 16-bit operand-sizes here? */
1510 /* `movl m32, %eax' */
1511 { 5, { 0xa1 }, { 0xff } },
1512 /* `movl m32, %eax' and `mov; m32, %ecx' */
1513 { 6, { 0x89, 0x05 }, {0xff, 0xf7 } },
1514 /* `movl m32, %edx' */
1515 { 6, { 0x89, 0x15 }, {0xff, 0xff } },
1517 /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'.
1518 Because of the symmetry, there are actually two ways to encode
1519 these instructions; opcode bytes 0x29 and 0x2b for `subl' and
1520 opcode bytes 0x31 and 0x33 for `xorl'. */
1522 /* `subl %eax, %eax' */
1523 { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } },
1524 /* `subl %ecx, %ecx' */
1525 { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } },
1526 /* `subl %edx, %edx' */
1527 { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } },
1528 /* `xorl %eax, %eax' */
1529 { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } },
1530 /* `xorl %ecx, %ecx' */
1531 { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } },
1532 /* `xorl %edx, %edx' */
1533 { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } },
1538 /* Check whether PC points to a no-op instruction. */
1540 i386_skip_noop (CORE_ADDR pc
)
1545 if (target_read_code (pc
, &op
, 1))
1551 /* Ignore `nop' instruction. */
1555 if (target_read_code (pc
, &op
, 1))
1559 /* Ignore no-op instruction `mov %edi, %edi'.
1560 Microsoft system dlls often start with
1561 a `mov %edi,%edi' instruction.
1562 The 5 bytes before the function start are
1563 filled with `nop' instructions.
1564 This pattern can be used for hot-patching:
1565 The `mov %edi, %edi' instruction can be replaced by a
1566 near jump to the location of the 5 `nop' instructions
1567 which can be replaced by a 32-bit jump to anywhere
1568 in the 32-bit address space. */
1570 else if (op
== 0x8b)
1572 if (target_read_code (pc
+ 1, &op
, 1))
1578 if (target_read_code (pc
, &op
, 1))
1588 /* Check whether PC points at a code that sets up a new stack frame.
1589 If so, it updates CACHE and returns the address of the first
1590 instruction after the sequence that sets up the frame or LIMIT,
1591 whichever is smaller. If we don't recognize the code, return PC. */
1594 i386_analyze_frame_setup (struct gdbarch
*gdbarch
,
1595 CORE_ADDR pc
, CORE_ADDR limit
,
1596 struct i386_frame_cache
*cache
)
1598 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1599 struct i386_insn
*insn
;
1606 if (target_read_code (pc
, &op
, 1))
1609 if (op
== 0x55) /* pushl %ebp */
1611 /* Take into account that we've executed the `pushl %ebp' that
1612 starts this instruction sequence. */
1613 cache
->saved_regs
[I386_EBP_REGNUM
] = 0;
1614 cache
->sp_offset
+= 4;
1617 /* If that's all, return now. */
1621 /* Check for some special instructions that might be migrated by
1622 GCC into the prologue and skip them. At this point in the
1623 prologue, code should only touch the scratch registers %eax,
1624 %ecx and %edx, so while the number of posibilities is sheer,
1627 Make sure we only skip these instructions if we later see the
1628 `movl %esp, %ebp' that actually sets up the frame. */
1629 while (pc
+ skip
< limit
)
1631 insn
= i386_match_insn (pc
+ skip
, i386_frame_setup_skip_insns
);
1638 /* If that's all, return now. */
1639 if (limit
<= pc
+ skip
)
1642 if (target_read_code (pc
+ skip
, &op
, 1))
1645 /* The i386 prologue looks like
1651 and a different prologue can be generated for atom.
1655 lea -0x10(%esp),%esp
1657 We handle both of them here. */
1661 /* Check for `movl %esp, %ebp' -- can be written in two ways. */
1663 if (read_code_unsigned_integer (pc
+ skip
+ 1, 1, byte_order
)
1669 if (read_code_unsigned_integer (pc
+ skip
+ 1, 1, byte_order
)
1674 case 0x8d: /* Check for 'lea (%ebp), %ebp'. */
1675 if (read_code_unsigned_integer (pc
+ skip
+ 1, 2, byte_order
)
1684 /* OK, we actually have a frame. We just don't know how large
1685 it is yet. Set its size to zero. We'll adjust it if
1686 necessary. We also now commit to skipping the special
1687 instructions mentioned before. */
1690 /* If that's all, return now. */
1694 /* Check for stack adjustment
1700 NOTE: You can't subtract a 16-bit immediate from a 32-bit
1701 reg, so we don't have to worry about a data16 prefix. */
1702 if (target_read_code (pc
, &op
, 1))
1706 /* `subl' with 8-bit immediate. */
1707 if (read_code_unsigned_integer (pc
+ 1, 1, byte_order
) != 0xec)
1708 /* Some instruction starting with 0x83 other than `subl'. */
1711 /* `subl' with signed 8-bit immediate (though it wouldn't
1712 make sense to be negative). */
1713 cache
->locals
= read_code_integer (pc
+ 2, 1, byte_order
);
1716 else if (op
== 0x81)
1718 /* Maybe it is `subl' with a 32-bit immediate. */
1719 if (read_code_unsigned_integer (pc
+ 1, 1, byte_order
) != 0xec)
1720 /* Some instruction starting with 0x81 other than `subl'. */
1723 /* It is `subl' with a 32-bit immediate. */
1724 cache
->locals
= read_code_integer (pc
+ 2, 4, byte_order
);
1727 else if (op
== 0x8d)
1729 /* The ModR/M byte is 0x64. */
1730 if (read_code_unsigned_integer (pc
+ 1, 1, byte_order
) != 0x64)
1732 /* 'lea' with 8-bit displacement. */
1733 cache
->locals
= -1 * read_code_integer (pc
+ 3, 1, byte_order
);
1738 /* Some instruction other than `subl' nor 'lea'. */
1742 else if (op
== 0xc8) /* enter */
1744 cache
->locals
= read_code_unsigned_integer (pc
+ 1, 2, byte_order
);
1751 /* Check whether PC points at code that saves registers on the stack.
1752 If so, it updates CACHE and returns the address of the first
1753 instruction after the register saves or CURRENT_PC, whichever is
1754 smaller. Otherwise, return PC. */
1757 i386_analyze_register_saves (CORE_ADDR pc
, CORE_ADDR current_pc
,
1758 struct i386_frame_cache
*cache
)
1760 CORE_ADDR offset
= 0;
1764 if (cache
->locals
> 0)
1765 offset
-= cache
->locals
;
1766 for (i
= 0; i
< 8 && pc
< current_pc
; i
++)
1768 if (target_read_code (pc
, &op
, 1))
1770 if (op
< 0x50 || op
> 0x57)
1774 cache
->saved_regs
[op
- 0x50] = offset
;
1775 cache
->sp_offset
+= 4;
1782 /* Do a full analysis of the prologue at PC and update CACHE
1783 accordingly. Bail out early if CURRENT_PC is reached. Return the
1784 address where the analysis stopped.
1786 We handle these cases:
1788 The startup sequence can be at the start of the function, or the
1789 function can start with a branch to startup code at the end.
1791 %ebp can be set up with either the 'enter' instruction, or "pushl
1792 %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was
1793 once used in the System V compiler).
1795 Local space is allocated just below the saved %ebp by either the
1796 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a
1797 16-bit unsigned argument for space to allocate, and the 'addl'
1798 instruction could have either a signed byte, or 32-bit immediate.
1800 Next, the registers used by this function are pushed. With the
1801 System V compiler they will always be in the order: %edi, %esi,
1802 %ebx (and sometimes a harmless bug causes it to also save but not
1803 restore %eax); however, the code below is willing to see the pushes
1804 in any order, and will handle up to 8 of them.
1806 If the setup sequence is at the end of the function, then the next
1807 instruction will be a branch back to the start. */
1810 i386_analyze_prologue (struct gdbarch
*gdbarch
,
1811 CORE_ADDR pc
, CORE_ADDR current_pc
,
1812 struct i386_frame_cache
*cache
)
1814 pc
= i386_skip_noop (pc
);
1815 pc
= i386_follow_jump (gdbarch
, pc
);
1816 pc
= i386_analyze_struct_return (pc
, current_pc
, cache
);
1817 pc
= i386_skip_probe (pc
);
1818 pc
= i386_analyze_stack_align (pc
, current_pc
, cache
);
1819 pc
= i386_analyze_frame_setup (gdbarch
, pc
, current_pc
, cache
);
1820 return i386_analyze_register_saves (pc
, current_pc
, cache
);
1823 /* Return PC of first real instruction. */
1826 i386_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
1828 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1830 static gdb_byte pic_pat
[6] =
1832 0xe8, 0, 0, 0, 0, /* call 0x0 */
1833 0x5b, /* popl %ebx */
1835 struct i386_frame_cache cache
;
1839 CORE_ADDR func_addr
;
1841 if (find_pc_partial_function (start_pc
, NULL
, &func_addr
, NULL
))
1843 CORE_ADDR post_prologue_pc
1844 = skip_prologue_using_sal (gdbarch
, func_addr
);
1845 struct compunit_symtab
*cust
= find_pc_compunit_symtab (func_addr
);
1847 /* Clang always emits a line note before the prologue and another
1848 one after. We trust clang to emit usable line notes. */
1849 if (post_prologue_pc
1851 && COMPUNIT_PRODUCER (cust
) != NULL
1852 && startswith (COMPUNIT_PRODUCER (cust
), "clang ")))
1853 return std::max (start_pc
, post_prologue_pc
);
1857 pc
= i386_analyze_prologue (gdbarch
, start_pc
, 0xffffffff, &cache
);
1858 if (cache
.locals
< 0)
1861 /* Found valid frame setup. */
1863 /* The native cc on SVR4 in -K PIC mode inserts the following code
1864 to get the address of the global offset table (GOT) into register
1869 movl %ebx,x(%ebp) (optional)
1872 This code is with the rest of the prologue (at the end of the
1873 function), so we have to skip it to get to the first real
1874 instruction at the start of the function. */
1876 for (i
= 0; i
< 6; i
++)
1878 if (target_read_code (pc
+ i
, &op
, 1))
1881 if (pic_pat
[i
] != op
)
1888 if (target_read_code (pc
+ delta
, &op
, 1))
1891 if (op
== 0x89) /* movl %ebx, x(%ebp) */
1893 op
= read_code_unsigned_integer (pc
+ delta
+ 1, 1, byte_order
);
1895 if (op
== 0x5d) /* One byte offset from %ebp. */
1897 else if (op
== 0x9d) /* Four byte offset from %ebp. */
1899 else /* Unexpected instruction. */
1902 if (target_read_code (pc
+ delta
, &op
, 1))
1907 if (delta
> 0 && op
== 0x81
1908 && read_code_unsigned_integer (pc
+ delta
+ 1, 1, byte_order
)
1915 /* If the function starts with a branch (to startup code at the end)
1916 the last instruction should bring us back to the first
1917 instruction of the real code. */
1918 if (i386_follow_jump (gdbarch
, start_pc
) != start_pc
)
1919 pc
= i386_follow_jump (gdbarch
, pc
);
1924 /* Check that the code pointed to by PC corresponds to a call to
1925 __main, skip it if so. Return PC otherwise. */
1928 i386_skip_main_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1930 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1933 if (target_read_code (pc
, &op
, 1))
1939 if (target_read_code (pc
+ 1, buf
, sizeof buf
) == 0)
1941 /* Make sure address is computed correctly as a 32bit
1942 integer even if CORE_ADDR is 64 bit wide. */
1943 struct bound_minimal_symbol s
;
1944 CORE_ADDR call_dest
;
1946 call_dest
= pc
+ 5 + extract_signed_integer (buf
, 4, byte_order
);
1947 call_dest
= call_dest
& 0xffffffffU
;
1948 s
= lookup_minimal_symbol_by_pc (call_dest
);
1949 if (s
.minsym
!= NULL
1950 && MSYMBOL_LINKAGE_NAME (s
.minsym
) != NULL
1951 && strcmp (MSYMBOL_LINKAGE_NAME (s
.minsym
), "__main") == 0)
1959 /* This function is 64-bit safe. */
1962 i386_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1966 frame_unwind_register (next_frame
, gdbarch_pc_regnum (gdbarch
), buf
);
1967 return extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
1971 /* Normal frames. */
1974 i386_frame_cache_1 (struct frame_info
*this_frame
,
1975 struct i386_frame_cache
*cache
)
1977 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1978 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1982 cache
->pc
= get_frame_func (this_frame
);
1984 /* In principle, for normal frames, %ebp holds the frame pointer,
1985 which holds the base address for the current stack frame.
1986 However, for functions that don't need it, the frame pointer is
1987 optional. For these "frameless" functions the frame pointer is
1988 actually the frame pointer of the calling frame. Signal
1989 trampolines are just a special case of a "frameless" function.
1990 They (usually) share their frame pointer with the frame that was
1991 in progress when the signal occurred. */
1993 get_frame_register (this_frame
, I386_EBP_REGNUM
, buf
);
1994 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
);
1995 if (cache
->base
== 0)
2001 /* For normal frames, %eip is stored at 4(%ebp). */
2002 cache
->saved_regs
[I386_EIP_REGNUM
] = 4;
2005 i386_analyze_prologue (gdbarch
, cache
->pc
, get_frame_pc (this_frame
),
2008 if (cache
->locals
< 0)
2010 /* We didn't find a valid frame, which means that CACHE->base
2011 currently holds the frame pointer for our calling frame. If
2012 we're at the start of a function, or somewhere half-way its
2013 prologue, the function's frame probably hasn't been fully
2014 setup yet. Try to reconstruct the base address for the stack
2015 frame by looking at the stack pointer. For truly "frameless"
2016 functions this might work too. */
2018 if (cache
->saved_sp_reg
!= -1)
2020 /* Saved stack pointer has been saved. */
2021 get_frame_register (this_frame
, cache
->saved_sp_reg
, buf
);
2022 cache
->saved_sp
= extract_unsigned_integer (buf
, 4, byte_order
);
2024 /* We're halfway aligning the stack. */
2025 cache
->base
= ((cache
->saved_sp
- 4) & 0xfffffff0) - 4;
2026 cache
->saved_regs
[I386_EIP_REGNUM
] = cache
->saved_sp
- 4;
2028 /* This will be added back below. */
2029 cache
->saved_regs
[I386_EIP_REGNUM
] -= cache
->base
;
2031 else if (cache
->pc
!= 0
2032 || target_read_code (get_frame_pc (this_frame
), buf
, 1))
2034 /* We're in a known function, but did not find a frame
2035 setup. Assume that the function does not use %ebp.
2036 Alternatively, we may have jumped to an invalid
2037 address; in that case there is definitely no new
2039 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
2040 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
)
2044 /* We're in an unknown function. We could not find the start
2045 of the function to analyze the prologue; our best option is
2046 to assume a typical frame layout with the caller's %ebp
2048 cache
->saved_regs
[I386_EBP_REGNUM
] = 0;
2051 if (cache
->saved_sp_reg
!= -1)
2053 /* Saved stack pointer has been saved (but the SAVED_SP_REG
2054 register may be unavailable). */
2055 if (cache
->saved_sp
== 0
2056 && deprecated_frame_register_read (this_frame
,
2057 cache
->saved_sp_reg
, buf
))
2058 cache
->saved_sp
= extract_unsigned_integer (buf
, 4, byte_order
);
2060 /* Now that we have the base address for the stack frame we can
2061 calculate the value of %esp in the calling frame. */
2062 else if (cache
->saved_sp
== 0)
2063 cache
->saved_sp
= cache
->base
+ 8;
2065 /* Adjust all the saved registers such that they contain addresses
2066 instead of offsets. */
2067 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
2068 if (cache
->saved_regs
[i
] != -1)
2069 cache
->saved_regs
[i
] += cache
->base
;
2074 static struct i386_frame_cache
*
2075 i386_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2077 struct i386_frame_cache
*cache
;
2080 return (struct i386_frame_cache
*) *this_cache
;
2082 cache
= i386_alloc_frame_cache ();
2083 *this_cache
= cache
;
2087 i386_frame_cache_1 (this_frame
, cache
);
2089 CATCH (ex
, RETURN_MASK_ERROR
)
2091 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
2092 throw_exception (ex
);
2100 i386_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2101 struct frame_id
*this_id
)
2103 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
2106 (*this_id
) = frame_id_build_unavailable_stack (cache
->pc
);
2107 else if (cache
->base
== 0)
2109 /* This marks the outermost frame. */
2113 /* See the end of i386_push_dummy_call. */
2114 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
2118 static enum unwind_stop_reason
2119 i386_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2122 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
2125 return UNWIND_UNAVAILABLE
;
2127 /* This marks the outermost frame. */
2128 if (cache
->base
== 0)
2129 return UNWIND_OUTERMOST
;
2131 return UNWIND_NO_REASON
;
2134 static struct value
*
2135 i386_frame_prev_register (struct frame_info
*this_frame
, void **this_cache
,
2138 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
2140 gdb_assert (regnum
>= 0);
2142 /* The System V ABI says that:
2144 "The flags register contains the system flags, such as the
2145 direction flag and the carry flag. The direction flag must be
2146 set to the forward (that is, zero) direction before entry and
2147 upon exit from a function. Other user flags have no specified
2148 role in the standard calling sequence and are not preserved."
2150 To guarantee the "upon exit" part of that statement we fake a
2151 saved flags register that has its direction flag cleared.
2153 Note that GCC doesn't seem to rely on the fact that the direction
2154 flag is cleared after a function return; it always explicitly
2155 clears the flag before operations where it matters.
2157 FIXME: kettenis/20030316: I'm not quite sure whether this is the
2158 right thing to do. The way we fake the flags register here makes
2159 it impossible to change it. */
2161 if (regnum
== I386_EFLAGS_REGNUM
)
2165 val
= get_frame_register_unsigned (this_frame
, regnum
);
2167 return frame_unwind_got_constant (this_frame
, regnum
, val
);
2170 if (regnum
== I386_EIP_REGNUM
&& cache
->pc_in_eax
)
2171 return frame_unwind_got_register (this_frame
, regnum
, I386_EAX_REGNUM
);
2173 if (regnum
== I386_ESP_REGNUM
2174 && (cache
->saved_sp
!= 0 || cache
->saved_sp_reg
!= -1))
2176 /* If the SP has been saved, but we don't know where, then this
2177 means that SAVED_SP_REG register was found unavailable back
2178 when we built the cache. */
2179 if (cache
->saved_sp
== 0)
2180 return frame_unwind_got_register (this_frame
, regnum
,
2181 cache
->saved_sp_reg
);
2183 return frame_unwind_got_constant (this_frame
, regnum
,
2187 if (regnum
< I386_NUM_SAVED_REGS
&& cache
->saved_regs
[regnum
] != -1)
2188 return frame_unwind_got_memory (this_frame
, regnum
,
2189 cache
->saved_regs
[regnum
]);
2191 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
2194 static const struct frame_unwind i386_frame_unwind
=
2197 i386_frame_unwind_stop_reason
,
2199 i386_frame_prev_register
,
2201 default_frame_sniffer
2204 /* Normal frames, but in a function epilogue. */
2206 /* Implement the stack_frame_destroyed_p gdbarch method.
2208 The epilogue is defined here as the 'ret' instruction, which will
2209 follow any instruction such as 'leave' or 'pop %ebp' that destroys
2210 the function's stack frame. */
2213 i386_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2216 struct compunit_symtab
*cust
;
2218 cust
= find_pc_compunit_symtab (pc
);
2219 if (cust
!= NULL
&& COMPUNIT_EPILOGUE_UNWIND_VALID (cust
))
2222 if (target_read_memory (pc
, &insn
, 1))
2223 return 0; /* Can't read memory at pc. */
2225 if (insn
!= 0xc3) /* 'ret' instruction. */
2232 i386_epilogue_frame_sniffer (const struct frame_unwind
*self
,
2233 struct frame_info
*this_frame
,
2234 void **this_prologue_cache
)
2236 if (frame_relative_level (this_frame
) == 0)
2237 return i386_stack_frame_destroyed_p (get_frame_arch (this_frame
),
2238 get_frame_pc (this_frame
));
2243 static struct i386_frame_cache
*
2244 i386_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2246 struct i386_frame_cache
*cache
;
2250 return (struct i386_frame_cache
*) *this_cache
;
2252 cache
= i386_alloc_frame_cache ();
2253 *this_cache
= cache
;
2257 cache
->pc
= get_frame_func (this_frame
);
2259 /* At this point the stack looks as if we just entered the
2260 function, with the return address at the top of the
2262 sp
= get_frame_register_unsigned (this_frame
, I386_ESP_REGNUM
);
2263 cache
->base
= sp
+ cache
->sp_offset
;
2264 cache
->saved_sp
= cache
->base
+ 8;
2265 cache
->saved_regs
[I386_EIP_REGNUM
] = cache
->base
+ 4;
2269 CATCH (ex
, RETURN_MASK_ERROR
)
2271 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
2272 throw_exception (ex
);
2279 static enum unwind_stop_reason
2280 i386_epilogue_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2283 struct i386_frame_cache
*cache
=
2284 i386_epilogue_frame_cache (this_frame
, this_cache
);
2287 return UNWIND_UNAVAILABLE
;
2289 return UNWIND_NO_REASON
;
2293 i386_epilogue_frame_this_id (struct frame_info
*this_frame
,
2295 struct frame_id
*this_id
)
2297 struct i386_frame_cache
*cache
=
2298 i386_epilogue_frame_cache (this_frame
, this_cache
);
2301 (*this_id
) = frame_id_build_unavailable_stack (cache
->pc
);
2303 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
2306 static struct value
*
2307 i386_epilogue_frame_prev_register (struct frame_info
*this_frame
,
2308 void **this_cache
, int regnum
)
2310 /* Make sure we've initialized the cache. */
2311 i386_epilogue_frame_cache (this_frame
, this_cache
);
2313 return i386_frame_prev_register (this_frame
, this_cache
, regnum
);
2316 static const struct frame_unwind i386_epilogue_frame_unwind
=
2319 i386_epilogue_frame_unwind_stop_reason
,
2320 i386_epilogue_frame_this_id
,
2321 i386_epilogue_frame_prev_register
,
2323 i386_epilogue_frame_sniffer
2327 /* Stack-based trampolines. */
2329 /* These trampolines are used on cross x86 targets, when taking the
2330 address of a nested function. When executing these trampolines,
2331 no stack frame is set up, so we are in a similar situation as in
2332 epilogues and i386_epilogue_frame_this_id can be re-used. */
2334 /* Static chain passed in register. */
2336 struct i386_insn i386_tramp_chain_in_reg_insns
[] =
2338 /* `movl imm32, %eax' and `movl imm32, %ecx' */
2339 { 5, { 0xb8 }, { 0xfe } },
2342 { 5, { 0xe9 }, { 0xff } },
2347 /* Static chain passed on stack (when regparm=3). */
2349 struct i386_insn i386_tramp_chain_on_stack_insns
[] =
2352 { 5, { 0x68 }, { 0xff } },
2355 { 5, { 0xe9 }, { 0xff } },
2360 /* Return whether PC points inside a stack trampoline. */
2363 i386_in_stack_tramp_p (CORE_ADDR pc
)
2368 /* A stack trampoline is detected if no name is associated
2369 to the current pc and if it points inside a trampoline
2372 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
2376 if (target_read_memory (pc
, &insn
, 1))
2379 if (!i386_match_insn_block (pc
, i386_tramp_chain_in_reg_insns
)
2380 && !i386_match_insn_block (pc
, i386_tramp_chain_on_stack_insns
))
2387 i386_stack_tramp_frame_sniffer (const struct frame_unwind
*self
,
2388 struct frame_info
*this_frame
,
2391 if (frame_relative_level (this_frame
) == 0)
2392 return i386_in_stack_tramp_p (get_frame_pc (this_frame
));
2397 static const struct frame_unwind i386_stack_tramp_frame_unwind
=
2400 i386_epilogue_frame_unwind_stop_reason
,
2401 i386_epilogue_frame_this_id
,
2402 i386_epilogue_frame_prev_register
,
2404 i386_stack_tramp_frame_sniffer
2407 /* Generate a bytecode expression to get the value of the saved PC. */
2410 i386_gen_return_address (struct gdbarch
*gdbarch
,
2411 struct agent_expr
*ax
, struct axs_value
*value
,
2414 /* The following sequence assumes the traditional use of the base
2416 ax_reg (ax
, I386_EBP_REGNUM
);
2418 ax_simple (ax
, aop_add
);
2419 value
->type
= register_type (gdbarch
, I386_EIP_REGNUM
);
2420 value
->kind
= axs_lvalue_memory
;
2424 /* Signal trampolines. */
2426 static struct i386_frame_cache
*
2427 i386_sigtramp_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2429 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2430 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2431 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2432 struct i386_frame_cache
*cache
;
2437 return (struct i386_frame_cache
*) *this_cache
;
2439 cache
= i386_alloc_frame_cache ();
2443 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
2444 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
) - 4;
2446 addr
= tdep
->sigcontext_addr (this_frame
);
2447 if (tdep
->sc_reg_offset
)
2451 gdb_assert (tdep
->sc_num_regs
<= I386_NUM_SAVED_REGS
);
2453 for (i
= 0; i
< tdep
->sc_num_regs
; i
++)
2454 if (tdep
->sc_reg_offset
[i
] != -1)
2455 cache
->saved_regs
[i
] = addr
+ tdep
->sc_reg_offset
[i
];
2459 cache
->saved_regs
[I386_EIP_REGNUM
] = addr
+ tdep
->sc_pc_offset
;
2460 cache
->saved_regs
[I386_ESP_REGNUM
] = addr
+ tdep
->sc_sp_offset
;
2465 CATCH (ex
, RETURN_MASK_ERROR
)
2467 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
2468 throw_exception (ex
);
2472 *this_cache
= cache
;
2476 static enum unwind_stop_reason
2477 i386_sigtramp_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2480 struct i386_frame_cache
*cache
=
2481 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2484 return UNWIND_UNAVAILABLE
;
2486 return UNWIND_NO_REASON
;
2490 i386_sigtramp_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2491 struct frame_id
*this_id
)
2493 struct i386_frame_cache
*cache
=
2494 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2497 (*this_id
) = frame_id_build_unavailable_stack (get_frame_pc (this_frame
));
2500 /* See the end of i386_push_dummy_call. */
2501 (*this_id
) = frame_id_build (cache
->base
+ 8, get_frame_pc (this_frame
));
2505 static struct value
*
2506 i386_sigtramp_frame_prev_register (struct frame_info
*this_frame
,
2507 void **this_cache
, int regnum
)
2509 /* Make sure we've initialized the cache. */
2510 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2512 return i386_frame_prev_register (this_frame
, this_cache
, regnum
);
2516 i386_sigtramp_frame_sniffer (const struct frame_unwind
*self
,
2517 struct frame_info
*this_frame
,
2518 void **this_prologue_cache
)
2520 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (this_frame
));
2522 /* We shouldn't even bother if we don't have a sigcontext_addr
2524 if (tdep
->sigcontext_addr
== NULL
)
2527 if (tdep
->sigtramp_p
!= NULL
)
2529 if (tdep
->sigtramp_p (this_frame
))
2533 if (tdep
->sigtramp_start
!= 0)
2535 CORE_ADDR pc
= get_frame_pc (this_frame
);
2537 gdb_assert (tdep
->sigtramp_end
!= 0);
2538 if (pc
>= tdep
->sigtramp_start
&& pc
< tdep
->sigtramp_end
)
2545 static const struct frame_unwind i386_sigtramp_frame_unwind
=
2548 i386_sigtramp_frame_unwind_stop_reason
,
2549 i386_sigtramp_frame_this_id
,
2550 i386_sigtramp_frame_prev_register
,
2552 i386_sigtramp_frame_sniffer
2557 i386_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
2559 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
2564 static const struct frame_base i386_frame_base
=
2567 i386_frame_base_address
,
2568 i386_frame_base_address
,
2569 i386_frame_base_address
2572 static struct frame_id
2573 i386_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
2577 fp
= get_frame_register_unsigned (this_frame
, I386_EBP_REGNUM
);
2579 /* See the end of i386_push_dummy_call. */
2580 return frame_id_build (fp
+ 8, get_frame_pc (this_frame
));
2583 /* _Decimal128 function return values need 16-byte alignment on the
2587 i386_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
2589 return sp
& -(CORE_ADDR
)16;
2593 /* Figure out where the longjmp will land. Slurp the args out of the
2594 stack. We expect the first arg to be a pointer to the jmp_buf
2595 structure from which we extract the address that we will land at.
2596 This address is copied into PC. This routine returns non-zero on
2600 i386_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
2603 CORE_ADDR sp
, jb_addr
;
2604 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2605 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2606 int jb_pc_offset
= gdbarch_tdep (gdbarch
)->jb_pc_offset
;
2608 /* If JB_PC_OFFSET is -1, we have no way to find out where the
2609 longjmp will land. */
2610 if (jb_pc_offset
== -1)
2613 get_frame_register (frame
, I386_ESP_REGNUM
, buf
);
2614 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
2615 if (target_read_memory (sp
+ 4, buf
, 4))
2618 jb_addr
= extract_unsigned_integer (buf
, 4, byte_order
);
2619 if (target_read_memory (jb_addr
+ jb_pc_offset
, buf
, 4))
2622 *pc
= extract_unsigned_integer (buf
, 4, byte_order
);
2627 /* Check whether TYPE must be 16-byte-aligned when passed as a
2628 function argument. 16-byte vectors, _Decimal128 and structures or
2629 unions containing such types must be 16-byte-aligned; other
2630 arguments are 4-byte-aligned. */
2633 i386_16_byte_align_p (struct type
*type
)
2635 type
= check_typedef (type
);
2636 if ((TYPE_CODE (type
) == TYPE_CODE_DECFLOAT
2637 || (TYPE_CODE (type
) == TYPE_CODE_ARRAY
&& TYPE_VECTOR (type
)))
2638 && TYPE_LENGTH (type
) == 16)
2640 if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
2641 return i386_16_byte_align_p (TYPE_TARGET_TYPE (type
));
2642 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
2643 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
2646 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
2648 if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type
, i
)))
2655 /* Implementation for set_gdbarch_push_dummy_code. */
2658 i386_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
, CORE_ADDR funaddr
,
2659 struct value
**args
, int nargs
, struct type
*value_type
,
2660 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
,
2661 struct regcache
*regcache
)
2663 /* Use 0xcc breakpoint - 1 byte. */
2667 /* Keep the stack aligned. */
2672 i386_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2673 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
2674 struct value
**args
, CORE_ADDR sp
, int struct_return
,
2675 CORE_ADDR struct_addr
)
2677 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2683 /* BND registers can be in arbitrary values at the moment of the
2684 inferior call. This can cause boundary violations that are not
2685 due to a real bug or even desired by the user. The best to be done
2686 is set the BND registers to allow access to the whole memory, INIT
2687 state, before pushing the inferior call. */
2688 i387_reset_bnd_regs (gdbarch
, regcache
);
2690 /* Determine the total space required for arguments and struct
2691 return address in a first pass (allowing for 16-byte-aligned
2692 arguments), then push arguments in a second pass. */
2694 for (write_pass
= 0; write_pass
< 2; write_pass
++)
2696 int args_space_used
= 0;
2702 /* Push value address. */
2703 store_unsigned_integer (buf
, 4, byte_order
, struct_addr
);
2704 write_memory (sp
, buf
, 4);
2705 args_space_used
+= 4;
2711 for (i
= 0; i
< nargs
; i
++)
2713 int len
= TYPE_LENGTH (value_enclosing_type (args
[i
]));
2717 if (i386_16_byte_align_p (value_enclosing_type (args
[i
])))
2718 args_space_used
= align_up (args_space_used
, 16);
2720 write_memory (sp
+ args_space_used
,
2721 value_contents_all (args
[i
]), len
);
2722 /* The System V ABI says that:
2724 "An argument's size is increased, if necessary, to make it a
2725 multiple of [32-bit] words. This may require tail padding,
2726 depending on the size of the argument."
2728 This makes sure the stack stays word-aligned. */
2729 args_space_used
+= align_up (len
, 4);
2733 if (i386_16_byte_align_p (value_enclosing_type (args
[i
])))
2734 args_space
= align_up (args_space
, 16);
2735 args_space
+= align_up (len
, 4);
2743 /* The original System V ABI only requires word alignment,
2744 but modern incarnations need 16-byte alignment in order
2745 to support SSE. Since wasting a few bytes here isn't
2746 harmful we unconditionally enforce 16-byte alignment. */
2751 /* Store return address. */
2753 store_unsigned_integer (buf
, 4, byte_order
, bp_addr
);
2754 write_memory (sp
, buf
, 4);
2756 /* Finally, update the stack pointer... */
2757 store_unsigned_integer (buf
, 4, byte_order
, sp
);
2758 regcache
->cooked_write (I386_ESP_REGNUM
, buf
);
2760 /* ...and fake a frame pointer. */
2761 regcache
->cooked_write (I386_EBP_REGNUM
, buf
);
2763 /* MarkK wrote: This "+ 8" is all over the place:
2764 (i386_frame_this_id, i386_sigtramp_frame_this_id,
2765 i386_dummy_id). It's there, since all frame unwinders for
2766 a given target have to agree (within a certain margin) on the
2767 definition of the stack address of a frame. Otherwise frame id
2768 comparison might not work correctly. Since DWARF2/GCC uses the
2769 stack address *before* the function call as a frame's CFA. On
2770 the i386, when %ebp is used as a frame pointer, the offset
2771 between the contents %ebp and the CFA as defined by GCC. */
2775 /* These registers are used for returning integers (and on some
2776 targets also for returning `struct' and `union' values when their
2777 size and alignment match an integer type). */
2778 #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */
2779 #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */
2781 /* Read, for architecture GDBARCH, a function return value of TYPE
2782 from REGCACHE, and copy that into VALBUF. */
2785 i386_extract_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
2786 struct regcache
*regcache
, gdb_byte
*valbuf
)
2788 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2789 int len
= TYPE_LENGTH (type
);
2790 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
2792 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2794 if (tdep
->st0_regnum
< 0)
2796 warning (_("Cannot find floating-point return value."));
2797 memset (valbuf
, 0, len
);
2801 /* Floating-point return values can be found in %st(0). Convert
2802 its contents to the desired type. This is probably not
2803 exactly how it would happen on the target itself, but it is
2804 the best we can do. */
2805 regcache
->raw_read (I386_ST0_REGNUM
, buf
);
2806 target_float_convert (buf
, i387_ext_type (gdbarch
), valbuf
, type
);
2810 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
2811 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
2813 if (len
<= low_size
)
2815 regcache
->raw_read (LOW_RETURN_REGNUM
, buf
);
2816 memcpy (valbuf
, buf
, len
);
2818 else if (len
<= (low_size
+ high_size
))
2820 regcache
->raw_read (LOW_RETURN_REGNUM
, buf
);
2821 memcpy (valbuf
, buf
, low_size
);
2822 regcache
->raw_read (HIGH_RETURN_REGNUM
, buf
);
2823 memcpy (valbuf
+ low_size
, buf
, len
- low_size
);
2826 internal_error (__FILE__
, __LINE__
,
2827 _("Cannot extract return value of %d bytes long."),
2832 /* Write, for architecture GDBARCH, a function return value of TYPE
2833 from VALBUF into REGCACHE. */
2836 i386_store_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
2837 struct regcache
*regcache
, const gdb_byte
*valbuf
)
2839 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2840 int len
= TYPE_LENGTH (type
);
2842 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2845 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
2847 if (tdep
->st0_regnum
< 0)
2849 warning (_("Cannot set floating-point return value."));
2853 /* Returning floating-point values is a bit tricky. Apart from
2854 storing the return value in %st(0), we have to simulate the
2855 state of the FPU at function return point. */
2857 /* Convert the value found in VALBUF to the extended
2858 floating-point format used by the FPU. This is probably
2859 not exactly how it would happen on the target itself, but
2860 it is the best we can do. */
2861 target_float_convert (valbuf
, type
, buf
, i387_ext_type (gdbarch
));
2862 regcache
->raw_write (I386_ST0_REGNUM
, buf
);
2864 /* Set the top of the floating-point register stack to 7. The
2865 actual value doesn't really matter, but 7 is what a normal
2866 function return would end up with if the program started out
2867 with a freshly initialized FPU. */
2868 regcache_raw_read_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), &fstat
);
2870 regcache_raw_write_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), fstat
);
2872 /* Mark %st(1) through %st(7) as empty. Since we set the top of
2873 the floating-point register stack to 7, the appropriate value
2874 for the tag word is 0x3fff. */
2875 regcache_raw_write_unsigned (regcache
, I387_FTAG_REGNUM (tdep
), 0x3fff);
2879 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
2880 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
2882 if (len
<= low_size
)
2883 regcache
->raw_write_part (LOW_RETURN_REGNUM
, 0, len
, valbuf
);
2884 else if (len
<= (low_size
+ high_size
))
2886 regcache
->raw_write (LOW_RETURN_REGNUM
, valbuf
);
2887 regcache
->raw_write_part (HIGH_RETURN_REGNUM
, 0, len
- low_size
,
2891 internal_error (__FILE__
, __LINE__
,
2892 _("Cannot store return value of %d bytes long."), len
);
2897 /* This is the variable that is set with "set struct-convention", and
2898 its legitimate values. */
2899 static const char default_struct_convention
[] = "default";
2900 static const char pcc_struct_convention
[] = "pcc";
2901 static const char reg_struct_convention
[] = "reg";
2902 static const char *const valid_conventions
[] =
2904 default_struct_convention
,
2905 pcc_struct_convention
,
2906 reg_struct_convention
,
2909 static const char *struct_convention
= default_struct_convention
;
2911 /* Return non-zero if TYPE, which is assumed to be a structure,
2912 a union type, or an array type, should be returned in registers
2913 for architecture GDBARCH. */
2916 i386_reg_struct_return_p (struct gdbarch
*gdbarch
, struct type
*type
)
2918 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2919 enum type_code code
= TYPE_CODE (type
);
2920 int len
= TYPE_LENGTH (type
);
2922 gdb_assert (code
== TYPE_CODE_STRUCT
2923 || code
== TYPE_CODE_UNION
2924 || code
== TYPE_CODE_ARRAY
);
2926 if (struct_convention
== pcc_struct_convention
2927 || (struct_convention
== default_struct_convention
2928 && tdep
->struct_return
== pcc_struct_return
))
2931 /* Structures consisting of a single `float', `double' or 'long
2932 double' member are returned in %st(0). */
2933 if (code
== TYPE_CODE_STRUCT
&& TYPE_NFIELDS (type
) == 1)
2935 type
= check_typedef (TYPE_FIELD_TYPE (type
, 0));
2936 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2937 return (len
== 4 || len
== 8 || len
== 12);
2940 return (len
== 1 || len
== 2 || len
== 4 || len
== 8);
2943 /* Determine, for architecture GDBARCH, how a return value of TYPE
2944 should be returned. If it is supposed to be returned in registers,
2945 and READBUF is non-zero, read the appropriate value from REGCACHE,
2946 and copy it into READBUF. If WRITEBUF is non-zero, write the value
2947 from WRITEBUF into REGCACHE. */
2949 static enum return_value_convention
2950 i386_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
2951 struct type
*type
, struct regcache
*regcache
,
2952 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2954 enum type_code code
= TYPE_CODE (type
);
2956 if (((code
== TYPE_CODE_STRUCT
2957 || code
== TYPE_CODE_UNION
2958 || code
== TYPE_CODE_ARRAY
)
2959 && !i386_reg_struct_return_p (gdbarch
, type
))
2960 /* Complex double and long double uses the struct return covention. */
2961 || (code
== TYPE_CODE_COMPLEX
&& TYPE_LENGTH (type
) == 16)
2962 || (code
== TYPE_CODE_COMPLEX
&& TYPE_LENGTH (type
) == 24)
2963 /* 128-bit decimal float uses the struct return convention. */
2964 || (code
== TYPE_CODE_DECFLOAT
&& TYPE_LENGTH (type
) == 16))
2966 /* The System V ABI says that:
2968 "A function that returns a structure or union also sets %eax
2969 to the value of the original address of the caller's area
2970 before it returns. Thus when the caller receives control
2971 again, the address of the returned object resides in register
2972 %eax and can be used to access the object."
2974 So the ABI guarantees that we can always find the return
2975 value just after the function has returned. */
2977 /* Note that the ABI doesn't mention functions returning arrays,
2978 which is something possible in certain languages such as Ada.
2979 In this case, the value is returned as if it was wrapped in
2980 a record, so the convention applied to records also applies
2987 regcache_raw_read_unsigned (regcache
, I386_EAX_REGNUM
, &addr
);
2988 read_memory (addr
, readbuf
, TYPE_LENGTH (type
));
2991 return RETURN_VALUE_ABI_RETURNS_ADDRESS
;
2994 /* This special case is for structures consisting of a single
2995 `float', `double' or 'long double' member. These structures are
2996 returned in %st(0). For these structures, we call ourselves
2997 recursively, changing TYPE into the type of the first member of
2998 the structure. Since that should work for all structures that
2999 have only one member, we don't bother to check the member's type
3001 if (code
== TYPE_CODE_STRUCT
&& TYPE_NFIELDS (type
) == 1)
3003 type
= check_typedef (TYPE_FIELD_TYPE (type
, 0));
3004 return i386_return_value (gdbarch
, function
, type
, regcache
,
3009 i386_extract_return_value (gdbarch
, type
, regcache
, readbuf
);
3011 i386_store_return_value (gdbarch
, type
, regcache
, writebuf
);
3013 return RETURN_VALUE_REGISTER_CONVENTION
;
3018 i387_ext_type (struct gdbarch
*gdbarch
)
3020 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3022 if (!tdep
->i387_ext_type
)
3024 tdep
->i387_ext_type
= tdesc_find_type (gdbarch
, "i387_ext");
3025 gdb_assert (tdep
->i387_ext_type
!= NULL
);
3028 return tdep
->i387_ext_type
;
3031 /* Construct type for pseudo BND registers. We can't use
3032 tdesc_find_type since a complement of one value has to be used
3033 to describe the upper bound. */
3035 static struct type
*
3036 i386_bnd_type (struct gdbarch
*gdbarch
)
3038 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3041 if (!tdep
->i386_bnd_type
)
3044 const struct builtin_type
*bt
= builtin_type (gdbarch
);
3046 /* The type we're building is described bellow: */
3051 void *ubound
; /* One complement of raw ubound field. */
3055 t
= arch_composite_type (gdbarch
,
3056 "__gdb_builtin_type_bound128", TYPE_CODE_STRUCT
);
3058 append_composite_type_field (t
, "lbound", bt
->builtin_data_ptr
);
3059 append_composite_type_field (t
, "ubound", bt
->builtin_data_ptr
);
3061 TYPE_NAME (t
) = "builtin_type_bound128";
3062 tdep
->i386_bnd_type
= t
;
3065 return tdep
->i386_bnd_type
;
3068 /* Construct vector type for pseudo ZMM registers. We can't use
3069 tdesc_find_type since ZMM isn't described in target description. */
3071 static struct type
*
3072 i386_zmm_type (struct gdbarch
*gdbarch
)
3074 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3076 if (!tdep
->i386_zmm_type
)
3078 const struct builtin_type
*bt
= builtin_type (gdbarch
);
3080 /* The type we're building is this: */
3082 union __gdb_builtin_type_vec512i
3084 int128_t uint128
[4];
3085 int64_t v4_int64
[8];
3086 int32_t v8_int32
[16];
3087 int16_t v16_int16
[32];
3088 int8_t v32_int8
[64];
3089 double v4_double
[8];
3096 t
= arch_composite_type (gdbarch
,
3097 "__gdb_builtin_type_vec512i", TYPE_CODE_UNION
);
3098 append_composite_type_field (t
, "v16_float",
3099 init_vector_type (bt
->builtin_float
, 16));
3100 append_composite_type_field (t
, "v8_double",
3101 init_vector_type (bt
->builtin_double
, 8));
3102 append_composite_type_field (t
, "v64_int8",
3103 init_vector_type (bt
->builtin_int8
, 64));
3104 append_composite_type_field (t
, "v32_int16",
3105 init_vector_type (bt
->builtin_int16
, 32));
3106 append_composite_type_field (t
, "v16_int32",
3107 init_vector_type (bt
->builtin_int32
, 16));
3108 append_composite_type_field (t
, "v8_int64",
3109 init_vector_type (bt
->builtin_int64
, 8));
3110 append_composite_type_field (t
, "v4_int128",
3111 init_vector_type (bt
->builtin_int128
, 4));
3113 TYPE_VECTOR (t
) = 1;
3114 TYPE_NAME (t
) = "builtin_type_vec512i";
3115 tdep
->i386_zmm_type
= t
;
3118 return tdep
->i386_zmm_type
;
3121 /* Construct vector type for pseudo YMM registers. We can't use
3122 tdesc_find_type since YMM isn't described in target description. */
3124 static struct type
*
3125 i386_ymm_type (struct gdbarch
*gdbarch
)
3127 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3129 if (!tdep
->i386_ymm_type
)
3131 const struct builtin_type
*bt
= builtin_type (gdbarch
);
3133 /* The type we're building is this: */
3135 union __gdb_builtin_type_vec256i
3137 int128_t uint128
[2];
3138 int64_t v2_int64
[4];
3139 int32_t v4_int32
[8];
3140 int16_t v8_int16
[16];
3141 int8_t v16_int8
[32];
3142 double v2_double
[4];
3149 t
= arch_composite_type (gdbarch
,
3150 "__gdb_builtin_type_vec256i", TYPE_CODE_UNION
);
3151 append_composite_type_field (t
, "v8_float",
3152 init_vector_type (bt
->builtin_float
, 8));
3153 append_composite_type_field (t
, "v4_double",
3154 init_vector_type (bt
->builtin_double
, 4));
3155 append_composite_type_field (t
, "v32_int8",
3156 init_vector_type (bt
->builtin_int8
, 32));
3157 append_composite_type_field (t
, "v16_int16",
3158 init_vector_type (bt
->builtin_int16
, 16));
3159 append_composite_type_field (t
, "v8_int32",
3160 init_vector_type (bt
->builtin_int32
, 8));
3161 append_composite_type_field (t
, "v4_int64",
3162 init_vector_type (bt
->builtin_int64
, 4));
3163 append_composite_type_field (t
, "v2_int128",
3164 init_vector_type (bt
->builtin_int128
, 2));
3166 TYPE_VECTOR (t
) = 1;
3167 TYPE_NAME (t
) = "builtin_type_vec256i";
3168 tdep
->i386_ymm_type
= t
;
3171 return tdep
->i386_ymm_type
;
3174 /* Construct vector type for MMX registers. */
3175 static struct type
*
3176 i386_mmx_type (struct gdbarch
*gdbarch
)
3178 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3180 if (!tdep
->i386_mmx_type
)
3182 const struct builtin_type
*bt
= builtin_type (gdbarch
);
3184 /* The type we're building is this: */
3186 union __gdb_builtin_type_vec64i
3189 int32_t v2_int32
[2];
3190 int16_t v4_int16
[4];
3197 t
= arch_composite_type (gdbarch
,
3198 "__gdb_builtin_type_vec64i", TYPE_CODE_UNION
);
3200 append_composite_type_field (t
, "uint64", bt
->builtin_int64
);
3201 append_composite_type_field (t
, "v2_int32",
3202 init_vector_type (bt
->builtin_int32
, 2));
3203 append_composite_type_field (t
, "v4_int16",
3204 init_vector_type (bt
->builtin_int16
, 4));
3205 append_composite_type_field (t
, "v8_int8",
3206 init_vector_type (bt
->builtin_int8
, 8));
3208 TYPE_VECTOR (t
) = 1;
3209 TYPE_NAME (t
) = "builtin_type_vec64i";
3210 tdep
->i386_mmx_type
= t
;
3213 return tdep
->i386_mmx_type
;
3216 /* Return the GDB type object for the "standard" data type of data in
3220 i386_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
3222 if (i386_bnd_regnum_p (gdbarch
, regnum
))
3223 return i386_bnd_type (gdbarch
);
3224 if (i386_mmx_regnum_p (gdbarch
, regnum
))
3225 return i386_mmx_type (gdbarch
);
3226 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
3227 return i386_ymm_type (gdbarch
);
3228 else if (i386_ymm_avx512_regnum_p (gdbarch
, regnum
))
3229 return i386_ymm_type (gdbarch
);
3230 else if (i386_zmm_regnum_p (gdbarch
, regnum
))
3231 return i386_zmm_type (gdbarch
);
3234 const struct builtin_type
*bt
= builtin_type (gdbarch
);
3235 if (i386_byte_regnum_p (gdbarch
, regnum
))
3236 return bt
->builtin_int8
;
3237 else if (i386_word_regnum_p (gdbarch
, regnum
))
3238 return bt
->builtin_int16
;
3239 else if (i386_dword_regnum_p (gdbarch
, regnum
))
3240 return bt
->builtin_int32
;
3241 else if (i386_k_regnum_p (gdbarch
, regnum
))
3242 return bt
->builtin_int64
;
3245 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
3248 /* Map a cooked register onto a raw register or memory. For the i386,
3249 the MMX registers need to be mapped onto floating point registers. */
3252 i386_mmx_regnum_to_fp_regnum (readable_regcache
*regcache
, int regnum
)
3254 struct gdbarch_tdep
*tdep
= gdbarch_tdep (regcache
->arch ());
3259 mmxreg
= regnum
- tdep
->mm0_regnum
;
3260 regcache
->raw_read (I387_FSTAT_REGNUM (tdep
), &fstat
);
3261 tos
= (fstat
>> 11) & 0x7;
3262 fpreg
= (mmxreg
+ tos
) % 8;
3264 return (I387_ST0_REGNUM (tdep
) + fpreg
);
3267 /* A helper function for us by i386_pseudo_register_read_value and
3268 amd64_pseudo_register_read_value. It does all the work but reads
3269 the data into an already-allocated value. */
3272 i386_pseudo_register_read_into_value (struct gdbarch
*gdbarch
,
3273 readable_regcache
*regcache
,
3275 struct value
*result_value
)
3277 gdb_byte raw_buf
[I386_MAX_REGISTER_SIZE
];
3278 enum register_status status
;
3279 gdb_byte
*buf
= value_contents_raw (result_value
);
3281 if (i386_mmx_regnum_p (gdbarch
, regnum
))
3283 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
3285 /* Extract (always little endian). */
3286 status
= regcache
->raw_read (fpnum
, raw_buf
);
3287 if (status
!= REG_VALID
)
3288 mark_value_bytes_unavailable (result_value
, 0,
3289 TYPE_LENGTH (value_type (result_value
)));
3291 memcpy (buf
, raw_buf
, register_size (gdbarch
, regnum
));
3295 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3296 if (i386_bnd_regnum_p (gdbarch
, regnum
))
3298 regnum
-= tdep
->bnd0_regnum
;
3300 /* Extract (always little endian). Read lower 128bits. */
3301 status
= regcache
->raw_read (I387_BND0R_REGNUM (tdep
) + regnum
,
3303 if (status
!= REG_VALID
)
3304 mark_value_bytes_unavailable (result_value
, 0, 16);
3307 enum bfd_endian byte_order
= gdbarch_byte_order (target_gdbarch ());
3308 LONGEST upper
, lower
;
3309 int size
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_data_ptr
);
3311 lower
= extract_unsigned_integer (raw_buf
, 8, byte_order
);
3312 upper
= extract_unsigned_integer (raw_buf
+ 8, 8, byte_order
);
3315 memcpy (buf
, &lower
, size
);
3316 memcpy (buf
+ size
, &upper
, size
);
3319 else if (i386_k_regnum_p (gdbarch
, regnum
))
3321 regnum
-= tdep
->k0_regnum
;
3323 /* Extract (always little endian). */
3324 status
= regcache
->raw_read (tdep
->k0_regnum
+ regnum
, raw_buf
);
3325 if (status
!= REG_VALID
)
3326 mark_value_bytes_unavailable (result_value
, 0, 8);
3328 memcpy (buf
, raw_buf
, 8);
3330 else if (i386_zmm_regnum_p (gdbarch
, regnum
))
3332 regnum
-= tdep
->zmm0_regnum
;
3334 if (regnum
< num_lower_zmm_regs
)
3336 /* Extract (always little endian). Read lower 128bits. */
3337 status
= regcache
->raw_read (I387_XMM0_REGNUM (tdep
) + regnum
,
3339 if (status
!= REG_VALID
)
3340 mark_value_bytes_unavailable (result_value
, 0, 16);
3342 memcpy (buf
, raw_buf
, 16);
3344 /* Extract (always little endian). Read upper 128bits. */
3345 status
= regcache
->raw_read (tdep
->ymm0h_regnum
+ regnum
,
3347 if (status
!= REG_VALID
)
3348 mark_value_bytes_unavailable (result_value
, 16, 16);
3350 memcpy (buf
+ 16, raw_buf
, 16);
3354 /* Extract (always little endian). Read lower 128bits. */
3355 status
= regcache
->raw_read (I387_XMM16_REGNUM (tdep
) + regnum
3356 - num_lower_zmm_regs
,
3358 if (status
!= REG_VALID
)
3359 mark_value_bytes_unavailable (result_value
, 0, 16);
3361 memcpy (buf
, raw_buf
, 16);
3363 /* Extract (always little endian). Read upper 128bits. */
3364 status
= regcache
->raw_read (I387_YMM16H_REGNUM (tdep
) + regnum
3365 - num_lower_zmm_regs
,
3367 if (status
!= REG_VALID
)
3368 mark_value_bytes_unavailable (result_value
, 16, 16);
3370 memcpy (buf
+ 16, raw_buf
, 16);
3373 /* Read upper 256bits. */
3374 status
= regcache
->raw_read (tdep
->zmm0h_regnum
+ regnum
,
3376 if (status
!= REG_VALID
)
3377 mark_value_bytes_unavailable (result_value
, 32, 32);
3379 memcpy (buf
+ 32, raw_buf
, 32);
3381 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
3383 regnum
-= tdep
->ymm0_regnum
;
3385 /* Extract (always little endian). Read lower 128bits. */
3386 status
= regcache
->raw_read (I387_XMM0_REGNUM (tdep
) + regnum
,
3388 if (status
!= REG_VALID
)
3389 mark_value_bytes_unavailable (result_value
, 0, 16);
3391 memcpy (buf
, raw_buf
, 16);
3392 /* Read upper 128bits. */
3393 status
= regcache
->raw_read (tdep
->ymm0h_regnum
+ regnum
,
3395 if (status
!= REG_VALID
)
3396 mark_value_bytes_unavailable (result_value
, 16, 32);
3398 memcpy (buf
+ 16, raw_buf
, 16);
3400 else if (i386_ymm_avx512_regnum_p (gdbarch
, regnum
))
3402 regnum
-= tdep
->ymm16_regnum
;
3403 /* Extract (always little endian). Read lower 128bits. */
3404 status
= regcache
->raw_read (I387_XMM16_REGNUM (tdep
) + regnum
,
3406 if (status
!= REG_VALID
)
3407 mark_value_bytes_unavailable (result_value
, 0, 16);
3409 memcpy (buf
, raw_buf
, 16);
3410 /* Read upper 128bits. */
3411 status
= regcache
->raw_read (tdep
->ymm16h_regnum
+ regnum
,
3413 if (status
!= REG_VALID
)
3414 mark_value_bytes_unavailable (result_value
, 16, 16);
3416 memcpy (buf
+ 16, raw_buf
, 16);
3418 else if (i386_word_regnum_p (gdbarch
, regnum
))
3420 int gpnum
= regnum
- tdep
->ax_regnum
;
3422 /* Extract (always little endian). */
3423 status
= regcache
->raw_read (gpnum
, raw_buf
);
3424 if (status
!= REG_VALID
)
3425 mark_value_bytes_unavailable (result_value
, 0,
3426 TYPE_LENGTH (value_type (result_value
)));
3428 memcpy (buf
, raw_buf
, 2);
3430 else if (i386_byte_regnum_p (gdbarch
, regnum
))
3432 int gpnum
= regnum
- tdep
->al_regnum
;
3434 /* Extract (always little endian). We read both lower and
3436 status
= regcache
->raw_read (gpnum
% 4, raw_buf
);
3437 if (status
!= REG_VALID
)
3438 mark_value_bytes_unavailable (result_value
, 0,
3439 TYPE_LENGTH (value_type (result_value
)));
3440 else if (gpnum
>= 4)
3441 memcpy (buf
, raw_buf
+ 1, 1);
3443 memcpy (buf
, raw_buf
, 1);
3446 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
3450 static struct value
*
3451 i386_pseudo_register_read_value (struct gdbarch
*gdbarch
,
3452 readable_regcache
*regcache
,
3455 struct value
*result
;
3457 result
= allocate_value (register_type (gdbarch
, regnum
));
3458 VALUE_LVAL (result
) = lval_register
;
3459 VALUE_REGNUM (result
) = regnum
;
3461 i386_pseudo_register_read_into_value (gdbarch
, regcache
, regnum
, result
);
3467 i386_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
3468 int regnum
, const gdb_byte
*buf
)
3470 gdb_byte raw_buf
[I386_MAX_REGISTER_SIZE
];
3472 if (i386_mmx_regnum_p (gdbarch
, regnum
))
3474 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
3477 regcache
->raw_read (fpnum
, raw_buf
);
3478 /* ... Modify ... (always little endian). */
3479 memcpy (raw_buf
, buf
, register_size (gdbarch
, regnum
));
3481 regcache
->raw_write (fpnum
, raw_buf
);
3485 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3487 if (i386_bnd_regnum_p (gdbarch
, regnum
))
3489 ULONGEST upper
, lower
;
3490 int size
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_data_ptr
);
3491 enum bfd_endian byte_order
= gdbarch_byte_order (target_gdbarch ());
3493 /* New values from input value. */
3494 regnum
-= tdep
->bnd0_regnum
;
3495 lower
= extract_unsigned_integer (buf
, size
, byte_order
);
3496 upper
= extract_unsigned_integer (buf
+ size
, size
, byte_order
);
3498 /* Fetching register buffer. */
3499 regcache
->raw_read (I387_BND0R_REGNUM (tdep
) + regnum
,
3504 /* Set register bits. */
3505 memcpy (raw_buf
, &lower
, 8);
3506 memcpy (raw_buf
+ 8, &upper
, 8);
3508 regcache
->raw_write (I387_BND0R_REGNUM (tdep
) + regnum
, raw_buf
);
3510 else if (i386_k_regnum_p (gdbarch
, regnum
))
3512 regnum
-= tdep
->k0_regnum
;
3514 regcache
->raw_write (tdep
->k0_regnum
+ regnum
, buf
);
3516 else if (i386_zmm_regnum_p (gdbarch
, regnum
))
3518 regnum
-= tdep
->zmm0_regnum
;
3520 if (regnum
< num_lower_zmm_regs
)
3522 /* Write lower 128bits. */
3523 regcache
->raw_write (I387_XMM0_REGNUM (tdep
) + regnum
, buf
);
3524 /* Write upper 128bits. */
3525 regcache
->raw_write (I387_YMM0_REGNUM (tdep
) + regnum
, buf
+ 16);
3529 /* Write lower 128bits. */
3530 regcache
->raw_write (I387_XMM16_REGNUM (tdep
) + regnum
3531 - num_lower_zmm_regs
, buf
);
3532 /* Write upper 128bits. */
3533 regcache
->raw_write (I387_YMM16H_REGNUM (tdep
) + regnum
3534 - num_lower_zmm_regs
, buf
+ 16);
3536 /* Write upper 256bits. */
3537 regcache
->raw_write (tdep
->zmm0h_regnum
+ regnum
, buf
+ 32);
3539 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
3541 regnum
-= tdep
->ymm0_regnum
;
3543 /* ... Write lower 128bits. */
3544 regcache
->raw_write (I387_XMM0_REGNUM (tdep
) + regnum
, buf
);
3545 /* ... Write upper 128bits. */
3546 regcache
->raw_write (tdep
->ymm0h_regnum
+ regnum
, buf
+ 16);
3548 else if (i386_ymm_avx512_regnum_p (gdbarch
, regnum
))
3550 regnum
-= tdep
->ymm16_regnum
;
3552 /* ... Write lower 128bits. */
3553 regcache
->raw_write (I387_XMM16_REGNUM (tdep
) + regnum
, buf
);
3554 /* ... Write upper 128bits. */
3555 regcache
->raw_write (tdep
->ymm16h_regnum
+ regnum
, buf
+ 16);
3557 else if (i386_word_regnum_p (gdbarch
, regnum
))
3559 int gpnum
= regnum
- tdep
->ax_regnum
;
3562 regcache
->raw_read (gpnum
, raw_buf
);
3563 /* ... Modify ... (always little endian). */
3564 memcpy (raw_buf
, buf
, 2);
3566 regcache
->raw_write (gpnum
, raw_buf
);
3568 else if (i386_byte_regnum_p (gdbarch
, regnum
))
3570 int gpnum
= regnum
- tdep
->al_regnum
;
3572 /* Read ... We read both lower and upper registers. */
3573 regcache
->raw_read (gpnum
% 4, raw_buf
);
3574 /* ... Modify ... (always little endian). */
3576 memcpy (raw_buf
+ 1, buf
, 1);
3578 memcpy (raw_buf
, buf
, 1);
3580 regcache
->raw_write (gpnum
% 4, raw_buf
);
3583 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
3587 /* Implement the 'ax_pseudo_register_collect' gdbarch method. */
3590 i386_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
3591 struct agent_expr
*ax
, int regnum
)
3593 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3595 if (i386_mmx_regnum_p (gdbarch
, regnum
))
3597 /* MMX to FPU register mapping depends on current TOS. Let's just
3598 not care and collect everything... */
3601 ax_reg_mask (ax
, I387_FSTAT_REGNUM (tdep
));
3602 for (i
= 0; i
< 8; i
++)
3603 ax_reg_mask (ax
, I387_ST0_REGNUM (tdep
) + i
);
3606 else if (i386_bnd_regnum_p (gdbarch
, regnum
))
3608 regnum
-= tdep
->bnd0_regnum
;
3609 ax_reg_mask (ax
, I387_BND0R_REGNUM (tdep
) + regnum
);
3612 else if (i386_k_regnum_p (gdbarch
, regnum
))
3614 regnum
-= tdep
->k0_regnum
;
3615 ax_reg_mask (ax
, tdep
->k0_regnum
+ regnum
);
3618 else if (i386_zmm_regnum_p (gdbarch
, regnum
))
3620 regnum
-= tdep
->zmm0_regnum
;
3621 if (regnum
< num_lower_zmm_regs
)
3623 ax_reg_mask (ax
, I387_XMM0_REGNUM (tdep
) + regnum
);
3624 ax_reg_mask (ax
, tdep
->ymm0h_regnum
+ regnum
);
3628 ax_reg_mask (ax
, I387_XMM16_REGNUM (tdep
) + regnum
3629 - num_lower_zmm_regs
);
3630 ax_reg_mask (ax
, I387_YMM16H_REGNUM (tdep
) + regnum
3631 - num_lower_zmm_regs
);
3633 ax_reg_mask (ax
, tdep
->zmm0h_regnum
+ regnum
);
3636 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
3638 regnum
-= tdep
->ymm0_regnum
;
3639 ax_reg_mask (ax
, I387_XMM0_REGNUM (tdep
) + regnum
);
3640 ax_reg_mask (ax
, tdep
->ymm0h_regnum
+ regnum
);
3643 else if (i386_ymm_avx512_regnum_p (gdbarch
, regnum
))
3645 regnum
-= tdep
->ymm16_regnum
;
3646 ax_reg_mask (ax
, I387_XMM16_REGNUM (tdep
) + regnum
);
3647 ax_reg_mask (ax
, tdep
->ymm16h_regnum
+ regnum
);
3650 else if (i386_word_regnum_p (gdbarch
, regnum
))
3652 int gpnum
= regnum
- tdep
->ax_regnum
;
3654 ax_reg_mask (ax
, gpnum
);
3657 else if (i386_byte_regnum_p (gdbarch
, regnum
))
3659 int gpnum
= regnum
- tdep
->al_regnum
;
3661 ax_reg_mask (ax
, gpnum
% 4);
3665 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
3670 /* Return the register number of the register allocated by GCC after
3671 REGNUM, or -1 if there is no such register. */
3674 i386_next_regnum (int regnum
)
3676 /* GCC allocates the registers in the order:
3678 %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ...
3680 Since storing a variable in %esp doesn't make any sense we return
3681 -1 for %ebp and for %esp itself. */
3682 static int next_regnum
[] =
3684 I386_EDX_REGNUM
, /* Slot for %eax. */
3685 I386_EBX_REGNUM
, /* Slot for %ecx. */
3686 I386_ECX_REGNUM
, /* Slot for %edx. */
3687 I386_ESI_REGNUM
, /* Slot for %ebx. */
3688 -1, -1, /* Slots for %esp and %ebp. */
3689 I386_EDI_REGNUM
, /* Slot for %esi. */
3690 I386_EBP_REGNUM
/* Slot for %edi. */
3693 if (regnum
>= 0 && regnum
< sizeof (next_regnum
) / sizeof (next_regnum
[0]))
3694 return next_regnum
[regnum
];
3699 /* Return nonzero if a value of type TYPE stored in register REGNUM
3700 needs any special handling. */
3703 i386_convert_register_p (struct gdbarch
*gdbarch
,
3704 int regnum
, struct type
*type
)
3706 int len
= TYPE_LENGTH (type
);
3708 /* Values may be spread across multiple registers. Most debugging
3709 formats aren't expressive enough to specify the locations, so
3710 some heuristics is involved. Right now we only handle types that
3711 have a length that is a multiple of the word size, since GCC
3712 doesn't seem to put any other types into registers. */
3713 if (len
> 4 && len
% 4 == 0)
3715 int last_regnum
= regnum
;
3719 last_regnum
= i386_next_regnum (last_regnum
);
3723 if (last_regnum
!= -1)
3727 return i387_convert_register_p (gdbarch
, regnum
, type
);
3730 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
3731 return its contents in TO. */
3734 i386_register_to_value (struct frame_info
*frame
, int regnum
,
3735 struct type
*type
, gdb_byte
*to
,
3736 int *optimizedp
, int *unavailablep
)
3738 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3739 int len
= TYPE_LENGTH (type
);
3741 if (i386_fp_regnum_p (gdbarch
, regnum
))
3742 return i387_register_to_value (frame
, regnum
, type
, to
,
3743 optimizedp
, unavailablep
);
3745 /* Read a value spread across multiple registers. */
3747 gdb_assert (len
> 4 && len
% 4 == 0);
3751 gdb_assert (regnum
!= -1);
3752 gdb_assert (register_size (gdbarch
, regnum
) == 4);
3754 if (!get_frame_register_bytes (frame
, regnum
, 0,
3755 register_size (gdbarch
, regnum
),
3756 to
, optimizedp
, unavailablep
))
3759 regnum
= i386_next_regnum (regnum
);
3764 *optimizedp
= *unavailablep
= 0;
3768 /* Write the contents FROM of a value of type TYPE into register
3769 REGNUM in frame FRAME. */
3772 i386_value_to_register (struct frame_info
*frame
, int regnum
,
3773 struct type
*type
, const gdb_byte
*from
)
3775 int len
= TYPE_LENGTH (type
);
3777 if (i386_fp_regnum_p (get_frame_arch (frame
), regnum
))
3779 i387_value_to_register (frame
, regnum
, type
, from
);
3783 /* Write a value spread across multiple registers. */
3785 gdb_assert (len
> 4 && len
% 4 == 0);
3789 gdb_assert (regnum
!= -1);
3790 gdb_assert (register_size (get_frame_arch (frame
), regnum
) == 4);
3792 put_frame_register (frame
, regnum
, from
);
3793 regnum
= i386_next_regnum (regnum
);
3799 /* Supply register REGNUM from the buffer specified by GREGS and LEN
3800 in the general-purpose register set REGSET to register cache
3801 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3804 i386_supply_gregset (const struct regset
*regset
, struct regcache
*regcache
,
3805 int regnum
, const void *gregs
, size_t len
)
3807 struct gdbarch
*gdbarch
= regcache
->arch ();
3808 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3809 const gdb_byte
*regs
= (const gdb_byte
*) gregs
;
3812 gdb_assert (len
>= tdep
->sizeof_gregset
);
3814 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
3816 if ((regnum
== i
|| regnum
== -1)
3817 && tdep
->gregset_reg_offset
[i
] != -1)
3818 regcache
->raw_supply (i
, regs
+ tdep
->gregset_reg_offset
[i
]);
3822 /* Collect register REGNUM from the register cache REGCACHE and store
3823 it in the buffer specified by GREGS and LEN as described by the
3824 general-purpose register set REGSET. If REGNUM is -1, do this for
3825 all registers in REGSET. */
3828 i386_collect_gregset (const struct regset
*regset
,
3829 const struct regcache
*regcache
,
3830 int regnum
, void *gregs
, size_t len
)
3832 struct gdbarch
*gdbarch
= regcache
->arch ();
3833 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3834 gdb_byte
*regs
= (gdb_byte
*) gregs
;
3837 gdb_assert (len
>= tdep
->sizeof_gregset
);
3839 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
3841 if ((regnum
== i
|| regnum
== -1)
3842 && tdep
->gregset_reg_offset
[i
] != -1)
3843 regcache
->raw_collect (i
, regs
+ tdep
->gregset_reg_offset
[i
]);
3847 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
3848 in the floating-point register set REGSET to register cache
3849 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3852 i386_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
3853 int regnum
, const void *fpregs
, size_t len
)
3855 struct gdbarch
*gdbarch
= regcache
->arch ();
3856 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3858 if (len
== I387_SIZEOF_FXSAVE
)
3860 i387_supply_fxsave (regcache
, regnum
, fpregs
);
3864 gdb_assert (len
>= tdep
->sizeof_fpregset
);
3865 i387_supply_fsave (regcache
, regnum
, fpregs
);
3868 /* Collect register REGNUM from the register cache REGCACHE and store
3869 it in the buffer specified by FPREGS and LEN as described by the
3870 floating-point register set REGSET. If REGNUM is -1, do this for
3871 all registers in REGSET. */
3874 i386_collect_fpregset (const struct regset
*regset
,
3875 const struct regcache
*regcache
,
3876 int regnum
, void *fpregs
, size_t len
)
3878 struct gdbarch
*gdbarch
= regcache
->arch ();
3879 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3881 if (len
== I387_SIZEOF_FXSAVE
)
3883 i387_collect_fxsave (regcache
, regnum
, fpregs
);
3887 gdb_assert (len
>= tdep
->sizeof_fpregset
);
3888 i387_collect_fsave (regcache
, regnum
, fpregs
);
3891 /* Register set definitions. */
3893 const struct regset i386_gregset
=
3895 NULL
, i386_supply_gregset
, i386_collect_gregset
3898 const struct regset i386_fpregset
=
3900 NULL
, i386_supply_fpregset
, i386_collect_fpregset
3903 /* Default iterator over core file register note sections. */
3906 i386_iterate_over_regset_sections (struct gdbarch
*gdbarch
,
3907 iterate_over_regset_sections_cb
*cb
,
3909 const struct regcache
*regcache
)
3911 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3913 cb (".reg", tdep
->sizeof_gregset
, tdep
->sizeof_gregset
, &i386_gregset
, NULL
,
3915 if (tdep
->sizeof_fpregset
)
3916 cb (".reg2", tdep
->sizeof_fpregset
, tdep
->sizeof_fpregset
, tdep
->fpregset
,
3921 /* Stuff for WIN32 PE style DLL's but is pretty generic really. */
3924 i386_pe_skip_trampoline_code (struct frame_info
*frame
,
3925 CORE_ADDR pc
, char *name
)
3927 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3928 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3931 if (pc
&& read_memory_unsigned_integer (pc
, 2, byte_order
) == 0x25ff)
3933 unsigned long indirect
=
3934 read_memory_unsigned_integer (pc
+ 2, 4, byte_order
);
3935 struct minimal_symbol
*indsym
=
3936 indirect
? lookup_minimal_symbol_by_pc (indirect
).minsym
: 0;
3937 const char *symname
= indsym
? MSYMBOL_LINKAGE_NAME (indsym
) : 0;
3941 if (startswith (symname
, "__imp_")
3942 || startswith (symname
, "_imp_"))
3944 read_memory_unsigned_integer (indirect
, 4, byte_order
);
3947 return 0; /* Not a trampoline. */
3951 /* Return whether the THIS_FRAME corresponds to a sigtramp
3955 i386_sigtramp_p (struct frame_info
*this_frame
)
3957 CORE_ADDR pc
= get_frame_pc (this_frame
);
3960 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
3961 return (name
&& strcmp ("_sigtramp", name
) == 0);
3965 /* We have two flavours of disassembly. The machinery on this page
3966 deals with switching between those. */
3969 i386_print_insn (bfd_vma pc
, struct disassemble_info
*info
)
3971 gdb_assert (disassembly_flavor
== att_flavor
3972 || disassembly_flavor
== intel_flavor
);
3974 info
->disassembler_options
= disassembly_flavor
;
3976 return default_print_insn (pc
, info
);
3980 /* There are a few i386 architecture variants that differ only
3981 slightly from the generic i386 target. For now, we don't give them
3982 their own source file, but include them here. As a consequence,
3983 they'll always be included. */
3985 /* System V Release 4 (SVR4). */
3987 /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp
3991 i386_svr4_sigtramp_p (struct frame_info
*this_frame
)
3993 CORE_ADDR pc
= get_frame_pc (this_frame
);
3996 /* The origin of these symbols is currently unknown. */
3997 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
3998 return (name
&& (strcmp ("_sigreturn", name
) == 0
3999 || strcmp ("sigvechandler", name
) == 0));
4002 /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the
4003 address of the associated sigcontext (ucontext) structure. */
4006 i386_svr4_sigcontext_addr (struct frame_info
*this_frame
)
4008 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
4009 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4013 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
4014 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
4016 return read_memory_unsigned_integer (sp
+ 8, 4, byte_order
);
4021 /* Implementation of `gdbarch_stap_is_single_operand', as defined in
4025 i386_stap_is_single_operand (struct gdbarch
*gdbarch
, const char *s
)
4027 return (*s
== '$' /* Literal number. */
4028 || (isdigit (*s
) && s
[1] == '(' && s
[2] == '%') /* Displacement. */
4029 || (*s
== '(' && s
[1] == '%') /* Register indirection. */
4030 || (*s
== '%' && isalpha (s
[1]))); /* Register access. */
4033 /* Helper function for i386_stap_parse_special_token.
4035 This function parses operands of the form `-8+3+1(%rbp)', which
4036 must be interpreted as `*(-8 + 3 - 1 + (void *) $eax)'.
4038 Return 1 if the operand was parsed successfully, zero
4042 i386_stap_parse_special_token_triplet (struct gdbarch
*gdbarch
,
4043 struct stap_parse_info
*p
)
4045 const char *s
= p
->arg
;
4047 if (isdigit (*s
) || *s
== '-' || *s
== '+')
4051 long displacements
[3];
4067 if (!isdigit ((unsigned char) *s
))
4070 displacements
[0] = strtol (s
, &endp
, 10);
4073 if (*s
!= '+' && *s
!= '-')
4075 /* We are not dealing with a triplet. */
4088 if (!isdigit ((unsigned char) *s
))
4091 displacements
[1] = strtol (s
, &endp
, 10);
4094 if (*s
!= '+' && *s
!= '-')
4096 /* We are not dealing with a triplet. */
4109 if (!isdigit ((unsigned char) *s
))
4112 displacements
[2] = strtol (s
, &endp
, 10);
4115 if (*s
!= '(' || s
[1] != '%')
4121 while (isalnum (*s
))
4127 len
= s
- start
- 1;
4128 regname
= (char *) alloca (len
+ 1);
4130 strncpy (regname
, start
, len
);
4131 regname
[len
] = '\0';
4133 if (user_reg_map_name_to_regnum (gdbarch
, regname
, len
) == -1)
4134 error (_("Invalid register name `%s' on expression `%s'."),
4135 regname
, p
->saved_arg
);
4137 for (i
= 0; i
< 3; i
++)
4139 write_exp_elt_opcode (&p
->pstate
, OP_LONG
);
4141 (&p
->pstate
, builtin_type (gdbarch
)->builtin_long
);
4142 write_exp_elt_longcst (&p
->pstate
, displacements
[i
]);
4143 write_exp_elt_opcode (&p
->pstate
, OP_LONG
);
4145 write_exp_elt_opcode (&p
->pstate
, UNOP_NEG
);
4148 write_exp_elt_opcode (&p
->pstate
, OP_REGISTER
);
4151 write_exp_string (&p
->pstate
, str
);
4152 write_exp_elt_opcode (&p
->pstate
, OP_REGISTER
);
4154 write_exp_elt_opcode (&p
->pstate
, UNOP_CAST
);
4155 write_exp_elt_type (&p
->pstate
,
4156 builtin_type (gdbarch
)->builtin_data_ptr
);
4157 write_exp_elt_opcode (&p
->pstate
, UNOP_CAST
);
4159 write_exp_elt_opcode (&p
->pstate
, BINOP_ADD
);
4160 write_exp_elt_opcode (&p
->pstate
, BINOP_ADD
);
4161 write_exp_elt_opcode (&p
->pstate
, BINOP_ADD
);
4163 write_exp_elt_opcode (&p
->pstate
, UNOP_CAST
);
4164 write_exp_elt_type (&p
->pstate
,
4165 lookup_pointer_type (p
->arg_type
));
4166 write_exp_elt_opcode (&p
->pstate
, UNOP_CAST
);
4168 write_exp_elt_opcode (&p
->pstate
, UNOP_IND
);
4178 /* Helper function for i386_stap_parse_special_token.
4180 This function parses operands of the form `register base +
4181 (register index * size) + offset', as represented in
4182 `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'.
4184 Return 1 if the operand was parsed successfully, zero
4188 i386_stap_parse_special_token_three_arg_disp (struct gdbarch
*gdbarch
,
4189 struct stap_parse_info
*p
)
4191 const char *s
= p
->arg
;
4193 if (isdigit (*s
) || *s
== '(' || *s
== '-' || *s
== '+')
4195 int offset_minus
= 0;
4204 struct stoken base_token
, index_token
;
4214 if (offset_minus
&& !isdigit (*s
))
4221 offset
= strtol (s
, &endp
, 10);
4225 if (*s
!= '(' || s
[1] != '%')
4231 while (isalnum (*s
))
4234 if (*s
!= ',' || s
[1] != '%')
4237 len_base
= s
- start
;
4238 base
= (char *) alloca (len_base
+ 1);
4239 strncpy (base
, start
, len_base
);
4240 base
[len_base
] = '\0';
4242 if (user_reg_map_name_to_regnum (gdbarch
, base
, len_base
) == -1)
4243 error (_("Invalid register name `%s' on expression `%s'."),
4244 base
, p
->saved_arg
);
4249 while (isalnum (*s
))
4252 len_index
= s
- start
;
4253 index
= (char *) alloca (len_index
+ 1);
4254 strncpy (index
, start
, len_index
);
4255 index
[len_index
] = '\0';
4257 if (user_reg_map_name_to_regnum (gdbarch
, index
, len_index
) == -1)
4258 error (_("Invalid register name `%s' on expression `%s'."),
4259 index
, p
->saved_arg
);
4261 if (*s
!= ',' && *s
!= ')')
4277 size
= strtol (s
, &endp
, 10);
4288 write_exp_elt_opcode (&p
->pstate
, OP_LONG
);
4289 write_exp_elt_type (&p
->pstate
,
4290 builtin_type (gdbarch
)->builtin_long
);
4291 write_exp_elt_longcst (&p
->pstate
, offset
);
4292 write_exp_elt_opcode (&p
->pstate
, OP_LONG
);
4294 write_exp_elt_opcode (&p
->pstate
, UNOP_NEG
);
4297 write_exp_elt_opcode (&p
->pstate
, OP_REGISTER
);
4298 base_token
.ptr
= base
;
4299 base_token
.length
= len_base
;
4300 write_exp_string (&p
->pstate
, base_token
);
4301 write_exp_elt_opcode (&p
->pstate
, OP_REGISTER
);
4304 write_exp_elt_opcode (&p
->pstate
, BINOP_ADD
);
4306 write_exp_elt_opcode (&p
->pstate
, OP_REGISTER
);
4307 index_token
.ptr
= index
;
4308 index_token
.length
= len_index
;
4309 write_exp_string (&p
->pstate
, index_token
);
4310 write_exp_elt_opcode (&p
->pstate
, OP_REGISTER
);
4314 write_exp_elt_opcode (&p
->pstate
, OP_LONG
);
4315 write_exp_elt_type (&p
->pstate
,
4316 builtin_type (gdbarch
)->builtin_long
);
4317 write_exp_elt_longcst (&p
->pstate
, size
);
4318 write_exp_elt_opcode (&p
->pstate
, OP_LONG
);
4320 write_exp_elt_opcode (&p
->pstate
, UNOP_NEG
);
4321 write_exp_elt_opcode (&p
->pstate
, BINOP_MUL
);
4324 write_exp_elt_opcode (&p
->pstate
, BINOP_ADD
);
4326 write_exp_elt_opcode (&p
->pstate
, UNOP_CAST
);
4327 write_exp_elt_type (&p
->pstate
,
4328 lookup_pointer_type (p
->arg_type
));
4329 write_exp_elt_opcode (&p
->pstate
, UNOP_CAST
);
4331 write_exp_elt_opcode (&p
->pstate
, UNOP_IND
);
4341 /* Implementation of `gdbarch_stap_parse_special_token', as defined in
4345 i386_stap_parse_special_token (struct gdbarch
*gdbarch
,
4346 struct stap_parse_info
*p
)
4348 /* In order to parse special tokens, we use a state-machine that go
4349 through every known token and try to get a match. */
4353 THREE_ARG_DISPLACEMENT
,
4358 current_state
= TRIPLET
;
4360 /* The special tokens to be parsed here are:
4362 - `register base + (register index * size) + offset', as represented
4363 in `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'.
4365 - Operands of the form `-8+3+1(%rbp)', which must be interpreted as
4366 `*(-8 + 3 - 1 + (void *) $eax)'. */
4368 while (current_state
!= DONE
)
4370 switch (current_state
)
4373 if (i386_stap_parse_special_token_triplet (gdbarch
, p
))
4377 case THREE_ARG_DISPLACEMENT
:
4378 if (i386_stap_parse_special_token_three_arg_disp (gdbarch
, p
))
4383 /* Advancing to the next state. */
4392 /* gdbarch gnu_triplet_regexp method. Both arches are acceptable as GDB always
4393 also supplies -m64 or -m32 by gdbarch_gcc_target_options. */
4396 i386_gnu_triplet_regexp (struct gdbarch
*gdbarch
)
4398 return "(x86_64|i.86)";
4403 /* Implement the "in_indirect_branch_thunk" gdbarch function. */
4406 i386_in_indirect_branch_thunk (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4408 return x86_in_indirect_branch_thunk (pc
, i386_register_names
,
4409 I386_EAX_REGNUM
, I386_EIP_REGNUM
);
4415 i386_elf_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
4417 static const char *const stap_integer_prefixes
[] = { "$", NULL
};
4418 static const char *const stap_register_prefixes
[] = { "%", NULL
};
4419 static const char *const stap_register_indirection_prefixes
[] = { "(",
4421 static const char *const stap_register_indirection_suffixes
[] = { ")",
4424 /* We typically use stabs-in-ELF with the SVR4 register numbering. */
4425 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
4427 /* Registering SystemTap handlers. */
4428 set_gdbarch_stap_integer_prefixes (gdbarch
, stap_integer_prefixes
);
4429 set_gdbarch_stap_register_prefixes (gdbarch
, stap_register_prefixes
);
4430 set_gdbarch_stap_register_indirection_prefixes (gdbarch
,
4431 stap_register_indirection_prefixes
);
4432 set_gdbarch_stap_register_indirection_suffixes (gdbarch
,
4433 stap_register_indirection_suffixes
);
4434 set_gdbarch_stap_is_single_operand (gdbarch
,
4435 i386_stap_is_single_operand
);
4436 set_gdbarch_stap_parse_special_token (gdbarch
,
4437 i386_stap_parse_special_token
);
4439 set_gdbarch_in_indirect_branch_thunk (gdbarch
,
4440 i386_in_indirect_branch_thunk
);
4443 /* System V Release 4 (SVR4). */
4446 i386_svr4_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
4448 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4450 /* System V Release 4 uses ELF. */
4451 i386_elf_init_abi (info
, gdbarch
);
4453 /* System V Release 4 has shared libraries. */
4454 set_gdbarch_skip_trampoline_code (gdbarch
, find_solib_trampoline_target
);
4456 tdep
->sigtramp_p
= i386_svr4_sigtramp_p
;
4457 tdep
->sigcontext_addr
= i386_svr4_sigcontext_addr
;
4458 tdep
->sc_pc_offset
= 36 + 14 * 4;
4459 tdep
->sc_sp_offset
= 36 + 17 * 4;
4461 tdep
->jb_pc_offset
= 20;
4466 /* i386 register groups. In addition to the normal groups, add "mmx"
4469 static struct reggroup
*i386_sse_reggroup
;
4470 static struct reggroup
*i386_mmx_reggroup
;
4473 i386_init_reggroups (void)
4475 i386_sse_reggroup
= reggroup_new ("sse", USER_REGGROUP
);
4476 i386_mmx_reggroup
= reggroup_new ("mmx", USER_REGGROUP
);
4480 i386_add_reggroups (struct gdbarch
*gdbarch
)
4482 reggroup_add (gdbarch
, i386_sse_reggroup
);
4483 reggroup_add (gdbarch
, i386_mmx_reggroup
);
4484 reggroup_add (gdbarch
, general_reggroup
);
4485 reggroup_add (gdbarch
, float_reggroup
);
4486 reggroup_add (gdbarch
, all_reggroup
);
4487 reggroup_add (gdbarch
, save_reggroup
);
4488 reggroup_add (gdbarch
, restore_reggroup
);
4489 reggroup_add (gdbarch
, vector_reggroup
);
4490 reggroup_add (gdbarch
, system_reggroup
);
4494 i386_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
4495 struct reggroup
*group
)
4497 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4498 int fp_regnum_p
, mmx_regnum_p
, xmm_regnum_p
, mxcsr_regnum_p
,
4499 ymm_regnum_p
, ymmh_regnum_p
, ymm_avx512_regnum_p
, ymmh_avx512_regnum_p
,
4500 bndr_regnum_p
, bnd_regnum_p
, zmm_regnum_p
, zmmh_regnum_p
,
4501 mpx_ctrl_regnum_p
, xmm_avx512_regnum_p
,
4502 avx512_p
, avx_p
, sse_p
, pkru_regnum_p
;
4504 /* Don't include pseudo registers, except for MMX, in any register
4506 if (i386_byte_regnum_p (gdbarch
, regnum
))
4509 if (i386_word_regnum_p (gdbarch
, regnum
))
4512 if (i386_dword_regnum_p (gdbarch
, regnum
))
4515 mmx_regnum_p
= i386_mmx_regnum_p (gdbarch
, regnum
);
4516 if (group
== i386_mmx_reggroup
)
4517 return mmx_regnum_p
;
4519 pkru_regnum_p
= i386_pkru_regnum_p(gdbarch
, regnum
);
4520 xmm_regnum_p
= i386_xmm_regnum_p (gdbarch
, regnum
);
4521 xmm_avx512_regnum_p
= i386_xmm_avx512_regnum_p (gdbarch
, regnum
);
4522 mxcsr_regnum_p
= i386_mxcsr_regnum_p (gdbarch
, regnum
);
4523 if (group
== i386_sse_reggroup
)
4524 return xmm_regnum_p
|| xmm_avx512_regnum_p
|| mxcsr_regnum_p
;
4526 ymm_regnum_p
= i386_ymm_regnum_p (gdbarch
, regnum
);
4527 ymm_avx512_regnum_p
= i386_ymm_avx512_regnum_p (gdbarch
, regnum
);
4528 zmm_regnum_p
= i386_zmm_regnum_p (gdbarch
, regnum
);
4530 avx512_p
= ((tdep
->xcr0
& X86_XSTATE_AVX_AVX512_MASK
)
4531 == X86_XSTATE_AVX_AVX512_MASK
);
4532 avx_p
= ((tdep
->xcr0
& X86_XSTATE_AVX_AVX512_MASK
)
4533 == X86_XSTATE_AVX_MASK
) && !avx512_p
;
4534 sse_p
= ((tdep
->xcr0
& X86_XSTATE_AVX_AVX512_MASK
)
4535 == X86_XSTATE_SSE_MASK
) && !avx512_p
&& ! avx_p
;
4537 if (group
== vector_reggroup
)
4538 return (mmx_regnum_p
4539 || (zmm_regnum_p
&& avx512_p
)
4540 || ((ymm_regnum_p
|| ymm_avx512_regnum_p
) && avx_p
)
4541 || ((xmm_regnum_p
|| xmm_avx512_regnum_p
) && sse_p
)
4544 fp_regnum_p
= (i386_fp_regnum_p (gdbarch
, regnum
)
4545 || i386_fpc_regnum_p (gdbarch
, regnum
));
4546 if (group
== float_reggroup
)
4549 /* For "info reg all", don't include upper YMM registers nor XMM
4550 registers when AVX is supported. */
4551 ymmh_regnum_p
= i386_ymmh_regnum_p (gdbarch
, regnum
);
4552 ymmh_avx512_regnum_p
= i386_ymmh_avx512_regnum_p (gdbarch
, regnum
);
4553 zmmh_regnum_p
= i386_zmmh_regnum_p (gdbarch
, regnum
);
4554 if (group
== all_reggroup
4555 && (((xmm_regnum_p
|| xmm_avx512_regnum_p
) && !sse_p
)
4556 || ((ymm_regnum_p
|| ymm_avx512_regnum_p
) && !avx_p
)
4558 || ymmh_avx512_regnum_p
4562 bnd_regnum_p
= i386_bnd_regnum_p (gdbarch
, regnum
);
4563 if (group
== all_reggroup
4564 && ((bnd_regnum_p
&& (tdep
->xcr0
& X86_XSTATE_MPX_MASK
))))
4565 return bnd_regnum_p
;
4567 bndr_regnum_p
= i386_bndr_regnum_p (gdbarch
, regnum
);
4568 if (group
== all_reggroup
4569 && ((bndr_regnum_p
&& (tdep
->xcr0
& X86_XSTATE_MPX_MASK
))))
4572 mpx_ctrl_regnum_p
= i386_mpx_ctrl_regnum_p (gdbarch
, regnum
);
4573 if (group
== all_reggroup
4574 && ((mpx_ctrl_regnum_p
&& (tdep
->xcr0
& X86_XSTATE_MPX_MASK
))))
4575 return mpx_ctrl_regnum_p
;
4577 if (group
== general_reggroup
)
4578 return (!fp_regnum_p
4582 && !xmm_avx512_regnum_p
4585 && !ymm_avx512_regnum_p
4586 && !ymmh_avx512_regnum_p
4589 && !mpx_ctrl_regnum_p
4594 return default_register_reggroup_p (gdbarch
, regnum
, group
);
4598 /* Get the ARGIth function argument for the current function. */
4601 i386_fetch_pointer_argument (struct frame_info
*frame
, int argi
,
4604 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4605 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4606 CORE_ADDR sp
= get_frame_register_unsigned (frame
, I386_ESP_REGNUM
);
4607 return read_memory_unsigned_integer (sp
+ (4 * (argi
+ 1)), 4, byte_order
);
4610 #define PREFIX_REPZ 0x01
4611 #define PREFIX_REPNZ 0x02
4612 #define PREFIX_LOCK 0x04
4613 #define PREFIX_DATA 0x08
4614 #define PREFIX_ADDR 0x10
4626 /* i386 arith/logic operations */
4639 struct i386_record_s
4641 struct gdbarch
*gdbarch
;
4642 struct regcache
*regcache
;
4643 CORE_ADDR orig_addr
;
4649 uint8_t mod
, reg
, rm
;
4658 /* Parse the "modrm" part of the memory address irp->addr points at.
4659 Returns -1 if something goes wrong, 0 otherwise. */
4662 i386_record_modrm (struct i386_record_s
*irp
)
4664 struct gdbarch
*gdbarch
= irp
->gdbarch
;
4666 if (record_read_memory (gdbarch
, irp
->addr
, &irp
->modrm
, 1))
4670 irp
->mod
= (irp
->modrm
>> 6) & 3;
4671 irp
->reg
= (irp
->modrm
>> 3) & 7;
4672 irp
->rm
= irp
->modrm
& 7;
4677 /* Extract the memory address that the current instruction writes to,
4678 and return it in *ADDR. Return -1 if something goes wrong. */
4681 i386_record_lea_modrm_addr (struct i386_record_s
*irp
, uint64_t *addr
)
4683 struct gdbarch
*gdbarch
= irp
->gdbarch
;
4684 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4689 if (irp
->aflag
|| irp
->regmap
[X86_RECORD_R8_REGNUM
])
4696 uint8_t base
= irp
->rm
;
4701 if (record_read_memory (gdbarch
, irp
->addr
, &byte
, 1))
4704 scale
= (byte
>> 6) & 3;
4705 index
= ((byte
>> 3) & 7) | irp
->rex_x
;
4713 if ((base
& 7) == 5)
4716 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 4))
4719 *addr
= extract_signed_integer (buf
, 4, byte_order
);
4720 if (irp
->regmap
[X86_RECORD_R8_REGNUM
] && !havesib
)
4721 *addr
+= irp
->addr
+ irp
->rip_offset
;
4725 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 1))
4728 *addr
= (int8_t) buf
[0];
4731 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 4))
4733 *addr
= extract_signed_integer (buf
, 4, byte_order
);
4741 if (base
== 4 && irp
->popl_esp_hack
)
4742 *addr
+= irp
->popl_esp_hack
;
4743 regcache_raw_read_unsigned (irp
->regcache
, irp
->regmap
[base
],
4746 if (irp
->aflag
== 2)
4751 *addr
= (uint32_t) (offset64
+ *addr
);
4753 if (havesib
&& (index
!= 4 || scale
!= 0))
4755 regcache_raw_read_unsigned (irp
->regcache
, irp
->regmap
[index
],
4757 if (irp
->aflag
== 2)
4758 *addr
+= offset64
<< scale
;
4760 *addr
= (uint32_t) (*addr
+ (offset64
<< scale
));
4765 /* Since we are in 64-bit mode with ADDR32 prefix, zero-extend
4766 address from 32-bit to 64-bit. */
4767 *addr
= (uint32_t) *addr
;
4778 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 2))
4781 *addr
= extract_signed_integer (buf
, 2, byte_order
);
4787 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 1))
4790 *addr
= (int8_t) buf
[0];
4793 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 2))
4796 *addr
= extract_signed_integer (buf
, 2, byte_order
);
4803 regcache_raw_read_unsigned (irp
->regcache
,
4804 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
4806 *addr
= (uint32_t) (*addr
+ offset64
);
4807 regcache_raw_read_unsigned (irp
->regcache
,
4808 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
4810 *addr
= (uint32_t) (*addr
+ offset64
);
4813 regcache_raw_read_unsigned (irp
->regcache
,
4814 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
4816 *addr
= (uint32_t) (*addr
+ offset64
);
4817 regcache_raw_read_unsigned (irp
->regcache
,
4818 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
4820 *addr
= (uint32_t) (*addr
+ offset64
);
4823 regcache_raw_read_unsigned (irp
->regcache
,
4824 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
4826 *addr
= (uint32_t) (*addr
+ offset64
);
4827 regcache_raw_read_unsigned (irp
->regcache
,
4828 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
4830 *addr
= (uint32_t) (*addr
+ offset64
);
4833 regcache_raw_read_unsigned (irp
->regcache
,
4834 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
4836 *addr
= (uint32_t) (*addr
+ offset64
);
4837 regcache_raw_read_unsigned (irp
->regcache
,
4838 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
4840 *addr
= (uint32_t) (*addr
+ offset64
);
4843 regcache_raw_read_unsigned (irp
->regcache
,
4844 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
4846 *addr
= (uint32_t) (*addr
+ offset64
);
4849 regcache_raw_read_unsigned (irp
->regcache
,
4850 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
4852 *addr
= (uint32_t) (*addr
+ offset64
);
4855 regcache_raw_read_unsigned (irp
->regcache
,
4856 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
4858 *addr
= (uint32_t) (*addr
+ offset64
);
4861 regcache_raw_read_unsigned (irp
->regcache
,
4862 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
4864 *addr
= (uint32_t) (*addr
+ offset64
);
4874 /* Record the address and contents of the memory that will be changed
4875 by the current instruction. Return -1 if something goes wrong, 0
4879 i386_record_lea_modrm (struct i386_record_s
*irp
)
4881 struct gdbarch
*gdbarch
= irp
->gdbarch
;
4884 if (irp
->override
>= 0)
4886 if (record_full_memory_query
)
4889 Process record ignores the memory change of instruction at address %s\n\
4890 because it can't get the value of the segment register.\n\
4891 Do you want to stop the program?"),
4892 paddress (gdbarch
, irp
->orig_addr
)))
4899 if (i386_record_lea_modrm_addr (irp
, &addr
))
4902 if (record_full_arch_list_add_mem (addr
, 1 << irp
->ot
))
4908 /* Record the effects of a push operation. Return -1 if something
4909 goes wrong, 0 otherwise. */
4912 i386_record_push (struct i386_record_s
*irp
, int size
)
4916 if (record_full_arch_list_add_reg (irp
->regcache
,
4917 irp
->regmap
[X86_RECORD_RESP_REGNUM
]))
4919 regcache_raw_read_unsigned (irp
->regcache
,
4920 irp
->regmap
[X86_RECORD_RESP_REGNUM
],
4922 if (record_full_arch_list_add_mem ((CORE_ADDR
) addr
- size
, size
))
4929 /* Defines contents to record. */
4930 #define I386_SAVE_FPU_REGS 0xfffd
4931 #define I386_SAVE_FPU_ENV 0xfffe
4932 #define I386_SAVE_FPU_ENV_REG_STACK 0xffff
4934 /* Record the values of the floating point registers which will be
4935 changed by the current instruction. Returns -1 if something is
4936 wrong, 0 otherwise. */
4938 static int i386_record_floats (struct gdbarch
*gdbarch
,
4939 struct i386_record_s
*ir
,
4942 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4945 /* Oza: Because of floating point insn push/pop of fpu stack is going to
4946 happen. Currently we store st0-st7 registers, but we need not store all
4947 registers all the time, in future we use ftag register and record only
4948 those who are not marked as an empty. */
4950 if (I386_SAVE_FPU_REGS
== iregnum
)
4952 for (i
= I387_ST0_REGNUM (tdep
); i
<= I387_ST0_REGNUM (tdep
) + 7; i
++)
4954 if (record_full_arch_list_add_reg (ir
->regcache
, i
))
4958 else if (I386_SAVE_FPU_ENV
== iregnum
)
4960 for (i
= I387_FCTRL_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
4962 if (record_full_arch_list_add_reg (ir
->regcache
, i
))
4966 else if (I386_SAVE_FPU_ENV_REG_STACK
== iregnum
)
4968 for (i
= I387_ST0_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
4970 if (record_full_arch_list_add_reg (ir
->regcache
, i
))
4974 else if ((iregnum
>= I387_ST0_REGNUM (tdep
)) &&
4975 (iregnum
<= I387_FOP_REGNUM (tdep
)))
4977 if (record_full_arch_list_add_reg (ir
->regcache
,iregnum
))
4982 /* Parameter error. */
4985 if(I386_SAVE_FPU_ENV
!= iregnum
)
4987 for (i
= I387_FCTRL_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
4989 if (record_full_arch_list_add_reg (ir
->regcache
, i
))
4996 /* Parse the current instruction, and record the values of the
4997 registers and memory that will be changed by the current
4998 instruction. Returns -1 if something goes wrong, 0 otherwise. */
5000 #define I386_RECORD_FULL_ARCH_LIST_ADD_REG(regnum) \
5001 record_full_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)])
5004 i386_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5005 CORE_ADDR input_addr
)
5007 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5013 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
5014 struct i386_record_s ir
;
5015 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5019 memset (&ir
, 0, sizeof (struct i386_record_s
));
5020 ir
.regcache
= regcache
;
5021 ir
.addr
= input_addr
;
5022 ir
.orig_addr
= input_addr
;
5026 ir
.popl_esp_hack
= 0;
5027 ir
.regmap
= tdep
->record_regmap
;
5028 ir
.gdbarch
= gdbarch
;
5030 if (record_debug
> 1)
5031 fprintf_unfiltered (gdb_stdlog
, "Process record: i386_process_record "
5033 paddress (gdbarch
, ir
.addr
));
5038 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
5041 switch (opcode8
) /* Instruction prefixes */
5043 case REPE_PREFIX_OPCODE
:
5044 prefixes
|= PREFIX_REPZ
;
5046 case REPNE_PREFIX_OPCODE
:
5047 prefixes
|= PREFIX_REPNZ
;
5049 case LOCK_PREFIX_OPCODE
:
5050 prefixes
|= PREFIX_LOCK
;
5052 case CS_PREFIX_OPCODE
:
5053 ir
.override
= X86_RECORD_CS_REGNUM
;
5055 case SS_PREFIX_OPCODE
:
5056 ir
.override
= X86_RECORD_SS_REGNUM
;
5058 case DS_PREFIX_OPCODE
:
5059 ir
.override
= X86_RECORD_DS_REGNUM
;
5061 case ES_PREFIX_OPCODE
:
5062 ir
.override
= X86_RECORD_ES_REGNUM
;
5064 case FS_PREFIX_OPCODE
:
5065 ir
.override
= X86_RECORD_FS_REGNUM
;
5067 case GS_PREFIX_OPCODE
:
5068 ir
.override
= X86_RECORD_GS_REGNUM
;
5070 case DATA_PREFIX_OPCODE
:
5071 prefixes
|= PREFIX_DATA
;
5073 case ADDR_PREFIX_OPCODE
:
5074 prefixes
|= PREFIX_ADDR
;
5076 case 0x40: /* i386 inc %eax */
5077 case 0x41: /* i386 inc %ecx */
5078 case 0x42: /* i386 inc %edx */
5079 case 0x43: /* i386 inc %ebx */
5080 case 0x44: /* i386 inc %esp */
5081 case 0x45: /* i386 inc %ebp */
5082 case 0x46: /* i386 inc %esi */
5083 case 0x47: /* i386 inc %edi */
5084 case 0x48: /* i386 dec %eax */
5085 case 0x49: /* i386 dec %ecx */
5086 case 0x4a: /* i386 dec %edx */
5087 case 0x4b: /* i386 dec %ebx */
5088 case 0x4c: /* i386 dec %esp */
5089 case 0x4d: /* i386 dec %ebp */
5090 case 0x4e: /* i386 dec %esi */
5091 case 0x4f: /* i386 dec %edi */
5092 if (ir
.regmap
[X86_RECORD_R8_REGNUM
]) /* 64 bit target */
5095 rex_w
= (opcode8
>> 3) & 1;
5096 rex_r
= (opcode8
& 0x4) << 1;
5097 ir
.rex_x
= (opcode8
& 0x2) << 2;
5098 ir
.rex_b
= (opcode8
& 0x1) << 3;
5100 else /* 32 bit target */
5109 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && rex_w
== 1)
5115 if (prefixes
& PREFIX_DATA
)
5118 if (prefixes
& PREFIX_ADDR
)
5120 else if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5123 /* Now check op code. */
5124 opcode
= (uint32_t) opcode8
;
5129 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
5132 opcode
= (uint32_t) opcode8
| 0x0f00;
5136 case 0x00: /* arith & logic */
5184 if (((opcode
>> 3) & 7) != OP_CMPL
)
5186 if ((opcode
& 1) == 0)
5189 ir
.ot
= ir
.dflag
+ OT_WORD
;
5191 switch ((opcode
>> 1) & 3)
5193 case 0: /* OP Ev, Gv */
5194 if (i386_record_modrm (&ir
))
5198 if (i386_record_lea_modrm (&ir
))
5204 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5206 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5209 case 1: /* OP Gv, Ev */
5210 if (i386_record_modrm (&ir
))
5213 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5215 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5217 case 2: /* OP A, Iv */
5218 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5222 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5225 case 0x80: /* GRP1 */
5229 if (i386_record_modrm (&ir
))
5232 if (ir
.reg
!= OP_CMPL
)
5234 if ((opcode
& 1) == 0)
5237 ir
.ot
= ir
.dflag
+ OT_WORD
;
5244 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
5245 if (i386_record_lea_modrm (&ir
))
5249 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5251 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5254 case 0x40: /* inc */
5263 case 0x48: /* dec */
5272 I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode
& 7);
5273 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5276 case 0xf6: /* GRP3 */
5278 if ((opcode
& 1) == 0)
5281 ir
.ot
= ir
.dflag
+ OT_WORD
;
5282 if (i386_record_modrm (&ir
))
5285 if (ir
.mod
!= 3 && ir
.reg
== 0)
5286 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
5291 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5297 if (i386_record_lea_modrm (&ir
))
5303 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5305 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5307 if (ir
.reg
== 3) /* neg */
5308 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5314 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5315 if (ir
.ot
!= OT_BYTE
)
5316 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5317 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5321 opcode
= opcode
<< 8 | ir
.modrm
;
5327 case 0xfe: /* GRP4 */
5328 case 0xff: /* GRP5 */
5329 if (i386_record_modrm (&ir
))
5331 if (ir
.reg
>= 2 && opcode
== 0xfe)
5334 opcode
= opcode
<< 8 | ir
.modrm
;
5341 if ((opcode
& 1) == 0)
5344 ir
.ot
= ir
.dflag
+ OT_WORD
;
5347 if (i386_record_lea_modrm (&ir
))
5353 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5355 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5357 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5360 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5362 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5364 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5367 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
5368 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5370 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5374 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5377 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5379 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5384 opcode
= opcode
<< 8 | ir
.modrm
;
5390 case 0x84: /* test */
5394 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5397 case 0x98: /* CWDE/CBW */
5398 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5401 case 0x99: /* CDQ/CWD */
5402 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5403 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5406 case 0x0faf: /* imul */
5409 ir
.ot
= ir
.dflag
+ OT_WORD
;
5410 if (i386_record_modrm (&ir
))
5413 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
5414 else if (opcode
== 0x6b)
5417 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5419 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5420 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5423 case 0x0fc0: /* xadd */
5425 if ((opcode
& 1) == 0)
5428 ir
.ot
= ir
.dflag
+ OT_WORD
;
5429 if (i386_record_modrm (&ir
))
5434 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5436 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5437 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5439 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5443 if (i386_record_lea_modrm (&ir
))
5445 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5447 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5449 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5452 case 0x0fb0: /* cmpxchg */
5454 if ((opcode
& 1) == 0)
5457 ir
.ot
= ir
.dflag
+ OT_WORD
;
5458 if (i386_record_modrm (&ir
))
5463 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5464 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5466 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5470 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5471 if (i386_record_lea_modrm (&ir
))
5474 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5477 case 0x0fc7: /* cmpxchg8b / rdrand / rdseed */
5478 if (i386_record_modrm (&ir
))
5482 /* rdrand and rdseed use the 3 bits of the REG field of ModR/M as
5483 an extended opcode. rdrand has bits 110 (/6) and rdseed
5484 has bits 111 (/7). */
5485 if (ir
.reg
== 6 || ir
.reg
== 7)
5487 /* The storage register is described by the 3 R/M bits, but the
5488 REX.B prefix may be used to give access to registers
5489 R8~R15. In this case ir.rex_b + R/M will give us the register
5490 in the range R8~R15.
5492 REX.W may also be used to access 64-bit registers, but we
5493 already record entire registers and not just partial bits
5495 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rex_b
+ ir
.rm
);
5496 /* These instructions also set conditional bits. */
5497 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5502 /* We don't handle this particular instruction yet. */
5504 opcode
= opcode
<< 8 | ir
.modrm
;
5508 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5509 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5510 if (i386_record_lea_modrm (&ir
))
5512 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5515 case 0x50: /* push */
5525 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5527 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5531 case 0x06: /* push es */
5532 case 0x0e: /* push cs */
5533 case 0x16: /* push ss */
5534 case 0x1e: /* push ds */
5535 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5540 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5544 case 0x0fa0: /* push fs */
5545 case 0x0fa8: /* push gs */
5546 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5551 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5555 case 0x60: /* pusha */
5556 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5561 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 4)))
5565 case 0x58: /* pop */
5573 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5574 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode
& 0x7) | ir
.rex_b
);
5577 case 0x61: /* popa */
5578 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5583 for (regnum
= X86_RECORD_REAX_REGNUM
;
5584 regnum
<= X86_RECORD_REDI_REGNUM
;
5586 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum
);
5589 case 0x8f: /* pop */
5590 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5591 ir
.ot
= ir
.dflag
? OT_QUAD
: OT_WORD
;
5593 ir
.ot
= ir
.dflag
+ OT_WORD
;
5594 if (i386_record_modrm (&ir
))
5597 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5600 ir
.popl_esp_hack
= 1 << ir
.ot
;
5601 if (i386_record_lea_modrm (&ir
))
5604 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5607 case 0xc8: /* enter */
5608 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
5609 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5611 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5615 case 0xc9: /* leave */
5616 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5617 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
5620 case 0x07: /* pop es */
5621 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5626 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5627 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM
);
5628 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5631 case 0x17: /* pop ss */
5632 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5637 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5638 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM
);
5639 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5642 case 0x1f: /* pop ds */
5643 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5648 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5649 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM
);
5650 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5653 case 0x0fa1: /* pop fs */
5654 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5655 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM
);
5656 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5659 case 0x0fa9: /* pop gs */
5660 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5661 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM
);
5662 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5665 case 0x88: /* mov */
5669 if ((opcode
& 1) == 0)
5672 ir
.ot
= ir
.dflag
+ OT_WORD
;
5674 if (i386_record_modrm (&ir
))
5679 if (opcode
== 0xc6 || opcode
== 0xc7)
5680 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
5681 if (i386_record_lea_modrm (&ir
))
5686 if (opcode
== 0xc6 || opcode
== 0xc7)
5688 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5690 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5694 case 0x8a: /* mov */
5696 if ((opcode
& 1) == 0)
5699 ir
.ot
= ir
.dflag
+ OT_WORD
;
5700 if (i386_record_modrm (&ir
))
5703 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5705 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5708 case 0x8c: /* mov seg */
5709 if (i386_record_modrm (&ir
))
5714 opcode
= opcode
<< 8 | ir
.modrm
;
5719 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5723 if (i386_record_lea_modrm (&ir
))
5728 case 0x8e: /* mov seg */
5729 if (i386_record_modrm (&ir
))
5734 regnum
= X86_RECORD_ES_REGNUM
;
5737 regnum
= X86_RECORD_SS_REGNUM
;
5740 regnum
= X86_RECORD_DS_REGNUM
;
5743 regnum
= X86_RECORD_FS_REGNUM
;
5746 regnum
= X86_RECORD_GS_REGNUM
;
5750 opcode
= opcode
<< 8 | ir
.modrm
;
5754 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum
);
5755 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5758 case 0x0fb6: /* movzbS */
5759 case 0x0fb7: /* movzwS */
5760 case 0x0fbe: /* movsbS */
5761 case 0x0fbf: /* movswS */
5762 if (i386_record_modrm (&ir
))
5764 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
5767 case 0x8d: /* lea */
5768 if (i386_record_modrm (&ir
))
5773 opcode
= opcode
<< 8 | ir
.modrm
;
5778 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5780 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5783 case 0xa0: /* mov EAX */
5786 case 0xd7: /* xlat */
5787 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5790 case 0xa2: /* mov EAX */
5792 if (ir
.override
>= 0)
5794 if (record_full_memory_query
)
5797 Process record ignores the memory change of instruction at address %s\n\
5798 because it can't get the value of the segment register.\n\
5799 Do you want to stop the program?"),
5800 paddress (gdbarch
, ir
.orig_addr
)))
5806 if ((opcode
& 1) == 0)
5809 ir
.ot
= ir
.dflag
+ OT_WORD
;
5812 if (record_read_memory (gdbarch
, ir
.addr
, buf
, 8))
5815 addr
= extract_unsigned_integer (buf
, 8, byte_order
);
5819 if (record_read_memory (gdbarch
, ir
.addr
, buf
, 4))
5822 addr
= extract_unsigned_integer (buf
, 4, byte_order
);
5826 if (record_read_memory (gdbarch
, ir
.addr
, buf
, 2))
5829 addr
= extract_unsigned_integer (buf
, 2, byte_order
);
5831 if (record_full_arch_list_add_mem (addr
, 1 << ir
.ot
))
5836 case 0xb0: /* mov R, Ib */
5844 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((ir
.regmap
[X86_RECORD_R8_REGNUM
])
5845 ? ((opcode
& 0x7) | ir
.rex_b
)
5846 : ((opcode
& 0x7) & 0x3));
5849 case 0xb8: /* mov R, Iv */
5857 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode
& 0x7) | ir
.rex_b
);
5860 case 0x91: /* xchg R, EAX */
5867 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5868 I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode
& 0x7);
5871 case 0x86: /* xchg Ev, Gv */
5873 if ((opcode
& 1) == 0)
5876 ir
.ot
= ir
.dflag
+ OT_WORD
;
5877 if (i386_record_modrm (&ir
))
5882 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5884 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5888 if (i386_record_lea_modrm (&ir
))
5892 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5894 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5897 case 0xc4: /* les Gv */
5898 case 0xc5: /* lds Gv */
5899 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5905 case 0x0fb2: /* lss Gv */
5906 case 0x0fb4: /* lfs Gv */
5907 case 0x0fb5: /* lgs Gv */
5908 if (i386_record_modrm (&ir
))
5916 opcode
= opcode
<< 8 | ir
.modrm
;
5921 case 0xc4: /* les Gv */
5922 regnum
= X86_RECORD_ES_REGNUM
;
5924 case 0xc5: /* lds Gv */
5925 regnum
= X86_RECORD_DS_REGNUM
;
5927 case 0x0fb2: /* lss Gv */
5928 regnum
= X86_RECORD_SS_REGNUM
;
5930 case 0x0fb4: /* lfs Gv */
5931 regnum
= X86_RECORD_FS_REGNUM
;
5933 case 0x0fb5: /* lgs Gv */
5934 regnum
= X86_RECORD_GS_REGNUM
;
5937 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum
);
5938 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
5939 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5942 case 0xc0: /* shifts */
5948 if ((opcode
& 1) == 0)
5951 ir
.ot
= ir
.dflag
+ OT_WORD
;
5952 if (i386_record_modrm (&ir
))
5954 if (ir
.mod
!= 3 && (opcode
== 0xd2 || opcode
== 0xd3))
5956 if (i386_record_lea_modrm (&ir
))
5962 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5964 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5966 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5973 if (i386_record_modrm (&ir
))
5977 if (record_full_arch_list_add_reg (ir
.regcache
, ir
.rm
))
5982 if (i386_record_lea_modrm (&ir
))
5987 case 0xd8: /* Floats. */
5995 if (i386_record_modrm (&ir
))
5997 ir
.reg
|= ((opcode
& 7) << 3);
6003 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
6011 /* For fcom, ficom nothing to do. */
6017 /* For fcomp, ficomp pop FPU stack, store all. */
6018 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
6045 /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul,
6046 fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension
6047 of code, always affects st(0) register. */
6048 if (i386_record_floats (gdbarch
, &ir
, I387_ST0_REGNUM (tdep
)))
6072 /* Handling fld, fild. */
6073 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
6077 switch (ir
.reg
>> 4)
6080 if (record_full_arch_list_add_mem (addr64
, 4))
6084 if (record_full_arch_list_add_mem (addr64
, 8))
6090 if (record_full_arch_list_add_mem (addr64
, 2))
6096 switch (ir
.reg
>> 4)
6099 if (record_full_arch_list_add_mem (addr64
, 4))
6101 if (3 == (ir
.reg
& 7))
6103 /* For fstp m32fp. */
6104 if (i386_record_floats (gdbarch
, &ir
,
6105 I386_SAVE_FPU_REGS
))
6110 if (record_full_arch_list_add_mem (addr64
, 4))
6112 if ((3 == (ir
.reg
& 7))
6113 || (5 == (ir
.reg
& 7))
6114 || (7 == (ir
.reg
& 7)))
6116 /* For fstp insn. */
6117 if (i386_record_floats (gdbarch
, &ir
,
6118 I386_SAVE_FPU_REGS
))
6123 if (record_full_arch_list_add_mem (addr64
, 8))
6125 if (3 == (ir
.reg
& 7))
6127 /* For fstp m64fp. */
6128 if (i386_record_floats (gdbarch
, &ir
,
6129 I386_SAVE_FPU_REGS
))
6134 if ((3 <= (ir
.reg
& 7)) && (6 <= (ir
.reg
& 7)))
6136 /* For fistp, fbld, fild, fbstp. */
6137 if (i386_record_floats (gdbarch
, &ir
,
6138 I386_SAVE_FPU_REGS
))
6143 if (record_full_arch_list_add_mem (addr64
, 2))
6152 if (i386_record_floats (gdbarch
, &ir
,
6153 I386_SAVE_FPU_ENV_REG_STACK
))
6158 if (i386_record_floats (gdbarch
, &ir
, I387_FCTRL_REGNUM (tdep
)))
6163 if (i386_record_floats (gdbarch
, &ir
,
6164 I386_SAVE_FPU_ENV_REG_STACK
))
6170 if (record_full_arch_list_add_mem (addr64
, 28))
6175 if (record_full_arch_list_add_mem (addr64
, 14))
6181 if (record_full_arch_list_add_mem (addr64
, 2))
6183 /* Insn fstp, fbstp. */
6184 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
6189 if (record_full_arch_list_add_mem (addr64
, 10))
6195 if (record_full_arch_list_add_mem (addr64
, 28))
6201 if (record_full_arch_list_add_mem (addr64
, 14))
6205 if (record_full_arch_list_add_mem (addr64
, 80))
6208 if (i386_record_floats (gdbarch
, &ir
,
6209 I386_SAVE_FPU_ENV_REG_STACK
))
6213 if (record_full_arch_list_add_mem (addr64
, 8))
6216 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
6221 opcode
= opcode
<< 8 | ir
.modrm
;
6226 /* Opcode is an extension of modR/M byte. */
6232 if (i386_record_floats (gdbarch
, &ir
, I387_ST0_REGNUM (tdep
)))
6236 if (0x0c == (ir
.modrm
>> 4))
6238 if ((ir
.modrm
& 0x0f) <= 7)
6240 if (i386_record_floats (gdbarch
, &ir
,
6241 I386_SAVE_FPU_REGS
))
6246 if (i386_record_floats (gdbarch
, &ir
,
6247 I387_ST0_REGNUM (tdep
)))
6249 /* If only st(0) is changing, then we have already
6251 if ((ir
.modrm
& 0x0f) - 0x08)
6253 if (i386_record_floats (gdbarch
, &ir
,
6254 I387_ST0_REGNUM (tdep
) +
6255 ((ir
.modrm
& 0x0f) - 0x08)))
6273 if (i386_record_floats (gdbarch
, &ir
,
6274 I387_ST0_REGNUM (tdep
)))
6292 if (i386_record_floats (gdbarch
, &ir
,
6293 I386_SAVE_FPU_REGS
))
6297 if (i386_record_floats (gdbarch
, &ir
,
6298 I387_ST0_REGNUM (tdep
)))
6300 if (i386_record_floats (gdbarch
, &ir
,
6301 I387_ST0_REGNUM (tdep
) + 1))
6308 if (0xe9 == ir
.modrm
)
6310 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
6313 else if ((0x0c == ir
.modrm
>> 4) || (0x0d == ir
.modrm
>> 4))
6315 if (i386_record_floats (gdbarch
, &ir
,
6316 I387_ST0_REGNUM (tdep
)))
6318 if (((ir
.modrm
& 0x0f) > 0) && ((ir
.modrm
& 0x0f) <= 7))
6320 if (i386_record_floats (gdbarch
, &ir
,
6321 I387_ST0_REGNUM (tdep
) +
6325 else if ((ir
.modrm
& 0x0f) - 0x08)
6327 if (i386_record_floats (gdbarch
, &ir
,
6328 I387_ST0_REGNUM (tdep
) +
6329 ((ir
.modrm
& 0x0f) - 0x08)))
6335 if (0xe3 == ir
.modrm
)
6337 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_ENV
))
6340 else if ((0x0c == ir
.modrm
>> 4) || (0x0d == ir
.modrm
>> 4))
6342 if (i386_record_floats (gdbarch
, &ir
,
6343 I387_ST0_REGNUM (tdep
)))
6345 if (((ir
.modrm
& 0x0f) > 0) && ((ir
.modrm
& 0x0f) <= 7))
6347 if (i386_record_floats (gdbarch
, &ir
,
6348 I387_ST0_REGNUM (tdep
) +
6352 else if ((ir
.modrm
& 0x0f) - 0x08)
6354 if (i386_record_floats (gdbarch
, &ir
,
6355 I387_ST0_REGNUM (tdep
) +
6356 ((ir
.modrm
& 0x0f) - 0x08)))
6362 if ((0x0c == ir
.modrm
>> 4)
6363 || (0x0d == ir
.modrm
>> 4)
6364 || (0x0f == ir
.modrm
>> 4))
6366 if ((ir
.modrm
& 0x0f) <= 7)
6368 if (i386_record_floats (gdbarch
, &ir
,
6369 I387_ST0_REGNUM (tdep
) +
6375 if (i386_record_floats (gdbarch
, &ir
,
6376 I387_ST0_REGNUM (tdep
) +
6377 ((ir
.modrm
& 0x0f) - 0x08)))
6383 if (0x0c == ir
.modrm
>> 4)
6385 if (i386_record_floats (gdbarch
, &ir
,
6386 I387_FTAG_REGNUM (tdep
)))
6389 else if ((0x0d == ir
.modrm
>> 4) || (0x0e == ir
.modrm
>> 4))
6391 if ((ir
.modrm
& 0x0f) <= 7)
6393 if (i386_record_floats (gdbarch
, &ir
,
6394 I387_ST0_REGNUM (tdep
) +
6400 if (i386_record_floats (gdbarch
, &ir
,
6401 I386_SAVE_FPU_REGS
))
6407 if ((0x0c == ir
.modrm
>> 4)
6408 || (0x0e == ir
.modrm
>> 4)
6409 || (0x0f == ir
.modrm
>> 4)
6410 || (0xd9 == ir
.modrm
))
6412 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
6417 if (0xe0 == ir
.modrm
)
6419 if (record_full_arch_list_add_reg (ir
.regcache
,
6423 else if ((0x0f == ir
.modrm
>> 4) || (0x0e == ir
.modrm
>> 4))
6425 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
6433 case 0xa4: /* movsS */
6435 case 0xaa: /* stosS */
6437 case 0x6c: /* insS */
6439 regcache_raw_read_unsigned (ir
.regcache
,
6440 ir
.regmap
[X86_RECORD_RECX_REGNUM
],
6446 if ((opcode
& 1) == 0)
6449 ir
.ot
= ir
.dflag
+ OT_WORD
;
6450 regcache_raw_read_unsigned (ir
.regcache
,
6451 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
6454 regcache_raw_read_unsigned (ir
.regcache
,
6455 ir
.regmap
[X86_RECORD_ES_REGNUM
],
6457 regcache_raw_read_unsigned (ir
.regcache
,
6458 ir
.regmap
[X86_RECORD_DS_REGNUM
],
6460 if (ir
.aflag
&& (es
!= ds
))
6462 /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */
6463 if (record_full_memory_query
)
6466 Process record ignores the memory change of instruction at address %s\n\
6467 because it can't get the value of the segment register.\n\
6468 Do you want to stop the program?"),
6469 paddress (gdbarch
, ir
.orig_addr
)))
6475 if (record_full_arch_list_add_mem (addr
, 1 << ir
.ot
))
6479 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
6480 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6481 if (opcode
== 0xa4 || opcode
== 0xa5)
6482 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
6483 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
6484 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6488 case 0xa6: /* cmpsS */
6490 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
6491 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
6492 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
6493 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6494 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6497 case 0xac: /* lodsS */
6499 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6500 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
6501 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
6502 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6503 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6506 case 0xae: /* scasS */
6508 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
6509 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
6510 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6511 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6514 case 0x6e: /* outsS */
6516 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
6517 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
6518 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6519 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6522 case 0xe4: /* port I/O */
6526 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6527 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6537 case 0xc2: /* ret im */
6538 case 0xc3: /* ret */
6539 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
6540 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6543 case 0xca: /* lret im */
6544 case 0xcb: /* lret */
6545 case 0xcf: /* iret */
6546 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
6547 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
6548 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6551 case 0xe8: /* call im */
6552 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
6554 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
6558 case 0x9a: /* lcall im */
6559 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6564 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
6565 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
6569 case 0xe9: /* jmp im */
6570 case 0xea: /* ljmp im */
6571 case 0xeb: /* jmp Jb */
6572 case 0x70: /* jcc Jb */
6588 case 0x0f80: /* jcc Jv */
6606 case 0x0f90: /* setcc Gv */
6622 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6624 if (i386_record_modrm (&ir
))
6627 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rex_b
? (ir
.rm
| ir
.rex_b
)
6631 if (i386_record_lea_modrm (&ir
))
6636 case 0x0f40: /* cmov Gv, Ev */
6652 if (i386_record_modrm (&ir
))
6655 if (ir
.dflag
== OT_BYTE
)
6657 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
6661 case 0x9c: /* pushf */
6662 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6663 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
6665 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
6669 case 0x9d: /* popf */
6670 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
6671 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6674 case 0x9e: /* sahf */
6675 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6681 case 0xf5: /* cmc */
6682 case 0xf8: /* clc */
6683 case 0xf9: /* stc */
6684 case 0xfc: /* cld */
6685 case 0xfd: /* std */
6686 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6689 case 0x9f: /* lahf */
6690 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6695 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6696 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6699 /* bit operations */
6700 case 0x0fba: /* bt/bts/btr/btc Gv, im */
6701 ir
.ot
= ir
.dflag
+ OT_WORD
;
6702 if (i386_record_modrm (&ir
))
6707 opcode
= opcode
<< 8 | ir
.modrm
;
6713 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6716 if (i386_record_lea_modrm (&ir
))
6720 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6723 case 0x0fa3: /* bt Gv, Ev */
6724 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6727 case 0x0fab: /* bts */
6728 case 0x0fb3: /* btr */
6729 case 0x0fbb: /* btc */
6730 ir
.ot
= ir
.dflag
+ OT_WORD
;
6731 if (i386_record_modrm (&ir
))
6734 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6738 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
6740 regcache_raw_read_unsigned (ir
.regcache
,
6741 ir
.regmap
[ir
.reg
| rex_r
],
6746 addr64
+= ((int16_t) addr
>> 4) << 4;
6749 addr64
+= ((int32_t) addr
>> 5) << 5;
6752 addr64
+= ((int64_t) addr
>> 6) << 6;
6755 if (record_full_arch_list_add_mem (addr64
, 1 << ir
.ot
))
6757 if (i386_record_lea_modrm (&ir
))
6760 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6763 case 0x0fbc: /* bsf */
6764 case 0x0fbd: /* bsr */
6765 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
6766 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6770 case 0x27: /* daa */
6771 case 0x2f: /* das */
6772 case 0x37: /* aaa */
6773 case 0x3f: /* aas */
6774 case 0xd4: /* aam */
6775 case 0xd5: /* aad */
6776 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6781 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6782 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6786 case 0x90: /* nop */
6787 if (prefixes
& PREFIX_LOCK
)
6794 case 0x9b: /* fwait */
6795 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
6797 opcode
= (uint32_t) opcode8
;
6803 case 0xcc: /* int3 */
6804 printf_unfiltered (_("Process record does not support instruction "
6811 case 0xcd: /* int */
6815 if (record_read_memory (gdbarch
, ir
.addr
, &interrupt
, 1))
6818 if (interrupt
!= 0x80
6819 || tdep
->i386_intx80_record
== NULL
)
6821 printf_unfiltered (_("Process record does not support "
6822 "instruction int 0x%02x.\n"),
6827 ret
= tdep
->i386_intx80_record (ir
.regcache
);
6834 case 0xce: /* into */
6835 printf_unfiltered (_("Process record does not support "
6836 "instruction into.\n"));
6841 case 0xfa: /* cli */
6842 case 0xfb: /* sti */
6845 case 0x62: /* bound */
6846 printf_unfiltered (_("Process record does not support "
6847 "instruction bound.\n"));
6852 case 0x0fc8: /* bswap reg */
6860 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode
& 7) | ir
.rex_b
);
6863 case 0xd6: /* salc */
6864 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6869 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6870 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6873 case 0xe0: /* loopnz */
6874 case 0xe1: /* loopz */
6875 case 0xe2: /* loop */
6876 case 0xe3: /* jecxz */
6877 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6878 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6881 case 0x0f30: /* wrmsr */
6882 printf_unfiltered (_("Process record does not support "
6883 "instruction wrmsr.\n"));
6888 case 0x0f32: /* rdmsr */
6889 printf_unfiltered (_("Process record does not support "
6890 "instruction rdmsr.\n"));
6895 case 0x0f31: /* rdtsc */
6896 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6897 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
6900 case 0x0f34: /* sysenter */
6903 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6908 if (tdep
->i386_sysenter_record
== NULL
)
6910 printf_unfiltered (_("Process record does not support "
6911 "instruction sysenter.\n"));
6915 ret
= tdep
->i386_sysenter_record (ir
.regcache
);
6921 case 0x0f35: /* sysexit */
6922 printf_unfiltered (_("Process record does not support "
6923 "instruction sysexit.\n"));
6928 case 0x0f05: /* syscall */
6931 if (tdep
->i386_syscall_record
== NULL
)
6933 printf_unfiltered (_("Process record does not support "
6934 "instruction syscall.\n"));
6938 ret
= tdep
->i386_syscall_record (ir
.regcache
);
6944 case 0x0f07: /* sysret */
6945 printf_unfiltered (_("Process record does not support "
6946 "instruction sysret.\n"));
6951 case 0x0fa2: /* cpuid */
6952 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6953 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6954 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
6955 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM
);
6958 case 0xf4: /* hlt */
6959 printf_unfiltered (_("Process record does not support "
6960 "instruction hlt.\n"));
6966 if (i386_record_modrm (&ir
))
6973 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6977 if (i386_record_lea_modrm (&ir
))
6986 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6990 opcode
= opcode
<< 8 | ir
.modrm
;
6997 if (i386_record_modrm (&ir
))
7008 opcode
= opcode
<< 8 | ir
.modrm
;
7011 if (ir
.override
>= 0)
7013 if (record_full_memory_query
)
7016 Process record ignores the memory change of instruction at address %s\n\
7017 because it can't get the value of the segment register.\n\
7018 Do you want to stop the program?"),
7019 paddress (gdbarch
, ir
.orig_addr
)))
7025 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
7027 if (record_full_arch_list_add_mem (addr64
, 2))
7030 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
7032 if (record_full_arch_list_add_mem (addr64
, 8))
7037 if (record_full_arch_list_add_mem (addr64
, 4))
7048 case 0: /* monitor */
7051 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7055 opcode
= opcode
<< 8 | ir
.modrm
;
7063 if (ir
.override
>= 0)
7065 if (record_full_memory_query
)
7068 Process record ignores the memory change of instruction at address %s\n\
7069 because it can't get the value of the segment register.\n\
7070 Do you want to stop the program?"),
7071 paddress (gdbarch
, ir
.orig_addr
)))
7079 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
7081 if (record_full_arch_list_add_mem (addr64
, 2))
7084 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
7086 if (record_full_arch_list_add_mem (addr64
, 8))
7091 if (record_full_arch_list_add_mem (addr64
, 4))
7103 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
7104 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
7108 else if (ir
.rm
== 1)
7116 opcode
= opcode
<< 8 | ir
.modrm
;
7123 if (record_full_arch_list_add_reg (ir
.regcache
, ir
.rm
| ir
.rex_b
))
7129 if (i386_record_lea_modrm (&ir
))
7132 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7135 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7137 case 7: /* invlpg */
7140 if (ir
.rm
== 0 && ir
.regmap
[X86_RECORD_R8_REGNUM
])
7141 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM
);
7145 opcode
= opcode
<< 8 | ir
.modrm
;
7150 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7154 opcode
= opcode
<< 8 | ir
.modrm
;
7160 case 0x0f08: /* invd */
7161 case 0x0f09: /* wbinvd */
7164 case 0x63: /* arpl */
7165 if (i386_record_modrm (&ir
))
7167 if (ir
.mod
== 3 || ir
.regmap
[X86_RECORD_R8_REGNUM
])
7169 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.regmap
[X86_RECORD_R8_REGNUM
]
7170 ? (ir
.reg
| rex_r
) : ir
.rm
);
7174 ir
.ot
= ir
.dflag
? OT_LONG
: OT_WORD
;
7175 if (i386_record_lea_modrm (&ir
))
7178 if (!ir
.regmap
[X86_RECORD_R8_REGNUM
])
7179 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7182 case 0x0f02: /* lar */
7183 case 0x0f03: /* lsl */
7184 if (i386_record_modrm (&ir
))
7186 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
7187 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7191 if (i386_record_modrm (&ir
))
7193 if (ir
.mod
== 3 && ir
.reg
== 3)
7196 opcode
= opcode
<< 8 | ir
.modrm
;
7208 /* nop (multi byte) */
7211 case 0x0f20: /* mov reg, crN */
7212 case 0x0f22: /* mov crN, reg */
7213 if (i386_record_modrm (&ir
))
7215 if ((ir
.modrm
& 0xc0) != 0xc0)
7218 opcode
= opcode
<< 8 | ir
.modrm
;
7229 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7231 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
7235 opcode
= opcode
<< 8 | ir
.modrm
;
7241 case 0x0f21: /* mov reg, drN */
7242 case 0x0f23: /* mov drN, reg */
7243 if (i386_record_modrm (&ir
))
7245 if ((ir
.modrm
& 0xc0) != 0xc0 || ir
.reg
== 4
7246 || ir
.reg
== 5 || ir
.reg
>= 8)
7249 opcode
= opcode
<< 8 | ir
.modrm
;
7253 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7255 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
7258 case 0x0f06: /* clts */
7259 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7262 /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */
7264 case 0x0f0d: /* 3DNow! prefetch */
7267 case 0x0f0e: /* 3DNow! femms */
7268 case 0x0f77: /* emms */
7269 if (i386_fpc_regnum_p (gdbarch
, I387_FTAG_REGNUM(tdep
)))
7271 record_full_arch_list_add_reg (ir
.regcache
, I387_FTAG_REGNUM(tdep
));
7274 case 0x0f0f: /* 3DNow! data */
7275 if (i386_record_modrm (&ir
))
7277 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
7282 case 0x0c: /* 3DNow! pi2fw */
7283 case 0x0d: /* 3DNow! pi2fd */
7284 case 0x1c: /* 3DNow! pf2iw */
7285 case 0x1d: /* 3DNow! pf2id */
7286 case 0x8a: /* 3DNow! pfnacc */
7287 case 0x8e: /* 3DNow! pfpnacc */
7288 case 0x90: /* 3DNow! pfcmpge */
7289 case 0x94: /* 3DNow! pfmin */
7290 case 0x96: /* 3DNow! pfrcp */
7291 case 0x97: /* 3DNow! pfrsqrt */
7292 case 0x9a: /* 3DNow! pfsub */
7293 case 0x9e: /* 3DNow! pfadd */
7294 case 0xa0: /* 3DNow! pfcmpgt */
7295 case 0xa4: /* 3DNow! pfmax */
7296 case 0xa6: /* 3DNow! pfrcpit1 */
7297 case 0xa7: /* 3DNow! pfrsqit1 */
7298 case 0xaa: /* 3DNow! pfsubr */
7299 case 0xae: /* 3DNow! pfacc */
7300 case 0xb0: /* 3DNow! pfcmpeq */
7301 case 0xb4: /* 3DNow! pfmul */
7302 case 0xb6: /* 3DNow! pfrcpit2 */
7303 case 0xb7: /* 3DNow! pmulhrw */
7304 case 0xbb: /* 3DNow! pswapd */
7305 case 0xbf: /* 3DNow! pavgusb */
7306 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.reg
))
7307 goto no_support_3dnow_data
;
7308 record_full_arch_list_add_reg (ir
.regcache
, ir
.reg
);
7312 no_support_3dnow_data
:
7313 opcode
= (opcode
<< 8) | opcode8
;
7319 case 0x0faa: /* rsm */
7320 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7321 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
7322 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
7323 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
7324 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM
);
7325 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
7326 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
7327 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
7328 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
7332 if (i386_record_modrm (&ir
))
7336 case 0: /* fxsave */
7340 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7341 if (i386_record_lea_modrm_addr (&ir
, &tmpu64
))
7343 if (record_full_arch_list_add_mem (tmpu64
, 512))
7348 case 1: /* fxrstor */
7352 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7354 for (i
= I387_MM0_REGNUM (tdep
);
7355 i386_mmx_regnum_p (gdbarch
, i
); i
++)
7356 record_full_arch_list_add_reg (ir
.regcache
, i
);
7358 for (i
= I387_XMM0_REGNUM (tdep
);
7359 i386_xmm_regnum_p (gdbarch
, i
); i
++)
7360 record_full_arch_list_add_reg (ir
.regcache
, i
);
7362 if (i386_mxcsr_regnum_p (gdbarch
, I387_MXCSR_REGNUM(tdep
)))
7363 record_full_arch_list_add_reg (ir
.regcache
,
7364 I387_MXCSR_REGNUM(tdep
));
7366 for (i
= I387_ST0_REGNUM (tdep
);
7367 i386_fp_regnum_p (gdbarch
, i
); i
++)
7368 record_full_arch_list_add_reg (ir
.regcache
, i
);
7370 for (i
= I387_FCTRL_REGNUM (tdep
);
7371 i386_fpc_regnum_p (gdbarch
, i
); i
++)
7372 record_full_arch_list_add_reg (ir
.regcache
, i
);
7376 case 2: /* ldmxcsr */
7377 if (!i386_mxcsr_regnum_p (gdbarch
, I387_MXCSR_REGNUM(tdep
)))
7379 record_full_arch_list_add_reg (ir
.regcache
, I387_MXCSR_REGNUM(tdep
));
7382 case 3: /* stmxcsr */
7384 if (i386_record_lea_modrm (&ir
))
7388 case 5: /* lfence */
7389 case 6: /* mfence */
7390 case 7: /* sfence clflush */
7394 opcode
= (opcode
<< 8) | ir
.modrm
;
7400 case 0x0fc3: /* movnti */
7401 ir
.ot
= (ir
.dflag
== 2) ? OT_QUAD
: OT_LONG
;
7402 if (i386_record_modrm (&ir
))
7407 if (i386_record_lea_modrm (&ir
))
7411 /* Add prefix to opcode. */
7526 /* Mask out PREFIX_ADDR. */
7527 switch ((prefixes
& ~PREFIX_ADDR
))
7539 reswitch_prefix_add
:
7547 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
7550 opcode
= (uint32_t) opcode8
| opcode
<< 8;
7551 goto reswitch_prefix_add
;
7554 case 0x0f10: /* movups */
7555 case 0x660f10: /* movupd */
7556 case 0xf30f10: /* movss */
7557 case 0xf20f10: /* movsd */
7558 case 0x0f12: /* movlps */
7559 case 0x660f12: /* movlpd */
7560 case 0xf30f12: /* movsldup */
7561 case 0xf20f12: /* movddup */
7562 case 0x0f14: /* unpcklps */
7563 case 0x660f14: /* unpcklpd */
7564 case 0x0f15: /* unpckhps */
7565 case 0x660f15: /* unpckhpd */
7566 case 0x0f16: /* movhps */
7567 case 0x660f16: /* movhpd */
7568 case 0xf30f16: /* movshdup */
7569 case 0x0f28: /* movaps */
7570 case 0x660f28: /* movapd */
7571 case 0x0f2a: /* cvtpi2ps */
7572 case 0x660f2a: /* cvtpi2pd */
7573 case 0xf30f2a: /* cvtsi2ss */
7574 case 0xf20f2a: /* cvtsi2sd */
7575 case 0x0f2c: /* cvttps2pi */
7576 case 0x660f2c: /* cvttpd2pi */
7577 case 0x0f2d: /* cvtps2pi */
7578 case 0x660f2d: /* cvtpd2pi */
7579 case 0x660f3800: /* pshufb */
7580 case 0x660f3801: /* phaddw */
7581 case 0x660f3802: /* phaddd */
7582 case 0x660f3803: /* phaddsw */
7583 case 0x660f3804: /* pmaddubsw */
7584 case 0x660f3805: /* phsubw */
7585 case 0x660f3806: /* phsubd */
7586 case 0x660f3807: /* phsubsw */
7587 case 0x660f3808: /* psignb */
7588 case 0x660f3809: /* psignw */
7589 case 0x660f380a: /* psignd */
7590 case 0x660f380b: /* pmulhrsw */
7591 case 0x660f3810: /* pblendvb */
7592 case 0x660f3814: /* blendvps */
7593 case 0x660f3815: /* blendvpd */
7594 case 0x660f381c: /* pabsb */
7595 case 0x660f381d: /* pabsw */
7596 case 0x660f381e: /* pabsd */
7597 case 0x660f3820: /* pmovsxbw */
7598 case 0x660f3821: /* pmovsxbd */
7599 case 0x660f3822: /* pmovsxbq */
7600 case 0x660f3823: /* pmovsxwd */
7601 case 0x660f3824: /* pmovsxwq */
7602 case 0x660f3825: /* pmovsxdq */
7603 case 0x660f3828: /* pmuldq */
7604 case 0x660f3829: /* pcmpeqq */
7605 case 0x660f382a: /* movntdqa */
7606 case 0x660f3a08: /* roundps */
7607 case 0x660f3a09: /* roundpd */
7608 case 0x660f3a0a: /* roundss */
7609 case 0x660f3a0b: /* roundsd */
7610 case 0x660f3a0c: /* blendps */
7611 case 0x660f3a0d: /* blendpd */
7612 case 0x660f3a0e: /* pblendw */
7613 case 0x660f3a0f: /* palignr */
7614 case 0x660f3a20: /* pinsrb */
7615 case 0x660f3a21: /* insertps */
7616 case 0x660f3a22: /* pinsrd pinsrq */
7617 case 0x660f3a40: /* dpps */
7618 case 0x660f3a41: /* dppd */
7619 case 0x660f3a42: /* mpsadbw */
7620 case 0x660f3a60: /* pcmpestrm */
7621 case 0x660f3a61: /* pcmpestri */
7622 case 0x660f3a62: /* pcmpistrm */
7623 case 0x660f3a63: /* pcmpistri */
7624 case 0x0f51: /* sqrtps */
7625 case 0x660f51: /* sqrtpd */
7626 case 0xf20f51: /* sqrtsd */
7627 case 0xf30f51: /* sqrtss */
7628 case 0x0f52: /* rsqrtps */
7629 case 0xf30f52: /* rsqrtss */
7630 case 0x0f53: /* rcpps */
7631 case 0xf30f53: /* rcpss */
7632 case 0x0f54: /* andps */
7633 case 0x660f54: /* andpd */
7634 case 0x0f55: /* andnps */
7635 case 0x660f55: /* andnpd */
7636 case 0x0f56: /* orps */
7637 case 0x660f56: /* orpd */
7638 case 0x0f57: /* xorps */
7639 case 0x660f57: /* xorpd */
7640 case 0x0f58: /* addps */
7641 case 0x660f58: /* addpd */
7642 case 0xf20f58: /* addsd */
7643 case 0xf30f58: /* addss */
7644 case 0x0f59: /* mulps */
7645 case 0x660f59: /* mulpd */
7646 case 0xf20f59: /* mulsd */
7647 case 0xf30f59: /* mulss */
7648 case 0x0f5a: /* cvtps2pd */
7649 case 0x660f5a: /* cvtpd2ps */
7650 case 0xf20f5a: /* cvtsd2ss */
7651 case 0xf30f5a: /* cvtss2sd */
7652 case 0x0f5b: /* cvtdq2ps */
7653 case 0x660f5b: /* cvtps2dq */
7654 case 0xf30f5b: /* cvttps2dq */
7655 case 0x0f5c: /* subps */
7656 case 0x660f5c: /* subpd */
7657 case 0xf20f5c: /* subsd */
7658 case 0xf30f5c: /* subss */
7659 case 0x0f5d: /* minps */
7660 case 0x660f5d: /* minpd */
7661 case 0xf20f5d: /* minsd */
7662 case 0xf30f5d: /* minss */
7663 case 0x0f5e: /* divps */
7664 case 0x660f5e: /* divpd */
7665 case 0xf20f5e: /* divsd */
7666 case 0xf30f5e: /* divss */
7667 case 0x0f5f: /* maxps */
7668 case 0x660f5f: /* maxpd */
7669 case 0xf20f5f: /* maxsd */
7670 case 0xf30f5f: /* maxss */
7671 case 0x660f60: /* punpcklbw */
7672 case 0x660f61: /* punpcklwd */
7673 case 0x660f62: /* punpckldq */
7674 case 0x660f63: /* packsswb */
7675 case 0x660f64: /* pcmpgtb */
7676 case 0x660f65: /* pcmpgtw */
7677 case 0x660f66: /* pcmpgtd */
7678 case 0x660f67: /* packuswb */
7679 case 0x660f68: /* punpckhbw */
7680 case 0x660f69: /* punpckhwd */
7681 case 0x660f6a: /* punpckhdq */
7682 case 0x660f6b: /* packssdw */
7683 case 0x660f6c: /* punpcklqdq */
7684 case 0x660f6d: /* punpckhqdq */
7685 case 0x660f6e: /* movd */
7686 case 0x660f6f: /* movdqa */
7687 case 0xf30f6f: /* movdqu */
7688 case 0x660f70: /* pshufd */
7689 case 0xf20f70: /* pshuflw */
7690 case 0xf30f70: /* pshufhw */
7691 case 0x660f74: /* pcmpeqb */
7692 case 0x660f75: /* pcmpeqw */
7693 case 0x660f76: /* pcmpeqd */
7694 case 0x660f7c: /* haddpd */
7695 case 0xf20f7c: /* haddps */
7696 case 0x660f7d: /* hsubpd */
7697 case 0xf20f7d: /* hsubps */
7698 case 0xf30f7e: /* movq */
7699 case 0x0fc2: /* cmpps */
7700 case 0x660fc2: /* cmppd */
7701 case 0xf20fc2: /* cmpsd */
7702 case 0xf30fc2: /* cmpss */
7703 case 0x660fc4: /* pinsrw */
7704 case 0x0fc6: /* shufps */
7705 case 0x660fc6: /* shufpd */
7706 case 0x660fd0: /* addsubpd */
7707 case 0xf20fd0: /* addsubps */
7708 case 0x660fd1: /* psrlw */
7709 case 0x660fd2: /* psrld */
7710 case 0x660fd3: /* psrlq */
7711 case 0x660fd4: /* paddq */
7712 case 0x660fd5: /* pmullw */
7713 case 0xf30fd6: /* movq2dq */
7714 case 0x660fd8: /* psubusb */
7715 case 0x660fd9: /* psubusw */
7716 case 0x660fda: /* pminub */
7717 case 0x660fdb: /* pand */
7718 case 0x660fdc: /* paddusb */
7719 case 0x660fdd: /* paddusw */
7720 case 0x660fde: /* pmaxub */
7721 case 0x660fdf: /* pandn */
7722 case 0x660fe0: /* pavgb */
7723 case 0x660fe1: /* psraw */
7724 case 0x660fe2: /* psrad */
7725 case 0x660fe3: /* pavgw */
7726 case 0x660fe4: /* pmulhuw */
7727 case 0x660fe5: /* pmulhw */
7728 case 0x660fe6: /* cvttpd2dq */
7729 case 0xf20fe6: /* cvtpd2dq */
7730 case 0xf30fe6: /* cvtdq2pd */
7731 case 0x660fe8: /* psubsb */
7732 case 0x660fe9: /* psubsw */
7733 case 0x660fea: /* pminsw */
7734 case 0x660feb: /* por */
7735 case 0x660fec: /* paddsb */
7736 case 0x660fed: /* paddsw */
7737 case 0x660fee: /* pmaxsw */
7738 case 0x660fef: /* pxor */
7739 case 0xf20ff0: /* lddqu */
7740 case 0x660ff1: /* psllw */
7741 case 0x660ff2: /* pslld */
7742 case 0x660ff3: /* psllq */
7743 case 0x660ff4: /* pmuludq */
7744 case 0x660ff5: /* pmaddwd */
7745 case 0x660ff6: /* psadbw */
7746 case 0x660ff8: /* psubb */
7747 case 0x660ff9: /* psubw */
7748 case 0x660ffa: /* psubd */
7749 case 0x660ffb: /* psubq */
7750 case 0x660ffc: /* paddb */
7751 case 0x660ffd: /* paddw */
7752 case 0x660ffe: /* paddd */
7753 if (i386_record_modrm (&ir
))
7756 if (!i386_xmm_regnum_p (gdbarch
, I387_XMM0_REGNUM (tdep
) + ir
.reg
))
7758 record_full_arch_list_add_reg (ir
.regcache
,
7759 I387_XMM0_REGNUM (tdep
) + ir
.reg
);
7760 if ((opcode
& 0xfffffffc) == 0x660f3a60)
7761 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7764 case 0x0f11: /* movups */
7765 case 0x660f11: /* movupd */
7766 case 0xf30f11: /* movss */
7767 case 0xf20f11: /* movsd */
7768 case 0x0f13: /* movlps */
7769 case 0x660f13: /* movlpd */
7770 case 0x0f17: /* movhps */
7771 case 0x660f17: /* movhpd */
7772 case 0x0f29: /* movaps */
7773 case 0x660f29: /* movapd */
7774 case 0x660f3a14: /* pextrb */
7775 case 0x660f3a15: /* pextrw */
7776 case 0x660f3a16: /* pextrd pextrq */
7777 case 0x660f3a17: /* extractps */
7778 case 0x660f7f: /* movdqa */
7779 case 0xf30f7f: /* movdqu */
7780 if (i386_record_modrm (&ir
))
7784 if (opcode
== 0x0f13 || opcode
== 0x660f13
7785 || opcode
== 0x0f17 || opcode
== 0x660f17)
7788 if (!i386_xmm_regnum_p (gdbarch
,
7789 I387_XMM0_REGNUM (tdep
) + ir
.rm
))
7791 record_full_arch_list_add_reg (ir
.regcache
,
7792 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
7814 if (i386_record_lea_modrm (&ir
))
7819 case 0x0f2b: /* movntps */
7820 case 0x660f2b: /* movntpd */
7821 case 0x0fe7: /* movntq */
7822 case 0x660fe7: /* movntdq */
7825 if (opcode
== 0x0fe7)
7829 if (i386_record_lea_modrm (&ir
))
7833 case 0xf30f2c: /* cvttss2si */
7834 case 0xf20f2c: /* cvttsd2si */
7835 case 0xf30f2d: /* cvtss2si */
7836 case 0xf20f2d: /* cvtsd2si */
7837 case 0xf20f38f0: /* crc32 */
7838 case 0xf20f38f1: /* crc32 */
7839 case 0x0f50: /* movmskps */
7840 case 0x660f50: /* movmskpd */
7841 case 0x0fc5: /* pextrw */
7842 case 0x660fc5: /* pextrw */
7843 case 0x0fd7: /* pmovmskb */
7844 case 0x660fd7: /* pmovmskb */
7845 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
7848 case 0x0f3800: /* pshufb */
7849 case 0x0f3801: /* phaddw */
7850 case 0x0f3802: /* phaddd */
7851 case 0x0f3803: /* phaddsw */
7852 case 0x0f3804: /* pmaddubsw */
7853 case 0x0f3805: /* phsubw */
7854 case 0x0f3806: /* phsubd */
7855 case 0x0f3807: /* phsubsw */
7856 case 0x0f3808: /* psignb */
7857 case 0x0f3809: /* psignw */
7858 case 0x0f380a: /* psignd */
7859 case 0x0f380b: /* pmulhrsw */
7860 case 0x0f381c: /* pabsb */
7861 case 0x0f381d: /* pabsw */
7862 case 0x0f381e: /* pabsd */
7863 case 0x0f382b: /* packusdw */
7864 case 0x0f3830: /* pmovzxbw */
7865 case 0x0f3831: /* pmovzxbd */
7866 case 0x0f3832: /* pmovzxbq */
7867 case 0x0f3833: /* pmovzxwd */
7868 case 0x0f3834: /* pmovzxwq */
7869 case 0x0f3835: /* pmovzxdq */
7870 case 0x0f3837: /* pcmpgtq */
7871 case 0x0f3838: /* pminsb */
7872 case 0x0f3839: /* pminsd */
7873 case 0x0f383a: /* pminuw */
7874 case 0x0f383b: /* pminud */
7875 case 0x0f383c: /* pmaxsb */
7876 case 0x0f383d: /* pmaxsd */
7877 case 0x0f383e: /* pmaxuw */
7878 case 0x0f383f: /* pmaxud */
7879 case 0x0f3840: /* pmulld */
7880 case 0x0f3841: /* phminposuw */
7881 case 0x0f3a0f: /* palignr */
7882 case 0x0f60: /* punpcklbw */
7883 case 0x0f61: /* punpcklwd */
7884 case 0x0f62: /* punpckldq */
7885 case 0x0f63: /* packsswb */
7886 case 0x0f64: /* pcmpgtb */
7887 case 0x0f65: /* pcmpgtw */
7888 case 0x0f66: /* pcmpgtd */
7889 case 0x0f67: /* packuswb */
7890 case 0x0f68: /* punpckhbw */
7891 case 0x0f69: /* punpckhwd */
7892 case 0x0f6a: /* punpckhdq */
7893 case 0x0f6b: /* packssdw */
7894 case 0x0f6e: /* movd */
7895 case 0x0f6f: /* movq */
7896 case 0x0f70: /* pshufw */
7897 case 0x0f74: /* pcmpeqb */
7898 case 0x0f75: /* pcmpeqw */
7899 case 0x0f76: /* pcmpeqd */
7900 case 0x0fc4: /* pinsrw */
7901 case 0x0fd1: /* psrlw */
7902 case 0x0fd2: /* psrld */
7903 case 0x0fd3: /* psrlq */
7904 case 0x0fd4: /* paddq */
7905 case 0x0fd5: /* pmullw */
7906 case 0xf20fd6: /* movdq2q */
7907 case 0x0fd8: /* psubusb */
7908 case 0x0fd9: /* psubusw */
7909 case 0x0fda: /* pminub */
7910 case 0x0fdb: /* pand */
7911 case 0x0fdc: /* paddusb */
7912 case 0x0fdd: /* paddusw */
7913 case 0x0fde: /* pmaxub */
7914 case 0x0fdf: /* pandn */
7915 case 0x0fe0: /* pavgb */
7916 case 0x0fe1: /* psraw */
7917 case 0x0fe2: /* psrad */
7918 case 0x0fe3: /* pavgw */
7919 case 0x0fe4: /* pmulhuw */
7920 case 0x0fe5: /* pmulhw */
7921 case 0x0fe8: /* psubsb */
7922 case 0x0fe9: /* psubsw */
7923 case 0x0fea: /* pminsw */
7924 case 0x0feb: /* por */
7925 case 0x0fec: /* paddsb */
7926 case 0x0fed: /* paddsw */
7927 case 0x0fee: /* pmaxsw */
7928 case 0x0fef: /* pxor */
7929 case 0x0ff1: /* psllw */
7930 case 0x0ff2: /* pslld */
7931 case 0x0ff3: /* psllq */
7932 case 0x0ff4: /* pmuludq */
7933 case 0x0ff5: /* pmaddwd */
7934 case 0x0ff6: /* psadbw */
7935 case 0x0ff8: /* psubb */
7936 case 0x0ff9: /* psubw */
7937 case 0x0ffa: /* psubd */
7938 case 0x0ffb: /* psubq */
7939 case 0x0ffc: /* paddb */
7940 case 0x0ffd: /* paddw */
7941 case 0x0ffe: /* paddd */
7942 if (i386_record_modrm (&ir
))
7944 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.reg
))
7946 record_full_arch_list_add_reg (ir
.regcache
,
7947 I387_MM0_REGNUM (tdep
) + ir
.reg
);
7950 case 0x0f71: /* psllw */
7951 case 0x0f72: /* pslld */
7952 case 0x0f73: /* psllq */
7953 if (i386_record_modrm (&ir
))
7955 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.rm
))
7957 record_full_arch_list_add_reg (ir
.regcache
,
7958 I387_MM0_REGNUM (tdep
) + ir
.rm
);
7961 case 0x660f71: /* psllw */
7962 case 0x660f72: /* pslld */
7963 case 0x660f73: /* psllq */
7964 if (i386_record_modrm (&ir
))
7967 if (!i386_xmm_regnum_p (gdbarch
, I387_XMM0_REGNUM (tdep
) + ir
.rm
))
7969 record_full_arch_list_add_reg (ir
.regcache
,
7970 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
7973 case 0x0f7e: /* movd */
7974 case 0x660f7e: /* movd */
7975 if (i386_record_modrm (&ir
))
7978 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
7985 if (i386_record_lea_modrm (&ir
))
7990 case 0x0f7f: /* movq */
7991 if (i386_record_modrm (&ir
))
7995 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.rm
))
7997 record_full_arch_list_add_reg (ir
.regcache
,
7998 I387_MM0_REGNUM (tdep
) + ir
.rm
);
8003 if (i386_record_lea_modrm (&ir
))
8008 case 0xf30fb8: /* popcnt */
8009 if (i386_record_modrm (&ir
))
8011 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
8012 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
8015 case 0x660fd6: /* movq */
8016 if (i386_record_modrm (&ir
))
8021 if (!i386_xmm_regnum_p (gdbarch
,
8022 I387_XMM0_REGNUM (tdep
) + ir
.rm
))
8024 record_full_arch_list_add_reg (ir
.regcache
,
8025 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
8030 if (i386_record_lea_modrm (&ir
))
8035 case 0x660f3817: /* ptest */
8036 case 0x0f2e: /* ucomiss */
8037 case 0x660f2e: /* ucomisd */
8038 case 0x0f2f: /* comiss */
8039 case 0x660f2f: /* comisd */
8040 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
8043 case 0x0ff7: /* maskmovq */
8044 regcache_raw_read_unsigned (ir
.regcache
,
8045 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
8047 if (record_full_arch_list_add_mem (addr
, 64))
8051 case 0x660ff7: /* maskmovdqu */
8052 regcache_raw_read_unsigned (ir
.regcache
,
8053 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
8055 if (record_full_arch_list_add_mem (addr
, 128))
8070 /* In the future, maybe still need to deal with need_dasm. */
8071 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM
);
8072 if (record_full_arch_list_add_end ())
8078 printf_unfiltered (_("Process record does not support instruction 0x%02x "
8079 "at address %s.\n"),
8080 (unsigned int) (opcode
),
8081 paddress (gdbarch
, ir
.orig_addr
));
8085 static const int i386_record_regmap
[] =
8087 I386_EAX_REGNUM
, I386_ECX_REGNUM
, I386_EDX_REGNUM
, I386_EBX_REGNUM
,
8088 I386_ESP_REGNUM
, I386_EBP_REGNUM
, I386_ESI_REGNUM
, I386_EDI_REGNUM
,
8089 0, 0, 0, 0, 0, 0, 0, 0,
8090 I386_EIP_REGNUM
, I386_EFLAGS_REGNUM
, I386_CS_REGNUM
, I386_SS_REGNUM
,
8091 I386_DS_REGNUM
, I386_ES_REGNUM
, I386_FS_REGNUM
, I386_GS_REGNUM
8094 /* Check that the given address appears suitable for a fast
8095 tracepoint, which on x86-64 means that we need an instruction of at
8096 least 5 bytes, so that we can overwrite it with a 4-byte-offset
8097 jump and not have to worry about program jumps to an address in the
8098 middle of the tracepoint jump. On x86, it may be possible to use
8099 4-byte jumps with a 2-byte offset to a trampoline located in the
8100 bottom 64 KiB of memory. Returns 1 if OK, and writes a size
8101 of instruction to replace, and 0 if not, plus an explanatory
8105 i386_fast_tracepoint_valid_at (struct gdbarch
*gdbarch
, CORE_ADDR addr
,
8110 /* Ask the target for the minimum instruction length supported. */
8111 jumplen
= target_get_min_fast_tracepoint_insn_len ();
8115 /* If the target does not support the get_min_fast_tracepoint_insn_len
8116 operation, assume that fast tracepoints will always be implemented
8117 using 4-byte relative jumps on both x86 and x86-64. */
8120 else if (jumplen
== 0)
8122 /* If the target does support get_min_fast_tracepoint_insn_len but
8123 returns zero, then the IPA has not loaded yet. In this case,
8124 we optimistically assume that truncated 2-byte relative jumps
8125 will be available on x86, and compensate later if this assumption
8126 turns out to be incorrect. On x86-64 architectures, 4-byte relative
8127 jumps will always be used. */
8128 jumplen
= (register_size (gdbarch
, 0) == 8) ? 5 : 4;
8131 /* Check for fit. */
8132 len
= gdb_insn_length (gdbarch
, addr
);
8136 /* Return a bit of target-specific detail to add to the caller's
8137 generic failure message. */
8139 *msg
= string_printf (_("; instruction is only %d bytes long, "
8140 "need at least %d bytes for the jump"),
8152 /* Return a floating-point format for a floating-point variable of
8153 length LEN in bits. If non-NULL, NAME is the name of its type.
8154 If no suitable type is found, return NULL. */
8156 const struct floatformat
**
8157 i386_floatformat_for_type (struct gdbarch
*gdbarch
,
8158 const char *name
, int len
)
8160 if (len
== 128 && name
)
8161 if (strcmp (name
, "__float128") == 0
8162 || strcmp (name
, "_Float128") == 0
8163 || strcmp (name
, "complex _Float128") == 0)
8164 return floatformats_ia64_quad
;
8166 return default_floatformat_for_type (gdbarch
, name
, len
);
8170 i386_validate_tdesc_p (struct gdbarch_tdep
*tdep
,
8171 struct tdesc_arch_data
*tdesc_data
)
8173 const struct target_desc
*tdesc
= tdep
->tdesc
;
8174 const struct tdesc_feature
*feature_core
;
8176 const struct tdesc_feature
*feature_sse
, *feature_avx
, *feature_mpx
,
8177 *feature_avx512
, *feature_pkeys
;
8178 int i
, num_regs
, valid_p
;
8180 if (! tdesc_has_registers (tdesc
))
8183 /* Get core registers. */
8184 feature_core
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.core");
8185 if (feature_core
== NULL
)
8188 /* Get SSE registers. */
8189 feature_sse
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.sse");
8191 /* Try AVX registers. */
8192 feature_avx
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx");
8194 /* Try MPX registers. */
8195 feature_mpx
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.mpx");
8197 /* Try AVX512 registers. */
8198 feature_avx512
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx512");
8201 feature_pkeys
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.pkeys");
8205 /* The XCR0 bits. */
8208 /* AVX512 register description requires AVX register description. */
8212 tdep
->xcr0
= X86_XSTATE_AVX_AVX512_MASK
;
8214 /* It may have been set by OSABI initialization function. */
8215 if (tdep
->k0_regnum
< 0)
8217 tdep
->k_register_names
= i386_k_names
;
8218 tdep
->k0_regnum
= I386_K0_REGNUM
;
8221 for (i
= 0; i
< I387_NUM_K_REGS
; i
++)
8222 valid_p
&= tdesc_numbered_register (feature_avx512
, tdesc_data
,
8223 tdep
->k0_regnum
+ i
,
8226 if (tdep
->num_zmm_regs
== 0)
8228 tdep
->zmmh_register_names
= i386_zmmh_names
;
8229 tdep
->num_zmm_regs
= 8;
8230 tdep
->zmm0h_regnum
= I386_ZMM0H_REGNUM
;
8233 for (i
= 0; i
< tdep
->num_zmm_regs
; i
++)
8234 valid_p
&= tdesc_numbered_register (feature_avx512
, tdesc_data
,
8235 tdep
->zmm0h_regnum
+ i
,
8236 tdep
->zmmh_register_names
[i
]);
8238 for (i
= 0; i
< tdep
->num_xmm_avx512_regs
; i
++)
8239 valid_p
&= tdesc_numbered_register (feature_avx512
, tdesc_data
,
8240 tdep
->xmm16_regnum
+ i
,
8241 tdep
->xmm_avx512_register_names
[i
]);
8243 for (i
= 0; i
< tdep
->num_ymm_avx512_regs
; i
++)
8244 valid_p
&= tdesc_numbered_register (feature_avx512
, tdesc_data
,
8245 tdep
->ymm16h_regnum
+ i
,
8246 tdep
->ymm16h_register_names
[i
]);
8250 /* AVX register description requires SSE register description. */
8254 if (!feature_avx512
)
8255 tdep
->xcr0
= X86_XSTATE_AVX_MASK
;
8257 /* It may have been set by OSABI initialization function. */
8258 if (tdep
->num_ymm_regs
== 0)
8260 tdep
->ymmh_register_names
= i386_ymmh_names
;
8261 tdep
->num_ymm_regs
= 8;
8262 tdep
->ymm0h_regnum
= I386_YMM0H_REGNUM
;
8265 for (i
= 0; i
< tdep
->num_ymm_regs
; i
++)
8266 valid_p
&= tdesc_numbered_register (feature_avx
, tdesc_data
,
8267 tdep
->ymm0h_regnum
+ i
,
8268 tdep
->ymmh_register_names
[i
]);
8270 else if (feature_sse
)
8271 tdep
->xcr0
= X86_XSTATE_SSE_MASK
;
8274 tdep
->xcr0
= X86_XSTATE_X87_MASK
;
8275 tdep
->num_xmm_regs
= 0;
8278 num_regs
= tdep
->num_core_regs
;
8279 for (i
= 0; i
< num_regs
; i
++)
8280 valid_p
&= tdesc_numbered_register (feature_core
, tdesc_data
, i
,
8281 tdep
->register_names
[i
]);
8285 /* Need to include %mxcsr, so add one. */
8286 num_regs
+= tdep
->num_xmm_regs
+ 1;
8287 for (; i
< num_regs
; i
++)
8288 valid_p
&= tdesc_numbered_register (feature_sse
, tdesc_data
, i
,
8289 tdep
->register_names
[i
]);
8294 tdep
->xcr0
|= X86_XSTATE_MPX_MASK
;
8296 if (tdep
->bnd0r_regnum
< 0)
8298 tdep
->mpx_register_names
= i386_mpx_names
;
8299 tdep
->bnd0r_regnum
= I386_BND0R_REGNUM
;
8300 tdep
->bndcfgu_regnum
= I386_BNDCFGU_REGNUM
;
8303 for (i
= 0; i
< I387_NUM_MPX_REGS
; i
++)
8304 valid_p
&= tdesc_numbered_register (feature_mpx
, tdesc_data
,
8305 I387_BND0R_REGNUM (tdep
) + i
,
8306 tdep
->mpx_register_names
[i
]);
8311 tdep
->xcr0
|= X86_XSTATE_PKRU
;
8312 if (tdep
->pkru_regnum
< 0)
8314 tdep
->pkeys_register_names
= i386_pkeys_names
;
8315 tdep
->pkru_regnum
= I386_PKRU_REGNUM
;
8316 tdep
->num_pkeys_regs
= 1;
8319 for (i
= 0; i
< I387_NUM_PKEYS_REGS
; i
++)
8320 valid_p
&= tdesc_numbered_register (feature_pkeys
, tdesc_data
,
8321 I387_PKRU_REGNUM (tdep
) + i
,
8322 tdep
->pkeys_register_names
[i
]);
8330 /* Implement the type_align gdbarch function. */
8333 i386_type_align (struct gdbarch
*gdbarch
, struct type
*type
)
8335 type
= check_typedef (type
);
8337 if (gdbarch_ptr_bit (gdbarch
) == 32)
8339 if ((TYPE_CODE (type
) == TYPE_CODE_INT
8340 || TYPE_CODE (type
) == TYPE_CODE_FLT
)
8341 && TYPE_LENGTH (type
) > 4)
8344 /* Handle x86's funny long double. */
8345 if (TYPE_CODE (type
) == TYPE_CODE_FLT
8346 && gdbarch_long_double_bit (gdbarch
) == TYPE_LENGTH (type
) * 8)
8350 return TYPE_LENGTH (type
);
8354 /* Note: This is called for both i386 and amd64. */
8356 static struct gdbarch
*
8357 i386_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
8359 struct gdbarch_tdep
*tdep
;
8360 struct gdbarch
*gdbarch
;
8361 struct tdesc_arch_data
*tdesc_data
;
8362 const struct target_desc
*tdesc
;
8368 /* If there is already a candidate, use it. */
8369 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
8371 return arches
->gdbarch
;
8373 /* Allocate space for the new architecture. Assume i386 for now. */
8374 tdep
= XCNEW (struct gdbarch_tdep
);
8375 gdbarch
= gdbarch_alloc (&info
, tdep
);
8377 /* General-purpose registers. */
8378 tdep
->gregset_reg_offset
= NULL
;
8379 tdep
->gregset_num_regs
= I386_NUM_GREGS
;
8380 tdep
->sizeof_gregset
= 0;
8382 /* Floating-point registers. */
8383 tdep
->sizeof_fpregset
= I387_SIZEOF_FSAVE
;
8384 tdep
->fpregset
= &i386_fpregset
;
8386 /* The default settings include the FPU registers, the MMX registers
8387 and the SSE registers. This can be overridden for a specific ABI
8388 by adjusting the members `st0_regnum', `mm0_regnum' and
8389 `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers
8390 will show up in the output of "info all-registers". */
8392 tdep
->st0_regnum
= I386_ST0_REGNUM
;
8394 /* I386_NUM_XREGS includes %mxcsr, so substract one. */
8395 tdep
->num_xmm_regs
= I386_NUM_XREGS
- 1;
8397 tdep
->jb_pc_offset
= -1;
8398 tdep
->struct_return
= pcc_struct_return
;
8399 tdep
->sigtramp_start
= 0;
8400 tdep
->sigtramp_end
= 0;
8401 tdep
->sigtramp_p
= i386_sigtramp_p
;
8402 tdep
->sigcontext_addr
= NULL
;
8403 tdep
->sc_reg_offset
= NULL
;
8404 tdep
->sc_pc_offset
= -1;
8405 tdep
->sc_sp_offset
= -1;
8407 tdep
->xsave_xcr0_offset
= -1;
8409 tdep
->record_regmap
= i386_record_regmap
;
8411 set_gdbarch_type_align (gdbarch
, i386_type_align
);
8413 /* The format used for `long double' on almost all i386 targets is
8414 the i387 extended floating-point format. In fact, of all targets
8415 in the GCC 2.95 tree, only OSF/1 does it different, and insists
8416 on having a `long double' that's not `long' at all. */
8417 set_gdbarch_long_double_format (gdbarch
, floatformats_i387_ext
);
8419 /* Although the i387 extended floating-point has only 80 significant
8420 bits, a `long double' actually takes up 96, probably to enforce
8422 set_gdbarch_long_double_bit (gdbarch
, 96);
8424 /* Support for floating-point data type variants. */
8425 set_gdbarch_floatformat_for_type (gdbarch
, i386_floatformat_for_type
);
8427 /* Register numbers of various important registers. */
8428 set_gdbarch_sp_regnum (gdbarch
, I386_ESP_REGNUM
); /* %esp */
8429 set_gdbarch_pc_regnum (gdbarch
, I386_EIP_REGNUM
); /* %eip */
8430 set_gdbarch_ps_regnum (gdbarch
, I386_EFLAGS_REGNUM
); /* %eflags */
8431 set_gdbarch_fp0_regnum (gdbarch
, I386_ST0_REGNUM
); /* %st(0) */
8433 /* NOTE: kettenis/20040418: GCC does have two possible register
8434 numbering schemes on the i386: dbx and SVR4. These schemes
8435 differ in how they number %ebp, %esp, %eflags, and the
8436 floating-point registers, and are implemented by the arrays
8437 dbx_register_map[] and svr4_dbx_register_map in
8438 gcc/config/i386.c. GCC also defines a third numbering scheme in
8439 gcc/config/i386.c, which it designates as the "default" register
8440 map used in 64bit mode. This last register numbering scheme is
8441 implemented in dbx64_register_map, and is used for AMD64; see
8444 Currently, each GCC i386 target always uses the same register
8445 numbering scheme across all its supported debugging formats
8446 i.e. SDB (COFF), stabs and DWARF 2. This is because
8447 gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the
8448 DBX_REGISTER_NUMBER macro which is defined by each target's
8449 respective config header in a manner independent of the requested
8450 output debugging format.
8452 This does not match the arrangement below, which presumes that
8453 the SDB and stabs numbering schemes differ from the DWARF and
8454 DWARF 2 ones. The reason for this arrangement is that it is
8455 likely to get the numbering scheme for the target's
8456 default/native debug format right. For targets where GCC is the
8457 native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for
8458 targets where the native toolchain uses a different numbering
8459 scheme for a particular debug format (stabs-in-ELF on Solaris)
8460 the defaults below will have to be overridden, like
8461 i386_elf_init_abi() does. */
8463 /* Use the dbx register numbering scheme for stabs and COFF. */
8464 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
8465 set_gdbarch_sdb_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
8467 /* Use the SVR4 register numbering scheme for DWARF 2. */
8468 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, i386_svr4_dwarf_reg_to_regnum
);
8470 /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to
8471 be in use on any of the supported i386 targets. */
8473 set_gdbarch_print_float_info (gdbarch
, i387_print_float_info
);
8475 set_gdbarch_get_longjmp_target (gdbarch
, i386_get_longjmp_target
);
8477 /* Call dummy code. */
8478 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
8479 set_gdbarch_push_dummy_code (gdbarch
, i386_push_dummy_code
);
8480 set_gdbarch_push_dummy_call (gdbarch
, i386_push_dummy_call
);
8481 set_gdbarch_frame_align (gdbarch
, i386_frame_align
);
8483 set_gdbarch_convert_register_p (gdbarch
, i386_convert_register_p
);
8484 set_gdbarch_register_to_value (gdbarch
, i386_register_to_value
);
8485 set_gdbarch_value_to_register (gdbarch
, i386_value_to_register
);
8487 set_gdbarch_return_value (gdbarch
, i386_return_value
);
8489 set_gdbarch_skip_prologue (gdbarch
, i386_skip_prologue
);
8491 /* Stack grows downward. */
8492 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
8494 set_gdbarch_breakpoint_kind_from_pc (gdbarch
, i386_breakpoint::kind_from_pc
);
8495 set_gdbarch_sw_breakpoint_from_kind (gdbarch
, i386_breakpoint::bp_from_kind
);
8497 set_gdbarch_decr_pc_after_break (gdbarch
, 1);
8498 set_gdbarch_max_insn_length (gdbarch
, I386_MAX_INSN_LEN
);
8500 set_gdbarch_frame_args_skip (gdbarch
, 8);
8502 set_gdbarch_print_insn (gdbarch
, i386_print_insn
);
8504 set_gdbarch_dummy_id (gdbarch
, i386_dummy_id
);
8506 set_gdbarch_unwind_pc (gdbarch
, i386_unwind_pc
);
8508 /* Add the i386 register groups. */
8509 i386_add_reggroups (gdbarch
);
8510 tdep
->register_reggroup_p
= i386_register_reggroup_p
;
8512 /* Helper for function argument information. */
8513 set_gdbarch_fetch_pointer_argument (gdbarch
, i386_fetch_pointer_argument
);
8515 /* Hook the function epilogue frame unwinder. This unwinder is
8516 appended to the list first, so that it supercedes the DWARF
8517 unwinder in function epilogues (where the DWARF unwinder
8518 currently fails). */
8519 frame_unwind_append_unwinder (gdbarch
, &i386_epilogue_frame_unwind
);
8521 /* Hook in the DWARF CFI frame unwinder. This unwinder is appended
8522 to the list before the prologue-based unwinders, so that DWARF
8523 CFI info will be used if it is available. */
8524 dwarf2_append_unwinders (gdbarch
);
8526 frame_base_set_default (gdbarch
, &i386_frame_base
);
8528 /* Pseudo registers may be changed by amd64_init_abi. */
8529 set_gdbarch_pseudo_register_read_value (gdbarch
,
8530 i386_pseudo_register_read_value
);
8531 set_gdbarch_pseudo_register_write (gdbarch
, i386_pseudo_register_write
);
8532 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
8533 i386_ax_pseudo_register_collect
);
8535 set_tdesc_pseudo_register_type (gdbarch
, i386_pseudo_register_type
);
8536 set_tdesc_pseudo_register_name (gdbarch
, i386_pseudo_register_name
);
8538 /* Override the normal target description method to make the AVX
8539 upper halves anonymous. */
8540 set_gdbarch_register_name (gdbarch
, i386_register_name
);
8542 /* Even though the default ABI only includes general-purpose registers,
8543 floating-point registers and the SSE registers, we have to leave a
8544 gap for the upper AVX, MPX and AVX512 registers. */
8545 set_gdbarch_num_regs (gdbarch
, I386_PKEYS_NUM_REGS
);
8547 set_gdbarch_gnu_triplet_regexp (gdbarch
, i386_gnu_triplet_regexp
);
8549 /* Get the x86 target description from INFO. */
8550 tdesc
= info
.target_desc
;
8551 if (! tdesc_has_registers (tdesc
))
8552 tdesc
= i386_target_description (X86_XSTATE_SSE_MASK
);
8553 tdep
->tdesc
= tdesc
;
8555 tdep
->num_core_regs
= I386_NUM_GREGS
+ I387_NUM_REGS
;
8556 tdep
->register_names
= i386_register_names
;
8558 /* No upper YMM registers. */
8559 tdep
->ymmh_register_names
= NULL
;
8560 tdep
->ymm0h_regnum
= -1;
8562 /* No upper ZMM registers. */
8563 tdep
->zmmh_register_names
= NULL
;
8564 tdep
->zmm0h_regnum
= -1;
8566 /* No high XMM registers. */
8567 tdep
->xmm_avx512_register_names
= NULL
;
8568 tdep
->xmm16_regnum
= -1;
8570 /* No upper YMM16-31 registers. */
8571 tdep
->ymm16h_register_names
= NULL
;
8572 tdep
->ymm16h_regnum
= -1;
8574 tdep
->num_byte_regs
= 8;
8575 tdep
->num_word_regs
= 8;
8576 tdep
->num_dword_regs
= 0;
8577 tdep
->num_mmx_regs
= 8;
8578 tdep
->num_ymm_regs
= 0;
8580 /* No MPX registers. */
8581 tdep
->bnd0r_regnum
= -1;
8582 tdep
->bndcfgu_regnum
= -1;
8584 /* No AVX512 registers. */
8585 tdep
->k0_regnum
= -1;
8586 tdep
->num_zmm_regs
= 0;
8587 tdep
->num_ymm_avx512_regs
= 0;
8588 tdep
->num_xmm_avx512_regs
= 0;
8590 /* No PKEYS registers */
8591 tdep
->pkru_regnum
= -1;
8592 tdep
->num_pkeys_regs
= 0;
8594 tdesc_data
= tdesc_data_alloc ();
8596 set_gdbarch_relocate_instruction (gdbarch
, i386_relocate_instruction
);
8598 set_gdbarch_gen_return_address (gdbarch
, i386_gen_return_address
);
8600 set_gdbarch_insn_is_call (gdbarch
, i386_insn_is_call
);
8601 set_gdbarch_insn_is_ret (gdbarch
, i386_insn_is_ret
);
8602 set_gdbarch_insn_is_jump (gdbarch
, i386_insn_is_jump
);
8604 /* Hook in ABI-specific overrides, if they have been registered.
8605 Note: If INFO specifies a 64 bit arch, this is where we turn
8606 a 32-bit i386 into a 64-bit amd64. */
8607 info
.tdesc_data
= tdesc_data
;
8608 gdbarch_init_osabi (info
, gdbarch
);
8610 if (!i386_validate_tdesc_p (tdep
, tdesc_data
))
8612 tdesc_data_cleanup (tdesc_data
);
8614 gdbarch_free (gdbarch
);
8618 num_bnd_cooked
= (tdep
->bnd0r_regnum
> 0 ? I387_NUM_BND_REGS
: 0);
8620 /* Wire in pseudo registers. Number of pseudo registers may be
8622 set_gdbarch_num_pseudo_regs (gdbarch
, (tdep
->num_byte_regs
8623 + tdep
->num_word_regs
8624 + tdep
->num_dword_regs
8625 + tdep
->num_mmx_regs
8626 + tdep
->num_ymm_regs
8628 + tdep
->num_ymm_avx512_regs
8629 + tdep
->num_zmm_regs
));
8631 /* Target description may be changed. */
8632 tdesc
= tdep
->tdesc
;
8634 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
8636 /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */
8637 set_gdbarch_register_reggroup_p (gdbarch
, tdep
->register_reggroup_p
);
8639 /* Make %al the first pseudo-register. */
8640 tdep
->al_regnum
= gdbarch_num_regs (gdbarch
);
8641 tdep
->ax_regnum
= tdep
->al_regnum
+ tdep
->num_byte_regs
;
8643 ymm0_regnum
= tdep
->ax_regnum
+ tdep
->num_word_regs
;
8644 if (tdep
->num_dword_regs
)
8646 /* Support dword pseudo-register if it hasn't been disabled. */
8647 tdep
->eax_regnum
= ymm0_regnum
;
8648 ymm0_regnum
+= tdep
->num_dword_regs
;
8651 tdep
->eax_regnum
= -1;
8653 mm0_regnum
= ymm0_regnum
;
8654 if (tdep
->num_ymm_regs
)
8656 /* Support YMM pseudo-register if it is available. */
8657 tdep
->ymm0_regnum
= ymm0_regnum
;
8658 mm0_regnum
+= tdep
->num_ymm_regs
;
8661 tdep
->ymm0_regnum
= -1;
8663 if (tdep
->num_ymm_avx512_regs
)
8665 /* Support YMM16-31 pseudo registers if available. */
8666 tdep
->ymm16_regnum
= mm0_regnum
;
8667 mm0_regnum
+= tdep
->num_ymm_avx512_regs
;
8670 tdep
->ymm16_regnum
= -1;
8672 if (tdep
->num_zmm_regs
)
8674 /* Support ZMM pseudo-register if it is available. */
8675 tdep
->zmm0_regnum
= mm0_regnum
;
8676 mm0_regnum
+= tdep
->num_zmm_regs
;
8679 tdep
->zmm0_regnum
= -1;
8681 bnd0_regnum
= mm0_regnum
;
8682 if (tdep
->num_mmx_regs
!= 0)
8684 /* Support MMX pseudo-register if MMX hasn't been disabled. */
8685 tdep
->mm0_regnum
= mm0_regnum
;
8686 bnd0_regnum
+= tdep
->num_mmx_regs
;
8689 tdep
->mm0_regnum
= -1;
8691 if (tdep
->bnd0r_regnum
> 0)
8692 tdep
->bnd0_regnum
= bnd0_regnum
;
8694 tdep
-> bnd0_regnum
= -1;
8696 /* Hook in the legacy prologue-based unwinders last (fallback). */
8697 frame_unwind_append_unwinder (gdbarch
, &i386_stack_tramp_frame_unwind
);
8698 frame_unwind_append_unwinder (gdbarch
, &i386_sigtramp_frame_unwind
);
8699 frame_unwind_append_unwinder (gdbarch
, &i386_frame_unwind
);
8701 /* If we have a register mapping, enable the generic core file
8702 support, unless it has already been enabled. */
8703 if (tdep
->gregset_reg_offset
8704 && !gdbarch_iterate_over_regset_sections_p (gdbarch
))
8705 set_gdbarch_iterate_over_regset_sections
8706 (gdbarch
, i386_iterate_over_regset_sections
);
8708 set_gdbarch_fast_tracepoint_valid_at (gdbarch
,
8709 i386_fast_tracepoint_valid_at
);
8716 /* Return the target description for a specified XSAVE feature mask. */
8718 const struct target_desc
*
8719 i386_target_description (uint64_t xcr0
)
8721 static target_desc
*i386_tdescs \
8722 [2/*SSE*/][2/*AVX*/][2/*MPX*/][2/*AVX512*/][2/*PKRU*/] = {};
8723 target_desc
**tdesc
;
8725 tdesc
= &i386_tdescs
[(xcr0
& X86_XSTATE_SSE
) ? 1 : 0]
8726 [(xcr0
& X86_XSTATE_AVX
) ? 1 : 0]
8727 [(xcr0
& X86_XSTATE_MPX
) ? 1 : 0]
8728 [(xcr0
& X86_XSTATE_AVX512
) ? 1 : 0]
8729 [(xcr0
& X86_XSTATE_PKRU
) ? 1 : 0];
8732 *tdesc
= i386_create_target_description (xcr0
, false);
8737 #define MPX_BASE_MASK (~(ULONGEST) 0xfff)
8739 /* Find the bound directory base address. */
8741 static unsigned long
8742 i386_mpx_bd_base (void)
8744 struct regcache
*rcache
;
8745 struct gdbarch_tdep
*tdep
;
8747 enum register_status regstatus
;
8749 rcache
= get_current_regcache ();
8750 tdep
= gdbarch_tdep (rcache
->arch ());
8752 regstatus
= regcache_raw_read_unsigned (rcache
, tdep
->bndcfgu_regnum
, &ret
);
8754 if (regstatus
!= REG_VALID
)
8755 error (_("BNDCFGU register invalid, read status %d."), regstatus
);
8757 return ret
& MPX_BASE_MASK
;
8761 i386_mpx_enabled (void)
8763 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_current_arch ());
8764 const struct target_desc
*tdesc
= tdep
->tdesc
;
8766 return (tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.mpx") != NULL
);
8769 #define MPX_BD_MASK 0xfffffff00000ULL /* select bits [47:20] */
8770 #define MPX_BT_MASK 0x0000000ffff8 /* select bits [19:3] */
8771 #define MPX_BD_MASK_32 0xfffff000 /* select bits [31:12] */
8772 #define MPX_BT_MASK_32 0x00000ffc /* select bits [11:2] */
8774 /* Find the bound table entry given the pointer location and the base
8775 address of the table. */
8778 i386_mpx_get_bt_entry (CORE_ADDR ptr
, CORE_ADDR bd_base
)
8782 CORE_ADDR mpx_bd_mask
, bd_ptr_r_shift
, bd_ptr_l_shift
;
8783 CORE_ADDR bt_mask
, bt_select_r_shift
, bt_select_l_shift
;
8784 CORE_ADDR bd_entry_addr
;
8787 struct gdbarch
*gdbarch
= get_current_arch ();
8788 struct type
*data_ptr_type
= builtin_type (gdbarch
)->builtin_data_ptr
;
8791 if (gdbarch_ptr_bit (gdbarch
) == 64)
8793 mpx_bd_mask
= (CORE_ADDR
) MPX_BD_MASK
;
8794 bd_ptr_r_shift
= 20;
8796 bt_select_r_shift
= 3;
8797 bt_select_l_shift
= 5;
8798 bt_mask
= (CORE_ADDR
) MPX_BT_MASK
;
8800 if ( sizeof (CORE_ADDR
) == 4)
8801 error (_("bound table examination not supported\
8802 for 64-bit process with 32-bit GDB"));
8806 mpx_bd_mask
= MPX_BD_MASK_32
;
8807 bd_ptr_r_shift
= 12;
8809 bt_select_r_shift
= 2;
8810 bt_select_l_shift
= 4;
8811 bt_mask
= MPX_BT_MASK_32
;
8814 offset1
= ((ptr
& mpx_bd_mask
) >> bd_ptr_r_shift
) << bd_ptr_l_shift
;
8815 bd_entry_addr
= bd_base
+ offset1
;
8816 bd_entry
= read_memory_typed_address (bd_entry_addr
, data_ptr_type
);
8818 if ((bd_entry
& 0x1) == 0)
8819 error (_("Invalid bounds directory entry at %s."),
8820 paddress (get_current_arch (), bd_entry_addr
));
8822 /* Clearing status bit. */
8824 bt_addr
= bd_entry
& ~bt_select_r_shift
;
8825 offset2
= ((ptr
& bt_mask
) >> bt_select_r_shift
) << bt_select_l_shift
;
8827 return bt_addr
+ offset2
;
8830 /* Print routine for the mpx bounds. */
8833 i386_mpx_print_bounds (const CORE_ADDR bt_entry
[4])
8835 struct ui_out
*uiout
= current_uiout
;
8837 struct gdbarch
*gdbarch
= get_current_arch ();
8838 CORE_ADDR onecompl
= ~((CORE_ADDR
) 0);
8839 int bounds_in_map
= ((~bt_entry
[1] == 0 && bt_entry
[0] == onecompl
) ? 1 : 0);
8841 if (bounds_in_map
== 1)
8843 uiout
->text ("Null bounds on map:");
8844 uiout
->text (" pointer value = ");
8845 uiout
->field_core_addr ("pointer-value", gdbarch
, bt_entry
[2]);
8851 uiout
->text ("{lbound = ");
8852 uiout
->field_core_addr ("lower-bound", gdbarch
, bt_entry
[0]);
8853 uiout
->text (", ubound = ");
8855 /* The upper bound is stored in 1's complement. */
8856 uiout
->field_core_addr ("upper-bound", gdbarch
, ~bt_entry
[1]);
8857 uiout
->text ("}: pointer value = ");
8858 uiout
->field_core_addr ("pointer-value", gdbarch
, bt_entry
[2]);
8860 if (gdbarch_ptr_bit (gdbarch
) == 64)
8861 size
= ( (~(int64_t) bt_entry
[1]) - (int64_t) bt_entry
[0]);
8863 size
= ( ~((int32_t) bt_entry
[1]) - (int32_t) bt_entry
[0]);
8865 /* In case the bounds are 0x0 and 0xffff... the difference will be -1.
8866 -1 represents in this sense full memory access, and there is no need
8869 size
= (size
> -1 ? size
+ 1 : size
);
8870 uiout
->text (", size = ");
8871 uiout
->field_fmt ("size", "%s", plongest (size
));
8873 uiout
->text (", metadata = ");
8874 uiout
->field_core_addr ("metadata", gdbarch
, bt_entry
[3]);
8879 /* Implement the command "show mpx bound". */
8882 i386_mpx_info_bounds (const char *args
, int from_tty
)
8884 CORE_ADDR bd_base
= 0;
8886 CORE_ADDR bt_entry_addr
= 0;
8887 CORE_ADDR bt_entry
[4];
8889 struct gdbarch
*gdbarch
= get_current_arch ();
8890 struct type
*data_ptr_type
= builtin_type (gdbarch
)->builtin_data_ptr
;
8892 if (gdbarch_bfd_arch_info (gdbarch
)->arch
!= bfd_arch_i386
8893 || !i386_mpx_enabled ())
8895 printf_unfiltered (_("Intel Memory Protection Extensions not "
8896 "supported on this target.\n"));
8902 printf_unfiltered (_("Address of pointer variable expected.\n"));
8906 addr
= parse_and_eval_address (args
);
8908 bd_base
= i386_mpx_bd_base ();
8909 bt_entry_addr
= i386_mpx_get_bt_entry (addr
, bd_base
);
8911 memset (bt_entry
, 0, sizeof (bt_entry
));
8913 for (i
= 0; i
< 4; i
++)
8914 bt_entry
[i
] = read_memory_typed_address (bt_entry_addr
8915 + i
* TYPE_LENGTH (data_ptr_type
),
8918 i386_mpx_print_bounds (bt_entry
);
8921 /* Implement the command "set mpx bound". */
8924 i386_mpx_set_bounds (const char *args
, int from_tty
)
8926 CORE_ADDR bd_base
= 0;
8927 CORE_ADDR addr
, lower
, upper
;
8928 CORE_ADDR bt_entry_addr
= 0;
8929 CORE_ADDR bt_entry
[2];
8930 const char *input
= args
;
8932 struct gdbarch
*gdbarch
= get_current_arch ();
8933 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
8934 struct type
*data_ptr_type
= builtin_type (gdbarch
)->builtin_data_ptr
;
8936 if (gdbarch_bfd_arch_info (gdbarch
)->arch
!= bfd_arch_i386
8937 || !i386_mpx_enabled ())
8938 error (_("Intel Memory Protection Extensions not supported\
8942 error (_("Pointer value expected."));
8944 addr
= value_as_address (parse_to_comma_and_eval (&input
));
8946 if (input
[0] == ',')
8948 if (input
[0] == '\0')
8949 error (_("wrong number of arguments: missing lower and upper bound."));
8950 lower
= value_as_address (parse_to_comma_and_eval (&input
));
8952 if (input
[0] == ',')
8954 if (input
[0] == '\0')
8955 error (_("Wrong number of arguments; Missing upper bound."));
8956 upper
= value_as_address (parse_to_comma_and_eval (&input
));
8958 bd_base
= i386_mpx_bd_base ();
8959 bt_entry_addr
= i386_mpx_get_bt_entry (addr
, bd_base
);
8960 for (i
= 0; i
< 2; i
++)
8961 bt_entry
[i
] = read_memory_typed_address (bt_entry_addr
8962 + i
* TYPE_LENGTH (data_ptr_type
),
8964 bt_entry
[0] = (uint64_t) lower
;
8965 bt_entry
[1] = ~(uint64_t) upper
;
8967 for (i
= 0; i
< 2; i
++)
8968 write_memory_unsigned_integer (bt_entry_addr
8969 + i
* TYPE_LENGTH (data_ptr_type
),
8970 TYPE_LENGTH (data_ptr_type
), byte_order
,
8974 static struct cmd_list_element
*mpx_set_cmdlist
, *mpx_show_cmdlist
;
8976 /* Helper function for the CLI commands. */
8979 set_mpx_cmd (const char *args
, int from_tty
)
8981 help_list (mpx_set_cmdlist
, "set mpx ", all_commands
, gdb_stdout
);
8984 /* Helper function for the CLI commands. */
8987 show_mpx_cmd (const char *args
, int from_tty
)
8989 cmd_show_list (mpx_show_cmdlist
, from_tty
, "");
8993 _initialize_i386_tdep (void)
8995 register_gdbarch_init (bfd_arch_i386
, i386_gdbarch_init
);
8997 /* Add the variable that controls the disassembly flavor. */
8998 add_setshow_enum_cmd ("disassembly-flavor", no_class
, valid_flavors
,
8999 &disassembly_flavor
, _("\
9000 Set the disassembly flavor."), _("\
9001 Show the disassembly flavor."), _("\
9002 The valid values are \"att\" and \"intel\", and the default value is \"att\"."),
9004 NULL
, /* FIXME: i18n: */
9005 &setlist
, &showlist
);
9007 /* Add the variable that controls the convention for returning
9009 add_setshow_enum_cmd ("struct-convention", no_class
, valid_conventions
,
9010 &struct_convention
, _("\
9011 Set the convention for returning small structs."), _("\
9012 Show the convention for returning small structs."), _("\
9013 Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\
9016 NULL
, /* FIXME: i18n: */
9017 &setlist
, &showlist
);
9019 /* Add "mpx" prefix for the set commands. */
9021 add_prefix_cmd ("mpx", class_support
, set_mpx_cmd
, _("\
9022 Set Intel Memory Protection Extensions specific variables."),
9023 &mpx_set_cmdlist
, "set mpx ",
9024 0 /* allow-unknown */, &setlist
);
9026 /* Add "mpx" prefix for the show commands. */
9028 add_prefix_cmd ("mpx", class_support
, show_mpx_cmd
, _("\
9029 Show Intel Memory Protection Extensions specific variables."),
9030 &mpx_show_cmdlist
, "show mpx ",
9031 0 /* allow-unknown */, &showlist
);
9033 /* Add "bound" command for the show mpx commands list. */
9035 add_cmd ("bound", no_class
, i386_mpx_info_bounds
,
9036 "Show the memory bounds for a given array/pointer storage\
9037 in the bound table.",
9040 /* Add "bound" command for the set mpx commands list. */
9042 add_cmd ("bound", no_class
, i386_mpx_set_bounds
,
9043 "Set the memory bounds for a given array/pointer storage\
9044 in the bound table.",
9047 gdbarch_register_osabi (bfd_arch_i386
, 0, GDB_OSABI_SVR4
,
9048 i386_svr4_init_abi
);
9050 /* Initialize the i386-specific register groups. */
9051 i386_init_reggroups ();
9053 /* Tell remote stub that we support XML target description. */
9054 register_remote_support_xml ("i386");
9062 { "i386/i386.xml", X86_XSTATE_SSE_MASK
},
9063 { "i386/i386-mmx.xml", X86_XSTATE_X87_MASK
},
9064 { "i386/i386-avx.xml", X86_XSTATE_AVX_MASK
},
9065 { "i386/i386-mpx.xml", X86_XSTATE_MPX_MASK
},
9066 { "i386/i386-avx-mpx.xml", X86_XSTATE_AVX_MPX_MASK
},
9067 { "i386/i386-avx-avx512.xml", X86_XSTATE_AVX_AVX512_MASK
},
9068 { "i386/i386-avx-mpx-avx512-pku.xml",
9069 X86_XSTATE_AVX_MPX_AVX512_PKU_MASK
},
9072 for (auto &a
: xml_masks
)
9074 auto tdesc
= i386_target_description (a
.mask
);
9076 selftests::record_xml_tdesc (a
.xml
, tdesc
);
9078 #endif /* GDB_SELF_TEST */