1 /* Intel 386 target-dependent stuff.
3 Copyright (C) 1988-2020 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "opcode/i386.h"
22 #include "arch-utils.h"
24 #include "dummy-frame.h"
25 #include "dwarf2/frame.h"
27 #include "frame-base.h"
28 #include "frame-unwind.h"
37 #include "reggroups.h"
42 #include "target-float.h"
47 #include "i386-tdep.h"
48 #include "i387-tdep.h"
49 #include "gdbsupport/x86-xstate.h"
53 #include "record-full.h"
54 #include "target-descriptions.h"
55 #include "arch/i386.h"
60 #include "stap-probe.h"
61 #include "user-regs.h"
62 #include "cli/cli-utils.h"
63 #include "expression.h"
64 #include "parser-defs.h"
67 #include <unordered_set>
72 static const char * const i386_register_names
[] =
74 "eax", "ecx", "edx", "ebx",
75 "esp", "ebp", "esi", "edi",
76 "eip", "eflags", "cs", "ss",
77 "ds", "es", "fs", "gs",
78 "st0", "st1", "st2", "st3",
79 "st4", "st5", "st6", "st7",
80 "fctrl", "fstat", "ftag", "fiseg",
81 "fioff", "foseg", "fooff", "fop",
82 "xmm0", "xmm1", "xmm2", "xmm3",
83 "xmm4", "xmm5", "xmm6", "xmm7",
87 static const char * const i386_zmm_names
[] =
89 "zmm0", "zmm1", "zmm2", "zmm3",
90 "zmm4", "zmm5", "zmm6", "zmm7"
93 static const char * const i386_zmmh_names
[] =
95 "zmm0h", "zmm1h", "zmm2h", "zmm3h",
96 "zmm4h", "zmm5h", "zmm6h", "zmm7h"
99 static const char * const i386_k_names
[] =
101 "k0", "k1", "k2", "k3",
102 "k4", "k5", "k6", "k7"
105 static const char * const i386_ymm_names
[] =
107 "ymm0", "ymm1", "ymm2", "ymm3",
108 "ymm4", "ymm5", "ymm6", "ymm7",
111 static const char * const i386_ymmh_names
[] =
113 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
114 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
117 static const char * const i386_mpx_names
[] =
119 "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus"
122 static const char * const i386_pkeys_names
[] =
127 /* Register names for MPX pseudo-registers. */
129 static const char * const i386_bnd_names
[] =
131 "bnd0", "bnd1", "bnd2", "bnd3"
134 /* Register names for MMX pseudo-registers. */
136 static const char * const i386_mmx_names
[] =
138 "mm0", "mm1", "mm2", "mm3",
139 "mm4", "mm5", "mm6", "mm7"
142 /* Register names for byte pseudo-registers. */
144 static const char * const i386_byte_names
[] =
146 "al", "cl", "dl", "bl",
147 "ah", "ch", "dh", "bh"
150 /* Register names for word pseudo-registers. */
152 static const char * const i386_word_names
[] =
154 "ax", "cx", "dx", "bx",
158 /* Constant used for reading/writing pseudo registers. In 64-bit mode, we have
159 16 lower ZMM regs that extend corresponding xmm/ymm registers. In addition,
160 we have 16 upper ZMM regs that have to be handled differently. */
162 const int num_lower_zmm_regs
= 16;
167 i386_mmx_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
169 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
170 int mm0_regnum
= tdep
->mm0_regnum
;
175 regnum
-= mm0_regnum
;
176 return regnum
>= 0 && regnum
< tdep
->num_mmx_regs
;
182 i386_byte_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
184 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
186 regnum
-= tdep
->al_regnum
;
187 return regnum
>= 0 && regnum
< tdep
->num_byte_regs
;
193 i386_word_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
195 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
197 regnum
-= tdep
->ax_regnum
;
198 return regnum
>= 0 && regnum
< tdep
->num_word_regs
;
201 /* Dword register? */
204 i386_dword_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
206 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
207 int eax_regnum
= tdep
->eax_regnum
;
212 regnum
-= eax_regnum
;
213 return regnum
>= 0 && regnum
< tdep
->num_dword_regs
;
216 /* AVX512 register? */
219 i386_zmmh_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
221 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
222 int zmm0h_regnum
= tdep
->zmm0h_regnum
;
224 if (zmm0h_regnum
< 0)
227 regnum
-= zmm0h_regnum
;
228 return regnum
>= 0 && regnum
< tdep
->num_zmm_regs
;
232 i386_zmm_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
234 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
235 int zmm0_regnum
= tdep
->zmm0_regnum
;
240 regnum
-= zmm0_regnum
;
241 return regnum
>= 0 && regnum
< tdep
->num_zmm_regs
;
245 i386_k_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
247 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
248 int k0_regnum
= tdep
->k0_regnum
;
254 return regnum
>= 0 && regnum
< I387_NUM_K_REGS
;
258 i386_ymmh_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
260 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
261 int ymm0h_regnum
= tdep
->ymm0h_regnum
;
263 if (ymm0h_regnum
< 0)
266 regnum
-= ymm0h_regnum
;
267 return regnum
>= 0 && regnum
< tdep
->num_ymm_regs
;
273 i386_ymm_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
275 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
276 int ymm0_regnum
= tdep
->ymm0_regnum
;
281 regnum
-= ymm0_regnum
;
282 return regnum
>= 0 && regnum
< tdep
->num_ymm_regs
;
286 i386_ymmh_avx512_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
288 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
289 int ymm16h_regnum
= tdep
->ymm16h_regnum
;
291 if (ymm16h_regnum
< 0)
294 regnum
-= ymm16h_regnum
;
295 return regnum
>= 0 && regnum
< tdep
->num_ymm_avx512_regs
;
299 i386_ymm_avx512_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
301 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
302 int ymm16_regnum
= tdep
->ymm16_regnum
;
304 if (ymm16_regnum
< 0)
307 regnum
-= ymm16_regnum
;
308 return regnum
>= 0 && regnum
< tdep
->num_ymm_avx512_regs
;
314 i386_bnd_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
316 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
317 int bnd0_regnum
= tdep
->bnd0_regnum
;
322 regnum
-= bnd0_regnum
;
323 return regnum
>= 0 && regnum
< I387_NUM_BND_REGS
;
329 i386_xmm_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
331 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
332 int num_xmm_regs
= I387_NUM_XMM_REGS (tdep
);
334 if (num_xmm_regs
== 0)
337 regnum
-= I387_XMM0_REGNUM (tdep
);
338 return regnum
>= 0 && regnum
< num_xmm_regs
;
341 /* XMM_512 register? */
344 i386_xmm_avx512_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
346 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
347 int num_xmm_avx512_regs
= I387_NUM_XMM_AVX512_REGS (tdep
);
349 if (num_xmm_avx512_regs
== 0)
352 regnum
-= I387_XMM16_REGNUM (tdep
);
353 return regnum
>= 0 && regnum
< num_xmm_avx512_regs
;
357 i386_mxcsr_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
359 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
361 if (I387_NUM_XMM_REGS (tdep
) == 0)
364 return (regnum
== I387_MXCSR_REGNUM (tdep
));
370 i386_fp_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
372 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
374 if (I387_ST0_REGNUM (tdep
) < 0)
377 return (I387_ST0_REGNUM (tdep
) <= regnum
378 && regnum
< I387_FCTRL_REGNUM (tdep
));
382 i386_fpc_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
384 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
386 if (I387_ST0_REGNUM (tdep
) < 0)
389 return (I387_FCTRL_REGNUM (tdep
) <= regnum
390 && regnum
< I387_XMM0_REGNUM (tdep
));
393 /* BNDr (raw) register? */
396 i386_bndr_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
398 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
400 if (I387_BND0R_REGNUM (tdep
) < 0)
403 regnum
-= tdep
->bnd0r_regnum
;
404 return regnum
>= 0 && regnum
< I387_NUM_BND_REGS
;
407 /* BND control register? */
410 i386_mpx_ctrl_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
412 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
414 if (I387_BNDCFGU_REGNUM (tdep
) < 0)
417 regnum
-= I387_BNDCFGU_REGNUM (tdep
);
418 return regnum
>= 0 && regnum
< I387_NUM_MPX_CTRL_REGS
;
424 i386_pkru_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
426 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
427 int pkru_regnum
= tdep
->pkru_regnum
;
432 regnum
-= pkru_regnum
;
433 return regnum
>= 0 && regnum
< I387_NUM_PKEYS_REGS
;
436 /* Return the name of register REGNUM, or the empty string if it is
437 an anonymous register. */
440 i386_register_name (struct gdbarch
*gdbarch
, int regnum
)
442 /* Hide the upper YMM registers. */
443 if (i386_ymmh_regnum_p (gdbarch
, regnum
))
446 /* Hide the upper YMM16-31 registers. */
447 if (i386_ymmh_avx512_regnum_p (gdbarch
, regnum
))
450 /* Hide the upper ZMM registers. */
451 if (i386_zmmh_regnum_p (gdbarch
, regnum
))
454 return tdesc_register_name (gdbarch
, regnum
);
457 /* Return the name of register REGNUM. */
460 i386_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
462 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
463 if (i386_bnd_regnum_p (gdbarch
, regnum
))
464 return i386_bnd_names
[regnum
- tdep
->bnd0_regnum
];
465 if (i386_mmx_regnum_p (gdbarch
, regnum
))
466 return i386_mmx_names
[regnum
- I387_MM0_REGNUM (tdep
)];
467 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
468 return i386_ymm_names
[regnum
- tdep
->ymm0_regnum
];
469 else if (i386_zmm_regnum_p (gdbarch
, regnum
))
470 return i386_zmm_names
[regnum
- tdep
->zmm0_regnum
];
471 else if (i386_byte_regnum_p (gdbarch
, regnum
))
472 return i386_byte_names
[regnum
- tdep
->al_regnum
];
473 else if (i386_word_regnum_p (gdbarch
, regnum
))
474 return i386_word_names
[regnum
- tdep
->ax_regnum
];
476 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
479 /* Convert a dbx register number REG to the appropriate register
480 number used by GDB. */
483 i386_dbx_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
485 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
487 /* This implements what GCC calls the "default" register map
488 (dbx_register_map[]). */
490 if (reg
>= 0 && reg
<= 7)
492 /* General-purpose registers. The debug info calls %ebp
493 register 4, and %esp register 5. */
500 else if (reg
>= 12 && reg
<= 19)
502 /* Floating-point registers. */
503 return reg
- 12 + I387_ST0_REGNUM (tdep
);
505 else if (reg
>= 21 && reg
<= 28)
508 int ymm0_regnum
= tdep
->ymm0_regnum
;
511 && i386_xmm_regnum_p (gdbarch
, reg
))
512 return reg
- 21 + ymm0_regnum
;
514 return reg
- 21 + I387_XMM0_REGNUM (tdep
);
516 else if (reg
>= 29 && reg
<= 36)
519 return reg
- 29 + I387_MM0_REGNUM (tdep
);
522 /* This will hopefully provoke a warning. */
523 return gdbarch_num_cooked_regs (gdbarch
);
526 /* Convert SVR4 DWARF register number REG to the appropriate register number
530 i386_svr4_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
532 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
534 /* This implements the GCC register map that tries to be compatible
535 with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */
537 /* The SVR4 register numbering includes %eip and %eflags, and
538 numbers the floating point registers differently. */
539 if (reg
>= 0 && reg
<= 9)
541 /* General-purpose registers. */
544 else if (reg
>= 11 && reg
<= 18)
546 /* Floating-point registers. */
547 return reg
- 11 + I387_ST0_REGNUM (tdep
);
549 else if (reg
>= 21 && reg
<= 36)
551 /* The SSE and MMX registers have the same numbers as with dbx. */
552 return i386_dbx_reg_to_regnum (gdbarch
, reg
);
557 case 37: return I387_FCTRL_REGNUM (tdep
);
558 case 38: return I387_FSTAT_REGNUM (tdep
);
559 case 39: return I387_MXCSR_REGNUM (tdep
);
560 case 40: return I386_ES_REGNUM
;
561 case 41: return I386_CS_REGNUM
;
562 case 42: return I386_SS_REGNUM
;
563 case 43: return I386_DS_REGNUM
;
564 case 44: return I386_FS_REGNUM
;
565 case 45: return I386_GS_REGNUM
;
571 /* Wrapper on i386_svr4_dwarf_reg_to_regnum to return
572 num_regs + num_pseudo_regs for other debug formats. */
575 i386_svr4_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
577 int regnum
= i386_svr4_dwarf_reg_to_regnum (gdbarch
, reg
);
580 return gdbarch_num_cooked_regs (gdbarch
);
586 /* This is the variable that is set with "set disassembly-flavor", and
587 its legitimate values. */
588 static const char att_flavor
[] = "att";
589 static const char intel_flavor
[] = "intel";
590 static const char *const valid_flavors
[] =
596 static const char *disassembly_flavor
= att_flavor
;
599 /* Use the program counter to determine the contents and size of a
600 breakpoint instruction. Return a pointer to a string of bytes that
601 encode a breakpoint instruction, store the length of the string in
602 *LEN and optionally adjust *PC to point to the correct memory
603 location for inserting the breakpoint.
605 On the i386 we have a single breakpoint that fits in a single byte
606 and can be inserted anywhere.
608 This function is 64-bit safe. */
610 constexpr gdb_byte i386_break_insn
[] = { 0xcc }; /* int 3 */
612 typedef BP_MANIPULATION (i386_break_insn
) i386_breakpoint
;
615 /* Displaced instruction handling. */
617 /* Skip the legacy instruction prefixes in INSN.
618 Not all prefixes are valid for any particular insn
619 but we needn't care, the insn will fault if it's invalid.
620 The result is a pointer to the first opcode byte,
621 or NULL if we run off the end of the buffer. */
624 i386_skip_prefixes (gdb_byte
*insn
, size_t max_len
)
626 gdb_byte
*end
= insn
+ max_len
;
632 case DATA_PREFIX_OPCODE
:
633 case ADDR_PREFIX_OPCODE
:
634 case CS_PREFIX_OPCODE
:
635 case DS_PREFIX_OPCODE
:
636 case ES_PREFIX_OPCODE
:
637 case FS_PREFIX_OPCODE
:
638 case GS_PREFIX_OPCODE
:
639 case SS_PREFIX_OPCODE
:
640 case LOCK_PREFIX_OPCODE
:
641 case REPE_PREFIX_OPCODE
:
642 case REPNE_PREFIX_OPCODE
:
654 i386_absolute_jmp_p (const gdb_byte
*insn
)
656 /* jmp far (absolute address in operand). */
662 /* jump near, absolute indirect (/4). */
663 if ((insn
[1] & 0x38) == 0x20)
666 /* jump far, absolute indirect (/5). */
667 if ((insn
[1] & 0x38) == 0x28)
674 /* Return non-zero if INSN is a jump, zero otherwise. */
677 i386_jmp_p (const gdb_byte
*insn
)
679 /* jump short, relative. */
683 /* jump near, relative. */
687 return i386_absolute_jmp_p (insn
);
691 i386_absolute_call_p (const gdb_byte
*insn
)
693 /* call far, absolute. */
699 /* Call near, absolute indirect (/2). */
700 if ((insn
[1] & 0x38) == 0x10)
703 /* Call far, absolute indirect (/3). */
704 if ((insn
[1] & 0x38) == 0x18)
712 i386_ret_p (const gdb_byte
*insn
)
716 case 0xc2: /* ret near, pop N bytes. */
717 case 0xc3: /* ret near */
718 case 0xca: /* ret far, pop N bytes. */
719 case 0xcb: /* ret far */
720 case 0xcf: /* iret */
729 i386_call_p (const gdb_byte
*insn
)
731 if (i386_absolute_call_p (insn
))
734 /* call near, relative. */
741 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
742 length in bytes. Otherwise, return zero. */
745 i386_syscall_p (const gdb_byte
*insn
, int *lengthp
)
747 /* Is it 'int $0x80'? */
748 if ((insn
[0] == 0xcd && insn
[1] == 0x80)
749 /* Or is it 'sysenter'? */
750 || (insn
[0] == 0x0f && insn
[1] == 0x34)
751 /* Or is it 'syscall'? */
752 || (insn
[0] == 0x0f && insn
[1] == 0x05))
761 /* The gdbarch insn_is_call method. */
764 i386_insn_is_call (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
766 gdb_byte buf
[I386_MAX_INSN_LEN
], *insn
;
768 read_code (addr
, buf
, I386_MAX_INSN_LEN
);
769 insn
= i386_skip_prefixes (buf
, I386_MAX_INSN_LEN
);
771 return i386_call_p (insn
);
774 /* The gdbarch insn_is_ret method. */
777 i386_insn_is_ret (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
779 gdb_byte buf
[I386_MAX_INSN_LEN
], *insn
;
781 read_code (addr
, buf
, I386_MAX_INSN_LEN
);
782 insn
= i386_skip_prefixes (buf
, I386_MAX_INSN_LEN
);
784 return i386_ret_p (insn
);
787 /* The gdbarch insn_is_jump method. */
790 i386_insn_is_jump (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
792 gdb_byte buf
[I386_MAX_INSN_LEN
], *insn
;
794 read_code (addr
, buf
, I386_MAX_INSN_LEN
);
795 insn
= i386_skip_prefixes (buf
, I386_MAX_INSN_LEN
);
797 return i386_jmp_p (insn
);
800 /* Some kernels may run one past a syscall insn, so we have to cope. */
802 displaced_step_closure_up
803 i386_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
804 CORE_ADDR from
, CORE_ADDR to
,
805 struct regcache
*regs
)
807 size_t len
= gdbarch_max_insn_length (gdbarch
);
808 std::unique_ptr
<i386_displaced_step_closure
> closure
809 (new i386_displaced_step_closure (len
));
810 gdb_byte
*buf
= closure
->buf
.data ();
812 read_memory (from
, buf
, len
);
814 /* GDB may get control back after the insn after the syscall.
815 Presumably this is a kernel bug.
816 If this is a syscall, make sure there's a nop afterwards. */
821 insn
= i386_skip_prefixes (buf
, len
);
822 if (insn
!= NULL
&& i386_syscall_p (insn
, &syscall_length
))
823 insn
[syscall_length
] = NOP_OPCODE
;
826 write_memory (to
, buf
, len
);
830 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
831 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
832 displaced_step_dump_bytes (gdb_stdlog
, buf
, len
);
835 /* This is a work around for a problem with g++ 4.8. */
836 return displaced_step_closure_up (closure
.release ());
839 /* Fix up the state of registers and memory after having single-stepped
840 a displaced instruction. */
843 i386_displaced_step_fixup (struct gdbarch
*gdbarch
,
844 struct displaced_step_closure
*closure_
,
845 CORE_ADDR from
, CORE_ADDR to
,
846 struct regcache
*regs
)
848 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
850 /* The offset we applied to the instruction's address.
851 This could well be negative (when viewed as a signed 32-bit
852 value), but ULONGEST won't reflect that, so take care when
854 ULONGEST insn_offset
= to
- from
;
856 i386_displaced_step_closure
*closure
857 = (i386_displaced_step_closure
*) closure_
;
858 gdb_byte
*insn
= closure
->buf
.data ();
859 /* The start of the insn, needed in case we see some prefixes. */
860 gdb_byte
*insn_start
= insn
;
863 fprintf_unfiltered (gdb_stdlog
,
864 "displaced: fixup (%s, %s), "
865 "insn = 0x%02x 0x%02x ...\n",
866 paddress (gdbarch
, from
), paddress (gdbarch
, to
),
869 /* The list of issues to contend with here is taken from
870 resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20.
871 Yay for Free Software! */
873 /* Relocate the %eip, if necessary. */
875 /* The instruction recognizers we use assume any leading prefixes
876 have been skipped. */
878 /* This is the size of the buffer in closure. */
879 size_t max_insn_len
= gdbarch_max_insn_length (gdbarch
);
880 gdb_byte
*opcode
= i386_skip_prefixes (insn
, max_insn_len
);
881 /* If there are too many prefixes, just ignore the insn.
882 It will fault when run. */
887 /* Except in the case of absolute or indirect jump or call
888 instructions, or a return instruction, the new eip is relative to
889 the displaced instruction; make it relative. Well, signal
890 handler returns don't need relocation either, but we use the
891 value of %eip to recognize those; see below. */
892 if (! i386_absolute_jmp_p (insn
)
893 && ! i386_absolute_call_p (insn
)
894 && ! i386_ret_p (insn
))
899 regcache_cooked_read_unsigned (regs
, I386_EIP_REGNUM
, &orig_eip
);
901 /* A signal trampoline system call changes the %eip, resuming
902 execution of the main program after the signal handler has
903 returned. That makes them like 'return' instructions; we
904 shouldn't relocate %eip.
906 But most system calls don't, and we do need to relocate %eip.
908 Our heuristic for distinguishing these cases: if stepping
909 over the system call instruction left control directly after
910 the instruction, the we relocate --- control almost certainly
911 doesn't belong in the displaced copy. Otherwise, we assume
912 the instruction has put control where it belongs, and leave
913 it unrelocated. Goodness help us if there are PC-relative
915 if (i386_syscall_p (insn
, &insn_len
)
916 && orig_eip
!= to
+ (insn
- insn_start
) + insn_len
917 /* GDB can get control back after the insn after the syscall.
918 Presumably this is a kernel bug.
919 i386_displaced_step_copy_insn ensures its a nop,
920 we add one to the length for it. */
921 && orig_eip
!= to
+ (insn
- insn_start
) + insn_len
+ 1)
924 fprintf_unfiltered (gdb_stdlog
,
925 "displaced: syscall changed %%eip; "
930 ULONGEST eip
= (orig_eip
- insn_offset
) & 0xffffffffUL
;
932 /* If we just stepped over a breakpoint insn, we don't backup
933 the pc on purpose; this is to match behaviour without
936 regcache_cooked_write_unsigned (regs
, I386_EIP_REGNUM
, eip
);
939 fprintf_unfiltered (gdb_stdlog
,
941 "relocated %%eip from %s to %s\n",
942 paddress (gdbarch
, orig_eip
),
943 paddress (gdbarch
, eip
));
947 /* If the instruction was PUSHFL, then the TF bit will be set in the
948 pushed value, and should be cleared. We'll leave this for later,
949 since GDB already messes up the TF flag when stepping over a
952 /* If the instruction was a call, the return address now atop the
953 stack is the address following the copied instruction. We need
954 to make it the address following the original instruction. */
955 if (i386_call_p (insn
))
959 const ULONGEST retaddr_len
= 4;
961 regcache_cooked_read_unsigned (regs
, I386_ESP_REGNUM
, &esp
);
962 retaddr
= read_memory_unsigned_integer (esp
, retaddr_len
, byte_order
);
963 retaddr
= (retaddr
- insn_offset
) & 0xffffffffUL
;
964 write_memory_unsigned_integer (esp
, retaddr_len
, byte_order
, retaddr
);
967 fprintf_unfiltered (gdb_stdlog
,
968 "displaced: relocated return addr at %s to %s\n",
969 paddress (gdbarch
, esp
),
970 paddress (gdbarch
, retaddr
));
975 append_insns (CORE_ADDR
*to
, ULONGEST len
, const gdb_byte
*buf
)
977 target_write_memory (*to
, buf
, len
);
982 i386_relocate_instruction (struct gdbarch
*gdbarch
,
983 CORE_ADDR
*to
, CORE_ADDR oldloc
)
985 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
986 gdb_byte buf
[I386_MAX_INSN_LEN
];
987 int offset
= 0, rel32
, newrel
;
989 gdb_byte
*insn
= buf
;
991 read_memory (oldloc
, buf
, I386_MAX_INSN_LEN
);
993 insn_length
= gdb_buffered_insn_length (gdbarch
, insn
,
994 I386_MAX_INSN_LEN
, oldloc
);
996 /* Get past the prefixes. */
997 insn
= i386_skip_prefixes (insn
, I386_MAX_INSN_LEN
);
999 /* Adjust calls with 32-bit relative addresses as push/jump, with
1000 the address pushed being the location where the original call in
1001 the user program would return to. */
1002 if (insn
[0] == 0xe8)
1004 gdb_byte push_buf
[16];
1005 unsigned int ret_addr
;
1007 /* Where "ret" in the original code will return to. */
1008 ret_addr
= oldloc
+ insn_length
;
1009 push_buf
[0] = 0x68; /* pushq $... */
1010 store_unsigned_integer (&push_buf
[1], 4, byte_order
, ret_addr
);
1011 /* Push the push. */
1012 append_insns (to
, 5, push_buf
);
1014 /* Convert the relative call to a relative jump. */
1017 /* Adjust the destination offset. */
1018 rel32
= extract_signed_integer (insn
+ 1, 4, byte_order
);
1019 newrel
= (oldloc
- *to
) + rel32
;
1020 store_signed_integer (insn
+ 1, 4, byte_order
, newrel
);
1022 if (debug_displaced
)
1023 fprintf_unfiltered (gdb_stdlog
,
1024 "Adjusted insn rel32=%s at %s to"
1025 " rel32=%s at %s\n",
1026 hex_string (rel32
), paddress (gdbarch
, oldloc
),
1027 hex_string (newrel
), paddress (gdbarch
, *to
));
1029 /* Write the adjusted jump into its displaced location. */
1030 append_insns (to
, 5, insn
);
1034 /* Adjust jumps with 32-bit relative addresses. Calls are already
1036 if (insn
[0] == 0xe9)
1038 /* Adjust conditional jumps. */
1039 else if (insn
[0] == 0x0f && (insn
[1] & 0xf0) == 0x80)
1044 rel32
= extract_signed_integer (insn
+ offset
, 4, byte_order
);
1045 newrel
= (oldloc
- *to
) + rel32
;
1046 store_signed_integer (insn
+ offset
, 4, byte_order
, newrel
);
1047 if (debug_displaced
)
1048 fprintf_unfiltered (gdb_stdlog
,
1049 "Adjusted insn rel32=%s at %s to"
1050 " rel32=%s at %s\n",
1051 hex_string (rel32
), paddress (gdbarch
, oldloc
),
1052 hex_string (newrel
), paddress (gdbarch
, *to
));
1055 /* Write the adjusted instructions into their displaced
1057 append_insns (to
, insn_length
, buf
);
1061 #ifdef I386_REGNO_TO_SYMMETRY
1062 #error "The Sequent Symmetry is no longer supported."
1065 /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi
1066 and %esp "belong" to the calling function. Therefore these
1067 registers should be saved if they're going to be modified. */
1069 /* The maximum number of saved registers. This should include all
1070 registers mentioned above, and %eip. */
1071 #define I386_NUM_SAVED_REGS I386_NUM_GREGS
1073 struct i386_frame_cache
1081 /* Saved registers. */
1082 CORE_ADDR saved_regs
[I386_NUM_SAVED_REGS
];
1087 /* Stack space reserved for local variables. */
1091 /* Allocate and initialize a frame cache. */
1093 static struct i386_frame_cache
*
1094 i386_alloc_frame_cache (void)
1096 struct i386_frame_cache
*cache
;
1099 cache
= FRAME_OBSTACK_ZALLOC (struct i386_frame_cache
);
1104 cache
->sp_offset
= -4;
1107 /* Saved registers. We initialize these to -1 since zero is a valid
1108 offset (that's where %ebp is supposed to be stored). */
1109 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
1110 cache
->saved_regs
[i
] = -1;
1111 cache
->saved_sp
= 0;
1112 cache
->saved_sp_reg
= -1;
1113 cache
->pc_in_eax
= 0;
1115 /* Frameless until proven otherwise. */
1121 /* If the instruction at PC is a jump, return the address of its
1122 target. Otherwise, return PC. */
1125 i386_follow_jump (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1127 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1132 if (target_read_code (pc
, &op
, 1))
1139 op
= read_code_unsigned_integer (pc
+ 1, 1, byte_order
);
1145 /* Relative jump: if data16 == 0, disp32, else disp16. */
1148 delta
= read_memory_integer (pc
+ 2, 2, byte_order
);
1150 /* Include the size of the jmp instruction (including the
1156 delta
= read_memory_integer (pc
+ 1, 4, byte_order
);
1158 /* Include the size of the jmp instruction. */
1163 /* Relative jump, disp8 (ignore data16). */
1164 delta
= read_memory_integer (pc
+ data16
+ 1, 1, byte_order
);
1166 delta
+= data16
+ 2;
1173 /* Check whether PC points at a prologue for a function returning a
1174 structure or union. If so, it updates CACHE and returns the
1175 address of the first instruction after the code sequence that
1176 removes the "hidden" argument from the stack or CURRENT_PC,
1177 whichever is smaller. Otherwise, return PC. */
1180 i386_analyze_struct_return (CORE_ADDR pc
, CORE_ADDR current_pc
,
1181 struct i386_frame_cache
*cache
)
1183 /* Functions that return a structure or union start with:
1186 xchgl %eax, (%esp) 0x87 0x04 0x24
1187 or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00
1189 (the System V compiler puts out the second `xchg' instruction,
1190 and the assembler doesn't try to optimize it, so the 'sib' form
1191 gets generated). This sequence is used to get the address of the
1192 return buffer for a function that returns a structure. */
1193 static gdb_byte proto1
[3] = { 0x87, 0x04, 0x24 };
1194 static gdb_byte proto2
[4] = { 0x87, 0x44, 0x24, 0x00 };
1198 if (current_pc
<= pc
)
1201 if (target_read_code (pc
, &op
, 1))
1204 if (op
!= 0x58) /* popl %eax */
1207 if (target_read_code (pc
+ 1, buf
, 4))
1210 if (memcmp (buf
, proto1
, 3) != 0 && memcmp (buf
, proto2
, 4) != 0)
1213 if (current_pc
== pc
)
1215 cache
->sp_offset
+= 4;
1219 if (current_pc
== pc
+ 1)
1221 cache
->pc_in_eax
= 1;
1225 if (buf
[1] == proto1
[1])
1232 i386_skip_probe (CORE_ADDR pc
)
1234 /* A function may start with
1248 if (target_read_code (pc
, &op
, 1))
1251 if (op
== 0x68 || op
== 0x6a)
1255 /* Skip past the `pushl' instruction; it has either a one-byte or a
1256 four-byte operand, depending on the opcode. */
1262 /* Read the following 8 bytes, which should be `call _probe' (6
1263 bytes) followed by `addl $4,%esp' (2 bytes). */
1264 read_memory (pc
+ delta
, buf
, sizeof (buf
));
1265 if (buf
[0] == 0xe8 && buf
[6] == 0xc4 && buf
[7] == 0x4)
1266 pc
+= delta
+ sizeof (buf
);
1272 /* GCC 4.1 and later, can put code in the prologue to realign the
1273 stack pointer. Check whether PC points to such code, and update
1274 CACHE accordingly. Return the first instruction after the code
1275 sequence or CURRENT_PC, whichever is smaller. If we don't
1276 recognize the code, return PC. */
1279 i386_analyze_stack_align (CORE_ADDR pc
, CORE_ADDR current_pc
,
1280 struct i386_frame_cache
*cache
)
1282 /* There are 2 code sequences to re-align stack before the frame
1285 1. Use a caller-saved saved register:
1291 2. Use a callee-saved saved register:
1298 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
1300 0x83 0xe4 0xf0 andl $-16, %esp
1301 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
1306 int offset
, offset_and
;
1307 static int regnums
[8] = {
1308 I386_EAX_REGNUM
, /* %eax */
1309 I386_ECX_REGNUM
, /* %ecx */
1310 I386_EDX_REGNUM
, /* %edx */
1311 I386_EBX_REGNUM
, /* %ebx */
1312 I386_ESP_REGNUM
, /* %esp */
1313 I386_EBP_REGNUM
, /* %ebp */
1314 I386_ESI_REGNUM
, /* %esi */
1315 I386_EDI_REGNUM
/* %edi */
1318 if (target_read_code (pc
, buf
, sizeof buf
))
1321 /* Check caller-saved saved register. The first instruction has
1322 to be "leal 4(%esp), %reg". */
1323 if (buf
[0] == 0x8d && buf
[2] == 0x24 && buf
[3] == 0x4)
1325 /* MOD must be binary 10 and R/M must be binary 100. */
1326 if ((buf
[1] & 0xc7) != 0x44)
1329 /* REG has register number. */
1330 reg
= (buf
[1] >> 3) & 7;
1335 /* Check callee-saved saved register. The first instruction
1336 has to be "pushl %reg". */
1337 if ((buf
[0] & 0xf8) != 0x50)
1343 /* The next instruction has to be "leal 8(%esp), %reg". */
1344 if (buf
[1] != 0x8d || buf
[3] != 0x24 || buf
[4] != 0x8)
1347 /* MOD must be binary 10 and R/M must be binary 100. */
1348 if ((buf
[2] & 0xc7) != 0x44)
1351 /* REG has register number. Registers in pushl and leal have to
1353 if (reg
!= ((buf
[2] >> 3) & 7))
1359 /* Rigister can't be %esp nor %ebp. */
1360 if (reg
== 4 || reg
== 5)
1363 /* The next instruction has to be "andl $-XXX, %esp". */
1364 if (buf
[offset
+ 1] != 0xe4
1365 || (buf
[offset
] != 0x81 && buf
[offset
] != 0x83))
1368 offset_and
= offset
;
1369 offset
+= buf
[offset
] == 0x81 ? 6 : 3;
1371 /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is
1372 0xfc. REG must be binary 110 and MOD must be binary 01. */
1373 if (buf
[offset
] != 0xff
1374 || buf
[offset
+ 2] != 0xfc
1375 || (buf
[offset
+ 1] & 0xf8) != 0x70)
1378 /* R/M has register. Registers in leal and pushl have to be the
1380 if (reg
!= (buf
[offset
+ 1] & 7))
1383 if (current_pc
> pc
+ offset_and
)
1384 cache
->saved_sp_reg
= regnums
[reg
];
1386 return std::min (pc
+ offset
+ 3, current_pc
);
1389 /* Maximum instruction length we need to handle. */
1390 #define I386_MAX_MATCHED_INSN_LEN 6
1392 /* Instruction description. */
1396 gdb_byte insn
[I386_MAX_MATCHED_INSN_LEN
];
1397 gdb_byte mask
[I386_MAX_MATCHED_INSN_LEN
];
1400 /* Return whether instruction at PC matches PATTERN. */
1403 i386_match_pattern (CORE_ADDR pc
, struct i386_insn pattern
)
1407 if (target_read_code (pc
, &op
, 1))
1410 if ((op
& pattern
.mask
[0]) == pattern
.insn
[0])
1412 gdb_byte buf
[I386_MAX_MATCHED_INSN_LEN
- 1];
1413 int insn_matched
= 1;
1416 gdb_assert (pattern
.len
> 1);
1417 gdb_assert (pattern
.len
<= I386_MAX_MATCHED_INSN_LEN
);
1419 if (target_read_code (pc
+ 1, buf
, pattern
.len
- 1))
1422 for (i
= 1; i
< pattern
.len
; i
++)
1424 if ((buf
[i
- 1] & pattern
.mask
[i
]) != pattern
.insn
[i
])
1427 return insn_matched
;
1432 /* Search for the instruction at PC in the list INSN_PATTERNS. Return
1433 the first instruction description that matches. Otherwise, return
1436 static struct i386_insn
*
1437 i386_match_insn (CORE_ADDR pc
, struct i386_insn
*insn_patterns
)
1439 struct i386_insn
*pattern
;
1441 for (pattern
= insn_patterns
; pattern
->len
> 0; pattern
++)
1443 if (i386_match_pattern (pc
, *pattern
))
1450 /* Return whether PC points inside a sequence of instructions that
1451 matches INSN_PATTERNS. */
1454 i386_match_insn_block (CORE_ADDR pc
, struct i386_insn
*insn_patterns
)
1456 CORE_ADDR current_pc
;
1458 struct i386_insn
*insn
;
1460 insn
= i386_match_insn (pc
, insn_patterns
);
1465 ix
= insn
- insn_patterns
;
1466 for (i
= ix
- 1; i
>= 0; i
--)
1468 current_pc
-= insn_patterns
[i
].len
;
1470 if (!i386_match_pattern (current_pc
, insn_patterns
[i
]))
1474 current_pc
= pc
+ insn
->len
;
1475 for (insn
= insn_patterns
+ ix
+ 1; insn
->len
> 0; insn
++)
1477 if (!i386_match_pattern (current_pc
, *insn
))
1480 current_pc
+= insn
->len
;
1486 /* Some special instructions that might be migrated by GCC into the
1487 part of the prologue that sets up the new stack frame. Because the
1488 stack frame hasn't been setup yet, no registers have been saved
1489 yet, and only the scratch registers %eax, %ecx and %edx can be
1492 struct i386_insn i386_frame_setup_skip_insns
[] =
1494 /* Check for `movb imm8, r' and `movl imm32, r'.
1496 ??? Should we handle 16-bit operand-sizes here? */
1498 /* `movb imm8, %al' and `movb imm8, %ah' */
1499 /* `movb imm8, %cl' and `movb imm8, %ch' */
1500 { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } },
1501 /* `movb imm8, %dl' and `movb imm8, %dh' */
1502 { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } },
1503 /* `movl imm32, %eax' and `movl imm32, %ecx' */
1504 { 5, { 0xb8 }, { 0xfe } },
1505 /* `movl imm32, %edx' */
1506 { 5, { 0xba }, { 0xff } },
1508 /* Check for `mov imm32, r32'. Note that there is an alternative
1509 encoding for `mov m32, %eax'.
1511 ??? Should we handle SIB addressing here?
1512 ??? Should we handle 16-bit operand-sizes here? */
1514 /* `movl m32, %eax' */
1515 { 5, { 0xa1 }, { 0xff } },
1516 /* `movl m32, %eax' and `mov; m32, %ecx' */
1517 { 6, { 0x89, 0x05 }, {0xff, 0xf7 } },
1518 /* `movl m32, %edx' */
1519 { 6, { 0x89, 0x15 }, {0xff, 0xff } },
1521 /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'.
1522 Because of the symmetry, there are actually two ways to encode
1523 these instructions; opcode bytes 0x29 and 0x2b for `subl' and
1524 opcode bytes 0x31 and 0x33 for `xorl'. */
1526 /* `subl %eax, %eax' */
1527 { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } },
1528 /* `subl %ecx, %ecx' */
1529 { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } },
1530 /* `subl %edx, %edx' */
1531 { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } },
1532 /* `xorl %eax, %eax' */
1533 { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } },
1534 /* `xorl %ecx, %ecx' */
1535 { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } },
1536 /* `xorl %edx, %edx' */
1537 { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } },
1541 /* Check whether PC points to an endbr32 instruction. */
1543 i386_skip_endbr (CORE_ADDR pc
)
1545 static const gdb_byte endbr32
[] = { 0xf3, 0x0f, 0x1e, 0xfb };
1547 gdb_byte buf
[sizeof (endbr32
)];
1549 /* Stop there if we can't read the code */
1550 if (target_read_code (pc
, buf
, sizeof (endbr32
)))
1553 /* If the instruction isn't an endbr32, stop */
1554 if (memcmp (buf
, endbr32
, sizeof (endbr32
)) != 0)
1557 return pc
+ sizeof (endbr32
);
1560 /* Check whether PC points to a no-op instruction. */
1562 i386_skip_noop (CORE_ADDR pc
)
1567 if (target_read_code (pc
, &op
, 1))
1573 /* Ignore `nop' instruction. */
1577 if (target_read_code (pc
, &op
, 1))
1581 /* Ignore no-op instruction `mov %edi, %edi'.
1582 Microsoft system dlls often start with
1583 a `mov %edi,%edi' instruction.
1584 The 5 bytes before the function start are
1585 filled with `nop' instructions.
1586 This pattern can be used for hot-patching:
1587 The `mov %edi, %edi' instruction can be replaced by a
1588 near jump to the location of the 5 `nop' instructions
1589 which can be replaced by a 32-bit jump to anywhere
1590 in the 32-bit address space. */
1592 else if (op
== 0x8b)
1594 if (target_read_code (pc
+ 1, &op
, 1))
1600 if (target_read_code (pc
, &op
, 1))
1610 /* Check whether PC points at a code that sets up a new stack frame.
1611 If so, it updates CACHE and returns the address of the first
1612 instruction after the sequence that sets up the frame or LIMIT,
1613 whichever is smaller. If we don't recognize the code, return PC. */
1616 i386_analyze_frame_setup (struct gdbarch
*gdbarch
,
1617 CORE_ADDR pc
, CORE_ADDR limit
,
1618 struct i386_frame_cache
*cache
)
1620 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1621 struct i386_insn
*insn
;
1628 if (target_read_code (pc
, &op
, 1))
1631 if (op
== 0x55) /* pushl %ebp */
1633 /* Take into account that we've executed the `pushl %ebp' that
1634 starts this instruction sequence. */
1635 cache
->saved_regs
[I386_EBP_REGNUM
] = 0;
1636 cache
->sp_offset
+= 4;
1639 /* If that's all, return now. */
1643 /* Check for some special instructions that might be migrated by
1644 GCC into the prologue and skip them. At this point in the
1645 prologue, code should only touch the scratch registers %eax,
1646 %ecx and %edx, so while the number of possibilities is sheer,
1649 Make sure we only skip these instructions if we later see the
1650 `movl %esp, %ebp' that actually sets up the frame. */
1651 while (pc
+ skip
< limit
)
1653 insn
= i386_match_insn (pc
+ skip
, i386_frame_setup_skip_insns
);
1660 /* If that's all, return now. */
1661 if (limit
<= pc
+ skip
)
1664 if (target_read_code (pc
+ skip
, &op
, 1))
1667 /* The i386 prologue looks like
1673 and a different prologue can be generated for atom.
1677 lea -0x10(%esp),%esp
1679 We handle both of them here. */
1683 /* Check for `movl %esp, %ebp' -- can be written in two ways. */
1685 if (read_code_unsigned_integer (pc
+ skip
+ 1, 1, byte_order
)
1691 if (read_code_unsigned_integer (pc
+ skip
+ 1, 1, byte_order
)
1696 case 0x8d: /* Check for 'lea (%ebp), %ebp'. */
1697 if (read_code_unsigned_integer (pc
+ skip
+ 1, 2, byte_order
)
1706 /* OK, we actually have a frame. We just don't know how large
1707 it is yet. Set its size to zero. We'll adjust it if
1708 necessary. We also now commit to skipping the special
1709 instructions mentioned before. */
1712 /* If that's all, return now. */
1716 /* Check for stack adjustment
1722 NOTE: You can't subtract a 16-bit immediate from a 32-bit
1723 reg, so we don't have to worry about a data16 prefix. */
1724 if (target_read_code (pc
, &op
, 1))
1728 /* `subl' with 8-bit immediate. */
1729 if (read_code_unsigned_integer (pc
+ 1, 1, byte_order
) != 0xec)
1730 /* Some instruction starting with 0x83 other than `subl'. */
1733 /* `subl' with signed 8-bit immediate (though it wouldn't
1734 make sense to be negative). */
1735 cache
->locals
= read_code_integer (pc
+ 2, 1, byte_order
);
1738 else if (op
== 0x81)
1740 /* Maybe it is `subl' with a 32-bit immediate. */
1741 if (read_code_unsigned_integer (pc
+ 1, 1, byte_order
) != 0xec)
1742 /* Some instruction starting with 0x81 other than `subl'. */
1745 /* It is `subl' with a 32-bit immediate. */
1746 cache
->locals
= read_code_integer (pc
+ 2, 4, byte_order
);
1749 else if (op
== 0x8d)
1751 /* The ModR/M byte is 0x64. */
1752 if (read_code_unsigned_integer (pc
+ 1, 1, byte_order
) != 0x64)
1754 /* 'lea' with 8-bit displacement. */
1755 cache
->locals
= -1 * read_code_integer (pc
+ 3, 1, byte_order
);
1760 /* Some instruction other than `subl' nor 'lea'. */
1764 else if (op
== 0xc8) /* enter */
1766 cache
->locals
= read_code_unsigned_integer (pc
+ 1, 2, byte_order
);
1773 /* Check whether PC points at code that saves registers on the stack.
1774 If so, it updates CACHE and returns the address of the first
1775 instruction after the register saves or CURRENT_PC, whichever is
1776 smaller. Otherwise, return PC. */
1779 i386_analyze_register_saves (CORE_ADDR pc
, CORE_ADDR current_pc
,
1780 struct i386_frame_cache
*cache
)
1782 CORE_ADDR offset
= 0;
1786 if (cache
->locals
> 0)
1787 offset
-= cache
->locals
;
1788 for (i
= 0; i
< 8 && pc
< current_pc
; i
++)
1790 if (target_read_code (pc
, &op
, 1))
1792 if (op
< 0x50 || op
> 0x57)
1796 cache
->saved_regs
[op
- 0x50] = offset
;
1797 cache
->sp_offset
+= 4;
1804 /* Do a full analysis of the prologue at PC and update CACHE
1805 accordingly. Bail out early if CURRENT_PC is reached. Return the
1806 address where the analysis stopped.
1808 We handle these cases:
1810 The startup sequence can be at the start of the function, or the
1811 function can start with a branch to startup code at the end.
1813 %ebp can be set up with either the 'enter' instruction, or "pushl
1814 %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was
1815 once used in the System V compiler).
1817 Local space is allocated just below the saved %ebp by either the
1818 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a
1819 16-bit unsigned argument for space to allocate, and the 'addl'
1820 instruction could have either a signed byte, or 32-bit immediate.
1822 Next, the registers used by this function are pushed. With the
1823 System V compiler they will always be in the order: %edi, %esi,
1824 %ebx (and sometimes a harmless bug causes it to also save but not
1825 restore %eax); however, the code below is willing to see the pushes
1826 in any order, and will handle up to 8 of them.
1828 If the setup sequence is at the end of the function, then the next
1829 instruction will be a branch back to the start. */
1832 i386_analyze_prologue (struct gdbarch
*gdbarch
,
1833 CORE_ADDR pc
, CORE_ADDR current_pc
,
1834 struct i386_frame_cache
*cache
)
1836 pc
= i386_skip_endbr (pc
);
1837 pc
= i386_skip_noop (pc
);
1838 pc
= i386_follow_jump (gdbarch
, pc
);
1839 pc
= i386_analyze_struct_return (pc
, current_pc
, cache
);
1840 pc
= i386_skip_probe (pc
);
1841 pc
= i386_analyze_stack_align (pc
, current_pc
, cache
);
1842 pc
= i386_analyze_frame_setup (gdbarch
, pc
, current_pc
, cache
);
1843 return i386_analyze_register_saves (pc
, current_pc
, cache
);
1846 /* Return PC of first real instruction. */
1849 i386_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
1851 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1853 static gdb_byte pic_pat
[6] =
1855 0xe8, 0, 0, 0, 0, /* call 0x0 */
1856 0x5b, /* popl %ebx */
1858 struct i386_frame_cache cache
;
1862 CORE_ADDR func_addr
;
1864 if (find_pc_partial_function (start_pc
, NULL
, &func_addr
, NULL
))
1866 CORE_ADDR post_prologue_pc
1867 = skip_prologue_using_sal (gdbarch
, func_addr
);
1868 struct compunit_symtab
*cust
= find_pc_compunit_symtab (func_addr
);
1870 /* LLVM backend (Clang/Flang) always emits a line note before the
1871 prologue and another one after. We trust clang to emit usable
1873 if (post_prologue_pc
1875 && COMPUNIT_PRODUCER (cust
) != NULL
1876 && producer_is_llvm (COMPUNIT_PRODUCER (cust
))))
1877 return std::max (start_pc
, post_prologue_pc
);
1881 pc
= i386_analyze_prologue (gdbarch
, start_pc
, 0xffffffff, &cache
);
1882 if (cache
.locals
< 0)
1885 /* Found valid frame setup. */
1887 /* The native cc on SVR4 in -K PIC mode inserts the following code
1888 to get the address of the global offset table (GOT) into register
1893 movl %ebx,x(%ebp) (optional)
1896 This code is with the rest of the prologue (at the end of the
1897 function), so we have to skip it to get to the first real
1898 instruction at the start of the function. */
1900 for (i
= 0; i
< 6; i
++)
1902 if (target_read_code (pc
+ i
, &op
, 1))
1905 if (pic_pat
[i
] != op
)
1912 if (target_read_code (pc
+ delta
, &op
, 1))
1915 if (op
== 0x89) /* movl %ebx, x(%ebp) */
1917 op
= read_code_unsigned_integer (pc
+ delta
+ 1, 1, byte_order
);
1919 if (op
== 0x5d) /* One byte offset from %ebp. */
1921 else if (op
== 0x9d) /* Four byte offset from %ebp. */
1923 else /* Unexpected instruction. */
1926 if (target_read_code (pc
+ delta
, &op
, 1))
1931 if (delta
> 0 && op
== 0x81
1932 && read_code_unsigned_integer (pc
+ delta
+ 1, 1, byte_order
)
1939 /* If the function starts with a branch (to startup code at the end)
1940 the last instruction should bring us back to the first
1941 instruction of the real code. */
1942 if (i386_follow_jump (gdbarch
, start_pc
) != start_pc
)
1943 pc
= i386_follow_jump (gdbarch
, pc
);
1948 /* Check that the code pointed to by PC corresponds to a call to
1949 __main, skip it if so. Return PC otherwise. */
1952 i386_skip_main_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1954 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1957 if (target_read_code (pc
, &op
, 1))
1963 if (target_read_code (pc
+ 1, buf
, sizeof buf
) == 0)
1965 /* Make sure address is computed correctly as a 32bit
1966 integer even if CORE_ADDR is 64 bit wide. */
1967 struct bound_minimal_symbol s
;
1968 CORE_ADDR call_dest
;
1970 call_dest
= pc
+ 5 + extract_signed_integer (buf
, 4, byte_order
);
1971 call_dest
= call_dest
& 0xffffffffU
;
1972 s
= lookup_minimal_symbol_by_pc (call_dest
);
1973 if (s
.minsym
!= NULL
1974 && s
.minsym
->linkage_name () != NULL
1975 && strcmp (s
.minsym
->linkage_name (), "__main") == 0)
1983 /* This function is 64-bit safe. */
1986 i386_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1990 frame_unwind_register (next_frame
, gdbarch_pc_regnum (gdbarch
), buf
);
1991 return extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
1995 /* Normal frames. */
1998 i386_frame_cache_1 (struct frame_info
*this_frame
,
1999 struct i386_frame_cache
*cache
)
2001 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2002 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2006 cache
->pc
= get_frame_func (this_frame
);
2008 /* In principle, for normal frames, %ebp holds the frame pointer,
2009 which holds the base address for the current stack frame.
2010 However, for functions that don't need it, the frame pointer is
2011 optional. For these "frameless" functions the frame pointer is
2012 actually the frame pointer of the calling frame. Signal
2013 trampolines are just a special case of a "frameless" function.
2014 They (usually) share their frame pointer with the frame that was
2015 in progress when the signal occurred. */
2017 get_frame_register (this_frame
, I386_EBP_REGNUM
, buf
);
2018 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
);
2019 if (cache
->base
== 0)
2025 /* For normal frames, %eip is stored at 4(%ebp). */
2026 cache
->saved_regs
[I386_EIP_REGNUM
] = 4;
2029 i386_analyze_prologue (gdbarch
, cache
->pc
, get_frame_pc (this_frame
),
2032 if (cache
->locals
< 0)
2034 /* We didn't find a valid frame, which means that CACHE->base
2035 currently holds the frame pointer for our calling frame. If
2036 we're at the start of a function, or somewhere half-way its
2037 prologue, the function's frame probably hasn't been fully
2038 setup yet. Try to reconstruct the base address for the stack
2039 frame by looking at the stack pointer. For truly "frameless"
2040 functions this might work too. */
2042 if (cache
->saved_sp_reg
!= -1)
2044 /* Saved stack pointer has been saved. */
2045 get_frame_register (this_frame
, cache
->saved_sp_reg
, buf
);
2046 cache
->saved_sp
= extract_unsigned_integer (buf
, 4, byte_order
);
2048 /* We're halfway aligning the stack. */
2049 cache
->base
= ((cache
->saved_sp
- 4) & 0xfffffff0) - 4;
2050 cache
->saved_regs
[I386_EIP_REGNUM
] = cache
->saved_sp
- 4;
2052 /* This will be added back below. */
2053 cache
->saved_regs
[I386_EIP_REGNUM
] -= cache
->base
;
2055 else if (cache
->pc
!= 0
2056 || target_read_code (get_frame_pc (this_frame
), buf
, 1))
2058 /* We're in a known function, but did not find a frame
2059 setup. Assume that the function does not use %ebp.
2060 Alternatively, we may have jumped to an invalid
2061 address; in that case there is definitely no new
2063 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
2064 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
)
2068 /* We're in an unknown function. We could not find the start
2069 of the function to analyze the prologue; our best option is
2070 to assume a typical frame layout with the caller's %ebp
2072 cache
->saved_regs
[I386_EBP_REGNUM
] = 0;
2075 if (cache
->saved_sp_reg
!= -1)
2077 /* Saved stack pointer has been saved (but the SAVED_SP_REG
2078 register may be unavailable). */
2079 if (cache
->saved_sp
== 0
2080 && deprecated_frame_register_read (this_frame
,
2081 cache
->saved_sp_reg
, buf
))
2082 cache
->saved_sp
= extract_unsigned_integer (buf
, 4, byte_order
);
2084 /* Now that we have the base address for the stack frame we can
2085 calculate the value of %esp in the calling frame. */
2086 else if (cache
->saved_sp
== 0)
2087 cache
->saved_sp
= cache
->base
+ 8;
2089 /* Adjust all the saved registers such that they contain addresses
2090 instead of offsets. */
2091 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
2092 if (cache
->saved_regs
[i
] != -1)
2093 cache
->saved_regs
[i
] += cache
->base
;
2098 static struct i386_frame_cache
*
2099 i386_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2101 struct i386_frame_cache
*cache
;
2104 return (struct i386_frame_cache
*) *this_cache
;
2106 cache
= i386_alloc_frame_cache ();
2107 *this_cache
= cache
;
2111 i386_frame_cache_1 (this_frame
, cache
);
2113 catch (const gdb_exception_error
&ex
)
2115 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
2123 i386_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2124 struct frame_id
*this_id
)
2126 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
2129 (*this_id
) = frame_id_build_unavailable_stack (cache
->pc
);
2130 else if (cache
->base
== 0)
2132 /* This marks the outermost frame. */
2136 /* See the end of i386_push_dummy_call. */
2137 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
2141 static enum unwind_stop_reason
2142 i386_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2145 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
2148 return UNWIND_UNAVAILABLE
;
2150 /* This marks the outermost frame. */
2151 if (cache
->base
== 0)
2152 return UNWIND_OUTERMOST
;
2154 return UNWIND_NO_REASON
;
2157 static struct value
*
2158 i386_frame_prev_register (struct frame_info
*this_frame
, void **this_cache
,
2161 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
2163 gdb_assert (regnum
>= 0);
2165 /* The System V ABI says that:
2167 "The flags register contains the system flags, such as the
2168 direction flag and the carry flag. The direction flag must be
2169 set to the forward (that is, zero) direction before entry and
2170 upon exit from a function. Other user flags have no specified
2171 role in the standard calling sequence and are not preserved."
2173 To guarantee the "upon exit" part of that statement we fake a
2174 saved flags register that has its direction flag cleared.
2176 Note that GCC doesn't seem to rely on the fact that the direction
2177 flag is cleared after a function return; it always explicitly
2178 clears the flag before operations where it matters.
2180 FIXME: kettenis/20030316: I'm not quite sure whether this is the
2181 right thing to do. The way we fake the flags register here makes
2182 it impossible to change it. */
2184 if (regnum
== I386_EFLAGS_REGNUM
)
2188 val
= get_frame_register_unsigned (this_frame
, regnum
);
2190 return frame_unwind_got_constant (this_frame
, regnum
, val
);
2193 if (regnum
== I386_EIP_REGNUM
&& cache
->pc_in_eax
)
2194 return frame_unwind_got_register (this_frame
, regnum
, I386_EAX_REGNUM
);
2196 if (regnum
== I386_ESP_REGNUM
2197 && (cache
->saved_sp
!= 0 || cache
->saved_sp_reg
!= -1))
2199 /* If the SP has been saved, but we don't know where, then this
2200 means that SAVED_SP_REG register was found unavailable back
2201 when we built the cache. */
2202 if (cache
->saved_sp
== 0)
2203 return frame_unwind_got_register (this_frame
, regnum
,
2204 cache
->saved_sp_reg
);
2206 return frame_unwind_got_constant (this_frame
, regnum
,
2210 if (regnum
< I386_NUM_SAVED_REGS
&& cache
->saved_regs
[regnum
] != -1)
2211 return frame_unwind_got_memory (this_frame
, regnum
,
2212 cache
->saved_regs
[regnum
]);
2214 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
2217 static const struct frame_unwind i386_frame_unwind
=
2220 i386_frame_unwind_stop_reason
,
2222 i386_frame_prev_register
,
2224 default_frame_sniffer
2227 /* Normal frames, but in a function epilogue. */
2229 /* Implement the stack_frame_destroyed_p gdbarch method.
2231 The epilogue is defined here as the 'ret' instruction, which will
2232 follow any instruction such as 'leave' or 'pop %ebp' that destroys
2233 the function's stack frame. */
2236 i386_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2239 struct compunit_symtab
*cust
;
2241 cust
= find_pc_compunit_symtab (pc
);
2242 if (cust
!= NULL
&& COMPUNIT_EPILOGUE_UNWIND_VALID (cust
))
2245 if (target_read_memory (pc
, &insn
, 1))
2246 return 0; /* Can't read memory at pc. */
2248 if (insn
!= 0xc3) /* 'ret' instruction. */
2255 i386_epilogue_frame_sniffer (const struct frame_unwind
*self
,
2256 struct frame_info
*this_frame
,
2257 void **this_prologue_cache
)
2259 if (frame_relative_level (this_frame
) == 0)
2260 return i386_stack_frame_destroyed_p (get_frame_arch (this_frame
),
2261 get_frame_pc (this_frame
));
2266 static struct i386_frame_cache
*
2267 i386_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2269 struct i386_frame_cache
*cache
;
2273 return (struct i386_frame_cache
*) *this_cache
;
2275 cache
= i386_alloc_frame_cache ();
2276 *this_cache
= cache
;
2280 cache
->pc
= get_frame_func (this_frame
);
2282 /* At this point the stack looks as if we just entered the
2283 function, with the return address at the top of the
2285 sp
= get_frame_register_unsigned (this_frame
, I386_ESP_REGNUM
);
2286 cache
->base
= sp
+ cache
->sp_offset
;
2287 cache
->saved_sp
= cache
->base
+ 8;
2288 cache
->saved_regs
[I386_EIP_REGNUM
] = cache
->base
+ 4;
2292 catch (const gdb_exception_error
&ex
)
2294 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
2301 static enum unwind_stop_reason
2302 i386_epilogue_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2305 struct i386_frame_cache
*cache
=
2306 i386_epilogue_frame_cache (this_frame
, this_cache
);
2309 return UNWIND_UNAVAILABLE
;
2311 return UNWIND_NO_REASON
;
2315 i386_epilogue_frame_this_id (struct frame_info
*this_frame
,
2317 struct frame_id
*this_id
)
2319 struct i386_frame_cache
*cache
=
2320 i386_epilogue_frame_cache (this_frame
, this_cache
);
2323 (*this_id
) = frame_id_build_unavailable_stack (cache
->pc
);
2325 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
2328 static struct value
*
2329 i386_epilogue_frame_prev_register (struct frame_info
*this_frame
,
2330 void **this_cache
, int regnum
)
2332 /* Make sure we've initialized the cache. */
2333 i386_epilogue_frame_cache (this_frame
, this_cache
);
2335 return i386_frame_prev_register (this_frame
, this_cache
, regnum
);
2338 static const struct frame_unwind i386_epilogue_frame_unwind
=
2341 i386_epilogue_frame_unwind_stop_reason
,
2342 i386_epilogue_frame_this_id
,
2343 i386_epilogue_frame_prev_register
,
2345 i386_epilogue_frame_sniffer
2349 /* Stack-based trampolines. */
2351 /* These trampolines are used on cross x86 targets, when taking the
2352 address of a nested function. When executing these trampolines,
2353 no stack frame is set up, so we are in a similar situation as in
2354 epilogues and i386_epilogue_frame_this_id can be re-used. */
2356 /* Static chain passed in register. */
2358 struct i386_insn i386_tramp_chain_in_reg_insns
[] =
2360 /* `movl imm32, %eax' and `movl imm32, %ecx' */
2361 { 5, { 0xb8 }, { 0xfe } },
2364 { 5, { 0xe9 }, { 0xff } },
2369 /* Static chain passed on stack (when regparm=3). */
2371 struct i386_insn i386_tramp_chain_on_stack_insns
[] =
2374 { 5, { 0x68 }, { 0xff } },
2377 { 5, { 0xe9 }, { 0xff } },
2382 /* Return whether PC points inside a stack trampoline. */
2385 i386_in_stack_tramp_p (CORE_ADDR pc
)
2390 /* A stack trampoline is detected if no name is associated
2391 to the current pc and if it points inside a trampoline
2394 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
2398 if (target_read_memory (pc
, &insn
, 1))
2401 if (!i386_match_insn_block (pc
, i386_tramp_chain_in_reg_insns
)
2402 && !i386_match_insn_block (pc
, i386_tramp_chain_on_stack_insns
))
2409 i386_stack_tramp_frame_sniffer (const struct frame_unwind
*self
,
2410 struct frame_info
*this_frame
,
2413 if (frame_relative_level (this_frame
) == 0)
2414 return i386_in_stack_tramp_p (get_frame_pc (this_frame
));
2419 static const struct frame_unwind i386_stack_tramp_frame_unwind
=
2422 i386_epilogue_frame_unwind_stop_reason
,
2423 i386_epilogue_frame_this_id
,
2424 i386_epilogue_frame_prev_register
,
2426 i386_stack_tramp_frame_sniffer
2429 /* Generate a bytecode expression to get the value of the saved PC. */
2432 i386_gen_return_address (struct gdbarch
*gdbarch
,
2433 struct agent_expr
*ax
, struct axs_value
*value
,
2436 /* The following sequence assumes the traditional use of the base
2438 ax_reg (ax
, I386_EBP_REGNUM
);
2440 ax_simple (ax
, aop_add
);
2441 value
->type
= register_type (gdbarch
, I386_EIP_REGNUM
);
2442 value
->kind
= axs_lvalue_memory
;
2446 /* Signal trampolines. */
2448 static struct i386_frame_cache
*
2449 i386_sigtramp_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2451 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2452 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2453 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2454 struct i386_frame_cache
*cache
;
2459 return (struct i386_frame_cache
*) *this_cache
;
2461 cache
= i386_alloc_frame_cache ();
2465 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
2466 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
) - 4;
2468 addr
= tdep
->sigcontext_addr (this_frame
);
2469 if (tdep
->sc_reg_offset
)
2473 gdb_assert (tdep
->sc_num_regs
<= I386_NUM_SAVED_REGS
);
2475 for (i
= 0; i
< tdep
->sc_num_regs
; i
++)
2476 if (tdep
->sc_reg_offset
[i
] != -1)
2477 cache
->saved_regs
[i
] = addr
+ tdep
->sc_reg_offset
[i
];
2481 cache
->saved_regs
[I386_EIP_REGNUM
] = addr
+ tdep
->sc_pc_offset
;
2482 cache
->saved_regs
[I386_ESP_REGNUM
] = addr
+ tdep
->sc_sp_offset
;
2487 catch (const gdb_exception_error
&ex
)
2489 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
2493 *this_cache
= cache
;
2497 static enum unwind_stop_reason
2498 i386_sigtramp_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2501 struct i386_frame_cache
*cache
=
2502 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2505 return UNWIND_UNAVAILABLE
;
2507 return UNWIND_NO_REASON
;
2511 i386_sigtramp_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2512 struct frame_id
*this_id
)
2514 struct i386_frame_cache
*cache
=
2515 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2518 (*this_id
) = frame_id_build_unavailable_stack (get_frame_pc (this_frame
));
2521 /* See the end of i386_push_dummy_call. */
2522 (*this_id
) = frame_id_build (cache
->base
+ 8, get_frame_pc (this_frame
));
2526 static struct value
*
2527 i386_sigtramp_frame_prev_register (struct frame_info
*this_frame
,
2528 void **this_cache
, int regnum
)
2530 /* Make sure we've initialized the cache. */
2531 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2533 return i386_frame_prev_register (this_frame
, this_cache
, regnum
);
2537 i386_sigtramp_frame_sniffer (const struct frame_unwind
*self
,
2538 struct frame_info
*this_frame
,
2539 void **this_prologue_cache
)
2541 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (this_frame
));
2543 /* We shouldn't even bother if we don't have a sigcontext_addr
2545 if (tdep
->sigcontext_addr
== NULL
)
2548 if (tdep
->sigtramp_p
!= NULL
)
2550 if (tdep
->sigtramp_p (this_frame
))
2554 if (tdep
->sigtramp_start
!= 0)
2556 CORE_ADDR pc
= get_frame_pc (this_frame
);
2558 gdb_assert (tdep
->sigtramp_end
!= 0);
2559 if (pc
>= tdep
->sigtramp_start
&& pc
< tdep
->sigtramp_end
)
2566 static const struct frame_unwind i386_sigtramp_frame_unwind
=
2569 i386_sigtramp_frame_unwind_stop_reason
,
2570 i386_sigtramp_frame_this_id
,
2571 i386_sigtramp_frame_prev_register
,
2573 i386_sigtramp_frame_sniffer
2578 i386_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
2580 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
2585 static const struct frame_base i386_frame_base
=
2588 i386_frame_base_address
,
2589 i386_frame_base_address
,
2590 i386_frame_base_address
2593 static struct frame_id
2594 i386_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
2598 fp
= get_frame_register_unsigned (this_frame
, I386_EBP_REGNUM
);
2600 /* See the end of i386_push_dummy_call. */
2601 return frame_id_build (fp
+ 8, get_frame_pc (this_frame
));
2604 /* _Decimal128 function return values need 16-byte alignment on the
2608 i386_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
2610 return sp
& -(CORE_ADDR
)16;
2614 /* Figure out where the longjmp will land. Slurp the args out of the
2615 stack. We expect the first arg to be a pointer to the jmp_buf
2616 structure from which we extract the address that we will land at.
2617 This address is copied into PC. This routine returns non-zero on
2621 i386_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
2624 CORE_ADDR sp
, jb_addr
;
2625 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2626 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2627 int jb_pc_offset
= gdbarch_tdep (gdbarch
)->jb_pc_offset
;
2629 /* If JB_PC_OFFSET is -1, we have no way to find out where the
2630 longjmp will land. */
2631 if (jb_pc_offset
== -1)
2634 get_frame_register (frame
, I386_ESP_REGNUM
, buf
);
2635 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
2636 if (target_read_memory (sp
+ 4, buf
, 4))
2639 jb_addr
= extract_unsigned_integer (buf
, 4, byte_order
);
2640 if (target_read_memory (jb_addr
+ jb_pc_offset
, buf
, 4))
2643 *pc
= extract_unsigned_integer (buf
, 4, byte_order
);
2648 /* Check whether TYPE must be 16-byte-aligned when passed as a
2649 function argument. 16-byte vectors, _Decimal128 and structures or
2650 unions containing such types must be 16-byte-aligned; other
2651 arguments are 4-byte-aligned. */
2654 i386_16_byte_align_p (struct type
*type
)
2656 type
= check_typedef (type
);
2657 if ((type
->code () == TYPE_CODE_DECFLOAT
2658 || (type
->code () == TYPE_CODE_ARRAY
&& type
->is_vector ()))
2659 && TYPE_LENGTH (type
) == 16)
2661 if (type
->code () == TYPE_CODE_ARRAY
)
2662 return i386_16_byte_align_p (TYPE_TARGET_TYPE (type
));
2663 if (type
->code () == TYPE_CODE_STRUCT
2664 || type
->code () == TYPE_CODE_UNION
)
2667 for (i
= 0; i
< type
->num_fields (); i
++)
2669 if (i386_16_byte_align_p (type
->field (i
).type ()))
2676 /* Implementation for set_gdbarch_push_dummy_code. */
2679 i386_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
, CORE_ADDR funaddr
,
2680 struct value
**args
, int nargs
, struct type
*value_type
,
2681 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
,
2682 struct regcache
*regcache
)
2684 /* Use 0xcc breakpoint - 1 byte. */
2688 /* Keep the stack aligned. */
2692 /* The "push_dummy_call" gdbarch method, optionally with the thiscall
2693 calling convention. */
2696 i386_thiscall_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2697 struct regcache
*regcache
, CORE_ADDR bp_addr
,
2698 int nargs
, struct value
**args
, CORE_ADDR sp
,
2699 function_call_return_method return_method
,
2700 CORE_ADDR struct_addr
, bool thiscall
)
2702 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2708 /* BND registers can be in arbitrary values at the moment of the
2709 inferior call. This can cause boundary violations that are not
2710 due to a real bug or even desired by the user. The best to be done
2711 is set the BND registers to allow access to the whole memory, INIT
2712 state, before pushing the inferior call. */
2713 i387_reset_bnd_regs (gdbarch
, regcache
);
2715 /* Determine the total space required for arguments and struct
2716 return address in a first pass (allowing for 16-byte-aligned
2717 arguments), then push arguments in a second pass. */
2719 for (write_pass
= 0; write_pass
< 2; write_pass
++)
2721 int args_space_used
= 0;
2723 if (return_method
== return_method_struct
)
2727 /* Push value address. */
2728 store_unsigned_integer (buf
, 4, byte_order
, struct_addr
);
2729 write_memory (sp
, buf
, 4);
2730 args_space_used
+= 4;
2736 for (i
= thiscall
? 1 : 0; i
< nargs
; i
++)
2738 int len
= TYPE_LENGTH (value_enclosing_type (args
[i
]));
2742 if (i386_16_byte_align_p (value_enclosing_type (args
[i
])))
2743 args_space_used
= align_up (args_space_used
, 16);
2745 write_memory (sp
+ args_space_used
,
2746 value_contents_all (args
[i
]), len
);
2747 /* The System V ABI says that:
2749 "An argument's size is increased, if necessary, to make it a
2750 multiple of [32-bit] words. This may require tail padding,
2751 depending on the size of the argument."
2753 This makes sure the stack stays word-aligned. */
2754 args_space_used
+= align_up (len
, 4);
2758 if (i386_16_byte_align_p (value_enclosing_type (args
[i
])))
2759 args_space
= align_up (args_space
, 16);
2760 args_space
+= align_up (len
, 4);
2768 /* The original System V ABI only requires word alignment,
2769 but modern incarnations need 16-byte alignment in order
2770 to support SSE. Since wasting a few bytes here isn't
2771 harmful we unconditionally enforce 16-byte alignment. */
2776 /* Store return address. */
2778 store_unsigned_integer (buf
, 4, byte_order
, bp_addr
);
2779 write_memory (sp
, buf
, 4);
2781 /* Finally, update the stack pointer... */
2782 store_unsigned_integer (buf
, 4, byte_order
, sp
);
2783 regcache
->cooked_write (I386_ESP_REGNUM
, buf
);
2785 /* ...and fake a frame pointer. */
2786 regcache
->cooked_write (I386_EBP_REGNUM
, buf
);
2788 /* The 'this' pointer needs to be in ECX. */
2790 regcache
->cooked_write (I386_ECX_REGNUM
, value_contents_all (args
[0]));
2792 /* MarkK wrote: This "+ 8" is all over the place:
2793 (i386_frame_this_id, i386_sigtramp_frame_this_id,
2794 i386_dummy_id). It's there, since all frame unwinders for
2795 a given target have to agree (within a certain margin) on the
2796 definition of the stack address of a frame. Otherwise frame id
2797 comparison might not work correctly. Since DWARF2/GCC uses the
2798 stack address *before* the function call as a frame's CFA. On
2799 the i386, when %ebp is used as a frame pointer, the offset
2800 between the contents %ebp and the CFA as defined by GCC. */
2804 /* Implement the "push_dummy_call" gdbarch method. */
2807 i386_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2808 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
2809 struct value
**args
, CORE_ADDR sp
,
2810 function_call_return_method return_method
,
2811 CORE_ADDR struct_addr
)
2813 return i386_thiscall_push_dummy_call (gdbarch
, function
, regcache
, bp_addr
,
2814 nargs
, args
, sp
, return_method
,
2815 struct_addr
, false);
2818 /* These registers are used for returning integers (and on some
2819 targets also for returning `struct' and `union' values when their
2820 size and alignment match an integer type). */
2821 #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */
2822 #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */
2824 /* Read, for architecture GDBARCH, a function return value of TYPE
2825 from REGCACHE, and copy that into VALBUF. */
2828 i386_extract_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
2829 struct regcache
*regcache
, gdb_byte
*valbuf
)
2831 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2832 int len
= TYPE_LENGTH (type
);
2833 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
2835 if (type
->code () == TYPE_CODE_FLT
)
2837 if (tdep
->st0_regnum
< 0)
2839 warning (_("Cannot find floating-point return value."));
2840 memset (valbuf
, 0, len
);
2844 /* Floating-point return values can be found in %st(0). Convert
2845 its contents to the desired type. This is probably not
2846 exactly how it would happen on the target itself, but it is
2847 the best we can do. */
2848 regcache
->raw_read (I386_ST0_REGNUM
, buf
);
2849 target_float_convert (buf
, i387_ext_type (gdbarch
), valbuf
, type
);
2853 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
2854 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
2856 if (len
<= low_size
)
2858 regcache
->raw_read (LOW_RETURN_REGNUM
, buf
);
2859 memcpy (valbuf
, buf
, len
);
2861 else if (len
<= (low_size
+ high_size
))
2863 regcache
->raw_read (LOW_RETURN_REGNUM
, buf
);
2864 memcpy (valbuf
, buf
, low_size
);
2865 regcache
->raw_read (HIGH_RETURN_REGNUM
, buf
);
2866 memcpy (valbuf
+ low_size
, buf
, len
- low_size
);
2869 internal_error (__FILE__
, __LINE__
,
2870 _("Cannot extract return value of %d bytes long."),
2875 /* Write, for architecture GDBARCH, a function return value of TYPE
2876 from VALBUF into REGCACHE. */
2879 i386_store_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
2880 struct regcache
*regcache
, const gdb_byte
*valbuf
)
2882 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2883 int len
= TYPE_LENGTH (type
);
2885 if (type
->code () == TYPE_CODE_FLT
)
2888 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
2890 if (tdep
->st0_regnum
< 0)
2892 warning (_("Cannot set floating-point return value."));
2896 /* Returning floating-point values is a bit tricky. Apart from
2897 storing the return value in %st(0), we have to simulate the
2898 state of the FPU at function return point. */
2900 /* Convert the value found in VALBUF to the extended
2901 floating-point format used by the FPU. This is probably
2902 not exactly how it would happen on the target itself, but
2903 it is the best we can do. */
2904 target_float_convert (valbuf
, type
, buf
, i387_ext_type (gdbarch
));
2905 regcache
->raw_write (I386_ST0_REGNUM
, buf
);
2907 /* Set the top of the floating-point register stack to 7. The
2908 actual value doesn't really matter, but 7 is what a normal
2909 function return would end up with if the program started out
2910 with a freshly initialized FPU. */
2911 regcache_raw_read_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), &fstat
);
2913 regcache_raw_write_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), fstat
);
2915 /* Mark %st(1) through %st(7) as empty. Since we set the top of
2916 the floating-point register stack to 7, the appropriate value
2917 for the tag word is 0x3fff. */
2918 regcache_raw_write_unsigned (regcache
, I387_FTAG_REGNUM (tdep
), 0x3fff);
2922 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
2923 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
2925 if (len
<= low_size
)
2926 regcache
->raw_write_part (LOW_RETURN_REGNUM
, 0, len
, valbuf
);
2927 else if (len
<= (low_size
+ high_size
))
2929 regcache
->raw_write (LOW_RETURN_REGNUM
, valbuf
);
2930 regcache
->raw_write_part (HIGH_RETURN_REGNUM
, 0, len
- low_size
,
2934 internal_error (__FILE__
, __LINE__
,
2935 _("Cannot store return value of %d bytes long."), len
);
2940 /* This is the variable that is set with "set struct-convention", and
2941 its legitimate values. */
2942 static const char default_struct_convention
[] = "default";
2943 static const char pcc_struct_convention
[] = "pcc";
2944 static const char reg_struct_convention
[] = "reg";
2945 static const char *const valid_conventions
[] =
2947 default_struct_convention
,
2948 pcc_struct_convention
,
2949 reg_struct_convention
,
2952 static const char *struct_convention
= default_struct_convention
;
2954 /* Return non-zero if TYPE, which is assumed to be a structure,
2955 a union type, or an array type, should be returned in registers
2956 for architecture GDBARCH. */
2959 i386_reg_struct_return_p (struct gdbarch
*gdbarch
, struct type
*type
)
2961 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2962 enum type_code code
= type
->code ();
2963 int len
= TYPE_LENGTH (type
);
2965 gdb_assert (code
== TYPE_CODE_STRUCT
2966 || code
== TYPE_CODE_UNION
2967 || code
== TYPE_CODE_ARRAY
);
2969 if (struct_convention
== pcc_struct_convention
2970 || (struct_convention
== default_struct_convention
2971 && tdep
->struct_return
== pcc_struct_return
))
2974 /* Structures consisting of a single `float', `double' or 'long
2975 double' member are returned in %st(0). */
2976 if (code
== TYPE_CODE_STRUCT
&& type
->num_fields () == 1)
2978 type
= check_typedef (type
->field (0).type ());
2979 if (type
->code () == TYPE_CODE_FLT
)
2980 return (len
== 4 || len
== 8 || len
== 12);
2983 return (len
== 1 || len
== 2 || len
== 4 || len
== 8);
2986 /* Determine, for architecture GDBARCH, how a return value of TYPE
2987 should be returned. If it is supposed to be returned in registers,
2988 and READBUF is non-zero, read the appropriate value from REGCACHE,
2989 and copy it into READBUF. If WRITEBUF is non-zero, write the value
2990 from WRITEBUF into REGCACHE. */
2992 static enum return_value_convention
2993 i386_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
2994 struct type
*type
, struct regcache
*regcache
,
2995 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2997 enum type_code code
= type
->code ();
2999 if (((code
== TYPE_CODE_STRUCT
3000 || code
== TYPE_CODE_UNION
3001 || code
== TYPE_CODE_ARRAY
)
3002 && !i386_reg_struct_return_p (gdbarch
, type
))
3003 /* Complex double and long double uses the struct return convention. */
3004 || (code
== TYPE_CODE_COMPLEX
&& TYPE_LENGTH (type
) == 16)
3005 || (code
== TYPE_CODE_COMPLEX
&& TYPE_LENGTH (type
) == 24)
3006 /* 128-bit decimal float uses the struct return convention. */
3007 || (code
== TYPE_CODE_DECFLOAT
&& TYPE_LENGTH (type
) == 16))
3009 /* The System V ABI says that:
3011 "A function that returns a structure or union also sets %eax
3012 to the value of the original address of the caller's area
3013 before it returns. Thus when the caller receives control
3014 again, the address of the returned object resides in register
3015 %eax and can be used to access the object."
3017 So the ABI guarantees that we can always find the return
3018 value just after the function has returned. */
3020 /* Note that the ABI doesn't mention functions returning arrays,
3021 which is something possible in certain languages such as Ada.
3022 In this case, the value is returned as if it was wrapped in
3023 a record, so the convention applied to records also applies
3030 regcache_raw_read_unsigned (regcache
, I386_EAX_REGNUM
, &addr
);
3031 read_memory (addr
, readbuf
, TYPE_LENGTH (type
));
3034 return RETURN_VALUE_ABI_RETURNS_ADDRESS
;
3037 /* This special case is for structures consisting of a single
3038 `float', `double' or 'long double' member. These structures are
3039 returned in %st(0). For these structures, we call ourselves
3040 recursively, changing TYPE into the type of the first member of
3041 the structure. Since that should work for all structures that
3042 have only one member, we don't bother to check the member's type
3044 if (code
== TYPE_CODE_STRUCT
&& type
->num_fields () == 1)
3046 type
= check_typedef (type
->field (0).type ());
3047 return i386_return_value (gdbarch
, function
, type
, regcache
,
3052 i386_extract_return_value (gdbarch
, type
, regcache
, readbuf
);
3054 i386_store_return_value (gdbarch
, type
, regcache
, writebuf
);
3056 return RETURN_VALUE_REGISTER_CONVENTION
;
3061 i387_ext_type (struct gdbarch
*gdbarch
)
3063 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3065 if (!tdep
->i387_ext_type
)
3067 tdep
->i387_ext_type
= tdesc_find_type (gdbarch
, "i387_ext");
3068 gdb_assert (tdep
->i387_ext_type
!= NULL
);
3071 return tdep
->i387_ext_type
;
3074 /* Construct type for pseudo BND registers. We can't use
3075 tdesc_find_type since a complement of one value has to be used
3076 to describe the upper bound. */
3078 static struct type
*
3079 i386_bnd_type (struct gdbarch
*gdbarch
)
3081 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3084 if (!tdep
->i386_bnd_type
)
3087 const struct builtin_type
*bt
= builtin_type (gdbarch
);
3089 /* The type we're building is described bellow: */
3094 void *ubound
; /* One complement of raw ubound field. */
3098 t
= arch_composite_type (gdbarch
,
3099 "__gdb_builtin_type_bound128", TYPE_CODE_STRUCT
);
3101 append_composite_type_field (t
, "lbound", bt
->builtin_data_ptr
);
3102 append_composite_type_field (t
, "ubound", bt
->builtin_data_ptr
);
3104 t
->set_name ("builtin_type_bound128");
3105 tdep
->i386_bnd_type
= t
;
3108 return tdep
->i386_bnd_type
;
3111 /* Construct vector type for pseudo ZMM registers. We can't use
3112 tdesc_find_type since ZMM isn't described in target description. */
3114 static struct type
*
3115 i386_zmm_type (struct gdbarch
*gdbarch
)
3117 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3119 if (!tdep
->i386_zmm_type
)
3121 const struct builtin_type
*bt
= builtin_type (gdbarch
);
3123 /* The type we're building is this: */
3125 union __gdb_builtin_type_vec512i
3127 int128_t v4_int128
[4];
3128 int64_t v8_int64
[8];
3129 int32_t v16_int32
[16];
3130 int16_t v32_int16
[32];
3131 int8_t v64_int8
[64];
3132 double v8_double
[8];
3133 float v16_float
[16];
3134 bfloat16_t v32_bfloat16
[32];
3140 t
= arch_composite_type (gdbarch
,
3141 "__gdb_builtin_type_vec512i", TYPE_CODE_UNION
);
3142 append_composite_type_field (t
, "v32_bfloat16",
3143 init_vector_type (bt
->builtin_bfloat16
, 32));
3144 append_composite_type_field (t
, "v16_float",
3145 init_vector_type (bt
->builtin_float
, 16));
3146 append_composite_type_field (t
, "v8_double",
3147 init_vector_type (bt
->builtin_double
, 8));
3148 append_composite_type_field (t
, "v64_int8",
3149 init_vector_type (bt
->builtin_int8
, 64));
3150 append_composite_type_field (t
, "v32_int16",
3151 init_vector_type (bt
->builtin_int16
, 32));
3152 append_composite_type_field (t
, "v16_int32",
3153 init_vector_type (bt
->builtin_int32
, 16));
3154 append_composite_type_field (t
, "v8_int64",
3155 init_vector_type (bt
->builtin_int64
, 8));
3156 append_composite_type_field (t
, "v4_int128",
3157 init_vector_type (bt
->builtin_int128
, 4));
3159 t
->set_is_vector (true);
3160 t
->set_name ("builtin_type_vec512i");
3161 tdep
->i386_zmm_type
= t
;
3164 return tdep
->i386_zmm_type
;
3167 /* Construct vector type for pseudo YMM registers. We can't use
3168 tdesc_find_type since YMM isn't described in target description. */
3170 static struct type
*
3171 i386_ymm_type (struct gdbarch
*gdbarch
)
3173 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3175 if (!tdep
->i386_ymm_type
)
3177 const struct builtin_type
*bt
= builtin_type (gdbarch
);
3179 /* The type we're building is this: */
3181 union __gdb_builtin_type_vec256i
3183 int128_t v2_int128
[2];
3184 int64_t v4_int64
[4];
3185 int32_t v8_int32
[8];
3186 int16_t v16_int16
[16];
3187 int8_t v32_int8
[32];
3188 double v4_double
[4];
3190 bfloat16_t v16_bfloat16
[16];
3196 t
= arch_composite_type (gdbarch
,
3197 "__gdb_builtin_type_vec256i", TYPE_CODE_UNION
);
3198 append_composite_type_field (t
, "v16_bfloat16",
3199 init_vector_type (bt
->builtin_bfloat16
, 16));
3200 append_composite_type_field (t
, "v8_float",
3201 init_vector_type (bt
->builtin_float
, 8));
3202 append_composite_type_field (t
, "v4_double",
3203 init_vector_type (bt
->builtin_double
, 4));
3204 append_composite_type_field (t
, "v32_int8",
3205 init_vector_type (bt
->builtin_int8
, 32));
3206 append_composite_type_field (t
, "v16_int16",
3207 init_vector_type (bt
->builtin_int16
, 16));
3208 append_composite_type_field (t
, "v8_int32",
3209 init_vector_type (bt
->builtin_int32
, 8));
3210 append_composite_type_field (t
, "v4_int64",
3211 init_vector_type (bt
->builtin_int64
, 4));
3212 append_composite_type_field (t
, "v2_int128",
3213 init_vector_type (bt
->builtin_int128
, 2));
3215 t
->set_is_vector (true);
3216 t
->set_name ("builtin_type_vec256i");
3217 tdep
->i386_ymm_type
= t
;
3220 return tdep
->i386_ymm_type
;
3223 /* Construct vector type for MMX registers. */
3224 static struct type
*
3225 i386_mmx_type (struct gdbarch
*gdbarch
)
3227 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3229 if (!tdep
->i386_mmx_type
)
3231 const struct builtin_type
*bt
= builtin_type (gdbarch
);
3233 /* The type we're building is this: */
3235 union __gdb_builtin_type_vec64i
3238 int32_t v2_int32
[2];
3239 int16_t v4_int16
[4];
3246 t
= arch_composite_type (gdbarch
,
3247 "__gdb_builtin_type_vec64i", TYPE_CODE_UNION
);
3249 append_composite_type_field (t
, "uint64", bt
->builtin_int64
);
3250 append_composite_type_field (t
, "v2_int32",
3251 init_vector_type (bt
->builtin_int32
, 2));
3252 append_composite_type_field (t
, "v4_int16",
3253 init_vector_type (bt
->builtin_int16
, 4));
3254 append_composite_type_field (t
, "v8_int8",
3255 init_vector_type (bt
->builtin_int8
, 8));
3257 t
->set_is_vector (true);
3258 t
->set_name ("builtin_type_vec64i");
3259 tdep
->i386_mmx_type
= t
;
3262 return tdep
->i386_mmx_type
;
3265 /* Return the GDB type object for the "standard" data type of data in
3269 i386_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
3271 if (i386_bnd_regnum_p (gdbarch
, regnum
))
3272 return i386_bnd_type (gdbarch
);
3273 if (i386_mmx_regnum_p (gdbarch
, regnum
))
3274 return i386_mmx_type (gdbarch
);
3275 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
3276 return i386_ymm_type (gdbarch
);
3277 else if (i386_ymm_avx512_regnum_p (gdbarch
, regnum
))
3278 return i386_ymm_type (gdbarch
);
3279 else if (i386_zmm_regnum_p (gdbarch
, regnum
))
3280 return i386_zmm_type (gdbarch
);
3283 const struct builtin_type
*bt
= builtin_type (gdbarch
);
3284 if (i386_byte_regnum_p (gdbarch
, regnum
))
3285 return bt
->builtin_int8
;
3286 else if (i386_word_regnum_p (gdbarch
, regnum
))
3287 return bt
->builtin_int16
;
3288 else if (i386_dword_regnum_p (gdbarch
, regnum
))
3289 return bt
->builtin_int32
;
3290 else if (i386_k_regnum_p (gdbarch
, regnum
))
3291 return bt
->builtin_int64
;
3294 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
3297 /* Map a cooked register onto a raw register or memory. For the i386,
3298 the MMX registers need to be mapped onto floating point registers. */
3301 i386_mmx_regnum_to_fp_regnum (readable_regcache
*regcache
, int regnum
)
3303 struct gdbarch_tdep
*tdep
= gdbarch_tdep (regcache
->arch ());
3308 mmxreg
= regnum
- tdep
->mm0_regnum
;
3309 regcache
->raw_read (I387_FSTAT_REGNUM (tdep
), &fstat
);
3310 tos
= (fstat
>> 11) & 0x7;
3311 fpreg
= (mmxreg
+ tos
) % 8;
3313 return (I387_ST0_REGNUM (tdep
) + fpreg
);
3316 /* A helper function for us by i386_pseudo_register_read_value and
3317 amd64_pseudo_register_read_value. It does all the work but reads
3318 the data into an already-allocated value. */
3321 i386_pseudo_register_read_into_value (struct gdbarch
*gdbarch
,
3322 readable_regcache
*regcache
,
3324 struct value
*result_value
)
3326 gdb_byte raw_buf
[I386_MAX_REGISTER_SIZE
];
3327 enum register_status status
;
3328 gdb_byte
*buf
= value_contents_raw (result_value
);
3330 if (i386_mmx_regnum_p (gdbarch
, regnum
))
3332 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
3334 /* Extract (always little endian). */
3335 status
= regcache
->raw_read (fpnum
, raw_buf
);
3336 if (status
!= REG_VALID
)
3337 mark_value_bytes_unavailable (result_value
, 0,
3338 TYPE_LENGTH (value_type (result_value
)));
3340 memcpy (buf
, raw_buf
, register_size (gdbarch
, regnum
));
3344 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3345 if (i386_bnd_regnum_p (gdbarch
, regnum
))
3347 regnum
-= tdep
->bnd0_regnum
;
3349 /* Extract (always little endian). Read lower 128bits. */
3350 status
= regcache
->raw_read (I387_BND0R_REGNUM (tdep
) + regnum
,
3352 if (status
!= REG_VALID
)
3353 mark_value_bytes_unavailable (result_value
, 0, 16);
3356 enum bfd_endian byte_order
= gdbarch_byte_order (target_gdbarch ());
3357 LONGEST upper
, lower
;
3358 int size
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_data_ptr
);
3360 lower
= extract_unsigned_integer (raw_buf
, 8, byte_order
);
3361 upper
= extract_unsigned_integer (raw_buf
+ 8, 8, byte_order
);
3364 memcpy (buf
, &lower
, size
);
3365 memcpy (buf
+ size
, &upper
, size
);
3368 else if (i386_k_regnum_p (gdbarch
, regnum
))
3370 regnum
-= tdep
->k0_regnum
;
3372 /* Extract (always little endian). */
3373 status
= regcache
->raw_read (tdep
->k0_regnum
+ regnum
, raw_buf
);
3374 if (status
!= REG_VALID
)
3375 mark_value_bytes_unavailable (result_value
, 0, 8);
3377 memcpy (buf
, raw_buf
, 8);
3379 else if (i386_zmm_regnum_p (gdbarch
, regnum
))
3381 regnum
-= tdep
->zmm0_regnum
;
3383 if (regnum
< num_lower_zmm_regs
)
3385 /* Extract (always little endian). Read lower 128bits. */
3386 status
= regcache
->raw_read (I387_XMM0_REGNUM (tdep
) + regnum
,
3388 if (status
!= REG_VALID
)
3389 mark_value_bytes_unavailable (result_value
, 0, 16);
3391 memcpy (buf
, raw_buf
, 16);
3393 /* Extract (always little endian). Read upper 128bits. */
3394 status
= regcache
->raw_read (tdep
->ymm0h_regnum
+ regnum
,
3396 if (status
!= REG_VALID
)
3397 mark_value_bytes_unavailable (result_value
, 16, 16);
3399 memcpy (buf
+ 16, raw_buf
, 16);
3403 /* Extract (always little endian). Read lower 128bits. */
3404 status
= regcache
->raw_read (I387_XMM16_REGNUM (tdep
) + regnum
3405 - num_lower_zmm_regs
,
3407 if (status
!= REG_VALID
)
3408 mark_value_bytes_unavailable (result_value
, 0, 16);
3410 memcpy (buf
, raw_buf
, 16);
3412 /* Extract (always little endian). Read upper 128bits. */
3413 status
= regcache
->raw_read (I387_YMM16H_REGNUM (tdep
) + regnum
3414 - num_lower_zmm_regs
,
3416 if (status
!= REG_VALID
)
3417 mark_value_bytes_unavailable (result_value
, 16, 16);
3419 memcpy (buf
+ 16, raw_buf
, 16);
3422 /* Read upper 256bits. */
3423 status
= regcache
->raw_read (tdep
->zmm0h_regnum
+ regnum
,
3425 if (status
!= REG_VALID
)
3426 mark_value_bytes_unavailable (result_value
, 32, 32);
3428 memcpy (buf
+ 32, raw_buf
, 32);
3430 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
3432 regnum
-= tdep
->ymm0_regnum
;
3434 /* Extract (always little endian). Read lower 128bits. */
3435 status
= regcache
->raw_read (I387_XMM0_REGNUM (tdep
) + regnum
,
3437 if (status
!= REG_VALID
)
3438 mark_value_bytes_unavailable (result_value
, 0, 16);
3440 memcpy (buf
, raw_buf
, 16);
3441 /* Read upper 128bits. */
3442 status
= regcache
->raw_read (tdep
->ymm0h_regnum
+ regnum
,
3444 if (status
!= REG_VALID
)
3445 mark_value_bytes_unavailable (result_value
, 16, 32);
3447 memcpy (buf
+ 16, raw_buf
, 16);
3449 else if (i386_ymm_avx512_regnum_p (gdbarch
, regnum
))
3451 regnum
-= tdep
->ymm16_regnum
;
3452 /* Extract (always little endian). Read lower 128bits. */
3453 status
= regcache
->raw_read (I387_XMM16_REGNUM (tdep
) + regnum
,
3455 if (status
!= REG_VALID
)
3456 mark_value_bytes_unavailable (result_value
, 0, 16);
3458 memcpy (buf
, raw_buf
, 16);
3459 /* Read upper 128bits. */
3460 status
= regcache
->raw_read (tdep
->ymm16h_regnum
+ regnum
,
3462 if (status
!= REG_VALID
)
3463 mark_value_bytes_unavailable (result_value
, 16, 16);
3465 memcpy (buf
+ 16, raw_buf
, 16);
3467 else if (i386_word_regnum_p (gdbarch
, regnum
))
3469 int gpnum
= regnum
- tdep
->ax_regnum
;
3471 /* Extract (always little endian). */
3472 status
= regcache
->raw_read (gpnum
, raw_buf
);
3473 if (status
!= REG_VALID
)
3474 mark_value_bytes_unavailable (result_value
, 0,
3475 TYPE_LENGTH (value_type (result_value
)));
3477 memcpy (buf
, raw_buf
, 2);
3479 else if (i386_byte_regnum_p (gdbarch
, regnum
))
3481 int gpnum
= regnum
- tdep
->al_regnum
;
3483 /* Extract (always little endian). We read both lower and
3485 status
= regcache
->raw_read (gpnum
% 4, raw_buf
);
3486 if (status
!= REG_VALID
)
3487 mark_value_bytes_unavailable (result_value
, 0,
3488 TYPE_LENGTH (value_type (result_value
)));
3489 else if (gpnum
>= 4)
3490 memcpy (buf
, raw_buf
+ 1, 1);
3492 memcpy (buf
, raw_buf
, 1);
3495 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
3499 static struct value
*
3500 i386_pseudo_register_read_value (struct gdbarch
*gdbarch
,
3501 readable_regcache
*regcache
,
3504 struct value
*result
;
3506 result
= allocate_value (register_type (gdbarch
, regnum
));
3507 VALUE_LVAL (result
) = lval_register
;
3508 VALUE_REGNUM (result
) = regnum
;
3510 i386_pseudo_register_read_into_value (gdbarch
, regcache
, regnum
, result
);
3516 i386_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
3517 int regnum
, const gdb_byte
*buf
)
3519 gdb_byte raw_buf
[I386_MAX_REGISTER_SIZE
];
3521 if (i386_mmx_regnum_p (gdbarch
, regnum
))
3523 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
3526 regcache
->raw_read (fpnum
, raw_buf
);
3527 /* ... Modify ... (always little endian). */
3528 memcpy (raw_buf
, buf
, register_size (gdbarch
, regnum
));
3530 regcache
->raw_write (fpnum
, raw_buf
);
3534 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3536 if (i386_bnd_regnum_p (gdbarch
, regnum
))
3538 ULONGEST upper
, lower
;
3539 int size
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_data_ptr
);
3540 enum bfd_endian byte_order
= gdbarch_byte_order (target_gdbarch ());
3542 /* New values from input value. */
3543 regnum
-= tdep
->bnd0_regnum
;
3544 lower
= extract_unsigned_integer (buf
, size
, byte_order
);
3545 upper
= extract_unsigned_integer (buf
+ size
, size
, byte_order
);
3547 /* Fetching register buffer. */
3548 regcache
->raw_read (I387_BND0R_REGNUM (tdep
) + regnum
,
3553 /* Set register bits. */
3554 memcpy (raw_buf
, &lower
, 8);
3555 memcpy (raw_buf
+ 8, &upper
, 8);
3557 regcache
->raw_write (I387_BND0R_REGNUM (tdep
) + regnum
, raw_buf
);
3559 else if (i386_k_regnum_p (gdbarch
, regnum
))
3561 regnum
-= tdep
->k0_regnum
;
3563 regcache
->raw_write (tdep
->k0_regnum
+ regnum
, buf
);
3565 else if (i386_zmm_regnum_p (gdbarch
, regnum
))
3567 regnum
-= tdep
->zmm0_regnum
;
3569 if (regnum
< num_lower_zmm_regs
)
3571 /* Write lower 128bits. */
3572 regcache
->raw_write (I387_XMM0_REGNUM (tdep
) + regnum
, buf
);
3573 /* Write upper 128bits. */
3574 regcache
->raw_write (I387_YMM0_REGNUM (tdep
) + regnum
, buf
+ 16);
3578 /* Write lower 128bits. */
3579 regcache
->raw_write (I387_XMM16_REGNUM (tdep
) + regnum
3580 - num_lower_zmm_regs
, buf
);
3581 /* Write upper 128bits. */
3582 regcache
->raw_write (I387_YMM16H_REGNUM (tdep
) + regnum
3583 - num_lower_zmm_regs
, buf
+ 16);
3585 /* Write upper 256bits. */
3586 regcache
->raw_write (tdep
->zmm0h_regnum
+ regnum
, buf
+ 32);
3588 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
3590 regnum
-= tdep
->ymm0_regnum
;
3592 /* ... Write lower 128bits. */
3593 regcache
->raw_write (I387_XMM0_REGNUM (tdep
) + regnum
, buf
);
3594 /* ... Write upper 128bits. */
3595 regcache
->raw_write (tdep
->ymm0h_regnum
+ regnum
, buf
+ 16);
3597 else if (i386_ymm_avx512_regnum_p (gdbarch
, regnum
))
3599 regnum
-= tdep
->ymm16_regnum
;
3601 /* ... Write lower 128bits. */
3602 regcache
->raw_write (I387_XMM16_REGNUM (tdep
) + regnum
, buf
);
3603 /* ... Write upper 128bits. */
3604 regcache
->raw_write (tdep
->ymm16h_regnum
+ regnum
, buf
+ 16);
3606 else if (i386_word_regnum_p (gdbarch
, regnum
))
3608 int gpnum
= regnum
- tdep
->ax_regnum
;
3611 regcache
->raw_read (gpnum
, raw_buf
);
3612 /* ... Modify ... (always little endian). */
3613 memcpy (raw_buf
, buf
, 2);
3615 regcache
->raw_write (gpnum
, raw_buf
);
3617 else if (i386_byte_regnum_p (gdbarch
, regnum
))
3619 int gpnum
= regnum
- tdep
->al_regnum
;
3621 /* Read ... We read both lower and upper registers. */
3622 regcache
->raw_read (gpnum
% 4, raw_buf
);
3623 /* ... Modify ... (always little endian). */
3625 memcpy (raw_buf
+ 1, buf
, 1);
3627 memcpy (raw_buf
, buf
, 1);
3629 regcache
->raw_write (gpnum
% 4, raw_buf
);
3632 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
3636 /* Implement the 'ax_pseudo_register_collect' gdbarch method. */
3639 i386_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
3640 struct agent_expr
*ax
, int regnum
)
3642 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3644 if (i386_mmx_regnum_p (gdbarch
, regnum
))
3646 /* MMX to FPU register mapping depends on current TOS. Let's just
3647 not care and collect everything... */
3650 ax_reg_mask (ax
, I387_FSTAT_REGNUM (tdep
));
3651 for (i
= 0; i
< 8; i
++)
3652 ax_reg_mask (ax
, I387_ST0_REGNUM (tdep
) + i
);
3655 else if (i386_bnd_regnum_p (gdbarch
, regnum
))
3657 regnum
-= tdep
->bnd0_regnum
;
3658 ax_reg_mask (ax
, I387_BND0R_REGNUM (tdep
) + regnum
);
3661 else if (i386_k_regnum_p (gdbarch
, regnum
))
3663 regnum
-= tdep
->k0_regnum
;
3664 ax_reg_mask (ax
, tdep
->k0_regnum
+ regnum
);
3667 else if (i386_zmm_regnum_p (gdbarch
, regnum
))
3669 regnum
-= tdep
->zmm0_regnum
;
3670 if (regnum
< num_lower_zmm_regs
)
3672 ax_reg_mask (ax
, I387_XMM0_REGNUM (tdep
) + regnum
);
3673 ax_reg_mask (ax
, tdep
->ymm0h_regnum
+ regnum
);
3677 ax_reg_mask (ax
, I387_XMM16_REGNUM (tdep
) + regnum
3678 - num_lower_zmm_regs
);
3679 ax_reg_mask (ax
, I387_YMM16H_REGNUM (tdep
) + regnum
3680 - num_lower_zmm_regs
);
3682 ax_reg_mask (ax
, tdep
->zmm0h_regnum
+ regnum
);
3685 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
3687 regnum
-= tdep
->ymm0_regnum
;
3688 ax_reg_mask (ax
, I387_XMM0_REGNUM (tdep
) + regnum
);
3689 ax_reg_mask (ax
, tdep
->ymm0h_regnum
+ regnum
);
3692 else if (i386_ymm_avx512_regnum_p (gdbarch
, regnum
))
3694 regnum
-= tdep
->ymm16_regnum
;
3695 ax_reg_mask (ax
, I387_XMM16_REGNUM (tdep
) + regnum
);
3696 ax_reg_mask (ax
, tdep
->ymm16h_regnum
+ regnum
);
3699 else if (i386_word_regnum_p (gdbarch
, regnum
))
3701 int gpnum
= regnum
- tdep
->ax_regnum
;
3703 ax_reg_mask (ax
, gpnum
);
3706 else if (i386_byte_regnum_p (gdbarch
, regnum
))
3708 int gpnum
= regnum
- tdep
->al_regnum
;
3710 ax_reg_mask (ax
, gpnum
% 4);
3714 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
3719 /* Return the register number of the register allocated by GCC after
3720 REGNUM, or -1 if there is no such register. */
3723 i386_next_regnum (int regnum
)
3725 /* GCC allocates the registers in the order:
3727 %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ...
3729 Since storing a variable in %esp doesn't make any sense we return
3730 -1 for %ebp and for %esp itself. */
3731 static int next_regnum
[] =
3733 I386_EDX_REGNUM
, /* Slot for %eax. */
3734 I386_EBX_REGNUM
, /* Slot for %ecx. */
3735 I386_ECX_REGNUM
, /* Slot for %edx. */
3736 I386_ESI_REGNUM
, /* Slot for %ebx. */
3737 -1, -1, /* Slots for %esp and %ebp. */
3738 I386_EDI_REGNUM
, /* Slot for %esi. */
3739 I386_EBP_REGNUM
/* Slot for %edi. */
3742 if (regnum
>= 0 && regnum
< sizeof (next_regnum
) / sizeof (next_regnum
[0]))
3743 return next_regnum
[regnum
];
3748 /* Return nonzero if a value of type TYPE stored in register REGNUM
3749 needs any special handling. */
3752 i386_convert_register_p (struct gdbarch
*gdbarch
,
3753 int regnum
, struct type
*type
)
3755 int len
= TYPE_LENGTH (type
);
3757 /* Values may be spread across multiple registers. Most debugging
3758 formats aren't expressive enough to specify the locations, so
3759 some heuristics is involved. Right now we only handle types that
3760 have a length that is a multiple of the word size, since GCC
3761 doesn't seem to put any other types into registers. */
3762 if (len
> 4 && len
% 4 == 0)
3764 int last_regnum
= regnum
;
3768 last_regnum
= i386_next_regnum (last_regnum
);
3772 if (last_regnum
!= -1)
3776 return i387_convert_register_p (gdbarch
, regnum
, type
);
3779 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
3780 return its contents in TO. */
3783 i386_register_to_value (struct frame_info
*frame
, int regnum
,
3784 struct type
*type
, gdb_byte
*to
,
3785 int *optimizedp
, int *unavailablep
)
3787 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3788 int len
= TYPE_LENGTH (type
);
3790 if (i386_fp_regnum_p (gdbarch
, regnum
))
3791 return i387_register_to_value (frame
, regnum
, type
, to
,
3792 optimizedp
, unavailablep
);
3794 /* Read a value spread across multiple registers. */
3796 gdb_assert (len
> 4 && len
% 4 == 0);
3800 gdb_assert (regnum
!= -1);
3801 gdb_assert (register_size (gdbarch
, regnum
) == 4);
3803 if (!get_frame_register_bytes (frame
, regnum
, 0,
3804 register_size (gdbarch
, regnum
),
3805 to
, optimizedp
, unavailablep
))
3808 regnum
= i386_next_regnum (regnum
);
3813 *optimizedp
= *unavailablep
= 0;
3817 /* Write the contents FROM of a value of type TYPE into register
3818 REGNUM in frame FRAME. */
3821 i386_value_to_register (struct frame_info
*frame
, int regnum
,
3822 struct type
*type
, const gdb_byte
*from
)
3824 int len
= TYPE_LENGTH (type
);
3826 if (i386_fp_regnum_p (get_frame_arch (frame
), regnum
))
3828 i387_value_to_register (frame
, regnum
, type
, from
);
3832 /* Write a value spread across multiple registers. */
3834 gdb_assert (len
> 4 && len
% 4 == 0);
3838 gdb_assert (regnum
!= -1);
3839 gdb_assert (register_size (get_frame_arch (frame
), regnum
) == 4);
3841 put_frame_register (frame
, regnum
, from
);
3842 regnum
= i386_next_regnum (regnum
);
3848 /* Supply register REGNUM from the buffer specified by GREGS and LEN
3849 in the general-purpose register set REGSET to register cache
3850 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3853 i386_supply_gregset (const struct regset
*regset
, struct regcache
*regcache
,
3854 int regnum
, const void *gregs
, size_t len
)
3856 struct gdbarch
*gdbarch
= regcache
->arch ();
3857 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3858 const gdb_byte
*regs
= (const gdb_byte
*) gregs
;
3861 gdb_assert (len
>= tdep
->sizeof_gregset
);
3863 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
3865 if ((regnum
== i
|| regnum
== -1)
3866 && tdep
->gregset_reg_offset
[i
] != -1)
3867 regcache
->raw_supply (i
, regs
+ tdep
->gregset_reg_offset
[i
]);
3871 /* Collect register REGNUM from the register cache REGCACHE and store
3872 it in the buffer specified by GREGS and LEN as described by the
3873 general-purpose register set REGSET. If REGNUM is -1, do this for
3874 all registers in REGSET. */
3877 i386_collect_gregset (const struct regset
*regset
,
3878 const struct regcache
*regcache
,
3879 int regnum
, void *gregs
, size_t len
)
3881 struct gdbarch
*gdbarch
= regcache
->arch ();
3882 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3883 gdb_byte
*regs
= (gdb_byte
*) gregs
;
3886 gdb_assert (len
>= tdep
->sizeof_gregset
);
3888 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
3890 if ((regnum
== i
|| regnum
== -1)
3891 && tdep
->gregset_reg_offset
[i
] != -1)
3892 regcache
->raw_collect (i
, regs
+ tdep
->gregset_reg_offset
[i
]);
3896 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
3897 in the floating-point register set REGSET to register cache
3898 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3901 i386_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
3902 int regnum
, const void *fpregs
, size_t len
)
3904 struct gdbarch
*gdbarch
= regcache
->arch ();
3905 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3907 if (len
== I387_SIZEOF_FXSAVE
)
3909 i387_supply_fxsave (regcache
, regnum
, fpregs
);
3913 gdb_assert (len
>= tdep
->sizeof_fpregset
);
3914 i387_supply_fsave (regcache
, regnum
, fpregs
);
3917 /* Collect register REGNUM from the register cache REGCACHE and store
3918 it in the buffer specified by FPREGS and LEN as described by the
3919 floating-point register set REGSET. If REGNUM is -1, do this for
3920 all registers in REGSET. */
3923 i386_collect_fpregset (const struct regset
*regset
,
3924 const struct regcache
*regcache
,
3925 int regnum
, void *fpregs
, size_t len
)
3927 struct gdbarch
*gdbarch
= regcache
->arch ();
3928 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3930 if (len
== I387_SIZEOF_FXSAVE
)
3932 i387_collect_fxsave (regcache
, regnum
, fpregs
);
3936 gdb_assert (len
>= tdep
->sizeof_fpregset
);
3937 i387_collect_fsave (regcache
, regnum
, fpregs
);
3940 /* Register set definitions. */
3942 const struct regset i386_gregset
=
3944 NULL
, i386_supply_gregset
, i386_collect_gregset
3947 const struct regset i386_fpregset
=
3949 NULL
, i386_supply_fpregset
, i386_collect_fpregset
3952 /* Default iterator over core file register note sections. */
3955 i386_iterate_over_regset_sections (struct gdbarch
*gdbarch
,
3956 iterate_over_regset_sections_cb
*cb
,
3958 const struct regcache
*regcache
)
3960 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3962 cb (".reg", tdep
->sizeof_gregset
, tdep
->sizeof_gregset
, &i386_gregset
, NULL
,
3964 if (tdep
->sizeof_fpregset
)
3965 cb (".reg2", tdep
->sizeof_fpregset
, tdep
->sizeof_fpregset
, tdep
->fpregset
,
3970 /* Stuff for WIN32 PE style DLL's but is pretty generic really. */
3973 i386_pe_skip_trampoline_code (struct frame_info
*frame
,
3974 CORE_ADDR pc
, char *name
)
3976 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3977 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3980 if (pc
&& read_memory_unsigned_integer (pc
, 2, byte_order
) == 0x25ff)
3982 unsigned long indirect
=
3983 read_memory_unsigned_integer (pc
+ 2, 4, byte_order
);
3984 struct minimal_symbol
*indsym
=
3985 indirect
? lookup_minimal_symbol_by_pc (indirect
).minsym
: 0;
3986 const char *symname
= indsym
? indsym
->linkage_name () : 0;
3990 if (startswith (symname
, "__imp_")
3991 || startswith (symname
, "_imp_"))
3993 read_memory_unsigned_integer (indirect
, 4, byte_order
);
3996 return 0; /* Not a trampoline. */
4000 /* Return whether the THIS_FRAME corresponds to a sigtramp
4004 i386_sigtramp_p (struct frame_info
*this_frame
)
4006 CORE_ADDR pc
= get_frame_pc (this_frame
);
4009 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
4010 return (name
&& strcmp ("_sigtramp", name
) == 0);
4014 /* We have two flavours of disassembly. The machinery on this page
4015 deals with switching between those. */
4018 i386_print_insn (bfd_vma pc
, struct disassemble_info
*info
)
4020 gdb_assert (disassembly_flavor
== att_flavor
4021 || disassembly_flavor
== intel_flavor
);
4023 info
->disassembler_options
= disassembly_flavor
;
4025 return default_print_insn (pc
, info
);
4029 /* There are a few i386 architecture variants that differ only
4030 slightly from the generic i386 target. For now, we don't give them
4031 their own source file, but include them here. As a consequence,
4032 they'll always be included. */
4034 /* System V Release 4 (SVR4). */
4036 /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp
4040 i386_svr4_sigtramp_p (struct frame_info
*this_frame
)
4042 CORE_ADDR pc
= get_frame_pc (this_frame
);
4045 /* The origin of these symbols is currently unknown. */
4046 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
4047 return (name
&& (strcmp ("_sigreturn", name
) == 0
4048 || strcmp ("sigvechandler", name
) == 0));
4051 /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the
4052 address of the associated sigcontext (ucontext) structure. */
4055 i386_svr4_sigcontext_addr (struct frame_info
*this_frame
)
4057 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
4058 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4062 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
4063 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
4065 return read_memory_unsigned_integer (sp
+ 8, 4, byte_order
);
4070 /* Implementation of `gdbarch_stap_is_single_operand', as defined in
4074 i386_stap_is_single_operand (struct gdbarch
*gdbarch
, const char *s
)
4076 return (*s
== '$' /* Literal number. */
4077 || (isdigit (*s
) && s
[1] == '(' && s
[2] == '%') /* Displacement. */
4078 || (*s
== '(' && s
[1] == '%') /* Register indirection. */
4079 || (*s
== '%' && isalpha (s
[1]))); /* Register access. */
4082 /* Helper function for i386_stap_parse_special_token.
4084 This function parses operands of the form `-8+3+1(%rbp)', which
4085 must be interpreted as `*(-8 + 3 - 1 + (void *) $eax)'.
4087 Return true if the operand was parsed successfully, false
4091 i386_stap_parse_special_token_triplet (struct gdbarch
*gdbarch
,
4092 struct stap_parse_info
*p
)
4094 const char *s
= p
->arg
;
4096 if (isdigit (*s
) || *s
== '-' || *s
== '+')
4100 long displacements
[3];
4107 got_minus
[0] = false;
4113 got_minus
[0] = true;
4116 if (!isdigit ((unsigned char) *s
))
4119 displacements
[0] = strtol (s
, &endp
, 10);
4122 if (*s
!= '+' && *s
!= '-')
4124 /* We are not dealing with a triplet. */
4128 got_minus
[1] = false;
4134 got_minus
[1] = true;
4137 if (!isdigit ((unsigned char) *s
))
4140 displacements
[1] = strtol (s
, &endp
, 10);
4143 if (*s
!= '+' && *s
!= '-')
4145 /* We are not dealing with a triplet. */
4149 got_minus
[2] = false;
4155 got_minus
[2] = true;
4158 if (!isdigit ((unsigned char) *s
))
4161 displacements
[2] = strtol (s
, &endp
, 10);
4164 if (*s
!= '(' || s
[1] != '%')
4170 while (isalnum (*s
))
4176 len
= s
- start
- 1;
4177 regname
= (char *) alloca (len
+ 1);
4179 strncpy (regname
, start
, len
);
4180 regname
[len
] = '\0';
4182 if (user_reg_map_name_to_regnum (gdbarch
, regname
, len
) == -1)
4183 error (_("Invalid register name `%s' on expression `%s'."),
4184 regname
, p
->saved_arg
);
4186 for (i
= 0; i
< 3; i
++)
4188 write_exp_elt_opcode (&p
->pstate
, OP_LONG
);
4190 (&p
->pstate
, builtin_type (gdbarch
)->builtin_long
);
4191 write_exp_elt_longcst (&p
->pstate
, displacements
[i
]);
4192 write_exp_elt_opcode (&p
->pstate
, OP_LONG
);
4194 write_exp_elt_opcode (&p
->pstate
, UNOP_NEG
);
4197 write_exp_elt_opcode (&p
->pstate
, OP_REGISTER
);
4200 write_exp_string (&p
->pstate
, str
);
4201 write_exp_elt_opcode (&p
->pstate
, OP_REGISTER
);
4203 write_exp_elt_opcode (&p
->pstate
, UNOP_CAST
);
4204 write_exp_elt_type (&p
->pstate
,
4205 builtin_type (gdbarch
)->builtin_data_ptr
);
4206 write_exp_elt_opcode (&p
->pstate
, UNOP_CAST
);
4208 write_exp_elt_opcode (&p
->pstate
, BINOP_ADD
);
4209 write_exp_elt_opcode (&p
->pstate
, BINOP_ADD
);
4210 write_exp_elt_opcode (&p
->pstate
, BINOP_ADD
);
4212 write_exp_elt_opcode (&p
->pstate
, UNOP_CAST
);
4213 write_exp_elt_type (&p
->pstate
,
4214 lookup_pointer_type (p
->arg_type
));
4215 write_exp_elt_opcode (&p
->pstate
, UNOP_CAST
);
4217 write_exp_elt_opcode (&p
->pstate
, UNOP_IND
);
4227 /* Helper function for i386_stap_parse_special_token.
4229 This function parses operands of the form `register base +
4230 (register index * size) + offset', as represented in
4231 `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'.
4233 Return true if the operand was parsed successfully, false
4237 i386_stap_parse_special_token_three_arg_disp (struct gdbarch
*gdbarch
,
4238 struct stap_parse_info
*p
)
4240 const char *s
= p
->arg
;
4242 if (isdigit (*s
) || *s
== '(' || *s
== '-' || *s
== '+')
4244 bool offset_minus
= false;
4246 bool size_minus
= false;
4253 struct stoken base_token
, index_token
;
4260 offset_minus
= true;
4263 if (offset_minus
&& !isdigit (*s
))
4270 offset
= strtol (s
, &endp
, 10);
4274 if (*s
!= '(' || s
[1] != '%')
4280 while (isalnum (*s
))
4283 if (*s
!= ',' || s
[1] != '%')
4286 len_base
= s
- start
;
4287 base
= (char *) alloca (len_base
+ 1);
4288 strncpy (base
, start
, len_base
);
4289 base
[len_base
] = '\0';
4291 if (user_reg_map_name_to_regnum (gdbarch
, base
, len_base
) == -1)
4292 error (_("Invalid register name `%s' on expression `%s'."),
4293 base
, p
->saved_arg
);
4298 while (isalnum (*s
))
4301 len_index
= s
- start
;
4302 index
= (char *) alloca (len_index
+ 1);
4303 strncpy (index
, start
, len_index
);
4304 index
[len_index
] = '\0';
4306 if (user_reg_map_name_to_regnum (gdbarch
, index
, len_index
) == -1)
4307 error (_("Invalid register name `%s' on expression `%s'."),
4308 index
, p
->saved_arg
);
4310 if (*s
!= ',' && *s
!= ')')
4326 size
= strtol (s
, &endp
, 10);
4337 write_exp_elt_opcode (&p
->pstate
, OP_LONG
);
4338 write_exp_elt_type (&p
->pstate
,
4339 builtin_type (gdbarch
)->builtin_long
);
4340 write_exp_elt_longcst (&p
->pstate
, offset
);
4341 write_exp_elt_opcode (&p
->pstate
, OP_LONG
);
4343 write_exp_elt_opcode (&p
->pstate
, UNOP_NEG
);
4346 write_exp_elt_opcode (&p
->pstate
, OP_REGISTER
);
4347 base_token
.ptr
= base
;
4348 base_token
.length
= len_base
;
4349 write_exp_string (&p
->pstate
, base_token
);
4350 write_exp_elt_opcode (&p
->pstate
, OP_REGISTER
);
4353 write_exp_elt_opcode (&p
->pstate
, BINOP_ADD
);
4355 write_exp_elt_opcode (&p
->pstate
, OP_REGISTER
);
4356 index_token
.ptr
= index
;
4357 index_token
.length
= len_index
;
4358 write_exp_string (&p
->pstate
, index_token
);
4359 write_exp_elt_opcode (&p
->pstate
, OP_REGISTER
);
4363 write_exp_elt_opcode (&p
->pstate
, OP_LONG
);
4364 write_exp_elt_type (&p
->pstate
,
4365 builtin_type (gdbarch
)->builtin_long
);
4366 write_exp_elt_longcst (&p
->pstate
, size
);
4367 write_exp_elt_opcode (&p
->pstate
, OP_LONG
);
4369 write_exp_elt_opcode (&p
->pstate
, UNOP_NEG
);
4370 write_exp_elt_opcode (&p
->pstate
, BINOP_MUL
);
4373 write_exp_elt_opcode (&p
->pstate
, BINOP_ADD
);
4375 write_exp_elt_opcode (&p
->pstate
, UNOP_CAST
);
4376 write_exp_elt_type (&p
->pstate
,
4377 lookup_pointer_type (p
->arg_type
));
4378 write_exp_elt_opcode (&p
->pstate
, UNOP_CAST
);
4380 write_exp_elt_opcode (&p
->pstate
, UNOP_IND
);
4390 /* Implementation of `gdbarch_stap_parse_special_token', as defined in
4394 i386_stap_parse_special_token (struct gdbarch
*gdbarch
,
4395 struct stap_parse_info
*p
)
4397 /* In order to parse special tokens, we use a state-machine that go
4398 through every known token and try to get a match. */
4402 THREE_ARG_DISPLACEMENT
,
4407 current_state
= TRIPLET
;
4409 /* The special tokens to be parsed here are:
4411 - `register base + (register index * size) + offset', as represented
4412 in `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'.
4414 - Operands of the form `-8+3+1(%rbp)', which must be interpreted as
4415 `*(-8 + 3 - 1 + (void *) $eax)'. */
4417 while (current_state
!= DONE
)
4419 switch (current_state
)
4422 if (i386_stap_parse_special_token_triplet (gdbarch
, p
))
4426 case THREE_ARG_DISPLACEMENT
:
4427 if (i386_stap_parse_special_token_three_arg_disp (gdbarch
, p
))
4432 /* Advancing to the next state. */
4439 /* Implementation of 'gdbarch_stap_adjust_register', as defined in
4443 i386_stap_adjust_register (struct gdbarch
*gdbarch
, struct stap_parse_info
*p
,
4444 const std::string
®name
, int regnum
)
4446 static const std::unordered_set
<std::string
> reg_assoc
4447 = { "ax", "bx", "cx", "dx",
4448 "si", "di", "bp", "sp" };
4450 /* If we are dealing with a register whose size is less than the size
4451 specified by the "[-]N@" prefix, and it is one of the registers that
4452 we know has an extended variant available, then use the extended
4453 version of the register instead. */
4454 if (register_size (gdbarch
, regnum
) < TYPE_LENGTH (p
->arg_type
)
4455 && reg_assoc
.find (regname
) != reg_assoc
.end ())
4456 return "e" + regname
;
4458 /* Otherwise, just use the requested register. */
4464 /* gdbarch gnu_triplet_regexp method. Both arches are acceptable as GDB always
4465 also supplies -m64 or -m32 by gdbarch_gcc_target_options. */
4468 i386_gnu_triplet_regexp (struct gdbarch
*gdbarch
)
4470 return "(x86_64|i.86)";
4475 /* Implement the "in_indirect_branch_thunk" gdbarch function. */
4478 i386_in_indirect_branch_thunk (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4480 return x86_in_indirect_branch_thunk (pc
, i386_register_names
,
4481 I386_EAX_REGNUM
, I386_EIP_REGNUM
);
4487 i386_elf_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
4489 static const char *const stap_integer_prefixes
[] = { "$", NULL
};
4490 static const char *const stap_register_prefixes
[] = { "%", NULL
};
4491 static const char *const stap_register_indirection_prefixes
[] = { "(",
4493 static const char *const stap_register_indirection_suffixes
[] = { ")",
4496 /* We typically use stabs-in-ELF with the SVR4 register numbering. */
4497 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
4499 /* Registering SystemTap handlers. */
4500 set_gdbarch_stap_integer_prefixes (gdbarch
, stap_integer_prefixes
);
4501 set_gdbarch_stap_register_prefixes (gdbarch
, stap_register_prefixes
);
4502 set_gdbarch_stap_register_indirection_prefixes (gdbarch
,
4503 stap_register_indirection_prefixes
);
4504 set_gdbarch_stap_register_indirection_suffixes (gdbarch
,
4505 stap_register_indirection_suffixes
);
4506 set_gdbarch_stap_is_single_operand (gdbarch
,
4507 i386_stap_is_single_operand
);
4508 set_gdbarch_stap_parse_special_token (gdbarch
,
4509 i386_stap_parse_special_token
);
4510 set_gdbarch_stap_adjust_register (gdbarch
,
4511 i386_stap_adjust_register
);
4513 set_gdbarch_in_indirect_branch_thunk (gdbarch
,
4514 i386_in_indirect_branch_thunk
);
4517 /* System V Release 4 (SVR4). */
4520 i386_svr4_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
4522 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4524 /* System V Release 4 uses ELF. */
4525 i386_elf_init_abi (info
, gdbarch
);
4527 /* System V Release 4 has shared libraries. */
4528 set_gdbarch_skip_trampoline_code (gdbarch
, find_solib_trampoline_target
);
4530 tdep
->sigtramp_p
= i386_svr4_sigtramp_p
;
4531 tdep
->sigcontext_addr
= i386_svr4_sigcontext_addr
;
4532 tdep
->sc_pc_offset
= 36 + 14 * 4;
4533 tdep
->sc_sp_offset
= 36 + 17 * 4;
4535 tdep
->jb_pc_offset
= 20;
4540 /* i386 register groups. In addition to the normal groups, add "mmx"
4543 static struct reggroup
*i386_sse_reggroup
;
4544 static struct reggroup
*i386_mmx_reggroup
;
4547 i386_init_reggroups (void)
4549 i386_sse_reggroup
= reggroup_new ("sse", USER_REGGROUP
);
4550 i386_mmx_reggroup
= reggroup_new ("mmx", USER_REGGROUP
);
4554 i386_add_reggroups (struct gdbarch
*gdbarch
)
4556 reggroup_add (gdbarch
, i386_sse_reggroup
);
4557 reggroup_add (gdbarch
, i386_mmx_reggroup
);
4558 reggroup_add (gdbarch
, general_reggroup
);
4559 reggroup_add (gdbarch
, float_reggroup
);
4560 reggroup_add (gdbarch
, all_reggroup
);
4561 reggroup_add (gdbarch
, save_reggroup
);
4562 reggroup_add (gdbarch
, restore_reggroup
);
4563 reggroup_add (gdbarch
, vector_reggroup
);
4564 reggroup_add (gdbarch
, system_reggroup
);
4568 i386_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
4569 struct reggroup
*group
)
4571 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4572 int fp_regnum_p
, mmx_regnum_p
, xmm_regnum_p
, mxcsr_regnum_p
,
4573 ymm_regnum_p
, ymmh_regnum_p
, ymm_avx512_regnum_p
, ymmh_avx512_regnum_p
,
4574 bndr_regnum_p
, bnd_regnum_p
, zmm_regnum_p
, zmmh_regnum_p
,
4575 mpx_ctrl_regnum_p
, xmm_avx512_regnum_p
,
4576 avx512_p
, avx_p
, sse_p
, pkru_regnum_p
;
4578 /* Don't include pseudo registers, except for MMX, in any register
4580 if (i386_byte_regnum_p (gdbarch
, regnum
))
4583 if (i386_word_regnum_p (gdbarch
, regnum
))
4586 if (i386_dword_regnum_p (gdbarch
, regnum
))
4589 mmx_regnum_p
= i386_mmx_regnum_p (gdbarch
, regnum
);
4590 if (group
== i386_mmx_reggroup
)
4591 return mmx_regnum_p
;
4593 pkru_regnum_p
= i386_pkru_regnum_p(gdbarch
, regnum
);
4594 xmm_regnum_p
= i386_xmm_regnum_p (gdbarch
, regnum
);
4595 xmm_avx512_regnum_p
= i386_xmm_avx512_regnum_p (gdbarch
, regnum
);
4596 mxcsr_regnum_p
= i386_mxcsr_regnum_p (gdbarch
, regnum
);
4597 if (group
== i386_sse_reggroup
)
4598 return xmm_regnum_p
|| xmm_avx512_regnum_p
|| mxcsr_regnum_p
;
4600 ymm_regnum_p
= i386_ymm_regnum_p (gdbarch
, regnum
);
4601 ymm_avx512_regnum_p
= i386_ymm_avx512_regnum_p (gdbarch
, regnum
);
4602 zmm_regnum_p
= i386_zmm_regnum_p (gdbarch
, regnum
);
4604 avx512_p
= ((tdep
->xcr0
& X86_XSTATE_AVX_AVX512_MASK
)
4605 == X86_XSTATE_AVX_AVX512_MASK
);
4606 avx_p
= ((tdep
->xcr0
& X86_XSTATE_AVX_AVX512_MASK
)
4607 == X86_XSTATE_AVX_MASK
) && !avx512_p
;
4608 sse_p
= ((tdep
->xcr0
& X86_XSTATE_AVX_AVX512_MASK
)
4609 == X86_XSTATE_SSE_MASK
) && !avx512_p
&& ! avx_p
;
4611 if (group
== vector_reggroup
)
4612 return (mmx_regnum_p
4613 || (zmm_regnum_p
&& avx512_p
)
4614 || ((ymm_regnum_p
|| ymm_avx512_regnum_p
) && avx_p
)
4615 || ((xmm_regnum_p
|| xmm_avx512_regnum_p
) && sse_p
)
4618 fp_regnum_p
= (i386_fp_regnum_p (gdbarch
, regnum
)
4619 || i386_fpc_regnum_p (gdbarch
, regnum
));
4620 if (group
== float_reggroup
)
4623 /* For "info reg all", don't include upper YMM registers nor XMM
4624 registers when AVX is supported. */
4625 ymmh_regnum_p
= i386_ymmh_regnum_p (gdbarch
, regnum
);
4626 ymmh_avx512_regnum_p
= i386_ymmh_avx512_regnum_p (gdbarch
, regnum
);
4627 zmmh_regnum_p
= i386_zmmh_regnum_p (gdbarch
, regnum
);
4628 if (group
== all_reggroup
4629 && (((xmm_regnum_p
|| xmm_avx512_regnum_p
) && !sse_p
)
4630 || ((ymm_regnum_p
|| ymm_avx512_regnum_p
) && !avx_p
)
4632 || ymmh_avx512_regnum_p
4636 bnd_regnum_p
= i386_bnd_regnum_p (gdbarch
, regnum
);
4637 if (group
== all_reggroup
4638 && ((bnd_regnum_p
&& (tdep
->xcr0
& X86_XSTATE_MPX_MASK
))))
4639 return bnd_regnum_p
;
4641 bndr_regnum_p
= i386_bndr_regnum_p (gdbarch
, regnum
);
4642 if (group
== all_reggroup
4643 && ((bndr_regnum_p
&& (tdep
->xcr0
& X86_XSTATE_MPX_MASK
))))
4646 mpx_ctrl_regnum_p
= i386_mpx_ctrl_regnum_p (gdbarch
, regnum
);
4647 if (group
== all_reggroup
4648 && ((mpx_ctrl_regnum_p
&& (tdep
->xcr0
& X86_XSTATE_MPX_MASK
))))
4649 return mpx_ctrl_regnum_p
;
4651 if (group
== general_reggroup
)
4652 return (!fp_regnum_p
4656 && !xmm_avx512_regnum_p
4659 && !ymm_avx512_regnum_p
4660 && !ymmh_avx512_regnum_p
4663 && !mpx_ctrl_regnum_p
4668 return default_register_reggroup_p (gdbarch
, regnum
, group
);
4672 /* Get the ARGIth function argument for the current function. */
4675 i386_fetch_pointer_argument (struct frame_info
*frame
, int argi
,
4678 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4679 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4680 CORE_ADDR sp
= get_frame_register_unsigned (frame
, I386_ESP_REGNUM
);
4681 return read_memory_unsigned_integer (sp
+ (4 * (argi
+ 1)), 4, byte_order
);
4684 #define PREFIX_REPZ 0x01
4685 #define PREFIX_REPNZ 0x02
4686 #define PREFIX_LOCK 0x04
4687 #define PREFIX_DATA 0x08
4688 #define PREFIX_ADDR 0x10
4700 /* i386 arith/logic operations */
4713 struct i386_record_s
4715 struct gdbarch
*gdbarch
;
4716 struct regcache
*regcache
;
4717 CORE_ADDR orig_addr
;
4723 uint8_t mod
, reg
, rm
;
4732 /* Parse the "modrm" part of the memory address irp->addr points at.
4733 Returns -1 if something goes wrong, 0 otherwise. */
4736 i386_record_modrm (struct i386_record_s
*irp
)
4738 struct gdbarch
*gdbarch
= irp
->gdbarch
;
4740 if (record_read_memory (gdbarch
, irp
->addr
, &irp
->modrm
, 1))
4744 irp
->mod
= (irp
->modrm
>> 6) & 3;
4745 irp
->reg
= (irp
->modrm
>> 3) & 7;
4746 irp
->rm
= irp
->modrm
& 7;
4751 /* Extract the memory address that the current instruction writes to,
4752 and return it in *ADDR. Return -1 if something goes wrong. */
4755 i386_record_lea_modrm_addr (struct i386_record_s
*irp
, uint64_t *addr
)
4757 struct gdbarch
*gdbarch
= irp
->gdbarch
;
4758 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4763 if (irp
->aflag
|| irp
->regmap
[X86_RECORD_R8_REGNUM
])
4770 uint8_t base
= irp
->rm
;
4775 if (record_read_memory (gdbarch
, irp
->addr
, &byte
, 1))
4778 scale
= (byte
>> 6) & 3;
4779 index
= ((byte
>> 3) & 7) | irp
->rex_x
;
4787 if ((base
& 7) == 5)
4790 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 4))
4793 *addr
= extract_signed_integer (buf
, 4, byte_order
);
4794 if (irp
->regmap
[X86_RECORD_R8_REGNUM
] && !havesib
)
4795 *addr
+= irp
->addr
+ irp
->rip_offset
;
4799 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 1))
4802 *addr
= (int8_t) buf
[0];
4805 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 4))
4807 *addr
= extract_signed_integer (buf
, 4, byte_order
);
4815 if (base
== 4 && irp
->popl_esp_hack
)
4816 *addr
+= irp
->popl_esp_hack
;
4817 regcache_raw_read_unsigned (irp
->regcache
, irp
->regmap
[base
],
4820 if (irp
->aflag
== 2)
4825 *addr
= (uint32_t) (offset64
+ *addr
);
4827 if (havesib
&& (index
!= 4 || scale
!= 0))
4829 regcache_raw_read_unsigned (irp
->regcache
, irp
->regmap
[index
],
4831 if (irp
->aflag
== 2)
4832 *addr
+= offset64
<< scale
;
4834 *addr
= (uint32_t) (*addr
+ (offset64
<< scale
));
4839 /* Since we are in 64-bit mode with ADDR32 prefix, zero-extend
4840 address from 32-bit to 64-bit. */
4841 *addr
= (uint32_t) *addr
;
4852 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 2))
4855 *addr
= extract_signed_integer (buf
, 2, byte_order
);
4861 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 1))
4864 *addr
= (int8_t) buf
[0];
4867 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 2))
4870 *addr
= extract_signed_integer (buf
, 2, byte_order
);
4877 regcache_raw_read_unsigned (irp
->regcache
,
4878 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
4880 *addr
= (uint32_t) (*addr
+ offset64
);
4881 regcache_raw_read_unsigned (irp
->regcache
,
4882 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
4884 *addr
= (uint32_t) (*addr
+ offset64
);
4887 regcache_raw_read_unsigned (irp
->regcache
,
4888 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
4890 *addr
= (uint32_t) (*addr
+ offset64
);
4891 regcache_raw_read_unsigned (irp
->regcache
,
4892 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
4894 *addr
= (uint32_t) (*addr
+ offset64
);
4897 regcache_raw_read_unsigned (irp
->regcache
,
4898 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
4900 *addr
= (uint32_t) (*addr
+ offset64
);
4901 regcache_raw_read_unsigned (irp
->regcache
,
4902 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
4904 *addr
= (uint32_t) (*addr
+ offset64
);
4907 regcache_raw_read_unsigned (irp
->regcache
,
4908 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
4910 *addr
= (uint32_t) (*addr
+ offset64
);
4911 regcache_raw_read_unsigned (irp
->regcache
,
4912 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
4914 *addr
= (uint32_t) (*addr
+ offset64
);
4917 regcache_raw_read_unsigned (irp
->regcache
,
4918 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
4920 *addr
= (uint32_t) (*addr
+ offset64
);
4923 regcache_raw_read_unsigned (irp
->regcache
,
4924 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
4926 *addr
= (uint32_t) (*addr
+ offset64
);
4929 regcache_raw_read_unsigned (irp
->regcache
,
4930 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
4932 *addr
= (uint32_t) (*addr
+ offset64
);
4935 regcache_raw_read_unsigned (irp
->regcache
,
4936 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
4938 *addr
= (uint32_t) (*addr
+ offset64
);
4948 /* Record the address and contents of the memory that will be changed
4949 by the current instruction. Return -1 if something goes wrong, 0
4953 i386_record_lea_modrm (struct i386_record_s
*irp
)
4955 struct gdbarch
*gdbarch
= irp
->gdbarch
;
4958 if (irp
->override
>= 0)
4960 if (record_full_memory_query
)
4963 Process record ignores the memory change of instruction at address %s\n\
4964 because it can't get the value of the segment register.\n\
4965 Do you want to stop the program?"),
4966 paddress (gdbarch
, irp
->orig_addr
)))
4973 if (i386_record_lea_modrm_addr (irp
, &addr
))
4976 if (record_full_arch_list_add_mem (addr
, 1 << irp
->ot
))
4982 /* Record the effects of a push operation. Return -1 if something
4983 goes wrong, 0 otherwise. */
4986 i386_record_push (struct i386_record_s
*irp
, int size
)
4990 if (record_full_arch_list_add_reg (irp
->regcache
,
4991 irp
->regmap
[X86_RECORD_RESP_REGNUM
]))
4993 regcache_raw_read_unsigned (irp
->regcache
,
4994 irp
->regmap
[X86_RECORD_RESP_REGNUM
],
4996 if (record_full_arch_list_add_mem ((CORE_ADDR
) addr
- size
, size
))
5003 /* Defines contents to record. */
5004 #define I386_SAVE_FPU_REGS 0xfffd
5005 #define I386_SAVE_FPU_ENV 0xfffe
5006 #define I386_SAVE_FPU_ENV_REG_STACK 0xffff
5008 /* Record the values of the floating point registers which will be
5009 changed by the current instruction. Returns -1 if something is
5010 wrong, 0 otherwise. */
5012 static int i386_record_floats (struct gdbarch
*gdbarch
,
5013 struct i386_record_s
*ir
,
5016 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5019 /* Oza: Because of floating point insn push/pop of fpu stack is going to
5020 happen. Currently we store st0-st7 registers, but we need not store all
5021 registers all the time, in future we use ftag register and record only
5022 those who are not marked as an empty. */
5024 if (I386_SAVE_FPU_REGS
== iregnum
)
5026 for (i
= I387_ST0_REGNUM (tdep
); i
<= I387_ST0_REGNUM (tdep
) + 7; i
++)
5028 if (record_full_arch_list_add_reg (ir
->regcache
, i
))
5032 else if (I386_SAVE_FPU_ENV
== iregnum
)
5034 for (i
= I387_FCTRL_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
5036 if (record_full_arch_list_add_reg (ir
->regcache
, i
))
5040 else if (I386_SAVE_FPU_ENV_REG_STACK
== iregnum
)
5042 for (i
= I387_ST0_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
5044 if (record_full_arch_list_add_reg (ir
->regcache
, i
))
5048 else if ((iregnum
>= I387_ST0_REGNUM (tdep
)) &&
5049 (iregnum
<= I387_FOP_REGNUM (tdep
)))
5051 if (record_full_arch_list_add_reg (ir
->regcache
,iregnum
))
5056 /* Parameter error. */
5059 if(I386_SAVE_FPU_ENV
!= iregnum
)
5061 for (i
= I387_FCTRL_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
5063 if (record_full_arch_list_add_reg (ir
->regcache
, i
))
5070 /* Parse the current instruction, and record the values of the
5071 registers and memory that will be changed by the current
5072 instruction. Returns -1 if something goes wrong, 0 otherwise. */
5074 #define I386_RECORD_FULL_ARCH_LIST_ADD_REG(regnum) \
5075 record_full_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)])
5078 i386_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5079 CORE_ADDR input_addr
)
5081 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5087 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
5088 struct i386_record_s ir
;
5089 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5093 memset (&ir
, 0, sizeof (struct i386_record_s
));
5094 ir
.regcache
= regcache
;
5095 ir
.addr
= input_addr
;
5096 ir
.orig_addr
= input_addr
;
5100 ir
.popl_esp_hack
= 0;
5101 ir
.regmap
= tdep
->record_regmap
;
5102 ir
.gdbarch
= gdbarch
;
5104 if (record_debug
> 1)
5105 fprintf_unfiltered (gdb_stdlog
, "Process record: i386_process_record "
5107 paddress (gdbarch
, ir
.addr
));
5112 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
5115 switch (opcode8
) /* Instruction prefixes */
5117 case REPE_PREFIX_OPCODE
:
5118 prefixes
|= PREFIX_REPZ
;
5120 case REPNE_PREFIX_OPCODE
:
5121 prefixes
|= PREFIX_REPNZ
;
5123 case LOCK_PREFIX_OPCODE
:
5124 prefixes
|= PREFIX_LOCK
;
5126 case CS_PREFIX_OPCODE
:
5127 ir
.override
= X86_RECORD_CS_REGNUM
;
5129 case SS_PREFIX_OPCODE
:
5130 ir
.override
= X86_RECORD_SS_REGNUM
;
5132 case DS_PREFIX_OPCODE
:
5133 ir
.override
= X86_RECORD_DS_REGNUM
;
5135 case ES_PREFIX_OPCODE
:
5136 ir
.override
= X86_RECORD_ES_REGNUM
;
5138 case FS_PREFIX_OPCODE
:
5139 ir
.override
= X86_RECORD_FS_REGNUM
;
5141 case GS_PREFIX_OPCODE
:
5142 ir
.override
= X86_RECORD_GS_REGNUM
;
5144 case DATA_PREFIX_OPCODE
:
5145 prefixes
|= PREFIX_DATA
;
5147 case ADDR_PREFIX_OPCODE
:
5148 prefixes
|= PREFIX_ADDR
;
5150 case 0x40: /* i386 inc %eax */
5151 case 0x41: /* i386 inc %ecx */
5152 case 0x42: /* i386 inc %edx */
5153 case 0x43: /* i386 inc %ebx */
5154 case 0x44: /* i386 inc %esp */
5155 case 0x45: /* i386 inc %ebp */
5156 case 0x46: /* i386 inc %esi */
5157 case 0x47: /* i386 inc %edi */
5158 case 0x48: /* i386 dec %eax */
5159 case 0x49: /* i386 dec %ecx */
5160 case 0x4a: /* i386 dec %edx */
5161 case 0x4b: /* i386 dec %ebx */
5162 case 0x4c: /* i386 dec %esp */
5163 case 0x4d: /* i386 dec %ebp */
5164 case 0x4e: /* i386 dec %esi */
5165 case 0x4f: /* i386 dec %edi */
5166 if (ir
.regmap
[X86_RECORD_R8_REGNUM
]) /* 64 bit target */
5169 rex_w
= (opcode8
>> 3) & 1;
5170 rex_r
= (opcode8
& 0x4) << 1;
5171 ir
.rex_x
= (opcode8
& 0x2) << 2;
5172 ir
.rex_b
= (opcode8
& 0x1) << 3;
5174 else /* 32 bit target */
5183 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && rex_w
== 1)
5189 if (prefixes
& PREFIX_DATA
)
5192 if (prefixes
& PREFIX_ADDR
)
5194 else if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5197 /* Now check op code. */
5198 opcode
= (uint32_t) opcode8
;
5203 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
5206 opcode
= (uint32_t) opcode8
| 0x0f00;
5210 case 0x00: /* arith & logic */
5258 if (((opcode
>> 3) & 7) != OP_CMPL
)
5260 if ((opcode
& 1) == 0)
5263 ir
.ot
= ir
.dflag
+ OT_WORD
;
5265 switch ((opcode
>> 1) & 3)
5267 case 0: /* OP Ev, Gv */
5268 if (i386_record_modrm (&ir
))
5272 if (i386_record_lea_modrm (&ir
))
5278 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5280 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5283 case 1: /* OP Gv, Ev */
5284 if (i386_record_modrm (&ir
))
5287 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5289 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5291 case 2: /* OP A, Iv */
5292 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5296 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5299 case 0x80: /* GRP1 */
5303 if (i386_record_modrm (&ir
))
5306 if (ir
.reg
!= OP_CMPL
)
5308 if ((opcode
& 1) == 0)
5311 ir
.ot
= ir
.dflag
+ OT_WORD
;
5318 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
5319 if (i386_record_lea_modrm (&ir
))
5323 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5325 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5328 case 0x40: /* inc */
5337 case 0x48: /* dec */
5346 I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode
& 7);
5347 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5350 case 0xf6: /* GRP3 */
5352 if ((opcode
& 1) == 0)
5355 ir
.ot
= ir
.dflag
+ OT_WORD
;
5356 if (i386_record_modrm (&ir
))
5359 if (ir
.mod
!= 3 && ir
.reg
== 0)
5360 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
5365 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5371 if (i386_record_lea_modrm (&ir
))
5377 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5379 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5381 if (ir
.reg
== 3) /* neg */
5382 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5388 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5389 if (ir
.ot
!= OT_BYTE
)
5390 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5391 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5395 opcode
= opcode
<< 8 | ir
.modrm
;
5401 case 0xfe: /* GRP4 */
5402 case 0xff: /* GRP5 */
5403 if (i386_record_modrm (&ir
))
5405 if (ir
.reg
>= 2 && opcode
== 0xfe)
5408 opcode
= opcode
<< 8 | ir
.modrm
;
5415 if ((opcode
& 1) == 0)
5418 ir
.ot
= ir
.dflag
+ OT_WORD
;
5421 if (i386_record_lea_modrm (&ir
))
5427 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5429 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5431 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5434 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5436 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5438 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5441 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
5442 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5444 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5448 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5451 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5453 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5458 opcode
= opcode
<< 8 | ir
.modrm
;
5464 case 0x84: /* test */
5468 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5471 case 0x98: /* CWDE/CBW */
5472 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5475 case 0x99: /* CDQ/CWD */
5476 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5477 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5480 case 0x0faf: /* imul */
5483 ir
.ot
= ir
.dflag
+ OT_WORD
;
5484 if (i386_record_modrm (&ir
))
5487 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
5488 else if (opcode
== 0x6b)
5491 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5493 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5494 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5497 case 0x0fc0: /* xadd */
5499 if ((opcode
& 1) == 0)
5502 ir
.ot
= ir
.dflag
+ OT_WORD
;
5503 if (i386_record_modrm (&ir
))
5508 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5510 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5511 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5513 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5517 if (i386_record_lea_modrm (&ir
))
5519 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5521 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5523 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5526 case 0x0fb0: /* cmpxchg */
5528 if ((opcode
& 1) == 0)
5531 ir
.ot
= ir
.dflag
+ OT_WORD
;
5532 if (i386_record_modrm (&ir
))
5537 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5538 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5540 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5544 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5545 if (i386_record_lea_modrm (&ir
))
5548 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5551 case 0x0fc7: /* cmpxchg8b / rdrand / rdseed */
5552 if (i386_record_modrm (&ir
))
5556 /* rdrand and rdseed use the 3 bits of the REG field of ModR/M as
5557 an extended opcode. rdrand has bits 110 (/6) and rdseed
5558 has bits 111 (/7). */
5559 if (ir
.reg
== 6 || ir
.reg
== 7)
5561 /* The storage register is described by the 3 R/M bits, but the
5562 REX.B prefix may be used to give access to registers
5563 R8~R15. In this case ir.rex_b + R/M will give us the register
5564 in the range R8~R15.
5566 REX.W may also be used to access 64-bit registers, but we
5567 already record entire registers and not just partial bits
5569 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rex_b
+ ir
.rm
);
5570 /* These instructions also set conditional bits. */
5571 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5576 /* We don't handle this particular instruction yet. */
5578 opcode
= opcode
<< 8 | ir
.modrm
;
5582 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5583 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5584 if (i386_record_lea_modrm (&ir
))
5586 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5589 case 0x50: /* push */
5599 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5601 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5605 case 0x06: /* push es */
5606 case 0x0e: /* push cs */
5607 case 0x16: /* push ss */
5608 case 0x1e: /* push ds */
5609 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5614 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5618 case 0x0fa0: /* push fs */
5619 case 0x0fa8: /* push gs */
5620 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5625 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5629 case 0x60: /* pusha */
5630 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5635 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 4)))
5639 case 0x58: /* pop */
5647 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5648 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode
& 0x7) | ir
.rex_b
);
5651 case 0x61: /* popa */
5652 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5657 for (regnum
= X86_RECORD_REAX_REGNUM
;
5658 regnum
<= X86_RECORD_REDI_REGNUM
;
5660 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum
);
5663 case 0x8f: /* pop */
5664 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5665 ir
.ot
= ir
.dflag
? OT_QUAD
: OT_WORD
;
5667 ir
.ot
= ir
.dflag
+ OT_WORD
;
5668 if (i386_record_modrm (&ir
))
5671 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5674 ir
.popl_esp_hack
= 1 << ir
.ot
;
5675 if (i386_record_lea_modrm (&ir
))
5678 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5681 case 0xc8: /* enter */
5682 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
5683 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5685 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5689 case 0xc9: /* leave */
5690 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5691 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
5694 case 0x07: /* pop es */
5695 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5700 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5701 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM
);
5702 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5705 case 0x17: /* pop ss */
5706 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5711 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5712 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM
);
5713 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5716 case 0x1f: /* pop ds */
5717 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5722 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5723 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM
);
5724 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5727 case 0x0fa1: /* pop fs */
5728 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5729 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM
);
5730 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5733 case 0x0fa9: /* pop gs */
5734 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5735 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM
);
5736 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5739 case 0x88: /* mov */
5743 if ((opcode
& 1) == 0)
5746 ir
.ot
= ir
.dflag
+ OT_WORD
;
5748 if (i386_record_modrm (&ir
))
5753 if (opcode
== 0xc6 || opcode
== 0xc7)
5754 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
5755 if (i386_record_lea_modrm (&ir
))
5760 if (opcode
== 0xc6 || opcode
== 0xc7)
5762 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5764 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5768 case 0x8a: /* mov */
5770 if ((opcode
& 1) == 0)
5773 ir
.ot
= ir
.dflag
+ OT_WORD
;
5774 if (i386_record_modrm (&ir
))
5777 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5779 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5782 case 0x8c: /* mov seg */
5783 if (i386_record_modrm (&ir
))
5788 opcode
= opcode
<< 8 | ir
.modrm
;
5793 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5797 if (i386_record_lea_modrm (&ir
))
5802 case 0x8e: /* mov seg */
5803 if (i386_record_modrm (&ir
))
5808 regnum
= X86_RECORD_ES_REGNUM
;
5811 regnum
= X86_RECORD_SS_REGNUM
;
5814 regnum
= X86_RECORD_DS_REGNUM
;
5817 regnum
= X86_RECORD_FS_REGNUM
;
5820 regnum
= X86_RECORD_GS_REGNUM
;
5824 opcode
= opcode
<< 8 | ir
.modrm
;
5828 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum
);
5829 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5832 case 0x0fb6: /* movzbS */
5833 case 0x0fb7: /* movzwS */
5834 case 0x0fbe: /* movsbS */
5835 case 0x0fbf: /* movswS */
5836 if (i386_record_modrm (&ir
))
5838 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
5841 case 0x8d: /* lea */
5842 if (i386_record_modrm (&ir
))
5847 opcode
= opcode
<< 8 | ir
.modrm
;
5852 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5854 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5857 case 0xa0: /* mov EAX */
5860 case 0xd7: /* xlat */
5861 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5864 case 0xa2: /* mov EAX */
5866 if (ir
.override
>= 0)
5868 if (record_full_memory_query
)
5871 Process record ignores the memory change of instruction at address %s\n\
5872 because it can't get the value of the segment register.\n\
5873 Do you want to stop the program?"),
5874 paddress (gdbarch
, ir
.orig_addr
)))
5880 if ((opcode
& 1) == 0)
5883 ir
.ot
= ir
.dflag
+ OT_WORD
;
5886 if (record_read_memory (gdbarch
, ir
.addr
, buf
, 8))
5889 addr
= extract_unsigned_integer (buf
, 8, byte_order
);
5893 if (record_read_memory (gdbarch
, ir
.addr
, buf
, 4))
5896 addr
= extract_unsigned_integer (buf
, 4, byte_order
);
5900 if (record_read_memory (gdbarch
, ir
.addr
, buf
, 2))
5903 addr
= extract_unsigned_integer (buf
, 2, byte_order
);
5905 if (record_full_arch_list_add_mem (addr
, 1 << ir
.ot
))
5910 case 0xb0: /* mov R, Ib */
5918 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((ir
.regmap
[X86_RECORD_R8_REGNUM
])
5919 ? ((opcode
& 0x7) | ir
.rex_b
)
5920 : ((opcode
& 0x7) & 0x3));
5923 case 0xb8: /* mov R, Iv */
5931 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode
& 0x7) | ir
.rex_b
);
5934 case 0x91: /* xchg R, EAX */
5941 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5942 I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode
& 0x7);
5945 case 0x86: /* xchg Ev, Gv */
5947 if ((opcode
& 1) == 0)
5950 ir
.ot
= ir
.dflag
+ OT_WORD
;
5951 if (i386_record_modrm (&ir
))
5956 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5958 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5962 if (i386_record_lea_modrm (&ir
))
5966 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5968 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5971 case 0xc4: /* les Gv */
5972 case 0xc5: /* lds Gv */
5973 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5979 case 0x0fb2: /* lss Gv */
5980 case 0x0fb4: /* lfs Gv */
5981 case 0x0fb5: /* lgs Gv */
5982 if (i386_record_modrm (&ir
))
5990 opcode
= opcode
<< 8 | ir
.modrm
;
5995 case 0xc4: /* les Gv */
5996 regnum
= X86_RECORD_ES_REGNUM
;
5998 case 0xc5: /* lds Gv */
5999 regnum
= X86_RECORD_DS_REGNUM
;
6001 case 0x0fb2: /* lss Gv */
6002 regnum
= X86_RECORD_SS_REGNUM
;
6004 case 0x0fb4: /* lfs Gv */
6005 regnum
= X86_RECORD_FS_REGNUM
;
6007 case 0x0fb5: /* lgs Gv */
6008 regnum
= X86_RECORD_GS_REGNUM
;
6011 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum
);
6012 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
6013 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6016 case 0xc0: /* shifts */
6022 if ((opcode
& 1) == 0)
6025 ir
.ot
= ir
.dflag
+ OT_WORD
;
6026 if (i386_record_modrm (&ir
))
6028 if (ir
.mod
!= 3 && (opcode
== 0xd2 || opcode
== 0xd3))
6030 if (i386_record_lea_modrm (&ir
))
6036 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
6038 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
6040 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6047 if (i386_record_modrm (&ir
))
6051 if (record_full_arch_list_add_reg (ir
.regcache
, ir
.rm
))
6056 if (i386_record_lea_modrm (&ir
))
6061 case 0xd8: /* Floats. */
6069 if (i386_record_modrm (&ir
))
6071 ir
.reg
|= ((opcode
& 7) << 3);
6077 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
6085 /* For fcom, ficom nothing to do. */
6091 /* For fcomp, ficomp pop FPU stack, store all. */
6092 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
6119 /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul,
6120 fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension
6121 of code, always affects st(0) register. */
6122 if (i386_record_floats (gdbarch
, &ir
, I387_ST0_REGNUM (tdep
)))
6146 /* Handling fld, fild. */
6147 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
6151 switch (ir
.reg
>> 4)
6154 if (record_full_arch_list_add_mem (addr64
, 4))
6158 if (record_full_arch_list_add_mem (addr64
, 8))
6164 if (record_full_arch_list_add_mem (addr64
, 2))
6170 switch (ir
.reg
>> 4)
6173 if (record_full_arch_list_add_mem (addr64
, 4))
6175 if (3 == (ir
.reg
& 7))
6177 /* For fstp m32fp. */
6178 if (i386_record_floats (gdbarch
, &ir
,
6179 I386_SAVE_FPU_REGS
))
6184 if (record_full_arch_list_add_mem (addr64
, 4))
6186 if ((3 == (ir
.reg
& 7))
6187 || (5 == (ir
.reg
& 7))
6188 || (7 == (ir
.reg
& 7)))
6190 /* For fstp insn. */
6191 if (i386_record_floats (gdbarch
, &ir
,
6192 I386_SAVE_FPU_REGS
))
6197 if (record_full_arch_list_add_mem (addr64
, 8))
6199 if (3 == (ir
.reg
& 7))
6201 /* For fstp m64fp. */
6202 if (i386_record_floats (gdbarch
, &ir
,
6203 I386_SAVE_FPU_REGS
))
6208 if ((3 <= (ir
.reg
& 7)) && (6 <= (ir
.reg
& 7)))
6210 /* For fistp, fbld, fild, fbstp. */
6211 if (i386_record_floats (gdbarch
, &ir
,
6212 I386_SAVE_FPU_REGS
))
6217 if (record_full_arch_list_add_mem (addr64
, 2))
6226 if (i386_record_floats (gdbarch
, &ir
,
6227 I386_SAVE_FPU_ENV_REG_STACK
))
6232 if (i386_record_floats (gdbarch
, &ir
, I387_FCTRL_REGNUM (tdep
)))
6237 if (i386_record_floats (gdbarch
, &ir
,
6238 I386_SAVE_FPU_ENV_REG_STACK
))
6244 if (record_full_arch_list_add_mem (addr64
, 28))
6249 if (record_full_arch_list_add_mem (addr64
, 14))
6255 if (record_full_arch_list_add_mem (addr64
, 2))
6257 /* Insn fstp, fbstp. */
6258 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
6263 if (record_full_arch_list_add_mem (addr64
, 10))
6269 if (record_full_arch_list_add_mem (addr64
, 28))
6275 if (record_full_arch_list_add_mem (addr64
, 14))
6279 if (record_full_arch_list_add_mem (addr64
, 80))
6282 if (i386_record_floats (gdbarch
, &ir
,
6283 I386_SAVE_FPU_ENV_REG_STACK
))
6287 if (record_full_arch_list_add_mem (addr64
, 8))
6290 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
6295 opcode
= opcode
<< 8 | ir
.modrm
;
6300 /* Opcode is an extension of modR/M byte. */
6306 if (i386_record_floats (gdbarch
, &ir
, I387_ST0_REGNUM (tdep
)))
6310 if (0x0c == (ir
.modrm
>> 4))
6312 if ((ir
.modrm
& 0x0f) <= 7)
6314 if (i386_record_floats (gdbarch
, &ir
,
6315 I386_SAVE_FPU_REGS
))
6320 if (i386_record_floats (gdbarch
, &ir
,
6321 I387_ST0_REGNUM (tdep
)))
6323 /* If only st(0) is changing, then we have already
6325 if ((ir
.modrm
& 0x0f) - 0x08)
6327 if (i386_record_floats (gdbarch
, &ir
,
6328 I387_ST0_REGNUM (tdep
) +
6329 ((ir
.modrm
& 0x0f) - 0x08)))
6347 if (i386_record_floats (gdbarch
, &ir
,
6348 I387_ST0_REGNUM (tdep
)))
6366 if (i386_record_floats (gdbarch
, &ir
,
6367 I386_SAVE_FPU_REGS
))
6371 if (i386_record_floats (gdbarch
, &ir
,
6372 I387_ST0_REGNUM (tdep
)))
6374 if (i386_record_floats (gdbarch
, &ir
,
6375 I387_ST0_REGNUM (tdep
) + 1))
6382 if (0xe9 == ir
.modrm
)
6384 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
6387 else if ((0x0c == ir
.modrm
>> 4) || (0x0d == ir
.modrm
>> 4))
6389 if (i386_record_floats (gdbarch
, &ir
,
6390 I387_ST0_REGNUM (tdep
)))
6392 if (((ir
.modrm
& 0x0f) > 0) && ((ir
.modrm
& 0x0f) <= 7))
6394 if (i386_record_floats (gdbarch
, &ir
,
6395 I387_ST0_REGNUM (tdep
) +
6399 else if ((ir
.modrm
& 0x0f) - 0x08)
6401 if (i386_record_floats (gdbarch
, &ir
,
6402 I387_ST0_REGNUM (tdep
) +
6403 ((ir
.modrm
& 0x0f) - 0x08)))
6409 if (0xe3 == ir
.modrm
)
6411 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_ENV
))
6414 else if ((0x0c == ir
.modrm
>> 4) || (0x0d == ir
.modrm
>> 4))
6416 if (i386_record_floats (gdbarch
, &ir
,
6417 I387_ST0_REGNUM (tdep
)))
6419 if (((ir
.modrm
& 0x0f) > 0) && ((ir
.modrm
& 0x0f) <= 7))
6421 if (i386_record_floats (gdbarch
, &ir
,
6422 I387_ST0_REGNUM (tdep
) +
6426 else if ((ir
.modrm
& 0x0f) - 0x08)
6428 if (i386_record_floats (gdbarch
, &ir
,
6429 I387_ST0_REGNUM (tdep
) +
6430 ((ir
.modrm
& 0x0f) - 0x08)))
6436 if ((0x0c == ir
.modrm
>> 4)
6437 || (0x0d == ir
.modrm
>> 4)
6438 || (0x0f == ir
.modrm
>> 4))
6440 if ((ir
.modrm
& 0x0f) <= 7)
6442 if (i386_record_floats (gdbarch
, &ir
,
6443 I387_ST0_REGNUM (tdep
) +
6449 if (i386_record_floats (gdbarch
, &ir
,
6450 I387_ST0_REGNUM (tdep
) +
6451 ((ir
.modrm
& 0x0f) - 0x08)))
6457 if (0x0c == ir
.modrm
>> 4)
6459 if (i386_record_floats (gdbarch
, &ir
,
6460 I387_FTAG_REGNUM (tdep
)))
6463 else if ((0x0d == ir
.modrm
>> 4) || (0x0e == ir
.modrm
>> 4))
6465 if ((ir
.modrm
& 0x0f) <= 7)
6467 if (i386_record_floats (gdbarch
, &ir
,
6468 I387_ST0_REGNUM (tdep
) +
6474 if (i386_record_floats (gdbarch
, &ir
,
6475 I386_SAVE_FPU_REGS
))
6481 if ((0x0c == ir
.modrm
>> 4)
6482 || (0x0e == ir
.modrm
>> 4)
6483 || (0x0f == ir
.modrm
>> 4)
6484 || (0xd9 == ir
.modrm
))
6486 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
6491 if (0xe0 == ir
.modrm
)
6493 if (record_full_arch_list_add_reg (ir
.regcache
,
6497 else if ((0x0f == ir
.modrm
>> 4) || (0x0e == ir
.modrm
>> 4))
6499 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
6507 case 0xa4: /* movsS */
6509 case 0xaa: /* stosS */
6511 case 0x6c: /* insS */
6513 regcache_raw_read_unsigned (ir
.regcache
,
6514 ir
.regmap
[X86_RECORD_RECX_REGNUM
],
6520 if ((opcode
& 1) == 0)
6523 ir
.ot
= ir
.dflag
+ OT_WORD
;
6524 regcache_raw_read_unsigned (ir
.regcache
,
6525 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
6528 regcache_raw_read_unsigned (ir
.regcache
,
6529 ir
.regmap
[X86_RECORD_ES_REGNUM
],
6531 regcache_raw_read_unsigned (ir
.regcache
,
6532 ir
.regmap
[X86_RECORD_DS_REGNUM
],
6534 if (ir
.aflag
&& (es
!= ds
))
6536 /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */
6537 if (record_full_memory_query
)
6540 Process record ignores the memory change of instruction at address %s\n\
6541 because it can't get the value of the segment register.\n\
6542 Do you want to stop the program?"),
6543 paddress (gdbarch
, ir
.orig_addr
)))
6549 if (record_full_arch_list_add_mem (addr
, 1 << ir
.ot
))
6553 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
6554 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6555 if (opcode
== 0xa4 || opcode
== 0xa5)
6556 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
6557 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
6558 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6562 case 0xa6: /* cmpsS */
6564 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
6565 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
6566 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
6567 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6568 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6571 case 0xac: /* lodsS */
6573 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6574 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
6575 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
6576 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6577 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6580 case 0xae: /* scasS */
6582 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
6583 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
6584 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6585 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6588 case 0x6e: /* outsS */
6590 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
6591 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
6592 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6593 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6596 case 0xe4: /* port I/O */
6600 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6601 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6611 case 0xc2: /* ret im */
6612 case 0xc3: /* ret */
6613 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
6614 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6617 case 0xca: /* lret im */
6618 case 0xcb: /* lret */
6619 case 0xcf: /* iret */
6620 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
6621 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
6622 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6625 case 0xe8: /* call im */
6626 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
6628 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
6632 case 0x9a: /* lcall im */
6633 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6638 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
6639 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
6643 case 0xe9: /* jmp im */
6644 case 0xea: /* ljmp im */
6645 case 0xeb: /* jmp Jb */
6646 case 0x70: /* jcc Jb */
6662 case 0x0f80: /* jcc Jv */
6680 case 0x0f90: /* setcc Gv */
6696 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6698 if (i386_record_modrm (&ir
))
6701 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rex_b
? (ir
.rm
| ir
.rex_b
)
6705 if (i386_record_lea_modrm (&ir
))
6710 case 0x0f40: /* cmov Gv, Ev */
6726 if (i386_record_modrm (&ir
))
6729 if (ir
.dflag
== OT_BYTE
)
6731 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
6735 case 0x9c: /* pushf */
6736 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6737 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
6739 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
6743 case 0x9d: /* popf */
6744 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
6745 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6748 case 0x9e: /* sahf */
6749 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6755 case 0xf5: /* cmc */
6756 case 0xf8: /* clc */
6757 case 0xf9: /* stc */
6758 case 0xfc: /* cld */
6759 case 0xfd: /* std */
6760 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6763 case 0x9f: /* lahf */
6764 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6769 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6770 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6773 /* bit operations */
6774 case 0x0fba: /* bt/bts/btr/btc Gv, im */
6775 ir
.ot
= ir
.dflag
+ OT_WORD
;
6776 if (i386_record_modrm (&ir
))
6781 opcode
= opcode
<< 8 | ir
.modrm
;
6787 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6790 if (i386_record_lea_modrm (&ir
))
6794 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6797 case 0x0fa3: /* bt Gv, Ev */
6798 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6801 case 0x0fab: /* bts */
6802 case 0x0fb3: /* btr */
6803 case 0x0fbb: /* btc */
6804 ir
.ot
= ir
.dflag
+ OT_WORD
;
6805 if (i386_record_modrm (&ir
))
6808 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6812 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
6814 regcache_raw_read_unsigned (ir
.regcache
,
6815 ir
.regmap
[ir
.reg
| rex_r
],
6820 addr64
+= ((int16_t) addr
>> 4) << 4;
6823 addr64
+= ((int32_t) addr
>> 5) << 5;
6826 addr64
+= ((int64_t) addr
>> 6) << 6;
6829 if (record_full_arch_list_add_mem (addr64
, 1 << ir
.ot
))
6831 if (i386_record_lea_modrm (&ir
))
6834 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6837 case 0x0fbc: /* bsf */
6838 case 0x0fbd: /* bsr */
6839 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
6840 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6844 case 0x27: /* daa */
6845 case 0x2f: /* das */
6846 case 0x37: /* aaa */
6847 case 0x3f: /* aas */
6848 case 0xd4: /* aam */
6849 case 0xd5: /* aad */
6850 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6855 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6856 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6860 case 0x90: /* nop */
6861 if (prefixes
& PREFIX_LOCK
)
6868 case 0x9b: /* fwait */
6869 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
6871 opcode
= (uint32_t) opcode8
;
6877 case 0xcc: /* int3 */
6878 printf_unfiltered (_("Process record does not support instruction "
6885 case 0xcd: /* int */
6889 if (record_read_memory (gdbarch
, ir
.addr
, &interrupt
, 1))
6892 if (interrupt
!= 0x80
6893 || tdep
->i386_intx80_record
== NULL
)
6895 printf_unfiltered (_("Process record does not support "
6896 "instruction int 0x%02x.\n"),
6901 ret
= tdep
->i386_intx80_record (ir
.regcache
);
6908 case 0xce: /* into */
6909 printf_unfiltered (_("Process record does not support "
6910 "instruction into.\n"));
6915 case 0xfa: /* cli */
6916 case 0xfb: /* sti */
6919 case 0x62: /* bound */
6920 printf_unfiltered (_("Process record does not support "
6921 "instruction bound.\n"));
6926 case 0x0fc8: /* bswap reg */
6934 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode
& 7) | ir
.rex_b
);
6937 case 0xd6: /* salc */
6938 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6943 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6944 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6947 case 0xe0: /* loopnz */
6948 case 0xe1: /* loopz */
6949 case 0xe2: /* loop */
6950 case 0xe3: /* jecxz */
6951 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6952 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6955 case 0x0f30: /* wrmsr */
6956 printf_unfiltered (_("Process record does not support "
6957 "instruction wrmsr.\n"));
6962 case 0x0f32: /* rdmsr */
6963 printf_unfiltered (_("Process record does not support "
6964 "instruction rdmsr.\n"));
6969 case 0x0f31: /* rdtsc */
6970 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6971 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
6974 case 0x0f34: /* sysenter */
6977 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6982 if (tdep
->i386_sysenter_record
== NULL
)
6984 printf_unfiltered (_("Process record does not support "
6985 "instruction sysenter.\n"));
6989 ret
= tdep
->i386_sysenter_record (ir
.regcache
);
6995 case 0x0f35: /* sysexit */
6996 printf_unfiltered (_("Process record does not support "
6997 "instruction sysexit.\n"));
7002 case 0x0f05: /* syscall */
7005 if (tdep
->i386_syscall_record
== NULL
)
7007 printf_unfiltered (_("Process record does not support "
7008 "instruction syscall.\n"));
7012 ret
= tdep
->i386_syscall_record (ir
.regcache
);
7018 case 0x0f07: /* sysret */
7019 printf_unfiltered (_("Process record does not support "
7020 "instruction sysret.\n"));
7025 case 0x0fa2: /* cpuid */
7026 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
7027 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
7028 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
7029 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM
);
7032 case 0xf4: /* hlt */
7033 printf_unfiltered (_("Process record does not support "
7034 "instruction hlt.\n"));
7040 if (i386_record_modrm (&ir
))
7047 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
7051 if (i386_record_lea_modrm (&ir
))
7060 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7064 opcode
= opcode
<< 8 | ir
.modrm
;
7071 if (i386_record_modrm (&ir
))
7082 opcode
= opcode
<< 8 | ir
.modrm
;
7085 if (ir
.override
>= 0)
7087 if (record_full_memory_query
)
7090 Process record ignores the memory change of instruction at address %s\n\
7091 because it can't get the value of the segment register.\n\
7092 Do you want to stop the program?"),
7093 paddress (gdbarch
, ir
.orig_addr
)))
7099 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
7101 if (record_full_arch_list_add_mem (addr64
, 2))
7104 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
7106 if (record_full_arch_list_add_mem (addr64
, 8))
7111 if (record_full_arch_list_add_mem (addr64
, 4))
7122 case 0: /* monitor */
7125 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7129 opcode
= opcode
<< 8 | ir
.modrm
;
7137 if (ir
.override
>= 0)
7139 if (record_full_memory_query
)
7142 Process record ignores the memory change of instruction at address %s\n\
7143 because it can't get the value of the segment register.\n\
7144 Do you want to stop the program?"),
7145 paddress (gdbarch
, ir
.orig_addr
)))
7153 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
7155 if (record_full_arch_list_add_mem (addr64
, 2))
7158 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
7160 if (record_full_arch_list_add_mem (addr64
, 8))
7165 if (record_full_arch_list_add_mem (addr64
, 4))
7177 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
7178 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
7182 else if (ir
.rm
== 1)
7190 opcode
= opcode
<< 8 | ir
.modrm
;
7197 if (record_full_arch_list_add_reg (ir
.regcache
, ir
.rm
| ir
.rex_b
))
7203 if (i386_record_lea_modrm (&ir
))
7206 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7209 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7211 case 7: /* invlpg */
7214 if (ir
.rm
== 0 && ir
.regmap
[X86_RECORD_R8_REGNUM
])
7215 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM
);
7219 opcode
= opcode
<< 8 | ir
.modrm
;
7224 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7228 opcode
= opcode
<< 8 | ir
.modrm
;
7234 case 0x0f08: /* invd */
7235 case 0x0f09: /* wbinvd */
7238 case 0x63: /* arpl */
7239 if (i386_record_modrm (&ir
))
7241 if (ir
.mod
== 3 || ir
.regmap
[X86_RECORD_R8_REGNUM
])
7243 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.regmap
[X86_RECORD_R8_REGNUM
]
7244 ? (ir
.reg
| rex_r
) : ir
.rm
);
7248 ir
.ot
= ir
.dflag
? OT_LONG
: OT_WORD
;
7249 if (i386_record_lea_modrm (&ir
))
7252 if (!ir
.regmap
[X86_RECORD_R8_REGNUM
])
7253 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7256 case 0x0f02: /* lar */
7257 case 0x0f03: /* lsl */
7258 if (i386_record_modrm (&ir
))
7260 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
7261 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7265 if (i386_record_modrm (&ir
))
7267 if (ir
.mod
== 3 && ir
.reg
== 3)
7270 opcode
= opcode
<< 8 | ir
.modrm
;
7282 /* nop (multi byte) */
7285 case 0x0f20: /* mov reg, crN */
7286 case 0x0f22: /* mov crN, reg */
7287 if (i386_record_modrm (&ir
))
7289 if ((ir
.modrm
& 0xc0) != 0xc0)
7292 opcode
= opcode
<< 8 | ir
.modrm
;
7303 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7305 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
7309 opcode
= opcode
<< 8 | ir
.modrm
;
7315 case 0x0f21: /* mov reg, drN */
7316 case 0x0f23: /* mov drN, reg */
7317 if (i386_record_modrm (&ir
))
7319 if ((ir
.modrm
& 0xc0) != 0xc0 || ir
.reg
== 4
7320 || ir
.reg
== 5 || ir
.reg
>= 8)
7323 opcode
= opcode
<< 8 | ir
.modrm
;
7327 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7329 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
7332 case 0x0f06: /* clts */
7333 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7336 /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */
7338 case 0x0f0d: /* 3DNow! prefetch */
7341 case 0x0f0e: /* 3DNow! femms */
7342 case 0x0f77: /* emms */
7343 if (i386_fpc_regnum_p (gdbarch
, I387_FTAG_REGNUM(tdep
)))
7345 record_full_arch_list_add_reg (ir
.regcache
, I387_FTAG_REGNUM(tdep
));
7348 case 0x0f0f: /* 3DNow! data */
7349 if (i386_record_modrm (&ir
))
7351 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
7356 case 0x0c: /* 3DNow! pi2fw */
7357 case 0x0d: /* 3DNow! pi2fd */
7358 case 0x1c: /* 3DNow! pf2iw */
7359 case 0x1d: /* 3DNow! pf2id */
7360 case 0x8a: /* 3DNow! pfnacc */
7361 case 0x8e: /* 3DNow! pfpnacc */
7362 case 0x90: /* 3DNow! pfcmpge */
7363 case 0x94: /* 3DNow! pfmin */
7364 case 0x96: /* 3DNow! pfrcp */
7365 case 0x97: /* 3DNow! pfrsqrt */
7366 case 0x9a: /* 3DNow! pfsub */
7367 case 0x9e: /* 3DNow! pfadd */
7368 case 0xa0: /* 3DNow! pfcmpgt */
7369 case 0xa4: /* 3DNow! pfmax */
7370 case 0xa6: /* 3DNow! pfrcpit1 */
7371 case 0xa7: /* 3DNow! pfrsqit1 */
7372 case 0xaa: /* 3DNow! pfsubr */
7373 case 0xae: /* 3DNow! pfacc */
7374 case 0xb0: /* 3DNow! pfcmpeq */
7375 case 0xb4: /* 3DNow! pfmul */
7376 case 0xb6: /* 3DNow! pfrcpit2 */
7377 case 0xb7: /* 3DNow! pmulhrw */
7378 case 0xbb: /* 3DNow! pswapd */
7379 case 0xbf: /* 3DNow! pavgusb */
7380 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.reg
))
7381 goto no_support_3dnow_data
;
7382 record_full_arch_list_add_reg (ir
.regcache
, ir
.reg
);
7386 no_support_3dnow_data
:
7387 opcode
= (opcode
<< 8) | opcode8
;
7393 case 0x0faa: /* rsm */
7394 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7395 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
7396 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
7397 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
7398 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM
);
7399 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
7400 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
7401 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
7402 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
7406 if (i386_record_modrm (&ir
))
7410 case 0: /* fxsave */
7414 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7415 if (i386_record_lea_modrm_addr (&ir
, &tmpu64
))
7417 if (record_full_arch_list_add_mem (tmpu64
, 512))
7422 case 1: /* fxrstor */
7426 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7428 for (i
= I387_MM0_REGNUM (tdep
);
7429 i386_mmx_regnum_p (gdbarch
, i
); i
++)
7430 record_full_arch_list_add_reg (ir
.regcache
, i
);
7432 for (i
= I387_XMM0_REGNUM (tdep
);
7433 i386_xmm_regnum_p (gdbarch
, i
); i
++)
7434 record_full_arch_list_add_reg (ir
.regcache
, i
);
7436 if (i386_mxcsr_regnum_p (gdbarch
, I387_MXCSR_REGNUM(tdep
)))
7437 record_full_arch_list_add_reg (ir
.regcache
,
7438 I387_MXCSR_REGNUM(tdep
));
7440 for (i
= I387_ST0_REGNUM (tdep
);
7441 i386_fp_regnum_p (gdbarch
, i
); i
++)
7442 record_full_arch_list_add_reg (ir
.regcache
, i
);
7444 for (i
= I387_FCTRL_REGNUM (tdep
);
7445 i386_fpc_regnum_p (gdbarch
, i
); i
++)
7446 record_full_arch_list_add_reg (ir
.regcache
, i
);
7450 case 2: /* ldmxcsr */
7451 if (!i386_mxcsr_regnum_p (gdbarch
, I387_MXCSR_REGNUM(tdep
)))
7453 record_full_arch_list_add_reg (ir
.regcache
, I387_MXCSR_REGNUM(tdep
));
7456 case 3: /* stmxcsr */
7458 if (i386_record_lea_modrm (&ir
))
7462 case 5: /* lfence */
7463 case 6: /* mfence */
7464 case 7: /* sfence clflush */
7468 opcode
= (opcode
<< 8) | ir
.modrm
;
7474 case 0x0fc3: /* movnti */
7475 ir
.ot
= (ir
.dflag
== 2) ? OT_QUAD
: OT_LONG
;
7476 if (i386_record_modrm (&ir
))
7481 if (i386_record_lea_modrm (&ir
))
7485 /* Add prefix to opcode. */
7600 /* Mask out PREFIX_ADDR. */
7601 switch ((prefixes
& ~PREFIX_ADDR
))
7613 reswitch_prefix_add
:
7621 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
7624 opcode
= (uint32_t) opcode8
| opcode
<< 8;
7625 goto reswitch_prefix_add
;
7628 case 0x0f10: /* movups */
7629 case 0x660f10: /* movupd */
7630 case 0xf30f10: /* movss */
7631 case 0xf20f10: /* movsd */
7632 case 0x0f12: /* movlps */
7633 case 0x660f12: /* movlpd */
7634 case 0xf30f12: /* movsldup */
7635 case 0xf20f12: /* movddup */
7636 case 0x0f14: /* unpcklps */
7637 case 0x660f14: /* unpcklpd */
7638 case 0x0f15: /* unpckhps */
7639 case 0x660f15: /* unpckhpd */
7640 case 0x0f16: /* movhps */
7641 case 0x660f16: /* movhpd */
7642 case 0xf30f16: /* movshdup */
7643 case 0x0f28: /* movaps */
7644 case 0x660f28: /* movapd */
7645 case 0x0f2a: /* cvtpi2ps */
7646 case 0x660f2a: /* cvtpi2pd */
7647 case 0xf30f2a: /* cvtsi2ss */
7648 case 0xf20f2a: /* cvtsi2sd */
7649 case 0x0f2c: /* cvttps2pi */
7650 case 0x660f2c: /* cvttpd2pi */
7651 case 0x0f2d: /* cvtps2pi */
7652 case 0x660f2d: /* cvtpd2pi */
7653 case 0x660f3800: /* pshufb */
7654 case 0x660f3801: /* phaddw */
7655 case 0x660f3802: /* phaddd */
7656 case 0x660f3803: /* phaddsw */
7657 case 0x660f3804: /* pmaddubsw */
7658 case 0x660f3805: /* phsubw */
7659 case 0x660f3806: /* phsubd */
7660 case 0x660f3807: /* phsubsw */
7661 case 0x660f3808: /* psignb */
7662 case 0x660f3809: /* psignw */
7663 case 0x660f380a: /* psignd */
7664 case 0x660f380b: /* pmulhrsw */
7665 case 0x660f3810: /* pblendvb */
7666 case 0x660f3814: /* blendvps */
7667 case 0x660f3815: /* blendvpd */
7668 case 0x660f381c: /* pabsb */
7669 case 0x660f381d: /* pabsw */
7670 case 0x660f381e: /* pabsd */
7671 case 0x660f3820: /* pmovsxbw */
7672 case 0x660f3821: /* pmovsxbd */
7673 case 0x660f3822: /* pmovsxbq */
7674 case 0x660f3823: /* pmovsxwd */
7675 case 0x660f3824: /* pmovsxwq */
7676 case 0x660f3825: /* pmovsxdq */
7677 case 0x660f3828: /* pmuldq */
7678 case 0x660f3829: /* pcmpeqq */
7679 case 0x660f382a: /* movntdqa */
7680 case 0x660f3a08: /* roundps */
7681 case 0x660f3a09: /* roundpd */
7682 case 0x660f3a0a: /* roundss */
7683 case 0x660f3a0b: /* roundsd */
7684 case 0x660f3a0c: /* blendps */
7685 case 0x660f3a0d: /* blendpd */
7686 case 0x660f3a0e: /* pblendw */
7687 case 0x660f3a0f: /* palignr */
7688 case 0x660f3a20: /* pinsrb */
7689 case 0x660f3a21: /* insertps */
7690 case 0x660f3a22: /* pinsrd pinsrq */
7691 case 0x660f3a40: /* dpps */
7692 case 0x660f3a41: /* dppd */
7693 case 0x660f3a42: /* mpsadbw */
7694 case 0x660f3a60: /* pcmpestrm */
7695 case 0x660f3a61: /* pcmpestri */
7696 case 0x660f3a62: /* pcmpistrm */
7697 case 0x660f3a63: /* pcmpistri */
7698 case 0x0f51: /* sqrtps */
7699 case 0x660f51: /* sqrtpd */
7700 case 0xf20f51: /* sqrtsd */
7701 case 0xf30f51: /* sqrtss */
7702 case 0x0f52: /* rsqrtps */
7703 case 0xf30f52: /* rsqrtss */
7704 case 0x0f53: /* rcpps */
7705 case 0xf30f53: /* rcpss */
7706 case 0x0f54: /* andps */
7707 case 0x660f54: /* andpd */
7708 case 0x0f55: /* andnps */
7709 case 0x660f55: /* andnpd */
7710 case 0x0f56: /* orps */
7711 case 0x660f56: /* orpd */
7712 case 0x0f57: /* xorps */
7713 case 0x660f57: /* xorpd */
7714 case 0x0f58: /* addps */
7715 case 0x660f58: /* addpd */
7716 case 0xf20f58: /* addsd */
7717 case 0xf30f58: /* addss */
7718 case 0x0f59: /* mulps */
7719 case 0x660f59: /* mulpd */
7720 case 0xf20f59: /* mulsd */
7721 case 0xf30f59: /* mulss */
7722 case 0x0f5a: /* cvtps2pd */
7723 case 0x660f5a: /* cvtpd2ps */
7724 case 0xf20f5a: /* cvtsd2ss */
7725 case 0xf30f5a: /* cvtss2sd */
7726 case 0x0f5b: /* cvtdq2ps */
7727 case 0x660f5b: /* cvtps2dq */
7728 case 0xf30f5b: /* cvttps2dq */
7729 case 0x0f5c: /* subps */
7730 case 0x660f5c: /* subpd */
7731 case 0xf20f5c: /* subsd */
7732 case 0xf30f5c: /* subss */
7733 case 0x0f5d: /* minps */
7734 case 0x660f5d: /* minpd */
7735 case 0xf20f5d: /* minsd */
7736 case 0xf30f5d: /* minss */
7737 case 0x0f5e: /* divps */
7738 case 0x660f5e: /* divpd */
7739 case 0xf20f5e: /* divsd */
7740 case 0xf30f5e: /* divss */
7741 case 0x0f5f: /* maxps */
7742 case 0x660f5f: /* maxpd */
7743 case 0xf20f5f: /* maxsd */
7744 case 0xf30f5f: /* maxss */
7745 case 0x660f60: /* punpcklbw */
7746 case 0x660f61: /* punpcklwd */
7747 case 0x660f62: /* punpckldq */
7748 case 0x660f63: /* packsswb */
7749 case 0x660f64: /* pcmpgtb */
7750 case 0x660f65: /* pcmpgtw */
7751 case 0x660f66: /* pcmpgtd */
7752 case 0x660f67: /* packuswb */
7753 case 0x660f68: /* punpckhbw */
7754 case 0x660f69: /* punpckhwd */
7755 case 0x660f6a: /* punpckhdq */
7756 case 0x660f6b: /* packssdw */
7757 case 0x660f6c: /* punpcklqdq */
7758 case 0x660f6d: /* punpckhqdq */
7759 case 0x660f6e: /* movd */
7760 case 0x660f6f: /* movdqa */
7761 case 0xf30f6f: /* movdqu */
7762 case 0x660f70: /* pshufd */
7763 case 0xf20f70: /* pshuflw */
7764 case 0xf30f70: /* pshufhw */
7765 case 0x660f74: /* pcmpeqb */
7766 case 0x660f75: /* pcmpeqw */
7767 case 0x660f76: /* pcmpeqd */
7768 case 0x660f7c: /* haddpd */
7769 case 0xf20f7c: /* haddps */
7770 case 0x660f7d: /* hsubpd */
7771 case 0xf20f7d: /* hsubps */
7772 case 0xf30f7e: /* movq */
7773 case 0x0fc2: /* cmpps */
7774 case 0x660fc2: /* cmppd */
7775 case 0xf20fc2: /* cmpsd */
7776 case 0xf30fc2: /* cmpss */
7777 case 0x660fc4: /* pinsrw */
7778 case 0x0fc6: /* shufps */
7779 case 0x660fc6: /* shufpd */
7780 case 0x660fd0: /* addsubpd */
7781 case 0xf20fd0: /* addsubps */
7782 case 0x660fd1: /* psrlw */
7783 case 0x660fd2: /* psrld */
7784 case 0x660fd3: /* psrlq */
7785 case 0x660fd4: /* paddq */
7786 case 0x660fd5: /* pmullw */
7787 case 0xf30fd6: /* movq2dq */
7788 case 0x660fd8: /* psubusb */
7789 case 0x660fd9: /* psubusw */
7790 case 0x660fda: /* pminub */
7791 case 0x660fdb: /* pand */
7792 case 0x660fdc: /* paddusb */
7793 case 0x660fdd: /* paddusw */
7794 case 0x660fde: /* pmaxub */
7795 case 0x660fdf: /* pandn */
7796 case 0x660fe0: /* pavgb */
7797 case 0x660fe1: /* psraw */
7798 case 0x660fe2: /* psrad */
7799 case 0x660fe3: /* pavgw */
7800 case 0x660fe4: /* pmulhuw */
7801 case 0x660fe5: /* pmulhw */
7802 case 0x660fe6: /* cvttpd2dq */
7803 case 0xf20fe6: /* cvtpd2dq */
7804 case 0xf30fe6: /* cvtdq2pd */
7805 case 0x660fe8: /* psubsb */
7806 case 0x660fe9: /* psubsw */
7807 case 0x660fea: /* pminsw */
7808 case 0x660feb: /* por */
7809 case 0x660fec: /* paddsb */
7810 case 0x660fed: /* paddsw */
7811 case 0x660fee: /* pmaxsw */
7812 case 0x660fef: /* pxor */
7813 case 0xf20ff0: /* lddqu */
7814 case 0x660ff1: /* psllw */
7815 case 0x660ff2: /* pslld */
7816 case 0x660ff3: /* psllq */
7817 case 0x660ff4: /* pmuludq */
7818 case 0x660ff5: /* pmaddwd */
7819 case 0x660ff6: /* psadbw */
7820 case 0x660ff8: /* psubb */
7821 case 0x660ff9: /* psubw */
7822 case 0x660ffa: /* psubd */
7823 case 0x660ffb: /* psubq */
7824 case 0x660ffc: /* paddb */
7825 case 0x660ffd: /* paddw */
7826 case 0x660ffe: /* paddd */
7827 if (i386_record_modrm (&ir
))
7830 if (!i386_xmm_regnum_p (gdbarch
, I387_XMM0_REGNUM (tdep
) + ir
.reg
))
7832 record_full_arch_list_add_reg (ir
.regcache
,
7833 I387_XMM0_REGNUM (tdep
) + ir
.reg
);
7834 if ((opcode
& 0xfffffffc) == 0x660f3a60)
7835 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7838 case 0x0f11: /* movups */
7839 case 0x660f11: /* movupd */
7840 case 0xf30f11: /* movss */
7841 case 0xf20f11: /* movsd */
7842 case 0x0f13: /* movlps */
7843 case 0x660f13: /* movlpd */
7844 case 0x0f17: /* movhps */
7845 case 0x660f17: /* movhpd */
7846 case 0x0f29: /* movaps */
7847 case 0x660f29: /* movapd */
7848 case 0x660f3a14: /* pextrb */
7849 case 0x660f3a15: /* pextrw */
7850 case 0x660f3a16: /* pextrd pextrq */
7851 case 0x660f3a17: /* extractps */
7852 case 0x660f7f: /* movdqa */
7853 case 0xf30f7f: /* movdqu */
7854 if (i386_record_modrm (&ir
))
7858 if (opcode
== 0x0f13 || opcode
== 0x660f13
7859 || opcode
== 0x0f17 || opcode
== 0x660f17)
7862 if (!i386_xmm_regnum_p (gdbarch
,
7863 I387_XMM0_REGNUM (tdep
) + ir
.rm
))
7865 record_full_arch_list_add_reg (ir
.regcache
,
7866 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
7888 if (i386_record_lea_modrm (&ir
))
7893 case 0x0f2b: /* movntps */
7894 case 0x660f2b: /* movntpd */
7895 case 0x0fe7: /* movntq */
7896 case 0x660fe7: /* movntdq */
7899 if (opcode
== 0x0fe7)
7903 if (i386_record_lea_modrm (&ir
))
7907 case 0xf30f2c: /* cvttss2si */
7908 case 0xf20f2c: /* cvttsd2si */
7909 case 0xf30f2d: /* cvtss2si */
7910 case 0xf20f2d: /* cvtsd2si */
7911 case 0xf20f38f0: /* crc32 */
7912 case 0xf20f38f1: /* crc32 */
7913 case 0x0f50: /* movmskps */
7914 case 0x660f50: /* movmskpd */
7915 case 0x0fc5: /* pextrw */
7916 case 0x660fc5: /* pextrw */
7917 case 0x0fd7: /* pmovmskb */
7918 case 0x660fd7: /* pmovmskb */
7919 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
7922 case 0x0f3800: /* pshufb */
7923 case 0x0f3801: /* phaddw */
7924 case 0x0f3802: /* phaddd */
7925 case 0x0f3803: /* phaddsw */
7926 case 0x0f3804: /* pmaddubsw */
7927 case 0x0f3805: /* phsubw */
7928 case 0x0f3806: /* phsubd */
7929 case 0x0f3807: /* phsubsw */
7930 case 0x0f3808: /* psignb */
7931 case 0x0f3809: /* psignw */
7932 case 0x0f380a: /* psignd */
7933 case 0x0f380b: /* pmulhrsw */
7934 case 0x0f381c: /* pabsb */
7935 case 0x0f381d: /* pabsw */
7936 case 0x0f381e: /* pabsd */
7937 case 0x0f382b: /* packusdw */
7938 case 0x0f3830: /* pmovzxbw */
7939 case 0x0f3831: /* pmovzxbd */
7940 case 0x0f3832: /* pmovzxbq */
7941 case 0x0f3833: /* pmovzxwd */
7942 case 0x0f3834: /* pmovzxwq */
7943 case 0x0f3835: /* pmovzxdq */
7944 case 0x0f3837: /* pcmpgtq */
7945 case 0x0f3838: /* pminsb */
7946 case 0x0f3839: /* pminsd */
7947 case 0x0f383a: /* pminuw */
7948 case 0x0f383b: /* pminud */
7949 case 0x0f383c: /* pmaxsb */
7950 case 0x0f383d: /* pmaxsd */
7951 case 0x0f383e: /* pmaxuw */
7952 case 0x0f383f: /* pmaxud */
7953 case 0x0f3840: /* pmulld */
7954 case 0x0f3841: /* phminposuw */
7955 case 0x0f3a0f: /* palignr */
7956 case 0x0f60: /* punpcklbw */
7957 case 0x0f61: /* punpcklwd */
7958 case 0x0f62: /* punpckldq */
7959 case 0x0f63: /* packsswb */
7960 case 0x0f64: /* pcmpgtb */
7961 case 0x0f65: /* pcmpgtw */
7962 case 0x0f66: /* pcmpgtd */
7963 case 0x0f67: /* packuswb */
7964 case 0x0f68: /* punpckhbw */
7965 case 0x0f69: /* punpckhwd */
7966 case 0x0f6a: /* punpckhdq */
7967 case 0x0f6b: /* packssdw */
7968 case 0x0f6e: /* movd */
7969 case 0x0f6f: /* movq */
7970 case 0x0f70: /* pshufw */
7971 case 0x0f74: /* pcmpeqb */
7972 case 0x0f75: /* pcmpeqw */
7973 case 0x0f76: /* pcmpeqd */
7974 case 0x0fc4: /* pinsrw */
7975 case 0x0fd1: /* psrlw */
7976 case 0x0fd2: /* psrld */
7977 case 0x0fd3: /* psrlq */
7978 case 0x0fd4: /* paddq */
7979 case 0x0fd5: /* pmullw */
7980 case 0xf20fd6: /* movdq2q */
7981 case 0x0fd8: /* psubusb */
7982 case 0x0fd9: /* psubusw */
7983 case 0x0fda: /* pminub */
7984 case 0x0fdb: /* pand */
7985 case 0x0fdc: /* paddusb */
7986 case 0x0fdd: /* paddusw */
7987 case 0x0fde: /* pmaxub */
7988 case 0x0fdf: /* pandn */
7989 case 0x0fe0: /* pavgb */
7990 case 0x0fe1: /* psraw */
7991 case 0x0fe2: /* psrad */
7992 case 0x0fe3: /* pavgw */
7993 case 0x0fe4: /* pmulhuw */
7994 case 0x0fe5: /* pmulhw */
7995 case 0x0fe8: /* psubsb */
7996 case 0x0fe9: /* psubsw */
7997 case 0x0fea: /* pminsw */
7998 case 0x0feb: /* por */
7999 case 0x0fec: /* paddsb */
8000 case 0x0fed: /* paddsw */
8001 case 0x0fee: /* pmaxsw */
8002 case 0x0fef: /* pxor */
8003 case 0x0ff1: /* psllw */
8004 case 0x0ff2: /* pslld */
8005 case 0x0ff3: /* psllq */
8006 case 0x0ff4: /* pmuludq */
8007 case 0x0ff5: /* pmaddwd */
8008 case 0x0ff6: /* psadbw */
8009 case 0x0ff8: /* psubb */
8010 case 0x0ff9: /* psubw */
8011 case 0x0ffa: /* psubd */
8012 case 0x0ffb: /* psubq */
8013 case 0x0ffc: /* paddb */
8014 case 0x0ffd: /* paddw */
8015 case 0x0ffe: /* paddd */
8016 if (i386_record_modrm (&ir
))
8018 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.reg
))
8020 record_full_arch_list_add_reg (ir
.regcache
,
8021 I387_MM0_REGNUM (tdep
) + ir
.reg
);
8024 case 0x0f71: /* psllw */
8025 case 0x0f72: /* pslld */
8026 case 0x0f73: /* psllq */
8027 if (i386_record_modrm (&ir
))
8029 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.rm
))
8031 record_full_arch_list_add_reg (ir
.regcache
,
8032 I387_MM0_REGNUM (tdep
) + ir
.rm
);
8035 case 0x660f71: /* psllw */
8036 case 0x660f72: /* pslld */
8037 case 0x660f73: /* psllq */
8038 if (i386_record_modrm (&ir
))
8041 if (!i386_xmm_regnum_p (gdbarch
, I387_XMM0_REGNUM (tdep
) + ir
.rm
))
8043 record_full_arch_list_add_reg (ir
.regcache
,
8044 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
8047 case 0x0f7e: /* movd */
8048 case 0x660f7e: /* movd */
8049 if (i386_record_modrm (&ir
))
8052 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
8059 if (i386_record_lea_modrm (&ir
))
8064 case 0x0f7f: /* movq */
8065 if (i386_record_modrm (&ir
))
8069 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.rm
))
8071 record_full_arch_list_add_reg (ir
.regcache
,
8072 I387_MM0_REGNUM (tdep
) + ir
.rm
);
8077 if (i386_record_lea_modrm (&ir
))
8082 case 0xf30fb8: /* popcnt */
8083 if (i386_record_modrm (&ir
))
8085 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
8086 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
8089 case 0x660fd6: /* movq */
8090 if (i386_record_modrm (&ir
))
8095 if (!i386_xmm_regnum_p (gdbarch
,
8096 I387_XMM0_REGNUM (tdep
) + ir
.rm
))
8098 record_full_arch_list_add_reg (ir
.regcache
,
8099 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
8104 if (i386_record_lea_modrm (&ir
))
8109 case 0x660f3817: /* ptest */
8110 case 0x0f2e: /* ucomiss */
8111 case 0x660f2e: /* ucomisd */
8112 case 0x0f2f: /* comiss */
8113 case 0x660f2f: /* comisd */
8114 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
8117 case 0x0ff7: /* maskmovq */
8118 regcache_raw_read_unsigned (ir
.regcache
,
8119 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
8121 if (record_full_arch_list_add_mem (addr
, 64))
8125 case 0x660ff7: /* maskmovdqu */
8126 regcache_raw_read_unsigned (ir
.regcache
,
8127 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
8129 if (record_full_arch_list_add_mem (addr
, 128))
8144 /* In the future, maybe still need to deal with need_dasm. */
8145 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM
);
8146 if (record_full_arch_list_add_end ())
8152 printf_unfiltered (_("Process record does not support instruction 0x%02x "
8153 "at address %s.\n"),
8154 (unsigned int) (opcode
),
8155 paddress (gdbarch
, ir
.orig_addr
));
8159 static const int i386_record_regmap
[] =
8161 I386_EAX_REGNUM
, I386_ECX_REGNUM
, I386_EDX_REGNUM
, I386_EBX_REGNUM
,
8162 I386_ESP_REGNUM
, I386_EBP_REGNUM
, I386_ESI_REGNUM
, I386_EDI_REGNUM
,
8163 0, 0, 0, 0, 0, 0, 0, 0,
8164 I386_EIP_REGNUM
, I386_EFLAGS_REGNUM
, I386_CS_REGNUM
, I386_SS_REGNUM
,
8165 I386_DS_REGNUM
, I386_ES_REGNUM
, I386_FS_REGNUM
, I386_GS_REGNUM
8168 /* Check that the given address appears suitable for a fast
8169 tracepoint, which on x86-64 means that we need an instruction of at
8170 least 5 bytes, so that we can overwrite it with a 4-byte-offset
8171 jump and not have to worry about program jumps to an address in the
8172 middle of the tracepoint jump. On x86, it may be possible to use
8173 4-byte jumps with a 2-byte offset to a trampoline located in the
8174 bottom 64 KiB of memory. Returns 1 if OK, and writes a size
8175 of instruction to replace, and 0 if not, plus an explanatory
8179 i386_fast_tracepoint_valid_at (struct gdbarch
*gdbarch
, CORE_ADDR addr
,
8184 /* Ask the target for the minimum instruction length supported. */
8185 jumplen
= target_get_min_fast_tracepoint_insn_len ();
8189 /* If the target does not support the get_min_fast_tracepoint_insn_len
8190 operation, assume that fast tracepoints will always be implemented
8191 using 4-byte relative jumps on both x86 and x86-64. */
8194 else if (jumplen
== 0)
8196 /* If the target does support get_min_fast_tracepoint_insn_len but
8197 returns zero, then the IPA has not loaded yet. In this case,
8198 we optimistically assume that truncated 2-byte relative jumps
8199 will be available on x86, and compensate later if this assumption
8200 turns out to be incorrect. On x86-64 architectures, 4-byte relative
8201 jumps will always be used. */
8202 jumplen
= (register_size (gdbarch
, 0) == 8) ? 5 : 4;
8205 /* Check for fit. */
8206 len
= gdb_insn_length (gdbarch
, addr
);
8210 /* Return a bit of target-specific detail to add to the caller's
8211 generic failure message. */
8213 *msg
= string_printf (_("; instruction is only %d bytes long, "
8214 "need at least %d bytes for the jump"),
8226 /* Return a floating-point format for a floating-point variable of
8227 length LEN in bits. If non-NULL, NAME is the name of its type.
8228 If no suitable type is found, return NULL. */
8230 static const struct floatformat
**
8231 i386_floatformat_for_type (struct gdbarch
*gdbarch
,
8232 const char *name
, int len
)
8234 if (len
== 128 && name
)
8235 if (strcmp (name
, "__float128") == 0
8236 || strcmp (name
, "_Float128") == 0
8237 || strcmp (name
, "complex _Float128") == 0
8238 || strcmp (name
, "complex(kind=16)") == 0
8239 || strcmp (name
, "quad complex") == 0
8240 || strcmp (name
, "real(kind=16)") == 0
8241 || strcmp (name
, "real*16") == 0)
8242 return floatformats_ia64_quad
;
8244 return default_floatformat_for_type (gdbarch
, name
, len
);
8248 i386_validate_tdesc_p (struct gdbarch_tdep
*tdep
,
8249 struct tdesc_arch_data
*tdesc_data
)
8251 const struct target_desc
*tdesc
= tdep
->tdesc
;
8252 const struct tdesc_feature
*feature_core
;
8254 const struct tdesc_feature
*feature_sse
, *feature_avx
, *feature_mpx
,
8255 *feature_avx512
, *feature_pkeys
, *feature_segments
;
8256 int i
, num_regs
, valid_p
;
8258 if (! tdesc_has_registers (tdesc
))
8261 /* Get core registers. */
8262 feature_core
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.core");
8263 if (feature_core
== NULL
)
8266 /* Get SSE registers. */
8267 feature_sse
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.sse");
8269 /* Try AVX registers. */
8270 feature_avx
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx");
8272 /* Try MPX registers. */
8273 feature_mpx
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.mpx");
8275 /* Try AVX512 registers. */
8276 feature_avx512
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx512");
8278 /* Try segment base registers. */
8279 feature_segments
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.segments");
8282 feature_pkeys
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.pkeys");
8286 /* The XCR0 bits. */
8289 /* AVX512 register description requires AVX register description. */
8293 tdep
->xcr0
= X86_XSTATE_AVX_AVX512_MASK
;
8295 /* It may have been set by OSABI initialization function. */
8296 if (tdep
->k0_regnum
< 0)
8298 tdep
->k_register_names
= i386_k_names
;
8299 tdep
->k0_regnum
= I386_K0_REGNUM
;
8302 for (i
= 0; i
< I387_NUM_K_REGS
; i
++)
8303 valid_p
&= tdesc_numbered_register (feature_avx512
, tdesc_data
,
8304 tdep
->k0_regnum
+ i
,
8307 if (tdep
->num_zmm_regs
== 0)
8309 tdep
->zmmh_register_names
= i386_zmmh_names
;
8310 tdep
->num_zmm_regs
= 8;
8311 tdep
->zmm0h_regnum
= I386_ZMM0H_REGNUM
;
8314 for (i
= 0; i
< tdep
->num_zmm_regs
; i
++)
8315 valid_p
&= tdesc_numbered_register (feature_avx512
, tdesc_data
,
8316 tdep
->zmm0h_regnum
+ i
,
8317 tdep
->zmmh_register_names
[i
]);
8319 for (i
= 0; i
< tdep
->num_xmm_avx512_regs
; i
++)
8320 valid_p
&= tdesc_numbered_register (feature_avx512
, tdesc_data
,
8321 tdep
->xmm16_regnum
+ i
,
8322 tdep
->xmm_avx512_register_names
[i
]);
8324 for (i
= 0; i
< tdep
->num_ymm_avx512_regs
; i
++)
8325 valid_p
&= tdesc_numbered_register (feature_avx512
, tdesc_data
,
8326 tdep
->ymm16h_regnum
+ i
,
8327 tdep
->ymm16h_register_names
[i
]);
8331 /* AVX register description requires SSE register description. */
8335 if (!feature_avx512
)
8336 tdep
->xcr0
= X86_XSTATE_AVX_MASK
;
8338 /* It may have been set by OSABI initialization function. */
8339 if (tdep
->num_ymm_regs
== 0)
8341 tdep
->ymmh_register_names
= i386_ymmh_names
;
8342 tdep
->num_ymm_regs
= 8;
8343 tdep
->ymm0h_regnum
= I386_YMM0H_REGNUM
;
8346 for (i
= 0; i
< tdep
->num_ymm_regs
; i
++)
8347 valid_p
&= tdesc_numbered_register (feature_avx
, tdesc_data
,
8348 tdep
->ymm0h_regnum
+ i
,
8349 tdep
->ymmh_register_names
[i
]);
8351 else if (feature_sse
)
8352 tdep
->xcr0
= X86_XSTATE_SSE_MASK
;
8355 tdep
->xcr0
= X86_XSTATE_X87_MASK
;
8356 tdep
->num_xmm_regs
= 0;
8359 num_regs
= tdep
->num_core_regs
;
8360 for (i
= 0; i
< num_regs
; i
++)
8361 valid_p
&= tdesc_numbered_register (feature_core
, tdesc_data
, i
,
8362 tdep
->register_names
[i
]);
8366 /* Need to include %mxcsr, so add one. */
8367 num_regs
+= tdep
->num_xmm_regs
+ 1;
8368 for (; i
< num_regs
; i
++)
8369 valid_p
&= tdesc_numbered_register (feature_sse
, tdesc_data
, i
,
8370 tdep
->register_names
[i
]);
8375 tdep
->xcr0
|= X86_XSTATE_MPX_MASK
;
8377 if (tdep
->bnd0r_regnum
< 0)
8379 tdep
->mpx_register_names
= i386_mpx_names
;
8380 tdep
->bnd0r_regnum
= I386_BND0R_REGNUM
;
8381 tdep
->bndcfgu_regnum
= I386_BNDCFGU_REGNUM
;
8384 for (i
= 0; i
< I387_NUM_MPX_REGS
; i
++)
8385 valid_p
&= tdesc_numbered_register (feature_mpx
, tdesc_data
,
8386 I387_BND0R_REGNUM (tdep
) + i
,
8387 tdep
->mpx_register_names
[i
]);
8390 if (feature_segments
)
8392 if (tdep
->fsbase_regnum
< 0)
8393 tdep
->fsbase_regnum
= I386_FSBASE_REGNUM
;
8394 valid_p
&= tdesc_numbered_register (feature_segments
, tdesc_data
,
8395 tdep
->fsbase_regnum
, "fs_base");
8396 valid_p
&= tdesc_numbered_register (feature_segments
, tdesc_data
,
8397 tdep
->fsbase_regnum
+ 1, "gs_base");
8402 tdep
->xcr0
|= X86_XSTATE_PKRU
;
8403 if (tdep
->pkru_regnum
< 0)
8405 tdep
->pkeys_register_names
= i386_pkeys_names
;
8406 tdep
->pkru_regnum
= I386_PKRU_REGNUM
;
8407 tdep
->num_pkeys_regs
= 1;
8410 for (i
= 0; i
< I387_NUM_PKEYS_REGS
; i
++)
8411 valid_p
&= tdesc_numbered_register (feature_pkeys
, tdesc_data
,
8412 I387_PKRU_REGNUM (tdep
) + i
,
8413 tdep
->pkeys_register_names
[i
]);
8421 /* Implement the type_align gdbarch function. */
8424 i386_type_align (struct gdbarch
*gdbarch
, struct type
*type
)
8426 type
= check_typedef (type
);
8428 if (gdbarch_ptr_bit (gdbarch
) == 32)
8430 if ((type
->code () == TYPE_CODE_INT
8431 || type
->code () == TYPE_CODE_FLT
)
8432 && TYPE_LENGTH (type
) > 4)
8435 /* Handle x86's funny long double. */
8436 if (type
->code () == TYPE_CODE_FLT
8437 && gdbarch_long_double_bit (gdbarch
) == TYPE_LENGTH (type
) * 8)
8445 /* Note: This is called for both i386 and amd64. */
8447 static struct gdbarch
*
8448 i386_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
8450 struct gdbarch_tdep
*tdep
;
8451 struct gdbarch
*gdbarch
;
8452 const struct target_desc
*tdesc
;
8458 /* If there is already a candidate, use it. */
8459 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
8461 return arches
->gdbarch
;
8463 /* Allocate space for the new architecture. Assume i386 for now. */
8464 tdep
= XCNEW (struct gdbarch_tdep
);
8465 gdbarch
= gdbarch_alloc (&info
, tdep
);
8467 /* General-purpose registers. */
8468 tdep
->gregset_reg_offset
= NULL
;
8469 tdep
->gregset_num_regs
= I386_NUM_GREGS
;
8470 tdep
->sizeof_gregset
= 0;
8472 /* Floating-point registers. */
8473 tdep
->sizeof_fpregset
= I387_SIZEOF_FSAVE
;
8474 tdep
->fpregset
= &i386_fpregset
;
8476 /* The default settings include the FPU registers, the MMX registers
8477 and the SSE registers. This can be overridden for a specific ABI
8478 by adjusting the members `st0_regnum', `mm0_regnum' and
8479 `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers
8480 will show up in the output of "info all-registers". */
8482 tdep
->st0_regnum
= I386_ST0_REGNUM
;
8484 /* I386_NUM_XREGS includes %mxcsr, so substract one. */
8485 tdep
->num_xmm_regs
= I386_NUM_XREGS
- 1;
8487 tdep
->jb_pc_offset
= -1;
8488 tdep
->struct_return
= pcc_struct_return
;
8489 tdep
->sigtramp_start
= 0;
8490 tdep
->sigtramp_end
= 0;
8491 tdep
->sigtramp_p
= i386_sigtramp_p
;
8492 tdep
->sigcontext_addr
= NULL
;
8493 tdep
->sc_reg_offset
= NULL
;
8494 tdep
->sc_pc_offset
= -1;
8495 tdep
->sc_sp_offset
= -1;
8497 tdep
->xsave_xcr0_offset
= -1;
8499 tdep
->record_regmap
= i386_record_regmap
;
8501 set_gdbarch_type_align (gdbarch
, i386_type_align
);
8503 /* The format used for `long double' on almost all i386 targets is
8504 the i387 extended floating-point format. In fact, of all targets
8505 in the GCC 2.95 tree, only OSF/1 does it different, and insists
8506 on having a `long double' that's not `long' at all. */
8507 set_gdbarch_long_double_format (gdbarch
, floatformats_i387_ext
);
8509 /* Although the i387 extended floating-point has only 80 significant
8510 bits, a `long double' actually takes up 96, probably to enforce
8512 set_gdbarch_long_double_bit (gdbarch
, 96);
8514 /* Support of bfloat16 format. */
8515 set_gdbarch_bfloat16_format (gdbarch
, floatformats_bfloat16
);
8517 /* Support for floating-point data type variants. */
8518 set_gdbarch_floatformat_for_type (gdbarch
, i386_floatformat_for_type
);
8520 /* Register numbers of various important registers. */
8521 set_gdbarch_sp_regnum (gdbarch
, I386_ESP_REGNUM
); /* %esp */
8522 set_gdbarch_pc_regnum (gdbarch
, I386_EIP_REGNUM
); /* %eip */
8523 set_gdbarch_ps_regnum (gdbarch
, I386_EFLAGS_REGNUM
); /* %eflags */
8524 set_gdbarch_fp0_regnum (gdbarch
, I386_ST0_REGNUM
); /* %st(0) */
8526 /* NOTE: kettenis/20040418: GCC does have two possible register
8527 numbering schemes on the i386: dbx and SVR4. These schemes
8528 differ in how they number %ebp, %esp, %eflags, and the
8529 floating-point registers, and are implemented by the arrays
8530 dbx_register_map[] and svr4_dbx_register_map in
8531 gcc/config/i386.c. GCC also defines a third numbering scheme in
8532 gcc/config/i386.c, which it designates as the "default" register
8533 map used in 64bit mode. This last register numbering scheme is
8534 implemented in dbx64_register_map, and is used for AMD64; see
8537 Currently, each GCC i386 target always uses the same register
8538 numbering scheme across all its supported debugging formats
8539 i.e. SDB (COFF), stabs and DWARF 2. This is because
8540 gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the
8541 DBX_REGISTER_NUMBER macro which is defined by each target's
8542 respective config header in a manner independent of the requested
8543 output debugging format.
8545 This does not match the arrangement below, which presumes that
8546 the SDB and stabs numbering schemes differ from the DWARF and
8547 DWARF 2 ones. The reason for this arrangement is that it is
8548 likely to get the numbering scheme for the target's
8549 default/native debug format right. For targets where GCC is the
8550 native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for
8551 targets where the native toolchain uses a different numbering
8552 scheme for a particular debug format (stabs-in-ELF on Solaris)
8553 the defaults below will have to be overridden, like
8554 i386_elf_init_abi() does. */
8556 /* Use the dbx register numbering scheme for stabs and COFF. */
8557 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
8558 set_gdbarch_sdb_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
8560 /* Use the SVR4 register numbering scheme for DWARF 2. */
8561 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, i386_svr4_dwarf_reg_to_regnum
);
8563 /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to
8564 be in use on any of the supported i386 targets. */
8566 set_gdbarch_print_float_info (gdbarch
, i387_print_float_info
);
8568 set_gdbarch_get_longjmp_target (gdbarch
, i386_get_longjmp_target
);
8570 /* Call dummy code. */
8571 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
8572 set_gdbarch_push_dummy_code (gdbarch
, i386_push_dummy_code
);
8573 set_gdbarch_push_dummy_call (gdbarch
, i386_push_dummy_call
);
8574 set_gdbarch_frame_align (gdbarch
, i386_frame_align
);
8576 set_gdbarch_convert_register_p (gdbarch
, i386_convert_register_p
);
8577 set_gdbarch_register_to_value (gdbarch
, i386_register_to_value
);
8578 set_gdbarch_value_to_register (gdbarch
, i386_value_to_register
);
8580 set_gdbarch_return_value (gdbarch
, i386_return_value
);
8582 set_gdbarch_skip_prologue (gdbarch
, i386_skip_prologue
);
8584 /* Stack grows downward. */
8585 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
8587 set_gdbarch_breakpoint_kind_from_pc (gdbarch
, i386_breakpoint::kind_from_pc
);
8588 set_gdbarch_sw_breakpoint_from_kind (gdbarch
, i386_breakpoint::bp_from_kind
);
8590 set_gdbarch_decr_pc_after_break (gdbarch
, 1);
8591 set_gdbarch_max_insn_length (gdbarch
, I386_MAX_INSN_LEN
);
8593 set_gdbarch_frame_args_skip (gdbarch
, 8);
8595 set_gdbarch_print_insn (gdbarch
, i386_print_insn
);
8597 set_gdbarch_dummy_id (gdbarch
, i386_dummy_id
);
8599 set_gdbarch_unwind_pc (gdbarch
, i386_unwind_pc
);
8601 /* Add the i386 register groups. */
8602 i386_add_reggroups (gdbarch
);
8603 tdep
->register_reggroup_p
= i386_register_reggroup_p
;
8605 /* Helper for function argument information. */
8606 set_gdbarch_fetch_pointer_argument (gdbarch
, i386_fetch_pointer_argument
);
8608 /* Hook the function epilogue frame unwinder. This unwinder is
8609 appended to the list first, so that it supercedes the DWARF
8610 unwinder in function epilogues (where the DWARF unwinder
8611 currently fails). */
8612 frame_unwind_append_unwinder (gdbarch
, &i386_epilogue_frame_unwind
);
8614 /* Hook in the DWARF CFI frame unwinder. This unwinder is appended
8615 to the list before the prologue-based unwinders, so that DWARF
8616 CFI info will be used if it is available. */
8617 dwarf2_append_unwinders (gdbarch
);
8619 frame_base_set_default (gdbarch
, &i386_frame_base
);
8621 /* Pseudo registers may be changed by amd64_init_abi. */
8622 set_gdbarch_pseudo_register_read_value (gdbarch
,
8623 i386_pseudo_register_read_value
);
8624 set_gdbarch_pseudo_register_write (gdbarch
, i386_pseudo_register_write
);
8625 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
8626 i386_ax_pseudo_register_collect
);
8628 set_tdesc_pseudo_register_type (gdbarch
, i386_pseudo_register_type
);
8629 set_tdesc_pseudo_register_name (gdbarch
, i386_pseudo_register_name
);
8631 /* Override the normal target description method to make the AVX
8632 upper halves anonymous. */
8633 set_gdbarch_register_name (gdbarch
, i386_register_name
);
8635 /* Even though the default ABI only includes general-purpose registers,
8636 floating-point registers and the SSE registers, we have to leave a
8637 gap for the upper AVX, MPX and AVX512 registers. */
8638 set_gdbarch_num_regs (gdbarch
, I386_NUM_REGS
);
8640 set_gdbarch_gnu_triplet_regexp (gdbarch
, i386_gnu_triplet_regexp
);
8642 /* Get the x86 target description from INFO. */
8643 tdesc
= info
.target_desc
;
8644 if (! tdesc_has_registers (tdesc
))
8645 tdesc
= i386_target_description (X86_XSTATE_SSE_MASK
, false);
8646 tdep
->tdesc
= tdesc
;
8648 tdep
->num_core_regs
= I386_NUM_GREGS
+ I387_NUM_REGS
;
8649 tdep
->register_names
= i386_register_names
;
8651 /* No upper YMM registers. */
8652 tdep
->ymmh_register_names
= NULL
;
8653 tdep
->ymm0h_regnum
= -1;
8655 /* No upper ZMM registers. */
8656 tdep
->zmmh_register_names
= NULL
;
8657 tdep
->zmm0h_regnum
= -1;
8659 /* No high XMM registers. */
8660 tdep
->xmm_avx512_register_names
= NULL
;
8661 tdep
->xmm16_regnum
= -1;
8663 /* No upper YMM16-31 registers. */
8664 tdep
->ymm16h_register_names
= NULL
;
8665 tdep
->ymm16h_regnum
= -1;
8667 tdep
->num_byte_regs
= 8;
8668 tdep
->num_word_regs
= 8;
8669 tdep
->num_dword_regs
= 0;
8670 tdep
->num_mmx_regs
= 8;
8671 tdep
->num_ymm_regs
= 0;
8673 /* No MPX registers. */
8674 tdep
->bnd0r_regnum
= -1;
8675 tdep
->bndcfgu_regnum
= -1;
8677 /* No AVX512 registers. */
8678 tdep
->k0_regnum
= -1;
8679 tdep
->num_zmm_regs
= 0;
8680 tdep
->num_ymm_avx512_regs
= 0;
8681 tdep
->num_xmm_avx512_regs
= 0;
8683 /* No PKEYS registers */
8684 tdep
->pkru_regnum
= -1;
8685 tdep
->num_pkeys_regs
= 0;
8687 /* No segment base registers. */
8688 tdep
->fsbase_regnum
= -1;
8690 tdesc_arch_data_up tdesc_data
= tdesc_data_alloc ();
8692 set_gdbarch_relocate_instruction (gdbarch
, i386_relocate_instruction
);
8694 set_gdbarch_gen_return_address (gdbarch
, i386_gen_return_address
);
8696 set_gdbarch_insn_is_call (gdbarch
, i386_insn_is_call
);
8697 set_gdbarch_insn_is_ret (gdbarch
, i386_insn_is_ret
);
8698 set_gdbarch_insn_is_jump (gdbarch
, i386_insn_is_jump
);
8700 /* Hook in ABI-specific overrides, if they have been registered.
8701 Note: If INFO specifies a 64 bit arch, this is where we turn
8702 a 32-bit i386 into a 64-bit amd64. */
8703 info
.tdesc_data
= tdesc_data
.get ();
8704 gdbarch_init_osabi (info
, gdbarch
);
8706 if (!i386_validate_tdesc_p (tdep
, tdesc_data
.get ()))
8709 gdbarch_free (gdbarch
);
8713 num_bnd_cooked
= (tdep
->bnd0r_regnum
> 0 ? I387_NUM_BND_REGS
: 0);
8715 /* Wire in pseudo registers. Number of pseudo registers may be
8717 set_gdbarch_num_pseudo_regs (gdbarch
, (tdep
->num_byte_regs
8718 + tdep
->num_word_regs
8719 + tdep
->num_dword_regs
8720 + tdep
->num_mmx_regs
8721 + tdep
->num_ymm_regs
8723 + tdep
->num_ymm_avx512_regs
8724 + tdep
->num_zmm_regs
));
8726 /* Target description may be changed. */
8727 tdesc
= tdep
->tdesc
;
8729 tdesc_use_registers (gdbarch
, tdesc
, std::move (tdesc_data
));
8731 /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */
8732 set_gdbarch_register_reggroup_p (gdbarch
, tdep
->register_reggroup_p
);
8734 /* Make %al the first pseudo-register. */
8735 tdep
->al_regnum
= gdbarch_num_regs (gdbarch
);
8736 tdep
->ax_regnum
= tdep
->al_regnum
+ tdep
->num_byte_regs
;
8738 ymm0_regnum
= tdep
->ax_regnum
+ tdep
->num_word_regs
;
8739 if (tdep
->num_dword_regs
)
8741 /* Support dword pseudo-register if it hasn't been disabled. */
8742 tdep
->eax_regnum
= ymm0_regnum
;
8743 ymm0_regnum
+= tdep
->num_dword_regs
;
8746 tdep
->eax_regnum
= -1;
8748 mm0_regnum
= ymm0_regnum
;
8749 if (tdep
->num_ymm_regs
)
8751 /* Support YMM pseudo-register if it is available. */
8752 tdep
->ymm0_regnum
= ymm0_regnum
;
8753 mm0_regnum
+= tdep
->num_ymm_regs
;
8756 tdep
->ymm0_regnum
= -1;
8758 if (tdep
->num_ymm_avx512_regs
)
8760 /* Support YMM16-31 pseudo registers if available. */
8761 tdep
->ymm16_regnum
= mm0_regnum
;
8762 mm0_regnum
+= tdep
->num_ymm_avx512_regs
;
8765 tdep
->ymm16_regnum
= -1;
8767 if (tdep
->num_zmm_regs
)
8769 /* Support ZMM pseudo-register if it is available. */
8770 tdep
->zmm0_regnum
= mm0_regnum
;
8771 mm0_regnum
+= tdep
->num_zmm_regs
;
8774 tdep
->zmm0_regnum
= -1;
8776 bnd0_regnum
= mm0_regnum
;
8777 if (tdep
->num_mmx_regs
!= 0)
8779 /* Support MMX pseudo-register if MMX hasn't been disabled. */
8780 tdep
->mm0_regnum
= mm0_regnum
;
8781 bnd0_regnum
+= tdep
->num_mmx_regs
;
8784 tdep
->mm0_regnum
= -1;
8786 if (tdep
->bnd0r_regnum
> 0)
8787 tdep
->bnd0_regnum
= bnd0_regnum
;
8789 tdep
-> bnd0_regnum
= -1;
8791 /* Hook in the legacy prologue-based unwinders last (fallback). */
8792 frame_unwind_append_unwinder (gdbarch
, &i386_stack_tramp_frame_unwind
);
8793 frame_unwind_append_unwinder (gdbarch
, &i386_sigtramp_frame_unwind
);
8794 frame_unwind_append_unwinder (gdbarch
, &i386_frame_unwind
);
8796 /* If we have a register mapping, enable the generic core file
8797 support, unless it has already been enabled. */
8798 if (tdep
->gregset_reg_offset
8799 && !gdbarch_iterate_over_regset_sections_p (gdbarch
))
8800 set_gdbarch_iterate_over_regset_sections
8801 (gdbarch
, i386_iterate_over_regset_sections
);
8803 set_gdbarch_fast_tracepoint_valid_at (gdbarch
,
8804 i386_fast_tracepoint_valid_at
);
8811 /* Return the target description for a specified XSAVE feature mask. */
8813 const struct target_desc
*
8814 i386_target_description (uint64_t xcr0
, bool segments
)
8816 static target_desc
*i386_tdescs \
8817 [2/*SSE*/][2/*AVX*/][2/*MPX*/][2/*AVX512*/][2/*PKRU*/][2/*segments*/] = {};
8818 target_desc
**tdesc
;
8820 tdesc
= &i386_tdescs
[(xcr0
& X86_XSTATE_SSE
) ? 1 : 0]
8821 [(xcr0
& X86_XSTATE_AVX
) ? 1 : 0]
8822 [(xcr0
& X86_XSTATE_MPX
) ? 1 : 0]
8823 [(xcr0
& X86_XSTATE_AVX512
) ? 1 : 0]
8824 [(xcr0
& X86_XSTATE_PKRU
) ? 1 : 0]
8828 *tdesc
= i386_create_target_description (xcr0
, false, segments
);
8833 #define MPX_BASE_MASK (~(ULONGEST) 0xfff)
8835 /* Find the bound directory base address. */
8837 static unsigned long
8838 i386_mpx_bd_base (void)
8840 struct regcache
*rcache
;
8841 struct gdbarch_tdep
*tdep
;
8843 enum register_status regstatus
;
8845 rcache
= get_current_regcache ();
8846 tdep
= gdbarch_tdep (rcache
->arch ());
8848 regstatus
= regcache_raw_read_unsigned (rcache
, tdep
->bndcfgu_regnum
, &ret
);
8850 if (regstatus
!= REG_VALID
)
8851 error (_("BNDCFGU register invalid, read status %d."), regstatus
);
8853 return ret
& MPX_BASE_MASK
;
8857 i386_mpx_enabled (void)
8859 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_current_arch ());
8860 const struct target_desc
*tdesc
= tdep
->tdesc
;
8862 return (tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.mpx") != NULL
);
8865 #define MPX_BD_MASK 0xfffffff00000ULL /* select bits [47:20] */
8866 #define MPX_BT_MASK 0x0000000ffff8 /* select bits [19:3] */
8867 #define MPX_BD_MASK_32 0xfffff000 /* select bits [31:12] */
8868 #define MPX_BT_MASK_32 0x00000ffc /* select bits [11:2] */
8870 /* Find the bound table entry given the pointer location and the base
8871 address of the table. */
8874 i386_mpx_get_bt_entry (CORE_ADDR ptr
, CORE_ADDR bd_base
)
8878 CORE_ADDR mpx_bd_mask
, bd_ptr_r_shift
, bd_ptr_l_shift
;
8879 CORE_ADDR bt_mask
, bt_select_r_shift
, bt_select_l_shift
;
8880 CORE_ADDR bd_entry_addr
;
8883 struct gdbarch
*gdbarch
= get_current_arch ();
8884 struct type
*data_ptr_type
= builtin_type (gdbarch
)->builtin_data_ptr
;
8887 if (gdbarch_ptr_bit (gdbarch
) == 64)
8889 mpx_bd_mask
= (CORE_ADDR
) MPX_BD_MASK
;
8890 bd_ptr_r_shift
= 20;
8892 bt_select_r_shift
= 3;
8893 bt_select_l_shift
= 5;
8894 bt_mask
= (CORE_ADDR
) MPX_BT_MASK
;
8896 if ( sizeof (CORE_ADDR
) == 4)
8897 error (_("bound table examination not supported\
8898 for 64-bit process with 32-bit GDB"));
8902 mpx_bd_mask
= MPX_BD_MASK_32
;
8903 bd_ptr_r_shift
= 12;
8905 bt_select_r_shift
= 2;
8906 bt_select_l_shift
= 4;
8907 bt_mask
= MPX_BT_MASK_32
;
8910 offset1
= ((ptr
& mpx_bd_mask
) >> bd_ptr_r_shift
) << bd_ptr_l_shift
;
8911 bd_entry_addr
= bd_base
+ offset1
;
8912 bd_entry
= read_memory_typed_address (bd_entry_addr
, data_ptr_type
);
8914 if ((bd_entry
& 0x1) == 0)
8915 error (_("Invalid bounds directory entry at %s."),
8916 paddress (get_current_arch (), bd_entry_addr
));
8918 /* Clearing status bit. */
8920 bt_addr
= bd_entry
& ~bt_select_r_shift
;
8921 offset2
= ((ptr
& bt_mask
) >> bt_select_r_shift
) << bt_select_l_shift
;
8923 return bt_addr
+ offset2
;
8926 /* Print routine for the mpx bounds. */
8929 i386_mpx_print_bounds (const CORE_ADDR bt_entry
[4])
8931 struct ui_out
*uiout
= current_uiout
;
8933 struct gdbarch
*gdbarch
= get_current_arch ();
8934 CORE_ADDR onecompl
= ~((CORE_ADDR
) 0);
8935 int bounds_in_map
= ((~bt_entry
[1] == 0 && bt_entry
[0] == onecompl
) ? 1 : 0);
8937 if (bounds_in_map
== 1)
8939 uiout
->text ("Null bounds on map:");
8940 uiout
->text (" pointer value = ");
8941 uiout
->field_core_addr ("pointer-value", gdbarch
, bt_entry
[2]);
8947 uiout
->text ("{lbound = ");
8948 uiout
->field_core_addr ("lower-bound", gdbarch
, bt_entry
[0]);
8949 uiout
->text (", ubound = ");
8951 /* The upper bound is stored in 1's complement. */
8952 uiout
->field_core_addr ("upper-bound", gdbarch
, ~bt_entry
[1]);
8953 uiout
->text ("}: pointer value = ");
8954 uiout
->field_core_addr ("pointer-value", gdbarch
, bt_entry
[2]);
8956 if (gdbarch_ptr_bit (gdbarch
) == 64)
8957 size
= ( (~(int64_t) bt_entry
[1]) - (int64_t) bt_entry
[0]);
8959 size
= ( ~((int32_t) bt_entry
[1]) - (int32_t) bt_entry
[0]);
8961 /* In case the bounds are 0x0 and 0xffff... the difference will be -1.
8962 -1 represents in this sense full memory access, and there is no need
8965 size
= (size
> -1 ? size
+ 1 : size
);
8966 uiout
->text (", size = ");
8967 uiout
->field_string ("size", plongest (size
));
8969 uiout
->text (", metadata = ");
8970 uiout
->field_core_addr ("metadata", gdbarch
, bt_entry
[3]);
8975 /* Implement the command "show mpx bound". */
8978 i386_mpx_info_bounds (const char *args
, int from_tty
)
8980 CORE_ADDR bd_base
= 0;
8982 CORE_ADDR bt_entry_addr
= 0;
8983 CORE_ADDR bt_entry
[4];
8985 struct gdbarch
*gdbarch
= get_current_arch ();
8986 struct type
*data_ptr_type
= builtin_type (gdbarch
)->builtin_data_ptr
;
8988 if (gdbarch_bfd_arch_info (gdbarch
)->arch
!= bfd_arch_i386
8989 || !i386_mpx_enabled ())
8991 printf_unfiltered (_("Intel Memory Protection Extensions not "
8992 "supported on this target.\n"));
8998 printf_unfiltered (_("Address of pointer variable expected.\n"));
9002 addr
= parse_and_eval_address (args
);
9004 bd_base
= i386_mpx_bd_base ();
9005 bt_entry_addr
= i386_mpx_get_bt_entry (addr
, bd_base
);
9007 memset (bt_entry
, 0, sizeof (bt_entry
));
9009 for (i
= 0; i
< 4; i
++)
9010 bt_entry
[i
] = read_memory_typed_address (bt_entry_addr
9011 + i
* TYPE_LENGTH (data_ptr_type
),
9014 i386_mpx_print_bounds (bt_entry
);
9017 /* Implement the command "set mpx bound". */
9020 i386_mpx_set_bounds (const char *args
, int from_tty
)
9022 CORE_ADDR bd_base
= 0;
9023 CORE_ADDR addr
, lower
, upper
;
9024 CORE_ADDR bt_entry_addr
= 0;
9025 CORE_ADDR bt_entry
[2];
9026 const char *input
= args
;
9028 struct gdbarch
*gdbarch
= get_current_arch ();
9029 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
9030 struct type
*data_ptr_type
= builtin_type (gdbarch
)->builtin_data_ptr
;
9032 if (gdbarch_bfd_arch_info (gdbarch
)->arch
!= bfd_arch_i386
9033 || !i386_mpx_enabled ())
9034 error (_("Intel Memory Protection Extensions not supported\
9038 error (_("Pointer value expected."));
9040 addr
= value_as_address (parse_to_comma_and_eval (&input
));
9042 if (input
[0] == ',')
9044 if (input
[0] == '\0')
9045 error (_("wrong number of arguments: missing lower and upper bound."));
9046 lower
= value_as_address (parse_to_comma_and_eval (&input
));
9048 if (input
[0] == ',')
9050 if (input
[0] == '\0')
9051 error (_("Wrong number of arguments; Missing upper bound."));
9052 upper
= value_as_address (parse_to_comma_and_eval (&input
));
9054 bd_base
= i386_mpx_bd_base ();
9055 bt_entry_addr
= i386_mpx_get_bt_entry (addr
, bd_base
);
9056 for (i
= 0; i
< 2; i
++)
9057 bt_entry
[i
] = read_memory_typed_address (bt_entry_addr
9058 + i
* TYPE_LENGTH (data_ptr_type
),
9060 bt_entry
[0] = (uint64_t) lower
;
9061 bt_entry
[1] = ~(uint64_t) upper
;
9063 for (i
= 0; i
< 2; i
++)
9064 write_memory_unsigned_integer (bt_entry_addr
9065 + i
* TYPE_LENGTH (data_ptr_type
),
9066 TYPE_LENGTH (data_ptr_type
), byte_order
,
9070 static struct cmd_list_element
*mpx_set_cmdlist
, *mpx_show_cmdlist
;
9072 void _initialize_i386_tdep ();
9074 _initialize_i386_tdep ()
9076 register_gdbarch_init (bfd_arch_i386
, i386_gdbarch_init
);
9078 /* Add the variable that controls the disassembly flavor. */
9079 add_setshow_enum_cmd ("disassembly-flavor", no_class
, valid_flavors
,
9080 &disassembly_flavor
, _("\
9081 Set the disassembly flavor."), _("\
9082 Show the disassembly flavor."), _("\
9083 The valid values are \"att\" and \"intel\", and the default value is \"att\"."),
9085 NULL
, /* FIXME: i18n: */
9086 &setlist
, &showlist
);
9088 /* Add the variable that controls the convention for returning
9090 add_setshow_enum_cmd ("struct-convention", no_class
, valid_conventions
,
9091 &struct_convention
, _("\
9092 Set the convention for returning small structs."), _("\
9093 Show the convention for returning small structs."), _("\
9094 Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\
9097 NULL
, /* FIXME: i18n: */
9098 &setlist
, &showlist
);
9100 /* Add "mpx" prefix for the set commands. */
9102 add_basic_prefix_cmd ("mpx", class_support
, _("\
9103 Set Intel Memory Protection Extensions specific variables."),
9104 &mpx_set_cmdlist
, "set mpx ",
9105 0 /* allow-unknown */, &setlist
);
9107 /* Add "mpx" prefix for the show commands. */
9109 add_show_prefix_cmd ("mpx", class_support
, _("\
9110 Show Intel Memory Protection Extensions specific variables."),
9111 &mpx_show_cmdlist
, "show mpx ",
9112 0 /* allow-unknown */, &showlist
);
9114 /* Add "bound" command for the show mpx commands list. */
9116 add_cmd ("bound", no_class
, i386_mpx_info_bounds
,
9117 "Show the memory bounds for a given array/pointer storage\
9118 in the bound table.",
9121 /* Add "bound" command for the set mpx commands list. */
9123 add_cmd ("bound", no_class
, i386_mpx_set_bounds
,
9124 "Set the memory bounds for a given array/pointer storage\
9125 in the bound table.",
9128 gdbarch_register_osabi (bfd_arch_i386
, 0, GDB_OSABI_SVR4
,
9129 i386_svr4_init_abi
);
9131 /* Initialize the i386-specific register groups. */
9132 i386_init_reggroups ();
9134 /* Tell remote stub that we support XML target description. */
9135 register_remote_support_xml ("i386");