1 /* Intel 386 target-dependent stuff.
3 Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009,
5 2010, 2011 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "opcode/i386.h"
24 #include "arch-utils.h"
26 #include "dummy-frame.h"
27 #include "dwarf2-frame.h"
30 #include "frame-base.h"
31 #include "frame-unwind.h"
39 #include "reggroups.h"
48 #include "exceptions.h"
49 #include "gdb_assert.h"
50 #include "gdb_string.h"
52 #include "i386-tdep.h"
53 #include "i387-tdep.h"
54 #include "i386-xstate.h"
59 #include "features/i386/i386.c"
60 #include "features/i386/i386-avx.c"
61 #include "features/i386/i386-mmx.c"
65 static const char *i386_register_names
[] =
67 "eax", "ecx", "edx", "ebx",
68 "esp", "ebp", "esi", "edi",
69 "eip", "eflags", "cs", "ss",
70 "ds", "es", "fs", "gs",
71 "st0", "st1", "st2", "st3",
72 "st4", "st5", "st6", "st7",
73 "fctrl", "fstat", "ftag", "fiseg",
74 "fioff", "foseg", "fooff", "fop",
75 "xmm0", "xmm1", "xmm2", "xmm3",
76 "xmm4", "xmm5", "xmm6", "xmm7",
80 static const char *i386_ymm_names
[] =
82 "ymm0", "ymm1", "ymm2", "ymm3",
83 "ymm4", "ymm5", "ymm6", "ymm7",
86 static const char *i386_ymmh_names
[] =
88 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
89 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
92 /* Register names for MMX pseudo-registers. */
94 static const char *i386_mmx_names
[] =
96 "mm0", "mm1", "mm2", "mm3",
97 "mm4", "mm5", "mm6", "mm7"
100 /* Register names for byte pseudo-registers. */
102 static const char *i386_byte_names
[] =
104 "al", "cl", "dl", "bl",
105 "ah", "ch", "dh", "bh"
108 /* Register names for word pseudo-registers. */
110 static const char *i386_word_names
[] =
112 "ax", "cx", "dx", "bx",
119 i386_mmx_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
121 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
122 int mm0_regnum
= tdep
->mm0_regnum
;
127 regnum
-= mm0_regnum
;
128 return regnum
>= 0 && regnum
< tdep
->num_mmx_regs
;
134 i386_byte_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
136 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
138 regnum
-= tdep
->al_regnum
;
139 return regnum
>= 0 && regnum
< tdep
->num_byte_regs
;
145 i386_word_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
147 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
149 regnum
-= tdep
->ax_regnum
;
150 return regnum
>= 0 && regnum
< tdep
->num_word_regs
;
153 /* Dword register? */
156 i386_dword_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
158 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
159 int eax_regnum
= tdep
->eax_regnum
;
164 regnum
-= eax_regnum
;
165 return regnum
>= 0 && regnum
< tdep
->num_dword_regs
;
169 i386_ymmh_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
171 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
172 int ymm0h_regnum
= tdep
->ymm0h_regnum
;
174 if (ymm0h_regnum
< 0)
177 regnum
-= ymm0h_regnum
;
178 return regnum
>= 0 && regnum
< tdep
->num_ymm_regs
;
184 i386_ymm_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
186 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
187 int ymm0_regnum
= tdep
->ymm0_regnum
;
192 regnum
-= ymm0_regnum
;
193 return regnum
>= 0 && regnum
< tdep
->num_ymm_regs
;
199 i386_xmm_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
201 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
202 int num_xmm_regs
= I387_NUM_XMM_REGS (tdep
);
204 if (num_xmm_regs
== 0)
207 regnum
-= I387_XMM0_REGNUM (tdep
);
208 return regnum
>= 0 && regnum
< num_xmm_regs
;
212 i386_mxcsr_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
214 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
216 if (I387_NUM_XMM_REGS (tdep
) == 0)
219 return (regnum
== I387_MXCSR_REGNUM (tdep
));
225 i386_fp_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
227 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
229 if (I387_ST0_REGNUM (tdep
) < 0)
232 return (I387_ST0_REGNUM (tdep
) <= regnum
233 && regnum
< I387_FCTRL_REGNUM (tdep
));
237 i386_fpc_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
239 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
241 if (I387_ST0_REGNUM (tdep
) < 0)
244 return (I387_FCTRL_REGNUM (tdep
) <= regnum
245 && regnum
< I387_XMM0_REGNUM (tdep
));
248 /* Return the name of register REGNUM, or the empty string if it is
249 an anonymous register. */
252 i386_register_name (struct gdbarch
*gdbarch
, int regnum
)
254 /* Hide the upper YMM registers. */
255 if (i386_ymmh_regnum_p (gdbarch
, regnum
))
258 return tdesc_register_name (gdbarch
, regnum
);
261 /* Return the name of register REGNUM. */
264 i386_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
266 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
267 if (i386_mmx_regnum_p (gdbarch
, regnum
))
268 return i386_mmx_names
[regnum
- I387_MM0_REGNUM (tdep
)];
269 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
270 return i386_ymm_names
[regnum
- tdep
->ymm0_regnum
];
271 else if (i386_byte_regnum_p (gdbarch
, regnum
))
272 return i386_byte_names
[regnum
- tdep
->al_regnum
];
273 else if (i386_word_regnum_p (gdbarch
, regnum
))
274 return i386_word_names
[regnum
- tdep
->ax_regnum
];
276 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
279 /* Convert a dbx register number REG to the appropriate register
280 number used by GDB. */
283 i386_dbx_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
285 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
287 /* This implements what GCC calls the "default" register map
288 (dbx_register_map[]). */
290 if (reg
>= 0 && reg
<= 7)
292 /* General-purpose registers. The debug info calls %ebp
293 register 4, and %esp register 5. */
300 else if (reg
>= 12 && reg
<= 19)
302 /* Floating-point registers. */
303 return reg
- 12 + I387_ST0_REGNUM (tdep
);
305 else if (reg
>= 21 && reg
<= 28)
308 int ymm0_regnum
= tdep
->ymm0_regnum
;
311 && i386_xmm_regnum_p (gdbarch
, reg
))
312 return reg
- 21 + ymm0_regnum
;
314 return reg
- 21 + I387_XMM0_REGNUM (tdep
);
316 else if (reg
>= 29 && reg
<= 36)
319 return reg
- 29 + I387_MM0_REGNUM (tdep
);
322 /* This will hopefully provoke a warning. */
323 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
326 /* Convert SVR4 register number REG to the appropriate register number
330 i386_svr4_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
332 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
334 /* This implements the GCC register map that tries to be compatible
335 with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */
337 /* The SVR4 register numbering includes %eip and %eflags, and
338 numbers the floating point registers differently. */
339 if (reg
>= 0 && reg
<= 9)
341 /* General-purpose registers. */
344 else if (reg
>= 11 && reg
<= 18)
346 /* Floating-point registers. */
347 return reg
- 11 + I387_ST0_REGNUM (tdep
);
349 else if (reg
>= 21 && reg
<= 36)
351 /* The SSE and MMX registers have the same numbers as with dbx. */
352 return i386_dbx_reg_to_regnum (gdbarch
, reg
);
357 case 37: return I387_FCTRL_REGNUM (tdep
);
358 case 38: return I387_FSTAT_REGNUM (tdep
);
359 case 39: return I387_MXCSR_REGNUM (tdep
);
360 case 40: return I386_ES_REGNUM
;
361 case 41: return I386_CS_REGNUM
;
362 case 42: return I386_SS_REGNUM
;
363 case 43: return I386_DS_REGNUM
;
364 case 44: return I386_FS_REGNUM
;
365 case 45: return I386_GS_REGNUM
;
368 /* This will hopefully provoke a warning. */
369 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
374 /* This is the variable that is set with "set disassembly-flavor", and
375 its legitimate values. */
376 static const char att_flavor
[] = "att";
377 static const char intel_flavor
[] = "intel";
378 static const char *valid_flavors
[] =
384 static const char *disassembly_flavor
= att_flavor
;
387 /* Use the program counter to determine the contents and size of a
388 breakpoint instruction. Return a pointer to a string of bytes that
389 encode a breakpoint instruction, store the length of the string in
390 *LEN and optionally adjust *PC to point to the correct memory
391 location for inserting the breakpoint.
393 On the i386 we have a single breakpoint that fits in a single byte
394 and can be inserted anywhere.
396 This function is 64-bit safe. */
398 static const gdb_byte
*
399 i386_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pc
, int *len
)
401 static gdb_byte break_insn
[] = { 0xcc }; /* int 3 */
403 *len
= sizeof (break_insn
);
407 /* Displaced instruction handling. */
409 /* Skip the legacy instruction prefixes in INSN.
410 Not all prefixes are valid for any particular insn
411 but we needn't care, the insn will fault if it's invalid.
412 The result is a pointer to the first opcode byte,
413 or NULL if we run off the end of the buffer. */
416 i386_skip_prefixes (gdb_byte
*insn
, size_t max_len
)
418 gdb_byte
*end
= insn
+ max_len
;
424 case DATA_PREFIX_OPCODE
:
425 case ADDR_PREFIX_OPCODE
:
426 case CS_PREFIX_OPCODE
:
427 case DS_PREFIX_OPCODE
:
428 case ES_PREFIX_OPCODE
:
429 case FS_PREFIX_OPCODE
:
430 case GS_PREFIX_OPCODE
:
431 case SS_PREFIX_OPCODE
:
432 case LOCK_PREFIX_OPCODE
:
433 case REPE_PREFIX_OPCODE
:
434 case REPNE_PREFIX_OPCODE
:
446 i386_absolute_jmp_p (const gdb_byte
*insn
)
448 /* jmp far (absolute address in operand). */
454 /* jump near, absolute indirect (/4). */
455 if ((insn
[1] & 0x38) == 0x20)
458 /* jump far, absolute indirect (/5). */
459 if ((insn
[1] & 0x38) == 0x28)
467 i386_absolute_call_p (const gdb_byte
*insn
)
469 /* call far, absolute. */
475 /* Call near, absolute indirect (/2). */
476 if ((insn
[1] & 0x38) == 0x10)
479 /* Call far, absolute indirect (/3). */
480 if ((insn
[1] & 0x38) == 0x18)
488 i386_ret_p (const gdb_byte
*insn
)
492 case 0xc2: /* ret near, pop N bytes. */
493 case 0xc3: /* ret near */
494 case 0xca: /* ret far, pop N bytes. */
495 case 0xcb: /* ret far */
496 case 0xcf: /* iret */
505 i386_call_p (const gdb_byte
*insn
)
507 if (i386_absolute_call_p (insn
))
510 /* call near, relative. */
517 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
518 length in bytes. Otherwise, return zero. */
521 i386_syscall_p (const gdb_byte
*insn
, int *lengthp
)
532 /* Some kernels may run one past a syscall insn, so we have to cope.
533 Otherwise this is just simple_displaced_step_copy_insn. */
535 struct displaced_step_closure
*
536 i386_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
537 CORE_ADDR from
, CORE_ADDR to
,
538 struct regcache
*regs
)
540 size_t len
= gdbarch_max_insn_length (gdbarch
);
541 gdb_byte
*buf
= xmalloc (len
);
543 read_memory (from
, buf
, len
);
545 /* GDB may get control back after the insn after the syscall.
546 Presumably this is a kernel bug.
547 If this is a syscall, make sure there's a nop afterwards. */
552 insn
= i386_skip_prefixes (buf
, len
);
553 if (insn
!= NULL
&& i386_syscall_p (insn
, &syscall_length
))
554 insn
[syscall_length
] = NOP_OPCODE
;
557 write_memory (to
, buf
, len
);
561 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
562 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
563 displaced_step_dump_bytes (gdb_stdlog
, buf
, len
);
566 return (struct displaced_step_closure
*) buf
;
569 /* Fix up the state of registers and memory after having single-stepped
570 a displaced instruction. */
573 i386_displaced_step_fixup (struct gdbarch
*gdbarch
,
574 struct displaced_step_closure
*closure
,
575 CORE_ADDR from
, CORE_ADDR to
,
576 struct regcache
*regs
)
578 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
580 /* The offset we applied to the instruction's address.
581 This could well be negative (when viewed as a signed 32-bit
582 value), but ULONGEST won't reflect that, so take care when
584 ULONGEST insn_offset
= to
- from
;
586 /* Since we use simple_displaced_step_copy_insn, our closure is a
587 copy of the instruction. */
588 gdb_byte
*insn
= (gdb_byte
*) closure
;
589 /* The start of the insn, needed in case we see some prefixes. */
590 gdb_byte
*insn_start
= insn
;
593 fprintf_unfiltered (gdb_stdlog
,
594 "displaced: fixup (%s, %s), "
595 "insn = 0x%02x 0x%02x ...\n",
596 paddress (gdbarch
, from
), paddress (gdbarch
, to
),
599 /* The list of issues to contend with here is taken from
600 resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20.
601 Yay for Free Software! */
603 /* Relocate the %eip, if necessary. */
605 /* The instruction recognizers we use assume any leading prefixes
606 have been skipped. */
608 /* This is the size of the buffer in closure. */
609 size_t max_insn_len
= gdbarch_max_insn_length (gdbarch
);
610 gdb_byte
*opcode
= i386_skip_prefixes (insn
, max_insn_len
);
611 /* If there are too many prefixes, just ignore the insn.
612 It will fault when run. */
617 /* Except in the case of absolute or indirect jump or call
618 instructions, or a return instruction, the new eip is relative to
619 the displaced instruction; make it relative. Well, signal
620 handler returns don't need relocation either, but we use the
621 value of %eip to recognize those; see below. */
622 if (! i386_absolute_jmp_p (insn
)
623 && ! i386_absolute_call_p (insn
)
624 && ! i386_ret_p (insn
))
629 regcache_cooked_read_unsigned (regs
, I386_EIP_REGNUM
, &orig_eip
);
631 /* A signal trampoline system call changes the %eip, resuming
632 execution of the main program after the signal handler has
633 returned. That makes them like 'return' instructions; we
634 shouldn't relocate %eip.
636 But most system calls don't, and we do need to relocate %eip.
638 Our heuristic for distinguishing these cases: if stepping
639 over the system call instruction left control directly after
640 the instruction, the we relocate --- control almost certainly
641 doesn't belong in the displaced copy. Otherwise, we assume
642 the instruction has put control where it belongs, and leave
643 it unrelocated. Goodness help us if there are PC-relative
645 if (i386_syscall_p (insn
, &insn_len
)
646 && orig_eip
!= to
+ (insn
- insn_start
) + insn_len
647 /* GDB can get control back after the insn after the syscall.
648 Presumably this is a kernel bug.
649 i386_displaced_step_copy_insn ensures its a nop,
650 we add one to the length for it. */
651 && orig_eip
!= to
+ (insn
- insn_start
) + insn_len
+ 1)
654 fprintf_unfiltered (gdb_stdlog
,
655 "displaced: syscall changed %%eip; "
660 ULONGEST eip
= (orig_eip
- insn_offset
) & 0xffffffffUL
;
662 /* If we just stepped over a breakpoint insn, we don't backup
663 the pc on purpose; this is to match behaviour without
666 regcache_cooked_write_unsigned (regs
, I386_EIP_REGNUM
, eip
);
669 fprintf_unfiltered (gdb_stdlog
,
671 "relocated %%eip from %s to %s\n",
672 paddress (gdbarch
, orig_eip
),
673 paddress (gdbarch
, eip
));
677 /* If the instruction was PUSHFL, then the TF bit will be set in the
678 pushed value, and should be cleared. We'll leave this for later,
679 since GDB already messes up the TF flag when stepping over a
682 /* If the instruction was a call, the return address now atop the
683 stack is the address following the copied instruction. We need
684 to make it the address following the original instruction. */
685 if (i386_call_p (insn
))
689 const ULONGEST retaddr_len
= 4;
691 regcache_cooked_read_unsigned (regs
, I386_ESP_REGNUM
, &esp
);
692 retaddr
= read_memory_unsigned_integer (esp
, retaddr_len
, byte_order
);
693 retaddr
= (retaddr
- insn_offset
) & 0xffffffffUL
;
694 write_memory_unsigned_integer (esp
, retaddr_len
, byte_order
, retaddr
);
697 fprintf_unfiltered (gdb_stdlog
,
698 "displaced: relocated return addr at %s to %s\n",
699 paddress (gdbarch
, esp
),
700 paddress (gdbarch
, retaddr
));
705 append_insns (CORE_ADDR
*to
, ULONGEST len
, const gdb_byte
*buf
)
707 target_write_memory (*to
, buf
, len
);
712 i386_relocate_instruction (struct gdbarch
*gdbarch
,
713 CORE_ADDR
*to
, CORE_ADDR oldloc
)
715 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
716 gdb_byte buf
[I386_MAX_INSN_LEN
];
717 int offset
= 0, rel32
, newrel
;
719 gdb_byte
*insn
= buf
;
721 read_memory (oldloc
, buf
, I386_MAX_INSN_LEN
);
723 insn_length
= gdb_buffered_insn_length (gdbarch
, insn
,
724 I386_MAX_INSN_LEN
, oldloc
);
726 /* Get past the prefixes. */
727 insn
= i386_skip_prefixes (insn
, I386_MAX_INSN_LEN
);
729 /* Adjust calls with 32-bit relative addresses as push/jump, with
730 the address pushed being the location where the original call in
731 the user program would return to. */
734 gdb_byte push_buf
[16];
735 unsigned int ret_addr
;
737 /* Where "ret" in the original code will return to. */
738 ret_addr
= oldloc
+ insn_length
;
739 push_buf
[0] = 0x68; /* pushq $... */
740 memcpy (&push_buf
[1], &ret_addr
, 4);
742 append_insns (to
, 5, push_buf
);
744 /* Convert the relative call to a relative jump. */
747 /* Adjust the destination offset. */
748 rel32
= extract_signed_integer (insn
+ 1, 4, byte_order
);
749 newrel
= (oldloc
- *to
) + rel32
;
750 store_signed_integer (insn
+ 1, 4, byte_order
, newrel
);
753 fprintf_unfiltered (gdb_stdlog
,
754 "Adjusted insn rel32=%s at %s to"
756 hex_string (rel32
), paddress (gdbarch
, oldloc
),
757 hex_string (newrel
), paddress (gdbarch
, *to
));
759 /* Write the adjusted jump into its displaced location. */
760 append_insns (to
, 5, insn
);
764 /* Adjust jumps with 32-bit relative addresses. Calls are already
768 /* Adjust conditional jumps. */
769 else if (insn
[0] == 0x0f && (insn
[1] & 0xf0) == 0x80)
774 rel32
= extract_signed_integer (insn
+ offset
, 4, byte_order
);
775 newrel
= (oldloc
- *to
) + rel32
;
776 store_signed_integer (insn
+ offset
, 4, byte_order
, newrel
);
778 fprintf_unfiltered (gdb_stdlog
,
779 "Adjusted insn rel32=%s at %s to"
781 hex_string (rel32
), paddress (gdbarch
, oldloc
),
782 hex_string (newrel
), paddress (gdbarch
, *to
));
785 /* Write the adjusted instructions into their displaced
787 append_insns (to
, insn_length
, buf
);
791 #ifdef I386_REGNO_TO_SYMMETRY
792 #error "The Sequent Symmetry is no longer supported."
795 /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi
796 and %esp "belong" to the calling function. Therefore these
797 registers should be saved if they're going to be modified. */
799 /* The maximum number of saved registers. This should include all
800 registers mentioned above, and %eip. */
801 #define I386_NUM_SAVED_REGS I386_NUM_GREGS
803 struct i386_frame_cache
811 /* Saved registers. */
812 CORE_ADDR saved_regs
[I386_NUM_SAVED_REGS
];
817 /* Stack space reserved for local variables. */
821 /* Allocate and initialize a frame cache. */
823 static struct i386_frame_cache
*
824 i386_alloc_frame_cache (void)
826 struct i386_frame_cache
*cache
;
829 cache
= FRAME_OBSTACK_ZALLOC (struct i386_frame_cache
);
834 cache
->sp_offset
= -4;
837 /* Saved registers. We initialize these to -1 since zero is a valid
838 offset (that's where %ebp is supposed to be stored). */
839 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
840 cache
->saved_regs
[i
] = -1;
842 cache
->saved_sp_reg
= -1;
843 cache
->pc_in_eax
= 0;
845 /* Frameless until proven otherwise. */
851 /* If the instruction at PC is a jump, return the address of its
852 target. Otherwise, return PC. */
855 i386_follow_jump (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
857 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
862 if (target_read_memory (pc
, &op
, 1))
868 op
= read_memory_unsigned_integer (pc
+ 1, 1, byte_order
);
874 /* Relative jump: if data16 == 0, disp32, else disp16. */
877 delta
= read_memory_integer (pc
+ 2, 2, byte_order
);
879 /* Include the size of the jmp instruction (including the
885 delta
= read_memory_integer (pc
+ 1, 4, byte_order
);
887 /* Include the size of the jmp instruction. */
892 /* Relative jump, disp8 (ignore data16). */
893 delta
= read_memory_integer (pc
+ data16
+ 1, 1, byte_order
);
902 /* Check whether PC points at a prologue for a function returning a
903 structure or union. If so, it updates CACHE and returns the
904 address of the first instruction after the code sequence that
905 removes the "hidden" argument from the stack or CURRENT_PC,
906 whichever is smaller. Otherwise, return PC. */
909 i386_analyze_struct_return (CORE_ADDR pc
, CORE_ADDR current_pc
,
910 struct i386_frame_cache
*cache
)
912 /* Functions that return a structure or union start with:
915 xchgl %eax, (%esp) 0x87 0x04 0x24
916 or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00
918 (the System V compiler puts out the second `xchg' instruction,
919 and the assembler doesn't try to optimize it, so the 'sib' form
920 gets generated). This sequence is used to get the address of the
921 return buffer for a function that returns a structure. */
922 static gdb_byte proto1
[3] = { 0x87, 0x04, 0x24 };
923 static gdb_byte proto2
[4] = { 0x87, 0x44, 0x24, 0x00 };
927 if (current_pc
<= pc
)
930 if (target_read_memory (pc
, &op
, 1))
933 if (op
!= 0x58) /* popl %eax */
936 if (target_read_memory (pc
+ 1, buf
, 4))
939 if (memcmp (buf
, proto1
, 3) != 0 && memcmp (buf
, proto2
, 4) != 0)
942 if (current_pc
== pc
)
944 cache
->sp_offset
+= 4;
948 if (current_pc
== pc
+ 1)
950 cache
->pc_in_eax
= 1;
954 if (buf
[1] == proto1
[1])
961 i386_skip_probe (CORE_ADDR pc
)
963 /* A function may start with
977 if (target_read_memory (pc
, &op
, 1))
980 if (op
== 0x68 || op
== 0x6a)
984 /* Skip past the `pushl' instruction; it has either a one-byte or a
985 four-byte operand, depending on the opcode. */
991 /* Read the following 8 bytes, which should be `call _probe' (6
992 bytes) followed by `addl $4,%esp' (2 bytes). */
993 read_memory (pc
+ delta
, buf
, sizeof (buf
));
994 if (buf
[0] == 0xe8 && buf
[6] == 0xc4 && buf
[7] == 0x4)
995 pc
+= delta
+ sizeof (buf
);
1001 /* GCC 4.1 and later, can put code in the prologue to realign the
1002 stack pointer. Check whether PC points to such code, and update
1003 CACHE accordingly. Return the first instruction after the code
1004 sequence or CURRENT_PC, whichever is smaller. If we don't
1005 recognize the code, return PC. */
1008 i386_analyze_stack_align (CORE_ADDR pc
, CORE_ADDR current_pc
,
1009 struct i386_frame_cache
*cache
)
1011 /* There are 2 code sequences to re-align stack before the frame
1014 1. Use a caller-saved saved register:
1020 2. Use a callee-saved saved register:
1027 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
1029 0x83 0xe4 0xf0 andl $-16, %esp
1030 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
1035 int offset
, offset_and
;
1036 static int regnums
[8] = {
1037 I386_EAX_REGNUM
, /* %eax */
1038 I386_ECX_REGNUM
, /* %ecx */
1039 I386_EDX_REGNUM
, /* %edx */
1040 I386_EBX_REGNUM
, /* %ebx */
1041 I386_ESP_REGNUM
, /* %esp */
1042 I386_EBP_REGNUM
, /* %ebp */
1043 I386_ESI_REGNUM
, /* %esi */
1044 I386_EDI_REGNUM
/* %edi */
1047 if (target_read_memory (pc
, buf
, sizeof buf
))
1050 /* Check caller-saved saved register. The first instruction has
1051 to be "leal 4(%esp), %reg". */
1052 if (buf
[0] == 0x8d && buf
[2] == 0x24 && buf
[3] == 0x4)
1054 /* MOD must be binary 10 and R/M must be binary 100. */
1055 if ((buf
[1] & 0xc7) != 0x44)
1058 /* REG has register number. */
1059 reg
= (buf
[1] >> 3) & 7;
1064 /* Check callee-saved saved register. The first instruction
1065 has to be "pushl %reg". */
1066 if ((buf
[0] & 0xf8) != 0x50)
1072 /* The next instruction has to be "leal 8(%esp), %reg". */
1073 if (buf
[1] != 0x8d || buf
[3] != 0x24 || buf
[4] != 0x8)
1076 /* MOD must be binary 10 and R/M must be binary 100. */
1077 if ((buf
[2] & 0xc7) != 0x44)
1080 /* REG has register number. Registers in pushl and leal have to
1082 if (reg
!= ((buf
[2] >> 3) & 7))
1088 /* Rigister can't be %esp nor %ebp. */
1089 if (reg
== 4 || reg
== 5)
1092 /* The next instruction has to be "andl $-XXX, %esp". */
1093 if (buf
[offset
+ 1] != 0xe4
1094 || (buf
[offset
] != 0x81 && buf
[offset
] != 0x83))
1097 offset_and
= offset
;
1098 offset
+= buf
[offset
] == 0x81 ? 6 : 3;
1100 /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is
1101 0xfc. REG must be binary 110 and MOD must be binary 01. */
1102 if (buf
[offset
] != 0xff
1103 || buf
[offset
+ 2] != 0xfc
1104 || (buf
[offset
+ 1] & 0xf8) != 0x70)
1107 /* R/M has register. Registers in leal and pushl have to be the
1109 if (reg
!= (buf
[offset
+ 1] & 7))
1112 if (current_pc
> pc
+ offset_and
)
1113 cache
->saved_sp_reg
= regnums
[reg
];
1115 return min (pc
+ offset
+ 3, current_pc
);
1118 /* Maximum instruction length we need to handle. */
1119 #define I386_MAX_MATCHED_INSN_LEN 6
1121 /* Instruction description. */
1125 gdb_byte insn
[I386_MAX_MATCHED_INSN_LEN
];
1126 gdb_byte mask
[I386_MAX_MATCHED_INSN_LEN
];
1129 /* Search for the instruction at PC in the list SKIP_INSNS. Return
1130 the first instruction description that matches. Otherwise, return
1133 static struct i386_insn
*
1134 i386_match_insn (CORE_ADDR pc
, struct i386_insn
*skip_insns
)
1136 struct i386_insn
*insn
;
1139 if (target_read_memory (pc
, &op
, 1))
1142 for (insn
= skip_insns
; insn
->len
> 0; insn
++)
1144 if ((op
& insn
->mask
[0]) == insn
->insn
[0])
1146 gdb_byte buf
[I386_MAX_MATCHED_INSN_LEN
- 1];
1147 int insn_matched
= 1;
1150 gdb_assert (insn
->len
> 1);
1151 gdb_assert (insn
->len
<= I386_MAX_MATCHED_INSN_LEN
);
1153 if (target_read_memory (pc
+ 1, buf
, insn
->len
- 1))
1156 for (i
= 1; i
< insn
->len
; i
++)
1158 if ((buf
[i
- 1] & insn
->mask
[i
]) != insn
->insn
[i
])
1170 /* Some special instructions that might be migrated by GCC into the
1171 part of the prologue that sets up the new stack frame. Because the
1172 stack frame hasn't been setup yet, no registers have been saved
1173 yet, and only the scratch registers %eax, %ecx and %edx can be
1176 struct i386_insn i386_frame_setup_skip_insns
[] =
1178 /* Check for `movb imm8, r' and `movl imm32, r'.
1180 ??? Should we handle 16-bit operand-sizes here? */
1182 /* `movb imm8, %al' and `movb imm8, %ah' */
1183 /* `movb imm8, %cl' and `movb imm8, %ch' */
1184 { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } },
1185 /* `movb imm8, %dl' and `movb imm8, %dh' */
1186 { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } },
1187 /* `movl imm32, %eax' and `movl imm32, %ecx' */
1188 { 5, { 0xb8 }, { 0xfe } },
1189 /* `movl imm32, %edx' */
1190 { 5, { 0xba }, { 0xff } },
1192 /* Check for `mov imm32, r32'. Note that there is an alternative
1193 encoding for `mov m32, %eax'.
1195 ??? Should we handle SIB adressing here?
1196 ??? Should we handle 16-bit operand-sizes here? */
1198 /* `movl m32, %eax' */
1199 { 5, { 0xa1 }, { 0xff } },
1200 /* `movl m32, %eax' and `mov; m32, %ecx' */
1201 { 6, { 0x89, 0x05 }, {0xff, 0xf7 } },
1202 /* `movl m32, %edx' */
1203 { 6, { 0x89, 0x15 }, {0xff, 0xff } },
1205 /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'.
1206 Because of the symmetry, there are actually two ways to encode
1207 these instructions; opcode bytes 0x29 and 0x2b for `subl' and
1208 opcode bytes 0x31 and 0x33 for `xorl'. */
1210 /* `subl %eax, %eax' */
1211 { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } },
1212 /* `subl %ecx, %ecx' */
1213 { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } },
1214 /* `subl %edx, %edx' */
1215 { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } },
1216 /* `xorl %eax, %eax' */
1217 { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } },
1218 /* `xorl %ecx, %ecx' */
1219 { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } },
1220 /* `xorl %edx, %edx' */
1221 { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } },
1226 /* Check whether PC points to a no-op instruction. */
1228 i386_skip_noop (CORE_ADDR pc
)
1233 if (target_read_memory (pc
, &op
, 1))
1239 /* Ignore `nop' instruction. */
1243 if (target_read_memory (pc
, &op
, 1))
1247 /* Ignore no-op instruction `mov %edi, %edi'.
1248 Microsoft system dlls often start with
1249 a `mov %edi,%edi' instruction.
1250 The 5 bytes before the function start are
1251 filled with `nop' instructions.
1252 This pattern can be used for hot-patching:
1253 The `mov %edi, %edi' instruction can be replaced by a
1254 near jump to the location of the 5 `nop' instructions
1255 which can be replaced by a 32-bit jump to anywhere
1256 in the 32-bit address space. */
1258 else if (op
== 0x8b)
1260 if (target_read_memory (pc
+ 1, &op
, 1))
1266 if (target_read_memory (pc
, &op
, 1))
1276 /* Check whether PC points at a code that sets up a new stack frame.
1277 If so, it updates CACHE and returns the address of the first
1278 instruction after the sequence that sets up the frame or LIMIT,
1279 whichever is smaller. If we don't recognize the code, return PC. */
1282 i386_analyze_frame_setup (struct gdbarch
*gdbarch
,
1283 CORE_ADDR pc
, CORE_ADDR limit
,
1284 struct i386_frame_cache
*cache
)
1286 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1287 struct i386_insn
*insn
;
1294 if (target_read_memory (pc
, &op
, 1))
1297 if (op
== 0x55) /* pushl %ebp */
1299 /* Take into account that we've executed the `pushl %ebp' that
1300 starts this instruction sequence. */
1301 cache
->saved_regs
[I386_EBP_REGNUM
] = 0;
1302 cache
->sp_offset
+= 4;
1305 /* If that's all, return now. */
1309 /* Check for some special instructions that might be migrated by
1310 GCC into the prologue and skip them. At this point in the
1311 prologue, code should only touch the scratch registers %eax,
1312 %ecx and %edx, so while the number of posibilities is sheer,
1315 Make sure we only skip these instructions if we later see the
1316 `movl %esp, %ebp' that actually sets up the frame. */
1317 while (pc
+ skip
< limit
)
1319 insn
= i386_match_insn (pc
+ skip
, i386_frame_setup_skip_insns
);
1326 /* If that's all, return now. */
1327 if (limit
<= pc
+ skip
)
1330 if (target_read_memory (pc
+ skip
, &op
, 1))
1333 /* Check for `movl %esp, %ebp' -- can be written in two ways. */
1337 if (read_memory_unsigned_integer (pc
+ skip
+ 1, 1, byte_order
)
1342 if (read_memory_unsigned_integer (pc
+ skip
+ 1, 1, byte_order
)
1350 /* OK, we actually have a frame. We just don't know how large
1351 it is yet. Set its size to zero. We'll adjust it if
1352 necessary. We also now commit to skipping the special
1353 instructions mentioned before. */
1357 /* If that's all, return now. */
1361 /* Check for stack adjustment
1365 NOTE: You can't subtract a 16-bit immediate from a 32-bit
1366 reg, so we don't have to worry about a data16 prefix. */
1367 if (target_read_memory (pc
, &op
, 1))
1371 /* `subl' with 8-bit immediate. */
1372 if (read_memory_unsigned_integer (pc
+ 1, 1, byte_order
) != 0xec)
1373 /* Some instruction starting with 0x83 other than `subl'. */
1376 /* `subl' with signed 8-bit immediate (though it wouldn't
1377 make sense to be negative). */
1378 cache
->locals
= read_memory_integer (pc
+ 2, 1, byte_order
);
1381 else if (op
== 0x81)
1383 /* Maybe it is `subl' with a 32-bit immediate. */
1384 if (read_memory_unsigned_integer (pc
+ 1, 1, byte_order
) != 0xec)
1385 /* Some instruction starting with 0x81 other than `subl'. */
1388 /* It is `subl' with a 32-bit immediate. */
1389 cache
->locals
= read_memory_integer (pc
+ 2, 4, byte_order
);
1394 /* Some instruction other than `subl'. */
1398 else if (op
== 0xc8) /* enter */
1400 cache
->locals
= read_memory_unsigned_integer (pc
+ 1, 2, byte_order
);
1407 /* Check whether PC points at code that saves registers on the stack.
1408 If so, it updates CACHE and returns the address of the first
1409 instruction after the register saves or CURRENT_PC, whichever is
1410 smaller. Otherwise, return PC. */
1413 i386_analyze_register_saves (CORE_ADDR pc
, CORE_ADDR current_pc
,
1414 struct i386_frame_cache
*cache
)
1416 CORE_ADDR offset
= 0;
1420 if (cache
->locals
> 0)
1421 offset
-= cache
->locals
;
1422 for (i
= 0; i
< 8 && pc
< current_pc
; i
++)
1424 if (target_read_memory (pc
, &op
, 1))
1426 if (op
< 0x50 || op
> 0x57)
1430 cache
->saved_regs
[op
- 0x50] = offset
;
1431 cache
->sp_offset
+= 4;
1438 /* Do a full analysis of the prologue at PC and update CACHE
1439 accordingly. Bail out early if CURRENT_PC is reached. Return the
1440 address where the analysis stopped.
1442 We handle these cases:
1444 The startup sequence can be at the start of the function, or the
1445 function can start with a branch to startup code at the end.
1447 %ebp can be set up with either the 'enter' instruction, or "pushl
1448 %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was
1449 once used in the System V compiler).
1451 Local space is allocated just below the saved %ebp by either the
1452 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a
1453 16-bit unsigned argument for space to allocate, and the 'addl'
1454 instruction could have either a signed byte, or 32-bit immediate.
1456 Next, the registers used by this function are pushed. With the
1457 System V compiler they will always be in the order: %edi, %esi,
1458 %ebx (and sometimes a harmless bug causes it to also save but not
1459 restore %eax); however, the code below is willing to see the pushes
1460 in any order, and will handle up to 8 of them.
1462 If the setup sequence is at the end of the function, then the next
1463 instruction will be a branch back to the start. */
1466 i386_analyze_prologue (struct gdbarch
*gdbarch
,
1467 CORE_ADDR pc
, CORE_ADDR current_pc
,
1468 struct i386_frame_cache
*cache
)
1470 pc
= i386_skip_noop (pc
);
1471 pc
= i386_follow_jump (gdbarch
, pc
);
1472 pc
= i386_analyze_struct_return (pc
, current_pc
, cache
);
1473 pc
= i386_skip_probe (pc
);
1474 pc
= i386_analyze_stack_align (pc
, current_pc
, cache
);
1475 pc
= i386_analyze_frame_setup (gdbarch
, pc
, current_pc
, cache
);
1476 return i386_analyze_register_saves (pc
, current_pc
, cache
);
1479 /* Return PC of first real instruction. */
1482 i386_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
1484 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1486 static gdb_byte pic_pat
[6] =
1488 0xe8, 0, 0, 0, 0, /* call 0x0 */
1489 0x5b, /* popl %ebx */
1491 struct i386_frame_cache cache
;
1497 pc
= i386_analyze_prologue (gdbarch
, start_pc
, 0xffffffff, &cache
);
1498 if (cache
.locals
< 0)
1501 /* Found valid frame setup. */
1503 /* The native cc on SVR4 in -K PIC mode inserts the following code
1504 to get the address of the global offset table (GOT) into register
1509 movl %ebx,x(%ebp) (optional)
1512 This code is with the rest of the prologue (at the end of the
1513 function), so we have to skip it to get to the first real
1514 instruction at the start of the function. */
1516 for (i
= 0; i
< 6; i
++)
1518 if (target_read_memory (pc
+ i
, &op
, 1))
1521 if (pic_pat
[i
] != op
)
1528 if (target_read_memory (pc
+ delta
, &op
, 1))
1531 if (op
== 0x89) /* movl %ebx, x(%ebp) */
1533 op
= read_memory_unsigned_integer (pc
+ delta
+ 1, 1, byte_order
);
1535 if (op
== 0x5d) /* One byte offset from %ebp. */
1537 else if (op
== 0x9d) /* Four byte offset from %ebp. */
1539 else /* Unexpected instruction. */
1542 if (target_read_memory (pc
+ delta
, &op
, 1))
1547 if (delta
> 0 && op
== 0x81
1548 && read_memory_unsigned_integer (pc
+ delta
+ 1, 1, byte_order
)
1555 /* If the function starts with a branch (to startup code at the end)
1556 the last instruction should bring us back to the first
1557 instruction of the real code. */
1558 if (i386_follow_jump (gdbarch
, start_pc
) != start_pc
)
1559 pc
= i386_follow_jump (gdbarch
, pc
);
1564 /* Check that the code pointed to by PC corresponds to a call to
1565 __main, skip it if so. Return PC otherwise. */
1568 i386_skip_main_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1570 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1573 if (target_read_memory (pc
, &op
, 1))
1579 if (target_read_memory (pc
+ 1, buf
, sizeof buf
) == 0)
1581 /* Make sure address is computed correctly as a 32bit
1582 integer even if CORE_ADDR is 64 bit wide. */
1583 struct minimal_symbol
*s
;
1584 CORE_ADDR call_dest
;
1586 call_dest
= pc
+ 5 + extract_signed_integer (buf
, 4, byte_order
);
1587 call_dest
= call_dest
& 0xffffffffU
;
1588 s
= lookup_minimal_symbol_by_pc (call_dest
);
1590 && SYMBOL_LINKAGE_NAME (s
) != NULL
1591 && strcmp (SYMBOL_LINKAGE_NAME (s
), "__main") == 0)
1599 /* This function is 64-bit safe. */
1602 i386_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1606 frame_unwind_register (next_frame
, gdbarch_pc_regnum (gdbarch
), buf
);
1607 return extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
1611 /* Normal frames. */
1614 i386_frame_cache_1 (struct frame_info
*this_frame
,
1615 struct i386_frame_cache
*cache
)
1617 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1618 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1622 cache
->pc
= get_frame_func (this_frame
);
1624 /* In principle, for normal frames, %ebp holds the frame pointer,
1625 which holds the base address for the current stack frame.
1626 However, for functions that don't need it, the frame pointer is
1627 optional. For these "frameless" functions the frame pointer is
1628 actually the frame pointer of the calling frame. Signal
1629 trampolines are just a special case of a "frameless" function.
1630 They (usually) share their frame pointer with the frame that was
1631 in progress when the signal occurred. */
1633 get_frame_register (this_frame
, I386_EBP_REGNUM
, buf
);
1634 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
);
1635 if (cache
->base
== 0)
1638 /* For normal frames, %eip is stored at 4(%ebp). */
1639 cache
->saved_regs
[I386_EIP_REGNUM
] = 4;
1642 i386_analyze_prologue (gdbarch
, cache
->pc
, get_frame_pc (this_frame
),
1645 if (cache
->locals
< 0)
1647 /* We didn't find a valid frame, which means that CACHE->base
1648 currently holds the frame pointer for our calling frame. If
1649 we're at the start of a function, or somewhere half-way its
1650 prologue, the function's frame probably hasn't been fully
1651 setup yet. Try to reconstruct the base address for the stack
1652 frame by looking at the stack pointer. For truly "frameless"
1653 functions this might work too. */
1655 if (cache
->saved_sp_reg
!= -1)
1657 /* Saved stack pointer has been saved. */
1658 get_frame_register (this_frame
, cache
->saved_sp_reg
, buf
);
1659 cache
->saved_sp
= extract_unsigned_integer (buf
, 4, byte_order
);
1661 /* We're halfway aligning the stack. */
1662 cache
->base
= ((cache
->saved_sp
- 4) & 0xfffffff0) - 4;
1663 cache
->saved_regs
[I386_EIP_REGNUM
] = cache
->saved_sp
- 4;
1665 /* This will be added back below. */
1666 cache
->saved_regs
[I386_EIP_REGNUM
] -= cache
->base
;
1668 else if (cache
->pc
!= 0
1669 || target_read_memory (get_frame_pc (this_frame
), buf
, 1))
1671 /* We're in a known function, but did not find a frame
1672 setup. Assume that the function does not use %ebp.
1673 Alternatively, we may have jumped to an invalid
1674 address; in that case there is definitely no new
1676 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
1677 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
)
1681 /* We're in an unknown function. We could not find the start
1682 of the function to analyze the prologue; our best option is
1683 to assume a typical frame layout with the caller's %ebp
1685 cache
->saved_regs
[I386_EBP_REGNUM
] = 0;
1688 if (cache
->saved_sp_reg
!= -1)
1690 /* Saved stack pointer has been saved (but the SAVED_SP_REG
1691 register may be unavailable). */
1692 if (cache
->saved_sp
== 0
1693 && frame_register_read (this_frame
, cache
->saved_sp_reg
, buf
))
1694 cache
->saved_sp
= extract_unsigned_integer (buf
, 4, byte_order
);
1696 /* Now that we have the base address for the stack frame we can
1697 calculate the value of %esp in the calling frame. */
1698 else if (cache
->saved_sp
== 0)
1699 cache
->saved_sp
= cache
->base
+ 8;
1701 /* Adjust all the saved registers such that they contain addresses
1702 instead of offsets. */
1703 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
1704 if (cache
->saved_regs
[i
] != -1)
1705 cache
->saved_regs
[i
] += cache
->base
;
1710 static struct i386_frame_cache
*
1711 i386_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1713 volatile struct gdb_exception ex
;
1714 struct i386_frame_cache
*cache
;
1719 cache
= i386_alloc_frame_cache ();
1720 *this_cache
= cache
;
1722 TRY_CATCH (ex
, RETURN_MASK_ERROR
)
1724 i386_frame_cache_1 (this_frame
, cache
);
1726 if (ex
.reason
< 0 && ex
.error
!= NOT_AVAILABLE_ERROR
)
1727 throw_exception (ex
);
1733 i386_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
1734 struct frame_id
*this_id
)
1736 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1738 /* This marks the outermost frame. */
1739 if (cache
->base
== 0)
1742 /* See the end of i386_push_dummy_call. */
1743 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
1746 static enum unwind_stop_reason
1747 i386_frame_unwind_stop_reason (struct frame_info
*this_frame
,
1750 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1753 return UNWIND_UNAVAILABLE
;
1755 /* This marks the outermost frame. */
1756 if (cache
->base
== 0)
1757 return UNWIND_OUTERMOST
;
1759 return UNWIND_NO_REASON
;
1762 static struct value
*
1763 i386_frame_prev_register (struct frame_info
*this_frame
, void **this_cache
,
1766 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1768 gdb_assert (regnum
>= 0);
1770 /* The System V ABI says that:
1772 "The flags register contains the system flags, such as the
1773 direction flag and the carry flag. The direction flag must be
1774 set to the forward (that is, zero) direction before entry and
1775 upon exit from a function. Other user flags have no specified
1776 role in the standard calling sequence and are not preserved."
1778 To guarantee the "upon exit" part of that statement we fake a
1779 saved flags register that has its direction flag cleared.
1781 Note that GCC doesn't seem to rely on the fact that the direction
1782 flag is cleared after a function return; it always explicitly
1783 clears the flag before operations where it matters.
1785 FIXME: kettenis/20030316: I'm not quite sure whether this is the
1786 right thing to do. The way we fake the flags register here makes
1787 it impossible to change it. */
1789 if (regnum
== I386_EFLAGS_REGNUM
)
1793 val
= get_frame_register_unsigned (this_frame
, regnum
);
1795 return frame_unwind_got_constant (this_frame
, regnum
, val
);
1798 if (regnum
== I386_EIP_REGNUM
&& cache
->pc_in_eax
)
1799 return frame_unwind_got_register (this_frame
, regnum
, I386_EAX_REGNUM
);
1801 if (regnum
== I386_ESP_REGNUM
)
1803 /* If the SP has been saved, but we don't know where, then this
1804 means that SAVED_SP_REG register was found unavailable back
1805 when we built the cache. */
1806 if (cache
->saved_sp
== 0 && cache
->saved_sp_reg
!= -1)
1807 return frame_unwind_got_register (this_frame
, regnum
,
1808 cache
->saved_sp_reg
);
1810 return frame_unwind_got_constant (this_frame
, regnum
,
1814 if (regnum
< I386_NUM_SAVED_REGS
&& cache
->saved_regs
[regnum
] != -1)
1815 return frame_unwind_got_memory (this_frame
, regnum
,
1816 cache
->saved_regs
[regnum
]);
1818 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
1821 static const struct frame_unwind i386_frame_unwind
=
1824 i386_frame_unwind_stop_reason
,
1826 i386_frame_prev_register
,
1828 default_frame_sniffer
1831 /* Normal frames, but in a function epilogue. */
1833 /* The epilogue is defined here as the 'ret' instruction, which will
1834 follow any instruction such as 'leave' or 'pop %ebp' that destroys
1835 the function's stack frame. */
1838 i386_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1842 if (target_read_memory (pc
, &insn
, 1))
1843 return 0; /* Can't read memory at pc. */
1845 if (insn
!= 0xc3) /* 'ret' instruction. */
1852 i386_epilogue_frame_sniffer (const struct frame_unwind
*self
,
1853 struct frame_info
*this_frame
,
1854 void **this_prologue_cache
)
1856 if (frame_relative_level (this_frame
) == 0)
1857 return i386_in_function_epilogue_p (get_frame_arch (this_frame
),
1858 get_frame_pc (this_frame
));
1863 static struct i386_frame_cache
*
1864 i386_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1866 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1867 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1868 volatile struct gdb_exception ex
;
1869 struct i386_frame_cache
*cache
;
1875 cache
= i386_alloc_frame_cache ();
1876 *this_cache
= cache
;
1878 TRY_CATCH (ex
, RETURN_MASK_ERROR
)
1880 /* Cache base will be %esp plus cache->sp_offset (-4). */
1881 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
1882 cache
->base
= extract_unsigned_integer (buf
, 4,
1883 byte_order
) + cache
->sp_offset
;
1885 /* Cache pc will be the frame func. */
1886 cache
->pc
= get_frame_pc (this_frame
);
1888 /* The saved %esp will be at cache->base plus 8. */
1889 cache
->saved_sp
= cache
->base
+ 8;
1891 /* The saved %eip will be at cache->base plus 4. */
1892 cache
->saved_regs
[I386_EIP_REGNUM
] = cache
->base
+ 4;
1896 if (ex
.reason
< 0 && ex
.error
!= NOT_AVAILABLE_ERROR
)
1897 throw_exception (ex
);
1902 static enum unwind_stop_reason
1903 i386_epilogue_frame_unwind_stop_reason (struct frame_info
*this_frame
,
1906 struct i386_frame_cache
*cache
1907 = i386_epilogue_frame_cache (this_frame
, this_cache
);
1910 return UNWIND_UNAVAILABLE
;
1912 return UNWIND_NO_REASON
;
1916 i386_epilogue_frame_this_id (struct frame_info
*this_frame
,
1918 struct frame_id
*this_id
)
1920 struct i386_frame_cache
*cache
= i386_epilogue_frame_cache (this_frame
,
1926 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
1929 static const struct frame_unwind i386_epilogue_frame_unwind
=
1932 i386_epilogue_frame_unwind_stop_reason
,
1933 i386_epilogue_frame_this_id
,
1934 i386_frame_prev_register
,
1936 i386_epilogue_frame_sniffer
1940 /* Signal trampolines. */
1942 static struct i386_frame_cache
*
1943 i386_sigtramp_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1945 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1946 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1947 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1948 volatile struct gdb_exception ex
;
1949 struct i386_frame_cache
*cache
;
1956 cache
= i386_alloc_frame_cache ();
1958 TRY_CATCH (ex
, RETURN_MASK_ERROR
)
1960 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
1961 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
) - 4;
1963 addr
= tdep
->sigcontext_addr (this_frame
);
1964 if (tdep
->sc_reg_offset
)
1968 gdb_assert (tdep
->sc_num_regs
<= I386_NUM_SAVED_REGS
);
1970 for (i
= 0; i
< tdep
->sc_num_regs
; i
++)
1971 if (tdep
->sc_reg_offset
[i
] != -1)
1972 cache
->saved_regs
[i
] = addr
+ tdep
->sc_reg_offset
[i
];
1976 cache
->saved_regs
[I386_EIP_REGNUM
] = addr
+ tdep
->sc_pc_offset
;
1977 cache
->saved_regs
[I386_ESP_REGNUM
] = addr
+ tdep
->sc_sp_offset
;
1982 if (ex
.reason
< 0 && ex
.error
!= NOT_AVAILABLE_ERROR
)
1983 throw_exception (ex
);
1985 *this_cache
= cache
;
1989 static enum unwind_stop_reason
1990 i386_sigtramp_frame_unwind_stop_reason (struct frame_info
*this_frame
,
1993 struct i386_frame_cache
*cache
=
1994 i386_sigtramp_frame_cache (this_frame
, this_cache
);
1997 return UNWIND_UNAVAILABLE
;
1999 return UNWIND_NO_REASON
;
2003 i386_sigtramp_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2004 struct frame_id
*this_id
)
2006 struct i386_frame_cache
*cache
=
2007 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2012 /* See the end of i386_push_dummy_call. */
2013 (*this_id
) = frame_id_build (cache
->base
+ 8, get_frame_pc (this_frame
));
2016 static struct value
*
2017 i386_sigtramp_frame_prev_register (struct frame_info
*this_frame
,
2018 void **this_cache
, int regnum
)
2020 /* Make sure we've initialized the cache. */
2021 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2023 return i386_frame_prev_register (this_frame
, this_cache
, regnum
);
2027 i386_sigtramp_frame_sniffer (const struct frame_unwind
*self
,
2028 struct frame_info
*this_frame
,
2029 void **this_prologue_cache
)
2031 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (this_frame
));
2033 /* We shouldn't even bother if we don't have a sigcontext_addr
2035 if (tdep
->sigcontext_addr
== NULL
)
2038 if (tdep
->sigtramp_p
!= NULL
)
2040 if (tdep
->sigtramp_p (this_frame
))
2044 if (tdep
->sigtramp_start
!= 0)
2046 CORE_ADDR pc
= get_frame_pc (this_frame
);
2048 gdb_assert (tdep
->sigtramp_end
!= 0);
2049 if (pc
>= tdep
->sigtramp_start
&& pc
< tdep
->sigtramp_end
)
2056 static const struct frame_unwind i386_sigtramp_frame_unwind
=
2059 i386_sigtramp_frame_unwind_stop_reason
,
2060 i386_sigtramp_frame_this_id
,
2061 i386_sigtramp_frame_prev_register
,
2063 i386_sigtramp_frame_sniffer
2068 i386_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
2070 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
2075 static const struct frame_base i386_frame_base
=
2078 i386_frame_base_address
,
2079 i386_frame_base_address
,
2080 i386_frame_base_address
2083 static struct frame_id
2084 i386_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
2088 fp
= get_frame_register_unsigned (this_frame
, I386_EBP_REGNUM
);
2090 /* See the end of i386_push_dummy_call. */
2091 return frame_id_build (fp
+ 8, get_frame_pc (this_frame
));
2095 /* Figure out where the longjmp will land. Slurp the args out of the
2096 stack. We expect the first arg to be a pointer to the jmp_buf
2097 structure from which we extract the address that we will land at.
2098 This address is copied into PC. This routine returns non-zero on
2102 i386_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
2105 CORE_ADDR sp
, jb_addr
;
2106 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2107 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2108 int jb_pc_offset
= gdbarch_tdep (gdbarch
)->jb_pc_offset
;
2110 /* If JB_PC_OFFSET is -1, we have no way to find out where the
2111 longjmp will land. */
2112 if (jb_pc_offset
== -1)
2115 get_frame_register (frame
, I386_ESP_REGNUM
, buf
);
2116 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
2117 if (target_read_memory (sp
+ 4, buf
, 4))
2120 jb_addr
= extract_unsigned_integer (buf
, 4, byte_order
);
2121 if (target_read_memory (jb_addr
+ jb_pc_offset
, buf
, 4))
2124 *pc
= extract_unsigned_integer (buf
, 4, byte_order
);
2129 /* Check whether TYPE must be 16-byte-aligned when passed as a
2130 function argument. 16-byte vectors, _Decimal128 and structures or
2131 unions containing such types must be 16-byte-aligned; other
2132 arguments are 4-byte-aligned. */
2135 i386_16_byte_align_p (struct type
*type
)
2137 type
= check_typedef (type
);
2138 if ((TYPE_CODE (type
) == TYPE_CODE_DECFLOAT
2139 || (TYPE_CODE (type
) == TYPE_CODE_ARRAY
&& TYPE_VECTOR (type
)))
2140 && TYPE_LENGTH (type
) == 16)
2142 if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
2143 return i386_16_byte_align_p (TYPE_TARGET_TYPE (type
));
2144 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
2145 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
2148 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
2150 if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type
, i
)))
2158 i386_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2159 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
2160 struct value
**args
, CORE_ADDR sp
, int struct_return
,
2161 CORE_ADDR struct_addr
)
2163 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2169 /* Determine the total space required for arguments and struct
2170 return address in a first pass (allowing for 16-byte-aligned
2171 arguments), then push arguments in a second pass. */
2173 for (write_pass
= 0; write_pass
< 2; write_pass
++)
2175 int args_space_used
= 0;
2176 int have_16_byte_aligned_arg
= 0;
2182 /* Push value address. */
2183 store_unsigned_integer (buf
, 4, byte_order
, struct_addr
);
2184 write_memory (sp
, buf
, 4);
2185 args_space_used
+= 4;
2191 for (i
= 0; i
< nargs
; i
++)
2193 int len
= TYPE_LENGTH (value_enclosing_type (args
[i
]));
2197 if (i386_16_byte_align_p (value_enclosing_type (args
[i
])))
2198 args_space_used
= align_up (args_space_used
, 16);
2200 write_memory (sp
+ args_space_used
,
2201 value_contents_all (args
[i
]), len
);
2202 /* The System V ABI says that:
2204 "An argument's size is increased, if necessary, to make it a
2205 multiple of [32-bit] words. This may require tail padding,
2206 depending on the size of the argument."
2208 This makes sure the stack stays word-aligned. */
2209 args_space_used
+= align_up (len
, 4);
2213 if (i386_16_byte_align_p (value_enclosing_type (args
[i
])))
2215 args_space
= align_up (args_space
, 16);
2216 have_16_byte_aligned_arg
= 1;
2218 args_space
+= align_up (len
, 4);
2224 if (have_16_byte_aligned_arg
)
2225 args_space
= align_up (args_space
, 16);
2230 /* Store return address. */
2232 store_unsigned_integer (buf
, 4, byte_order
, bp_addr
);
2233 write_memory (sp
, buf
, 4);
2235 /* Finally, update the stack pointer... */
2236 store_unsigned_integer (buf
, 4, byte_order
, sp
);
2237 regcache_cooked_write (regcache
, I386_ESP_REGNUM
, buf
);
2239 /* ...and fake a frame pointer. */
2240 regcache_cooked_write (regcache
, I386_EBP_REGNUM
, buf
);
2242 /* MarkK wrote: This "+ 8" is all over the place:
2243 (i386_frame_this_id, i386_sigtramp_frame_this_id,
2244 i386_dummy_id). It's there, since all frame unwinders for
2245 a given target have to agree (within a certain margin) on the
2246 definition of the stack address of a frame. Otherwise frame id
2247 comparison might not work correctly. Since DWARF2/GCC uses the
2248 stack address *before* the function call as a frame's CFA. On
2249 the i386, when %ebp is used as a frame pointer, the offset
2250 between the contents %ebp and the CFA as defined by GCC. */
2254 /* These registers are used for returning integers (and on some
2255 targets also for returning `struct' and `union' values when their
2256 size and alignment match an integer type). */
2257 #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */
2258 #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */
2260 /* Read, for architecture GDBARCH, a function return value of TYPE
2261 from REGCACHE, and copy that into VALBUF. */
2264 i386_extract_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
2265 struct regcache
*regcache
, gdb_byte
*valbuf
)
2267 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2268 int len
= TYPE_LENGTH (type
);
2269 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
2271 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2273 if (tdep
->st0_regnum
< 0)
2275 warning (_("Cannot find floating-point return value."));
2276 memset (valbuf
, 0, len
);
2280 /* Floating-point return values can be found in %st(0). Convert
2281 its contents to the desired type. This is probably not
2282 exactly how it would happen on the target itself, but it is
2283 the best we can do. */
2284 regcache_raw_read (regcache
, I386_ST0_REGNUM
, buf
);
2285 convert_typed_floating (buf
, i387_ext_type (gdbarch
), valbuf
, type
);
2289 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
2290 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
2292 if (len
<= low_size
)
2294 regcache_raw_read (regcache
, LOW_RETURN_REGNUM
, buf
);
2295 memcpy (valbuf
, buf
, len
);
2297 else if (len
<= (low_size
+ high_size
))
2299 regcache_raw_read (regcache
, LOW_RETURN_REGNUM
, buf
);
2300 memcpy (valbuf
, buf
, low_size
);
2301 regcache_raw_read (regcache
, HIGH_RETURN_REGNUM
, buf
);
2302 memcpy (valbuf
+ low_size
, buf
, len
- low_size
);
2305 internal_error (__FILE__
, __LINE__
,
2306 _("Cannot extract return value of %d bytes long."),
2311 /* Write, for architecture GDBARCH, a function return value of TYPE
2312 from VALBUF into REGCACHE. */
2315 i386_store_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
2316 struct regcache
*regcache
, const gdb_byte
*valbuf
)
2318 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2319 int len
= TYPE_LENGTH (type
);
2321 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2324 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
2326 if (tdep
->st0_regnum
< 0)
2328 warning (_("Cannot set floating-point return value."));
2332 /* Returning floating-point values is a bit tricky. Apart from
2333 storing the return value in %st(0), we have to simulate the
2334 state of the FPU at function return point. */
2336 /* Convert the value found in VALBUF to the extended
2337 floating-point format used by the FPU. This is probably
2338 not exactly how it would happen on the target itself, but
2339 it is the best we can do. */
2340 convert_typed_floating (valbuf
, type
, buf
, i387_ext_type (gdbarch
));
2341 regcache_raw_write (regcache
, I386_ST0_REGNUM
, buf
);
2343 /* Set the top of the floating-point register stack to 7. The
2344 actual value doesn't really matter, but 7 is what a normal
2345 function return would end up with if the program started out
2346 with a freshly initialized FPU. */
2347 regcache_raw_read_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), &fstat
);
2349 regcache_raw_write_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), fstat
);
2351 /* Mark %st(1) through %st(7) as empty. Since we set the top of
2352 the floating-point register stack to 7, the appropriate value
2353 for the tag word is 0x3fff. */
2354 regcache_raw_write_unsigned (regcache
, I387_FTAG_REGNUM (tdep
), 0x3fff);
2358 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
2359 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
2361 if (len
<= low_size
)
2362 regcache_raw_write_part (regcache
, LOW_RETURN_REGNUM
, 0, len
, valbuf
);
2363 else if (len
<= (low_size
+ high_size
))
2365 regcache_raw_write (regcache
, LOW_RETURN_REGNUM
, valbuf
);
2366 regcache_raw_write_part (regcache
, HIGH_RETURN_REGNUM
, 0,
2367 len
- low_size
, valbuf
+ low_size
);
2370 internal_error (__FILE__
, __LINE__
,
2371 _("Cannot store return value of %d bytes long."), len
);
2376 /* This is the variable that is set with "set struct-convention", and
2377 its legitimate values. */
2378 static const char default_struct_convention
[] = "default";
2379 static const char pcc_struct_convention
[] = "pcc";
2380 static const char reg_struct_convention
[] = "reg";
2381 static const char *valid_conventions
[] =
2383 default_struct_convention
,
2384 pcc_struct_convention
,
2385 reg_struct_convention
,
2388 static const char *struct_convention
= default_struct_convention
;
2390 /* Return non-zero if TYPE, which is assumed to be a structure,
2391 a union type, or an array type, should be returned in registers
2392 for architecture GDBARCH. */
2395 i386_reg_struct_return_p (struct gdbarch
*gdbarch
, struct type
*type
)
2397 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2398 enum type_code code
= TYPE_CODE (type
);
2399 int len
= TYPE_LENGTH (type
);
2401 gdb_assert (code
== TYPE_CODE_STRUCT
2402 || code
== TYPE_CODE_UNION
2403 || code
== TYPE_CODE_ARRAY
);
2405 if (struct_convention
== pcc_struct_convention
2406 || (struct_convention
== default_struct_convention
2407 && tdep
->struct_return
== pcc_struct_return
))
2410 /* Structures consisting of a single `float', `double' or 'long
2411 double' member are returned in %st(0). */
2412 if (code
== TYPE_CODE_STRUCT
&& TYPE_NFIELDS (type
) == 1)
2414 type
= check_typedef (TYPE_FIELD_TYPE (type
, 0));
2415 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2416 return (len
== 4 || len
== 8 || len
== 12);
2419 return (len
== 1 || len
== 2 || len
== 4 || len
== 8);
2422 /* Determine, for architecture GDBARCH, how a return value of TYPE
2423 should be returned. If it is supposed to be returned in registers,
2424 and READBUF is non-zero, read the appropriate value from REGCACHE,
2425 and copy it into READBUF. If WRITEBUF is non-zero, write the value
2426 from WRITEBUF into REGCACHE. */
2428 static enum return_value_convention
2429 i386_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
2430 struct type
*type
, struct regcache
*regcache
,
2431 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2433 enum type_code code
= TYPE_CODE (type
);
2435 if (((code
== TYPE_CODE_STRUCT
2436 || code
== TYPE_CODE_UNION
2437 || code
== TYPE_CODE_ARRAY
)
2438 && !i386_reg_struct_return_p (gdbarch
, type
))
2439 /* 128-bit decimal float uses the struct return convention. */
2440 || (code
== TYPE_CODE_DECFLOAT
&& TYPE_LENGTH (type
) == 16))
2442 /* The System V ABI says that:
2444 "A function that returns a structure or union also sets %eax
2445 to the value of the original address of the caller's area
2446 before it returns. Thus when the caller receives control
2447 again, the address of the returned object resides in register
2448 %eax and can be used to access the object."
2450 So the ABI guarantees that we can always find the return
2451 value just after the function has returned. */
2453 /* Note that the ABI doesn't mention functions returning arrays,
2454 which is something possible in certain languages such as Ada.
2455 In this case, the value is returned as if it was wrapped in
2456 a record, so the convention applied to records also applies
2463 regcache_raw_read_unsigned (regcache
, I386_EAX_REGNUM
, &addr
);
2464 read_memory (addr
, readbuf
, TYPE_LENGTH (type
));
2467 return RETURN_VALUE_ABI_RETURNS_ADDRESS
;
2470 /* This special case is for structures consisting of a single
2471 `float', `double' or 'long double' member. These structures are
2472 returned in %st(0). For these structures, we call ourselves
2473 recursively, changing TYPE into the type of the first member of
2474 the structure. Since that should work for all structures that
2475 have only one member, we don't bother to check the member's type
2477 if (code
== TYPE_CODE_STRUCT
&& TYPE_NFIELDS (type
) == 1)
2479 type
= check_typedef (TYPE_FIELD_TYPE (type
, 0));
2480 return i386_return_value (gdbarch
, func_type
, type
, regcache
,
2485 i386_extract_return_value (gdbarch
, type
, regcache
, readbuf
);
2487 i386_store_return_value (gdbarch
, type
, regcache
, writebuf
);
2489 return RETURN_VALUE_REGISTER_CONVENTION
;
2494 i387_ext_type (struct gdbarch
*gdbarch
)
2496 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2498 if (!tdep
->i387_ext_type
)
2500 tdep
->i387_ext_type
= tdesc_find_type (gdbarch
, "i387_ext");
2501 gdb_assert (tdep
->i387_ext_type
!= NULL
);
2504 return tdep
->i387_ext_type
;
2507 /* Construct vector type for pseudo YMM registers. We can't use
2508 tdesc_find_type since YMM isn't described in target description. */
2510 static struct type
*
2511 i386_ymm_type (struct gdbarch
*gdbarch
)
2513 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2515 if (!tdep
->i386_ymm_type
)
2517 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2519 /* The type we're building is this: */
2521 union __gdb_builtin_type_vec256i
2523 int128_t uint128
[2];
2524 int64_t v2_int64
[4];
2525 int32_t v4_int32
[8];
2526 int16_t v8_int16
[16];
2527 int8_t v16_int8
[32];
2528 double v2_double
[4];
2535 t
= arch_composite_type (gdbarch
,
2536 "__gdb_builtin_type_vec256i", TYPE_CODE_UNION
);
2537 append_composite_type_field (t
, "v8_float",
2538 init_vector_type (bt
->builtin_float
, 8));
2539 append_composite_type_field (t
, "v4_double",
2540 init_vector_type (bt
->builtin_double
, 4));
2541 append_composite_type_field (t
, "v32_int8",
2542 init_vector_type (bt
->builtin_int8
, 32));
2543 append_composite_type_field (t
, "v16_int16",
2544 init_vector_type (bt
->builtin_int16
, 16));
2545 append_composite_type_field (t
, "v8_int32",
2546 init_vector_type (bt
->builtin_int32
, 8));
2547 append_composite_type_field (t
, "v4_int64",
2548 init_vector_type (bt
->builtin_int64
, 4));
2549 append_composite_type_field (t
, "v2_int128",
2550 init_vector_type (bt
->builtin_int128
, 2));
2552 TYPE_VECTOR (t
) = 1;
2553 TYPE_NAME (t
) = "builtin_type_vec256i";
2554 tdep
->i386_ymm_type
= t
;
2557 return tdep
->i386_ymm_type
;
2560 /* Construct vector type for MMX registers. */
2561 static struct type
*
2562 i386_mmx_type (struct gdbarch
*gdbarch
)
2564 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2566 if (!tdep
->i386_mmx_type
)
2568 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2570 /* The type we're building is this: */
2572 union __gdb_builtin_type_vec64i
2575 int32_t v2_int32
[2];
2576 int16_t v4_int16
[4];
2583 t
= arch_composite_type (gdbarch
,
2584 "__gdb_builtin_type_vec64i", TYPE_CODE_UNION
);
2586 append_composite_type_field (t
, "uint64", bt
->builtin_int64
);
2587 append_composite_type_field (t
, "v2_int32",
2588 init_vector_type (bt
->builtin_int32
, 2));
2589 append_composite_type_field (t
, "v4_int16",
2590 init_vector_type (bt
->builtin_int16
, 4));
2591 append_composite_type_field (t
, "v8_int8",
2592 init_vector_type (bt
->builtin_int8
, 8));
2594 TYPE_VECTOR (t
) = 1;
2595 TYPE_NAME (t
) = "builtin_type_vec64i";
2596 tdep
->i386_mmx_type
= t
;
2599 return tdep
->i386_mmx_type
;
2602 /* Return the GDB type object for the "standard" data type of data in
2605 static struct type
*
2606 i386_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
2608 if (i386_mmx_regnum_p (gdbarch
, regnum
))
2609 return i386_mmx_type (gdbarch
);
2610 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
2611 return i386_ymm_type (gdbarch
);
2614 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2615 if (i386_byte_regnum_p (gdbarch
, regnum
))
2616 return bt
->builtin_int8
;
2617 else if (i386_word_regnum_p (gdbarch
, regnum
))
2618 return bt
->builtin_int16
;
2619 else if (i386_dword_regnum_p (gdbarch
, regnum
))
2620 return bt
->builtin_int32
;
2623 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
2626 /* Map a cooked register onto a raw register or memory. For the i386,
2627 the MMX registers need to be mapped onto floating point registers. */
2630 i386_mmx_regnum_to_fp_regnum (struct regcache
*regcache
, int regnum
)
2632 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_regcache_arch (regcache
));
2637 mmxreg
= regnum
- tdep
->mm0_regnum
;
2638 regcache_raw_read_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), &fstat
);
2639 tos
= (fstat
>> 11) & 0x7;
2640 fpreg
= (mmxreg
+ tos
) % 8;
2642 return (I387_ST0_REGNUM (tdep
) + fpreg
);
2645 enum register_status
2646 i386_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2647 int regnum
, gdb_byte
*buf
)
2649 gdb_byte raw_buf
[MAX_REGISTER_SIZE
];
2650 enum register_status status
;
2652 if (i386_mmx_regnum_p (gdbarch
, regnum
))
2654 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
2656 /* Extract (always little endian). */
2657 status
= regcache_raw_read (regcache
, fpnum
, raw_buf
);
2658 if (status
!= REG_VALID
)
2660 memcpy (buf
, raw_buf
, register_size (gdbarch
, regnum
));
2664 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2666 if (i386_ymm_regnum_p (gdbarch
, regnum
))
2668 regnum
-= tdep
->ymm0_regnum
;
2670 /* Extract (always little endian). Read lower 128bits. */
2671 status
= regcache_raw_read (regcache
,
2672 I387_XMM0_REGNUM (tdep
) + regnum
,
2674 if (status
!= REG_VALID
)
2676 memcpy (buf
, raw_buf
, 16);
2677 /* Read upper 128bits. */
2678 status
= regcache_raw_read (regcache
,
2679 tdep
->ymm0h_regnum
+ regnum
,
2681 if (status
!= REG_VALID
)
2683 memcpy (buf
+ 16, raw_buf
, 16);
2685 else if (i386_word_regnum_p (gdbarch
, regnum
))
2687 int gpnum
= regnum
- tdep
->ax_regnum
;
2689 /* Extract (always little endian). */
2690 status
= regcache_raw_read (regcache
, gpnum
, raw_buf
);
2691 if (status
!= REG_VALID
)
2693 memcpy (buf
, raw_buf
, 2);
2695 else if (i386_byte_regnum_p (gdbarch
, regnum
))
2697 /* Check byte pseudo registers last since this function will
2698 be called from amd64_pseudo_register_read, which handles
2699 byte pseudo registers differently. */
2700 int gpnum
= regnum
- tdep
->al_regnum
;
2702 /* Extract (always little endian). We read both lower and
2704 status
= regcache_raw_read (regcache
, gpnum
% 4, raw_buf
);
2705 if (status
!= REG_VALID
)
2708 memcpy (buf
, raw_buf
+ 1, 1);
2710 memcpy (buf
, raw_buf
, 1);
2713 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
2720 i386_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2721 int regnum
, const gdb_byte
*buf
)
2723 gdb_byte raw_buf
[MAX_REGISTER_SIZE
];
2725 if (i386_mmx_regnum_p (gdbarch
, regnum
))
2727 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
2730 regcache_raw_read (regcache
, fpnum
, raw_buf
);
2731 /* ... Modify ... (always little endian). */
2732 memcpy (raw_buf
, buf
, register_size (gdbarch
, regnum
));
2734 regcache_raw_write (regcache
, fpnum
, raw_buf
);
2738 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2740 if (i386_ymm_regnum_p (gdbarch
, regnum
))
2742 regnum
-= tdep
->ymm0_regnum
;
2744 /* ... Write lower 128bits. */
2745 regcache_raw_write (regcache
,
2746 I387_XMM0_REGNUM (tdep
) + regnum
,
2748 /* ... Write upper 128bits. */
2749 regcache_raw_write (regcache
,
2750 tdep
->ymm0h_regnum
+ regnum
,
2753 else if (i386_word_regnum_p (gdbarch
, regnum
))
2755 int gpnum
= regnum
- tdep
->ax_regnum
;
2758 regcache_raw_read (regcache
, gpnum
, raw_buf
);
2759 /* ... Modify ... (always little endian). */
2760 memcpy (raw_buf
, buf
, 2);
2762 regcache_raw_write (regcache
, gpnum
, raw_buf
);
2764 else if (i386_byte_regnum_p (gdbarch
, regnum
))
2766 /* Check byte pseudo registers last since this function will
2767 be called from amd64_pseudo_register_read, which handles
2768 byte pseudo registers differently. */
2769 int gpnum
= regnum
- tdep
->al_regnum
;
2771 /* Read ... We read both lower and upper registers. */
2772 regcache_raw_read (regcache
, gpnum
% 4, raw_buf
);
2773 /* ... Modify ... (always little endian). */
2775 memcpy (raw_buf
+ 1, buf
, 1);
2777 memcpy (raw_buf
, buf
, 1);
2779 regcache_raw_write (regcache
, gpnum
% 4, raw_buf
);
2782 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
2787 /* Return the register number of the register allocated by GCC after
2788 REGNUM, or -1 if there is no such register. */
2791 i386_next_regnum (int regnum
)
2793 /* GCC allocates the registers in the order:
2795 %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ...
2797 Since storing a variable in %esp doesn't make any sense we return
2798 -1 for %ebp and for %esp itself. */
2799 static int next_regnum
[] =
2801 I386_EDX_REGNUM
, /* Slot for %eax. */
2802 I386_EBX_REGNUM
, /* Slot for %ecx. */
2803 I386_ECX_REGNUM
, /* Slot for %edx. */
2804 I386_ESI_REGNUM
, /* Slot for %ebx. */
2805 -1, -1, /* Slots for %esp and %ebp. */
2806 I386_EDI_REGNUM
, /* Slot for %esi. */
2807 I386_EBP_REGNUM
/* Slot for %edi. */
2810 if (regnum
>= 0 && regnum
< sizeof (next_regnum
) / sizeof (next_regnum
[0]))
2811 return next_regnum
[regnum
];
2816 /* Return nonzero if a value of type TYPE stored in register REGNUM
2817 needs any special handling. */
2820 i386_convert_register_p (struct gdbarch
*gdbarch
,
2821 int regnum
, struct type
*type
)
2823 int len
= TYPE_LENGTH (type
);
2825 /* Values may be spread across multiple registers. Most debugging
2826 formats aren't expressive enough to specify the locations, so
2827 some heuristics is involved. Right now we only handle types that
2828 have a length that is a multiple of the word size, since GCC
2829 doesn't seem to put any other types into registers. */
2830 if (len
> 4 && len
% 4 == 0)
2832 int last_regnum
= regnum
;
2836 last_regnum
= i386_next_regnum (last_regnum
);
2840 if (last_regnum
!= -1)
2844 return i387_convert_register_p (gdbarch
, regnum
, type
);
2847 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
2848 return its contents in TO. */
2851 i386_register_to_value (struct frame_info
*frame
, int regnum
,
2852 struct type
*type
, gdb_byte
*to
,
2853 int *optimizedp
, int *unavailablep
)
2855 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2856 int len
= TYPE_LENGTH (type
);
2858 if (i386_fp_regnum_p (gdbarch
, regnum
))
2859 return i387_register_to_value (frame
, regnum
, type
, to
,
2860 optimizedp
, unavailablep
);
2862 /* Read a value spread across multiple registers. */
2864 gdb_assert (len
> 4 && len
% 4 == 0);
2868 gdb_assert (regnum
!= -1);
2869 gdb_assert (register_size (gdbarch
, regnum
) == 4);
2871 if (!get_frame_register_bytes (frame
, regnum
, 0,
2872 register_size (gdbarch
, regnum
),
2873 to
, optimizedp
, unavailablep
))
2876 regnum
= i386_next_regnum (regnum
);
2881 *optimizedp
= *unavailablep
= 0;
2885 /* Write the contents FROM of a value of type TYPE into register
2886 REGNUM in frame FRAME. */
2889 i386_value_to_register (struct frame_info
*frame
, int regnum
,
2890 struct type
*type
, const gdb_byte
*from
)
2892 int len
= TYPE_LENGTH (type
);
2894 if (i386_fp_regnum_p (get_frame_arch (frame
), regnum
))
2896 i387_value_to_register (frame
, regnum
, type
, from
);
2900 /* Write a value spread across multiple registers. */
2902 gdb_assert (len
> 4 && len
% 4 == 0);
2906 gdb_assert (regnum
!= -1);
2907 gdb_assert (register_size (get_frame_arch (frame
), regnum
) == 4);
2909 put_frame_register (frame
, regnum
, from
);
2910 regnum
= i386_next_regnum (regnum
);
2916 /* Supply register REGNUM from the buffer specified by GREGS and LEN
2917 in the general-purpose register set REGSET to register cache
2918 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
2921 i386_supply_gregset (const struct regset
*regset
, struct regcache
*regcache
,
2922 int regnum
, const void *gregs
, size_t len
)
2924 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
2925 const gdb_byte
*regs
= gregs
;
2928 gdb_assert (len
== tdep
->sizeof_gregset
);
2930 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
2932 if ((regnum
== i
|| regnum
== -1)
2933 && tdep
->gregset_reg_offset
[i
] != -1)
2934 regcache_raw_supply (regcache
, i
, regs
+ tdep
->gregset_reg_offset
[i
]);
2938 /* Collect register REGNUM from the register cache REGCACHE and store
2939 it in the buffer specified by GREGS and LEN as described by the
2940 general-purpose register set REGSET. If REGNUM is -1, do this for
2941 all registers in REGSET. */
2944 i386_collect_gregset (const struct regset
*regset
,
2945 const struct regcache
*regcache
,
2946 int regnum
, void *gregs
, size_t len
)
2948 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
2949 gdb_byte
*regs
= gregs
;
2952 gdb_assert (len
== tdep
->sizeof_gregset
);
2954 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
2956 if ((regnum
== i
|| regnum
== -1)
2957 && tdep
->gregset_reg_offset
[i
] != -1)
2958 regcache_raw_collect (regcache
, i
, regs
+ tdep
->gregset_reg_offset
[i
]);
2962 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
2963 in the floating-point register set REGSET to register cache
2964 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
2967 i386_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
2968 int regnum
, const void *fpregs
, size_t len
)
2970 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
2972 if (len
== I387_SIZEOF_FXSAVE
)
2974 i387_supply_fxsave (regcache
, regnum
, fpregs
);
2978 gdb_assert (len
== tdep
->sizeof_fpregset
);
2979 i387_supply_fsave (regcache
, regnum
, fpregs
);
2982 /* Collect register REGNUM from the register cache REGCACHE and store
2983 it in the buffer specified by FPREGS and LEN as described by the
2984 floating-point register set REGSET. If REGNUM is -1, do this for
2985 all registers in REGSET. */
2988 i386_collect_fpregset (const struct regset
*regset
,
2989 const struct regcache
*regcache
,
2990 int regnum
, void *fpregs
, size_t len
)
2992 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
2994 if (len
== I387_SIZEOF_FXSAVE
)
2996 i387_collect_fxsave (regcache
, regnum
, fpregs
);
3000 gdb_assert (len
== tdep
->sizeof_fpregset
);
3001 i387_collect_fsave (regcache
, regnum
, fpregs
);
3004 /* Similar to i386_supply_fpregset, but use XSAVE extended state. */
3007 i386_supply_xstateregset (const struct regset
*regset
,
3008 struct regcache
*regcache
, int regnum
,
3009 const void *xstateregs
, size_t len
)
3011 i387_supply_xsave (regcache
, regnum
, xstateregs
);
3014 /* Similar to i386_collect_fpregset , but use XSAVE extended state. */
3017 i386_collect_xstateregset (const struct regset
*regset
,
3018 const struct regcache
*regcache
,
3019 int regnum
, void *xstateregs
, size_t len
)
3021 i387_collect_xsave (regcache
, regnum
, xstateregs
, 1);
3024 /* Return the appropriate register set for the core section identified
3025 by SECT_NAME and SECT_SIZE. */
3027 const struct regset
*
3028 i386_regset_from_core_section (struct gdbarch
*gdbarch
,
3029 const char *sect_name
, size_t sect_size
)
3031 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3033 if (strcmp (sect_name
, ".reg") == 0 && sect_size
== tdep
->sizeof_gregset
)
3035 if (tdep
->gregset
== NULL
)
3036 tdep
->gregset
= regset_alloc (gdbarch
, i386_supply_gregset
,
3037 i386_collect_gregset
);
3038 return tdep
->gregset
;
3041 if ((strcmp (sect_name
, ".reg2") == 0 && sect_size
== tdep
->sizeof_fpregset
)
3042 || (strcmp (sect_name
, ".reg-xfp") == 0
3043 && sect_size
== I387_SIZEOF_FXSAVE
))
3045 if (tdep
->fpregset
== NULL
)
3046 tdep
->fpregset
= regset_alloc (gdbarch
, i386_supply_fpregset
,
3047 i386_collect_fpregset
);
3048 return tdep
->fpregset
;
3051 if (strcmp (sect_name
, ".reg-xstate") == 0)
3053 if (tdep
->xstateregset
== NULL
)
3054 tdep
->xstateregset
= regset_alloc (gdbarch
,
3055 i386_supply_xstateregset
,
3056 i386_collect_xstateregset
);
3058 return tdep
->xstateregset
;
3065 /* Stuff for WIN32 PE style DLL's but is pretty generic really. */
3068 i386_pe_skip_trampoline_code (struct frame_info
*frame
,
3069 CORE_ADDR pc
, char *name
)
3071 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3072 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3075 if (pc
&& read_memory_unsigned_integer (pc
, 2, byte_order
) == 0x25ff)
3077 unsigned long indirect
=
3078 read_memory_unsigned_integer (pc
+ 2, 4, byte_order
);
3079 struct minimal_symbol
*indsym
=
3080 indirect
? lookup_minimal_symbol_by_pc (indirect
) : 0;
3081 char *symname
= indsym
? SYMBOL_LINKAGE_NAME (indsym
) : 0;
3085 if (strncmp (symname
, "__imp_", 6) == 0
3086 || strncmp (symname
, "_imp_", 5) == 0)
3088 read_memory_unsigned_integer (indirect
, 4, byte_order
);
3091 return 0; /* Not a trampoline. */
3095 /* Return whether the THIS_FRAME corresponds to a sigtramp
3099 i386_sigtramp_p (struct frame_info
*this_frame
)
3101 CORE_ADDR pc
= get_frame_pc (this_frame
);
3104 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
3105 return (name
&& strcmp ("_sigtramp", name
) == 0);
3109 /* We have two flavours of disassembly. The machinery on this page
3110 deals with switching between those. */
3113 i386_print_insn (bfd_vma pc
, struct disassemble_info
*info
)
3115 gdb_assert (disassembly_flavor
== att_flavor
3116 || disassembly_flavor
== intel_flavor
);
3118 /* FIXME: kettenis/20020915: Until disassembler_options is properly
3119 constified, cast to prevent a compiler warning. */
3120 info
->disassembler_options
= (char *) disassembly_flavor
;
3122 return print_insn_i386 (pc
, info
);
3126 /* There are a few i386 architecture variants that differ only
3127 slightly from the generic i386 target. For now, we don't give them
3128 their own source file, but include them here. As a consequence,
3129 they'll always be included. */
3131 /* System V Release 4 (SVR4). */
3133 /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp
3137 i386_svr4_sigtramp_p (struct frame_info
*this_frame
)
3139 CORE_ADDR pc
= get_frame_pc (this_frame
);
3142 /* UnixWare uses _sigacthandler. The origin of the other symbols is
3143 currently unknown. */
3144 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
3145 return (name
&& (strcmp ("_sigreturn", name
) == 0
3146 || strcmp ("_sigacthandler", name
) == 0
3147 || strcmp ("sigvechandler", name
) == 0));
3150 /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the
3151 address of the associated sigcontext (ucontext) structure. */
3154 i386_svr4_sigcontext_addr (struct frame_info
*this_frame
)
3156 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3157 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3161 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
3162 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
3164 return read_memory_unsigned_integer (sp
+ 8, 4, byte_order
);
3171 i386_elf_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
3173 /* We typically use stabs-in-ELF with the SVR4 register numbering. */
3174 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
3177 /* System V Release 4 (SVR4). */
3180 i386_svr4_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
3182 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3184 /* System V Release 4 uses ELF. */
3185 i386_elf_init_abi (info
, gdbarch
);
3187 /* System V Release 4 has shared libraries. */
3188 set_gdbarch_skip_trampoline_code (gdbarch
, find_solib_trampoline_target
);
3190 tdep
->sigtramp_p
= i386_svr4_sigtramp_p
;
3191 tdep
->sigcontext_addr
= i386_svr4_sigcontext_addr
;
3192 tdep
->sc_pc_offset
= 36 + 14 * 4;
3193 tdep
->sc_sp_offset
= 36 + 17 * 4;
3195 tdep
->jb_pc_offset
= 20;
3201 i386_go32_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
3203 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3205 /* DJGPP doesn't have any special frames for signal handlers. */
3206 tdep
->sigtramp_p
= NULL
;
3208 tdep
->jb_pc_offset
= 36;
3210 /* DJGPP does not support the SSE registers. */
3211 if (! tdesc_has_registers (info
.target_desc
))
3212 tdep
->tdesc
= tdesc_i386_mmx
;
3214 /* Native compiler is GCC, which uses the SVR4 register numbering
3215 even in COFF and STABS. See the comment in i386_gdbarch_init,
3216 before the calls to set_gdbarch_stab_reg_to_regnum and
3217 set_gdbarch_sdb_reg_to_regnum. */
3218 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
3219 set_gdbarch_sdb_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
3221 set_gdbarch_has_dos_based_file_system (gdbarch
, 1);
3225 /* i386 register groups. In addition to the normal groups, add "mmx"
3228 static struct reggroup
*i386_sse_reggroup
;
3229 static struct reggroup
*i386_mmx_reggroup
;
3232 i386_init_reggroups (void)
3234 i386_sse_reggroup
= reggroup_new ("sse", USER_REGGROUP
);
3235 i386_mmx_reggroup
= reggroup_new ("mmx", USER_REGGROUP
);
3239 i386_add_reggroups (struct gdbarch
*gdbarch
)
3241 reggroup_add (gdbarch
, i386_sse_reggroup
);
3242 reggroup_add (gdbarch
, i386_mmx_reggroup
);
3243 reggroup_add (gdbarch
, general_reggroup
);
3244 reggroup_add (gdbarch
, float_reggroup
);
3245 reggroup_add (gdbarch
, all_reggroup
);
3246 reggroup_add (gdbarch
, save_reggroup
);
3247 reggroup_add (gdbarch
, restore_reggroup
);
3248 reggroup_add (gdbarch
, vector_reggroup
);
3249 reggroup_add (gdbarch
, system_reggroup
);
3253 i386_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
3254 struct reggroup
*group
)
3256 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3257 int fp_regnum_p
, mmx_regnum_p
, xmm_regnum_p
, mxcsr_regnum_p
,
3258 ymm_regnum_p
, ymmh_regnum_p
;
3260 /* Don't include pseudo registers, except for MMX, in any register
3262 if (i386_byte_regnum_p (gdbarch
, regnum
))
3265 if (i386_word_regnum_p (gdbarch
, regnum
))
3268 if (i386_dword_regnum_p (gdbarch
, regnum
))
3271 mmx_regnum_p
= i386_mmx_regnum_p (gdbarch
, regnum
);
3272 if (group
== i386_mmx_reggroup
)
3273 return mmx_regnum_p
;
3275 xmm_regnum_p
= i386_xmm_regnum_p (gdbarch
, regnum
);
3276 mxcsr_regnum_p
= i386_mxcsr_regnum_p (gdbarch
, regnum
);
3277 if (group
== i386_sse_reggroup
)
3278 return xmm_regnum_p
|| mxcsr_regnum_p
;
3280 ymm_regnum_p
= i386_ymm_regnum_p (gdbarch
, regnum
);
3281 if (group
== vector_reggroup
)
3282 return (mmx_regnum_p
3286 && ((tdep
->xcr0
& I386_XSTATE_AVX_MASK
)
3287 == I386_XSTATE_SSE_MASK
)));
3289 fp_regnum_p
= (i386_fp_regnum_p (gdbarch
, regnum
)
3290 || i386_fpc_regnum_p (gdbarch
, regnum
));
3291 if (group
== float_reggroup
)
3294 /* For "info reg all", don't include upper YMM registers nor XMM
3295 registers when AVX is supported. */
3296 ymmh_regnum_p
= i386_ymmh_regnum_p (gdbarch
, regnum
);
3297 if (group
== all_reggroup
3299 && (tdep
->xcr0
& I386_XSTATE_AVX
))
3303 if (group
== general_reggroup
)
3304 return (!fp_regnum_p
3311 return default_register_reggroup_p (gdbarch
, regnum
, group
);
3315 /* Get the ARGIth function argument for the current function. */
3318 i386_fetch_pointer_argument (struct frame_info
*frame
, int argi
,
3321 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3322 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3323 CORE_ADDR sp
= get_frame_register_unsigned (frame
, I386_ESP_REGNUM
);
3324 return read_memory_unsigned_integer (sp
+ (4 * (argi
+ 1)), 4, byte_order
);
3328 i386_skip_permanent_breakpoint (struct regcache
*regcache
)
3330 CORE_ADDR current_pc
= regcache_read_pc (regcache
);
3332 /* On i386, breakpoint is exactly 1 byte long, so we just
3333 adjust the PC in the regcache. */
3335 regcache_write_pc (regcache
, current_pc
);
3339 #define PREFIX_REPZ 0x01
3340 #define PREFIX_REPNZ 0x02
3341 #define PREFIX_LOCK 0x04
3342 #define PREFIX_DATA 0x08
3343 #define PREFIX_ADDR 0x10
3355 /* i386 arith/logic operations */
3368 struct i386_record_s
3370 struct gdbarch
*gdbarch
;
3371 struct regcache
*regcache
;
3372 CORE_ADDR orig_addr
;
3378 uint8_t mod
, reg
, rm
;
3387 /* Parse "modrm" part in current memory address that irp->addr point to
3388 Return -1 if something wrong. */
3391 i386_record_modrm (struct i386_record_s
*irp
)
3393 struct gdbarch
*gdbarch
= irp
->gdbarch
;
3395 if (target_read_memory (irp
->addr
, &irp
->modrm
, 1))
3398 printf_unfiltered (_("Process record: error reading memory at "
3399 "addr %s len = 1.\n"),
3400 paddress (gdbarch
, irp
->addr
));
3404 irp
->mod
= (irp
->modrm
>> 6) & 3;
3405 irp
->reg
= (irp
->modrm
>> 3) & 7;
3406 irp
->rm
= irp
->modrm
& 7;
3411 /* Get the memory address that current instruction write to and set it to
3412 the argument "addr".
3413 Return -1 if something wrong. */
3416 i386_record_lea_modrm_addr (struct i386_record_s
*irp
, uint64_t *addr
)
3418 struct gdbarch
*gdbarch
= irp
->gdbarch
;
3419 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3431 uint8_t base
= irp
->rm
;
3436 if (target_read_memory (irp
->addr
, &byte
, 1))
3439 printf_unfiltered (_("Process record: error reading memory "
3440 "at addr %s len = 1.\n"),
3441 paddress (gdbarch
, irp
->addr
));
3445 scale
= (byte
>> 6) & 3;
3446 index
= ((byte
>> 3) & 7) | irp
->rex_x
;
3454 if ((base
& 7) == 5)
3457 if (target_read_memory (irp
->addr
, buf
, 4))
3460 printf_unfiltered (_("Process record: error reading "
3461 "memory at addr %s len = 4.\n"),
3462 paddress (gdbarch
, irp
->addr
));
3466 *addr
= extract_signed_integer (buf
, 4, byte_order
);
3467 if (irp
->regmap
[X86_RECORD_R8_REGNUM
] && !havesib
)
3468 *addr
+= irp
->addr
+ irp
->rip_offset
;
3472 if (target_read_memory (irp
->addr
, buf
, 1))
3475 printf_unfiltered (_("Process record: error reading memory "
3476 "at addr %s len = 1.\n"),
3477 paddress (gdbarch
, irp
->addr
));
3481 *addr
= (int8_t) buf
[0];
3484 if (target_read_memory (irp
->addr
, buf
, 4))
3487 printf_unfiltered (_("Process record: error reading memory "
3488 "at addr %s len = 4.\n"),
3489 paddress (gdbarch
, irp
->addr
));
3492 *addr
= extract_signed_integer (buf
, 4, byte_order
);
3500 if (base
== 4 && irp
->popl_esp_hack
)
3501 *addr
+= irp
->popl_esp_hack
;
3502 regcache_raw_read_unsigned (irp
->regcache
, irp
->regmap
[base
],
3505 if (irp
->aflag
== 2)
3510 *addr
= (uint32_t) (offset64
+ *addr
);
3512 if (havesib
&& (index
!= 4 || scale
!= 0))
3514 regcache_raw_read_unsigned (irp
->regcache
, irp
->regmap
[index
],
3516 if (irp
->aflag
== 2)
3517 *addr
+= offset64
<< scale
;
3519 *addr
= (uint32_t) (*addr
+ (offset64
<< scale
));
3530 if (target_read_memory (irp
->addr
, buf
, 2))
3533 printf_unfiltered (_("Process record: error reading "
3534 "memory at addr %s len = 2.\n"),
3535 paddress (gdbarch
, irp
->addr
));
3539 *addr
= extract_signed_integer (buf
, 2, byte_order
);
3545 if (target_read_memory (irp
->addr
, buf
, 1))
3548 printf_unfiltered (_("Process record: error reading memory "
3549 "at addr %s len = 1.\n"),
3550 paddress (gdbarch
, irp
->addr
));
3554 *addr
= (int8_t) buf
[0];
3557 if (target_read_memory (irp
->addr
, buf
, 2))
3560 printf_unfiltered (_("Process record: error reading memory "
3561 "at addr %s len = 2.\n"),
3562 paddress (gdbarch
, irp
->addr
));
3566 *addr
= extract_signed_integer (buf
, 2, byte_order
);
3573 regcache_raw_read_unsigned (irp
->regcache
,
3574 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
3576 *addr
= (uint32_t) (*addr
+ offset64
);
3577 regcache_raw_read_unsigned (irp
->regcache
,
3578 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
3580 *addr
= (uint32_t) (*addr
+ offset64
);
3583 regcache_raw_read_unsigned (irp
->regcache
,
3584 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
3586 *addr
= (uint32_t) (*addr
+ offset64
);
3587 regcache_raw_read_unsigned (irp
->regcache
,
3588 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
3590 *addr
= (uint32_t) (*addr
+ offset64
);
3593 regcache_raw_read_unsigned (irp
->regcache
,
3594 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
3596 *addr
= (uint32_t) (*addr
+ offset64
);
3597 regcache_raw_read_unsigned (irp
->regcache
,
3598 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
3600 *addr
= (uint32_t) (*addr
+ offset64
);
3603 regcache_raw_read_unsigned (irp
->regcache
,
3604 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
3606 *addr
= (uint32_t) (*addr
+ offset64
);
3607 regcache_raw_read_unsigned (irp
->regcache
,
3608 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
3610 *addr
= (uint32_t) (*addr
+ offset64
);
3613 regcache_raw_read_unsigned (irp
->regcache
,
3614 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
3616 *addr
= (uint32_t) (*addr
+ offset64
);
3619 regcache_raw_read_unsigned (irp
->regcache
,
3620 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
3622 *addr
= (uint32_t) (*addr
+ offset64
);
3625 regcache_raw_read_unsigned (irp
->regcache
,
3626 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
3628 *addr
= (uint32_t) (*addr
+ offset64
);
3631 regcache_raw_read_unsigned (irp
->regcache
,
3632 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
3634 *addr
= (uint32_t) (*addr
+ offset64
);
3644 /* Record the value of the memory that willbe changed in current instruction
3645 to "record_arch_list".
3646 Return -1 if something wrong. */
3649 i386_record_lea_modrm (struct i386_record_s
*irp
)
3651 struct gdbarch
*gdbarch
= irp
->gdbarch
;
3654 if (irp
->override
>= 0)
3656 if (record_memory_query
)
3660 target_terminal_ours ();
3662 Process record ignores the memory change of instruction at address %s\n\
3663 because it can't get the value of the segment register.\n\
3664 Do you want to stop the program?"),
3665 paddress (gdbarch
, irp
->orig_addr
));
3666 target_terminal_inferior ();
3674 if (i386_record_lea_modrm_addr (irp
, &addr
))
3677 if (record_arch_list_add_mem (addr
, 1 << irp
->ot
))
3683 /* Record the push operation to "record_arch_list".
3684 Return -1 if something wrong. */
3687 i386_record_push (struct i386_record_s
*irp
, int size
)
3691 if (record_arch_list_add_reg (irp
->regcache
,
3692 irp
->regmap
[X86_RECORD_RESP_REGNUM
]))
3694 regcache_raw_read_unsigned (irp
->regcache
,
3695 irp
->regmap
[X86_RECORD_RESP_REGNUM
],
3697 if (record_arch_list_add_mem ((CORE_ADDR
) addr
- size
, size
))
3704 /* Defines contents to record. */
3705 #define I386_SAVE_FPU_REGS 0xfffd
3706 #define I386_SAVE_FPU_ENV 0xfffe
3707 #define I386_SAVE_FPU_ENV_REG_STACK 0xffff
3709 /* Record the value of floating point registers which will be changed
3710 by the current instruction to "record_arch_list". Return -1 if
3711 something is wrong. */
3713 static int i386_record_floats (struct gdbarch
*gdbarch
,
3714 struct i386_record_s
*ir
,
3717 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3720 /* Oza: Because of floating point insn push/pop of fpu stack is going to
3721 happen. Currently we store st0-st7 registers, but we need not store all
3722 registers all the time, in future we use ftag register and record only
3723 those who are not marked as an empty. */
3725 if (I386_SAVE_FPU_REGS
== iregnum
)
3727 for (i
= I387_ST0_REGNUM (tdep
); i
<= I387_ST0_REGNUM (tdep
) + 7; i
++)
3729 if (record_arch_list_add_reg (ir
->regcache
, i
))
3733 else if (I386_SAVE_FPU_ENV
== iregnum
)
3735 for (i
= I387_FCTRL_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
3737 if (record_arch_list_add_reg (ir
->regcache
, i
))
3741 else if (I386_SAVE_FPU_ENV_REG_STACK
== iregnum
)
3743 for (i
= I387_ST0_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
3745 if (record_arch_list_add_reg (ir
->regcache
, i
))
3749 else if ((iregnum
>= I387_ST0_REGNUM (tdep
)) &&
3750 (iregnum
<= I387_FOP_REGNUM (tdep
)))
3752 if (record_arch_list_add_reg (ir
->regcache
,iregnum
))
3757 /* Parameter error. */
3760 if(I386_SAVE_FPU_ENV
!= iregnum
)
3762 for (i
= I387_FCTRL_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
3764 if (record_arch_list_add_reg (ir
->regcache
, i
))
3771 /* Parse the current instruction and record the values of the registers and
3772 memory that will be changed in current instruction to "record_arch_list".
3773 Return -1 if something wrong. */
3775 #define I386_RECORD_ARCH_LIST_ADD_REG(regnum) \
3776 record_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)])
3779 i386_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
3780 CORE_ADDR input_addr
)
3782 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3788 gdb_byte buf
[MAX_REGISTER_SIZE
];
3789 struct i386_record_s ir
;
3790 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3795 memset (&ir
, 0, sizeof (struct i386_record_s
));
3796 ir
.regcache
= regcache
;
3797 ir
.addr
= input_addr
;
3798 ir
.orig_addr
= input_addr
;
3802 ir
.popl_esp_hack
= 0;
3803 ir
.regmap
= tdep
->record_regmap
;
3804 ir
.gdbarch
= gdbarch
;
3806 if (record_debug
> 1)
3807 fprintf_unfiltered (gdb_stdlog
, "Process record: i386_process_record "
3809 paddress (gdbarch
, ir
.addr
));
3814 if (target_read_memory (ir
.addr
, &opcode8
, 1))
3817 printf_unfiltered (_("Process record: error reading memory at "
3818 "addr %s len = 1.\n"),
3819 paddress (gdbarch
, ir
.addr
));
3823 switch (opcode8
) /* Instruction prefixes */
3825 case REPE_PREFIX_OPCODE
:
3826 prefixes
|= PREFIX_REPZ
;
3828 case REPNE_PREFIX_OPCODE
:
3829 prefixes
|= PREFIX_REPNZ
;
3831 case LOCK_PREFIX_OPCODE
:
3832 prefixes
|= PREFIX_LOCK
;
3834 case CS_PREFIX_OPCODE
:
3835 ir
.override
= X86_RECORD_CS_REGNUM
;
3837 case SS_PREFIX_OPCODE
:
3838 ir
.override
= X86_RECORD_SS_REGNUM
;
3840 case DS_PREFIX_OPCODE
:
3841 ir
.override
= X86_RECORD_DS_REGNUM
;
3843 case ES_PREFIX_OPCODE
:
3844 ir
.override
= X86_RECORD_ES_REGNUM
;
3846 case FS_PREFIX_OPCODE
:
3847 ir
.override
= X86_RECORD_FS_REGNUM
;
3849 case GS_PREFIX_OPCODE
:
3850 ir
.override
= X86_RECORD_GS_REGNUM
;
3852 case DATA_PREFIX_OPCODE
:
3853 prefixes
|= PREFIX_DATA
;
3855 case ADDR_PREFIX_OPCODE
:
3856 prefixes
|= PREFIX_ADDR
;
3858 case 0x40: /* i386 inc %eax */
3859 case 0x41: /* i386 inc %ecx */
3860 case 0x42: /* i386 inc %edx */
3861 case 0x43: /* i386 inc %ebx */
3862 case 0x44: /* i386 inc %esp */
3863 case 0x45: /* i386 inc %ebp */
3864 case 0x46: /* i386 inc %esi */
3865 case 0x47: /* i386 inc %edi */
3866 case 0x48: /* i386 dec %eax */
3867 case 0x49: /* i386 dec %ecx */
3868 case 0x4a: /* i386 dec %edx */
3869 case 0x4b: /* i386 dec %ebx */
3870 case 0x4c: /* i386 dec %esp */
3871 case 0x4d: /* i386 dec %ebp */
3872 case 0x4e: /* i386 dec %esi */
3873 case 0x4f: /* i386 dec %edi */
3874 if (ir
.regmap
[X86_RECORD_R8_REGNUM
]) /* 64 bit target */
3878 rex_w
= (opcode8
>> 3) & 1;
3879 rex_r
= (opcode8
& 0x4) << 1;
3880 ir
.rex_x
= (opcode8
& 0x2) << 2;
3881 ir
.rex_b
= (opcode8
& 0x1) << 3;
3883 else /* 32 bit target */
3892 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && rex_w
== 1)
3898 if (prefixes
& PREFIX_DATA
)
3901 if (prefixes
& PREFIX_ADDR
)
3903 else if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
3906 /* Now check op code. */
3907 opcode
= (uint32_t) opcode8
;
3912 if (target_read_memory (ir
.addr
, &opcode8
, 1))
3915 printf_unfiltered (_("Process record: error reading memory at "
3916 "addr %s len = 1.\n"),
3917 paddress (gdbarch
, ir
.addr
));
3921 opcode
= (uint32_t) opcode8
| 0x0f00;
3925 case 0x00: /* arith & logic */
3973 if (((opcode
>> 3) & 7) != OP_CMPL
)
3975 if ((opcode
& 1) == 0)
3978 ir
.ot
= ir
.dflag
+ OT_WORD
;
3980 switch ((opcode
>> 1) & 3)
3982 case 0: /* OP Ev, Gv */
3983 if (i386_record_modrm (&ir
))
3987 if (i386_record_lea_modrm (&ir
))
3993 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3995 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
3998 case 1: /* OP Gv, Ev */
3999 if (i386_record_modrm (&ir
))
4002 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4004 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4006 case 2: /* OP A, Iv */
4007 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4011 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4014 case 0x80: /* GRP1 */
4018 if (i386_record_modrm (&ir
))
4021 if (ir
.reg
!= OP_CMPL
)
4023 if ((opcode
& 1) == 0)
4026 ir
.ot
= ir
.dflag
+ OT_WORD
;
4033 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
4034 if (i386_record_lea_modrm (&ir
))
4038 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
4040 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4043 case 0x40: /* inc */
4052 case 0x48: /* dec */
4061 I386_RECORD_ARCH_LIST_ADD_REG (opcode
& 7);
4062 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4065 case 0xf6: /* GRP3 */
4067 if ((opcode
& 1) == 0)
4070 ir
.ot
= ir
.dflag
+ OT_WORD
;
4071 if (i386_record_modrm (&ir
))
4074 if (ir
.mod
!= 3 && ir
.reg
== 0)
4075 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
4080 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4086 if (i386_record_lea_modrm (&ir
))
4092 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4094 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4096 if (ir
.reg
== 3) /* neg */
4097 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4103 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4104 if (ir
.ot
!= OT_BYTE
)
4105 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
4106 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4110 opcode
= opcode
<< 8 | ir
.modrm
;
4116 case 0xfe: /* GRP4 */
4117 case 0xff: /* GRP5 */
4118 if (i386_record_modrm (&ir
))
4120 if (ir
.reg
>= 2 && opcode
== 0xfe)
4123 opcode
= opcode
<< 8 | ir
.modrm
;
4130 if ((opcode
& 1) == 0)
4133 ir
.ot
= ir
.dflag
+ OT_WORD
;
4136 if (i386_record_lea_modrm (&ir
))
4142 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4144 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4146 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4149 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4151 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4153 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4156 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
4157 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4159 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4163 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4166 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4168 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4173 opcode
= opcode
<< 8 | ir
.modrm
;
4179 case 0x84: /* test */
4183 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4186 case 0x98: /* CWDE/CBW */
4187 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4190 case 0x99: /* CDQ/CWD */
4191 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4192 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
4195 case 0x0faf: /* imul */
4198 ir
.ot
= ir
.dflag
+ OT_WORD
;
4199 if (i386_record_modrm (&ir
))
4202 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
4203 else if (opcode
== 0x6b)
4206 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4208 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4209 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4212 case 0x0fc0: /* xadd */
4214 if ((opcode
& 1) == 0)
4217 ir
.ot
= ir
.dflag
+ OT_WORD
;
4218 if (i386_record_modrm (&ir
))
4223 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4225 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4226 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4228 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4232 if (i386_record_lea_modrm (&ir
))
4234 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4236 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4238 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4241 case 0x0fb0: /* cmpxchg */
4243 if ((opcode
& 1) == 0)
4246 ir
.ot
= ir
.dflag
+ OT_WORD
;
4247 if (i386_record_modrm (&ir
))
4252 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4253 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4255 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4259 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4260 if (i386_record_lea_modrm (&ir
))
4263 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4266 case 0x0fc7: /* cmpxchg8b */
4267 if (i386_record_modrm (&ir
))
4272 opcode
= opcode
<< 8 | ir
.modrm
;
4275 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4276 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
4277 if (i386_record_lea_modrm (&ir
))
4279 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4282 case 0x50: /* push */
4292 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4294 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4298 case 0x06: /* push es */
4299 case 0x0e: /* push cs */
4300 case 0x16: /* push ss */
4301 case 0x1e: /* push ds */
4302 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4307 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4311 case 0x0fa0: /* push fs */
4312 case 0x0fa8: /* push gs */
4313 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4318 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4322 case 0x60: /* pusha */
4323 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4328 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 4)))
4332 case 0x58: /* pop */
4340 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4341 I386_RECORD_ARCH_LIST_ADD_REG ((opcode
& 0x7) | ir
.rex_b
);
4344 case 0x61: /* popa */
4345 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4350 for (regnum
= X86_RECORD_REAX_REGNUM
;
4351 regnum
<= X86_RECORD_REDI_REGNUM
;
4353 I386_RECORD_ARCH_LIST_ADD_REG (regnum
);
4356 case 0x8f: /* pop */
4357 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4358 ir
.ot
= ir
.dflag
? OT_QUAD
: OT_WORD
;
4360 ir
.ot
= ir
.dflag
+ OT_WORD
;
4361 if (i386_record_modrm (&ir
))
4364 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
4367 ir
.popl_esp_hack
= 1 << ir
.ot
;
4368 if (i386_record_lea_modrm (&ir
))
4371 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4374 case 0xc8: /* enter */
4375 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
4376 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4378 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4382 case 0xc9: /* leave */
4383 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4384 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
4387 case 0x07: /* pop es */
4388 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4393 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4394 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM
);
4395 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4398 case 0x17: /* pop ss */
4399 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4404 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4405 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM
);
4406 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4409 case 0x1f: /* pop ds */
4410 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4415 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4416 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM
);
4417 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4420 case 0x0fa1: /* pop fs */
4421 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4422 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM
);
4423 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4426 case 0x0fa9: /* pop gs */
4427 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4428 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM
);
4429 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4432 case 0x88: /* mov */
4436 if ((opcode
& 1) == 0)
4439 ir
.ot
= ir
.dflag
+ OT_WORD
;
4441 if (i386_record_modrm (&ir
))
4446 if (opcode
== 0xc6 || opcode
== 0xc7)
4447 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
4448 if (i386_record_lea_modrm (&ir
))
4453 if (opcode
== 0xc6 || opcode
== 0xc7)
4455 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4457 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4461 case 0x8a: /* mov */
4463 if ((opcode
& 1) == 0)
4466 ir
.ot
= ir
.dflag
+ OT_WORD
;
4467 if (i386_record_modrm (&ir
))
4470 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4472 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4475 case 0x8c: /* mov seg */
4476 if (i386_record_modrm (&ir
))
4481 opcode
= opcode
<< 8 | ir
.modrm
;
4486 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4490 if (i386_record_lea_modrm (&ir
))
4495 case 0x8e: /* mov seg */
4496 if (i386_record_modrm (&ir
))
4501 regnum
= X86_RECORD_ES_REGNUM
;
4504 regnum
= X86_RECORD_SS_REGNUM
;
4507 regnum
= X86_RECORD_DS_REGNUM
;
4510 regnum
= X86_RECORD_FS_REGNUM
;
4513 regnum
= X86_RECORD_GS_REGNUM
;
4517 opcode
= opcode
<< 8 | ir
.modrm
;
4521 I386_RECORD_ARCH_LIST_ADD_REG (regnum
);
4522 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4525 case 0x0fb6: /* movzbS */
4526 case 0x0fb7: /* movzwS */
4527 case 0x0fbe: /* movsbS */
4528 case 0x0fbf: /* movswS */
4529 if (i386_record_modrm (&ir
))
4531 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
4534 case 0x8d: /* lea */
4535 if (i386_record_modrm (&ir
))
4540 opcode
= opcode
<< 8 | ir
.modrm
;
4545 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4547 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4550 case 0xa0: /* mov EAX */
4553 case 0xd7: /* xlat */
4554 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4557 case 0xa2: /* mov EAX */
4559 if (ir
.override
>= 0)
4561 if (record_memory_query
)
4565 target_terminal_ours ();
4567 Process record ignores the memory change of instruction at address %s\n\
4568 because it can't get the value of the segment register.\n\
4569 Do you want to stop the program?"),
4570 paddress (gdbarch
, ir
.orig_addr
));
4571 target_terminal_inferior ();
4578 if ((opcode
& 1) == 0)
4581 ir
.ot
= ir
.dflag
+ OT_WORD
;
4584 if (target_read_memory (ir
.addr
, buf
, 8))
4587 printf_unfiltered (_("Process record: error reading "
4588 "memory at addr 0x%s len = 8.\n"),
4589 paddress (gdbarch
, ir
.addr
));
4593 addr
= extract_unsigned_integer (buf
, 8, byte_order
);
4597 if (target_read_memory (ir
.addr
, buf
, 4))
4600 printf_unfiltered (_("Process record: error reading "
4601 "memory at addr 0x%s len = 4.\n"),
4602 paddress (gdbarch
, ir
.addr
));
4606 addr
= extract_unsigned_integer (buf
, 4, byte_order
);
4610 if (target_read_memory (ir
.addr
, buf
, 2))
4613 printf_unfiltered (_("Process record: error reading "
4614 "memory at addr 0x%s len = 2.\n"),
4615 paddress (gdbarch
, ir
.addr
));
4619 addr
= extract_unsigned_integer (buf
, 2, byte_order
);
4621 if (record_arch_list_add_mem (addr
, 1 << ir
.ot
))
4626 case 0xb0: /* mov R, Ib */
4634 I386_RECORD_ARCH_LIST_ADD_REG ((ir
.regmap
[X86_RECORD_R8_REGNUM
])
4635 ? ((opcode
& 0x7) | ir
.rex_b
)
4636 : ((opcode
& 0x7) & 0x3));
4639 case 0xb8: /* mov R, Iv */
4647 I386_RECORD_ARCH_LIST_ADD_REG ((opcode
& 0x7) | ir
.rex_b
);
4650 case 0x91: /* xchg R, EAX */
4657 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4658 I386_RECORD_ARCH_LIST_ADD_REG (opcode
& 0x7);
4661 case 0x86: /* xchg Ev, Gv */
4663 if ((opcode
& 1) == 0)
4666 ir
.ot
= ir
.dflag
+ OT_WORD
;
4667 if (i386_record_modrm (&ir
))
4672 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4674 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4678 if (i386_record_lea_modrm (&ir
))
4682 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4684 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4687 case 0xc4: /* les Gv */
4688 case 0xc5: /* lds Gv */
4689 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4695 case 0x0fb2: /* lss Gv */
4696 case 0x0fb4: /* lfs Gv */
4697 case 0x0fb5: /* lgs Gv */
4698 if (i386_record_modrm (&ir
))
4706 opcode
= opcode
<< 8 | ir
.modrm
;
4711 case 0xc4: /* les Gv */
4712 regnum
= X86_RECORD_ES_REGNUM
;
4714 case 0xc5: /* lds Gv */
4715 regnum
= X86_RECORD_DS_REGNUM
;
4717 case 0x0fb2: /* lss Gv */
4718 regnum
= X86_RECORD_SS_REGNUM
;
4720 case 0x0fb4: /* lfs Gv */
4721 regnum
= X86_RECORD_FS_REGNUM
;
4723 case 0x0fb5: /* lgs Gv */
4724 regnum
= X86_RECORD_GS_REGNUM
;
4727 I386_RECORD_ARCH_LIST_ADD_REG (regnum
);
4728 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
4729 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4732 case 0xc0: /* shifts */
4738 if ((opcode
& 1) == 0)
4741 ir
.ot
= ir
.dflag
+ OT_WORD
;
4742 if (i386_record_modrm (&ir
))
4744 if (ir
.mod
!= 3 && (opcode
== 0xd2 || opcode
== 0xd3))
4746 if (i386_record_lea_modrm (&ir
))
4752 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4754 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4756 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4763 if (i386_record_modrm (&ir
))
4767 if (record_arch_list_add_reg (ir
.regcache
, ir
.rm
))
4772 if (i386_record_lea_modrm (&ir
))
4777 case 0xd8: /* Floats. */
4785 if (i386_record_modrm (&ir
))
4787 ir
.reg
|= ((opcode
& 7) << 3);
4793 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
4801 /* For fcom, ficom nothing to do. */
4807 /* For fcomp, ficomp pop FPU stack, store all. */
4808 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
4835 /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul,
4836 fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension
4837 of code, always affects st(0) register. */
4838 if (i386_record_floats (gdbarch
, &ir
, I387_ST0_REGNUM (tdep
)))
4862 /* Handling fld, fild. */
4863 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
4867 switch (ir
.reg
>> 4)
4870 if (record_arch_list_add_mem (addr64
, 4))
4874 if (record_arch_list_add_mem (addr64
, 8))
4880 if (record_arch_list_add_mem (addr64
, 2))
4886 switch (ir
.reg
>> 4)
4889 if (record_arch_list_add_mem (addr64
, 4))
4891 if (3 == (ir
.reg
& 7))
4893 /* For fstp m32fp. */
4894 if (i386_record_floats (gdbarch
, &ir
,
4895 I386_SAVE_FPU_REGS
))
4900 if (record_arch_list_add_mem (addr64
, 4))
4902 if ((3 == (ir
.reg
& 7))
4903 || (5 == (ir
.reg
& 7))
4904 || (7 == (ir
.reg
& 7)))
4906 /* For fstp insn. */
4907 if (i386_record_floats (gdbarch
, &ir
,
4908 I386_SAVE_FPU_REGS
))
4913 if (record_arch_list_add_mem (addr64
, 8))
4915 if (3 == (ir
.reg
& 7))
4917 /* For fstp m64fp. */
4918 if (i386_record_floats (gdbarch
, &ir
,
4919 I386_SAVE_FPU_REGS
))
4924 if ((3 <= (ir
.reg
& 7)) && (6 <= (ir
.reg
& 7)))
4926 /* For fistp, fbld, fild, fbstp. */
4927 if (i386_record_floats (gdbarch
, &ir
,
4928 I386_SAVE_FPU_REGS
))
4933 if (record_arch_list_add_mem (addr64
, 2))
4942 if (i386_record_floats (gdbarch
, &ir
,
4943 I386_SAVE_FPU_ENV_REG_STACK
))
4948 if (i386_record_floats (gdbarch
, &ir
, I387_FCTRL_REGNUM (tdep
)))
4953 if (i386_record_floats (gdbarch
, &ir
,
4954 I386_SAVE_FPU_ENV_REG_STACK
))
4960 if (record_arch_list_add_mem (addr64
, 28))
4965 if (record_arch_list_add_mem (addr64
, 14))
4971 if (record_arch_list_add_mem (addr64
, 2))
4973 /* Insn fstp, fbstp. */
4974 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
4979 if (record_arch_list_add_mem (addr64
, 10))
4985 if (record_arch_list_add_mem (addr64
, 28))
4991 if (record_arch_list_add_mem (addr64
, 14))
4995 if (record_arch_list_add_mem (addr64
, 80))
4998 if (i386_record_floats (gdbarch
, &ir
,
4999 I386_SAVE_FPU_ENV_REG_STACK
))
5003 if (record_arch_list_add_mem (addr64
, 8))
5006 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5011 opcode
= opcode
<< 8 | ir
.modrm
;
5016 /* Opcode is an extension of modR/M byte. */
5022 if (i386_record_floats (gdbarch
, &ir
, I387_ST0_REGNUM (tdep
)))
5026 if (0x0c == (ir
.modrm
>> 4))
5028 if ((ir
.modrm
& 0x0f) <= 7)
5030 if (i386_record_floats (gdbarch
, &ir
,
5031 I386_SAVE_FPU_REGS
))
5036 if (i386_record_floats (gdbarch
, &ir
,
5037 I387_ST0_REGNUM (tdep
)))
5039 /* If only st(0) is changing, then we have already
5041 if ((ir
.modrm
& 0x0f) - 0x08)
5043 if (i386_record_floats (gdbarch
, &ir
,
5044 I387_ST0_REGNUM (tdep
) +
5045 ((ir
.modrm
& 0x0f) - 0x08)))
5063 if (i386_record_floats (gdbarch
, &ir
,
5064 I387_ST0_REGNUM (tdep
)))
5082 if (i386_record_floats (gdbarch
, &ir
,
5083 I386_SAVE_FPU_REGS
))
5087 if (i386_record_floats (gdbarch
, &ir
,
5088 I387_ST0_REGNUM (tdep
)))
5090 if (i386_record_floats (gdbarch
, &ir
,
5091 I387_ST0_REGNUM (tdep
) + 1))
5098 if (0xe9 == ir
.modrm
)
5100 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5103 else if ((0x0c == ir
.modrm
>> 4) || (0x0d == ir
.modrm
>> 4))
5105 if (i386_record_floats (gdbarch
, &ir
,
5106 I387_ST0_REGNUM (tdep
)))
5108 if (((ir
.modrm
& 0x0f) > 0) && ((ir
.modrm
& 0x0f) <= 7))
5110 if (i386_record_floats (gdbarch
, &ir
,
5111 I387_ST0_REGNUM (tdep
) +
5115 else if ((ir
.modrm
& 0x0f) - 0x08)
5117 if (i386_record_floats (gdbarch
, &ir
,
5118 I387_ST0_REGNUM (tdep
) +
5119 ((ir
.modrm
& 0x0f) - 0x08)))
5125 if (0xe3 == ir
.modrm
)
5127 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_ENV
))
5130 else if ((0x0c == ir
.modrm
>> 4) || (0x0d == ir
.modrm
>> 4))
5132 if (i386_record_floats (gdbarch
, &ir
,
5133 I387_ST0_REGNUM (tdep
)))
5135 if (((ir
.modrm
& 0x0f) > 0) && ((ir
.modrm
& 0x0f) <= 7))
5137 if (i386_record_floats (gdbarch
, &ir
,
5138 I387_ST0_REGNUM (tdep
) +
5142 else if ((ir
.modrm
& 0x0f) - 0x08)
5144 if (i386_record_floats (gdbarch
, &ir
,
5145 I387_ST0_REGNUM (tdep
) +
5146 ((ir
.modrm
& 0x0f) - 0x08)))
5152 if ((0x0c == ir
.modrm
>> 4)
5153 || (0x0d == ir
.modrm
>> 4)
5154 || (0x0f == ir
.modrm
>> 4))
5156 if ((ir
.modrm
& 0x0f) <= 7)
5158 if (i386_record_floats (gdbarch
, &ir
,
5159 I387_ST0_REGNUM (tdep
) +
5165 if (i386_record_floats (gdbarch
, &ir
,
5166 I387_ST0_REGNUM (tdep
) +
5167 ((ir
.modrm
& 0x0f) - 0x08)))
5173 if (0x0c == ir
.modrm
>> 4)
5175 if (i386_record_floats (gdbarch
, &ir
,
5176 I387_FTAG_REGNUM (tdep
)))
5179 else if ((0x0d == ir
.modrm
>> 4) || (0x0e == ir
.modrm
>> 4))
5181 if ((ir
.modrm
& 0x0f) <= 7)
5183 if (i386_record_floats (gdbarch
, &ir
,
5184 I387_ST0_REGNUM (tdep
) +
5190 if (i386_record_floats (gdbarch
, &ir
,
5191 I386_SAVE_FPU_REGS
))
5197 if ((0x0c == ir
.modrm
>> 4)
5198 || (0x0e == ir
.modrm
>> 4)
5199 || (0x0f == ir
.modrm
>> 4)
5200 || (0xd9 == ir
.modrm
))
5202 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5207 if (0xe0 == ir
.modrm
)
5209 if (record_arch_list_add_reg (ir
.regcache
, I386_EAX_REGNUM
))
5212 else if ((0x0f == ir
.modrm
>> 4) || (0x0e == ir
.modrm
>> 4))
5214 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5222 case 0xa4: /* movsS */
5224 case 0xaa: /* stosS */
5226 case 0x6c: /* insS */
5228 regcache_raw_read_unsigned (ir
.regcache
,
5229 ir
.regmap
[X86_RECORD_RECX_REGNUM
],
5235 if ((opcode
& 1) == 0)
5238 ir
.ot
= ir
.dflag
+ OT_WORD
;
5239 regcache_raw_read_unsigned (ir
.regcache
,
5240 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
5243 regcache_raw_read_unsigned (ir
.regcache
,
5244 ir
.regmap
[X86_RECORD_ES_REGNUM
],
5246 regcache_raw_read_unsigned (ir
.regcache
,
5247 ir
.regmap
[X86_RECORD_DS_REGNUM
],
5249 if (ir
.aflag
&& (es
!= ds
))
5251 /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */
5252 if (record_memory_query
)
5256 target_terminal_ours ();
5258 Process record ignores the memory change of instruction at address %s\n\
5259 because it can't get the value of the segment register.\n\
5260 Do you want to stop the program?"),
5261 paddress (gdbarch
, ir
.orig_addr
));
5262 target_terminal_inferior ();
5269 if (record_arch_list_add_mem (addr
, 1 << ir
.ot
))
5273 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5274 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5275 if (opcode
== 0xa4 || opcode
== 0xa5)
5276 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
5277 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
5278 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5282 case 0xa6: /* cmpsS */
5284 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
5285 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
5286 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5287 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5288 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5291 case 0xac: /* lodsS */
5293 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5294 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
5295 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5296 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5297 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5300 case 0xae: /* scasS */
5302 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
5303 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5304 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5305 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5308 case 0x6e: /* outsS */
5310 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
5311 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5312 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5313 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5316 case 0xe4: /* port I/O */
5320 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5321 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5331 case 0xc2: /* ret im */
5332 case 0xc3: /* ret */
5333 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5334 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5337 case 0xca: /* lret im */
5338 case 0xcb: /* lret */
5339 case 0xcf: /* iret */
5340 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
5341 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5342 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5345 case 0xe8: /* call im */
5346 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5348 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5352 case 0x9a: /* lcall im */
5353 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5358 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
5359 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5363 case 0xe9: /* jmp im */
5364 case 0xea: /* ljmp im */
5365 case 0xeb: /* jmp Jb */
5366 case 0x70: /* jcc Jb */
5382 case 0x0f80: /* jcc Jv */
5400 case 0x0f90: /* setcc Gv */
5416 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5418 if (i386_record_modrm (&ir
))
5421 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rex_b
? (ir
.rm
| ir
.rex_b
)
5425 if (i386_record_lea_modrm (&ir
))
5430 case 0x0f40: /* cmov Gv, Ev */
5446 if (i386_record_modrm (&ir
))
5449 if (ir
.dflag
== OT_BYTE
)
5451 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
5455 case 0x9c: /* pushf */
5456 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5457 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5459 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5463 case 0x9d: /* popf */
5464 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5465 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5468 case 0x9e: /* sahf */
5469 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5475 case 0xf5: /* cmc */
5476 case 0xf8: /* clc */
5477 case 0xf9: /* stc */
5478 case 0xfc: /* cld */
5479 case 0xfd: /* std */
5480 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5483 case 0x9f: /* lahf */
5484 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5489 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5490 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5493 /* bit operations */
5494 case 0x0fba: /* bt/bts/btr/btc Gv, im */
5495 ir
.ot
= ir
.dflag
+ OT_WORD
;
5496 if (i386_record_modrm (&ir
))
5501 opcode
= opcode
<< 8 | ir
.modrm
;
5507 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5510 if (i386_record_lea_modrm (&ir
))
5514 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5517 case 0x0fa3: /* bt Gv, Ev */
5518 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5521 case 0x0fab: /* bts */
5522 case 0x0fb3: /* btr */
5523 case 0x0fbb: /* btc */
5524 ir
.ot
= ir
.dflag
+ OT_WORD
;
5525 if (i386_record_modrm (&ir
))
5528 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5532 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
5534 regcache_raw_read_unsigned (ir
.regcache
,
5535 ir
.regmap
[ir
.reg
| rex_r
],
5540 addr64
+= ((int16_t) addr
>> 4) << 4;
5543 addr64
+= ((int32_t) addr
>> 5) << 5;
5546 addr64
+= ((int64_t) addr
>> 6) << 6;
5549 if (record_arch_list_add_mem (addr64
, 1 << ir
.ot
))
5551 if (i386_record_lea_modrm (&ir
))
5554 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5557 case 0x0fbc: /* bsf */
5558 case 0x0fbd: /* bsr */
5559 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
5560 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5564 case 0x27: /* daa */
5565 case 0x2f: /* das */
5566 case 0x37: /* aaa */
5567 case 0x3f: /* aas */
5568 case 0xd4: /* aam */
5569 case 0xd5: /* aad */
5570 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5575 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5576 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5580 case 0x90: /* nop */
5581 if (prefixes
& PREFIX_LOCK
)
5588 case 0x9b: /* fwait */
5589 if (target_read_memory (ir
.addr
, &opcode8
, 1))
5592 printf_unfiltered (_("Process record: error reading memory at "
5593 "addr 0x%s len = 1.\n"),
5594 paddress (gdbarch
, ir
.addr
));
5597 opcode
= (uint32_t) opcode8
;
5603 case 0xcc: /* int3 */
5604 printf_unfiltered (_("Process record does not support instruction "
5611 case 0xcd: /* int */
5615 if (target_read_memory (ir
.addr
, &interrupt
, 1))
5618 printf_unfiltered (_("Process record: error reading memory "
5619 "at addr %s len = 1.\n"),
5620 paddress (gdbarch
, ir
.addr
));
5624 if (interrupt
!= 0x80
5625 || tdep
->i386_intx80_record
== NULL
)
5627 printf_unfiltered (_("Process record does not support "
5628 "instruction int 0x%02x.\n"),
5633 ret
= tdep
->i386_intx80_record (ir
.regcache
);
5640 case 0xce: /* into */
5641 printf_unfiltered (_("Process record does not support "
5642 "instruction into.\n"));
5647 case 0xfa: /* cli */
5648 case 0xfb: /* sti */
5651 case 0x62: /* bound */
5652 printf_unfiltered (_("Process record does not support "
5653 "instruction bound.\n"));
5658 case 0x0fc8: /* bswap reg */
5666 I386_RECORD_ARCH_LIST_ADD_REG ((opcode
& 7) | ir
.rex_b
);
5669 case 0xd6: /* salc */
5670 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5675 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5676 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5679 case 0xe0: /* loopnz */
5680 case 0xe1: /* loopz */
5681 case 0xe2: /* loop */
5682 case 0xe3: /* jecxz */
5683 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5684 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5687 case 0x0f30: /* wrmsr */
5688 printf_unfiltered (_("Process record does not support "
5689 "instruction wrmsr.\n"));
5694 case 0x0f32: /* rdmsr */
5695 printf_unfiltered (_("Process record does not support "
5696 "instruction rdmsr.\n"));
5701 case 0x0f31: /* rdtsc */
5702 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5703 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5706 case 0x0f34: /* sysenter */
5709 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5714 if (tdep
->i386_sysenter_record
== NULL
)
5716 printf_unfiltered (_("Process record does not support "
5717 "instruction sysenter.\n"));
5721 ret
= tdep
->i386_sysenter_record (ir
.regcache
);
5727 case 0x0f35: /* sysexit */
5728 printf_unfiltered (_("Process record does not support "
5729 "instruction sysexit.\n"));
5734 case 0x0f05: /* syscall */
5737 if (tdep
->i386_syscall_record
== NULL
)
5739 printf_unfiltered (_("Process record does not support "
5740 "instruction syscall.\n"));
5744 ret
= tdep
->i386_syscall_record (ir
.regcache
);
5750 case 0x0f07: /* sysret */
5751 printf_unfiltered (_("Process record does not support "
5752 "instruction sysret.\n"));
5757 case 0x0fa2: /* cpuid */
5758 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5759 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5760 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5761 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM
);
5764 case 0xf4: /* hlt */
5765 printf_unfiltered (_("Process record does not support "
5766 "instruction hlt.\n"));
5772 if (i386_record_modrm (&ir
))
5779 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5783 if (i386_record_lea_modrm (&ir
))
5792 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5796 opcode
= opcode
<< 8 | ir
.modrm
;
5803 if (i386_record_modrm (&ir
))
5814 opcode
= opcode
<< 8 | ir
.modrm
;
5817 if (ir
.override
>= 0)
5819 if (record_memory_query
)
5823 target_terminal_ours ();
5825 Process record ignores the memory change of instruction at address %s\n\
5826 because it can't get the value of the segment register.\n\
5827 Do you want to stop the program?"),
5828 paddress (gdbarch
, ir
.orig_addr
));
5829 target_terminal_inferior ();
5836 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
5838 if (record_arch_list_add_mem (addr64
, 2))
5841 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5843 if (record_arch_list_add_mem (addr64
, 8))
5848 if (record_arch_list_add_mem (addr64
, 4))
5859 case 0: /* monitor */
5862 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5866 opcode
= opcode
<< 8 | ir
.modrm
;
5874 if (ir
.override
>= 0)
5876 if (record_memory_query
)
5880 target_terminal_ours ();
5882 Process record ignores the memory change of instruction at address %s\n\
5883 because it can't get the value of the segment register.\n\
5884 Do you want to stop the program?"),
5885 paddress (gdbarch
, ir
.orig_addr
));
5886 target_terminal_inferior ();
5895 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
5897 if (record_arch_list_add_mem (addr64
, 2))
5900 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5902 if (record_arch_list_add_mem (addr64
, 8))
5907 if (record_arch_list_add_mem (addr64
, 4))
5919 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5920 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5924 else if (ir
.rm
== 1)
5931 opcode
= opcode
<< 8 | ir
.modrm
;
5938 if (record_arch_list_add_reg (ir
.regcache
, ir
.rm
| ir
.rex_b
))
5944 if (i386_record_lea_modrm (&ir
))
5947 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5950 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5952 case 7: /* invlpg */
5955 if (ir
.rm
== 0 && ir
.regmap
[X86_RECORD_R8_REGNUM
])
5956 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM
);
5960 opcode
= opcode
<< 8 | ir
.modrm
;
5965 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5969 opcode
= opcode
<< 8 | ir
.modrm
;
5975 case 0x0f08: /* invd */
5976 case 0x0f09: /* wbinvd */
5979 case 0x63: /* arpl */
5980 if (i386_record_modrm (&ir
))
5982 if (ir
.mod
== 3 || ir
.regmap
[X86_RECORD_R8_REGNUM
])
5984 I386_RECORD_ARCH_LIST_ADD_REG (ir
.regmap
[X86_RECORD_R8_REGNUM
]
5985 ? (ir
.reg
| rex_r
) : ir
.rm
);
5989 ir
.ot
= ir
.dflag
? OT_LONG
: OT_WORD
;
5990 if (i386_record_lea_modrm (&ir
))
5993 if (!ir
.regmap
[X86_RECORD_R8_REGNUM
])
5994 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5997 case 0x0f02: /* lar */
5998 case 0x0f03: /* lsl */
5999 if (i386_record_modrm (&ir
))
6001 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
6002 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6006 if (i386_record_modrm (&ir
))
6008 if (ir
.mod
== 3 && ir
.reg
== 3)
6011 opcode
= opcode
<< 8 | ir
.modrm
;
6023 /* nop (multi byte) */
6026 case 0x0f20: /* mov reg, crN */
6027 case 0x0f22: /* mov crN, reg */
6028 if (i386_record_modrm (&ir
))
6030 if ((ir
.modrm
& 0xc0) != 0xc0)
6033 opcode
= opcode
<< 8 | ir
.modrm
;
6044 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6046 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6050 opcode
= opcode
<< 8 | ir
.modrm
;
6056 case 0x0f21: /* mov reg, drN */
6057 case 0x0f23: /* mov drN, reg */
6058 if (i386_record_modrm (&ir
))
6060 if ((ir
.modrm
& 0xc0) != 0xc0 || ir
.reg
== 4
6061 || ir
.reg
== 5 || ir
.reg
>= 8)
6064 opcode
= opcode
<< 8 | ir
.modrm
;
6068 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6070 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6073 case 0x0f06: /* clts */
6074 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6077 /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */
6079 case 0x0f0d: /* 3DNow! prefetch */
6082 case 0x0f0e: /* 3DNow! femms */
6083 case 0x0f77: /* emms */
6084 if (i386_fpc_regnum_p (gdbarch
, I387_FTAG_REGNUM(tdep
)))
6086 record_arch_list_add_reg (ir
.regcache
, I387_FTAG_REGNUM(tdep
));
6089 case 0x0f0f: /* 3DNow! data */
6090 if (i386_record_modrm (&ir
))
6092 if (target_read_memory (ir
.addr
, &opcode8
, 1))
6094 printf_unfiltered (_("Process record: error reading memory at "
6095 "addr %s len = 1.\n"),
6096 paddress (gdbarch
, ir
.addr
));
6102 case 0x0c: /* 3DNow! pi2fw */
6103 case 0x0d: /* 3DNow! pi2fd */
6104 case 0x1c: /* 3DNow! pf2iw */
6105 case 0x1d: /* 3DNow! pf2id */
6106 case 0x8a: /* 3DNow! pfnacc */
6107 case 0x8e: /* 3DNow! pfpnacc */
6108 case 0x90: /* 3DNow! pfcmpge */
6109 case 0x94: /* 3DNow! pfmin */
6110 case 0x96: /* 3DNow! pfrcp */
6111 case 0x97: /* 3DNow! pfrsqrt */
6112 case 0x9a: /* 3DNow! pfsub */
6113 case 0x9e: /* 3DNow! pfadd */
6114 case 0xa0: /* 3DNow! pfcmpgt */
6115 case 0xa4: /* 3DNow! pfmax */
6116 case 0xa6: /* 3DNow! pfrcpit1 */
6117 case 0xa7: /* 3DNow! pfrsqit1 */
6118 case 0xaa: /* 3DNow! pfsubr */
6119 case 0xae: /* 3DNow! pfacc */
6120 case 0xb0: /* 3DNow! pfcmpeq */
6121 case 0xb4: /* 3DNow! pfmul */
6122 case 0xb6: /* 3DNow! pfrcpit2 */
6123 case 0xb7: /* 3DNow! pmulhrw */
6124 case 0xbb: /* 3DNow! pswapd */
6125 case 0xbf: /* 3DNow! pavgusb */
6126 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.reg
))
6127 goto no_support_3dnow_data
;
6128 record_arch_list_add_reg (ir
.regcache
, ir
.reg
);
6132 no_support_3dnow_data
:
6133 opcode
= (opcode
<< 8) | opcode8
;
6139 case 0x0faa: /* rsm */
6140 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6141 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6142 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6143 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
6144 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM
);
6145 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
6146 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
6147 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
6148 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
6152 if (i386_record_modrm (&ir
))
6156 case 0: /* fxsave */
6160 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6161 if (i386_record_lea_modrm_addr (&ir
, &tmpu64
))
6163 if (record_arch_list_add_mem (tmpu64
, 512))
6168 case 1: /* fxrstor */
6172 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6174 for (i
= I387_MM0_REGNUM (tdep
);
6175 i386_mmx_regnum_p (gdbarch
, i
); i
++)
6176 record_arch_list_add_reg (ir
.regcache
, i
);
6178 for (i
= I387_XMM0_REGNUM (tdep
);
6179 i386_xmm_regnum_p (gdbarch
, i
); i
++)
6180 record_arch_list_add_reg (ir
.regcache
, i
);
6182 if (i386_mxcsr_regnum_p (gdbarch
, I387_MXCSR_REGNUM(tdep
)))
6183 record_arch_list_add_reg (ir
.regcache
, I387_MXCSR_REGNUM(tdep
));
6185 for (i
= I387_ST0_REGNUM (tdep
);
6186 i386_fp_regnum_p (gdbarch
, i
); i
++)
6187 record_arch_list_add_reg (ir
.regcache
, i
);
6189 for (i
= I387_FCTRL_REGNUM (tdep
);
6190 i386_fpc_regnum_p (gdbarch
, i
); i
++)
6191 record_arch_list_add_reg (ir
.regcache
, i
);
6195 case 2: /* ldmxcsr */
6196 if (!i386_mxcsr_regnum_p (gdbarch
, I387_MXCSR_REGNUM(tdep
)))
6198 record_arch_list_add_reg (ir
.regcache
, I387_MXCSR_REGNUM(tdep
));
6201 case 3: /* stmxcsr */
6203 if (i386_record_lea_modrm (&ir
))
6207 case 5: /* lfence */
6208 case 6: /* mfence */
6209 case 7: /* sfence clflush */
6213 opcode
= (opcode
<< 8) | ir
.modrm
;
6219 case 0x0fc3: /* movnti */
6220 ir
.ot
= (ir
.dflag
== 2) ? OT_QUAD
: OT_LONG
;
6221 if (i386_record_modrm (&ir
))
6226 if (i386_record_lea_modrm (&ir
))
6230 /* Add prefix to opcode. */
6357 reswitch_prefix_add
:
6365 if (target_read_memory (ir
.addr
, &opcode8
, 1))
6367 printf_unfiltered (_("Process record: error reading memory at "
6368 "addr %s len = 1.\n"),
6369 paddress (gdbarch
, ir
.addr
));
6373 opcode
= (uint32_t) opcode8
| opcode
<< 8;
6374 goto reswitch_prefix_add
;
6377 case 0x0f10: /* movups */
6378 case 0x660f10: /* movupd */
6379 case 0xf30f10: /* movss */
6380 case 0xf20f10: /* movsd */
6381 case 0x0f12: /* movlps */
6382 case 0x660f12: /* movlpd */
6383 case 0xf30f12: /* movsldup */
6384 case 0xf20f12: /* movddup */
6385 case 0x0f14: /* unpcklps */
6386 case 0x660f14: /* unpcklpd */
6387 case 0x0f15: /* unpckhps */
6388 case 0x660f15: /* unpckhpd */
6389 case 0x0f16: /* movhps */
6390 case 0x660f16: /* movhpd */
6391 case 0xf30f16: /* movshdup */
6392 case 0x0f28: /* movaps */
6393 case 0x660f28: /* movapd */
6394 case 0x0f2a: /* cvtpi2ps */
6395 case 0x660f2a: /* cvtpi2pd */
6396 case 0xf30f2a: /* cvtsi2ss */
6397 case 0xf20f2a: /* cvtsi2sd */
6398 case 0x0f2c: /* cvttps2pi */
6399 case 0x660f2c: /* cvttpd2pi */
6400 case 0x0f2d: /* cvtps2pi */
6401 case 0x660f2d: /* cvtpd2pi */
6402 case 0x660f3800: /* pshufb */
6403 case 0x660f3801: /* phaddw */
6404 case 0x660f3802: /* phaddd */
6405 case 0x660f3803: /* phaddsw */
6406 case 0x660f3804: /* pmaddubsw */
6407 case 0x660f3805: /* phsubw */
6408 case 0x660f3806: /* phsubd */
6409 case 0x660f3807: /* phsubsw */
6410 case 0x660f3808: /* psignb */
6411 case 0x660f3809: /* psignw */
6412 case 0x660f380a: /* psignd */
6413 case 0x660f380b: /* pmulhrsw */
6414 case 0x660f3810: /* pblendvb */
6415 case 0x660f3814: /* blendvps */
6416 case 0x660f3815: /* blendvpd */
6417 case 0x660f381c: /* pabsb */
6418 case 0x660f381d: /* pabsw */
6419 case 0x660f381e: /* pabsd */
6420 case 0x660f3820: /* pmovsxbw */
6421 case 0x660f3821: /* pmovsxbd */
6422 case 0x660f3822: /* pmovsxbq */
6423 case 0x660f3823: /* pmovsxwd */
6424 case 0x660f3824: /* pmovsxwq */
6425 case 0x660f3825: /* pmovsxdq */
6426 case 0x660f3828: /* pmuldq */
6427 case 0x660f3829: /* pcmpeqq */
6428 case 0x660f382a: /* movntdqa */
6429 case 0x660f3a08: /* roundps */
6430 case 0x660f3a09: /* roundpd */
6431 case 0x660f3a0a: /* roundss */
6432 case 0x660f3a0b: /* roundsd */
6433 case 0x660f3a0c: /* blendps */
6434 case 0x660f3a0d: /* blendpd */
6435 case 0x660f3a0e: /* pblendw */
6436 case 0x660f3a0f: /* palignr */
6437 case 0x660f3a20: /* pinsrb */
6438 case 0x660f3a21: /* insertps */
6439 case 0x660f3a22: /* pinsrd pinsrq */
6440 case 0x660f3a40: /* dpps */
6441 case 0x660f3a41: /* dppd */
6442 case 0x660f3a42: /* mpsadbw */
6443 case 0x660f3a60: /* pcmpestrm */
6444 case 0x660f3a61: /* pcmpestri */
6445 case 0x660f3a62: /* pcmpistrm */
6446 case 0x660f3a63: /* pcmpistri */
6447 case 0x0f51: /* sqrtps */
6448 case 0x660f51: /* sqrtpd */
6449 case 0xf20f51: /* sqrtsd */
6450 case 0xf30f51: /* sqrtss */
6451 case 0x0f52: /* rsqrtps */
6452 case 0xf30f52: /* rsqrtss */
6453 case 0x0f53: /* rcpps */
6454 case 0xf30f53: /* rcpss */
6455 case 0x0f54: /* andps */
6456 case 0x660f54: /* andpd */
6457 case 0x0f55: /* andnps */
6458 case 0x660f55: /* andnpd */
6459 case 0x0f56: /* orps */
6460 case 0x660f56: /* orpd */
6461 case 0x0f57: /* xorps */
6462 case 0x660f57: /* xorpd */
6463 case 0x0f58: /* addps */
6464 case 0x660f58: /* addpd */
6465 case 0xf20f58: /* addsd */
6466 case 0xf30f58: /* addss */
6467 case 0x0f59: /* mulps */
6468 case 0x660f59: /* mulpd */
6469 case 0xf20f59: /* mulsd */
6470 case 0xf30f59: /* mulss */
6471 case 0x0f5a: /* cvtps2pd */
6472 case 0x660f5a: /* cvtpd2ps */
6473 case 0xf20f5a: /* cvtsd2ss */
6474 case 0xf30f5a: /* cvtss2sd */
6475 case 0x0f5b: /* cvtdq2ps */
6476 case 0x660f5b: /* cvtps2dq */
6477 case 0xf30f5b: /* cvttps2dq */
6478 case 0x0f5c: /* subps */
6479 case 0x660f5c: /* subpd */
6480 case 0xf20f5c: /* subsd */
6481 case 0xf30f5c: /* subss */
6482 case 0x0f5d: /* minps */
6483 case 0x660f5d: /* minpd */
6484 case 0xf20f5d: /* minsd */
6485 case 0xf30f5d: /* minss */
6486 case 0x0f5e: /* divps */
6487 case 0x660f5e: /* divpd */
6488 case 0xf20f5e: /* divsd */
6489 case 0xf30f5e: /* divss */
6490 case 0x0f5f: /* maxps */
6491 case 0x660f5f: /* maxpd */
6492 case 0xf20f5f: /* maxsd */
6493 case 0xf30f5f: /* maxss */
6494 case 0x660f60: /* punpcklbw */
6495 case 0x660f61: /* punpcklwd */
6496 case 0x660f62: /* punpckldq */
6497 case 0x660f63: /* packsswb */
6498 case 0x660f64: /* pcmpgtb */
6499 case 0x660f65: /* pcmpgtw */
6500 case 0x660f66: /* pcmpgtd */
6501 case 0x660f67: /* packuswb */
6502 case 0x660f68: /* punpckhbw */
6503 case 0x660f69: /* punpckhwd */
6504 case 0x660f6a: /* punpckhdq */
6505 case 0x660f6b: /* packssdw */
6506 case 0x660f6c: /* punpcklqdq */
6507 case 0x660f6d: /* punpckhqdq */
6508 case 0x660f6e: /* movd */
6509 case 0x660f6f: /* movdqa */
6510 case 0xf30f6f: /* movdqu */
6511 case 0x660f70: /* pshufd */
6512 case 0xf20f70: /* pshuflw */
6513 case 0xf30f70: /* pshufhw */
6514 case 0x660f74: /* pcmpeqb */
6515 case 0x660f75: /* pcmpeqw */
6516 case 0x660f76: /* pcmpeqd */
6517 case 0x660f7c: /* haddpd */
6518 case 0xf20f7c: /* haddps */
6519 case 0x660f7d: /* hsubpd */
6520 case 0xf20f7d: /* hsubps */
6521 case 0xf30f7e: /* movq */
6522 case 0x0fc2: /* cmpps */
6523 case 0x660fc2: /* cmppd */
6524 case 0xf20fc2: /* cmpsd */
6525 case 0xf30fc2: /* cmpss */
6526 case 0x660fc4: /* pinsrw */
6527 case 0x0fc6: /* shufps */
6528 case 0x660fc6: /* shufpd */
6529 case 0x660fd0: /* addsubpd */
6530 case 0xf20fd0: /* addsubps */
6531 case 0x660fd1: /* psrlw */
6532 case 0x660fd2: /* psrld */
6533 case 0x660fd3: /* psrlq */
6534 case 0x660fd4: /* paddq */
6535 case 0x660fd5: /* pmullw */
6536 case 0xf30fd6: /* movq2dq */
6537 case 0x660fd8: /* psubusb */
6538 case 0x660fd9: /* psubusw */
6539 case 0x660fda: /* pminub */
6540 case 0x660fdb: /* pand */
6541 case 0x660fdc: /* paddusb */
6542 case 0x660fdd: /* paddusw */
6543 case 0x660fde: /* pmaxub */
6544 case 0x660fdf: /* pandn */
6545 case 0x660fe0: /* pavgb */
6546 case 0x660fe1: /* psraw */
6547 case 0x660fe2: /* psrad */
6548 case 0x660fe3: /* pavgw */
6549 case 0x660fe4: /* pmulhuw */
6550 case 0x660fe5: /* pmulhw */
6551 case 0x660fe6: /* cvttpd2dq */
6552 case 0xf20fe6: /* cvtpd2dq */
6553 case 0xf30fe6: /* cvtdq2pd */
6554 case 0x660fe8: /* psubsb */
6555 case 0x660fe9: /* psubsw */
6556 case 0x660fea: /* pminsw */
6557 case 0x660feb: /* por */
6558 case 0x660fec: /* paddsb */
6559 case 0x660fed: /* paddsw */
6560 case 0x660fee: /* pmaxsw */
6561 case 0x660fef: /* pxor */
6562 case 0xf20ff0: /* lddqu */
6563 case 0x660ff1: /* psllw */
6564 case 0x660ff2: /* pslld */
6565 case 0x660ff3: /* psllq */
6566 case 0x660ff4: /* pmuludq */
6567 case 0x660ff5: /* pmaddwd */
6568 case 0x660ff6: /* psadbw */
6569 case 0x660ff8: /* psubb */
6570 case 0x660ff9: /* psubw */
6571 case 0x660ffa: /* psubd */
6572 case 0x660ffb: /* psubq */
6573 case 0x660ffc: /* paddb */
6574 case 0x660ffd: /* paddw */
6575 case 0x660ffe: /* paddd */
6576 if (i386_record_modrm (&ir
))
6579 if (!i386_xmm_regnum_p (gdbarch
, I387_XMM0_REGNUM (tdep
) + ir
.reg
))
6581 record_arch_list_add_reg (ir
.regcache
,
6582 I387_XMM0_REGNUM (tdep
) + ir
.reg
);
6583 if ((opcode
& 0xfffffffc) == 0x660f3a60)
6584 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6587 case 0x0f11: /* movups */
6588 case 0x660f11: /* movupd */
6589 case 0xf30f11: /* movss */
6590 case 0xf20f11: /* movsd */
6591 case 0x0f13: /* movlps */
6592 case 0x660f13: /* movlpd */
6593 case 0x0f17: /* movhps */
6594 case 0x660f17: /* movhpd */
6595 case 0x0f29: /* movaps */
6596 case 0x660f29: /* movapd */
6597 case 0x660f3a14: /* pextrb */
6598 case 0x660f3a15: /* pextrw */
6599 case 0x660f3a16: /* pextrd pextrq */
6600 case 0x660f3a17: /* extractps */
6601 case 0x660f7f: /* movdqa */
6602 case 0xf30f7f: /* movdqu */
6603 if (i386_record_modrm (&ir
))
6607 if (opcode
== 0x0f13 || opcode
== 0x660f13
6608 || opcode
== 0x0f17 || opcode
== 0x660f17)
6611 if (!i386_xmm_regnum_p (gdbarch
,
6612 I387_XMM0_REGNUM (tdep
) + ir
.rm
))
6614 record_arch_list_add_reg (ir
.regcache
,
6615 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
6637 if (i386_record_lea_modrm (&ir
))
6642 case 0x0f2b: /* movntps */
6643 case 0x660f2b: /* movntpd */
6644 case 0x0fe7: /* movntq */
6645 case 0x660fe7: /* movntdq */
6648 if (opcode
== 0x0fe7)
6652 if (i386_record_lea_modrm (&ir
))
6656 case 0xf30f2c: /* cvttss2si */
6657 case 0xf20f2c: /* cvttsd2si */
6658 case 0xf30f2d: /* cvtss2si */
6659 case 0xf20f2d: /* cvtsd2si */
6660 case 0xf20f38f0: /* crc32 */
6661 case 0xf20f38f1: /* crc32 */
6662 case 0x0f50: /* movmskps */
6663 case 0x660f50: /* movmskpd */
6664 case 0x0fc5: /* pextrw */
6665 case 0x660fc5: /* pextrw */
6666 case 0x0fd7: /* pmovmskb */
6667 case 0x660fd7: /* pmovmskb */
6668 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
6671 case 0x0f3800: /* pshufb */
6672 case 0x0f3801: /* phaddw */
6673 case 0x0f3802: /* phaddd */
6674 case 0x0f3803: /* phaddsw */
6675 case 0x0f3804: /* pmaddubsw */
6676 case 0x0f3805: /* phsubw */
6677 case 0x0f3806: /* phsubd */
6678 case 0x0f3807: /* phsubsw */
6679 case 0x0f3808: /* psignb */
6680 case 0x0f3809: /* psignw */
6681 case 0x0f380a: /* psignd */
6682 case 0x0f380b: /* pmulhrsw */
6683 case 0x0f381c: /* pabsb */
6684 case 0x0f381d: /* pabsw */
6685 case 0x0f381e: /* pabsd */
6686 case 0x0f382b: /* packusdw */
6687 case 0x0f3830: /* pmovzxbw */
6688 case 0x0f3831: /* pmovzxbd */
6689 case 0x0f3832: /* pmovzxbq */
6690 case 0x0f3833: /* pmovzxwd */
6691 case 0x0f3834: /* pmovzxwq */
6692 case 0x0f3835: /* pmovzxdq */
6693 case 0x0f3837: /* pcmpgtq */
6694 case 0x0f3838: /* pminsb */
6695 case 0x0f3839: /* pminsd */
6696 case 0x0f383a: /* pminuw */
6697 case 0x0f383b: /* pminud */
6698 case 0x0f383c: /* pmaxsb */
6699 case 0x0f383d: /* pmaxsd */
6700 case 0x0f383e: /* pmaxuw */
6701 case 0x0f383f: /* pmaxud */
6702 case 0x0f3840: /* pmulld */
6703 case 0x0f3841: /* phminposuw */
6704 case 0x0f3a0f: /* palignr */
6705 case 0x0f60: /* punpcklbw */
6706 case 0x0f61: /* punpcklwd */
6707 case 0x0f62: /* punpckldq */
6708 case 0x0f63: /* packsswb */
6709 case 0x0f64: /* pcmpgtb */
6710 case 0x0f65: /* pcmpgtw */
6711 case 0x0f66: /* pcmpgtd */
6712 case 0x0f67: /* packuswb */
6713 case 0x0f68: /* punpckhbw */
6714 case 0x0f69: /* punpckhwd */
6715 case 0x0f6a: /* punpckhdq */
6716 case 0x0f6b: /* packssdw */
6717 case 0x0f6e: /* movd */
6718 case 0x0f6f: /* movq */
6719 case 0x0f70: /* pshufw */
6720 case 0x0f74: /* pcmpeqb */
6721 case 0x0f75: /* pcmpeqw */
6722 case 0x0f76: /* pcmpeqd */
6723 case 0x0fc4: /* pinsrw */
6724 case 0x0fd1: /* psrlw */
6725 case 0x0fd2: /* psrld */
6726 case 0x0fd3: /* psrlq */
6727 case 0x0fd4: /* paddq */
6728 case 0x0fd5: /* pmullw */
6729 case 0xf20fd6: /* movdq2q */
6730 case 0x0fd8: /* psubusb */
6731 case 0x0fd9: /* psubusw */
6732 case 0x0fda: /* pminub */
6733 case 0x0fdb: /* pand */
6734 case 0x0fdc: /* paddusb */
6735 case 0x0fdd: /* paddusw */
6736 case 0x0fde: /* pmaxub */
6737 case 0x0fdf: /* pandn */
6738 case 0x0fe0: /* pavgb */
6739 case 0x0fe1: /* psraw */
6740 case 0x0fe2: /* psrad */
6741 case 0x0fe3: /* pavgw */
6742 case 0x0fe4: /* pmulhuw */
6743 case 0x0fe5: /* pmulhw */
6744 case 0x0fe8: /* psubsb */
6745 case 0x0fe9: /* psubsw */
6746 case 0x0fea: /* pminsw */
6747 case 0x0feb: /* por */
6748 case 0x0fec: /* paddsb */
6749 case 0x0fed: /* paddsw */
6750 case 0x0fee: /* pmaxsw */
6751 case 0x0fef: /* pxor */
6752 case 0x0ff1: /* psllw */
6753 case 0x0ff2: /* pslld */
6754 case 0x0ff3: /* psllq */
6755 case 0x0ff4: /* pmuludq */
6756 case 0x0ff5: /* pmaddwd */
6757 case 0x0ff6: /* psadbw */
6758 case 0x0ff8: /* psubb */
6759 case 0x0ff9: /* psubw */
6760 case 0x0ffa: /* psubd */
6761 case 0x0ffb: /* psubq */
6762 case 0x0ffc: /* paddb */
6763 case 0x0ffd: /* paddw */
6764 case 0x0ffe: /* paddd */
6765 if (i386_record_modrm (&ir
))
6767 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.reg
))
6769 record_arch_list_add_reg (ir
.regcache
,
6770 I387_MM0_REGNUM (tdep
) + ir
.reg
);
6773 case 0x0f71: /* psllw */
6774 case 0x0f72: /* pslld */
6775 case 0x0f73: /* psllq */
6776 if (i386_record_modrm (&ir
))
6778 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.rm
))
6780 record_arch_list_add_reg (ir
.regcache
,
6781 I387_MM0_REGNUM (tdep
) + ir
.rm
);
6784 case 0x660f71: /* psllw */
6785 case 0x660f72: /* pslld */
6786 case 0x660f73: /* psllq */
6787 if (i386_record_modrm (&ir
))
6790 if (!i386_xmm_regnum_p (gdbarch
, I387_XMM0_REGNUM (tdep
) + ir
.rm
))
6792 record_arch_list_add_reg (ir
.regcache
,
6793 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
6796 case 0x0f7e: /* movd */
6797 case 0x660f7e: /* movd */
6798 if (i386_record_modrm (&ir
))
6801 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6808 if (i386_record_lea_modrm (&ir
))
6813 case 0x0f7f: /* movq */
6814 if (i386_record_modrm (&ir
))
6818 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.rm
))
6820 record_arch_list_add_reg (ir
.regcache
,
6821 I387_MM0_REGNUM (tdep
) + ir
.rm
);
6826 if (i386_record_lea_modrm (&ir
))
6831 case 0xf30fb8: /* popcnt */
6832 if (i386_record_modrm (&ir
))
6834 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
6835 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6838 case 0x660fd6: /* movq */
6839 if (i386_record_modrm (&ir
))
6844 if (!i386_xmm_regnum_p (gdbarch
,
6845 I387_XMM0_REGNUM (tdep
) + ir
.rm
))
6847 record_arch_list_add_reg (ir
.regcache
,
6848 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
6853 if (i386_record_lea_modrm (&ir
))
6858 case 0x660f3817: /* ptest */
6859 case 0x0f2e: /* ucomiss */
6860 case 0x660f2e: /* ucomisd */
6861 case 0x0f2f: /* comiss */
6862 case 0x660f2f: /* comisd */
6863 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6866 case 0x0ff7: /* maskmovq */
6867 regcache_raw_read_unsigned (ir
.regcache
,
6868 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
6870 if (record_arch_list_add_mem (addr
, 64))
6874 case 0x660ff7: /* maskmovdqu */
6875 regcache_raw_read_unsigned (ir
.regcache
,
6876 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
6878 if (record_arch_list_add_mem (addr
, 128))
6893 /* In the future, maybe still need to deal with need_dasm. */
6894 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM
);
6895 if (record_arch_list_add_end ())
6901 printf_unfiltered (_("Process record does not support instruction 0x%02x "
6902 "at address %s.\n"),
6903 (unsigned int) (opcode
),
6904 paddress (gdbarch
, ir
.orig_addr
));
6908 static const int i386_record_regmap
[] =
6910 I386_EAX_REGNUM
, I386_ECX_REGNUM
, I386_EDX_REGNUM
, I386_EBX_REGNUM
,
6911 I386_ESP_REGNUM
, I386_EBP_REGNUM
, I386_ESI_REGNUM
, I386_EDI_REGNUM
,
6912 0, 0, 0, 0, 0, 0, 0, 0,
6913 I386_EIP_REGNUM
, I386_EFLAGS_REGNUM
, I386_CS_REGNUM
, I386_SS_REGNUM
,
6914 I386_DS_REGNUM
, I386_ES_REGNUM
, I386_FS_REGNUM
, I386_GS_REGNUM
6917 /* Check that the given address appears suitable for a fast
6918 tracepoint, which on x86 means that we need an instruction of at
6919 least 5 bytes, so that we can overwrite it with a 4-byte-offset
6920 jump and not have to worry about program jumps to an address in the
6921 middle of the tracepoint jump. Returns 1 if OK, and writes a size
6922 of instruction to replace, and 0 if not, plus an explanatory
6926 i386_fast_tracepoint_valid_at (struct gdbarch
*gdbarch
,
6927 CORE_ADDR addr
, int *isize
, char **msg
)
6930 static struct ui_file
*gdb_null
= NULL
;
6932 /* This is based on the target agent using a 4-byte relative jump.
6933 Alternate future possibilities include 8-byte offset for x86-84,
6934 or 3-byte jumps if the program has trampoline space close by. */
6937 /* Dummy file descriptor for the disassembler. */
6939 gdb_null
= ui_file_new ();
6941 /* Check for fit. */
6942 len
= gdb_print_insn (gdbarch
, addr
, gdb_null
, NULL
);
6945 /* Return a bit of target-specific detail to add to the caller's
6946 generic failure message. */
6948 *msg
= xstrprintf (_("; instruction is only %d bytes long, "
6949 "need at least %d bytes for the jump"),
6962 i386_validate_tdesc_p (struct gdbarch_tdep
*tdep
,
6963 struct tdesc_arch_data
*tdesc_data
)
6965 const struct target_desc
*tdesc
= tdep
->tdesc
;
6966 const struct tdesc_feature
*feature_core
;
6967 const struct tdesc_feature
*feature_sse
, *feature_avx
;
6968 int i
, num_regs
, valid_p
;
6970 if (! tdesc_has_registers (tdesc
))
6973 /* Get core registers. */
6974 feature_core
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.core");
6975 if (feature_core
== NULL
)
6978 /* Get SSE registers. */
6979 feature_sse
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.sse");
6981 /* Try AVX registers. */
6982 feature_avx
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx");
6986 /* The XCR0 bits. */
6989 /* AVX register description requires SSE register description. */
6993 tdep
->xcr0
= I386_XSTATE_AVX_MASK
;
6995 /* It may have been set by OSABI initialization function. */
6996 if (tdep
->num_ymm_regs
== 0)
6998 tdep
->ymmh_register_names
= i386_ymmh_names
;
6999 tdep
->num_ymm_regs
= 8;
7000 tdep
->ymm0h_regnum
= I386_YMM0H_REGNUM
;
7003 for (i
= 0; i
< tdep
->num_ymm_regs
; i
++)
7004 valid_p
&= tdesc_numbered_register (feature_avx
, tdesc_data
,
7005 tdep
->ymm0h_regnum
+ i
,
7006 tdep
->ymmh_register_names
[i
]);
7008 else if (feature_sse
)
7009 tdep
->xcr0
= I386_XSTATE_SSE_MASK
;
7012 tdep
->xcr0
= I386_XSTATE_X87_MASK
;
7013 tdep
->num_xmm_regs
= 0;
7016 num_regs
= tdep
->num_core_regs
;
7017 for (i
= 0; i
< num_regs
; i
++)
7018 valid_p
&= tdesc_numbered_register (feature_core
, tdesc_data
, i
,
7019 tdep
->register_names
[i
]);
7023 /* Need to include %mxcsr, so add one. */
7024 num_regs
+= tdep
->num_xmm_regs
+ 1;
7025 for (; i
< num_regs
; i
++)
7026 valid_p
&= tdesc_numbered_register (feature_sse
, tdesc_data
, i
,
7027 tdep
->register_names
[i
]);
7034 static struct gdbarch
*
7035 i386_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
7037 struct gdbarch_tdep
*tdep
;
7038 struct gdbarch
*gdbarch
;
7039 struct tdesc_arch_data
*tdesc_data
;
7040 const struct target_desc
*tdesc
;
7044 /* If there is already a candidate, use it. */
7045 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
7047 return arches
->gdbarch
;
7049 /* Allocate space for the new architecture. */
7050 tdep
= XCALLOC (1, struct gdbarch_tdep
);
7051 gdbarch
= gdbarch_alloc (&info
, tdep
);
7053 /* General-purpose registers. */
7054 tdep
->gregset
= NULL
;
7055 tdep
->gregset_reg_offset
= NULL
;
7056 tdep
->gregset_num_regs
= I386_NUM_GREGS
;
7057 tdep
->sizeof_gregset
= 0;
7059 /* Floating-point registers. */
7060 tdep
->fpregset
= NULL
;
7061 tdep
->sizeof_fpregset
= I387_SIZEOF_FSAVE
;
7063 tdep
->xstateregset
= NULL
;
7065 /* The default settings include the FPU registers, the MMX registers
7066 and the SSE registers. This can be overridden for a specific ABI
7067 by adjusting the members `st0_regnum', `mm0_regnum' and
7068 `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers
7069 will show up in the output of "info all-registers". */
7071 tdep
->st0_regnum
= I386_ST0_REGNUM
;
7073 /* I386_NUM_XREGS includes %mxcsr, so substract one. */
7074 tdep
->num_xmm_regs
= I386_NUM_XREGS
- 1;
7076 tdep
->jb_pc_offset
= -1;
7077 tdep
->struct_return
= pcc_struct_return
;
7078 tdep
->sigtramp_start
= 0;
7079 tdep
->sigtramp_end
= 0;
7080 tdep
->sigtramp_p
= i386_sigtramp_p
;
7081 tdep
->sigcontext_addr
= NULL
;
7082 tdep
->sc_reg_offset
= NULL
;
7083 tdep
->sc_pc_offset
= -1;
7084 tdep
->sc_sp_offset
= -1;
7086 tdep
->xsave_xcr0_offset
= -1;
7088 tdep
->record_regmap
= i386_record_regmap
;
7090 /* The format used for `long double' on almost all i386 targets is
7091 the i387 extended floating-point format. In fact, of all targets
7092 in the GCC 2.95 tree, only OSF/1 does it different, and insists
7093 on having a `long double' that's not `long' at all. */
7094 set_gdbarch_long_double_format (gdbarch
, floatformats_i387_ext
);
7096 /* Although the i387 extended floating-point has only 80 significant
7097 bits, a `long double' actually takes up 96, probably to enforce
7099 set_gdbarch_long_double_bit (gdbarch
, 96);
7101 /* Register numbers of various important registers. */
7102 set_gdbarch_sp_regnum (gdbarch
, I386_ESP_REGNUM
); /* %esp */
7103 set_gdbarch_pc_regnum (gdbarch
, I386_EIP_REGNUM
); /* %eip */
7104 set_gdbarch_ps_regnum (gdbarch
, I386_EFLAGS_REGNUM
); /* %eflags */
7105 set_gdbarch_fp0_regnum (gdbarch
, I386_ST0_REGNUM
); /* %st(0) */
7107 /* NOTE: kettenis/20040418: GCC does have two possible register
7108 numbering schemes on the i386: dbx and SVR4. These schemes
7109 differ in how they number %ebp, %esp, %eflags, and the
7110 floating-point registers, and are implemented by the arrays
7111 dbx_register_map[] and svr4_dbx_register_map in
7112 gcc/config/i386.c. GCC also defines a third numbering scheme in
7113 gcc/config/i386.c, which it designates as the "default" register
7114 map used in 64bit mode. This last register numbering scheme is
7115 implemented in dbx64_register_map, and is used for AMD64; see
7118 Currently, each GCC i386 target always uses the same register
7119 numbering scheme across all its supported debugging formats
7120 i.e. SDB (COFF), stabs and DWARF 2. This is because
7121 gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the
7122 DBX_REGISTER_NUMBER macro which is defined by each target's
7123 respective config header in a manner independent of the requested
7124 output debugging format.
7126 This does not match the arrangement below, which presumes that
7127 the SDB and stabs numbering schemes differ from the DWARF and
7128 DWARF 2 ones. The reason for this arrangement is that it is
7129 likely to get the numbering scheme for the target's
7130 default/native debug format right. For targets where GCC is the
7131 native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for
7132 targets where the native toolchain uses a different numbering
7133 scheme for a particular debug format (stabs-in-ELF on Solaris)
7134 the defaults below will have to be overridden, like
7135 i386_elf_init_abi() does. */
7137 /* Use the dbx register numbering scheme for stabs and COFF. */
7138 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
7139 set_gdbarch_sdb_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
7141 /* Use the SVR4 register numbering scheme for DWARF 2. */
7142 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
7144 /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to
7145 be in use on any of the supported i386 targets. */
7147 set_gdbarch_print_float_info (gdbarch
, i387_print_float_info
);
7149 set_gdbarch_get_longjmp_target (gdbarch
, i386_get_longjmp_target
);
7151 /* Call dummy code. */
7152 set_gdbarch_push_dummy_call (gdbarch
, i386_push_dummy_call
);
7154 set_gdbarch_convert_register_p (gdbarch
, i386_convert_register_p
);
7155 set_gdbarch_register_to_value (gdbarch
, i386_register_to_value
);
7156 set_gdbarch_value_to_register (gdbarch
, i386_value_to_register
);
7158 set_gdbarch_return_value (gdbarch
, i386_return_value
);
7160 set_gdbarch_skip_prologue (gdbarch
, i386_skip_prologue
);
7162 /* Stack grows downward. */
7163 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
7165 set_gdbarch_breakpoint_from_pc (gdbarch
, i386_breakpoint_from_pc
);
7166 set_gdbarch_decr_pc_after_break (gdbarch
, 1);
7167 set_gdbarch_max_insn_length (gdbarch
, I386_MAX_INSN_LEN
);
7169 set_gdbarch_frame_args_skip (gdbarch
, 8);
7171 set_gdbarch_print_insn (gdbarch
, i386_print_insn
);
7173 set_gdbarch_dummy_id (gdbarch
, i386_dummy_id
);
7175 set_gdbarch_unwind_pc (gdbarch
, i386_unwind_pc
);
7177 /* Add the i386 register groups. */
7178 i386_add_reggroups (gdbarch
);
7179 tdep
->register_reggroup_p
= i386_register_reggroup_p
;
7181 /* Helper for function argument information. */
7182 set_gdbarch_fetch_pointer_argument (gdbarch
, i386_fetch_pointer_argument
);
7184 /* Hook the function epilogue frame unwinder. This unwinder is
7185 appended to the list first, so that it supercedes the Dwarf
7186 unwinder in function epilogues (where the Dwarf unwinder
7187 currently fails). */
7188 frame_unwind_append_unwinder (gdbarch
, &i386_epilogue_frame_unwind
);
7190 /* Hook in the DWARF CFI frame unwinder. This unwinder is appended
7191 to the list before the prologue-based unwinders, so that Dwarf
7192 CFI info will be used if it is available. */
7193 dwarf2_append_unwinders (gdbarch
);
7195 frame_base_set_default (gdbarch
, &i386_frame_base
);
7197 /* Pseudo registers may be changed by amd64_init_abi. */
7198 set_gdbarch_pseudo_register_read (gdbarch
, i386_pseudo_register_read
);
7199 set_gdbarch_pseudo_register_write (gdbarch
, i386_pseudo_register_write
);
7201 set_tdesc_pseudo_register_type (gdbarch
, i386_pseudo_register_type
);
7202 set_tdesc_pseudo_register_name (gdbarch
, i386_pseudo_register_name
);
7204 /* Override the normal target description method to make the AVX
7205 upper halves anonymous. */
7206 set_gdbarch_register_name (gdbarch
, i386_register_name
);
7208 /* Even though the default ABI only includes general-purpose registers,
7209 floating-point registers and the SSE registers, we have to leave a
7210 gap for the upper AVX registers. */
7211 set_gdbarch_num_regs (gdbarch
, I386_AVX_NUM_REGS
);
7213 /* Get the x86 target description from INFO. */
7214 tdesc
= info
.target_desc
;
7215 if (! tdesc_has_registers (tdesc
))
7217 tdep
->tdesc
= tdesc
;
7219 tdep
->num_core_regs
= I386_NUM_GREGS
+ I387_NUM_REGS
;
7220 tdep
->register_names
= i386_register_names
;
7222 /* No upper YMM registers. */
7223 tdep
->ymmh_register_names
= NULL
;
7224 tdep
->ymm0h_regnum
= -1;
7226 tdep
->num_byte_regs
= 8;
7227 tdep
->num_word_regs
= 8;
7228 tdep
->num_dword_regs
= 0;
7229 tdep
->num_mmx_regs
= 8;
7230 tdep
->num_ymm_regs
= 0;
7232 tdesc_data
= tdesc_data_alloc ();
7234 set_gdbarch_relocate_instruction (gdbarch
, i386_relocate_instruction
);
7236 /* Hook in ABI-specific overrides, if they have been registered. */
7237 info
.tdep_info
= (void *) tdesc_data
;
7238 gdbarch_init_osabi (info
, gdbarch
);
7240 if (!i386_validate_tdesc_p (tdep
, tdesc_data
))
7242 tdesc_data_cleanup (tdesc_data
);
7244 gdbarch_free (gdbarch
);
7248 /* Wire in pseudo registers. Number of pseudo registers may be
7250 set_gdbarch_num_pseudo_regs (gdbarch
, (tdep
->num_byte_regs
7251 + tdep
->num_word_regs
7252 + tdep
->num_dword_regs
7253 + tdep
->num_mmx_regs
7254 + tdep
->num_ymm_regs
));
7256 /* Target description may be changed. */
7257 tdesc
= tdep
->tdesc
;
7259 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
7261 /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */
7262 set_gdbarch_register_reggroup_p (gdbarch
, tdep
->register_reggroup_p
);
7264 /* Make %al the first pseudo-register. */
7265 tdep
->al_regnum
= gdbarch_num_regs (gdbarch
);
7266 tdep
->ax_regnum
= tdep
->al_regnum
+ tdep
->num_byte_regs
;
7268 ymm0_regnum
= tdep
->ax_regnum
+ tdep
->num_word_regs
;
7269 if (tdep
->num_dword_regs
)
7271 /* Support dword pseudo-register if it hasn't been disabled. */
7272 tdep
->eax_regnum
= ymm0_regnum
;
7273 ymm0_regnum
+= tdep
->num_dword_regs
;
7276 tdep
->eax_regnum
= -1;
7278 mm0_regnum
= ymm0_regnum
;
7279 if (tdep
->num_ymm_regs
)
7281 /* Support YMM pseudo-register if it is available. */
7282 tdep
->ymm0_regnum
= ymm0_regnum
;
7283 mm0_regnum
+= tdep
->num_ymm_regs
;
7286 tdep
->ymm0_regnum
= -1;
7288 if (tdep
->num_mmx_regs
!= 0)
7290 /* Support MMX pseudo-register if MMX hasn't been disabled. */
7291 tdep
->mm0_regnum
= mm0_regnum
;
7294 tdep
->mm0_regnum
= -1;
7296 /* Hook in the legacy prologue-based unwinders last (fallback). */
7297 frame_unwind_append_unwinder (gdbarch
, &i386_sigtramp_frame_unwind
);
7298 frame_unwind_append_unwinder (gdbarch
, &i386_frame_unwind
);
7300 /* If we have a register mapping, enable the generic core file
7301 support, unless it has already been enabled. */
7302 if (tdep
->gregset_reg_offset
7303 && !gdbarch_regset_from_core_section_p (gdbarch
))
7304 set_gdbarch_regset_from_core_section (gdbarch
,
7305 i386_regset_from_core_section
);
7307 set_gdbarch_skip_permanent_breakpoint (gdbarch
,
7308 i386_skip_permanent_breakpoint
);
7310 set_gdbarch_fast_tracepoint_valid_at (gdbarch
,
7311 i386_fast_tracepoint_valid_at
);
7316 static enum gdb_osabi
7317 i386_coff_osabi_sniffer (bfd
*abfd
)
7319 if (strcmp (bfd_get_target (abfd
), "coff-go32-exe") == 0
7320 || strcmp (bfd_get_target (abfd
), "coff-go32") == 0)
7321 return GDB_OSABI_GO32
;
7323 return GDB_OSABI_UNKNOWN
;
7327 /* Provide a prototype to silence -Wmissing-prototypes. */
7328 void _initialize_i386_tdep (void);
7331 _initialize_i386_tdep (void)
7333 register_gdbarch_init (bfd_arch_i386
, i386_gdbarch_init
);
7335 /* Add the variable that controls the disassembly flavor. */
7336 add_setshow_enum_cmd ("disassembly-flavor", no_class
, valid_flavors
,
7337 &disassembly_flavor
, _("\
7338 Set the disassembly flavor."), _("\
7339 Show the disassembly flavor."), _("\
7340 The valid values are \"att\" and \"intel\", and the default value is \"att\"."),
7342 NULL
, /* FIXME: i18n: */
7343 &setlist
, &showlist
);
7345 /* Add the variable that controls the convention for returning
7347 add_setshow_enum_cmd ("struct-convention", no_class
, valid_conventions
,
7348 &struct_convention
, _("\
7349 Set the convention for returning small structs."), _("\
7350 Show the convention for returning small structs."), _("\
7351 Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\
7354 NULL
, /* FIXME: i18n: */
7355 &setlist
, &showlist
);
7357 gdbarch_register_osabi_sniffer (bfd_arch_i386
, bfd_target_coff_flavour
,
7358 i386_coff_osabi_sniffer
);
7360 gdbarch_register_osabi (bfd_arch_i386
, 0, GDB_OSABI_SVR4
,
7361 i386_svr4_init_abi
);
7362 gdbarch_register_osabi (bfd_arch_i386
, 0, GDB_OSABI_GO32
,
7363 i386_go32_init_abi
);
7365 /* Initialize the i386-specific register groups. */
7366 i386_init_reggroups ();
7368 /* Initialize the standard target descriptions. */
7369 initialize_tdesc_i386 ();
7370 initialize_tdesc_i386_mmx ();
7371 initialize_tdesc_i386_avx ();
7373 /* Tell remote stub that we support XML target description. */
7374 register_remote_support_xml ("i386");