1 /* Intel 386 target-dependent stuff.
3 Copyright (C) 1988-2020 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "opcode/i386.h"
22 #include "arch-utils.h"
24 #include "dummy-frame.h"
25 #include "dwarf2/frame.h"
27 #include "frame-base.h"
28 #include "frame-unwind.h"
37 #include "reggroups.h"
42 #include "target-float.h"
47 #include "i386-tdep.h"
48 #include "i387-tdep.h"
49 #include "gdbsupport/x86-xstate.h"
53 #include "record-full.h"
54 #include "target-descriptions.h"
55 #include "arch/i386.h"
60 #include "stap-probe.h"
61 #include "user-regs.h"
62 #include "cli/cli-utils.h"
63 #include "expression.h"
64 #include "parser-defs.h"
67 #include <unordered_set>
72 static const char * const i386_register_names
[] =
74 "eax", "ecx", "edx", "ebx",
75 "esp", "ebp", "esi", "edi",
76 "eip", "eflags", "cs", "ss",
77 "ds", "es", "fs", "gs",
78 "st0", "st1", "st2", "st3",
79 "st4", "st5", "st6", "st7",
80 "fctrl", "fstat", "ftag", "fiseg",
81 "fioff", "foseg", "fooff", "fop",
82 "xmm0", "xmm1", "xmm2", "xmm3",
83 "xmm4", "xmm5", "xmm6", "xmm7",
87 static const char * const i386_zmm_names
[] =
89 "zmm0", "zmm1", "zmm2", "zmm3",
90 "zmm4", "zmm5", "zmm6", "zmm7"
93 static const char * const i386_zmmh_names
[] =
95 "zmm0h", "zmm1h", "zmm2h", "zmm3h",
96 "zmm4h", "zmm5h", "zmm6h", "zmm7h"
99 static const char * const i386_k_names
[] =
101 "k0", "k1", "k2", "k3",
102 "k4", "k5", "k6", "k7"
105 static const char * const i386_ymm_names
[] =
107 "ymm0", "ymm1", "ymm2", "ymm3",
108 "ymm4", "ymm5", "ymm6", "ymm7",
111 static const char * const i386_ymmh_names
[] =
113 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
114 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
117 static const char * const i386_mpx_names
[] =
119 "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus"
122 static const char * const i386_pkeys_names
[] =
127 /* Register names for MPX pseudo-registers. */
129 static const char * const i386_bnd_names
[] =
131 "bnd0", "bnd1", "bnd2", "bnd3"
134 /* Register names for MMX pseudo-registers. */
136 static const char * const i386_mmx_names
[] =
138 "mm0", "mm1", "mm2", "mm3",
139 "mm4", "mm5", "mm6", "mm7"
142 /* Register names for byte pseudo-registers. */
144 static const char * const i386_byte_names
[] =
146 "al", "cl", "dl", "bl",
147 "ah", "ch", "dh", "bh"
150 /* Register names for word pseudo-registers. */
152 static const char * const i386_word_names
[] =
154 "ax", "cx", "dx", "bx",
158 /* Constant used for reading/writing pseudo registers. In 64-bit mode, we have
159 16 lower ZMM regs that extend corresponding xmm/ymm registers. In addition,
160 we have 16 upper ZMM regs that have to be handled differently. */
162 const int num_lower_zmm_regs
= 16;
167 i386_mmx_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
169 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
170 int mm0_regnum
= tdep
->mm0_regnum
;
175 regnum
-= mm0_regnum
;
176 return regnum
>= 0 && regnum
< tdep
->num_mmx_regs
;
182 i386_byte_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
184 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
186 regnum
-= tdep
->al_regnum
;
187 return regnum
>= 0 && regnum
< tdep
->num_byte_regs
;
193 i386_word_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
195 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
197 regnum
-= tdep
->ax_regnum
;
198 return regnum
>= 0 && regnum
< tdep
->num_word_regs
;
201 /* Dword register? */
204 i386_dword_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
206 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
207 int eax_regnum
= tdep
->eax_regnum
;
212 regnum
-= eax_regnum
;
213 return regnum
>= 0 && regnum
< tdep
->num_dword_regs
;
216 /* AVX512 register? */
219 i386_zmmh_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
221 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
222 int zmm0h_regnum
= tdep
->zmm0h_regnum
;
224 if (zmm0h_regnum
< 0)
227 regnum
-= zmm0h_regnum
;
228 return regnum
>= 0 && regnum
< tdep
->num_zmm_regs
;
232 i386_zmm_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
234 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
235 int zmm0_regnum
= tdep
->zmm0_regnum
;
240 regnum
-= zmm0_regnum
;
241 return regnum
>= 0 && regnum
< tdep
->num_zmm_regs
;
245 i386_k_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
247 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
248 int k0_regnum
= tdep
->k0_regnum
;
254 return regnum
>= 0 && regnum
< I387_NUM_K_REGS
;
258 i386_ymmh_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
260 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
261 int ymm0h_regnum
= tdep
->ymm0h_regnum
;
263 if (ymm0h_regnum
< 0)
266 regnum
-= ymm0h_regnum
;
267 return regnum
>= 0 && regnum
< tdep
->num_ymm_regs
;
273 i386_ymm_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
275 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
276 int ymm0_regnum
= tdep
->ymm0_regnum
;
281 regnum
-= ymm0_regnum
;
282 return regnum
>= 0 && regnum
< tdep
->num_ymm_regs
;
286 i386_ymmh_avx512_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
288 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
289 int ymm16h_regnum
= tdep
->ymm16h_regnum
;
291 if (ymm16h_regnum
< 0)
294 regnum
-= ymm16h_regnum
;
295 return regnum
>= 0 && regnum
< tdep
->num_ymm_avx512_regs
;
299 i386_ymm_avx512_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
301 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
302 int ymm16_regnum
= tdep
->ymm16_regnum
;
304 if (ymm16_regnum
< 0)
307 regnum
-= ymm16_regnum
;
308 return regnum
>= 0 && regnum
< tdep
->num_ymm_avx512_regs
;
314 i386_bnd_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
316 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
317 int bnd0_regnum
= tdep
->bnd0_regnum
;
322 regnum
-= bnd0_regnum
;
323 return regnum
>= 0 && regnum
< I387_NUM_BND_REGS
;
329 i386_xmm_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
331 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
332 int num_xmm_regs
= I387_NUM_XMM_REGS (tdep
);
334 if (num_xmm_regs
== 0)
337 regnum
-= I387_XMM0_REGNUM (tdep
);
338 return regnum
>= 0 && regnum
< num_xmm_regs
;
341 /* XMM_512 register? */
344 i386_xmm_avx512_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
346 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
347 int num_xmm_avx512_regs
= I387_NUM_XMM_AVX512_REGS (tdep
);
349 if (num_xmm_avx512_regs
== 0)
352 regnum
-= I387_XMM16_REGNUM (tdep
);
353 return regnum
>= 0 && regnum
< num_xmm_avx512_regs
;
357 i386_mxcsr_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
359 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
361 if (I387_NUM_XMM_REGS (tdep
) == 0)
364 return (regnum
== I387_MXCSR_REGNUM (tdep
));
370 i386_fp_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
372 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
374 if (I387_ST0_REGNUM (tdep
) < 0)
377 return (I387_ST0_REGNUM (tdep
) <= regnum
378 && regnum
< I387_FCTRL_REGNUM (tdep
));
382 i386_fpc_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
384 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
386 if (I387_ST0_REGNUM (tdep
) < 0)
389 return (I387_FCTRL_REGNUM (tdep
) <= regnum
390 && regnum
< I387_XMM0_REGNUM (tdep
));
393 /* BNDr (raw) register? */
396 i386_bndr_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
398 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
400 if (I387_BND0R_REGNUM (tdep
) < 0)
403 regnum
-= tdep
->bnd0r_regnum
;
404 return regnum
>= 0 && regnum
< I387_NUM_BND_REGS
;
407 /* BND control register? */
410 i386_mpx_ctrl_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
412 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
414 if (I387_BNDCFGU_REGNUM (tdep
) < 0)
417 regnum
-= I387_BNDCFGU_REGNUM (tdep
);
418 return regnum
>= 0 && regnum
< I387_NUM_MPX_CTRL_REGS
;
424 i386_pkru_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
426 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
427 int pkru_regnum
= tdep
->pkru_regnum
;
432 regnum
-= pkru_regnum
;
433 return regnum
>= 0 && regnum
< I387_NUM_PKEYS_REGS
;
436 /* Return the name of register REGNUM, or the empty string if it is
437 an anonymous register. */
440 i386_register_name (struct gdbarch
*gdbarch
, int regnum
)
442 /* Hide the upper YMM registers. */
443 if (i386_ymmh_regnum_p (gdbarch
, regnum
))
446 /* Hide the upper YMM16-31 registers. */
447 if (i386_ymmh_avx512_regnum_p (gdbarch
, regnum
))
450 /* Hide the upper ZMM registers. */
451 if (i386_zmmh_regnum_p (gdbarch
, regnum
))
454 return tdesc_register_name (gdbarch
, regnum
);
457 /* Return the name of register REGNUM. */
460 i386_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
462 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
463 if (i386_bnd_regnum_p (gdbarch
, regnum
))
464 return i386_bnd_names
[regnum
- tdep
->bnd0_regnum
];
465 if (i386_mmx_regnum_p (gdbarch
, regnum
))
466 return i386_mmx_names
[regnum
- I387_MM0_REGNUM (tdep
)];
467 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
468 return i386_ymm_names
[regnum
- tdep
->ymm0_regnum
];
469 else if (i386_zmm_regnum_p (gdbarch
, regnum
))
470 return i386_zmm_names
[regnum
- tdep
->zmm0_regnum
];
471 else if (i386_byte_regnum_p (gdbarch
, regnum
))
472 return i386_byte_names
[regnum
- tdep
->al_regnum
];
473 else if (i386_word_regnum_p (gdbarch
, regnum
))
474 return i386_word_names
[regnum
- tdep
->ax_regnum
];
476 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
479 /* Convert a dbx register number REG to the appropriate register
480 number used by GDB. */
483 i386_dbx_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
485 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
487 /* This implements what GCC calls the "default" register map
488 (dbx_register_map[]). */
490 if (reg
>= 0 && reg
<= 7)
492 /* General-purpose registers. The debug info calls %ebp
493 register 4, and %esp register 5. */
500 else if (reg
>= 12 && reg
<= 19)
502 /* Floating-point registers. */
503 return reg
- 12 + I387_ST0_REGNUM (tdep
);
505 else if (reg
>= 21 && reg
<= 28)
508 int ymm0_regnum
= tdep
->ymm0_regnum
;
511 && i386_xmm_regnum_p (gdbarch
, reg
))
512 return reg
- 21 + ymm0_regnum
;
514 return reg
- 21 + I387_XMM0_REGNUM (tdep
);
516 else if (reg
>= 29 && reg
<= 36)
519 return reg
- 29 + I387_MM0_REGNUM (tdep
);
522 /* This will hopefully provoke a warning. */
523 return gdbarch_num_cooked_regs (gdbarch
);
526 /* Convert SVR4 DWARF register number REG to the appropriate register number
530 i386_svr4_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
532 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
534 /* This implements the GCC register map that tries to be compatible
535 with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */
537 /* The SVR4 register numbering includes %eip and %eflags, and
538 numbers the floating point registers differently. */
539 if (reg
>= 0 && reg
<= 9)
541 /* General-purpose registers. */
544 else if (reg
>= 11 && reg
<= 18)
546 /* Floating-point registers. */
547 return reg
- 11 + I387_ST0_REGNUM (tdep
);
549 else if (reg
>= 21 && reg
<= 36)
551 /* The SSE and MMX registers have the same numbers as with dbx. */
552 return i386_dbx_reg_to_regnum (gdbarch
, reg
);
557 case 37: return I387_FCTRL_REGNUM (tdep
);
558 case 38: return I387_FSTAT_REGNUM (tdep
);
559 case 39: return I387_MXCSR_REGNUM (tdep
);
560 case 40: return I386_ES_REGNUM
;
561 case 41: return I386_CS_REGNUM
;
562 case 42: return I386_SS_REGNUM
;
563 case 43: return I386_DS_REGNUM
;
564 case 44: return I386_FS_REGNUM
;
565 case 45: return I386_GS_REGNUM
;
571 /* Wrapper on i386_svr4_dwarf_reg_to_regnum to return
572 num_regs + num_pseudo_regs for other debug formats. */
575 i386_svr4_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
577 int regnum
= i386_svr4_dwarf_reg_to_regnum (gdbarch
, reg
);
580 return gdbarch_num_cooked_regs (gdbarch
);
586 /* This is the variable that is set with "set disassembly-flavor", and
587 its legitimate values. */
588 static const char att_flavor
[] = "att";
589 static const char intel_flavor
[] = "intel";
590 static const char *const valid_flavors
[] =
596 static const char *disassembly_flavor
= att_flavor
;
599 /* Use the program counter to determine the contents and size of a
600 breakpoint instruction. Return a pointer to a string of bytes that
601 encode a breakpoint instruction, store the length of the string in
602 *LEN and optionally adjust *PC to point to the correct memory
603 location for inserting the breakpoint.
605 On the i386 we have a single breakpoint that fits in a single byte
606 and can be inserted anywhere.
608 This function is 64-bit safe. */
610 constexpr gdb_byte i386_break_insn
[] = { 0xcc }; /* int 3 */
612 typedef BP_MANIPULATION (i386_break_insn
) i386_breakpoint
;
615 /* Displaced instruction handling. */
617 /* Skip the legacy instruction prefixes in INSN.
618 Not all prefixes are valid for any particular insn
619 but we needn't care, the insn will fault if it's invalid.
620 The result is a pointer to the first opcode byte,
621 or NULL if we run off the end of the buffer. */
624 i386_skip_prefixes (gdb_byte
*insn
, size_t max_len
)
626 gdb_byte
*end
= insn
+ max_len
;
632 case DATA_PREFIX_OPCODE
:
633 case ADDR_PREFIX_OPCODE
:
634 case CS_PREFIX_OPCODE
:
635 case DS_PREFIX_OPCODE
:
636 case ES_PREFIX_OPCODE
:
637 case FS_PREFIX_OPCODE
:
638 case GS_PREFIX_OPCODE
:
639 case SS_PREFIX_OPCODE
:
640 case LOCK_PREFIX_OPCODE
:
641 case REPE_PREFIX_OPCODE
:
642 case REPNE_PREFIX_OPCODE
:
654 i386_absolute_jmp_p (const gdb_byte
*insn
)
656 /* jmp far (absolute address in operand). */
662 /* jump near, absolute indirect (/4). */
663 if ((insn
[1] & 0x38) == 0x20)
666 /* jump far, absolute indirect (/5). */
667 if ((insn
[1] & 0x38) == 0x28)
674 /* Return non-zero if INSN is a jump, zero otherwise. */
677 i386_jmp_p (const gdb_byte
*insn
)
679 /* jump short, relative. */
683 /* jump near, relative. */
687 return i386_absolute_jmp_p (insn
);
691 i386_absolute_call_p (const gdb_byte
*insn
)
693 /* call far, absolute. */
699 /* Call near, absolute indirect (/2). */
700 if ((insn
[1] & 0x38) == 0x10)
703 /* Call far, absolute indirect (/3). */
704 if ((insn
[1] & 0x38) == 0x18)
712 i386_ret_p (const gdb_byte
*insn
)
716 case 0xc2: /* ret near, pop N bytes. */
717 case 0xc3: /* ret near */
718 case 0xca: /* ret far, pop N bytes. */
719 case 0xcb: /* ret far */
720 case 0xcf: /* iret */
729 i386_call_p (const gdb_byte
*insn
)
731 if (i386_absolute_call_p (insn
))
734 /* call near, relative. */
741 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
742 length in bytes. Otherwise, return zero. */
745 i386_syscall_p (const gdb_byte
*insn
, int *lengthp
)
747 /* Is it 'int $0x80'? */
748 if ((insn
[0] == 0xcd && insn
[1] == 0x80)
749 /* Or is it 'sysenter'? */
750 || (insn
[0] == 0x0f && insn
[1] == 0x34)
751 /* Or is it 'syscall'? */
752 || (insn
[0] == 0x0f && insn
[1] == 0x05))
761 /* The gdbarch insn_is_call method. */
764 i386_insn_is_call (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
766 gdb_byte buf
[I386_MAX_INSN_LEN
], *insn
;
768 read_code (addr
, buf
, I386_MAX_INSN_LEN
);
769 insn
= i386_skip_prefixes (buf
, I386_MAX_INSN_LEN
);
771 return i386_call_p (insn
);
774 /* The gdbarch insn_is_ret method. */
777 i386_insn_is_ret (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
779 gdb_byte buf
[I386_MAX_INSN_LEN
], *insn
;
781 read_code (addr
, buf
, I386_MAX_INSN_LEN
);
782 insn
= i386_skip_prefixes (buf
, I386_MAX_INSN_LEN
);
784 return i386_ret_p (insn
);
787 /* The gdbarch insn_is_jump method. */
790 i386_insn_is_jump (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
792 gdb_byte buf
[I386_MAX_INSN_LEN
], *insn
;
794 read_code (addr
, buf
, I386_MAX_INSN_LEN
);
795 insn
= i386_skip_prefixes (buf
, I386_MAX_INSN_LEN
);
797 return i386_jmp_p (insn
);
800 /* Some kernels may run one past a syscall insn, so we have to cope. */
802 displaced_step_copy_insn_closure_up
803 i386_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
804 CORE_ADDR from
, CORE_ADDR to
,
805 struct regcache
*regs
)
807 size_t len
= gdbarch_max_insn_length (gdbarch
);
808 std::unique_ptr
<i386_displaced_step_copy_insn_closure
> closure
809 (new i386_displaced_step_copy_insn_closure (len
));
810 gdb_byte
*buf
= closure
->buf
.data ();
812 read_memory (from
, buf
, len
);
814 /* GDB may get control back after the insn after the syscall.
815 Presumably this is a kernel bug.
816 If this is a syscall, make sure there's a nop afterwards. */
821 insn
= i386_skip_prefixes (buf
, len
);
822 if (insn
!= NULL
&& i386_syscall_p (insn
, &syscall_length
))
823 insn
[syscall_length
] = NOP_OPCODE
;
826 write_memory (to
, buf
, len
);
828 displaced_debug_printf ("%s->%s: %s",
829 paddress (gdbarch
, from
), paddress (gdbarch
, to
),
830 displaced_step_dump_bytes (buf
, len
).c_str ());
832 /* This is a work around for a problem with g++ 4.8. */
833 return displaced_step_copy_insn_closure_up (closure
.release ());
836 /* Fix up the state of registers and memory after having single-stepped
837 a displaced instruction. */
840 i386_displaced_step_fixup (struct gdbarch
*gdbarch
,
841 struct displaced_step_copy_insn_closure
*closure_
,
842 CORE_ADDR from
, CORE_ADDR to
,
843 struct regcache
*regs
)
845 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
847 /* The offset we applied to the instruction's address.
848 This could well be negative (when viewed as a signed 32-bit
849 value), but ULONGEST won't reflect that, so take care when
851 ULONGEST insn_offset
= to
- from
;
853 i386_displaced_step_copy_insn_closure
*closure
854 = (i386_displaced_step_copy_insn_closure
*) closure_
;
855 gdb_byte
*insn
= closure
->buf
.data ();
856 /* The start of the insn, needed in case we see some prefixes. */
857 gdb_byte
*insn_start
= insn
;
859 displaced_debug_printf ("fixup (%s, %s), insn = 0x%02x 0x%02x ...",
860 paddress (gdbarch
, from
), paddress (gdbarch
, to
),
863 /* The list of issues to contend with here is taken from
864 resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20.
865 Yay for Free Software! */
867 /* Relocate the %eip, if necessary. */
869 /* The instruction recognizers we use assume any leading prefixes
870 have been skipped. */
872 /* This is the size of the buffer in closure. */
873 size_t max_insn_len
= gdbarch_max_insn_length (gdbarch
);
874 gdb_byte
*opcode
= i386_skip_prefixes (insn
, max_insn_len
);
875 /* If there are too many prefixes, just ignore the insn.
876 It will fault when run. */
881 /* Except in the case of absolute or indirect jump or call
882 instructions, or a return instruction, the new eip is relative to
883 the displaced instruction; make it relative. Well, signal
884 handler returns don't need relocation either, but we use the
885 value of %eip to recognize those; see below. */
886 if (! i386_absolute_jmp_p (insn
)
887 && ! i386_absolute_call_p (insn
)
888 && ! i386_ret_p (insn
))
893 regcache_cooked_read_unsigned (regs
, I386_EIP_REGNUM
, &orig_eip
);
895 /* A signal trampoline system call changes the %eip, resuming
896 execution of the main program after the signal handler has
897 returned. That makes them like 'return' instructions; we
898 shouldn't relocate %eip.
900 But most system calls don't, and we do need to relocate %eip.
902 Our heuristic for distinguishing these cases: if stepping
903 over the system call instruction left control directly after
904 the instruction, the we relocate --- control almost certainly
905 doesn't belong in the displaced copy. Otherwise, we assume
906 the instruction has put control where it belongs, and leave
907 it unrelocated. Goodness help us if there are PC-relative
909 if (i386_syscall_p (insn
, &insn_len
)
910 && orig_eip
!= to
+ (insn
- insn_start
) + insn_len
911 /* GDB can get control back after the insn after the syscall.
912 Presumably this is a kernel bug.
913 i386_displaced_step_copy_insn ensures its a nop,
914 we add one to the length for it. */
915 && orig_eip
!= to
+ (insn
- insn_start
) + insn_len
+ 1)
916 displaced_debug_printf ("syscall changed %%eip; not relocating");
919 ULONGEST eip
= (orig_eip
- insn_offset
) & 0xffffffffUL
;
921 /* If we just stepped over a breakpoint insn, we don't backup
922 the pc on purpose; this is to match behaviour without
925 regcache_cooked_write_unsigned (regs
, I386_EIP_REGNUM
, eip
);
927 displaced_debug_printf ("relocated %%eip from %s to %s",
928 paddress (gdbarch
, orig_eip
),
929 paddress (gdbarch
, eip
));
933 /* If the instruction was PUSHFL, then the TF bit will be set in the
934 pushed value, and should be cleared. We'll leave this for later,
935 since GDB already messes up the TF flag when stepping over a
938 /* If the instruction was a call, the return address now atop the
939 stack is the address following the copied instruction. We need
940 to make it the address following the original instruction. */
941 if (i386_call_p (insn
))
945 const ULONGEST retaddr_len
= 4;
947 regcache_cooked_read_unsigned (regs
, I386_ESP_REGNUM
, &esp
);
948 retaddr
= read_memory_unsigned_integer (esp
, retaddr_len
, byte_order
);
949 retaddr
= (retaddr
- insn_offset
) & 0xffffffffUL
;
950 write_memory_unsigned_integer (esp
, retaddr_len
, byte_order
, retaddr
);
952 displaced_debug_printf ("relocated return addr at %s to %s",
953 paddress (gdbarch
, esp
),
954 paddress (gdbarch
, retaddr
));
959 append_insns (CORE_ADDR
*to
, ULONGEST len
, const gdb_byte
*buf
)
961 target_write_memory (*to
, buf
, len
);
966 i386_relocate_instruction (struct gdbarch
*gdbarch
,
967 CORE_ADDR
*to
, CORE_ADDR oldloc
)
969 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
970 gdb_byte buf
[I386_MAX_INSN_LEN
];
971 int offset
= 0, rel32
, newrel
;
973 gdb_byte
*insn
= buf
;
975 read_memory (oldloc
, buf
, I386_MAX_INSN_LEN
);
977 insn_length
= gdb_buffered_insn_length (gdbarch
, insn
,
978 I386_MAX_INSN_LEN
, oldloc
);
980 /* Get past the prefixes. */
981 insn
= i386_skip_prefixes (insn
, I386_MAX_INSN_LEN
);
983 /* Adjust calls with 32-bit relative addresses as push/jump, with
984 the address pushed being the location where the original call in
985 the user program would return to. */
988 gdb_byte push_buf
[16];
989 unsigned int ret_addr
;
991 /* Where "ret" in the original code will return to. */
992 ret_addr
= oldloc
+ insn_length
;
993 push_buf
[0] = 0x68; /* pushq $... */
994 store_unsigned_integer (&push_buf
[1], 4, byte_order
, ret_addr
);
996 append_insns (to
, 5, push_buf
);
998 /* Convert the relative call to a relative jump. */
1001 /* Adjust the destination offset. */
1002 rel32
= extract_signed_integer (insn
+ 1, 4, byte_order
);
1003 newrel
= (oldloc
- *to
) + rel32
;
1004 store_signed_integer (insn
+ 1, 4, byte_order
, newrel
);
1006 displaced_debug_printf ("adjusted insn rel32=%s at %s to rel32=%s at %s",
1007 hex_string (rel32
), paddress (gdbarch
, oldloc
),
1008 hex_string (newrel
), paddress (gdbarch
, *to
));
1010 /* Write the adjusted jump into its displaced location. */
1011 append_insns (to
, 5, insn
);
1015 /* Adjust jumps with 32-bit relative addresses. Calls are already
1017 if (insn
[0] == 0xe9)
1019 /* Adjust conditional jumps. */
1020 else if (insn
[0] == 0x0f && (insn
[1] & 0xf0) == 0x80)
1025 rel32
= extract_signed_integer (insn
+ offset
, 4, byte_order
);
1026 newrel
= (oldloc
- *to
) + rel32
;
1027 store_signed_integer (insn
+ offset
, 4, byte_order
, newrel
);
1028 displaced_debug_printf ("adjusted insn rel32=%s at %s to rel32=%s at %s",
1029 hex_string (rel32
), paddress (gdbarch
, oldloc
),
1030 hex_string (newrel
), paddress (gdbarch
, *to
));
1033 /* Write the adjusted instructions into their displaced
1035 append_insns (to
, insn_length
, buf
);
1039 #ifdef I386_REGNO_TO_SYMMETRY
1040 #error "The Sequent Symmetry is no longer supported."
1043 /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi
1044 and %esp "belong" to the calling function. Therefore these
1045 registers should be saved if they're going to be modified. */
1047 /* The maximum number of saved registers. This should include all
1048 registers mentioned above, and %eip. */
1049 #define I386_NUM_SAVED_REGS I386_NUM_GREGS
1051 struct i386_frame_cache
1059 /* Saved registers. */
1060 CORE_ADDR saved_regs
[I386_NUM_SAVED_REGS
];
1065 /* Stack space reserved for local variables. */
1069 /* Allocate and initialize a frame cache. */
1071 static struct i386_frame_cache
*
1072 i386_alloc_frame_cache (void)
1074 struct i386_frame_cache
*cache
;
1077 cache
= FRAME_OBSTACK_ZALLOC (struct i386_frame_cache
);
1082 cache
->sp_offset
= -4;
1085 /* Saved registers. We initialize these to -1 since zero is a valid
1086 offset (that's where %ebp is supposed to be stored). */
1087 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
1088 cache
->saved_regs
[i
] = -1;
1089 cache
->saved_sp
= 0;
1090 cache
->saved_sp_reg
= -1;
1091 cache
->pc_in_eax
= 0;
1093 /* Frameless until proven otherwise. */
1099 /* If the instruction at PC is a jump, return the address of its
1100 target. Otherwise, return PC. */
1103 i386_follow_jump (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1105 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1110 if (target_read_code (pc
, &op
, 1))
1117 op
= read_code_unsigned_integer (pc
+ 1, 1, byte_order
);
1123 /* Relative jump: if data16 == 0, disp32, else disp16. */
1126 delta
= read_memory_integer (pc
+ 2, 2, byte_order
);
1128 /* Include the size of the jmp instruction (including the
1134 delta
= read_memory_integer (pc
+ 1, 4, byte_order
);
1136 /* Include the size of the jmp instruction. */
1141 /* Relative jump, disp8 (ignore data16). */
1142 delta
= read_memory_integer (pc
+ data16
+ 1, 1, byte_order
);
1144 delta
+= data16
+ 2;
1151 /* Check whether PC points at a prologue for a function returning a
1152 structure or union. If so, it updates CACHE and returns the
1153 address of the first instruction after the code sequence that
1154 removes the "hidden" argument from the stack or CURRENT_PC,
1155 whichever is smaller. Otherwise, return PC. */
1158 i386_analyze_struct_return (CORE_ADDR pc
, CORE_ADDR current_pc
,
1159 struct i386_frame_cache
*cache
)
1161 /* Functions that return a structure or union start with:
1164 xchgl %eax, (%esp) 0x87 0x04 0x24
1165 or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00
1167 (the System V compiler puts out the second `xchg' instruction,
1168 and the assembler doesn't try to optimize it, so the 'sib' form
1169 gets generated). This sequence is used to get the address of the
1170 return buffer for a function that returns a structure. */
1171 static gdb_byte proto1
[3] = { 0x87, 0x04, 0x24 };
1172 static gdb_byte proto2
[4] = { 0x87, 0x44, 0x24, 0x00 };
1176 if (current_pc
<= pc
)
1179 if (target_read_code (pc
, &op
, 1))
1182 if (op
!= 0x58) /* popl %eax */
1185 if (target_read_code (pc
+ 1, buf
, 4))
1188 if (memcmp (buf
, proto1
, 3) != 0 && memcmp (buf
, proto2
, 4) != 0)
1191 if (current_pc
== pc
)
1193 cache
->sp_offset
+= 4;
1197 if (current_pc
== pc
+ 1)
1199 cache
->pc_in_eax
= 1;
1203 if (buf
[1] == proto1
[1])
1210 i386_skip_probe (CORE_ADDR pc
)
1212 /* A function may start with
1226 if (target_read_code (pc
, &op
, 1))
1229 if (op
== 0x68 || op
== 0x6a)
1233 /* Skip past the `pushl' instruction; it has either a one-byte or a
1234 four-byte operand, depending on the opcode. */
1240 /* Read the following 8 bytes, which should be `call _probe' (6
1241 bytes) followed by `addl $4,%esp' (2 bytes). */
1242 read_memory (pc
+ delta
, buf
, sizeof (buf
));
1243 if (buf
[0] == 0xe8 && buf
[6] == 0xc4 && buf
[7] == 0x4)
1244 pc
+= delta
+ sizeof (buf
);
1250 /* GCC 4.1 and later, can put code in the prologue to realign the
1251 stack pointer. Check whether PC points to such code, and update
1252 CACHE accordingly. Return the first instruction after the code
1253 sequence or CURRENT_PC, whichever is smaller. If we don't
1254 recognize the code, return PC. */
1257 i386_analyze_stack_align (CORE_ADDR pc
, CORE_ADDR current_pc
,
1258 struct i386_frame_cache
*cache
)
1260 /* There are 2 code sequences to re-align stack before the frame
1263 1. Use a caller-saved saved register:
1269 2. Use a callee-saved saved register:
1276 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
1278 0x83 0xe4 0xf0 andl $-16, %esp
1279 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
1284 int offset
, offset_and
;
1285 static int regnums
[8] = {
1286 I386_EAX_REGNUM
, /* %eax */
1287 I386_ECX_REGNUM
, /* %ecx */
1288 I386_EDX_REGNUM
, /* %edx */
1289 I386_EBX_REGNUM
, /* %ebx */
1290 I386_ESP_REGNUM
, /* %esp */
1291 I386_EBP_REGNUM
, /* %ebp */
1292 I386_ESI_REGNUM
, /* %esi */
1293 I386_EDI_REGNUM
/* %edi */
1296 if (target_read_code (pc
, buf
, sizeof buf
))
1299 /* Check caller-saved saved register. The first instruction has
1300 to be "leal 4(%esp), %reg". */
1301 if (buf
[0] == 0x8d && buf
[2] == 0x24 && buf
[3] == 0x4)
1303 /* MOD must be binary 10 and R/M must be binary 100. */
1304 if ((buf
[1] & 0xc7) != 0x44)
1307 /* REG has register number. */
1308 reg
= (buf
[1] >> 3) & 7;
1313 /* Check callee-saved saved register. The first instruction
1314 has to be "pushl %reg". */
1315 if ((buf
[0] & 0xf8) != 0x50)
1321 /* The next instruction has to be "leal 8(%esp), %reg". */
1322 if (buf
[1] != 0x8d || buf
[3] != 0x24 || buf
[4] != 0x8)
1325 /* MOD must be binary 10 and R/M must be binary 100. */
1326 if ((buf
[2] & 0xc7) != 0x44)
1329 /* REG has register number. Registers in pushl and leal have to
1331 if (reg
!= ((buf
[2] >> 3) & 7))
1337 /* Rigister can't be %esp nor %ebp. */
1338 if (reg
== 4 || reg
== 5)
1341 /* The next instruction has to be "andl $-XXX, %esp". */
1342 if (buf
[offset
+ 1] != 0xe4
1343 || (buf
[offset
] != 0x81 && buf
[offset
] != 0x83))
1346 offset_and
= offset
;
1347 offset
+= buf
[offset
] == 0x81 ? 6 : 3;
1349 /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is
1350 0xfc. REG must be binary 110 and MOD must be binary 01. */
1351 if (buf
[offset
] != 0xff
1352 || buf
[offset
+ 2] != 0xfc
1353 || (buf
[offset
+ 1] & 0xf8) != 0x70)
1356 /* R/M has register. Registers in leal and pushl have to be the
1358 if (reg
!= (buf
[offset
+ 1] & 7))
1361 if (current_pc
> pc
+ offset_and
)
1362 cache
->saved_sp_reg
= regnums
[reg
];
1364 return std::min (pc
+ offset
+ 3, current_pc
);
1367 /* Maximum instruction length we need to handle. */
1368 #define I386_MAX_MATCHED_INSN_LEN 6
1370 /* Instruction description. */
1374 gdb_byte insn
[I386_MAX_MATCHED_INSN_LEN
];
1375 gdb_byte mask
[I386_MAX_MATCHED_INSN_LEN
];
1378 /* Return whether instruction at PC matches PATTERN. */
1381 i386_match_pattern (CORE_ADDR pc
, struct i386_insn pattern
)
1385 if (target_read_code (pc
, &op
, 1))
1388 if ((op
& pattern
.mask
[0]) == pattern
.insn
[0])
1390 gdb_byte buf
[I386_MAX_MATCHED_INSN_LEN
- 1];
1391 int insn_matched
= 1;
1394 gdb_assert (pattern
.len
> 1);
1395 gdb_assert (pattern
.len
<= I386_MAX_MATCHED_INSN_LEN
);
1397 if (target_read_code (pc
+ 1, buf
, pattern
.len
- 1))
1400 for (i
= 1; i
< pattern
.len
; i
++)
1402 if ((buf
[i
- 1] & pattern
.mask
[i
]) != pattern
.insn
[i
])
1405 return insn_matched
;
1410 /* Search for the instruction at PC in the list INSN_PATTERNS. Return
1411 the first instruction description that matches. Otherwise, return
1414 static struct i386_insn
*
1415 i386_match_insn (CORE_ADDR pc
, struct i386_insn
*insn_patterns
)
1417 struct i386_insn
*pattern
;
1419 for (pattern
= insn_patterns
; pattern
->len
> 0; pattern
++)
1421 if (i386_match_pattern (pc
, *pattern
))
1428 /* Return whether PC points inside a sequence of instructions that
1429 matches INSN_PATTERNS. */
1432 i386_match_insn_block (CORE_ADDR pc
, struct i386_insn
*insn_patterns
)
1434 CORE_ADDR current_pc
;
1436 struct i386_insn
*insn
;
1438 insn
= i386_match_insn (pc
, insn_patterns
);
1443 ix
= insn
- insn_patterns
;
1444 for (i
= ix
- 1; i
>= 0; i
--)
1446 current_pc
-= insn_patterns
[i
].len
;
1448 if (!i386_match_pattern (current_pc
, insn_patterns
[i
]))
1452 current_pc
= pc
+ insn
->len
;
1453 for (insn
= insn_patterns
+ ix
+ 1; insn
->len
> 0; insn
++)
1455 if (!i386_match_pattern (current_pc
, *insn
))
1458 current_pc
+= insn
->len
;
1464 /* Some special instructions that might be migrated by GCC into the
1465 part of the prologue that sets up the new stack frame. Because the
1466 stack frame hasn't been setup yet, no registers have been saved
1467 yet, and only the scratch registers %eax, %ecx and %edx can be
1470 struct i386_insn i386_frame_setup_skip_insns
[] =
1472 /* Check for `movb imm8, r' and `movl imm32, r'.
1474 ??? Should we handle 16-bit operand-sizes here? */
1476 /* `movb imm8, %al' and `movb imm8, %ah' */
1477 /* `movb imm8, %cl' and `movb imm8, %ch' */
1478 { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } },
1479 /* `movb imm8, %dl' and `movb imm8, %dh' */
1480 { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } },
1481 /* `movl imm32, %eax' and `movl imm32, %ecx' */
1482 { 5, { 0xb8 }, { 0xfe } },
1483 /* `movl imm32, %edx' */
1484 { 5, { 0xba }, { 0xff } },
1486 /* Check for `mov imm32, r32'. Note that there is an alternative
1487 encoding for `mov m32, %eax'.
1489 ??? Should we handle SIB addressing here?
1490 ??? Should we handle 16-bit operand-sizes here? */
1492 /* `movl m32, %eax' */
1493 { 5, { 0xa1 }, { 0xff } },
1494 /* `movl m32, %eax' and `mov; m32, %ecx' */
1495 { 6, { 0x89, 0x05 }, {0xff, 0xf7 } },
1496 /* `movl m32, %edx' */
1497 { 6, { 0x89, 0x15 }, {0xff, 0xff } },
1499 /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'.
1500 Because of the symmetry, there are actually two ways to encode
1501 these instructions; opcode bytes 0x29 and 0x2b for `subl' and
1502 opcode bytes 0x31 and 0x33 for `xorl'. */
1504 /* `subl %eax, %eax' */
1505 { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } },
1506 /* `subl %ecx, %ecx' */
1507 { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } },
1508 /* `subl %edx, %edx' */
1509 { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } },
1510 /* `xorl %eax, %eax' */
1511 { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } },
1512 /* `xorl %ecx, %ecx' */
1513 { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } },
1514 /* `xorl %edx, %edx' */
1515 { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } },
1519 /* Check whether PC points to an endbr32 instruction. */
1521 i386_skip_endbr (CORE_ADDR pc
)
1523 static const gdb_byte endbr32
[] = { 0xf3, 0x0f, 0x1e, 0xfb };
1525 gdb_byte buf
[sizeof (endbr32
)];
1527 /* Stop there if we can't read the code */
1528 if (target_read_code (pc
, buf
, sizeof (endbr32
)))
1531 /* If the instruction isn't an endbr32, stop */
1532 if (memcmp (buf
, endbr32
, sizeof (endbr32
)) != 0)
1535 return pc
+ sizeof (endbr32
);
1538 /* Check whether PC points to a no-op instruction. */
1540 i386_skip_noop (CORE_ADDR pc
)
1545 if (target_read_code (pc
, &op
, 1))
1551 /* Ignore `nop' instruction. */
1555 if (target_read_code (pc
, &op
, 1))
1559 /* Ignore no-op instruction `mov %edi, %edi'.
1560 Microsoft system dlls often start with
1561 a `mov %edi,%edi' instruction.
1562 The 5 bytes before the function start are
1563 filled with `nop' instructions.
1564 This pattern can be used for hot-patching:
1565 The `mov %edi, %edi' instruction can be replaced by a
1566 near jump to the location of the 5 `nop' instructions
1567 which can be replaced by a 32-bit jump to anywhere
1568 in the 32-bit address space. */
1570 else if (op
== 0x8b)
1572 if (target_read_code (pc
+ 1, &op
, 1))
1578 if (target_read_code (pc
, &op
, 1))
1588 /* Check whether PC points at a code that sets up a new stack frame.
1589 If so, it updates CACHE and returns the address of the first
1590 instruction after the sequence that sets up the frame or LIMIT,
1591 whichever is smaller. If we don't recognize the code, return PC. */
1594 i386_analyze_frame_setup (struct gdbarch
*gdbarch
,
1595 CORE_ADDR pc
, CORE_ADDR limit
,
1596 struct i386_frame_cache
*cache
)
1598 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1599 struct i386_insn
*insn
;
1606 if (target_read_code (pc
, &op
, 1))
1609 if (op
== 0x55) /* pushl %ebp */
1611 /* Take into account that we've executed the `pushl %ebp' that
1612 starts this instruction sequence. */
1613 cache
->saved_regs
[I386_EBP_REGNUM
] = 0;
1614 cache
->sp_offset
+= 4;
1617 /* If that's all, return now. */
1621 /* Check for some special instructions that might be migrated by
1622 GCC into the prologue and skip them. At this point in the
1623 prologue, code should only touch the scratch registers %eax,
1624 %ecx and %edx, so while the number of possibilities is sheer,
1627 Make sure we only skip these instructions if we later see the
1628 `movl %esp, %ebp' that actually sets up the frame. */
1629 while (pc
+ skip
< limit
)
1631 insn
= i386_match_insn (pc
+ skip
, i386_frame_setup_skip_insns
);
1638 /* If that's all, return now. */
1639 if (limit
<= pc
+ skip
)
1642 if (target_read_code (pc
+ skip
, &op
, 1))
1645 /* The i386 prologue looks like
1651 and a different prologue can be generated for atom.
1655 lea -0x10(%esp),%esp
1657 We handle both of them here. */
1661 /* Check for `movl %esp, %ebp' -- can be written in two ways. */
1663 if (read_code_unsigned_integer (pc
+ skip
+ 1, 1, byte_order
)
1669 if (read_code_unsigned_integer (pc
+ skip
+ 1, 1, byte_order
)
1674 case 0x8d: /* Check for 'lea (%ebp), %ebp'. */
1675 if (read_code_unsigned_integer (pc
+ skip
+ 1, 2, byte_order
)
1684 /* OK, we actually have a frame. We just don't know how large
1685 it is yet. Set its size to zero. We'll adjust it if
1686 necessary. We also now commit to skipping the special
1687 instructions mentioned before. */
1690 /* If that's all, return now. */
1694 /* Check for stack adjustment
1700 NOTE: You can't subtract a 16-bit immediate from a 32-bit
1701 reg, so we don't have to worry about a data16 prefix. */
1702 if (target_read_code (pc
, &op
, 1))
1706 /* `subl' with 8-bit immediate. */
1707 if (read_code_unsigned_integer (pc
+ 1, 1, byte_order
) != 0xec)
1708 /* Some instruction starting with 0x83 other than `subl'. */
1711 /* `subl' with signed 8-bit immediate (though it wouldn't
1712 make sense to be negative). */
1713 cache
->locals
= read_code_integer (pc
+ 2, 1, byte_order
);
1716 else if (op
== 0x81)
1718 /* Maybe it is `subl' with a 32-bit immediate. */
1719 if (read_code_unsigned_integer (pc
+ 1, 1, byte_order
) != 0xec)
1720 /* Some instruction starting with 0x81 other than `subl'. */
1723 /* It is `subl' with a 32-bit immediate. */
1724 cache
->locals
= read_code_integer (pc
+ 2, 4, byte_order
);
1727 else if (op
== 0x8d)
1729 /* The ModR/M byte is 0x64. */
1730 if (read_code_unsigned_integer (pc
+ 1, 1, byte_order
) != 0x64)
1732 /* 'lea' with 8-bit displacement. */
1733 cache
->locals
= -1 * read_code_integer (pc
+ 3, 1, byte_order
);
1738 /* Some instruction other than `subl' nor 'lea'. */
1742 else if (op
== 0xc8) /* enter */
1744 cache
->locals
= read_code_unsigned_integer (pc
+ 1, 2, byte_order
);
1751 /* Check whether PC points at code that saves registers on the stack.
1752 If so, it updates CACHE and returns the address of the first
1753 instruction after the register saves or CURRENT_PC, whichever is
1754 smaller. Otherwise, return PC. */
1757 i386_analyze_register_saves (CORE_ADDR pc
, CORE_ADDR current_pc
,
1758 struct i386_frame_cache
*cache
)
1760 CORE_ADDR offset
= 0;
1764 if (cache
->locals
> 0)
1765 offset
-= cache
->locals
;
1766 for (i
= 0; i
< 8 && pc
< current_pc
; i
++)
1768 if (target_read_code (pc
, &op
, 1))
1770 if (op
< 0x50 || op
> 0x57)
1774 cache
->saved_regs
[op
- 0x50] = offset
;
1775 cache
->sp_offset
+= 4;
1782 /* Do a full analysis of the prologue at PC and update CACHE
1783 accordingly. Bail out early if CURRENT_PC is reached. Return the
1784 address where the analysis stopped.
1786 We handle these cases:
1788 The startup sequence can be at the start of the function, or the
1789 function can start with a branch to startup code at the end.
1791 %ebp can be set up with either the 'enter' instruction, or "pushl
1792 %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was
1793 once used in the System V compiler).
1795 Local space is allocated just below the saved %ebp by either the
1796 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a
1797 16-bit unsigned argument for space to allocate, and the 'addl'
1798 instruction could have either a signed byte, or 32-bit immediate.
1800 Next, the registers used by this function are pushed. With the
1801 System V compiler they will always be in the order: %edi, %esi,
1802 %ebx (and sometimes a harmless bug causes it to also save but not
1803 restore %eax); however, the code below is willing to see the pushes
1804 in any order, and will handle up to 8 of them.
1806 If the setup sequence is at the end of the function, then the next
1807 instruction will be a branch back to the start. */
1810 i386_analyze_prologue (struct gdbarch
*gdbarch
,
1811 CORE_ADDR pc
, CORE_ADDR current_pc
,
1812 struct i386_frame_cache
*cache
)
1814 pc
= i386_skip_endbr (pc
);
1815 pc
= i386_skip_noop (pc
);
1816 pc
= i386_follow_jump (gdbarch
, pc
);
1817 pc
= i386_analyze_struct_return (pc
, current_pc
, cache
);
1818 pc
= i386_skip_probe (pc
);
1819 pc
= i386_analyze_stack_align (pc
, current_pc
, cache
);
1820 pc
= i386_analyze_frame_setup (gdbarch
, pc
, current_pc
, cache
);
1821 return i386_analyze_register_saves (pc
, current_pc
, cache
);
1824 /* Return PC of first real instruction. */
1827 i386_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
1829 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1831 static gdb_byte pic_pat
[6] =
1833 0xe8, 0, 0, 0, 0, /* call 0x0 */
1834 0x5b, /* popl %ebx */
1836 struct i386_frame_cache cache
;
1840 CORE_ADDR func_addr
;
1842 if (find_pc_partial_function (start_pc
, NULL
, &func_addr
, NULL
))
1844 CORE_ADDR post_prologue_pc
1845 = skip_prologue_using_sal (gdbarch
, func_addr
);
1846 struct compunit_symtab
*cust
= find_pc_compunit_symtab (func_addr
);
1848 /* LLVM backend (Clang/Flang) always emits a line note before the
1849 prologue and another one after. We trust clang to emit usable
1851 if (post_prologue_pc
1853 && COMPUNIT_PRODUCER (cust
) != NULL
1854 && producer_is_llvm (COMPUNIT_PRODUCER (cust
))))
1855 return std::max (start_pc
, post_prologue_pc
);
1859 pc
= i386_analyze_prologue (gdbarch
, start_pc
, 0xffffffff, &cache
);
1860 if (cache
.locals
< 0)
1863 /* Found valid frame setup. */
1865 /* The native cc on SVR4 in -K PIC mode inserts the following code
1866 to get the address of the global offset table (GOT) into register
1871 movl %ebx,x(%ebp) (optional)
1874 This code is with the rest of the prologue (at the end of the
1875 function), so we have to skip it to get to the first real
1876 instruction at the start of the function. */
1878 for (i
= 0; i
< 6; i
++)
1880 if (target_read_code (pc
+ i
, &op
, 1))
1883 if (pic_pat
[i
] != op
)
1890 if (target_read_code (pc
+ delta
, &op
, 1))
1893 if (op
== 0x89) /* movl %ebx, x(%ebp) */
1895 op
= read_code_unsigned_integer (pc
+ delta
+ 1, 1, byte_order
);
1897 if (op
== 0x5d) /* One byte offset from %ebp. */
1899 else if (op
== 0x9d) /* Four byte offset from %ebp. */
1901 else /* Unexpected instruction. */
1904 if (target_read_code (pc
+ delta
, &op
, 1))
1909 if (delta
> 0 && op
== 0x81
1910 && read_code_unsigned_integer (pc
+ delta
+ 1, 1, byte_order
)
1917 /* If the function starts with a branch (to startup code at the end)
1918 the last instruction should bring us back to the first
1919 instruction of the real code. */
1920 if (i386_follow_jump (gdbarch
, start_pc
) != start_pc
)
1921 pc
= i386_follow_jump (gdbarch
, pc
);
1926 /* Check that the code pointed to by PC corresponds to a call to
1927 __main, skip it if so. Return PC otherwise. */
1930 i386_skip_main_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1932 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1935 if (target_read_code (pc
, &op
, 1))
1941 if (target_read_code (pc
+ 1, buf
, sizeof buf
) == 0)
1943 /* Make sure address is computed correctly as a 32bit
1944 integer even if CORE_ADDR is 64 bit wide. */
1945 struct bound_minimal_symbol s
;
1946 CORE_ADDR call_dest
;
1948 call_dest
= pc
+ 5 + extract_signed_integer (buf
, 4, byte_order
);
1949 call_dest
= call_dest
& 0xffffffffU
;
1950 s
= lookup_minimal_symbol_by_pc (call_dest
);
1951 if (s
.minsym
!= NULL
1952 && s
.minsym
->linkage_name () != NULL
1953 && strcmp (s
.minsym
->linkage_name (), "__main") == 0)
1961 /* This function is 64-bit safe. */
1964 i386_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1968 frame_unwind_register (next_frame
, gdbarch_pc_regnum (gdbarch
), buf
);
1969 return extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
1973 /* Normal frames. */
1976 i386_frame_cache_1 (struct frame_info
*this_frame
,
1977 struct i386_frame_cache
*cache
)
1979 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1980 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1984 cache
->pc
= get_frame_func (this_frame
);
1986 /* In principle, for normal frames, %ebp holds the frame pointer,
1987 which holds the base address for the current stack frame.
1988 However, for functions that don't need it, the frame pointer is
1989 optional. For these "frameless" functions the frame pointer is
1990 actually the frame pointer of the calling frame. Signal
1991 trampolines are just a special case of a "frameless" function.
1992 They (usually) share their frame pointer with the frame that was
1993 in progress when the signal occurred. */
1995 get_frame_register (this_frame
, I386_EBP_REGNUM
, buf
);
1996 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
);
1997 if (cache
->base
== 0)
2003 /* For normal frames, %eip is stored at 4(%ebp). */
2004 cache
->saved_regs
[I386_EIP_REGNUM
] = 4;
2007 i386_analyze_prologue (gdbarch
, cache
->pc
, get_frame_pc (this_frame
),
2010 if (cache
->locals
< 0)
2012 /* We didn't find a valid frame, which means that CACHE->base
2013 currently holds the frame pointer for our calling frame. If
2014 we're at the start of a function, or somewhere half-way its
2015 prologue, the function's frame probably hasn't been fully
2016 setup yet. Try to reconstruct the base address for the stack
2017 frame by looking at the stack pointer. For truly "frameless"
2018 functions this might work too. */
2020 if (cache
->saved_sp_reg
!= -1)
2022 /* Saved stack pointer has been saved. */
2023 get_frame_register (this_frame
, cache
->saved_sp_reg
, buf
);
2024 cache
->saved_sp
= extract_unsigned_integer (buf
, 4, byte_order
);
2026 /* We're halfway aligning the stack. */
2027 cache
->base
= ((cache
->saved_sp
- 4) & 0xfffffff0) - 4;
2028 cache
->saved_regs
[I386_EIP_REGNUM
] = cache
->saved_sp
- 4;
2030 /* This will be added back below. */
2031 cache
->saved_regs
[I386_EIP_REGNUM
] -= cache
->base
;
2033 else if (cache
->pc
!= 0
2034 || target_read_code (get_frame_pc (this_frame
), buf
, 1))
2036 /* We're in a known function, but did not find a frame
2037 setup. Assume that the function does not use %ebp.
2038 Alternatively, we may have jumped to an invalid
2039 address; in that case there is definitely no new
2041 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
2042 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
)
2046 /* We're in an unknown function. We could not find the start
2047 of the function to analyze the prologue; our best option is
2048 to assume a typical frame layout with the caller's %ebp
2050 cache
->saved_regs
[I386_EBP_REGNUM
] = 0;
2053 if (cache
->saved_sp_reg
!= -1)
2055 /* Saved stack pointer has been saved (but the SAVED_SP_REG
2056 register may be unavailable). */
2057 if (cache
->saved_sp
== 0
2058 && deprecated_frame_register_read (this_frame
,
2059 cache
->saved_sp_reg
, buf
))
2060 cache
->saved_sp
= extract_unsigned_integer (buf
, 4, byte_order
);
2062 /* Now that we have the base address for the stack frame we can
2063 calculate the value of %esp in the calling frame. */
2064 else if (cache
->saved_sp
== 0)
2065 cache
->saved_sp
= cache
->base
+ 8;
2067 /* Adjust all the saved registers such that they contain addresses
2068 instead of offsets. */
2069 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
2070 if (cache
->saved_regs
[i
] != -1)
2071 cache
->saved_regs
[i
] += cache
->base
;
2076 static struct i386_frame_cache
*
2077 i386_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2079 struct i386_frame_cache
*cache
;
2082 return (struct i386_frame_cache
*) *this_cache
;
2084 cache
= i386_alloc_frame_cache ();
2085 *this_cache
= cache
;
2089 i386_frame_cache_1 (this_frame
, cache
);
2091 catch (const gdb_exception_error
&ex
)
2093 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
2101 i386_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2102 struct frame_id
*this_id
)
2104 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
2107 (*this_id
) = frame_id_build_unavailable_stack (cache
->pc
);
2108 else if (cache
->base
== 0)
2110 /* This marks the outermost frame. */
2114 /* See the end of i386_push_dummy_call. */
2115 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
2119 static enum unwind_stop_reason
2120 i386_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2123 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
2126 return UNWIND_UNAVAILABLE
;
2128 /* This marks the outermost frame. */
2129 if (cache
->base
== 0)
2130 return UNWIND_OUTERMOST
;
2132 return UNWIND_NO_REASON
;
2135 static struct value
*
2136 i386_frame_prev_register (struct frame_info
*this_frame
, void **this_cache
,
2139 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
2141 gdb_assert (regnum
>= 0);
2143 /* The System V ABI says that:
2145 "The flags register contains the system flags, such as the
2146 direction flag and the carry flag. The direction flag must be
2147 set to the forward (that is, zero) direction before entry and
2148 upon exit from a function. Other user flags have no specified
2149 role in the standard calling sequence and are not preserved."
2151 To guarantee the "upon exit" part of that statement we fake a
2152 saved flags register that has its direction flag cleared.
2154 Note that GCC doesn't seem to rely on the fact that the direction
2155 flag is cleared after a function return; it always explicitly
2156 clears the flag before operations where it matters.
2158 FIXME: kettenis/20030316: I'm not quite sure whether this is the
2159 right thing to do. The way we fake the flags register here makes
2160 it impossible to change it. */
2162 if (regnum
== I386_EFLAGS_REGNUM
)
2166 val
= get_frame_register_unsigned (this_frame
, regnum
);
2168 return frame_unwind_got_constant (this_frame
, regnum
, val
);
2171 if (regnum
== I386_EIP_REGNUM
&& cache
->pc_in_eax
)
2172 return frame_unwind_got_register (this_frame
, regnum
, I386_EAX_REGNUM
);
2174 if (regnum
== I386_ESP_REGNUM
2175 && (cache
->saved_sp
!= 0 || cache
->saved_sp_reg
!= -1))
2177 /* If the SP has been saved, but we don't know where, then this
2178 means that SAVED_SP_REG register was found unavailable back
2179 when we built the cache. */
2180 if (cache
->saved_sp
== 0)
2181 return frame_unwind_got_register (this_frame
, regnum
,
2182 cache
->saved_sp_reg
);
2184 return frame_unwind_got_constant (this_frame
, regnum
,
2188 if (regnum
< I386_NUM_SAVED_REGS
&& cache
->saved_regs
[regnum
] != -1)
2189 return frame_unwind_got_memory (this_frame
, regnum
,
2190 cache
->saved_regs
[regnum
]);
2192 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
2195 static const struct frame_unwind i386_frame_unwind
=
2198 i386_frame_unwind_stop_reason
,
2200 i386_frame_prev_register
,
2202 default_frame_sniffer
2205 /* Normal frames, but in a function epilogue. */
2207 /* Implement the stack_frame_destroyed_p gdbarch method.
2209 The epilogue is defined here as the 'ret' instruction, which will
2210 follow any instruction such as 'leave' or 'pop %ebp' that destroys
2211 the function's stack frame. */
2214 i386_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2217 struct compunit_symtab
*cust
;
2219 cust
= find_pc_compunit_symtab (pc
);
2220 if (cust
!= NULL
&& COMPUNIT_EPILOGUE_UNWIND_VALID (cust
))
2223 if (target_read_memory (pc
, &insn
, 1))
2224 return 0; /* Can't read memory at pc. */
2226 if (insn
!= 0xc3) /* 'ret' instruction. */
2233 i386_epilogue_frame_sniffer (const struct frame_unwind
*self
,
2234 struct frame_info
*this_frame
,
2235 void **this_prologue_cache
)
2237 if (frame_relative_level (this_frame
) == 0)
2238 return i386_stack_frame_destroyed_p (get_frame_arch (this_frame
),
2239 get_frame_pc (this_frame
));
2244 static struct i386_frame_cache
*
2245 i386_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2247 struct i386_frame_cache
*cache
;
2251 return (struct i386_frame_cache
*) *this_cache
;
2253 cache
= i386_alloc_frame_cache ();
2254 *this_cache
= cache
;
2258 cache
->pc
= get_frame_func (this_frame
);
2260 /* At this point the stack looks as if we just entered the
2261 function, with the return address at the top of the
2263 sp
= get_frame_register_unsigned (this_frame
, I386_ESP_REGNUM
);
2264 cache
->base
= sp
+ cache
->sp_offset
;
2265 cache
->saved_sp
= cache
->base
+ 8;
2266 cache
->saved_regs
[I386_EIP_REGNUM
] = cache
->base
+ 4;
2270 catch (const gdb_exception_error
&ex
)
2272 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
2279 static enum unwind_stop_reason
2280 i386_epilogue_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2283 struct i386_frame_cache
*cache
=
2284 i386_epilogue_frame_cache (this_frame
, this_cache
);
2287 return UNWIND_UNAVAILABLE
;
2289 return UNWIND_NO_REASON
;
2293 i386_epilogue_frame_this_id (struct frame_info
*this_frame
,
2295 struct frame_id
*this_id
)
2297 struct i386_frame_cache
*cache
=
2298 i386_epilogue_frame_cache (this_frame
, this_cache
);
2301 (*this_id
) = frame_id_build_unavailable_stack (cache
->pc
);
2303 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
2306 static struct value
*
2307 i386_epilogue_frame_prev_register (struct frame_info
*this_frame
,
2308 void **this_cache
, int regnum
)
2310 /* Make sure we've initialized the cache. */
2311 i386_epilogue_frame_cache (this_frame
, this_cache
);
2313 return i386_frame_prev_register (this_frame
, this_cache
, regnum
);
2316 static const struct frame_unwind i386_epilogue_frame_unwind
=
2319 i386_epilogue_frame_unwind_stop_reason
,
2320 i386_epilogue_frame_this_id
,
2321 i386_epilogue_frame_prev_register
,
2323 i386_epilogue_frame_sniffer
2327 /* Stack-based trampolines. */
2329 /* These trampolines are used on cross x86 targets, when taking the
2330 address of a nested function. When executing these trampolines,
2331 no stack frame is set up, so we are in a similar situation as in
2332 epilogues and i386_epilogue_frame_this_id can be re-used. */
2334 /* Static chain passed in register. */
2336 struct i386_insn i386_tramp_chain_in_reg_insns
[] =
2338 /* `movl imm32, %eax' and `movl imm32, %ecx' */
2339 { 5, { 0xb8 }, { 0xfe } },
2342 { 5, { 0xe9 }, { 0xff } },
2347 /* Static chain passed on stack (when regparm=3). */
2349 struct i386_insn i386_tramp_chain_on_stack_insns
[] =
2352 { 5, { 0x68 }, { 0xff } },
2355 { 5, { 0xe9 }, { 0xff } },
2360 /* Return whether PC points inside a stack trampoline. */
2363 i386_in_stack_tramp_p (CORE_ADDR pc
)
2368 /* A stack trampoline is detected if no name is associated
2369 to the current pc and if it points inside a trampoline
2372 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
2376 if (target_read_memory (pc
, &insn
, 1))
2379 if (!i386_match_insn_block (pc
, i386_tramp_chain_in_reg_insns
)
2380 && !i386_match_insn_block (pc
, i386_tramp_chain_on_stack_insns
))
2387 i386_stack_tramp_frame_sniffer (const struct frame_unwind
*self
,
2388 struct frame_info
*this_frame
,
2391 if (frame_relative_level (this_frame
) == 0)
2392 return i386_in_stack_tramp_p (get_frame_pc (this_frame
));
2397 static const struct frame_unwind i386_stack_tramp_frame_unwind
=
2400 i386_epilogue_frame_unwind_stop_reason
,
2401 i386_epilogue_frame_this_id
,
2402 i386_epilogue_frame_prev_register
,
2404 i386_stack_tramp_frame_sniffer
2407 /* Generate a bytecode expression to get the value of the saved PC. */
2410 i386_gen_return_address (struct gdbarch
*gdbarch
,
2411 struct agent_expr
*ax
, struct axs_value
*value
,
2414 /* The following sequence assumes the traditional use of the base
2416 ax_reg (ax
, I386_EBP_REGNUM
);
2418 ax_simple (ax
, aop_add
);
2419 value
->type
= register_type (gdbarch
, I386_EIP_REGNUM
);
2420 value
->kind
= axs_lvalue_memory
;
2424 /* Signal trampolines. */
2426 static struct i386_frame_cache
*
2427 i386_sigtramp_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2429 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2430 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2431 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2432 struct i386_frame_cache
*cache
;
2437 return (struct i386_frame_cache
*) *this_cache
;
2439 cache
= i386_alloc_frame_cache ();
2443 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
2444 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
) - 4;
2446 addr
= tdep
->sigcontext_addr (this_frame
);
2447 if (tdep
->sc_reg_offset
)
2451 gdb_assert (tdep
->sc_num_regs
<= I386_NUM_SAVED_REGS
);
2453 for (i
= 0; i
< tdep
->sc_num_regs
; i
++)
2454 if (tdep
->sc_reg_offset
[i
] != -1)
2455 cache
->saved_regs
[i
] = addr
+ tdep
->sc_reg_offset
[i
];
2459 cache
->saved_regs
[I386_EIP_REGNUM
] = addr
+ tdep
->sc_pc_offset
;
2460 cache
->saved_regs
[I386_ESP_REGNUM
] = addr
+ tdep
->sc_sp_offset
;
2465 catch (const gdb_exception_error
&ex
)
2467 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
2471 *this_cache
= cache
;
2475 static enum unwind_stop_reason
2476 i386_sigtramp_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2479 struct i386_frame_cache
*cache
=
2480 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2483 return UNWIND_UNAVAILABLE
;
2485 return UNWIND_NO_REASON
;
2489 i386_sigtramp_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2490 struct frame_id
*this_id
)
2492 struct i386_frame_cache
*cache
=
2493 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2496 (*this_id
) = frame_id_build_unavailable_stack (get_frame_pc (this_frame
));
2499 /* See the end of i386_push_dummy_call. */
2500 (*this_id
) = frame_id_build (cache
->base
+ 8, get_frame_pc (this_frame
));
2504 static struct value
*
2505 i386_sigtramp_frame_prev_register (struct frame_info
*this_frame
,
2506 void **this_cache
, int regnum
)
2508 /* Make sure we've initialized the cache. */
2509 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2511 return i386_frame_prev_register (this_frame
, this_cache
, regnum
);
2515 i386_sigtramp_frame_sniffer (const struct frame_unwind
*self
,
2516 struct frame_info
*this_frame
,
2517 void **this_prologue_cache
)
2519 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (this_frame
));
2521 /* We shouldn't even bother if we don't have a sigcontext_addr
2523 if (tdep
->sigcontext_addr
== NULL
)
2526 if (tdep
->sigtramp_p
!= NULL
)
2528 if (tdep
->sigtramp_p (this_frame
))
2532 if (tdep
->sigtramp_start
!= 0)
2534 CORE_ADDR pc
= get_frame_pc (this_frame
);
2536 gdb_assert (tdep
->sigtramp_end
!= 0);
2537 if (pc
>= tdep
->sigtramp_start
&& pc
< tdep
->sigtramp_end
)
2544 static const struct frame_unwind i386_sigtramp_frame_unwind
=
2547 i386_sigtramp_frame_unwind_stop_reason
,
2548 i386_sigtramp_frame_this_id
,
2549 i386_sigtramp_frame_prev_register
,
2551 i386_sigtramp_frame_sniffer
2556 i386_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
2558 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
2563 static const struct frame_base i386_frame_base
=
2566 i386_frame_base_address
,
2567 i386_frame_base_address
,
2568 i386_frame_base_address
2571 static struct frame_id
2572 i386_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
2576 fp
= get_frame_register_unsigned (this_frame
, I386_EBP_REGNUM
);
2578 /* See the end of i386_push_dummy_call. */
2579 return frame_id_build (fp
+ 8, get_frame_pc (this_frame
));
2582 /* _Decimal128 function return values need 16-byte alignment on the
2586 i386_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
2588 return sp
& -(CORE_ADDR
)16;
2592 /* Figure out where the longjmp will land. Slurp the args out of the
2593 stack. We expect the first arg to be a pointer to the jmp_buf
2594 structure from which we extract the address that we will land at.
2595 This address is copied into PC. This routine returns non-zero on
2599 i386_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
2602 CORE_ADDR sp
, jb_addr
;
2603 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2604 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2605 int jb_pc_offset
= gdbarch_tdep (gdbarch
)->jb_pc_offset
;
2607 /* If JB_PC_OFFSET is -1, we have no way to find out where the
2608 longjmp will land. */
2609 if (jb_pc_offset
== -1)
2612 get_frame_register (frame
, I386_ESP_REGNUM
, buf
);
2613 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
2614 if (target_read_memory (sp
+ 4, buf
, 4))
2617 jb_addr
= extract_unsigned_integer (buf
, 4, byte_order
);
2618 if (target_read_memory (jb_addr
+ jb_pc_offset
, buf
, 4))
2621 *pc
= extract_unsigned_integer (buf
, 4, byte_order
);
2626 /* Check whether TYPE must be 16-byte-aligned when passed as a
2627 function argument. 16-byte vectors, _Decimal128 and structures or
2628 unions containing such types must be 16-byte-aligned; other
2629 arguments are 4-byte-aligned. */
2632 i386_16_byte_align_p (struct type
*type
)
2634 type
= check_typedef (type
);
2635 if ((type
->code () == TYPE_CODE_DECFLOAT
2636 || (type
->code () == TYPE_CODE_ARRAY
&& type
->is_vector ()))
2637 && TYPE_LENGTH (type
) == 16)
2639 if (type
->code () == TYPE_CODE_ARRAY
)
2640 return i386_16_byte_align_p (TYPE_TARGET_TYPE (type
));
2641 if (type
->code () == TYPE_CODE_STRUCT
2642 || type
->code () == TYPE_CODE_UNION
)
2645 for (i
= 0; i
< type
->num_fields (); i
++)
2647 if (field_is_static (&type
->field (i
)))
2649 if (i386_16_byte_align_p (type
->field (i
).type ()))
2656 /* Implementation for set_gdbarch_push_dummy_code. */
2659 i386_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
, CORE_ADDR funaddr
,
2660 struct value
**args
, int nargs
, struct type
*value_type
,
2661 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
,
2662 struct regcache
*regcache
)
2664 /* Use 0xcc breakpoint - 1 byte. */
2668 /* Keep the stack aligned. */
2672 /* The "push_dummy_call" gdbarch method, optionally with the thiscall
2673 calling convention. */
2676 i386_thiscall_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2677 struct regcache
*regcache
, CORE_ADDR bp_addr
,
2678 int nargs
, struct value
**args
, CORE_ADDR sp
,
2679 function_call_return_method return_method
,
2680 CORE_ADDR struct_addr
, bool thiscall
)
2682 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2688 /* BND registers can be in arbitrary values at the moment of the
2689 inferior call. This can cause boundary violations that are not
2690 due to a real bug or even desired by the user. The best to be done
2691 is set the BND registers to allow access to the whole memory, INIT
2692 state, before pushing the inferior call. */
2693 i387_reset_bnd_regs (gdbarch
, regcache
);
2695 /* Determine the total space required for arguments and struct
2696 return address in a first pass (allowing for 16-byte-aligned
2697 arguments), then push arguments in a second pass. */
2699 for (write_pass
= 0; write_pass
< 2; write_pass
++)
2701 int args_space_used
= 0;
2703 if (return_method
== return_method_struct
)
2707 /* Push value address. */
2708 store_unsigned_integer (buf
, 4, byte_order
, struct_addr
);
2709 write_memory (sp
, buf
, 4);
2710 args_space_used
+= 4;
2716 for (i
= thiscall
? 1 : 0; i
< nargs
; i
++)
2718 int len
= TYPE_LENGTH (value_enclosing_type (args
[i
]));
2722 if (i386_16_byte_align_p (value_enclosing_type (args
[i
])))
2723 args_space_used
= align_up (args_space_used
, 16);
2725 write_memory (sp
+ args_space_used
,
2726 value_contents_all (args
[i
]), len
);
2727 /* The System V ABI says that:
2729 "An argument's size is increased, if necessary, to make it a
2730 multiple of [32-bit] words. This may require tail padding,
2731 depending on the size of the argument."
2733 This makes sure the stack stays word-aligned. */
2734 args_space_used
+= align_up (len
, 4);
2738 if (i386_16_byte_align_p (value_enclosing_type (args
[i
])))
2739 args_space
= align_up (args_space
, 16);
2740 args_space
+= align_up (len
, 4);
2748 /* The original System V ABI only requires word alignment,
2749 but modern incarnations need 16-byte alignment in order
2750 to support SSE. Since wasting a few bytes here isn't
2751 harmful we unconditionally enforce 16-byte alignment. */
2756 /* Store return address. */
2758 store_unsigned_integer (buf
, 4, byte_order
, bp_addr
);
2759 write_memory (sp
, buf
, 4);
2761 /* Finally, update the stack pointer... */
2762 store_unsigned_integer (buf
, 4, byte_order
, sp
);
2763 regcache
->cooked_write (I386_ESP_REGNUM
, buf
);
2765 /* ...and fake a frame pointer. */
2766 regcache
->cooked_write (I386_EBP_REGNUM
, buf
);
2768 /* The 'this' pointer needs to be in ECX. */
2770 regcache
->cooked_write (I386_ECX_REGNUM
, value_contents_all (args
[0]));
2772 /* MarkK wrote: This "+ 8" is all over the place:
2773 (i386_frame_this_id, i386_sigtramp_frame_this_id,
2774 i386_dummy_id). It's there, since all frame unwinders for
2775 a given target have to agree (within a certain margin) on the
2776 definition of the stack address of a frame. Otherwise frame id
2777 comparison might not work correctly. Since DWARF2/GCC uses the
2778 stack address *before* the function call as a frame's CFA. On
2779 the i386, when %ebp is used as a frame pointer, the offset
2780 between the contents %ebp and the CFA as defined by GCC. */
2784 /* Implement the "push_dummy_call" gdbarch method. */
2787 i386_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2788 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
2789 struct value
**args
, CORE_ADDR sp
,
2790 function_call_return_method return_method
,
2791 CORE_ADDR struct_addr
)
2793 return i386_thiscall_push_dummy_call (gdbarch
, function
, regcache
, bp_addr
,
2794 nargs
, args
, sp
, return_method
,
2795 struct_addr
, false);
2798 /* These registers are used for returning integers (and on some
2799 targets also for returning `struct' and `union' values when their
2800 size and alignment match an integer type). */
2801 #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */
2802 #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */
2804 /* Read, for architecture GDBARCH, a function return value of TYPE
2805 from REGCACHE, and copy that into VALBUF. */
2808 i386_extract_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
2809 struct regcache
*regcache
, gdb_byte
*valbuf
)
2811 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2812 int len
= TYPE_LENGTH (type
);
2813 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
2815 if (type
->code () == TYPE_CODE_FLT
)
2817 if (tdep
->st0_regnum
< 0)
2819 warning (_("Cannot find floating-point return value."));
2820 memset (valbuf
, 0, len
);
2824 /* Floating-point return values can be found in %st(0). Convert
2825 its contents to the desired type. This is probably not
2826 exactly how it would happen on the target itself, but it is
2827 the best we can do. */
2828 regcache
->raw_read (I386_ST0_REGNUM
, buf
);
2829 target_float_convert (buf
, i387_ext_type (gdbarch
), valbuf
, type
);
2833 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
2834 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
2836 if (len
<= low_size
)
2838 regcache
->raw_read (LOW_RETURN_REGNUM
, buf
);
2839 memcpy (valbuf
, buf
, len
);
2841 else if (len
<= (low_size
+ high_size
))
2843 regcache
->raw_read (LOW_RETURN_REGNUM
, buf
);
2844 memcpy (valbuf
, buf
, low_size
);
2845 regcache
->raw_read (HIGH_RETURN_REGNUM
, buf
);
2846 memcpy (valbuf
+ low_size
, buf
, len
- low_size
);
2849 internal_error (__FILE__
, __LINE__
,
2850 _("Cannot extract return value of %d bytes long."),
2855 /* Write, for architecture GDBARCH, a function return value of TYPE
2856 from VALBUF into REGCACHE. */
2859 i386_store_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
2860 struct regcache
*regcache
, const gdb_byte
*valbuf
)
2862 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2863 int len
= TYPE_LENGTH (type
);
2865 if (type
->code () == TYPE_CODE_FLT
)
2868 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
2870 if (tdep
->st0_regnum
< 0)
2872 warning (_("Cannot set floating-point return value."));
2876 /* Returning floating-point values is a bit tricky. Apart from
2877 storing the return value in %st(0), we have to simulate the
2878 state of the FPU at function return point. */
2880 /* Convert the value found in VALBUF to the extended
2881 floating-point format used by the FPU. This is probably
2882 not exactly how it would happen on the target itself, but
2883 it is the best we can do. */
2884 target_float_convert (valbuf
, type
, buf
, i387_ext_type (gdbarch
));
2885 regcache
->raw_write (I386_ST0_REGNUM
, buf
);
2887 /* Set the top of the floating-point register stack to 7. The
2888 actual value doesn't really matter, but 7 is what a normal
2889 function return would end up with if the program started out
2890 with a freshly initialized FPU. */
2891 regcache_raw_read_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), &fstat
);
2893 regcache_raw_write_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), fstat
);
2895 /* Mark %st(1) through %st(7) as empty. Since we set the top of
2896 the floating-point register stack to 7, the appropriate value
2897 for the tag word is 0x3fff. */
2898 regcache_raw_write_unsigned (regcache
, I387_FTAG_REGNUM (tdep
), 0x3fff);
2902 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
2903 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
2905 if (len
<= low_size
)
2906 regcache
->raw_write_part (LOW_RETURN_REGNUM
, 0, len
, valbuf
);
2907 else if (len
<= (low_size
+ high_size
))
2909 regcache
->raw_write (LOW_RETURN_REGNUM
, valbuf
);
2910 regcache
->raw_write_part (HIGH_RETURN_REGNUM
, 0, len
- low_size
,
2914 internal_error (__FILE__
, __LINE__
,
2915 _("Cannot store return value of %d bytes long."), len
);
2920 /* This is the variable that is set with "set struct-convention", and
2921 its legitimate values. */
2922 static const char default_struct_convention
[] = "default";
2923 static const char pcc_struct_convention
[] = "pcc";
2924 static const char reg_struct_convention
[] = "reg";
2925 static const char *const valid_conventions
[] =
2927 default_struct_convention
,
2928 pcc_struct_convention
,
2929 reg_struct_convention
,
2932 static const char *struct_convention
= default_struct_convention
;
2934 /* Return non-zero if TYPE, which is assumed to be a structure,
2935 a union type, or an array type, should be returned in registers
2936 for architecture GDBARCH. */
2939 i386_reg_struct_return_p (struct gdbarch
*gdbarch
, struct type
*type
)
2941 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2942 enum type_code code
= type
->code ();
2943 int len
= TYPE_LENGTH (type
);
2945 gdb_assert (code
== TYPE_CODE_STRUCT
2946 || code
== TYPE_CODE_UNION
2947 || code
== TYPE_CODE_ARRAY
);
2949 if (struct_convention
== pcc_struct_convention
2950 || (struct_convention
== default_struct_convention
2951 && tdep
->struct_return
== pcc_struct_return
))
2954 /* Structures consisting of a single `float', `double' or 'long
2955 double' member are returned in %st(0). */
2956 if (code
== TYPE_CODE_STRUCT
&& type
->num_fields () == 1)
2958 type
= check_typedef (type
->field (0).type ());
2959 if (type
->code () == TYPE_CODE_FLT
)
2960 return (len
== 4 || len
== 8 || len
== 12);
2963 return (len
== 1 || len
== 2 || len
== 4 || len
== 8);
2966 /* Determine, for architecture GDBARCH, how a return value of TYPE
2967 should be returned. If it is supposed to be returned in registers,
2968 and READBUF is non-zero, read the appropriate value from REGCACHE,
2969 and copy it into READBUF. If WRITEBUF is non-zero, write the value
2970 from WRITEBUF into REGCACHE. */
2972 static enum return_value_convention
2973 i386_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
2974 struct type
*type
, struct regcache
*regcache
,
2975 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2977 enum type_code code
= type
->code ();
2979 if (((code
== TYPE_CODE_STRUCT
2980 || code
== TYPE_CODE_UNION
2981 || code
== TYPE_CODE_ARRAY
)
2982 && !i386_reg_struct_return_p (gdbarch
, type
))
2983 /* Complex double and long double uses the struct return convention. */
2984 || (code
== TYPE_CODE_COMPLEX
&& TYPE_LENGTH (type
) == 16)
2985 || (code
== TYPE_CODE_COMPLEX
&& TYPE_LENGTH (type
) == 24)
2986 /* 128-bit decimal float uses the struct return convention. */
2987 || (code
== TYPE_CODE_DECFLOAT
&& TYPE_LENGTH (type
) == 16))
2989 /* The System V ABI says that:
2991 "A function that returns a structure or union also sets %eax
2992 to the value of the original address of the caller's area
2993 before it returns. Thus when the caller receives control
2994 again, the address of the returned object resides in register
2995 %eax and can be used to access the object."
2997 So the ABI guarantees that we can always find the return
2998 value just after the function has returned. */
3000 /* Note that the ABI doesn't mention functions returning arrays,
3001 which is something possible in certain languages such as Ada.
3002 In this case, the value is returned as if it was wrapped in
3003 a record, so the convention applied to records also applies
3010 regcache_raw_read_unsigned (regcache
, I386_EAX_REGNUM
, &addr
);
3011 read_memory (addr
, readbuf
, TYPE_LENGTH (type
));
3014 return RETURN_VALUE_ABI_RETURNS_ADDRESS
;
3017 /* This special case is for structures consisting of a single
3018 `float', `double' or 'long double' member. These structures are
3019 returned in %st(0). For these structures, we call ourselves
3020 recursively, changing TYPE into the type of the first member of
3021 the structure. Since that should work for all structures that
3022 have only one member, we don't bother to check the member's type
3024 if (code
== TYPE_CODE_STRUCT
&& type
->num_fields () == 1)
3026 type
= check_typedef (type
->field (0).type ());
3027 return i386_return_value (gdbarch
, function
, type
, regcache
,
3032 i386_extract_return_value (gdbarch
, type
, regcache
, readbuf
);
3034 i386_store_return_value (gdbarch
, type
, regcache
, writebuf
);
3036 return RETURN_VALUE_REGISTER_CONVENTION
;
3041 i387_ext_type (struct gdbarch
*gdbarch
)
3043 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3045 if (!tdep
->i387_ext_type
)
3047 tdep
->i387_ext_type
= tdesc_find_type (gdbarch
, "i387_ext");
3048 gdb_assert (tdep
->i387_ext_type
!= NULL
);
3051 return tdep
->i387_ext_type
;
3054 /* Construct type for pseudo BND registers. We can't use
3055 tdesc_find_type since a complement of one value has to be used
3056 to describe the upper bound. */
3058 static struct type
*
3059 i386_bnd_type (struct gdbarch
*gdbarch
)
3061 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3064 if (!tdep
->i386_bnd_type
)
3067 const struct builtin_type
*bt
= builtin_type (gdbarch
);
3069 /* The type we're building is described bellow: */
3074 void *ubound
; /* One complement of raw ubound field. */
3078 t
= arch_composite_type (gdbarch
,
3079 "__gdb_builtin_type_bound128", TYPE_CODE_STRUCT
);
3081 append_composite_type_field (t
, "lbound", bt
->builtin_data_ptr
);
3082 append_composite_type_field (t
, "ubound", bt
->builtin_data_ptr
);
3084 t
->set_name ("builtin_type_bound128");
3085 tdep
->i386_bnd_type
= t
;
3088 return tdep
->i386_bnd_type
;
3091 /* Construct vector type for pseudo ZMM registers. We can't use
3092 tdesc_find_type since ZMM isn't described in target description. */
3094 static struct type
*
3095 i386_zmm_type (struct gdbarch
*gdbarch
)
3097 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3099 if (!tdep
->i386_zmm_type
)
3101 const struct builtin_type
*bt
= builtin_type (gdbarch
);
3103 /* The type we're building is this: */
3105 union __gdb_builtin_type_vec512i
3107 int128_t v4_int128
[4];
3108 int64_t v8_int64
[8];
3109 int32_t v16_int32
[16];
3110 int16_t v32_int16
[32];
3111 int8_t v64_int8
[64];
3112 double v8_double
[8];
3113 float v16_float
[16];
3114 bfloat16_t v32_bfloat16
[32];
3120 t
= arch_composite_type (gdbarch
,
3121 "__gdb_builtin_type_vec512i", TYPE_CODE_UNION
);
3122 append_composite_type_field (t
, "v32_bfloat16",
3123 init_vector_type (bt
->builtin_bfloat16
, 32));
3124 append_composite_type_field (t
, "v16_float",
3125 init_vector_type (bt
->builtin_float
, 16));
3126 append_composite_type_field (t
, "v8_double",
3127 init_vector_type (bt
->builtin_double
, 8));
3128 append_composite_type_field (t
, "v64_int8",
3129 init_vector_type (bt
->builtin_int8
, 64));
3130 append_composite_type_field (t
, "v32_int16",
3131 init_vector_type (bt
->builtin_int16
, 32));
3132 append_composite_type_field (t
, "v16_int32",
3133 init_vector_type (bt
->builtin_int32
, 16));
3134 append_composite_type_field (t
, "v8_int64",
3135 init_vector_type (bt
->builtin_int64
, 8));
3136 append_composite_type_field (t
, "v4_int128",
3137 init_vector_type (bt
->builtin_int128
, 4));
3139 t
->set_is_vector (true);
3140 t
->set_name ("builtin_type_vec512i");
3141 tdep
->i386_zmm_type
= t
;
3144 return tdep
->i386_zmm_type
;
3147 /* Construct vector type for pseudo YMM registers. We can't use
3148 tdesc_find_type since YMM isn't described in target description. */
3150 static struct type
*
3151 i386_ymm_type (struct gdbarch
*gdbarch
)
3153 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3155 if (!tdep
->i386_ymm_type
)
3157 const struct builtin_type
*bt
= builtin_type (gdbarch
);
3159 /* The type we're building is this: */
3161 union __gdb_builtin_type_vec256i
3163 int128_t v2_int128
[2];
3164 int64_t v4_int64
[4];
3165 int32_t v8_int32
[8];
3166 int16_t v16_int16
[16];
3167 int8_t v32_int8
[32];
3168 double v4_double
[4];
3170 bfloat16_t v16_bfloat16
[16];
3176 t
= arch_composite_type (gdbarch
,
3177 "__gdb_builtin_type_vec256i", TYPE_CODE_UNION
);
3178 append_composite_type_field (t
, "v16_bfloat16",
3179 init_vector_type (bt
->builtin_bfloat16
, 16));
3180 append_composite_type_field (t
, "v8_float",
3181 init_vector_type (bt
->builtin_float
, 8));
3182 append_composite_type_field (t
, "v4_double",
3183 init_vector_type (bt
->builtin_double
, 4));
3184 append_composite_type_field (t
, "v32_int8",
3185 init_vector_type (bt
->builtin_int8
, 32));
3186 append_composite_type_field (t
, "v16_int16",
3187 init_vector_type (bt
->builtin_int16
, 16));
3188 append_composite_type_field (t
, "v8_int32",
3189 init_vector_type (bt
->builtin_int32
, 8));
3190 append_composite_type_field (t
, "v4_int64",
3191 init_vector_type (bt
->builtin_int64
, 4));
3192 append_composite_type_field (t
, "v2_int128",
3193 init_vector_type (bt
->builtin_int128
, 2));
3195 t
->set_is_vector (true);
3196 t
->set_name ("builtin_type_vec256i");
3197 tdep
->i386_ymm_type
= t
;
3200 return tdep
->i386_ymm_type
;
3203 /* Construct vector type for MMX registers. */
3204 static struct type
*
3205 i386_mmx_type (struct gdbarch
*gdbarch
)
3207 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3209 if (!tdep
->i386_mmx_type
)
3211 const struct builtin_type
*bt
= builtin_type (gdbarch
);
3213 /* The type we're building is this: */
3215 union __gdb_builtin_type_vec64i
3218 int32_t v2_int32
[2];
3219 int16_t v4_int16
[4];
3226 t
= arch_composite_type (gdbarch
,
3227 "__gdb_builtin_type_vec64i", TYPE_CODE_UNION
);
3229 append_composite_type_field (t
, "uint64", bt
->builtin_int64
);
3230 append_composite_type_field (t
, "v2_int32",
3231 init_vector_type (bt
->builtin_int32
, 2));
3232 append_composite_type_field (t
, "v4_int16",
3233 init_vector_type (bt
->builtin_int16
, 4));
3234 append_composite_type_field (t
, "v8_int8",
3235 init_vector_type (bt
->builtin_int8
, 8));
3237 t
->set_is_vector (true);
3238 t
->set_name ("builtin_type_vec64i");
3239 tdep
->i386_mmx_type
= t
;
3242 return tdep
->i386_mmx_type
;
3245 /* Return the GDB type object for the "standard" data type of data in
3249 i386_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
3251 if (i386_bnd_regnum_p (gdbarch
, regnum
))
3252 return i386_bnd_type (gdbarch
);
3253 if (i386_mmx_regnum_p (gdbarch
, regnum
))
3254 return i386_mmx_type (gdbarch
);
3255 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
3256 return i386_ymm_type (gdbarch
);
3257 else if (i386_ymm_avx512_regnum_p (gdbarch
, regnum
))
3258 return i386_ymm_type (gdbarch
);
3259 else if (i386_zmm_regnum_p (gdbarch
, regnum
))
3260 return i386_zmm_type (gdbarch
);
3263 const struct builtin_type
*bt
= builtin_type (gdbarch
);
3264 if (i386_byte_regnum_p (gdbarch
, regnum
))
3265 return bt
->builtin_int8
;
3266 else if (i386_word_regnum_p (gdbarch
, regnum
))
3267 return bt
->builtin_int16
;
3268 else if (i386_dword_regnum_p (gdbarch
, regnum
))
3269 return bt
->builtin_int32
;
3270 else if (i386_k_regnum_p (gdbarch
, regnum
))
3271 return bt
->builtin_int64
;
3274 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
3277 /* Map a cooked register onto a raw register or memory. For the i386,
3278 the MMX registers need to be mapped onto floating point registers. */
3281 i386_mmx_regnum_to_fp_regnum (readable_regcache
*regcache
, int regnum
)
3283 struct gdbarch_tdep
*tdep
= gdbarch_tdep (regcache
->arch ());
3288 mmxreg
= regnum
- tdep
->mm0_regnum
;
3289 regcache
->raw_read (I387_FSTAT_REGNUM (tdep
), &fstat
);
3290 tos
= (fstat
>> 11) & 0x7;
3291 fpreg
= (mmxreg
+ tos
) % 8;
3293 return (I387_ST0_REGNUM (tdep
) + fpreg
);
3296 /* A helper function for us by i386_pseudo_register_read_value and
3297 amd64_pseudo_register_read_value. It does all the work but reads
3298 the data into an already-allocated value. */
3301 i386_pseudo_register_read_into_value (struct gdbarch
*gdbarch
,
3302 readable_regcache
*regcache
,
3304 struct value
*result_value
)
3306 gdb_byte raw_buf
[I386_MAX_REGISTER_SIZE
];
3307 enum register_status status
;
3308 gdb_byte
*buf
= value_contents_raw (result_value
);
3310 if (i386_mmx_regnum_p (gdbarch
, regnum
))
3312 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
3314 /* Extract (always little endian). */
3315 status
= regcache
->raw_read (fpnum
, raw_buf
);
3316 if (status
!= REG_VALID
)
3317 mark_value_bytes_unavailable (result_value
, 0,
3318 TYPE_LENGTH (value_type (result_value
)));
3320 memcpy (buf
, raw_buf
, register_size (gdbarch
, regnum
));
3324 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3325 if (i386_bnd_regnum_p (gdbarch
, regnum
))
3327 regnum
-= tdep
->bnd0_regnum
;
3329 /* Extract (always little endian). Read lower 128bits. */
3330 status
= regcache
->raw_read (I387_BND0R_REGNUM (tdep
) + regnum
,
3332 if (status
!= REG_VALID
)
3333 mark_value_bytes_unavailable (result_value
, 0, 16);
3336 enum bfd_endian byte_order
= gdbarch_byte_order (target_gdbarch ());
3337 LONGEST upper
, lower
;
3338 int size
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_data_ptr
);
3340 lower
= extract_unsigned_integer (raw_buf
, 8, byte_order
);
3341 upper
= extract_unsigned_integer (raw_buf
+ 8, 8, byte_order
);
3344 memcpy (buf
, &lower
, size
);
3345 memcpy (buf
+ size
, &upper
, size
);
3348 else if (i386_k_regnum_p (gdbarch
, regnum
))
3350 regnum
-= tdep
->k0_regnum
;
3352 /* Extract (always little endian). */
3353 status
= regcache
->raw_read (tdep
->k0_regnum
+ regnum
, raw_buf
);
3354 if (status
!= REG_VALID
)
3355 mark_value_bytes_unavailable (result_value
, 0, 8);
3357 memcpy (buf
, raw_buf
, 8);
3359 else if (i386_zmm_regnum_p (gdbarch
, regnum
))
3361 regnum
-= tdep
->zmm0_regnum
;
3363 if (regnum
< num_lower_zmm_regs
)
3365 /* Extract (always little endian). Read lower 128bits. */
3366 status
= regcache
->raw_read (I387_XMM0_REGNUM (tdep
) + regnum
,
3368 if (status
!= REG_VALID
)
3369 mark_value_bytes_unavailable (result_value
, 0, 16);
3371 memcpy (buf
, raw_buf
, 16);
3373 /* Extract (always little endian). Read upper 128bits. */
3374 status
= regcache
->raw_read (tdep
->ymm0h_regnum
+ regnum
,
3376 if (status
!= REG_VALID
)
3377 mark_value_bytes_unavailable (result_value
, 16, 16);
3379 memcpy (buf
+ 16, raw_buf
, 16);
3383 /* Extract (always little endian). Read lower 128bits. */
3384 status
= regcache
->raw_read (I387_XMM16_REGNUM (tdep
) + regnum
3385 - num_lower_zmm_regs
,
3387 if (status
!= REG_VALID
)
3388 mark_value_bytes_unavailable (result_value
, 0, 16);
3390 memcpy (buf
, raw_buf
, 16);
3392 /* Extract (always little endian). Read upper 128bits. */
3393 status
= regcache
->raw_read (I387_YMM16H_REGNUM (tdep
) + regnum
3394 - num_lower_zmm_regs
,
3396 if (status
!= REG_VALID
)
3397 mark_value_bytes_unavailable (result_value
, 16, 16);
3399 memcpy (buf
+ 16, raw_buf
, 16);
3402 /* Read upper 256bits. */
3403 status
= regcache
->raw_read (tdep
->zmm0h_regnum
+ regnum
,
3405 if (status
!= REG_VALID
)
3406 mark_value_bytes_unavailable (result_value
, 32, 32);
3408 memcpy (buf
+ 32, raw_buf
, 32);
3410 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
3412 regnum
-= tdep
->ymm0_regnum
;
3414 /* Extract (always little endian). Read lower 128bits. */
3415 status
= regcache
->raw_read (I387_XMM0_REGNUM (tdep
) + regnum
,
3417 if (status
!= REG_VALID
)
3418 mark_value_bytes_unavailable (result_value
, 0, 16);
3420 memcpy (buf
, raw_buf
, 16);
3421 /* Read upper 128bits. */
3422 status
= regcache
->raw_read (tdep
->ymm0h_regnum
+ regnum
,
3424 if (status
!= REG_VALID
)
3425 mark_value_bytes_unavailable (result_value
, 16, 32);
3427 memcpy (buf
+ 16, raw_buf
, 16);
3429 else if (i386_ymm_avx512_regnum_p (gdbarch
, regnum
))
3431 regnum
-= tdep
->ymm16_regnum
;
3432 /* Extract (always little endian). Read lower 128bits. */
3433 status
= regcache
->raw_read (I387_XMM16_REGNUM (tdep
) + regnum
,
3435 if (status
!= REG_VALID
)
3436 mark_value_bytes_unavailable (result_value
, 0, 16);
3438 memcpy (buf
, raw_buf
, 16);
3439 /* Read upper 128bits. */
3440 status
= regcache
->raw_read (tdep
->ymm16h_regnum
+ regnum
,
3442 if (status
!= REG_VALID
)
3443 mark_value_bytes_unavailable (result_value
, 16, 16);
3445 memcpy (buf
+ 16, raw_buf
, 16);
3447 else if (i386_word_regnum_p (gdbarch
, regnum
))
3449 int gpnum
= regnum
- tdep
->ax_regnum
;
3451 /* Extract (always little endian). */
3452 status
= regcache
->raw_read (gpnum
, raw_buf
);
3453 if (status
!= REG_VALID
)
3454 mark_value_bytes_unavailable (result_value
, 0,
3455 TYPE_LENGTH (value_type (result_value
)));
3457 memcpy (buf
, raw_buf
, 2);
3459 else if (i386_byte_regnum_p (gdbarch
, regnum
))
3461 int gpnum
= regnum
- tdep
->al_regnum
;
3463 /* Extract (always little endian). We read both lower and
3465 status
= regcache
->raw_read (gpnum
% 4, raw_buf
);
3466 if (status
!= REG_VALID
)
3467 mark_value_bytes_unavailable (result_value
, 0,
3468 TYPE_LENGTH (value_type (result_value
)));
3469 else if (gpnum
>= 4)
3470 memcpy (buf
, raw_buf
+ 1, 1);
3472 memcpy (buf
, raw_buf
, 1);
3475 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
3479 static struct value
*
3480 i386_pseudo_register_read_value (struct gdbarch
*gdbarch
,
3481 readable_regcache
*regcache
,
3484 struct value
*result
;
3486 result
= allocate_value (register_type (gdbarch
, regnum
));
3487 VALUE_LVAL (result
) = lval_register
;
3488 VALUE_REGNUM (result
) = regnum
;
3490 i386_pseudo_register_read_into_value (gdbarch
, regcache
, regnum
, result
);
3496 i386_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
3497 int regnum
, const gdb_byte
*buf
)
3499 gdb_byte raw_buf
[I386_MAX_REGISTER_SIZE
];
3501 if (i386_mmx_regnum_p (gdbarch
, regnum
))
3503 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
3506 regcache
->raw_read (fpnum
, raw_buf
);
3507 /* ... Modify ... (always little endian). */
3508 memcpy (raw_buf
, buf
, register_size (gdbarch
, regnum
));
3510 regcache
->raw_write (fpnum
, raw_buf
);
3514 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3516 if (i386_bnd_regnum_p (gdbarch
, regnum
))
3518 ULONGEST upper
, lower
;
3519 int size
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_data_ptr
);
3520 enum bfd_endian byte_order
= gdbarch_byte_order (target_gdbarch ());
3522 /* New values from input value. */
3523 regnum
-= tdep
->bnd0_regnum
;
3524 lower
= extract_unsigned_integer (buf
, size
, byte_order
);
3525 upper
= extract_unsigned_integer (buf
+ size
, size
, byte_order
);
3527 /* Fetching register buffer. */
3528 regcache
->raw_read (I387_BND0R_REGNUM (tdep
) + regnum
,
3533 /* Set register bits. */
3534 memcpy (raw_buf
, &lower
, 8);
3535 memcpy (raw_buf
+ 8, &upper
, 8);
3537 regcache
->raw_write (I387_BND0R_REGNUM (tdep
) + regnum
, raw_buf
);
3539 else if (i386_k_regnum_p (gdbarch
, regnum
))
3541 regnum
-= tdep
->k0_regnum
;
3543 regcache
->raw_write (tdep
->k0_regnum
+ regnum
, buf
);
3545 else if (i386_zmm_regnum_p (gdbarch
, regnum
))
3547 regnum
-= tdep
->zmm0_regnum
;
3549 if (regnum
< num_lower_zmm_regs
)
3551 /* Write lower 128bits. */
3552 regcache
->raw_write (I387_XMM0_REGNUM (tdep
) + regnum
, buf
);
3553 /* Write upper 128bits. */
3554 regcache
->raw_write (I387_YMM0_REGNUM (tdep
) + regnum
, buf
+ 16);
3558 /* Write lower 128bits. */
3559 regcache
->raw_write (I387_XMM16_REGNUM (tdep
) + regnum
3560 - num_lower_zmm_regs
, buf
);
3561 /* Write upper 128bits. */
3562 regcache
->raw_write (I387_YMM16H_REGNUM (tdep
) + regnum
3563 - num_lower_zmm_regs
, buf
+ 16);
3565 /* Write upper 256bits. */
3566 regcache
->raw_write (tdep
->zmm0h_regnum
+ regnum
, buf
+ 32);
3568 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
3570 regnum
-= tdep
->ymm0_regnum
;
3572 /* ... Write lower 128bits. */
3573 regcache
->raw_write (I387_XMM0_REGNUM (tdep
) + regnum
, buf
);
3574 /* ... Write upper 128bits. */
3575 regcache
->raw_write (tdep
->ymm0h_regnum
+ regnum
, buf
+ 16);
3577 else if (i386_ymm_avx512_regnum_p (gdbarch
, regnum
))
3579 regnum
-= tdep
->ymm16_regnum
;
3581 /* ... Write lower 128bits. */
3582 regcache
->raw_write (I387_XMM16_REGNUM (tdep
) + regnum
, buf
);
3583 /* ... Write upper 128bits. */
3584 regcache
->raw_write (tdep
->ymm16h_regnum
+ regnum
, buf
+ 16);
3586 else if (i386_word_regnum_p (gdbarch
, regnum
))
3588 int gpnum
= regnum
- tdep
->ax_regnum
;
3591 regcache
->raw_read (gpnum
, raw_buf
);
3592 /* ... Modify ... (always little endian). */
3593 memcpy (raw_buf
, buf
, 2);
3595 regcache
->raw_write (gpnum
, raw_buf
);
3597 else if (i386_byte_regnum_p (gdbarch
, regnum
))
3599 int gpnum
= regnum
- tdep
->al_regnum
;
3601 /* Read ... We read both lower and upper registers. */
3602 regcache
->raw_read (gpnum
% 4, raw_buf
);
3603 /* ... Modify ... (always little endian). */
3605 memcpy (raw_buf
+ 1, buf
, 1);
3607 memcpy (raw_buf
, buf
, 1);
3609 regcache
->raw_write (gpnum
% 4, raw_buf
);
3612 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
3616 /* Implement the 'ax_pseudo_register_collect' gdbarch method. */
3619 i386_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
3620 struct agent_expr
*ax
, int regnum
)
3622 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3624 if (i386_mmx_regnum_p (gdbarch
, regnum
))
3626 /* MMX to FPU register mapping depends on current TOS. Let's just
3627 not care and collect everything... */
3630 ax_reg_mask (ax
, I387_FSTAT_REGNUM (tdep
));
3631 for (i
= 0; i
< 8; i
++)
3632 ax_reg_mask (ax
, I387_ST0_REGNUM (tdep
) + i
);
3635 else if (i386_bnd_regnum_p (gdbarch
, regnum
))
3637 regnum
-= tdep
->bnd0_regnum
;
3638 ax_reg_mask (ax
, I387_BND0R_REGNUM (tdep
) + regnum
);
3641 else if (i386_k_regnum_p (gdbarch
, regnum
))
3643 regnum
-= tdep
->k0_regnum
;
3644 ax_reg_mask (ax
, tdep
->k0_regnum
+ regnum
);
3647 else if (i386_zmm_regnum_p (gdbarch
, regnum
))
3649 regnum
-= tdep
->zmm0_regnum
;
3650 if (regnum
< num_lower_zmm_regs
)
3652 ax_reg_mask (ax
, I387_XMM0_REGNUM (tdep
) + regnum
);
3653 ax_reg_mask (ax
, tdep
->ymm0h_regnum
+ regnum
);
3657 ax_reg_mask (ax
, I387_XMM16_REGNUM (tdep
) + regnum
3658 - num_lower_zmm_regs
);
3659 ax_reg_mask (ax
, I387_YMM16H_REGNUM (tdep
) + regnum
3660 - num_lower_zmm_regs
);
3662 ax_reg_mask (ax
, tdep
->zmm0h_regnum
+ regnum
);
3665 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
3667 regnum
-= tdep
->ymm0_regnum
;
3668 ax_reg_mask (ax
, I387_XMM0_REGNUM (tdep
) + regnum
);
3669 ax_reg_mask (ax
, tdep
->ymm0h_regnum
+ regnum
);
3672 else if (i386_ymm_avx512_regnum_p (gdbarch
, regnum
))
3674 regnum
-= tdep
->ymm16_regnum
;
3675 ax_reg_mask (ax
, I387_XMM16_REGNUM (tdep
) + regnum
);
3676 ax_reg_mask (ax
, tdep
->ymm16h_regnum
+ regnum
);
3679 else if (i386_word_regnum_p (gdbarch
, regnum
))
3681 int gpnum
= regnum
- tdep
->ax_regnum
;
3683 ax_reg_mask (ax
, gpnum
);
3686 else if (i386_byte_regnum_p (gdbarch
, regnum
))
3688 int gpnum
= regnum
- tdep
->al_regnum
;
3690 ax_reg_mask (ax
, gpnum
% 4);
3694 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
3699 /* Return the register number of the register allocated by GCC after
3700 REGNUM, or -1 if there is no such register. */
3703 i386_next_regnum (int regnum
)
3705 /* GCC allocates the registers in the order:
3707 %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ...
3709 Since storing a variable in %esp doesn't make any sense we return
3710 -1 for %ebp and for %esp itself. */
3711 static int next_regnum
[] =
3713 I386_EDX_REGNUM
, /* Slot for %eax. */
3714 I386_EBX_REGNUM
, /* Slot for %ecx. */
3715 I386_ECX_REGNUM
, /* Slot for %edx. */
3716 I386_ESI_REGNUM
, /* Slot for %ebx. */
3717 -1, -1, /* Slots for %esp and %ebp. */
3718 I386_EDI_REGNUM
, /* Slot for %esi. */
3719 I386_EBP_REGNUM
/* Slot for %edi. */
3722 if (regnum
>= 0 && regnum
< sizeof (next_regnum
) / sizeof (next_regnum
[0]))
3723 return next_regnum
[regnum
];
3728 /* Return nonzero if a value of type TYPE stored in register REGNUM
3729 needs any special handling. */
3732 i386_convert_register_p (struct gdbarch
*gdbarch
,
3733 int regnum
, struct type
*type
)
3735 int len
= TYPE_LENGTH (type
);
3737 /* Values may be spread across multiple registers. Most debugging
3738 formats aren't expressive enough to specify the locations, so
3739 some heuristics is involved. Right now we only handle types that
3740 have a length that is a multiple of the word size, since GCC
3741 doesn't seem to put any other types into registers. */
3742 if (len
> 4 && len
% 4 == 0)
3744 int last_regnum
= regnum
;
3748 last_regnum
= i386_next_regnum (last_regnum
);
3752 if (last_regnum
!= -1)
3756 return i387_convert_register_p (gdbarch
, regnum
, type
);
3759 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
3760 return its contents in TO. */
3763 i386_register_to_value (struct frame_info
*frame
, int regnum
,
3764 struct type
*type
, gdb_byte
*to
,
3765 int *optimizedp
, int *unavailablep
)
3767 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3768 int len
= TYPE_LENGTH (type
);
3770 if (i386_fp_regnum_p (gdbarch
, regnum
))
3771 return i387_register_to_value (frame
, regnum
, type
, to
,
3772 optimizedp
, unavailablep
);
3774 /* Read a value spread across multiple registers. */
3776 gdb_assert (len
> 4 && len
% 4 == 0);
3780 gdb_assert (regnum
!= -1);
3781 gdb_assert (register_size (gdbarch
, regnum
) == 4);
3783 if (!get_frame_register_bytes (frame
, regnum
, 0,
3784 register_size (gdbarch
, regnum
),
3785 to
, optimizedp
, unavailablep
))
3788 regnum
= i386_next_regnum (regnum
);
3793 *optimizedp
= *unavailablep
= 0;
3797 /* Write the contents FROM of a value of type TYPE into register
3798 REGNUM in frame FRAME. */
3801 i386_value_to_register (struct frame_info
*frame
, int regnum
,
3802 struct type
*type
, const gdb_byte
*from
)
3804 int len
= TYPE_LENGTH (type
);
3806 if (i386_fp_regnum_p (get_frame_arch (frame
), regnum
))
3808 i387_value_to_register (frame
, regnum
, type
, from
);
3812 /* Write a value spread across multiple registers. */
3814 gdb_assert (len
> 4 && len
% 4 == 0);
3818 gdb_assert (regnum
!= -1);
3819 gdb_assert (register_size (get_frame_arch (frame
), regnum
) == 4);
3821 put_frame_register (frame
, regnum
, from
);
3822 regnum
= i386_next_regnum (regnum
);
3828 /* Supply register REGNUM from the buffer specified by GREGS and LEN
3829 in the general-purpose register set REGSET to register cache
3830 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3833 i386_supply_gregset (const struct regset
*regset
, struct regcache
*regcache
,
3834 int regnum
, const void *gregs
, size_t len
)
3836 struct gdbarch
*gdbarch
= regcache
->arch ();
3837 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3838 const gdb_byte
*regs
= (const gdb_byte
*) gregs
;
3841 gdb_assert (len
>= tdep
->sizeof_gregset
);
3843 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
3845 if ((regnum
== i
|| regnum
== -1)
3846 && tdep
->gregset_reg_offset
[i
] != -1)
3847 regcache
->raw_supply (i
, regs
+ tdep
->gregset_reg_offset
[i
]);
3851 /* Collect register REGNUM from the register cache REGCACHE and store
3852 it in the buffer specified by GREGS and LEN as described by the
3853 general-purpose register set REGSET. If REGNUM is -1, do this for
3854 all registers in REGSET. */
3857 i386_collect_gregset (const struct regset
*regset
,
3858 const struct regcache
*regcache
,
3859 int regnum
, void *gregs
, size_t len
)
3861 struct gdbarch
*gdbarch
= regcache
->arch ();
3862 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3863 gdb_byte
*regs
= (gdb_byte
*) gregs
;
3866 gdb_assert (len
>= tdep
->sizeof_gregset
);
3868 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
3870 if ((regnum
== i
|| regnum
== -1)
3871 && tdep
->gregset_reg_offset
[i
] != -1)
3872 regcache
->raw_collect (i
, regs
+ tdep
->gregset_reg_offset
[i
]);
3876 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
3877 in the floating-point register set REGSET to register cache
3878 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3881 i386_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
3882 int regnum
, const void *fpregs
, size_t len
)
3884 struct gdbarch
*gdbarch
= regcache
->arch ();
3885 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3887 if (len
== I387_SIZEOF_FXSAVE
)
3889 i387_supply_fxsave (regcache
, regnum
, fpregs
);
3893 gdb_assert (len
>= tdep
->sizeof_fpregset
);
3894 i387_supply_fsave (regcache
, regnum
, fpregs
);
3897 /* Collect register REGNUM from the register cache REGCACHE and store
3898 it in the buffer specified by FPREGS and LEN as described by the
3899 floating-point register set REGSET. If REGNUM is -1, do this for
3900 all registers in REGSET. */
3903 i386_collect_fpregset (const struct regset
*regset
,
3904 const struct regcache
*regcache
,
3905 int regnum
, void *fpregs
, size_t len
)
3907 struct gdbarch
*gdbarch
= regcache
->arch ();
3908 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3910 if (len
== I387_SIZEOF_FXSAVE
)
3912 i387_collect_fxsave (regcache
, regnum
, fpregs
);
3916 gdb_assert (len
>= tdep
->sizeof_fpregset
);
3917 i387_collect_fsave (regcache
, regnum
, fpregs
);
3920 /* Register set definitions. */
3922 const struct regset i386_gregset
=
3924 NULL
, i386_supply_gregset
, i386_collect_gregset
3927 const struct regset i386_fpregset
=
3929 NULL
, i386_supply_fpregset
, i386_collect_fpregset
3932 /* Default iterator over core file register note sections. */
3935 i386_iterate_over_regset_sections (struct gdbarch
*gdbarch
,
3936 iterate_over_regset_sections_cb
*cb
,
3938 const struct regcache
*regcache
)
3940 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3942 cb (".reg", tdep
->sizeof_gregset
, tdep
->sizeof_gregset
, &i386_gregset
, NULL
,
3944 if (tdep
->sizeof_fpregset
)
3945 cb (".reg2", tdep
->sizeof_fpregset
, tdep
->sizeof_fpregset
, tdep
->fpregset
,
3950 /* Stuff for WIN32 PE style DLL's but is pretty generic really. */
3953 i386_pe_skip_trampoline_code (struct frame_info
*frame
,
3954 CORE_ADDR pc
, char *name
)
3956 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3957 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3960 if (pc
&& read_memory_unsigned_integer (pc
, 2, byte_order
) == 0x25ff)
3962 unsigned long indirect
=
3963 read_memory_unsigned_integer (pc
+ 2, 4, byte_order
);
3964 struct minimal_symbol
*indsym
=
3965 indirect
? lookup_minimal_symbol_by_pc (indirect
).minsym
: 0;
3966 const char *symname
= indsym
? indsym
->linkage_name () : 0;
3970 if (startswith (symname
, "__imp_")
3971 || startswith (symname
, "_imp_"))
3973 read_memory_unsigned_integer (indirect
, 4, byte_order
);
3976 return 0; /* Not a trampoline. */
3980 /* Return whether the THIS_FRAME corresponds to a sigtramp
3984 i386_sigtramp_p (struct frame_info
*this_frame
)
3986 CORE_ADDR pc
= get_frame_pc (this_frame
);
3989 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
3990 return (name
&& strcmp ("_sigtramp", name
) == 0);
3994 /* We have two flavours of disassembly. The machinery on this page
3995 deals with switching between those. */
3998 i386_print_insn (bfd_vma pc
, struct disassemble_info
*info
)
4000 gdb_assert (disassembly_flavor
== att_flavor
4001 || disassembly_flavor
== intel_flavor
);
4003 info
->disassembler_options
= disassembly_flavor
;
4005 return default_print_insn (pc
, info
);
4009 /* There are a few i386 architecture variants that differ only
4010 slightly from the generic i386 target. For now, we don't give them
4011 their own source file, but include them here. As a consequence,
4012 they'll always be included. */
4014 /* System V Release 4 (SVR4). */
4016 /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp
4020 i386_svr4_sigtramp_p (struct frame_info
*this_frame
)
4022 CORE_ADDR pc
= get_frame_pc (this_frame
);
4025 /* The origin of these symbols is currently unknown. */
4026 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
4027 return (name
&& (strcmp ("_sigreturn", name
) == 0
4028 || strcmp ("sigvechandler", name
) == 0));
4031 /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the
4032 address of the associated sigcontext (ucontext) structure. */
4035 i386_svr4_sigcontext_addr (struct frame_info
*this_frame
)
4037 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
4038 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4042 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
4043 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
4045 return read_memory_unsigned_integer (sp
+ 8, 4, byte_order
);
4050 /* Implementation of `gdbarch_stap_is_single_operand', as defined in
4054 i386_stap_is_single_operand (struct gdbarch
*gdbarch
, const char *s
)
4056 return (*s
== '$' /* Literal number. */
4057 || (isdigit (*s
) && s
[1] == '(' && s
[2] == '%') /* Displacement. */
4058 || (*s
== '(' && s
[1] == '%') /* Register indirection. */
4059 || (*s
== '%' && isalpha (s
[1]))); /* Register access. */
4062 /* Helper function for i386_stap_parse_special_token.
4064 This function parses operands of the form `-8+3+1(%rbp)', which
4065 must be interpreted as `*(-8 + 3 - 1 + (void *) $eax)'.
4067 Return true if the operand was parsed successfully, false
4071 i386_stap_parse_special_token_triplet (struct gdbarch
*gdbarch
,
4072 struct stap_parse_info
*p
)
4074 const char *s
= p
->arg
;
4076 if (isdigit (*s
) || *s
== '-' || *s
== '+')
4080 long displacements
[3];
4087 got_minus
[0] = false;
4093 got_minus
[0] = true;
4096 if (!isdigit ((unsigned char) *s
))
4099 displacements
[0] = strtol (s
, &endp
, 10);
4102 if (*s
!= '+' && *s
!= '-')
4104 /* We are not dealing with a triplet. */
4108 got_minus
[1] = false;
4114 got_minus
[1] = true;
4117 if (!isdigit ((unsigned char) *s
))
4120 displacements
[1] = strtol (s
, &endp
, 10);
4123 if (*s
!= '+' && *s
!= '-')
4125 /* We are not dealing with a triplet. */
4129 got_minus
[2] = false;
4135 got_minus
[2] = true;
4138 if (!isdigit ((unsigned char) *s
))
4141 displacements
[2] = strtol (s
, &endp
, 10);
4144 if (*s
!= '(' || s
[1] != '%')
4150 while (isalnum (*s
))
4156 len
= s
- start
- 1;
4157 regname
= (char *) alloca (len
+ 1);
4159 strncpy (regname
, start
, len
);
4160 regname
[len
] = '\0';
4162 if (user_reg_map_name_to_regnum (gdbarch
, regname
, len
) == -1)
4163 error (_("Invalid register name `%s' on expression `%s'."),
4164 regname
, p
->saved_arg
);
4166 for (i
= 0; i
< 3; i
++)
4168 write_exp_elt_opcode (&p
->pstate
, OP_LONG
);
4170 (&p
->pstate
, builtin_type (gdbarch
)->builtin_long
);
4171 write_exp_elt_longcst (&p
->pstate
, displacements
[i
]);
4172 write_exp_elt_opcode (&p
->pstate
, OP_LONG
);
4174 write_exp_elt_opcode (&p
->pstate
, UNOP_NEG
);
4177 write_exp_elt_opcode (&p
->pstate
, OP_REGISTER
);
4180 write_exp_string (&p
->pstate
, str
);
4181 write_exp_elt_opcode (&p
->pstate
, OP_REGISTER
);
4183 write_exp_elt_opcode (&p
->pstate
, UNOP_CAST
);
4184 write_exp_elt_type (&p
->pstate
,
4185 builtin_type (gdbarch
)->builtin_data_ptr
);
4186 write_exp_elt_opcode (&p
->pstate
, UNOP_CAST
);
4188 write_exp_elt_opcode (&p
->pstate
, BINOP_ADD
);
4189 write_exp_elt_opcode (&p
->pstate
, BINOP_ADD
);
4190 write_exp_elt_opcode (&p
->pstate
, BINOP_ADD
);
4192 write_exp_elt_opcode (&p
->pstate
, UNOP_CAST
);
4193 write_exp_elt_type (&p
->pstate
,
4194 lookup_pointer_type (p
->arg_type
));
4195 write_exp_elt_opcode (&p
->pstate
, UNOP_CAST
);
4197 write_exp_elt_opcode (&p
->pstate
, UNOP_IND
);
4207 /* Helper function for i386_stap_parse_special_token.
4209 This function parses operands of the form `register base +
4210 (register index * size) + offset', as represented in
4211 `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'.
4213 Return true if the operand was parsed successfully, false
4217 i386_stap_parse_special_token_three_arg_disp (struct gdbarch
*gdbarch
,
4218 struct stap_parse_info
*p
)
4220 const char *s
= p
->arg
;
4222 if (isdigit (*s
) || *s
== '(' || *s
== '-' || *s
== '+')
4224 bool offset_minus
= false;
4226 bool size_minus
= false;
4233 struct stoken base_token
, index_token
;
4240 offset_minus
= true;
4243 if (offset_minus
&& !isdigit (*s
))
4250 offset
= strtol (s
, &endp
, 10);
4254 if (*s
!= '(' || s
[1] != '%')
4260 while (isalnum (*s
))
4263 if (*s
!= ',' || s
[1] != '%')
4266 len_base
= s
- start
;
4267 base
= (char *) alloca (len_base
+ 1);
4268 strncpy (base
, start
, len_base
);
4269 base
[len_base
] = '\0';
4271 if (user_reg_map_name_to_regnum (gdbarch
, base
, len_base
) == -1)
4272 error (_("Invalid register name `%s' on expression `%s'."),
4273 base
, p
->saved_arg
);
4278 while (isalnum (*s
))
4281 len_index
= s
- start
;
4282 index
= (char *) alloca (len_index
+ 1);
4283 strncpy (index
, start
, len_index
);
4284 index
[len_index
] = '\0';
4286 if (user_reg_map_name_to_regnum (gdbarch
, index
, len_index
) == -1)
4287 error (_("Invalid register name `%s' on expression `%s'."),
4288 index
, p
->saved_arg
);
4290 if (*s
!= ',' && *s
!= ')')
4306 size
= strtol (s
, &endp
, 10);
4317 write_exp_elt_opcode (&p
->pstate
, OP_LONG
);
4318 write_exp_elt_type (&p
->pstate
,
4319 builtin_type (gdbarch
)->builtin_long
);
4320 write_exp_elt_longcst (&p
->pstate
, offset
);
4321 write_exp_elt_opcode (&p
->pstate
, OP_LONG
);
4323 write_exp_elt_opcode (&p
->pstate
, UNOP_NEG
);
4326 write_exp_elt_opcode (&p
->pstate
, OP_REGISTER
);
4327 base_token
.ptr
= base
;
4328 base_token
.length
= len_base
;
4329 write_exp_string (&p
->pstate
, base_token
);
4330 write_exp_elt_opcode (&p
->pstate
, OP_REGISTER
);
4333 write_exp_elt_opcode (&p
->pstate
, BINOP_ADD
);
4335 write_exp_elt_opcode (&p
->pstate
, OP_REGISTER
);
4336 index_token
.ptr
= index
;
4337 index_token
.length
= len_index
;
4338 write_exp_string (&p
->pstate
, index_token
);
4339 write_exp_elt_opcode (&p
->pstate
, OP_REGISTER
);
4343 write_exp_elt_opcode (&p
->pstate
, OP_LONG
);
4344 write_exp_elt_type (&p
->pstate
,
4345 builtin_type (gdbarch
)->builtin_long
);
4346 write_exp_elt_longcst (&p
->pstate
, size
);
4347 write_exp_elt_opcode (&p
->pstate
, OP_LONG
);
4349 write_exp_elt_opcode (&p
->pstate
, UNOP_NEG
);
4350 write_exp_elt_opcode (&p
->pstate
, BINOP_MUL
);
4353 write_exp_elt_opcode (&p
->pstate
, BINOP_ADD
);
4355 write_exp_elt_opcode (&p
->pstate
, UNOP_CAST
);
4356 write_exp_elt_type (&p
->pstate
,
4357 lookup_pointer_type (p
->arg_type
));
4358 write_exp_elt_opcode (&p
->pstate
, UNOP_CAST
);
4360 write_exp_elt_opcode (&p
->pstate
, UNOP_IND
);
4370 /* Implementation of `gdbarch_stap_parse_special_token', as defined in
4374 i386_stap_parse_special_token (struct gdbarch
*gdbarch
,
4375 struct stap_parse_info
*p
)
4377 /* In order to parse special tokens, we use a state-machine that go
4378 through every known token and try to get a match. */
4382 THREE_ARG_DISPLACEMENT
,
4387 current_state
= TRIPLET
;
4389 /* The special tokens to be parsed here are:
4391 - `register base + (register index * size) + offset', as represented
4392 in `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'.
4394 - Operands of the form `-8+3+1(%rbp)', which must be interpreted as
4395 `*(-8 + 3 - 1 + (void *) $eax)'. */
4397 while (current_state
!= DONE
)
4399 switch (current_state
)
4402 if (i386_stap_parse_special_token_triplet (gdbarch
, p
))
4406 case THREE_ARG_DISPLACEMENT
:
4407 if (i386_stap_parse_special_token_three_arg_disp (gdbarch
, p
))
4412 /* Advancing to the next state. */
4419 /* Implementation of 'gdbarch_stap_adjust_register', as defined in
4423 i386_stap_adjust_register (struct gdbarch
*gdbarch
, struct stap_parse_info
*p
,
4424 const std::string
®name
, int regnum
)
4426 static const std::unordered_set
<std::string
> reg_assoc
4427 = { "ax", "bx", "cx", "dx",
4428 "si", "di", "bp", "sp" };
4430 /* If we are dealing with a register whose size is less than the size
4431 specified by the "[-]N@" prefix, and it is one of the registers that
4432 we know has an extended variant available, then use the extended
4433 version of the register instead. */
4434 if (register_size (gdbarch
, regnum
) < TYPE_LENGTH (p
->arg_type
)
4435 && reg_assoc
.find (regname
) != reg_assoc
.end ())
4436 return "e" + regname
;
4438 /* Otherwise, just use the requested register. */
4444 /* gdbarch gnu_triplet_regexp method. Both arches are acceptable as GDB always
4445 also supplies -m64 or -m32 by gdbarch_gcc_target_options. */
4448 i386_gnu_triplet_regexp (struct gdbarch
*gdbarch
)
4450 return "(x86_64|i.86)";
4455 /* Implement the "in_indirect_branch_thunk" gdbarch function. */
4458 i386_in_indirect_branch_thunk (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4460 return x86_in_indirect_branch_thunk (pc
, i386_register_names
,
4461 I386_EAX_REGNUM
, I386_EIP_REGNUM
);
4467 i386_elf_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
4469 static const char *const stap_integer_prefixes
[] = { "$", NULL
};
4470 static const char *const stap_register_prefixes
[] = { "%", NULL
};
4471 static const char *const stap_register_indirection_prefixes
[] = { "(",
4473 static const char *const stap_register_indirection_suffixes
[] = { ")",
4476 /* We typically use stabs-in-ELF with the SVR4 register numbering. */
4477 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
4479 /* Registering SystemTap handlers. */
4480 set_gdbarch_stap_integer_prefixes (gdbarch
, stap_integer_prefixes
);
4481 set_gdbarch_stap_register_prefixes (gdbarch
, stap_register_prefixes
);
4482 set_gdbarch_stap_register_indirection_prefixes (gdbarch
,
4483 stap_register_indirection_prefixes
);
4484 set_gdbarch_stap_register_indirection_suffixes (gdbarch
,
4485 stap_register_indirection_suffixes
);
4486 set_gdbarch_stap_is_single_operand (gdbarch
,
4487 i386_stap_is_single_operand
);
4488 set_gdbarch_stap_parse_special_token (gdbarch
,
4489 i386_stap_parse_special_token
);
4490 set_gdbarch_stap_adjust_register (gdbarch
,
4491 i386_stap_adjust_register
);
4493 set_gdbarch_in_indirect_branch_thunk (gdbarch
,
4494 i386_in_indirect_branch_thunk
);
4497 /* System V Release 4 (SVR4). */
4500 i386_svr4_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
4502 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4504 /* System V Release 4 uses ELF. */
4505 i386_elf_init_abi (info
, gdbarch
);
4507 /* System V Release 4 has shared libraries. */
4508 set_gdbarch_skip_trampoline_code (gdbarch
, find_solib_trampoline_target
);
4510 tdep
->sigtramp_p
= i386_svr4_sigtramp_p
;
4511 tdep
->sigcontext_addr
= i386_svr4_sigcontext_addr
;
4512 tdep
->sc_pc_offset
= 36 + 14 * 4;
4513 tdep
->sc_sp_offset
= 36 + 17 * 4;
4515 tdep
->jb_pc_offset
= 20;
4520 /* i386 register groups. In addition to the normal groups, add "mmx"
4523 static struct reggroup
*i386_sse_reggroup
;
4524 static struct reggroup
*i386_mmx_reggroup
;
4527 i386_init_reggroups (void)
4529 i386_sse_reggroup
= reggroup_new ("sse", USER_REGGROUP
);
4530 i386_mmx_reggroup
= reggroup_new ("mmx", USER_REGGROUP
);
4534 i386_add_reggroups (struct gdbarch
*gdbarch
)
4536 reggroup_add (gdbarch
, i386_sse_reggroup
);
4537 reggroup_add (gdbarch
, i386_mmx_reggroup
);
4538 reggroup_add (gdbarch
, general_reggroup
);
4539 reggroup_add (gdbarch
, float_reggroup
);
4540 reggroup_add (gdbarch
, all_reggroup
);
4541 reggroup_add (gdbarch
, save_reggroup
);
4542 reggroup_add (gdbarch
, restore_reggroup
);
4543 reggroup_add (gdbarch
, vector_reggroup
);
4544 reggroup_add (gdbarch
, system_reggroup
);
4548 i386_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
4549 struct reggroup
*group
)
4551 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4552 int fp_regnum_p
, mmx_regnum_p
, xmm_regnum_p
, mxcsr_regnum_p
,
4553 ymm_regnum_p
, ymmh_regnum_p
, ymm_avx512_regnum_p
, ymmh_avx512_regnum_p
,
4554 bndr_regnum_p
, bnd_regnum_p
, zmm_regnum_p
, zmmh_regnum_p
,
4555 mpx_ctrl_regnum_p
, xmm_avx512_regnum_p
,
4556 avx512_p
, avx_p
, sse_p
, pkru_regnum_p
;
4558 /* Don't include pseudo registers, except for MMX, in any register
4560 if (i386_byte_regnum_p (gdbarch
, regnum
))
4563 if (i386_word_regnum_p (gdbarch
, regnum
))
4566 if (i386_dword_regnum_p (gdbarch
, regnum
))
4569 mmx_regnum_p
= i386_mmx_regnum_p (gdbarch
, regnum
);
4570 if (group
== i386_mmx_reggroup
)
4571 return mmx_regnum_p
;
4573 pkru_regnum_p
= i386_pkru_regnum_p(gdbarch
, regnum
);
4574 xmm_regnum_p
= i386_xmm_regnum_p (gdbarch
, regnum
);
4575 xmm_avx512_regnum_p
= i386_xmm_avx512_regnum_p (gdbarch
, regnum
);
4576 mxcsr_regnum_p
= i386_mxcsr_regnum_p (gdbarch
, regnum
);
4577 if (group
== i386_sse_reggroup
)
4578 return xmm_regnum_p
|| xmm_avx512_regnum_p
|| mxcsr_regnum_p
;
4580 ymm_regnum_p
= i386_ymm_regnum_p (gdbarch
, regnum
);
4581 ymm_avx512_regnum_p
= i386_ymm_avx512_regnum_p (gdbarch
, regnum
);
4582 zmm_regnum_p
= i386_zmm_regnum_p (gdbarch
, regnum
);
4584 avx512_p
= ((tdep
->xcr0
& X86_XSTATE_AVX_AVX512_MASK
)
4585 == X86_XSTATE_AVX_AVX512_MASK
);
4586 avx_p
= ((tdep
->xcr0
& X86_XSTATE_AVX_AVX512_MASK
)
4587 == X86_XSTATE_AVX_MASK
) && !avx512_p
;
4588 sse_p
= ((tdep
->xcr0
& X86_XSTATE_AVX_AVX512_MASK
)
4589 == X86_XSTATE_SSE_MASK
) && !avx512_p
&& ! avx_p
;
4591 if (group
== vector_reggroup
)
4592 return (mmx_regnum_p
4593 || (zmm_regnum_p
&& avx512_p
)
4594 || ((ymm_regnum_p
|| ymm_avx512_regnum_p
) && avx_p
)
4595 || ((xmm_regnum_p
|| xmm_avx512_regnum_p
) && sse_p
)
4598 fp_regnum_p
= (i386_fp_regnum_p (gdbarch
, regnum
)
4599 || i386_fpc_regnum_p (gdbarch
, regnum
));
4600 if (group
== float_reggroup
)
4603 /* For "info reg all", don't include upper YMM registers nor XMM
4604 registers when AVX is supported. */
4605 ymmh_regnum_p
= i386_ymmh_regnum_p (gdbarch
, regnum
);
4606 ymmh_avx512_regnum_p
= i386_ymmh_avx512_regnum_p (gdbarch
, regnum
);
4607 zmmh_regnum_p
= i386_zmmh_regnum_p (gdbarch
, regnum
);
4608 if (group
== all_reggroup
4609 && (((xmm_regnum_p
|| xmm_avx512_regnum_p
) && !sse_p
)
4610 || ((ymm_regnum_p
|| ymm_avx512_regnum_p
) && !avx_p
)
4612 || ymmh_avx512_regnum_p
4616 bnd_regnum_p
= i386_bnd_regnum_p (gdbarch
, regnum
);
4617 if (group
== all_reggroup
4618 && ((bnd_regnum_p
&& (tdep
->xcr0
& X86_XSTATE_MPX_MASK
))))
4619 return bnd_regnum_p
;
4621 bndr_regnum_p
= i386_bndr_regnum_p (gdbarch
, regnum
);
4622 if (group
== all_reggroup
4623 && ((bndr_regnum_p
&& (tdep
->xcr0
& X86_XSTATE_MPX_MASK
))))
4626 mpx_ctrl_regnum_p
= i386_mpx_ctrl_regnum_p (gdbarch
, regnum
);
4627 if (group
== all_reggroup
4628 && ((mpx_ctrl_regnum_p
&& (tdep
->xcr0
& X86_XSTATE_MPX_MASK
))))
4629 return mpx_ctrl_regnum_p
;
4631 if (group
== general_reggroup
)
4632 return (!fp_regnum_p
4636 && !xmm_avx512_regnum_p
4639 && !ymm_avx512_regnum_p
4640 && !ymmh_avx512_regnum_p
4643 && !mpx_ctrl_regnum_p
4648 return default_register_reggroup_p (gdbarch
, regnum
, group
);
4652 /* Get the ARGIth function argument for the current function. */
4655 i386_fetch_pointer_argument (struct frame_info
*frame
, int argi
,
4658 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4659 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4660 CORE_ADDR sp
= get_frame_register_unsigned (frame
, I386_ESP_REGNUM
);
4661 return read_memory_unsigned_integer (sp
+ (4 * (argi
+ 1)), 4, byte_order
);
4664 #define PREFIX_REPZ 0x01
4665 #define PREFIX_REPNZ 0x02
4666 #define PREFIX_LOCK 0x04
4667 #define PREFIX_DATA 0x08
4668 #define PREFIX_ADDR 0x10
4680 /* i386 arith/logic operations */
4693 struct i386_record_s
4695 struct gdbarch
*gdbarch
;
4696 struct regcache
*regcache
;
4697 CORE_ADDR orig_addr
;
4703 uint8_t mod
, reg
, rm
;
4712 /* Parse the "modrm" part of the memory address irp->addr points at.
4713 Returns -1 if something goes wrong, 0 otherwise. */
4716 i386_record_modrm (struct i386_record_s
*irp
)
4718 struct gdbarch
*gdbarch
= irp
->gdbarch
;
4720 if (record_read_memory (gdbarch
, irp
->addr
, &irp
->modrm
, 1))
4724 irp
->mod
= (irp
->modrm
>> 6) & 3;
4725 irp
->reg
= (irp
->modrm
>> 3) & 7;
4726 irp
->rm
= irp
->modrm
& 7;
4731 /* Extract the memory address that the current instruction writes to,
4732 and return it in *ADDR. Return -1 if something goes wrong. */
4735 i386_record_lea_modrm_addr (struct i386_record_s
*irp
, uint64_t *addr
)
4737 struct gdbarch
*gdbarch
= irp
->gdbarch
;
4738 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4743 if (irp
->aflag
|| irp
->regmap
[X86_RECORD_R8_REGNUM
])
4750 uint8_t base
= irp
->rm
;
4755 if (record_read_memory (gdbarch
, irp
->addr
, &byte
, 1))
4758 scale
= (byte
>> 6) & 3;
4759 index
= ((byte
>> 3) & 7) | irp
->rex_x
;
4767 if ((base
& 7) == 5)
4770 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 4))
4773 *addr
= extract_signed_integer (buf
, 4, byte_order
);
4774 if (irp
->regmap
[X86_RECORD_R8_REGNUM
] && !havesib
)
4775 *addr
+= irp
->addr
+ irp
->rip_offset
;
4779 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 1))
4782 *addr
= (int8_t) buf
[0];
4785 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 4))
4787 *addr
= extract_signed_integer (buf
, 4, byte_order
);
4795 if (base
== 4 && irp
->popl_esp_hack
)
4796 *addr
+= irp
->popl_esp_hack
;
4797 regcache_raw_read_unsigned (irp
->regcache
, irp
->regmap
[base
],
4800 if (irp
->aflag
== 2)
4805 *addr
= (uint32_t) (offset64
+ *addr
);
4807 if (havesib
&& (index
!= 4 || scale
!= 0))
4809 regcache_raw_read_unsigned (irp
->regcache
, irp
->regmap
[index
],
4811 if (irp
->aflag
== 2)
4812 *addr
+= offset64
<< scale
;
4814 *addr
= (uint32_t) (*addr
+ (offset64
<< scale
));
4819 /* Since we are in 64-bit mode with ADDR32 prefix, zero-extend
4820 address from 32-bit to 64-bit. */
4821 *addr
= (uint32_t) *addr
;
4832 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 2))
4835 *addr
= extract_signed_integer (buf
, 2, byte_order
);
4841 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 1))
4844 *addr
= (int8_t) buf
[0];
4847 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 2))
4850 *addr
= extract_signed_integer (buf
, 2, byte_order
);
4857 regcache_raw_read_unsigned (irp
->regcache
,
4858 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
4860 *addr
= (uint32_t) (*addr
+ offset64
);
4861 regcache_raw_read_unsigned (irp
->regcache
,
4862 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
4864 *addr
= (uint32_t) (*addr
+ offset64
);
4867 regcache_raw_read_unsigned (irp
->regcache
,
4868 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
4870 *addr
= (uint32_t) (*addr
+ offset64
);
4871 regcache_raw_read_unsigned (irp
->regcache
,
4872 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
4874 *addr
= (uint32_t) (*addr
+ offset64
);
4877 regcache_raw_read_unsigned (irp
->regcache
,
4878 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
4880 *addr
= (uint32_t) (*addr
+ offset64
);
4881 regcache_raw_read_unsigned (irp
->regcache
,
4882 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
4884 *addr
= (uint32_t) (*addr
+ offset64
);
4887 regcache_raw_read_unsigned (irp
->regcache
,
4888 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
4890 *addr
= (uint32_t) (*addr
+ offset64
);
4891 regcache_raw_read_unsigned (irp
->regcache
,
4892 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
4894 *addr
= (uint32_t) (*addr
+ offset64
);
4897 regcache_raw_read_unsigned (irp
->regcache
,
4898 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
4900 *addr
= (uint32_t) (*addr
+ offset64
);
4903 regcache_raw_read_unsigned (irp
->regcache
,
4904 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
4906 *addr
= (uint32_t) (*addr
+ offset64
);
4909 regcache_raw_read_unsigned (irp
->regcache
,
4910 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
4912 *addr
= (uint32_t) (*addr
+ offset64
);
4915 regcache_raw_read_unsigned (irp
->regcache
,
4916 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
4918 *addr
= (uint32_t) (*addr
+ offset64
);
4928 /* Record the address and contents of the memory that will be changed
4929 by the current instruction. Return -1 if something goes wrong, 0
4933 i386_record_lea_modrm (struct i386_record_s
*irp
)
4935 struct gdbarch
*gdbarch
= irp
->gdbarch
;
4938 if (irp
->override
>= 0)
4940 if (record_full_memory_query
)
4943 Process record ignores the memory change of instruction at address %s\n\
4944 because it can't get the value of the segment register.\n\
4945 Do you want to stop the program?"),
4946 paddress (gdbarch
, irp
->orig_addr
)))
4953 if (i386_record_lea_modrm_addr (irp
, &addr
))
4956 if (record_full_arch_list_add_mem (addr
, 1 << irp
->ot
))
4962 /* Record the effects of a push operation. Return -1 if something
4963 goes wrong, 0 otherwise. */
4966 i386_record_push (struct i386_record_s
*irp
, int size
)
4970 if (record_full_arch_list_add_reg (irp
->regcache
,
4971 irp
->regmap
[X86_RECORD_RESP_REGNUM
]))
4973 regcache_raw_read_unsigned (irp
->regcache
,
4974 irp
->regmap
[X86_RECORD_RESP_REGNUM
],
4976 if (record_full_arch_list_add_mem ((CORE_ADDR
) addr
- size
, size
))
4983 /* Defines contents to record. */
4984 #define I386_SAVE_FPU_REGS 0xfffd
4985 #define I386_SAVE_FPU_ENV 0xfffe
4986 #define I386_SAVE_FPU_ENV_REG_STACK 0xffff
4988 /* Record the values of the floating point registers which will be
4989 changed by the current instruction. Returns -1 if something is
4990 wrong, 0 otherwise. */
4992 static int i386_record_floats (struct gdbarch
*gdbarch
,
4993 struct i386_record_s
*ir
,
4996 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4999 /* Oza: Because of floating point insn push/pop of fpu stack is going to
5000 happen. Currently we store st0-st7 registers, but we need not store all
5001 registers all the time, in future we use ftag register and record only
5002 those who are not marked as an empty. */
5004 if (I386_SAVE_FPU_REGS
== iregnum
)
5006 for (i
= I387_ST0_REGNUM (tdep
); i
<= I387_ST0_REGNUM (tdep
) + 7; i
++)
5008 if (record_full_arch_list_add_reg (ir
->regcache
, i
))
5012 else if (I386_SAVE_FPU_ENV
== iregnum
)
5014 for (i
= I387_FCTRL_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
5016 if (record_full_arch_list_add_reg (ir
->regcache
, i
))
5020 else if (I386_SAVE_FPU_ENV_REG_STACK
== iregnum
)
5022 for (i
= I387_ST0_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
5024 if (record_full_arch_list_add_reg (ir
->regcache
, i
))
5028 else if ((iregnum
>= I387_ST0_REGNUM (tdep
)) &&
5029 (iregnum
<= I387_FOP_REGNUM (tdep
)))
5031 if (record_full_arch_list_add_reg (ir
->regcache
,iregnum
))
5036 /* Parameter error. */
5039 if(I386_SAVE_FPU_ENV
!= iregnum
)
5041 for (i
= I387_FCTRL_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
5043 if (record_full_arch_list_add_reg (ir
->regcache
, i
))
5050 /* Parse the current instruction, and record the values of the
5051 registers and memory that will be changed by the current
5052 instruction. Returns -1 if something goes wrong, 0 otherwise. */
5054 #define I386_RECORD_FULL_ARCH_LIST_ADD_REG(regnum) \
5055 record_full_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)])
5058 i386_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5059 CORE_ADDR input_addr
)
5061 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5067 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
5068 struct i386_record_s ir
;
5069 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5073 memset (&ir
, 0, sizeof (struct i386_record_s
));
5074 ir
.regcache
= regcache
;
5075 ir
.addr
= input_addr
;
5076 ir
.orig_addr
= input_addr
;
5080 ir
.popl_esp_hack
= 0;
5081 ir
.regmap
= tdep
->record_regmap
;
5082 ir
.gdbarch
= gdbarch
;
5084 if (record_debug
> 1)
5085 fprintf_unfiltered (gdb_stdlog
, "Process record: i386_process_record "
5087 paddress (gdbarch
, ir
.addr
));
5092 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
5095 switch (opcode8
) /* Instruction prefixes */
5097 case REPE_PREFIX_OPCODE
:
5098 prefixes
|= PREFIX_REPZ
;
5100 case REPNE_PREFIX_OPCODE
:
5101 prefixes
|= PREFIX_REPNZ
;
5103 case LOCK_PREFIX_OPCODE
:
5104 prefixes
|= PREFIX_LOCK
;
5106 case CS_PREFIX_OPCODE
:
5107 ir
.override
= X86_RECORD_CS_REGNUM
;
5109 case SS_PREFIX_OPCODE
:
5110 ir
.override
= X86_RECORD_SS_REGNUM
;
5112 case DS_PREFIX_OPCODE
:
5113 ir
.override
= X86_RECORD_DS_REGNUM
;
5115 case ES_PREFIX_OPCODE
:
5116 ir
.override
= X86_RECORD_ES_REGNUM
;
5118 case FS_PREFIX_OPCODE
:
5119 ir
.override
= X86_RECORD_FS_REGNUM
;
5121 case GS_PREFIX_OPCODE
:
5122 ir
.override
= X86_RECORD_GS_REGNUM
;
5124 case DATA_PREFIX_OPCODE
:
5125 prefixes
|= PREFIX_DATA
;
5127 case ADDR_PREFIX_OPCODE
:
5128 prefixes
|= PREFIX_ADDR
;
5130 case 0x40: /* i386 inc %eax */
5131 case 0x41: /* i386 inc %ecx */
5132 case 0x42: /* i386 inc %edx */
5133 case 0x43: /* i386 inc %ebx */
5134 case 0x44: /* i386 inc %esp */
5135 case 0x45: /* i386 inc %ebp */
5136 case 0x46: /* i386 inc %esi */
5137 case 0x47: /* i386 inc %edi */
5138 case 0x48: /* i386 dec %eax */
5139 case 0x49: /* i386 dec %ecx */
5140 case 0x4a: /* i386 dec %edx */
5141 case 0x4b: /* i386 dec %ebx */
5142 case 0x4c: /* i386 dec %esp */
5143 case 0x4d: /* i386 dec %ebp */
5144 case 0x4e: /* i386 dec %esi */
5145 case 0x4f: /* i386 dec %edi */
5146 if (ir
.regmap
[X86_RECORD_R8_REGNUM
]) /* 64 bit target */
5149 rex_w
= (opcode8
>> 3) & 1;
5150 rex_r
= (opcode8
& 0x4) << 1;
5151 ir
.rex_x
= (opcode8
& 0x2) << 2;
5152 ir
.rex_b
= (opcode8
& 0x1) << 3;
5154 else /* 32 bit target */
5163 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && rex_w
== 1)
5169 if (prefixes
& PREFIX_DATA
)
5172 if (prefixes
& PREFIX_ADDR
)
5174 else if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5177 /* Now check op code. */
5178 opcode
= (uint32_t) opcode8
;
5183 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
5186 opcode
= (uint32_t) opcode8
| 0x0f00;
5190 case 0x00: /* arith & logic */
5238 if (((opcode
>> 3) & 7) != OP_CMPL
)
5240 if ((opcode
& 1) == 0)
5243 ir
.ot
= ir
.dflag
+ OT_WORD
;
5245 switch ((opcode
>> 1) & 3)
5247 case 0: /* OP Ev, Gv */
5248 if (i386_record_modrm (&ir
))
5252 if (i386_record_lea_modrm (&ir
))
5258 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5260 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5263 case 1: /* OP Gv, Ev */
5264 if (i386_record_modrm (&ir
))
5267 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5269 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5271 case 2: /* OP A, Iv */
5272 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5276 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5279 case 0x80: /* GRP1 */
5283 if (i386_record_modrm (&ir
))
5286 if (ir
.reg
!= OP_CMPL
)
5288 if ((opcode
& 1) == 0)
5291 ir
.ot
= ir
.dflag
+ OT_WORD
;
5298 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
5299 if (i386_record_lea_modrm (&ir
))
5303 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5305 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5308 case 0x40: /* inc */
5317 case 0x48: /* dec */
5326 I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode
& 7);
5327 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5330 case 0xf6: /* GRP3 */
5332 if ((opcode
& 1) == 0)
5335 ir
.ot
= ir
.dflag
+ OT_WORD
;
5336 if (i386_record_modrm (&ir
))
5339 if (ir
.mod
!= 3 && ir
.reg
== 0)
5340 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
5345 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5351 if (i386_record_lea_modrm (&ir
))
5357 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5359 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5361 if (ir
.reg
== 3) /* neg */
5362 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5368 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5369 if (ir
.ot
!= OT_BYTE
)
5370 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5371 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5375 opcode
= opcode
<< 8 | ir
.modrm
;
5381 case 0xfe: /* GRP4 */
5382 case 0xff: /* GRP5 */
5383 if (i386_record_modrm (&ir
))
5385 if (ir
.reg
>= 2 && opcode
== 0xfe)
5388 opcode
= opcode
<< 8 | ir
.modrm
;
5395 if ((opcode
& 1) == 0)
5398 ir
.ot
= ir
.dflag
+ OT_WORD
;
5401 if (i386_record_lea_modrm (&ir
))
5407 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5409 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5411 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5414 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5416 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5418 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5421 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
5422 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5424 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5428 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5431 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5433 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5438 opcode
= opcode
<< 8 | ir
.modrm
;
5444 case 0x84: /* test */
5448 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5451 case 0x98: /* CWDE/CBW */
5452 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5455 case 0x99: /* CDQ/CWD */
5456 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5457 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5460 case 0x0faf: /* imul */
5463 ir
.ot
= ir
.dflag
+ OT_WORD
;
5464 if (i386_record_modrm (&ir
))
5467 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
5468 else if (opcode
== 0x6b)
5471 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5473 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5474 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5477 case 0x0fc0: /* xadd */
5479 if ((opcode
& 1) == 0)
5482 ir
.ot
= ir
.dflag
+ OT_WORD
;
5483 if (i386_record_modrm (&ir
))
5488 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5490 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5491 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5493 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5497 if (i386_record_lea_modrm (&ir
))
5499 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5501 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5503 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5506 case 0x0fb0: /* cmpxchg */
5508 if ((opcode
& 1) == 0)
5511 ir
.ot
= ir
.dflag
+ OT_WORD
;
5512 if (i386_record_modrm (&ir
))
5517 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5518 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5520 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5524 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5525 if (i386_record_lea_modrm (&ir
))
5528 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5531 case 0x0fc7: /* cmpxchg8b / rdrand / rdseed */
5532 if (i386_record_modrm (&ir
))
5536 /* rdrand and rdseed use the 3 bits of the REG field of ModR/M as
5537 an extended opcode. rdrand has bits 110 (/6) and rdseed
5538 has bits 111 (/7). */
5539 if (ir
.reg
== 6 || ir
.reg
== 7)
5541 /* The storage register is described by the 3 R/M bits, but the
5542 REX.B prefix may be used to give access to registers
5543 R8~R15. In this case ir.rex_b + R/M will give us the register
5544 in the range R8~R15.
5546 REX.W may also be used to access 64-bit registers, but we
5547 already record entire registers and not just partial bits
5549 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rex_b
+ ir
.rm
);
5550 /* These instructions also set conditional bits. */
5551 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5556 /* We don't handle this particular instruction yet. */
5558 opcode
= opcode
<< 8 | ir
.modrm
;
5562 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5563 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5564 if (i386_record_lea_modrm (&ir
))
5566 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5569 case 0x50: /* push */
5579 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5581 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5585 case 0x06: /* push es */
5586 case 0x0e: /* push cs */
5587 case 0x16: /* push ss */
5588 case 0x1e: /* push ds */
5589 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5594 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5598 case 0x0fa0: /* push fs */
5599 case 0x0fa8: /* push gs */
5600 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5605 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5609 case 0x60: /* pusha */
5610 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5615 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 4)))
5619 case 0x58: /* pop */
5627 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5628 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode
& 0x7) | ir
.rex_b
);
5631 case 0x61: /* popa */
5632 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5637 for (regnum
= X86_RECORD_REAX_REGNUM
;
5638 regnum
<= X86_RECORD_REDI_REGNUM
;
5640 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum
);
5643 case 0x8f: /* pop */
5644 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5645 ir
.ot
= ir
.dflag
? OT_QUAD
: OT_WORD
;
5647 ir
.ot
= ir
.dflag
+ OT_WORD
;
5648 if (i386_record_modrm (&ir
))
5651 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5654 ir
.popl_esp_hack
= 1 << ir
.ot
;
5655 if (i386_record_lea_modrm (&ir
))
5658 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5661 case 0xc8: /* enter */
5662 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
5663 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5665 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5669 case 0xc9: /* leave */
5670 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5671 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
5674 case 0x07: /* pop es */
5675 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5680 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5681 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM
);
5682 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5685 case 0x17: /* pop ss */
5686 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5691 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5692 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM
);
5693 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5696 case 0x1f: /* pop ds */
5697 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5702 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5703 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM
);
5704 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5707 case 0x0fa1: /* pop fs */
5708 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5709 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM
);
5710 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5713 case 0x0fa9: /* pop gs */
5714 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5715 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM
);
5716 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5719 case 0x88: /* mov */
5723 if ((opcode
& 1) == 0)
5726 ir
.ot
= ir
.dflag
+ OT_WORD
;
5728 if (i386_record_modrm (&ir
))
5733 if (opcode
== 0xc6 || opcode
== 0xc7)
5734 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
5735 if (i386_record_lea_modrm (&ir
))
5740 if (opcode
== 0xc6 || opcode
== 0xc7)
5742 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5744 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5748 case 0x8a: /* mov */
5750 if ((opcode
& 1) == 0)
5753 ir
.ot
= ir
.dflag
+ OT_WORD
;
5754 if (i386_record_modrm (&ir
))
5757 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5759 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5762 case 0x8c: /* mov seg */
5763 if (i386_record_modrm (&ir
))
5768 opcode
= opcode
<< 8 | ir
.modrm
;
5773 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5777 if (i386_record_lea_modrm (&ir
))
5782 case 0x8e: /* mov seg */
5783 if (i386_record_modrm (&ir
))
5788 regnum
= X86_RECORD_ES_REGNUM
;
5791 regnum
= X86_RECORD_SS_REGNUM
;
5794 regnum
= X86_RECORD_DS_REGNUM
;
5797 regnum
= X86_RECORD_FS_REGNUM
;
5800 regnum
= X86_RECORD_GS_REGNUM
;
5804 opcode
= opcode
<< 8 | ir
.modrm
;
5808 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum
);
5809 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5812 case 0x0fb6: /* movzbS */
5813 case 0x0fb7: /* movzwS */
5814 case 0x0fbe: /* movsbS */
5815 case 0x0fbf: /* movswS */
5816 if (i386_record_modrm (&ir
))
5818 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
5821 case 0x8d: /* lea */
5822 if (i386_record_modrm (&ir
))
5827 opcode
= opcode
<< 8 | ir
.modrm
;
5832 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5834 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5837 case 0xa0: /* mov EAX */
5840 case 0xd7: /* xlat */
5841 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5844 case 0xa2: /* mov EAX */
5846 if (ir
.override
>= 0)
5848 if (record_full_memory_query
)
5851 Process record ignores the memory change of instruction at address %s\n\
5852 because it can't get the value of the segment register.\n\
5853 Do you want to stop the program?"),
5854 paddress (gdbarch
, ir
.orig_addr
)))
5860 if ((opcode
& 1) == 0)
5863 ir
.ot
= ir
.dflag
+ OT_WORD
;
5866 if (record_read_memory (gdbarch
, ir
.addr
, buf
, 8))
5869 addr
= extract_unsigned_integer (buf
, 8, byte_order
);
5873 if (record_read_memory (gdbarch
, ir
.addr
, buf
, 4))
5876 addr
= extract_unsigned_integer (buf
, 4, byte_order
);
5880 if (record_read_memory (gdbarch
, ir
.addr
, buf
, 2))
5883 addr
= extract_unsigned_integer (buf
, 2, byte_order
);
5885 if (record_full_arch_list_add_mem (addr
, 1 << ir
.ot
))
5890 case 0xb0: /* mov R, Ib */
5898 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((ir
.regmap
[X86_RECORD_R8_REGNUM
])
5899 ? ((opcode
& 0x7) | ir
.rex_b
)
5900 : ((opcode
& 0x7) & 0x3));
5903 case 0xb8: /* mov R, Iv */
5911 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode
& 0x7) | ir
.rex_b
);
5914 case 0x91: /* xchg R, EAX */
5921 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5922 I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode
& 0x7);
5925 case 0x86: /* xchg Ev, Gv */
5927 if ((opcode
& 1) == 0)
5930 ir
.ot
= ir
.dflag
+ OT_WORD
;
5931 if (i386_record_modrm (&ir
))
5936 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5938 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5942 if (i386_record_lea_modrm (&ir
))
5946 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5948 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5951 case 0xc4: /* les Gv */
5952 case 0xc5: /* lds Gv */
5953 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5959 case 0x0fb2: /* lss Gv */
5960 case 0x0fb4: /* lfs Gv */
5961 case 0x0fb5: /* lgs Gv */
5962 if (i386_record_modrm (&ir
))
5970 opcode
= opcode
<< 8 | ir
.modrm
;
5975 case 0xc4: /* les Gv */
5976 regnum
= X86_RECORD_ES_REGNUM
;
5978 case 0xc5: /* lds Gv */
5979 regnum
= X86_RECORD_DS_REGNUM
;
5981 case 0x0fb2: /* lss Gv */
5982 regnum
= X86_RECORD_SS_REGNUM
;
5984 case 0x0fb4: /* lfs Gv */
5985 regnum
= X86_RECORD_FS_REGNUM
;
5987 case 0x0fb5: /* lgs Gv */
5988 regnum
= X86_RECORD_GS_REGNUM
;
5991 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum
);
5992 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
5993 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5996 case 0xc0: /* shifts */
6002 if ((opcode
& 1) == 0)
6005 ir
.ot
= ir
.dflag
+ OT_WORD
;
6006 if (i386_record_modrm (&ir
))
6008 if (ir
.mod
!= 3 && (opcode
== 0xd2 || opcode
== 0xd3))
6010 if (i386_record_lea_modrm (&ir
))
6016 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
6018 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
6020 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6027 if (i386_record_modrm (&ir
))
6031 if (record_full_arch_list_add_reg (ir
.regcache
, ir
.rm
))
6036 if (i386_record_lea_modrm (&ir
))
6041 case 0xd8: /* Floats. */
6049 if (i386_record_modrm (&ir
))
6051 ir
.reg
|= ((opcode
& 7) << 3);
6057 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
6065 /* For fcom, ficom nothing to do. */
6071 /* For fcomp, ficomp pop FPU stack, store all. */
6072 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
6099 /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul,
6100 fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension
6101 of code, always affects st(0) register. */
6102 if (i386_record_floats (gdbarch
, &ir
, I387_ST0_REGNUM (tdep
)))
6126 /* Handling fld, fild. */
6127 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
6131 switch (ir
.reg
>> 4)
6134 if (record_full_arch_list_add_mem (addr64
, 4))
6138 if (record_full_arch_list_add_mem (addr64
, 8))
6144 if (record_full_arch_list_add_mem (addr64
, 2))
6150 switch (ir
.reg
>> 4)
6153 if (record_full_arch_list_add_mem (addr64
, 4))
6155 if (3 == (ir
.reg
& 7))
6157 /* For fstp m32fp. */
6158 if (i386_record_floats (gdbarch
, &ir
,
6159 I386_SAVE_FPU_REGS
))
6164 if (record_full_arch_list_add_mem (addr64
, 4))
6166 if ((3 == (ir
.reg
& 7))
6167 || (5 == (ir
.reg
& 7))
6168 || (7 == (ir
.reg
& 7)))
6170 /* For fstp insn. */
6171 if (i386_record_floats (gdbarch
, &ir
,
6172 I386_SAVE_FPU_REGS
))
6177 if (record_full_arch_list_add_mem (addr64
, 8))
6179 if (3 == (ir
.reg
& 7))
6181 /* For fstp m64fp. */
6182 if (i386_record_floats (gdbarch
, &ir
,
6183 I386_SAVE_FPU_REGS
))
6188 if ((3 <= (ir
.reg
& 7)) && (6 <= (ir
.reg
& 7)))
6190 /* For fistp, fbld, fild, fbstp. */
6191 if (i386_record_floats (gdbarch
, &ir
,
6192 I386_SAVE_FPU_REGS
))
6197 if (record_full_arch_list_add_mem (addr64
, 2))
6206 if (i386_record_floats (gdbarch
, &ir
,
6207 I386_SAVE_FPU_ENV_REG_STACK
))
6212 if (i386_record_floats (gdbarch
, &ir
, I387_FCTRL_REGNUM (tdep
)))
6217 if (i386_record_floats (gdbarch
, &ir
,
6218 I386_SAVE_FPU_ENV_REG_STACK
))
6224 if (record_full_arch_list_add_mem (addr64
, 28))
6229 if (record_full_arch_list_add_mem (addr64
, 14))
6235 if (record_full_arch_list_add_mem (addr64
, 2))
6237 /* Insn fstp, fbstp. */
6238 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
6243 if (record_full_arch_list_add_mem (addr64
, 10))
6249 if (record_full_arch_list_add_mem (addr64
, 28))
6255 if (record_full_arch_list_add_mem (addr64
, 14))
6259 if (record_full_arch_list_add_mem (addr64
, 80))
6262 if (i386_record_floats (gdbarch
, &ir
,
6263 I386_SAVE_FPU_ENV_REG_STACK
))
6267 if (record_full_arch_list_add_mem (addr64
, 8))
6270 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
6275 opcode
= opcode
<< 8 | ir
.modrm
;
6280 /* Opcode is an extension of modR/M byte. */
6286 if (i386_record_floats (gdbarch
, &ir
, I387_ST0_REGNUM (tdep
)))
6290 if (0x0c == (ir
.modrm
>> 4))
6292 if ((ir
.modrm
& 0x0f) <= 7)
6294 if (i386_record_floats (gdbarch
, &ir
,
6295 I386_SAVE_FPU_REGS
))
6300 if (i386_record_floats (gdbarch
, &ir
,
6301 I387_ST0_REGNUM (tdep
)))
6303 /* If only st(0) is changing, then we have already
6305 if ((ir
.modrm
& 0x0f) - 0x08)
6307 if (i386_record_floats (gdbarch
, &ir
,
6308 I387_ST0_REGNUM (tdep
) +
6309 ((ir
.modrm
& 0x0f) - 0x08)))
6327 if (i386_record_floats (gdbarch
, &ir
,
6328 I387_ST0_REGNUM (tdep
)))
6346 if (i386_record_floats (gdbarch
, &ir
,
6347 I386_SAVE_FPU_REGS
))
6351 if (i386_record_floats (gdbarch
, &ir
,
6352 I387_ST0_REGNUM (tdep
)))
6354 if (i386_record_floats (gdbarch
, &ir
,
6355 I387_ST0_REGNUM (tdep
) + 1))
6362 if (0xe9 == ir
.modrm
)
6364 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
6367 else if ((0x0c == ir
.modrm
>> 4) || (0x0d == ir
.modrm
>> 4))
6369 if (i386_record_floats (gdbarch
, &ir
,
6370 I387_ST0_REGNUM (tdep
)))
6372 if (((ir
.modrm
& 0x0f) > 0) && ((ir
.modrm
& 0x0f) <= 7))
6374 if (i386_record_floats (gdbarch
, &ir
,
6375 I387_ST0_REGNUM (tdep
) +
6379 else if ((ir
.modrm
& 0x0f) - 0x08)
6381 if (i386_record_floats (gdbarch
, &ir
,
6382 I387_ST0_REGNUM (tdep
) +
6383 ((ir
.modrm
& 0x0f) - 0x08)))
6389 if (0xe3 == ir
.modrm
)
6391 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_ENV
))
6394 else if ((0x0c == ir
.modrm
>> 4) || (0x0d == ir
.modrm
>> 4))
6396 if (i386_record_floats (gdbarch
, &ir
,
6397 I387_ST0_REGNUM (tdep
)))
6399 if (((ir
.modrm
& 0x0f) > 0) && ((ir
.modrm
& 0x0f) <= 7))
6401 if (i386_record_floats (gdbarch
, &ir
,
6402 I387_ST0_REGNUM (tdep
) +
6406 else if ((ir
.modrm
& 0x0f) - 0x08)
6408 if (i386_record_floats (gdbarch
, &ir
,
6409 I387_ST0_REGNUM (tdep
) +
6410 ((ir
.modrm
& 0x0f) - 0x08)))
6416 if ((0x0c == ir
.modrm
>> 4)
6417 || (0x0d == ir
.modrm
>> 4)
6418 || (0x0f == ir
.modrm
>> 4))
6420 if ((ir
.modrm
& 0x0f) <= 7)
6422 if (i386_record_floats (gdbarch
, &ir
,
6423 I387_ST0_REGNUM (tdep
) +
6429 if (i386_record_floats (gdbarch
, &ir
,
6430 I387_ST0_REGNUM (tdep
) +
6431 ((ir
.modrm
& 0x0f) - 0x08)))
6437 if (0x0c == ir
.modrm
>> 4)
6439 if (i386_record_floats (gdbarch
, &ir
,
6440 I387_FTAG_REGNUM (tdep
)))
6443 else if ((0x0d == ir
.modrm
>> 4) || (0x0e == ir
.modrm
>> 4))
6445 if ((ir
.modrm
& 0x0f) <= 7)
6447 if (i386_record_floats (gdbarch
, &ir
,
6448 I387_ST0_REGNUM (tdep
) +
6454 if (i386_record_floats (gdbarch
, &ir
,
6455 I386_SAVE_FPU_REGS
))
6461 if ((0x0c == ir
.modrm
>> 4)
6462 || (0x0e == ir
.modrm
>> 4)
6463 || (0x0f == ir
.modrm
>> 4)
6464 || (0xd9 == ir
.modrm
))
6466 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
6471 if (0xe0 == ir
.modrm
)
6473 if (record_full_arch_list_add_reg (ir
.regcache
,
6477 else if ((0x0f == ir
.modrm
>> 4) || (0x0e == ir
.modrm
>> 4))
6479 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
6487 case 0xa4: /* movsS */
6489 case 0xaa: /* stosS */
6491 case 0x6c: /* insS */
6493 regcache_raw_read_unsigned (ir
.regcache
,
6494 ir
.regmap
[X86_RECORD_RECX_REGNUM
],
6500 if ((opcode
& 1) == 0)
6503 ir
.ot
= ir
.dflag
+ OT_WORD
;
6504 regcache_raw_read_unsigned (ir
.regcache
,
6505 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
6508 regcache_raw_read_unsigned (ir
.regcache
,
6509 ir
.regmap
[X86_RECORD_ES_REGNUM
],
6511 regcache_raw_read_unsigned (ir
.regcache
,
6512 ir
.regmap
[X86_RECORD_DS_REGNUM
],
6514 if (ir
.aflag
&& (es
!= ds
))
6516 /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */
6517 if (record_full_memory_query
)
6520 Process record ignores the memory change of instruction at address %s\n\
6521 because it can't get the value of the segment register.\n\
6522 Do you want to stop the program?"),
6523 paddress (gdbarch
, ir
.orig_addr
)))
6529 if (record_full_arch_list_add_mem (addr
, 1 << ir
.ot
))
6533 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
6534 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6535 if (opcode
== 0xa4 || opcode
== 0xa5)
6536 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
6537 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
6538 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6542 case 0xa6: /* cmpsS */
6544 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
6545 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
6546 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
6547 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6548 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6551 case 0xac: /* lodsS */
6553 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6554 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
6555 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
6556 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6557 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6560 case 0xae: /* scasS */
6562 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
6563 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
6564 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6565 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6568 case 0x6e: /* outsS */
6570 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
6571 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
6572 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6573 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6576 case 0xe4: /* port I/O */
6580 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6581 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6591 case 0xc2: /* ret im */
6592 case 0xc3: /* ret */
6593 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
6594 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6597 case 0xca: /* lret im */
6598 case 0xcb: /* lret */
6599 case 0xcf: /* iret */
6600 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
6601 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
6602 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6605 case 0xe8: /* call im */
6606 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
6608 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
6612 case 0x9a: /* lcall im */
6613 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6618 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
6619 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
6623 case 0xe9: /* jmp im */
6624 case 0xea: /* ljmp im */
6625 case 0xeb: /* jmp Jb */
6626 case 0x70: /* jcc Jb */
6642 case 0x0f80: /* jcc Jv */
6660 case 0x0f90: /* setcc Gv */
6676 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6678 if (i386_record_modrm (&ir
))
6681 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rex_b
? (ir
.rm
| ir
.rex_b
)
6685 if (i386_record_lea_modrm (&ir
))
6690 case 0x0f40: /* cmov Gv, Ev */
6706 if (i386_record_modrm (&ir
))
6709 if (ir
.dflag
== OT_BYTE
)
6711 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
6715 case 0x9c: /* pushf */
6716 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6717 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
6719 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
6723 case 0x9d: /* popf */
6724 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
6725 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6728 case 0x9e: /* sahf */
6729 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6735 case 0xf5: /* cmc */
6736 case 0xf8: /* clc */
6737 case 0xf9: /* stc */
6738 case 0xfc: /* cld */
6739 case 0xfd: /* std */
6740 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6743 case 0x9f: /* lahf */
6744 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6749 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6750 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6753 /* bit operations */
6754 case 0x0fba: /* bt/bts/btr/btc Gv, im */
6755 ir
.ot
= ir
.dflag
+ OT_WORD
;
6756 if (i386_record_modrm (&ir
))
6761 opcode
= opcode
<< 8 | ir
.modrm
;
6767 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6770 if (i386_record_lea_modrm (&ir
))
6774 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6777 case 0x0fa3: /* bt Gv, Ev */
6778 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6781 case 0x0fab: /* bts */
6782 case 0x0fb3: /* btr */
6783 case 0x0fbb: /* btc */
6784 ir
.ot
= ir
.dflag
+ OT_WORD
;
6785 if (i386_record_modrm (&ir
))
6788 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6792 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
6794 regcache_raw_read_unsigned (ir
.regcache
,
6795 ir
.regmap
[ir
.reg
| rex_r
],
6800 addr64
+= ((int16_t) addr
>> 4) << 4;
6803 addr64
+= ((int32_t) addr
>> 5) << 5;
6806 addr64
+= ((int64_t) addr
>> 6) << 6;
6809 if (record_full_arch_list_add_mem (addr64
, 1 << ir
.ot
))
6811 if (i386_record_lea_modrm (&ir
))
6814 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6817 case 0x0fbc: /* bsf */
6818 case 0x0fbd: /* bsr */
6819 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
6820 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6824 case 0x27: /* daa */
6825 case 0x2f: /* das */
6826 case 0x37: /* aaa */
6827 case 0x3f: /* aas */
6828 case 0xd4: /* aam */
6829 case 0xd5: /* aad */
6830 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6835 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6836 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6840 case 0x90: /* nop */
6841 if (prefixes
& PREFIX_LOCK
)
6848 case 0x9b: /* fwait */
6849 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
6851 opcode
= (uint32_t) opcode8
;
6857 case 0xcc: /* int3 */
6858 printf_unfiltered (_("Process record does not support instruction "
6865 case 0xcd: /* int */
6869 if (record_read_memory (gdbarch
, ir
.addr
, &interrupt
, 1))
6872 if (interrupt
!= 0x80
6873 || tdep
->i386_intx80_record
== NULL
)
6875 printf_unfiltered (_("Process record does not support "
6876 "instruction int 0x%02x.\n"),
6881 ret
= tdep
->i386_intx80_record (ir
.regcache
);
6888 case 0xce: /* into */
6889 printf_unfiltered (_("Process record does not support "
6890 "instruction into.\n"));
6895 case 0xfa: /* cli */
6896 case 0xfb: /* sti */
6899 case 0x62: /* bound */
6900 printf_unfiltered (_("Process record does not support "
6901 "instruction bound.\n"));
6906 case 0x0fc8: /* bswap reg */
6914 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode
& 7) | ir
.rex_b
);
6917 case 0xd6: /* salc */
6918 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6923 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6924 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6927 case 0xe0: /* loopnz */
6928 case 0xe1: /* loopz */
6929 case 0xe2: /* loop */
6930 case 0xe3: /* jecxz */
6931 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6932 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6935 case 0x0f30: /* wrmsr */
6936 printf_unfiltered (_("Process record does not support "
6937 "instruction wrmsr.\n"));
6942 case 0x0f32: /* rdmsr */
6943 printf_unfiltered (_("Process record does not support "
6944 "instruction rdmsr.\n"));
6949 case 0x0f31: /* rdtsc */
6950 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6951 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
6954 case 0x0f34: /* sysenter */
6957 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6962 if (tdep
->i386_sysenter_record
== NULL
)
6964 printf_unfiltered (_("Process record does not support "
6965 "instruction sysenter.\n"));
6969 ret
= tdep
->i386_sysenter_record (ir
.regcache
);
6975 case 0x0f35: /* sysexit */
6976 printf_unfiltered (_("Process record does not support "
6977 "instruction sysexit.\n"));
6982 case 0x0f05: /* syscall */
6985 if (tdep
->i386_syscall_record
== NULL
)
6987 printf_unfiltered (_("Process record does not support "
6988 "instruction syscall.\n"));
6992 ret
= tdep
->i386_syscall_record (ir
.regcache
);
6998 case 0x0f07: /* sysret */
6999 printf_unfiltered (_("Process record does not support "
7000 "instruction sysret.\n"));
7005 case 0x0fa2: /* cpuid */
7006 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
7007 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
7008 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
7009 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM
);
7012 case 0xf4: /* hlt */
7013 printf_unfiltered (_("Process record does not support "
7014 "instruction hlt.\n"));
7020 if (i386_record_modrm (&ir
))
7027 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
7031 if (i386_record_lea_modrm (&ir
))
7040 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7044 opcode
= opcode
<< 8 | ir
.modrm
;
7051 if (i386_record_modrm (&ir
))
7062 opcode
= opcode
<< 8 | ir
.modrm
;
7065 if (ir
.override
>= 0)
7067 if (record_full_memory_query
)
7070 Process record ignores the memory change of instruction at address %s\n\
7071 because it can't get the value of the segment register.\n\
7072 Do you want to stop the program?"),
7073 paddress (gdbarch
, ir
.orig_addr
)))
7079 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
7081 if (record_full_arch_list_add_mem (addr64
, 2))
7084 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
7086 if (record_full_arch_list_add_mem (addr64
, 8))
7091 if (record_full_arch_list_add_mem (addr64
, 4))
7102 case 0: /* monitor */
7105 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7109 opcode
= opcode
<< 8 | ir
.modrm
;
7117 if (ir
.override
>= 0)
7119 if (record_full_memory_query
)
7122 Process record ignores the memory change of instruction at address %s\n\
7123 because it can't get the value of the segment register.\n\
7124 Do you want to stop the program?"),
7125 paddress (gdbarch
, ir
.orig_addr
)))
7133 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
7135 if (record_full_arch_list_add_mem (addr64
, 2))
7138 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
7140 if (record_full_arch_list_add_mem (addr64
, 8))
7145 if (record_full_arch_list_add_mem (addr64
, 4))
7157 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
7158 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
7162 else if (ir
.rm
== 1)
7170 opcode
= opcode
<< 8 | ir
.modrm
;
7177 if (record_full_arch_list_add_reg (ir
.regcache
, ir
.rm
| ir
.rex_b
))
7183 if (i386_record_lea_modrm (&ir
))
7186 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7189 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7191 case 7: /* invlpg */
7194 if (ir
.rm
== 0 && ir
.regmap
[X86_RECORD_R8_REGNUM
])
7195 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM
);
7199 opcode
= opcode
<< 8 | ir
.modrm
;
7204 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7208 opcode
= opcode
<< 8 | ir
.modrm
;
7214 case 0x0f08: /* invd */
7215 case 0x0f09: /* wbinvd */
7218 case 0x63: /* arpl */
7219 if (i386_record_modrm (&ir
))
7221 if (ir
.mod
== 3 || ir
.regmap
[X86_RECORD_R8_REGNUM
])
7223 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.regmap
[X86_RECORD_R8_REGNUM
]
7224 ? (ir
.reg
| rex_r
) : ir
.rm
);
7228 ir
.ot
= ir
.dflag
? OT_LONG
: OT_WORD
;
7229 if (i386_record_lea_modrm (&ir
))
7232 if (!ir
.regmap
[X86_RECORD_R8_REGNUM
])
7233 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7236 case 0x0f02: /* lar */
7237 case 0x0f03: /* lsl */
7238 if (i386_record_modrm (&ir
))
7240 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
7241 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7245 if (i386_record_modrm (&ir
))
7247 if (ir
.mod
== 3 && ir
.reg
== 3)
7250 opcode
= opcode
<< 8 | ir
.modrm
;
7262 /* nop (multi byte) */
7265 case 0x0f20: /* mov reg, crN */
7266 case 0x0f22: /* mov crN, reg */
7267 if (i386_record_modrm (&ir
))
7269 if ((ir
.modrm
& 0xc0) != 0xc0)
7272 opcode
= opcode
<< 8 | ir
.modrm
;
7283 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7285 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
7289 opcode
= opcode
<< 8 | ir
.modrm
;
7295 case 0x0f21: /* mov reg, drN */
7296 case 0x0f23: /* mov drN, reg */
7297 if (i386_record_modrm (&ir
))
7299 if ((ir
.modrm
& 0xc0) != 0xc0 || ir
.reg
== 4
7300 || ir
.reg
== 5 || ir
.reg
>= 8)
7303 opcode
= opcode
<< 8 | ir
.modrm
;
7307 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7309 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
7312 case 0x0f06: /* clts */
7313 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7316 /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */
7318 case 0x0f0d: /* 3DNow! prefetch */
7321 case 0x0f0e: /* 3DNow! femms */
7322 case 0x0f77: /* emms */
7323 if (i386_fpc_regnum_p (gdbarch
, I387_FTAG_REGNUM(tdep
)))
7325 record_full_arch_list_add_reg (ir
.regcache
, I387_FTAG_REGNUM(tdep
));
7328 case 0x0f0f: /* 3DNow! data */
7329 if (i386_record_modrm (&ir
))
7331 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
7336 case 0x0c: /* 3DNow! pi2fw */
7337 case 0x0d: /* 3DNow! pi2fd */
7338 case 0x1c: /* 3DNow! pf2iw */
7339 case 0x1d: /* 3DNow! pf2id */
7340 case 0x8a: /* 3DNow! pfnacc */
7341 case 0x8e: /* 3DNow! pfpnacc */
7342 case 0x90: /* 3DNow! pfcmpge */
7343 case 0x94: /* 3DNow! pfmin */
7344 case 0x96: /* 3DNow! pfrcp */
7345 case 0x97: /* 3DNow! pfrsqrt */
7346 case 0x9a: /* 3DNow! pfsub */
7347 case 0x9e: /* 3DNow! pfadd */
7348 case 0xa0: /* 3DNow! pfcmpgt */
7349 case 0xa4: /* 3DNow! pfmax */
7350 case 0xa6: /* 3DNow! pfrcpit1 */
7351 case 0xa7: /* 3DNow! pfrsqit1 */
7352 case 0xaa: /* 3DNow! pfsubr */
7353 case 0xae: /* 3DNow! pfacc */
7354 case 0xb0: /* 3DNow! pfcmpeq */
7355 case 0xb4: /* 3DNow! pfmul */
7356 case 0xb6: /* 3DNow! pfrcpit2 */
7357 case 0xb7: /* 3DNow! pmulhrw */
7358 case 0xbb: /* 3DNow! pswapd */
7359 case 0xbf: /* 3DNow! pavgusb */
7360 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.reg
))
7361 goto no_support_3dnow_data
;
7362 record_full_arch_list_add_reg (ir
.regcache
, ir
.reg
);
7366 no_support_3dnow_data
:
7367 opcode
= (opcode
<< 8) | opcode8
;
7373 case 0x0faa: /* rsm */
7374 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7375 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
7376 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
7377 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
7378 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM
);
7379 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
7380 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
7381 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
7382 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
7386 if (i386_record_modrm (&ir
))
7390 case 0: /* fxsave */
7394 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7395 if (i386_record_lea_modrm_addr (&ir
, &tmpu64
))
7397 if (record_full_arch_list_add_mem (tmpu64
, 512))
7402 case 1: /* fxrstor */
7406 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7408 for (i
= I387_MM0_REGNUM (tdep
);
7409 i386_mmx_regnum_p (gdbarch
, i
); i
++)
7410 record_full_arch_list_add_reg (ir
.regcache
, i
);
7412 for (i
= I387_XMM0_REGNUM (tdep
);
7413 i386_xmm_regnum_p (gdbarch
, i
); i
++)
7414 record_full_arch_list_add_reg (ir
.regcache
, i
);
7416 if (i386_mxcsr_regnum_p (gdbarch
, I387_MXCSR_REGNUM(tdep
)))
7417 record_full_arch_list_add_reg (ir
.regcache
,
7418 I387_MXCSR_REGNUM(tdep
));
7420 for (i
= I387_ST0_REGNUM (tdep
);
7421 i386_fp_regnum_p (gdbarch
, i
); i
++)
7422 record_full_arch_list_add_reg (ir
.regcache
, i
);
7424 for (i
= I387_FCTRL_REGNUM (tdep
);
7425 i386_fpc_regnum_p (gdbarch
, i
); i
++)
7426 record_full_arch_list_add_reg (ir
.regcache
, i
);
7430 case 2: /* ldmxcsr */
7431 if (!i386_mxcsr_regnum_p (gdbarch
, I387_MXCSR_REGNUM(tdep
)))
7433 record_full_arch_list_add_reg (ir
.regcache
, I387_MXCSR_REGNUM(tdep
));
7436 case 3: /* stmxcsr */
7438 if (i386_record_lea_modrm (&ir
))
7442 case 5: /* lfence */
7443 case 6: /* mfence */
7444 case 7: /* sfence clflush */
7448 opcode
= (opcode
<< 8) | ir
.modrm
;
7454 case 0x0fc3: /* movnti */
7455 ir
.ot
= (ir
.dflag
== 2) ? OT_QUAD
: OT_LONG
;
7456 if (i386_record_modrm (&ir
))
7461 if (i386_record_lea_modrm (&ir
))
7465 /* Add prefix to opcode. */
7580 /* Mask out PREFIX_ADDR. */
7581 switch ((prefixes
& ~PREFIX_ADDR
))
7593 reswitch_prefix_add
:
7601 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
7604 opcode
= (uint32_t) opcode8
| opcode
<< 8;
7605 goto reswitch_prefix_add
;
7608 case 0x0f10: /* movups */
7609 case 0x660f10: /* movupd */
7610 case 0xf30f10: /* movss */
7611 case 0xf20f10: /* movsd */
7612 case 0x0f12: /* movlps */
7613 case 0x660f12: /* movlpd */
7614 case 0xf30f12: /* movsldup */
7615 case 0xf20f12: /* movddup */
7616 case 0x0f14: /* unpcklps */
7617 case 0x660f14: /* unpcklpd */
7618 case 0x0f15: /* unpckhps */
7619 case 0x660f15: /* unpckhpd */
7620 case 0x0f16: /* movhps */
7621 case 0x660f16: /* movhpd */
7622 case 0xf30f16: /* movshdup */
7623 case 0x0f28: /* movaps */
7624 case 0x660f28: /* movapd */
7625 case 0x0f2a: /* cvtpi2ps */
7626 case 0x660f2a: /* cvtpi2pd */
7627 case 0xf30f2a: /* cvtsi2ss */
7628 case 0xf20f2a: /* cvtsi2sd */
7629 case 0x0f2c: /* cvttps2pi */
7630 case 0x660f2c: /* cvttpd2pi */
7631 case 0x0f2d: /* cvtps2pi */
7632 case 0x660f2d: /* cvtpd2pi */
7633 case 0x660f3800: /* pshufb */
7634 case 0x660f3801: /* phaddw */
7635 case 0x660f3802: /* phaddd */
7636 case 0x660f3803: /* phaddsw */
7637 case 0x660f3804: /* pmaddubsw */
7638 case 0x660f3805: /* phsubw */
7639 case 0x660f3806: /* phsubd */
7640 case 0x660f3807: /* phsubsw */
7641 case 0x660f3808: /* psignb */
7642 case 0x660f3809: /* psignw */
7643 case 0x660f380a: /* psignd */
7644 case 0x660f380b: /* pmulhrsw */
7645 case 0x660f3810: /* pblendvb */
7646 case 0x660f3814: /* blendvps */
7647 case 0x660f3815: /* blendvpd */
7648 case 0x660f381c: /* pabsb */
7649 case 0x660f381d: /* pabsw */
7650 case 0x660f381e: /* pabsd */
7651 case 0x660f3820: /* pmovsxbw */
7652 case 0x660f3821: /* pmovsxbd */
7653 case 0x660f3822: /* pmovsxbq */
7654 case 0x660f3823: /* pmovsxwd */
7655 case 0x660f3824: /* pmovsxwq */
7656 case 0x660f3825: /* pmovsxdq */
7657 case 0x660f3828: /* pmuldq */
7658 case 0x660f3829: /* pcmpeqq */
7659 case 0x660f382a: /* movntdqa */
7660 case 0x660f3a08: /* roundps */
7661 case 0x660f3a09: /* roundpd */
7662 case 0x660f3a0a: /* roundss */
7663 case 0x660f3a0b: /* roundsd */
7664 case 0x660f3a0c: /* blendps */
7665 case 0x660f3a0d: /* blendpd */
7666 case 0x660f3a0e: /* pblendw */
7667 case 0x660f3a0f: /* palignr */
7668 case 0x660f3a20: /* pinsrb */
7669 case 0x660f3a21: /* insertps */
7670 case 0x660f3a22: /* pinsrd pinsrq */
7671 case 0x660f3a40: /* dpps */
7672 case 0x660f3a41: /* dppd */
7673 case 0x660f3a42: /* mpsadbw */
7674 case 0x660f3a60: /* pcmpestrm */
7675 case 0x660f3a61: /* pcmpestri */
7676 case 0x660f3a62: /* pcmpistrm */
7677 case 0x660f3a63: /* pcmpistri */
7678 case 0x0f51: /* sqrtps */
7679 case 0x660f51: /* sqrtpd */
7680 case 0xf20f51: /* sqrtsd */
7681 case 0xf30f51: /* sqrtss */
7682 case 0x0f52: /* rsqrtps */
7683 case 0xf30f52: /* rsqrtss */
7684 case 0x0f53: /* rcpps */
7685 case 0xf30f53: /* rcpss */
7686 case 0x0f54: /* andps */
7687 case 0x660f54: /* andpd */
7688 case 0x0f55: /* andnps */
7689 case 0x660f55: /* andnpd */
7690 case 0x0f56: /* orps */
7691 case 0x660f56: /* orpd */
7692 case 0x0f57: /* xorps */
7693 case 0x660f57: /* xorpd */
7694 case 0x0f58: /* addps */
7695 case 0x660f58: /* addpd */
7696 case 0xf20f58: /* addsd */
7697 case 0xf30f58: /* addss */
7698 case 0x0f59: /* mulps */
7699 case 0x660f59: /* mulpd */
7700 case 0xf20f59: /* mulsd */
7701 case 0xf30f59: /* mulss */
7702 case 0x0f5a: /* cvtps2pd */
7703 case 0x660f5a: /* cvtpd2ps */
7704 case 0xf20f5a: /* cvtsd2ss */
7705 case 0xf30f5a: /* cvtss2sd */
7706 case 0x0f5b: /* cvtdq2ps */
7707 case 0x660f5b: /* cvtps2dq */
7708 case 0xf30f5b: /* cvttps2dq */
7709 case 0x0f5c: /* subps */
7710 case 0x660f5c: /* subpd */
7711 case 0xf20f5c: /* subsd */
7712 case 0xf30f5c: /* subss */
7713 case 0x0f5d: /* minps */
7714 case 0x660f5d: /* minpd */
7715 case 0xf20f5d: /* minsd */
7716 case 0xf30f5d: /* minss */
7717 case 0x0f5e: /* divps */
7718 case 0x660f5e: /* divpd */
7719 case 0xf20f5e: /* divsd */
7720 case 0xf30f5e: /* divss */
7721 case 0x0f5f: /* maxps */
7722 case 0x660f5f: /* maxpd */
7723 case 0xf20f5f: /* maxsd */
7724 case 0xf30f5f: /* maxss */
7725 case 0x660f60: /* punpcklbw */
7726 case 0x660f61: /* punpcklwd */
7727 case 0x660f62: /* punpckldq */
7728 case 0x660f63: /* packsswb */
7729 case 0x660f64: /* pcmpgtb */
7730 case 0x660f65: /* pcmpgtw */
7731 case 0x660f66: /* pcmpgtd */
7732 case 0x660f67: /* packuswb */
7733 case 0x660f68: /* punpckhbw */
7734 case 0x660f69: /* punpckhwd */
7735 case 0x660f6a: /* punpckhdq */
7736 case 0x660f6b: /* packssdw */
7737 case 0x660f6c: /* punpcklqdq */
7738 case 0x660f6d: /* punpckhqdq */
7739 case 0x660f6e: /* movd */
7740 case 0x660f6f: /* movdqa */
7741 case 0xf30f6f: /* movdqu */
7742 case 0x660f70: /* pshufd */
7743 case 0xf20f70: /* pshuflw */
7744 case 0xf30f70: /* pshufhw */
7745 case 0x660f74: /* pcmpeqb */
7746 case 0x660f75: /* pcmpeqw */
7747 case 0x660f76: /* pcmpeqd */
7748 case 0x660f7c: /* haddpd */
7749 case 0xf20f7c: /* haddps */
7750 case 0x660f7d: /* hsubpd */
7751 case 0xf20f7d: /* hsubps */
7752 case 0xf30f7e: /* movq */
7753 case 0x0fc2: /* cmpps */
7754 case 0x660fc2: /* cmppd */
7755 case 0xf20fc2: /* cmpsd */
7756 case 0xf30fc2: /* cmpss */
7757 case 0x660fc4: /* pinsrw */
7758 case 0x0fc6: /* shufps */
7759 case 0x660fc6: /* shufpd */
7760 case 0x660fd0: /* addsubpd */
7761 case 0xf20fd0: /* addsubps */
7762 case 0x660fd1: /* psrlw */
7763 case 0x660fd2: /* psrld */
7764 case 0x660fd3: /* psrlq */
7765 case 0x660fd4: /* paddq */
7766 case 0x660fd5: /* pmullw */
7767 case 0xf30fd6: /* movq2dq */
7768 case 0x660fd8: /* psubusb */
7769 case 0x660fd9: /* psubusw */
7770 case 0x660fda: /* pminub */
7771 case 0x660fdb: /* pand */
7772 case 0x660fdc: /* paddusb */
7773 case 0x660fdd: /* paddusw */
7774 case 0x660fde: /* pmaxub */
7775 case 0x660fdf: /* pandn */
7776 case 0x660fe0: /* pavgb */
7777 case 0x660fe1: /* psraw */
7778 case 0x660fe2: /* psrad */
7779 case 0x660fe3: /* pavgw */
7780 case 0x660fe4: /* pmulhuw */
7781 case 0x660fe5: /* pmulhw */
7782 case 0x660fe6: /* cvttpd2dq */
7783 case 0xf20fe6: /* cvtpd2dq */
7784 case 0xf30fe6: /* cvtdq2pd */
7785 case 0x660fe8: /* psubsb */
7786 case 0x660fe9: /* psubsw */
7787 case 0x660fea: /* pminsw */
7788 case 0x660feb: /* por */
7789 case 0x660fec: /* paddsb */
7790 case 0x660fed: /* paddsw */
7791 case 0x660fee: /* pmaxsw */
7792 case 0x660fef: /* pxor */
7793 case 0xf20ff0: /* lddqu */
7794 case 0x660ff1: /* psllw */
7795 case 0x660ff2: /* pslld */
7796 case 0x660ff3: /* psllq */
7797 case 0x660ff4: /* pmuludq */
7798 case 0x660ff5: /* pmaddwd */
7799 case 0x660ff6: /* psadbw */
7800 case 0x660ff8: /* psubb */
7801 case 0x660ff9: /* psubw */
7802 case 0x660ffa: /* psubd */
7803 case 0x660ffb: /* psubq */
7804 case 0x660ffc: /* paddb */
7805 case 0x660ffd: /* paddw */
7806 case 0x660ffe: /* paddd */
7807 if (i386_record_modrm (&ir
))
7810 if (!i386_xmm_regnum_p (gdbarch
, I387_XMM0_REGNUM (tdep
) + ir
.reg
))
7812 record_full_arch_list_add_reg (ir
.regcache
,
7813 I387_XMM0_REGNUM (tdep
) + ir
.reg
);
7814 if ((opcode
& 0xfffffffc) == 0x660f3a60)
7815 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7818 case 0x0f11: /* movups */
7819 case 0x660f11: /* movupd */
7820 case 0xf30f11: /* movss */
7821 case 0xf20f11: /* movsd */
7822 case 0x0f13: /* movlps */
7823 case 0x660f13: /* movlpd */
7824 case 0x0f17: /* movhps */
7825 case 0x660f17: /* movhpd */
7826 case 0x0f29: /* movaps */
7827 case 0x660f29: /* movapd */
7828 case 0x660f3a14: /* pextrb */
7829 case 0x660f3a15: /* pextrw */
7830 case 0x660f3a16: /* pextrd pextrq */
7831 case 0x660f3a17: /* extractps */
7832 case 0x660f7f: /* movdqa */
7833 case 0xf30f7f: /* movdqu */
7834 if (i386_record_modrm (&ir
))
7838 if (opcode
== 0x0f13 || opcode
== 0x660f13
7839 || opcode
== 0x0f17 || opcode
== 0x660f17)
7842 if (!i386_xmm_regnum_p (gdbarch
,
7843 I387_XMM0_REGNUM (tdep
) + ir
.rm
))
7845 record_full_arch_list_add_reg (ir
.regcache
,
7846 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
7868 if (i386_record_lea_modrm (&ir
))
7873 case 0x0f2b: /* movntps */
7874 case 0x660f2b: /* movntpd */
7875 case 0x0fe7: /* movntq */
7876 case 0x660fe7: /* movntdq */
7879 if (opcode
== 0x0fe7)
7883 if (i386_record_lea_modrm (&ir
))
7887 case 0xf30f2c: /* cvttss2si */
7888 case 0xf20f2c: /* cvttsd2si */
7889 case 0xf30f2d: /* cvtss2si */
7890 case 0xf20f2d: /* cvtsd2si */
7891 case 0xf20f38f0: /* crc32 */
7892 case 0xf20f38f1: /* crc32 */
7893 case 0x0f50: /* movmskps */
7894 case 0x660f50: /* movmskpd */
7895 case 0x0fc5: /* pextrw */
7896 case 0x660fc5: /* pextrw */
7897 case 0x0fd7: /* pmovmskb */
7898 case 0x660fd7: /* pmovmskb */
7899 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
7902 case 0x0f3800: /* pshufb */
7903 case 0x0f3801: /* phaddw */
7904 case 0x0f3802: /* phaddd */
7905 case 0x0f3803: /* phaddsw */
7906 case 0x0f3804: /* pmaddubsw */
7907 case 0x0f3805: /* phsubw */
7908 case 0x0f3806: /* phsubd */
7909 case 0x0f3807: /* phsubsw */
7910 case 0x0f3808: /* psignb */
7911 case 0x0f3809: /* psignw */
7912 case 0x0f380a: /* psignd */
7913 case 0x0f380b: /* pmulhrsw */
7914 case 0x0f381c: /* pabsb */
7915 case 0x0f381d: /* pabsw */
7916 case 0x0f381e: /* pabsd */
7917 case 0x0f382b: /* packusdw */
7918 case 0x0f3830: /* pmovzxbw */
7919 case 0x0f3831: /* pmovzxbd */
7920 case 0x0f3832: /* pmovzxbq */
7921 case 0x0f3833: /* pmovzxwd */
7922 case 0x0f3834: /* pmovzxwq */
7923 case 0x0f3835: /* pmovzxdq */
7924 case 0x0f3837: /* pcmpgtq */
7925 case 0x0f3838: /* pminsb */
7926 case 0x0f3839: /* pminsd */
7927 case 0x0f383a: /* pminuw */
7928 case 0x0f383b: /* pminud */
7929 case 0x0f383c: /* pmaxsb */
7930 case 0x0f383d: /* pmaxsd */
7931 case 0x0f383e: /* pmaxuw */
7932 case 0x0f383f: /* pmaxud */
7933 case 0x0f3840: /* pmulld */
7934 case 0x0f3841: /* phminposuw */
7935 case 0x0f3a0f: /* palignr */
7936 case 0x0f60: /* punpcklbw */
7937 case 0x0f61: /* punpcklwd */
7938 case 0x0f62: /* punpckldq */
7939 case 0x0f63: /* packsswb */
7940 case 0x0f64: /* pcmpgtb */
7941 case 0x0f65: /* pcmpgtw */
7942 case 0x0f66: /* pcmpgtd */
7943 case 0x0f67: /* packuswb */
7944 case 0x0f68: /* punpckhbw */
7945 case 0x0f69: /* punpckhwd */
7946 case 0x0f6a: /* punpckhdq */
7947 case 0x0f6b: /* packssdw */
7948 case 0x0f6e: /* movd */
7949 case 0x0f6f: /* movq */
7950 case 0x0f70: /* pshufw */
7951 case 0x0f74: /* pcmpeqb */
7952 case 0x0f75: /* pcmpeqw */
7953 case 0x0f76: /* pcmpeqd */
7954 case 0x0fc4: /* pinsrw */
7955 case 0x0fd1: /* psrlw */
7956 case 0x0fd2: /* psrld */
7957 case 0x0fd3: /* psrlq */
7958 case 0x0fd4: /* paddq */
7959 case 0x0fd5: /* pmullw */
7960 case 0xf20fd6: /* movdq2q */
7961 case 0x0fd8: /* psubusb */
7962 case 0x0fd9: /* psubusw */
7963 case 0x0fda: /* pminub */
7964 case 0x0fdb: /* pand */
7965 case 0x0fdc: /* paddusb */
7966 case 0x0fdd: /* paddusw */
7967 case 0x0fde: /* pmaxub */
7968 case 0x0fdf: /* pandn */
7969 case 0x0fe0: /* pavgb */
7970 case 0x0fe1: /* psraw */
7971 case 0x0fe2: /* psrad */
7972 case 0x0fe3: /* pavgw */
7973 case 0x0fe4: /* pmulhuw */
7974 case 0x0fe5: /* pmulhw */
7975 case 0x0fe8: /* psubsb */
7976 case 0x0fe9: /* psubsw */
7977 case 0x0fea: /* pminsw */
7978 case 0x0feb: /* por */
7979 case 0x0fec: /* paddsb */
7980 case 0x0fed: /* paddsw */
7981 case 0x0fee: /* pmaxsw */
7982 case 0x0fef: /* pxor */
7983 case 0x0ff1: /* psllw */
7984 case 0x0ff2: /* pslld */
7985 case 0x0ff3: /* psllq */
7986 case 0x0ff4: /* pmuludq */
7987 case 0x0ff5: /* pmaddwd */
7988 case 0x0ff6: /* psadbw */
7989 case 0x0ff8: /* psubb */
7990 case 0x0ff9: /* psubw */
7991 case 0x0ffa: /* psubd */
7992 case 0x0ffb: /* psubq */
7993 case 0x0ffc: /* paddb */
7994 case 0x0ffd: /* paddw */
7995 case 0x0ffe: /* paddd */
7996 if (i386_record_modrm (&ir
))
7998 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.reg
))
8000 record_full_arch_list_add_reg (ir
.regcache
,
8001 I387_MM0_REGNUM (tdep
) + ir
.reg
);
8004 case 0x0f71: /* psllw */
8005 case 0x0f72: /* pslld */
8006 case 0x0f73: /* psllq */
8007 if (i386_record_modrm (&ir
))
8009 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.rm
))
8011 record_full_arch_list_add_reg (ir
.regcache
,
8012 I387_MM0_REGNUM (tdep
) + ir
.rm
);
8015 case 0x660f71: /* psllw */
8016 case 0x660f72: /* pslld */
8017 case 0x660f73: /* psllq */
8018 if (i386_record_modrm (&ir
))
8021 if (!i386_xmm_regnum_p (gdbarch
, I387_XMM0_REGNUM (tdep
) + ir
.rm
))
8023 record_full_arch_list_add_reg (ir
.regcache
,
8024 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
8027 case 0x0f7e: /* movd */
8028 case 0x660f7e: /* movd */
8029 if (i386_record_modrm (&ir
))
8032 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
8039 if (i386_record_lea_modrm (&ir
))
8044 case 0x0f7f: /* movq */
8045 if (i386_record_modrm (&ir
))
8049 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.rm
))
8051 record_full_arch_list_add_reg (ir
.regcache
,
8052 I387_MM0_REGNUM (tdep
) + ir
.rm
);
8057 if (i386_record_lea_modrm (&ir
))
8062 case 0xf30fb8: /* popcnt */
8063 if (i386_record_modrm (&ir
))
8065 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
8066 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
8069 case 0x660fd6: /* movq */
8070 if (i386_record_modrm (&ir
))
8075 if (!i386_xmm_regnum_p (gdbarch
,
8076 I387_XMM0_REGNUM (tdep
) + ir
.rm
))
8078 record_full_arch_list_add_reg (ir
.regcache
,
8079 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
8084 if (i386_record_lea_modrm (&ir
))
8089 case 0x660f3817: /* ptest */
8090 case 0x0f2e: /* ucomiss */
8091 case 0x660f2e: /* ucomisd */
8092 case 0x0f2f: /* comiss */
8093 case 0x660f2f: /* comisd */
8094 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
8097 case 0x0ff7: /* maskmovq */
8098 regcache_raw_read_unsigned (ir
.regcache
,
8099 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
8101 if (record_full_arch_list_add_mem (addr
, 64))
8105 case 0x660ff7: /* maskmovdqu */
8106 regcache_raw_read_unsigned (ir
.regcache
,
8107 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
8109 if (record_full_arch_list_add_mem (addr
, 128))
8124 /* In the future, maybe still need to deal with need_dasm. */
8125 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM
);
8126 if (record_full_arch_list_add_end ())
8132 printf_unfiltered (_("Process record does not support instruction 0x%02x "
8133 "at address %s.\n"),
8134 (unsigned int) (opcode
),
8135 paddress (gdbarch
, ir
.orig_addr
));
8139 static const int i386_record_regmap
[] =
8141 I386_EAX_REGNUM
, I386_ECX_REGNUM
, I386_EDX_REGNUM
, I386_EBX_REGNUM
,
8142 I386_ESP_REGNUM
, I386_EBP_REGNUM
, I386_ESI_REGNUM
, I386_EDI_REGNUM
,
8143 0, 0, 0, 0, 0, 0, 0, 0,
8144 I386_EIP_REGNUM
, I386_EFLAGS_REGNUM
, I386_CS_REGNUM
, I386_SS_REGNUM
,
8145 I386_DS_REGNUM
, I386_ES_REGNUM
, I386_FS_REGNUM
, I386_GS_REGNUM
8148 /* Check that the given address appears suitable for a fast
8149 tracepoint, which on x86-64 means that we need an instruction of at
8150 least 5 bytes, so that we can overwrite it with a 4-byte-offset
8151 jump and not have to worry about program jumps to an address in the
8152 middle of the tracepoint jump. On x86, it may be possible to use
8153 4-byte jumps with a 2-byte offset to a trampoline located in the
8154 bottom 64 KiB of memory. Returns 1 if OK, and writes a size
8155 of instruction to replace, and 0 if not, plus an explanatory
8159 i386_fast_tracepoint_valid_at (struct gdbarch
*gdbarch
, CORE_ADDR addr
,
8164 /* Ask the target for the minimum instruction length supported. */
8165 jumplen
= target_get_min_fast_tracepoint_insn_len ();
8169 /* If the target does not support the get_min_fast_tracepoint_insn_len
8170 operation, assume that fast tracepoints will always be implemented
8171 using 4-byte relative jumps on both x86 and x86-64. */
8174 else if (jumplen
== 0)
8176 /* If the target does support get_min_fast_tracepoint_insn_len but
8177 returns zero, then the IPA has not loaded yet. In this case,
8178 we optimistically assume that truncated 2-byte relative jumps
8179 will be available on x86, and compensate later if this assumption
8180 turns out to be incorrect. On x86-64 architectures, 4-byte relative
8181 jumps will always be used. */
8182 jumplen
= (register_size (gdbarch
, 0) == 8) ? 5 : 4;
8185 /* Check for fit. */
8186 len
= gdb_insn_length (gdbarch
, addr
);
8190 /* Return a bit of target-specific detail to add to the caller's
8191 generic failure message. */
8193 *msg
= string_printf (_("; instruction is only %d bytes long, "
8194 "need at least %d bytes for the jump"),
8206 /* Return a floating-point format for a floating-point variable of
8207 length LEN in bits. If non-NULL, NAME is the name of its type.
8208 If no suitable type is found, return NULL. */
8210 static const struct floatformat
**
8211 i386_floatformat_for_type (struct gdbarch
*gdbarch
,
8212 const char *name
, int len
)
8214 if (len
== 128 && name
)
8215 if (strcmp (name
, "__float128") == 0
8216 || strcmp (name
, "_Float128") == 0
8217 || strcmp (name
, "complex _Float128") == 0
8218 || strcmp (name
, "complex(kind=16)") == 0
8219 || strcmp (name
, "quad complex") == 0
8220 || strcmp (name
, "real(kind=16)") == 0
8221 || strcmp (name
, "real*16") == 0)
8222 return floatformats_ia64_quad
;
8224 return default_floatformat_for_type (gdbarch
, name
, len
);
8228 i386_validate_tdesc_p (struct gdbarch_tdep
*tdep
,
8229 struct tdesc_arch_data
*tdesc_data
)
8231 const struct target_desc
*tdesc
= tdep
->tdesc
;
8232 const struct tdesc_feature
*feature_core
;
8234 const struct tdesc_feature
*feature_sse
, *feature_avx
, *feature_mpx
,
8235 *feature_avx512
, *feature_pkeys
, *feature_segments
;
8236 int i
, num_regs
, valid_p
;
8238 if (! tdesc_has_registers (tdesc
))
8241 /* Get core registers. */
8242 feature_core
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.core");
8243 if (feature_core
== NULL
)
8246 /* Get SSE registers. */
8247 feature_sse
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.sse");
8249 /* Try AVX registers. */
8250 feature_avx
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx");
8252 /* Try MPX registers. */
8253 feature_mpx
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.mpx");
8255 /* Try AVX512 registers. */
8256 feature_avx512
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx512");
8258 /* Try segment base registers. */
8259 feature_segments
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.segments");
8262 feature_pkeys
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.pkeys");
8266 /* The XCR0 bits. */
8269 /* AVX512 register description requires AVX register description. */
8273 tdep
->xcr0
= X86_XSTATE_AVX_AVX512_MASK
;
8275 /* It may have been set by OSABI initialization function. */
8276 if (tdep
->k0_regnum
< 0)
8278 tdep
->k_register_names
= i386_k_names
;
8279 tdep
->k0_regnum
= I386_K0_REGNUM
;
8282 for (i
= 0; i
< I387_NUM_K_REGS
; i
++)
8283 valid_p
&= tdesc_numbered_register (feature_avx512
, tdesc_data
,
8284 tdep
->k0_regnum
+ i
,
8287 if (tdep
->num_zmm_regs
== 0)
8289 tdep
->zmmh_register_names
= i386_zmmh_names
;
8290 tdep
->num_zmm_regs
= 8;
8291 tdep
->zmm0h_regnum
= I386_ZMM0H_REGNUM
;
8294 for (i
= 0; i
< tdep
->num_zmm_regs
; i
++)
8295 valid_p
&= tdesc_numbered_register (feature_avx512
, tdesc_data
,
8296 tdep
->zmm0h_regnum
+ i
,
8297 tdep
->zmmh_register_names
[i
]);
8299 for (i
= 0; i
< tdep
->num_xmm_avx512_regs
; i
++)
8300 valid_p
&= tdesc_numbered_register (feature_avx512
, tdesc_data
,
8301 tdep
->xmm16_regnum
+ i
,
8302 tdep
->xmm_avx512_register_names
[i
]);
8304 for (i
= 0; i
< tdep
->num_ymm_avx512_regs
; i
++)
8305 valid_p
&= tdesc_numbered_register (feature_avx512
, tdesc_data
,
8306 tdep
->ymm16h_regnum
+ i
,
8307 tdep
->ymm16h_register_names
[i
]);
8311 /* AVX register description requires SSE register description. */
8315 if (!feature_avx512
)
8316 tdep
->xcr0
= X86_XSTATE_AVX_MASK
;
8318 /* It may have been set by OSABI initialization function. */
8319 if (tdep
->num_ymm_regs
== 0)
8321 tdep
->ymmh_register_names
= i386_ymmh_names
;
8322 tdep
->num_ymm_regs
= 8;
8323 tdep
->ymm0h_regnum
= I386_YMM0H_REGNUM
;
8326 for (i
= 0; i
< tdep
->num_ymm_regs
; i
++)
8327 valid_p
&= tdesc_numbered_register (feature_avx
, tdesc_data
,
8328 tdep
->ymm0h_regnum
+ i
,
8329 tdep
->ymmh_register_names
[i
]);
8331 else if (feature_sse
)
8332 tdep
->xcr0
= X86_XSTATE_SSE_MASK
;
8335 tdep
->xcr0
= X86_XSTATE_X87_MASK
;
8336 tdep
->num_xmm_regs
= 0;
8339 num_regs
= tdep
->num_core_regs
;
8340 for (i
= 0; i
< num_regs
; i
++)
8341 valid_p
&= tdesc_numbered_register (feature_core
, tdesc_data
, i
,
8342 tdep
->register_names
[i
]);
8346 /* Need to include %mxcsr, so add one. */
8347 num_regs
+= tdep
->num_xmm_regs
+ 1;
8348 for (; i
< num_regs
; i
++)
8349 valid_p
&= tdesc_numbered_register (feature_sse
, tdesc_data
, i
,
8350 tdep
->register_names
[i
]);
8355 tdep
->xcr0
|= X86_XSTATE_MPX_MASK
;
8357 if (tdep
->bnd0r_regnum
< 0)
8359 tdep
->mpx_register_names
= i386_mpx_names
;
8360 tdep
->bnd0r_regnum
= I386_BND0R_REGNUM
;
8361 tdep
->bndcfgu_regnum
= I386_BNDCFGU_REGNUM
;
8364 for (i
= 0; i
< I387_NUM_MPX_REGS
; i
++)
8365 valid_p
&= tdesc_numbered_register (feature_mpx
, tdesc_data
,
8366 I387_BND0R_REGNUM (tdep
) + i
,
8367 tdep
->mpx_register_names
[i
]);
8370 if (feature_segments
)
8372 if (tdep
->fsbase_regnum
< 0)
8373 tdep
->fsbase_regnum
= I386_FSBASE_REGNUM
;
8374 valid_p
&= tdesc_numbered_register (feature_segments
, tdesc_data
,
8375 tdep
->fsbase_regnum
, "fs_base");
8376 valid_p
&= tdesc_numbered_register (feature_segments
, tdesc_data
,
8377 tdep
->fsbase_regnum
+ 1, "gs_base");
8382 tdep
->xcr0
|= X86_XSTATE_PKRU
;
8383 if (tdep
->pkru_regnum
< 0)
8385 tdep
->pkeys_register_names
= i386_pkeys_names
;
8386 tdep
->pkru_regnum
= I386_PKRU_REGNUM
;
8387 tdep
->num_pkeys_regs
= 1;
8390 for (i
= 0; i
< I387_NUM_PKEYS_REGS
; i
++)
8391 valid_p
&= tdesc_numbered_register (feature_pkeys
, tdesc_data
,
8392 I387_PKRU_REGNUM (tdep
) + i
,
8393 tdep
->pkeys_register_names
[i
]);
8401 /* Implement the type_align gdbarch function. */
8404 i386_type_align (struct gdbarch
*gdbarch
, struct type
*type
)
8406 type
= check_typedef (type
);
8408 if (gdbarch_ptr_bit (gdbarch
) == 32)
8410 if ((type
->code () == TYPE_CODE_INT
8411 || type
->code () == TYPE_CODE_FLT
)
8412 && TYPE_LENGTH (type
) > 4)
8415 /* Handle x86's funny long double. */
8416 if (type
->code () == TYPE_CODE_FLT
8417 && gdbarch_long_double_bit (gdbarch
) == TYPE_LENGTH (type
) * 8)
8425 /* Note: This is called for both i386 and amd64. */
8427 static struct gdbarch
*
8428 i386_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
8430 struct gdbarch_tdep
*tdep
;
8431 struct gdbarch
*gdbarch
;
8432 const struct target_desc
*tdesc
;
8438 /* If there is already a candidate, use it. */
8439 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
8441 return arches
->gdbarch
;
8443 /* Allocate space for the new architecture. Assume i386 for now. */
8444 tdep
= XCNEW (struct gdbarch_tdep
);
8445 gdbarch
= gdbarch_alloc (&info
, tdep
);
8447 /* General-purpose registers. */
8448 tdep
->gregset_reg_offset
= NULL
;
8449 tdep
->gregset_num_regs
= I386_NUM_GREGS
;
8450 tdep
->sizeof_gregset
= 0;
8452 /* Floating-point registers. */
8453 tdep
->sizeof_fpregset
= I387_SIZEOF_FSAVE
;
8454 tdep
->fpregset
= &i386_fpregset
;
8456 /* The default settings include the FPU registers, the MMX registers
8457 and the SSE registers. This can be overridden for a specific ABI
8458 by adjusting the members `st0_regnum', `mm0_regnum' and
8459 `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers
8460 will show up in the output of "info all-registers". */
8462 tdep
->st0_regnum
= I386_ST0_REGNUM
;
8464 /* I386_NUM_XREGS includes %mxcsr, so substract one. */
8465 tdep
->num_xmm_regs
= I386_NUM_XREGS
- 1;
8467 tdep
->jb_pc_offset
= -1;
8468 tdep
->struct_return
= pcc_struct_return
;
8469 tdep
->sigtramp_start
= 0;
8470 tdep
->sigtramp_end
= 0;
8471 tdep
->sigtramp_p
= i386_sigtramp_p
;
8472 tdep
->sigcontext_addr
= NULL
;
8473 tdep
->sc_reg_offset
= NULL
;
8474 tdep
->sc_pc_offset
= -1;
8475 tdep
->sc_sp_offset
= -1;
8477 tdep
->xsave_xcr0_offset
= -1;
8479 tdep
->record_regmap
= i386_record_regmap
;
8481 set_gdbarch_type_align (gdbarch
, i386_type_align
);
8483 /* The format used for `long double' on almost all i386 targets is
8484 the i387 extended floating-point format. In fact, of all targets
8485 in the GCC 2.95 tree, only OSF/1 does it different, and insists
8486 on having a `long double' that's not `long' at all. */
8487 set_gdbarch_long_double_format (gdbarch
, floatformats_i387_ext
);
8489 /* Although the i387 extended floating-point has only 80 significant
8490 bits, a `long double' actually takes up 96, probably to enforce
8492 set_gdbarch_long_double_bit (gdbarch
, 96);
8494 /* Support of bfloat16 format. */
8495 set_gdbarch_bfloat16_format (gdbarch
, floatformats_bfloat16
);
8497 /* Support for floating-point data type variants. */
8498 set_gdbarch_floatformat_for_type (gdbarch
, i386_floatformat_for_type
);
8500 /* Register numbers of various important registers. */
8501 set_gdbarch_sp_regnum (gdbarch
, I386_ESP_REGNUM
); /* %esp */
8502 set_gdbarch_pc_regnum (gdbarch
, I386_EIP_REGNUM
); /* %eip */
8503 set_gdbarch_ps_regnum (gdbarch
, I386_EFLAGS_REGNUM
); /* %eflags */
8504 set_gdbarch_fp0_regnum (gdbarch
, I386_ST0_REGNUM
); /* %st(0) */
8506 /* NOTE: kettenis/20040418: GCC does have two possible register
8507 numbering schemes on the i386: dbx and SVR4. These schemes
8508 differ in how they number %ebp, %esp, %eflags, and the
8509 floating-point registers, and are implemented by the arrays
8510 dbx_register_map[] and svr4_dbx_register_map in
8511 gcc/config/i386.c. GCC also defines a third numbering scheme in
8512 gcc/config/i386.c, which it designates as the "default" register
8513 map used in 64bit mode. This last register numbering scheme is
8514 implemented in dbx64_register_map, and is used for AMD64; see
8517 Currently, each GCC i386 target always uses the same register
8518 numbering scheme across all its supported debugging formats
8519 i.e. SDB (COFF), stabs and DWARF 2. This is because
8520 gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the
8521 DBX_REGISTER_NUMBER macro which is defined by each target's
8522 respective config header in a manner independent of the requested
8523 output debugging format.
8525 This does not match the arrangement below, which presumes that
8526 the SDB and stabs numbering schemes differ from the DWARF and
8527 DWARF 2 ones. The reason for this arrangement is that it is
8528 likely to get the numbering scheme for the target's
8529 default/native debug format right. For targets where GCC is the
8530 native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for
8531 targets where the native toolchain uses a different numbering
8532 scheme for a particular debug format (stabs-in-ELF on Solaris)
8533 the defaults below will have to be overridden, like
8534 i386_elf_init_abi() does. */
8536 /* Use the dbx register numbering scheme for stabs and COFF. */
8537 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
8538 set_gdbarch_sdb_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
8540 /* Use the SVR4 register numbering scheme for DWARF 2. */
8541 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, i386_svr4_dwarf_reg_to_regnum
);
8543 /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to
8544 be in use on any of the supported i386 targets. */
8546 set_gdbarch_print_float_info (gdbarch
, i387_print_float_info
);
8548 set_gdbarch_get_longjmp_target (gdbarch
, i386_get_longjmp_target
);
8550 /* Call dummy code. */
8551 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
8552 set_gdbarch_push_dummy_code (gdbarch
, i386_push_dummy_code
);
8553 set_gdbarch_push_dummy_call (gdbarch
, i386_push_dummy_call
);
8554 set_gdbarch_frame_align (gdbarch
, i386_frame_align
);
8556 set_gdbarch_convert_register_p (gdbarch
, i386_convert_register_p
);
8557 set_gdbarch_register_to_value (gdbarch
, i386_register_to_value
);
8558 set_gdbarch_value_to_register (gdbarch
, i386_value_to_register
);
8560 set_gdbarch_return_value (gdbarch
, i386_return_value
);
8562 set_gdbarch_skip_prologue (gdbarch
, i386_skip_prologue
);
8564 /* Stack grows downward. */
8565 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
8567 set_gdbarch_breakpoint_kind_from_pc (gdbarch
, i386_breakpoint::kind_from_pc
);
8568 set_gdbarch_sw_breakpoint_from_kind (gdbarch
, i386_breakpoint::bp_from_kind
);
8570 set_gdbarch_decr_pc_after_break (gdbarch
, 1);
8571 set_gdbarch_max_insn_length (gdbarch
, I386_MAX_INSN_LEN
);
8573 set_gdbarch_frame_args_skip (gdbarch
, 8);
8575 set_gdbarch_print_insn (gdbarch
, i386_print_insn
);
8577 set_gdbarch_dummy_id (gdbarch
, i386_dummy_id
);
8579 set_gdbarch_unwind_pc (gdbarch
, i386_unwind_pc
);
8581 /* Add the i386 register groups. */
8582 i386_add_reggroups (gdbarch
);
8583 tdep
->register_reggroup_p
= i386_register_reggroup_p
;
8585 /* Helper for function argument information. */
8586 set_gdbarch_fetch_pointer_argument (gdbarch
, i386_fetch_pointer_argument
);
8588 /* Hook the function epilogue frame unwinder. This unwinder is
8589 appended to the list first, so that it supercedes the DWARF
8590 unwinder in function epilogues (where the DWARF unwinder
8591 currently fails). */
8592 frame_unwind_append_unwinder (gdbarch
, &i386_epilogue_frame_unwind
);
8594 /* Hook in the DWARF CFI frame unwinder. This unwinder is appended
8595 to the list before the prologue-based unwinders, so that DWARF
8596 CFI info will be used if it is available. */
8597 dwarf2_append_unwinders (gdbarch
);
8599 frame_base_set_default (gdbarch
, &i386_frame_base
);
8601 /* Pseudo registers may be changed by amd64_init_abi. */
8602 set_gdbarch_pseudo_register_read_value (gdbarch
,
8603 i386_pseudo_register_read_value
);
8604 set_gdbarch_pseudo_register_write (gdbarch
, i386_pseudo_register_write
);
8605 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
8606 i386_ax_pseudo_register_collect
);
8608 set_tdesc_pseudo_register_type (gdbarch
, i386_pseudo_register_type
);
8609 set_tdesc_pseudo_register_name (gdbarch
, i386_pseudo_register_name
);
8611 /* Override the normal target description method to make the AVX
8612 upper halves anonymous. */
8613 set_gdbarch_register_name (gdbarch
, i386_register_name
);
8615 /* Even though the default ABI only includes general-purpose registers,
8616 floating-point registers and the SSE registers, we have to leave a
8617 gap for the upper AVX, MPX and AVX512 registers. */
8618 set_gdbarch_num_regs (gdbarch
, I386_NUM_REGS
);
8620 set_gdbarch_gnu_triplet_regexp (gdbarch
, i386_gnu_triplet_regexp
);
8622 /* Get the x86 target description from INFO. */
8623 tdesc
= info
.target_desc
;
8624 if (! tdesc_has_registers (tdesc
))
8625 tdesc
= i386_target_description (X86_XSTATE_SSE_MASK
, false);
8626 tdep
->tdesc
= tdesc
;
8628 tdep
->num_core_regs
= I386_NUM_GREGS
+ I387_NUM_REGS
;
8629 tdep
->register_names
= i386_register_names
;
8631 /* No upper YMM registers. */
8632 tdep
->ymmh_register_names
= NULL
;
8633 tdep
->ymm0h_regnum
= -1;
8635 /* No upper ZMM registers. */
8636 tdep
->zmmh_register_names
= NULL
;
8637 tdep
->zmm0h_regnum
= -1;
8639 /* No high XMM registers. */
8640 tdep
->xmm_avx512_register_names
= NULL
;
8641 tdep
->xmm16_regnum
= -1;
8643 /* No upper YMM16-31 registers. */
8644 tdep
->ymm16h_register_names
= NULL
;
8645 tdep
->ymm16h_regnum
= -1;
8647 tdep
->num_byte_regs
= 8;
8648 tdep
->num_word_regs
= 8;
8649 tdep
->num_dword_regs
= 0;
8650 tdep
->num_mmx_regs
= 8;
8651 tdep
->num_ymm_regs
= 0;
8653 /* No MPX registers. */
8654 tdep
->bnd0r_regnum
= -1;
8655 tdep
->bndcfgu_regnum
= -1;
8657 /* No AVX512 registers. */
8658 tdep
->k0_regnum
= -1;
8659 tdep
->num_zmm_regs
= 0;
8660 tdep
->num_ymm_avx512_regs
= 0;
8661 tdep
->num_xmm_avx512_regs
= 0;
8663 /* No PKEYS registers */
8664 tdep
->pkru_regnum
= -1;
8665 tdep
->num_pkeys_regs
= 0;
8667 /* No segment base registers. */
8668 tdep
->fsbase_regnum
= -1;
8670 tdesc_arch_data_up tdesc_data
= tdesc_data_alloc ();
8672 set_gdbarch_relocate_instruction (gdbarch
, i386_relocate_instruction
);
8674 set_gdbarch_gen_return_address (gdbarch
, i386_gen_return_address
);
8676 set_gdbarch_insn_is_call (gdbarch
, i386_insn_is_call
);
8677 set_gdbarch_insn_is_ret (gdbarch
, i386_insn_is_ret
);
8678 set_gdbarch_insn_is_jump (gdbarch
, i386_insn_is_jump
);
8680 /* Hook in ABI-specific overrides, if they have been registered.
8681 Note: If INFO specifies a 64 bit arch, this is where we turn
8682 a 32-bit i386 into a 64-bit amd64. */
8683 info
.tdesc_data
= tdesc_data
.get ();
8684 gdbarch_init_osabi (info
, gdbarch
);
8686 if (!i386_validate_tdesc_p (tdep
, tdesc_data
.get ()))
8689 gdbarch_free (gdbarch
);
8693 num_bnd_cooked
= (tdep
->bnd0r_regnum
> 0 ? I387_NUM_BND_REGS
: 0);
8695 /* Wire in pseudo registers. Number of pseudo registers may be
8697 set_gdbarch_num_pseudo_regs (gdbarch
, (tdep
->num_byte_regs
8698 + tdep
->num_word_regs
8699 + tdep
->num_dword_regs
8700 + tdep
->num_mmx_regs
8701 + tdep
->num_ymm_regs
8703 + tdep
->num_ymm_avx512_regs
8704 + tdep
->num_zmm_regs
));
8706 /* Target description may be changed. */
8707 tdesc
= tdep
->tdesc
;
8709 tdesc_use_registers (gdbarch
, tdesc
, std::move (tdesc_data
));
8711 /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */
8712 set_gdbarch_register_reggroup_p (gdbarch
, tdep
->register_reggroup_p
);
8714 /* Make %al the first pseudo-register. */
8715 tdep
->al_regnum
= gdbarch_num_regs (gdbarch
);
8716 tdep
->ax_regnum
= tdep
->al_regnum
+ tdep
->num_byte_regs
;
8718 ymm0_regnum
= tdep
->ax_regnum
+ tdep
->num_word_regs
;
8719 if (tdep
->num_dword_regs
)
8721 /* Support dword pseudo-register if it hasn't been disabled. */
8722 tdep
->eax_regnum
= ymm0_regnum
;
8723 ymm0_regnum
+= tdep
->num_dword_regs
;
8726 tdep
->eax_regnum
= -1;
8728 mm0_regnum
= ymm0_regnum
;
8729 if (tdep
->num_ymm_regs
)
8731 /* Support YMM pseudo-register if it is available. */
8732 tdep
->ymm0_regnum
= ymm0_regnum
;
8733 mm0_regnum
+= tdep
->num_ymm_regs
;
8736 tdep
->ymm0_regnum
= -1;
8738 if (tdep
->num_ymm_avx512_regs
)
8740 /* Support YMM16-31 pseudo registers if available. */
8741 tdep
->ymm16_regnum
= mm0_regnum
;
8742 mm0_regnum
+= tdep
->num_ymm_avx512_regs
;
8745 tdep
->ymm16_regnum
= -1;
8747 if (tdep
->num_zmm_regs
)
8749 /* Support ZMM pseudo-register if it is available. */
8750 tdep
->zmm0_regnum
= mm0_regnum
;
8751 mm0_regnum
+= tdep
->num_zmm_regs
;
8754 tdep
->zmm0_regnum
= -1;
8756 bnd0_regnum
= mm0_regnum
;
8757 if (tdep
->num_mmx_regs
!= 0)
8759 /* Support MMX pseudo-register if MMX hasn't been disabled. */
8760 tdep
->mm0_regnum
= mm0_regnum
;
8761 bnd0_regnum
+= tdep
->num_mmx_regs
;
8764 tdep
->mm0_regnum
= -1;
8766 if (tdep
->bnd0r_regnum
> 0)
8767 tdep
->bnd0_regnum
= bnd0_regnum
;
8769 tdep
-> bnd0_regnum
= -1;
8771 /* Hook in the legacy prologue-based unwinders last (fallback). */
8772 frame_unwind_append_unwinder (gdbarch
, &i386_stack_tramp_frame_unwind
);
8773 frame_unwind_append_unwinder (gdbarch
, &i386_sigtramp_frame_unwind
);
8774 frame_unwind_append_unwinder (gdbarch
, &i386_frame_unwind
);
8776 /* If we have a register mapping, enable the generic core file
8777 support, unless it has already been enabled. */
8778 if (tdep
->gregset_reg_offset
8779 && !gdbarch_iterate_over_regset_sections_p (gdbarch
))
8780 set_gdbarch_iterate_over_regset_sections
8781 (gdbarch
, i386_iterate_over_regset_sections
);
8783 set_gdbarch_fast_tracepoint_valid_at (gdbarch
,
8784 i386_fast_tracepoint_valid_at
);
8791 /* Return the target description for a specified XSAVE feature mask. */
8793 const struct target_desc
*
8794 i386_target_description (uint64_t xcr0
, bool segments
)
8796 static target_desc
*i386_tdescs \
8797 [2/*SSE*/][2/*AVX*/][2/*MPX*/][2/*AVX512*/][2/*PKRU*/][2/*segments*/] = {};
8798 target_desc
**tdesc
;
8800 tdesc
= &i386_tdescs
[(xcr0
& X86_XSTATE_SSE
) ? 1 : 0]
8801 [(xcr0
& X86_XSTATE_AVX
) ? 1 : 0]
8802 [(xcr0
& X86_XSTATE_MPX
) ? 1 : 0]
8803 [(xcr0
& X86_XSTATE_AVX512
) ? 1 : 0]
8804 [(xcr0
& X86_XSTATE_PKRU
) ? 1 : 0]
8808 *tdesc
= i386_create_target_description (xcr0
, false, segments
);
8813 #define MPX_BASE_MASK (~(ULONGEST) 0xfff)
8815 /* Find the bound directory base address. */
8817 static unsigned long
8818 i386_mpx_bd_base (void)
8820 struct regcache
*rcache
;
8821 struct gdbarch_tdep
*tdep
;
8823 enum register_status regstatus
;
8825 rcache
= get_current_regcache ();
8826 tdep
= gdbarch_tdep (rcache
->arch ());
8828 regstatus
= regcache_raw_read_unsigned (rcache
, tdep
->bndcfgu_regnum
, &ret
);
8830 if (regstatus
!= REG_VALID
)
8831 error (_("BNDCFGU register invalid, read status %d."), regstatus
);
8833 return ret
& MPX_BASE_MASK
;
8837 i386_mpx_enabled (void)
8839 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_current_arch ());
8840 const struct target_desc
*tdesc
= tdep
->tdesc
;
8842 return (tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.mpx") != NULL
);
8845 #define MPX_BD_MASK 0xfffffff00000ULL /* select bits [47:20] */
8846 #define MPX_BT_MASK 0x0000000ffff8 /* select bits [19:3] */
8847 #define MPX_BD_MASK_32 0xfffff000 /* select bits [31:12] */
8848 #define MPX_BT_MASK_32 0x00000ffc /* select bits [11:2] */
8850 /* Find the bound table entry given the pointer location and the base
8851 address of the table. */
8854 i386_mpx_get_bt_entry (CORE_ADDR ptr
, CORE_ADDR bd_base
)
8858 CORE_ADDR mpx_bd_mask
, bd_ptr_r_shift
, bd_ptr_l_shift
;
8859 CORE_ADDR bt_mask
, bt_select_r_shift
, bt_select_l_shift
;
8860 CORE_ADDR bd_entry_addr
;
8863 struct gdbarch
*gdbarch
= get_current_arch ();
8864 struct type
*data_ptr_type
= builtin_type (gdbarch
)->builtin_data_ptr
;
8867 if (gdbarch_ptr_bit (gdbarch
) == 64)
8869 mpx_bd_mask
= (CORE_ADDR
) MPX_BD_MASK
;
8870 bd_ptr_r_shift
= 20;
8872 bt_select_r_shift
= 3;
8873 bt_select_l_shift
= 5;
8874 bt_mask
= (CORE_ADDR
) MPX_BT_MASK
;
8876 if ( sizeof (CORE_ADDR
) == 4)
8877 error (_("bound table examination not supported\
8878 for 64-bit process with 32-bit GDB"));
8882 mpx_bd_mask
= MPX_BD_MASK_32
;
8883 bd_ptr_r_shift
= 12;
8885 bt_select_r_shift
= 2;
8886 bt_select_l_shift
= 4;
8887 bt_mask
= MPX_BT_MASK_32
;
8890 offset1
= ((ptr
& mpx_bd_mask
) >> bd_ptr_r_shift
) << bd_ptr_l_shift
;
8891 bd_entry_addr
= bd_base
+ offset1
;
8892 bd_entry
= read_memory_typed_address (bd_entry_addr
, data_ptr_type
);
8894 if ((bd_entry
& 0x1) == 0)
8895 error (_("Invalid bounds directory entry at %s."),
8896 paddress (get_current_arch (), bd_entry_addr
));
8898 /* Clearing status bit. */
8900 bt_addr
= bd_entry
& ~bt_select_r_shift
;
8901 offset2
= ((ptr
& bt_mask
) >> bt_select_r_shift
) << bt_select_l_shift
;
8903 return bt_addr
+ offset2
;
8906 /* Print routine for the mpx bounds. */
8909 i386_mpx_print_bounds (const CORE_ADDR bt_entry
[4])
8911 struct ui_out
*uiout
= current_uiout
;
8913 struct gdbarch
*gdbarch
= get_current_arch ();
8914 CORE_ADDR onecompl
= ~((CORE_ADDR
) 0);
8915 int bounds_in_map
= ((~bt_entry
[1] == 0 && bt_entry
[0] == onecompl
) ? 1 : 0);
8917 if (bounds_in_map
== 1)
8919 uiout
->text ("Null bounds on map:");
8920 uiout
->text (" pointer value = ");
8921 uiout
->field_core_addr ("pointer-value", gdbarch
, bt_entry
[2]);
8927 uiout
->text ("{lbound = ");
8928 uiout
->field_core_addr ("lower-bound", gdbarch
, bt_entry
[0]);
8929 uiout
->text (", ubound = ");
8931 /* The upper bound is stored in 1's complement. */
8932 uiout
->field_core_addr ("upper-bound", gdbarch
, ~bt_entry
[1]);
8933 uiout
->text ("}: pointer value = ");
8934 uiout
->field_core_addr ("pointer-value", gdbarch
, bt_entry
[2]);
8936 if (gdbarch_ptr_bit (gdbarch
) == 64)
8937 size
= ( (~(int64_t) bt_entry
[1]) - (int64_t) bt_entry
[0]);
8939 size
= ( ~((int32_t) bt_entry
[1]) - (int32_t) bt_entry
[0]);
8941 /* In case the bounds are 0x0 and 0xffff... the difference will be -1.
8942 -1 represents in this sense full memory access, and there is no need
8945 size
= (size
> -1 ? size
+ 1 : size
);
8946 uiout
->text (", size = ");
8947 uiout
->field_string ("size", plongest (size
));
8949 uiout
->text (", metadata = ");
8950 uiout
->field_core_addr ("metadata", gdbarch
, bt_entry
[3]);
8955 /* Implement the command "show mpx bound". */
8958 i386_mpx_info_bounds (const char *args
, int from_tty
)
8960 CORE_ADDR bd_base
= 0;
8962 CORE_ADDR bt_entry_addr
= 0;
8963 CORE_ADDR bt_entry
[4];
8965 struct gdbarch
*gdbarch
= get_current_arch ();
8966 struct type
*data_ptr_type
= builtin_type (gdbarch
)->builtin_data_ptr
;
8968 if (gdbarch_bfd_arch_info (gdbarch
)->arch
!= bfd_arch_i386
8969 || !i386_mpx_enabled ())
8971 printf_unfiltered (_("Intel Memory Protection Extensions not "
8972 "supported on this target.\n"));
8978 printf_unfiltered (_("Address of pointer variable expected.\n"));
8982 addr
= parse_and_eval_address (args
);
8984 bd_base
= i386_mpx_bd_base ();
8985 bt_entry_addr
= i386_mpx_get_bt_entry (addr
, bd_base
);
8987 memset (bt_entry
, 0, sizeof (bt_entry
));
8989 for (i
= 0; i
< 4; i
++)
8990 bt_entry
[i
] = read_memory_typed_address (bt_entry_addr
8991 + i
* TYPE_LENGTH (data_ptr_type
),
8994 i386_mpx_print_bounds (bt_entry
);
8997 /* Implement the command "set mpx bound". */
9000 i386_mpx_set_bounds (const char *args
, int from_tty
)
9002 CORE_ADDR bd_base
= 0;
9003 CORE_ADDR addr
, lower
, upper
;
9004 CORE_ADDR bt_entry_addr
= 0;
9005 CORE_ADDR bt_entry
[2];
9006 const char *input
= args
;
9008 struct gdbarch
*gdbarch
= get_current_arch ();
9009 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
9010 struct type
*data_ptr_type
= builtin_type (gdbarch
)->builtin_data_ptr
;
9012 if (gdbarch_bfd_arch_info (gdbarch
)->arch
!= bfd_arch_i386
9013 || !i386_mpx_enabled ())
9014 error (_("Intel Memory Protection Extensions not supported\
9018 error (_("Pointer value expected."));
9020 addr
= value_as_address (parse_to_comma_and_eval (&input
));
9022 if (input
[0] == ',')
9024 if (input
[0] == '\0')
9025 error (_("wrong number of arguments: missing lower and upper bound."));
9026 lower
= value_as_address (parse_to_comma_and_eval (&input
));
9028 if (input
[0] == ',')
9030 if (input
[0] == '\0')
9031 error (_("Wrong number of arguments; Missing upper bound."));
9032 upper
= value_as_address (parse_to_comma_and_eval (&input
));
9034 bd_base
= i386_mpx_bd_base ();
9035 bt_entry_addr
= i386_mpx_get_bt_entry (addr
, bd_base
);
9036 for (i
= 0; i
< 2; i
++)
9037 bt_entry
[i
] = read_memory_typed_address (bt_entry_addr
9038 + i
* TYPE_LENGTH (data_ptr_type
),
9040 bt_entry
[0] = (uint64_t) lower
;
9041 bt_entry
[1] = ~(uint64_t) upper
;
9043 for (i
= 0; i
< 2; i
++)
9044 write_memory_unsigned_integer (bt_entry_addr
9045 + i
* TYPE_LENGTH (data_ptr_type
),
9046 TYPE_LENGTH (data_ptr_type
), byte_order
,
9050 static struct cmd_list_element
*mpx_set_cmdlist
, *mpx_show_cmdlist
;
9052 void _initialize_i386_tdep ();
9054 _initialize_i386_tdep ()
9056 register_gdbarch_init (bfd_arch_i386
, i386_gdbarch_init
);
9058 /* Add the variable that controls the disassembly flavor. */
9059 add_setshow_enum_cmd ("disassembly-flavor", no_class
, valid_flavors
,
9060 &disassembly_flavor
, _("\
9061 Set the disassembly flavor."), _("\
9062 Show the disassembly flavor."), _("\
9063 The valid values are \"att\" and \"intel\", and the default value is \"att\"."),
9065 NULL
, /* FIXME: i18n: */
9066 &setlist
, &showlist
);
9068 /* Add the variable that controls the convention for returning
9070 add_setshow_enum_cmd ("struct-convention", no_class
, valid_conventions
,
9071 &struct_convention
, _("\
9072 Set the convention for returning small structs."), _("\
9073 Show the convention for returning small structs."), _("\
9074 Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\
9077 NULL
, /* FIXME: i18n: */
9078 &setlist
, &showlist
);
9080 /* Add "mpx" prefix for the set commands. */
9082 add_basic_prefix_cmd ("mpx", class_support
, _("\
9083 Set Intel Memory Protection Extensions specific variables."),
9084 &mpx_set_cmdlist
, "set mpx ",
9085 0 /* allow-unknown */, &setlist
);
9087 /* Add "mpx" prefix for the show commands. */
9089 add_show_prefix_cmd ("mpx", class_support
, _("\
9090 Show Intel Memory Protection Extensions specific variables."),
9091 &mpx_show_cmdlist
, "show mpx ",
9092 0 /* allow-unknown */, &showlist
);
9094 /* Add "bound" command for the show mpx commands list. */
9096 add_cmd ("bound", no_class
, i386_mpx_info_bounds
,
9097 "Show the memory bounds for a given array/pointer storage\
9098 in the bound table.",
9101 /* Add "bound" command for the set mpx commands list. */
9103 add_cmd ("bound", no_class
, i386_mpx_set_bounds
,
9104 "Set the memory bounds for a given array/pointer storage\
9105 in the bound table.",
9108 gdbarch_register_osabi (bfd_arch_i386
, 0, GDB_OSABI_SVR4
,
9109 i386_svr4_init_abi
);
9111 /* Initialize the i386-specific register groups. */
9112 i386_init_reggroups ();
9114 /* Tell remote stub that we support XML target description. */
9115 register_remote_support_xml ("i386");