1 /* Intel 386 target-dependent stuff.
3 Copyright (C) 1988-2012 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "opcode/i386.h"
22 #include "arch-utils.h"
24 #include "dummy-frame.h"
25 #include "dwarf2-frame.h"
28 #include "frame-base.h"
29 #include "frame-unwind.h"
37 #include "reggroups.h"
46 #include "exceptions.h"
47 #include "gdb_assert.h"
48 #include "gdb_string.h"
50 #include "i386-tdep.h"
51 #include "i387-tdep.h"
52 #include "i386-xstate.h"
57 #include "features/i386/i386.c"
58 #include "features/i386/i386-avx.c"
59 #include "features/i386/i386-mmx.c"
64 #include "stap-probe.h"
65 #include "user-regs.h"
66 #include "cli/cli-utils.h"
67 #include "expression.h"
68 #include "parser-defs.h"
73 static const char *i386_register_names
[] =
75 "eax", "ecx", "edx", "ebx",
76 "esp", "ebp", "esi", "edi",
77 "eip", "eflags", "cs", "ss",
78 "ds", "es", "fs", "gs",
79 "st0", "st1", "st2", "st3",
80 "st4", "st5", "st6", "st7",
81 "fctrl", "fstat", "ftag", "fiseg",
82 "fioff", "foseg", "fooff", "fop",
83 "xmm0", "xmm1", "xmm2", "xmm3",
84 "xmm4", "xmm5", "xmm6", "xmm7",
88 static const char *i386_ymm_names
[] =
90 "ymm0", "ymm1", "ymm2", "ymm3",
91 "ymm4", "ymm5", "ymm6", "ymm7",
94 static const char *i386_ymmh_names
[] =
96 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
97 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
100 /* Register names for MMX pseudo-registers. */
102 static const char *i386_mmx_names
[] =
104 "mm0", "mm1", "mm2", "mm3",
105 "mm4", "mm5", "mm6", "mm7"
108 /* Register names for byte pseudo-registers. */
110 static const char *i386_byte_names
[] =
112 "al", "cl", "dl", "bl",
113 "ah", "ch", "dh", "bh"
116 /* Register names for word pseudo-registers. */
118 static const char *i386_word_names
[] =
120 "ax", "cx", "dx", "bx",
127 i386_mmx_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
129 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
130 int mm0_regnum
= tdep
->mm0_regnum
;
135 regnum
-= mm0_regnum
;
136 return regnum
>= 0 && regnum
< tdep
->num_mmx_regs
;
142 i386_byte_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
144 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
146 regnum
-= tdep
->al_regnum
;
147 return regnum
>= 0 && regnum
< tdep
->num_byte_regs
;
153 i386_word_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
155 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
157 regnum
-= tdep
->ax_regnum
;
158 return regnum
>= 0 && regnum
< tdep
->num_word_regs
;
161 /* Dword register? */
164 i386_dword_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
166 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
167 int eax_regnum
= tdep
->eax_regnum
;
172 regnum
-= eax_regnum
;
173 return regnum
>= 0 && regnum
< tdep
->num_dword_regs
;
177 i386_ymmh_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
179 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
180 int ymm0h_regnum
= tdep
->ymm0h_regnum
;
182 if (ymm0h_regnum
< 0)
185 regnum
-= ymm0h_regnum
;
186 return regnum
>= 0 && regnum
< tdep
->num_ymm_regs
;
192 i386_ymm_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
194 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
195 int ymm0_regnum
= tdep
->ymm0_regnum
;
200 regnum
-= ymm0_regnum
;
201 return regnum
>= 0 && regnum
< tdep
->num_ymm_regs
;
207 i386_xmm_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
209 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
210 int num_xmm_regs
= I387_NUM_XMM_REGS (tdep
);
212 if (num_xmm_regs
== 0)
215 regnum
-= I387_XMM0_REGNUM (tdep
);
216 return regnum
>= 0 && regnum
< num_xmm_regs
;
220 i386_mxcsr_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
222 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
224 if (I387_NUM_XMM_REGS (tdep
) == 0)
227 return (regnum
== I387_MXCSR_REGNUM (tdep
));
233 i386_fp_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
235 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
237 if (I387_ST0_REGNUM (tdep
) < 0)
240 return (I387_ST0_REGNUM (tdep
) <= regnum
241 && regnum
< I387_FCTRL_REGNUM (tdep
));
245 i386_fpc_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
247 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
249 if (I387_ST0_REGNUM (tdep
) < 0)
252 return (I387_FCTRL_REGNUM (tdep
) <= regnum
253 && regnum
< I387_XMM0_REGNUM (tdep
));
256 /* Return the name of register REGNUM, or the empty string if it is
257 an anonymous register. */
260 i386_register_name (struct gdbarch
*gdbarch
, int regnum
)
262 /* Hide the upper YMM registers. */
263 if (i386_ymmh_regnum_p (gdbarch
, regnum
))
266 return tdesc_register_name (gdbarch
, regnum
);
269 /* Return the name of register REGNUM. */
272 i386_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
274 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
275 if (i386_mmx_regnum_p (gdbarch
, regnum
))
276 return i386_mmx_names
[regnum
- I387_MM0_REGNUM (tdep
)];
277 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
278 return i386_ymm_names
[regnum
- tdep
->ymm0_regnum
];
279 else if (i386_byte_regnum_p (gdbarch
, regnum
))
280 return i386_byte_names
[regnum
- tdep
->al_regnum
];
281 else if (i386_word_regnum_p (gdbarch
, regnum
))
282 return i386_word_names
[regnum
- tdep
->ax_regnum
];
284 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
287 /* Convert a dbx register number REG to the appropriate register
288 number used by GDB. */
291 i386_dbx_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
293 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
295 /* This implements what GCC calls the "default" register map
296 (dbx_register_map[]). */
298 if (reg
>= 0 && reg
<= 7)
300 /* General-purpose registers. The debug info calls %ebp
301 register 4, and %esp register 5. */
308 else if (reg
>= 12 && reg
<= 19)
310 /* Floating-point registers. */
311 return reg
- 12 + I387_ST0_REGNUM (tdep
);
313 else if (reg
>= 21 && reg
<= 28)
316 int ymm0_regnum
= tdep
->ymm0_regnum
;
319 && i386_xmm_regnum_p (gdbarch
, reg
))
320 return reg
- 21 + ymm0_regnum
;
322 return reg
- 21 + I387_XMM0_REGNUM (tdep
);
324 else if (reg
>= 29 && reg
<= 36)
327 return reg
- 29 + I387_MM0_REGNUM (tdep
);
330 /* This will hopefully provoke a warning. */
331 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
334 /* Convert SVR4 register number REG to the appropriate register number
338 i386_svr4_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
340 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
342 /* This implements the GCC register map that tries to be compatible
343 with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */
345 /* The SVR4 register numbering includes %eip and %eflags, and
346 numbers the floating point registers differently. */
347 if (reg
>= 0 && reg
<= 9)
349 /* General-purpose registers. */
352 else if (reg
>= 11 && reg
<= 18)
354 /* Floating-point registers. */
355 return reg
- 11 + I387_ST0_REGNUM (tdep
);
357 else if (reg
>= 21 && reg
<= 36)
359 /* The SSE and MMX registers have the same numbers as with dbx. */
360 return i386_dbx_reg_to_regnum (gdbarch
, reg
);
365 case 37: return I387_FCTRL_REGNUM (tdep
);
366 case 38: return I387_FSTAT_REGNUM (tdep
);
367 case 39: return I387_MXCSR_REGNUM (tdep
);
368 case 40: return I386_ES_REGNUM
;
369 case 41: return I386_CS_REGNUM
;
370 case 42: return I386_SS_REGNUM
;
371 case 43: return I386_DS_REGNUM
;
372 case 44: return I386_FS_REGNUM
;
373 case 45: return I386_GS_REGNUM
;
376 /* This will hopefully provoke a warning. */
377 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
382 /* This is the variable that is set with "set disassembly-flavor", and
383 its legitimate values. */
384 static const char att_flavor
[] = "att";
385 static const char intel_flavor
[] = "intel";
386 static const char *const valid_flavors
[] =
392 static const char *disassembly_flavor
= att_flavor
;
395 /* Use the program counter to determine the contents and size of a
396 breakpoint instruction. Return a pointer to a string of bytes that
397 encode a breakpoint instruction, store the length of the string in
398 *LEN and optionally adjust *PC to point to the correct memory
399 location for inserting the breakpoint.
401 On the i386 we have a single breakpoint that fits in a single byte
402 and can be inserted anywhere.
404 This function is 64-bit safe. */
406 static const gdb_byte
*
407 i386_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pc
, int *len
)
409 static gdb_byte break_insn
[] = { 0xcc }; /* int 3 */
411 *len
= sizeof (break_insn
);
415 /* Displaced instruction handling. */
417 /* Skip the legacy instruction prefixes in INSN.
418 Not all prefixes are valid for any particular insn
419 but we needn't care, the insn will fault if it's invalid.
420 The result is a pointer to the first opcode byte,
421 or NULL if we run off the end of the buffer. */
424 i386_skip_prefixes (gdb_byte
*insn
, size_t max_len
)
426 gdb_byte
*end
= insn
+ max_len
;
432 case DATA_PREFIX_OPCODE
:
433 case ADDR_PREFIX_OPCODE
:
434 case CS_PREFIX_OPCODE
:
435 case DS_PREFIX_OPCODE
:
436 case ES_PREFIX_OPCODE
:
437 case FS_PREFIX_OPCODE
:
438 case GS_PREFIX_OPCODE
:
439 case SS_PREFIX_OPCODE
:
440 case LOCK_PREFIX_OPCODE
:
441 case REPE_PREFIX_OPCODE
:
442 case REPNE_PREFIX_OPCODE
:
454 i386_absolute_jmp_p (const gdb_byte
*insn
)
456 /* jmp far (absolute address in operand). */
462 /* jump near, absolute indirect (/4). */
463 if ((insn
[1] & 0x38) == 0x20)
466 /* jump far, absolute indirect (/5). */
467 if ((insn
[1] & 0x38) == 0x28)
475 i386_absolute_call_p (const gdb_byte
*insn
)
477 /* call far, absolute. */
483 /* Call near, absolute indirect (/2). */
484 if ((insn
[1] & 0x38) == 0x10)
487 /* Call far, absolute indirect (/3). */
488 if ((insn
[1] & 0x38) == 0x18)
496 i386_ret_p (const gdb_byte
*insn
)
500 case 0xc2: /* ret near, pop N bytes. */
501 case 0xc3: /* ret near */
502 case 0xca: /* ret far, pop N bytes. */
503 case 0xcb: /* ret far */
504 case 0xcf: /* iret */
513 i386_call_p (const gdb_byte
*insn
)
515 if (i386_absolute_call_p (insn
))
518 /* call near, relative. */
525 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
526 length in bytes. Otherwise, return zero. */
529 i386_syscall_p (const gdb_byte
*insn
, int *lengthp
)
531 /* Is it 'int $0x80'? */
532 if ((insn
[0] == 0xcd && insn
[1] == 0x80)
533 /* Or is it 'sysenter'? */
534 || (insn
[0] == 0x0f && insn
[1] == 0x34)
535 /* Or is it 'syscall'? */
536 || (insn
[0] == 0x0f && insn
[1] == 0x05))
545 /* Some kernels may run one past a syscall insn, so we have to cope.
546 Otherwise this is just simple_displaced_step_copy_insn. */
548 struct displaced_step_closure
*
549 i386_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
550 CORE_ADDR from
, CORE_ADDR to
,
551 struct regcache
*regs
)
553 size_t len
= gdbarch_max_insn_length (gdbarch
);
554 gdb_byte
*buf
= xmalloc (len
);
556 read_memory (from
, buf
, len
);
558 /* GDB may get control back after the insn after the syscall.
559 Presumably this is a kernel bug.
560 If this is a syscall, make sure there's a nop afterwards. */
565 insn
= i386_skip_prefixes (buf
, len
);
566 if (insn
!= NULL
&& i386_syscall_p (insn
, &syscall_length
))
567 insn
[syscall_length
] = NOP_OPCODE
;
570 write_memory (to
, buf
, len
);
574 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
575 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
576 displaced_step_dump_bytes (gdb_stdlog
, buf
, len
);
579 return (struct displaced_step_closure
*) buf
;
582 /* Fix up the state of registers and memory after having single-stepped
583 a displaced instruction. */
586 i386_displaced_step_fixup (struct gdbarch
*gdbarch
,
587 struct displaced_step_closure
*closure
,
588 CORE_ADDR from
, CORE_ADDR to
,
589 struct regcache
*regs
)
591 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
593 /* The offset we applied to the instruction's address.
594 This could well be negative (when viewed as a signed 32-bit
595 value), but ULONGEST won't reflect that, so take care when
597 ULONGEST insn_offset
= to
- from
;
599 /* Since we use simple_displaced_step_copy_insn, our closure is a
600 copy of the instruction. */
601 gdb_byte
*insn
= (gdb_byte
*) closure
;
602 /* The start of the insn, needed in case we see some prefixes. */
603 gdb_byte
*insn_start
= insn
;
606 fprintf_unfiltered (gdb_stdlog
,
607 "displaced: fixup (%s, %s), "
608 "insn = 0x%02x 0x%02x ...\n",
609 paddress (gdbarch
, from
), paddress (gdbarch
, to
),
612 /* The list of issues to contend with here is taken from
613 resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20.
614 Yay for Free Software! */
616 /* Relocate the %eip, if necessary. */
618 /* The instruction recognizers we use assume any leading prefixes
619 have been skipped. */
621 /* This is the size of the buffer in closure. */
622 size_t max_insn_len
= gdbarch_max_insn_length (gdbarch
);
623 gdb_byte
*opcode
= i386_skip_prefixes (insn
, max_insn_len
);
624 /* If there are too many prefixes, just ignore the insn.
625 It will fault when run. */
630 /* Except in the case of absolute or indirect jump or call
631 instructions, or a return instruction, the new eip is relative to
632 the displaced instruction; make it relative. Well, signal
633 handler returns don't need relocation either, but we use the
634 value of %eip to recognize those; see below. */
635 if (! i386_absolute_jmp_p (insn
)
636 && ! i386_absolute_call_p (insn
)
637 && ! i386_ret_p (insn
))
642 regcache_cooked_read_unsigned (regs
, I386_EIP_REGNUM
, &orig_eip
);
644 /* A signal trampoline system call changes the %eip, resuming
645 execution of the main program after the signal handler has
646 returned. That makes them like 'return' instructions; we
647 shouldn't relocate %eip.
649 But most system calls don't, and we do need to relocate %eip.
651 Our heuristic for distinguishing these cases: if stepping
652 over the system call instruction left control directly after
653 the instruction, the we relocate --- control almost certainly
654 doesn't belong in the displaced copy. Otherwise, we assume
655 the instruction has put control where it belongs, and leave
656 it unrelocated. Goodness help us if there are PC-relative
658 if (i386_syscall_p (insn
, &insn_len
)
659 && orig_eip
!= to
+ (insn
- insn_start
) + insn_len
660 /* GDB can get control back after the insn after the syscall.
661 Presumably this is a kernel bug.
662 i386_displaced_step_copy_insn ensures its a nop,
663 we add one to the length for it. */
664 && orig_eip
!= to
+ (insn
- insn_start
) + insn_len
+ 1)
667 fprintf_unfiltered (gdb_stdlog
,
668 "displaced: syscall changed %%eip; "
673 ULONGEST eip
= (orig_eip
- insn_offset
) & 0xffffffffUL
;
675 /* If we just stepped over a breakpoint insn, we don't backup
676 the pc on purpose; this is to match behaviour without
679 regcache_cooked_write_unsigned (regs
, I386_EIP_REGNUM
, eip
);
682 fprintf_unfiltered (gdb_stdlog
,
684 "relocated %%eip from %s to %s\n",
685 paddress (gdbarch
, orig_eip
),
686 paddress (gdbarch
, eip
));
690 /* If the instruction was PUSHFL, then the TF bit will be set in the
691 pushed value, and should be cleared. We'll leave this for later,
692 since GDB already messes up the TF flag when stepping over a
695 /* If the instruction was a call, the return address now atop the
696 stack is the address following the copied instruction. We need
697 to make it the address following the original instruction. */
698 if (i386_call_p (insn
))
702 const ULONGEST retaddr_len
= 4;
704 regcache_cooked_read_unsigned (regs
, I386_ESP_REGNUM
, &esp
);
705 retaddr
= read_memory_unsigned_integer (esp
, retaddr_len
, byte_order
);
706 retaddr
= (retaddr
- insn_offset
) & 0xffffffffUL
;
707 write_memory_unsigned_integer (esp
, retaddr_len
, byte_order
, retaddr
);
710 fprintf_unfiltered (gdb_stdlog
,
711 "displaced: relocated return addr at %s to %s\n",
712 paddress (gdbarch
, esp
),
713 paddress (gdbarch
, retaddr
));
718 append_insns (CORE_ADDR
*to
, ULONGEST len
, const gdb_byte
*buf
)
720 target_write_memory (*to
, buf
, len
);
725 i386_relocate_instruction (struct gdbarch
*gdbarch
,
726 CORE_ADDR
*to
, CORE_ADDR oldloc
)
728 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
729 gdb_byte buf
[I386_MAX_INSN_LEN
];
730 int offset
= 0, rel32
, newrel
;
732 gdb_byte
*insn
= buf
;
734 read_memory (oldloc
, buf
, I386_MAX_INSN_LEN
);
736 insn_length
= gdb_buffered_insn_length (gdbarch
, insn
,
737 I386_MAX_INSN_LEN
, oldloc
);
739 /* Get past the prefixes. */
740 insn
= i386_skip_prefixes (insn
, I386_MAX_INSN_LEN
);
742 /* Adjust calls with 32-bit relative addresses as push/jump, with
743 the address pushed being the location where the original call in
744 the user program would return to. */
747 gdb_byte push_buf
[16];
748 unsigned int ret_addr
;
750 /* Where "ret" in the original code will return to. */
751 ret_addr
= oldloc
+ insn_length
;
752 push_buf
[0] = 0x68; /* pushq $... */
753 store_unsigned_integer (&push_buf
[1], 4, byte_order
, ret_addr
);
755 append_insns (to
, 5, push_buf
);
757 /* Convert the relative call to a relative jump. */
760 /* Adjust the destination offset. */
761 rel32
= extract_signed_integer (insn
+ 1, 4, byte_order
);
762 newrel
= (oldloc
- *to
) + rel32
;
763 store_signed_integer (insn
+ 1, 4, byte_order
, newrel
);
766 fprintf_unfiltered (gdb_stdlog
,
767 "Adjusted insn rel32=%s at %s to"
769 hex_string (rel32
), paddress (gdbarch
, oldloc
),
770 hex_string (newrel
), paddress (gdbarch
, *to
));
772 /* Write the adjusted jump into its displaced location. */
773 append_insns (to
, 5, insn
);
777 /* Adjust jumps with 32-bit relative addresses. Calls are already
781 /* Adjust conditional jumps. */
782 else if (insn
[0] == 0x0f && (insn
[1] & 0xf0) == 0x80)
787 rel32
= extract_signed_integer (insn
+ offset
, 4, byte_order
);
788 newrel
= (oldloc
- *to
) + rel32
;
789 store_signed_integer (insn
+ offset
, 4, byte_order
, newrel
);
791 fprintf_unfiltered (gdb_stdlog
,
792 "Adjusted insn rel32=%s at %s to"
794 hex_string (rel32
), paddress (gdbarch
, oldloc
),
795 hex_string (newrel
), paddress (gdbarch
, *to
));
798 /* Write the adjusted instructions into their displaced
800 append_insns (to
, insn_length
, buf
);
804 #ifdef I386_REGNO_TO_SYMMETRY
805 #error "The Sequent Symmetry is no longer supported."
808 /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi
809 and %esp "belong" to the calling function. Therefore these
810 registers should be saved if they're going to be modified. */
812 /* The maximum number of saved registers. This should include all
813 registers mentioned above, and %eip. */
814 #define I386_NUM_SAVED_REGS I386_NUM_GREGS
816 struct i386_frame_cache
824 /* Saved registers. */
825 CORE_ADDR saved_regs
[I386_NUM_SAVED_REGS
];
830 /* Stack space reserved for local variables. */
834 /* Allocate and initialize a frame cache. */
836 static struct i386_frame_cache
*
837 i386_alloc_frame_cache (void)
839 struct i386_frame_cache
*cache
;
842 cache
= FRAME_OBSTACK_ZALLOC (struct i386_frame_cache
);
847 cache
->sp_offset
= -4;
850 /* Saved registers. We initialize these to -1 since zero is a valid
851 offset (that's where %ebp is supposed to be stored). */
852 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
853 cache
->saved_regs
[i
] = -1;
855 cache
->saved_sp_reg
= -1;
856 cache
->pc_in_eax
= 0;
858 /* Frameless until proven otherwise. */
864 /* If the instruction at PC is a jump, return the address of its
865 target. Otherwise, return PC. */
868 i386_follow_jump (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
870 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
875 if (target_read_memory (pc
, &op
, 1))
881 op
= read_memory_unsigned_integer (pc
+ 1, 1, byte_order
);
887 /* Relative jump: if data16 == 0, disp32, else disp16. */
890 delta
= read_memory_integer (pc
+ 2, 2, byte_order
);
892 /* Include the size of the jmp instruction (including the
898 delta
= read_memory_integer (pc
+ 1, 4, byte_order
);
900 /* Include the size of the jmp instruction. */
905 /* Relative jump, disp8 (ignore data16). */
906 delta
= read_memory_integer (pc
+ data16
+ 1, 1, byte_order
);
915 /* Check whether PC points at a prologue for a function returning a
916 structure or union. If so, it updates CACHE and returns the
917 address of the first instruction after the code sequence that
918 removes the "hidden" argument from the stack or CURRENT_PC,
919 whichever is smaller. Otherwise, return PC. */
922 i386_analyze_struct_return (CORE_ADDR pc
, CORE_ADDR current_pc
,
923 struct i386_frame_cache
*cache
)
925 /* Functions that return a structure or union start with:
928 xchgl %eax, (%esp) 0x87 0x04 0x24
929 or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00
931 (the System V compiler puts out the second `xchg' instruction,
932 and the assembler doesn't try to optimize it, so the 'sib' form
933 gets generated). This sequence is used to get the address of the
934 return buffer for a function that returns a structure. */
935 static gdb_byte proto1
[3] = { 0x87, 0x04, 0x24 };
936 static gdb_byte proto2
[4] = { 0x87, 0x44, 0x24, 0x00 };
940 if (current_pc
<= pc
)
943 if (target_read_memory (pc
, &op
, 1))
946 if (op
!= 0x58) /* popl %eax */
949 if (target_read_memory (pc
+ 1, buf
, 4))
952 if (memcmp (buf
, proto1
, 3) != 0 && memcmp (buf
, proto2
, 4) != 0)
955 if (current_pc
== pc
)
957 cache
->sp_offset
+= 4;
961 if (current_pc
== pc
+ 1)
963 cache
->pc_in_eax
= 1;
967 if (buf
[1] == proto1
[1])
974 i386_skip_probe (CORE_ADDR pc
)
976 /* A function may start with
990 if (target_read_memory (pc
, &op
, 1))
993 if (op
== 0x68 || op
== 0x6a)
997 /* Skip past the `pushl' instruction; it has either a one-byte or a
998 four-byte operand, depending on the opcode. */
1004 /* Read the following 8 bytes, which should be `call _probe' (6
1005 bytes) followed by `addl $4,%esp' (2 bytes). */
1006 read_memory (pc
+ delta
, buf
, sizeof (buf
));
1007 if (buf
[0] == 0xe8 && buf
[6] == 0xc4 && buf
[7] == 0x4)
1008 pc
+= delta
+ sizeof (buf
);
1014 /* GCC 4.1 and later, can put code in the prologue to realign the
1015 stack pointer. Check whether PC points to such code, and update
1016 CACHE accordingly. Return the first instruction after the code
1017 sequence or CURRENT_PC, whichever is smaller. If we don't
1018 recognize the code, return PC. */
1021 i386_analyze_stack_align (CORE_ADDR pc
, CORE_ADDR current_pc
,
1022 struct i386_frame_cache
*cache
)
1024 /* There are 2 code sequences to re-align stack before the frame
1027 1. Use a caller-saved saved register:
1033 2. Use a callee-saved saved register:
1040 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
1042 0x83 0xe4 0xf0 andl $-16, %esp
1043 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
1048 int offset
, offset_and
;
1049 static int regnums
[8] = {
1050 I386_EAX_REGNUM
, /* %eax */
1051 I386_ECX_REGNUM
, /* %ecx */
1052 I386_EDX_REGNUM
, /* %edx */
1053 I386_EBX_REGNUM
, /* %ebx */
1054 I386_ESP_REGNUM
, /* %esp */
1055 I386_EBP_REGNUM
, /* %ebp */
1056 I386_ESI_REGNUM
, /* %esi */
1057 I386_EDI_REGNUM
/* %edi */
1060 if (target_read_memory (pc
, buf
, sizeof buf
))
1063 /* Check caller-saved saved register. The first instruction has
1064 to be "leal 4(%esp), %reg". */
1065 if (buf
[0] == 0x8d && buf
[2] == 0x24 && buf
[3] == 0x4)
1067 /* MOD must be binary 10 and R/M must be binary 100. */
1068 if ((buf
[1] & 0xc7) != 0x44)
1071 /* REG has register number. */
1072 reg
= (buf
[1] >> 3) & 7;
1077 /* Check callee-saved saved register. The first instruction
1078 has to be "pushl %reg". */
1079 if ((buf
[0] & 0xf8) != 0x50)
1085 /* The next instruction has to be "leal 8(%esp), %reg". */
1086 if (buf
[1] != 0x8d || buf
[3] != 0x24 || buf
[4] != 0x8)
1089 /* MOD must be binary 10 and R/M must be binary 100. */
1090 if ((buf
[2] & 0xc7) != 0x44)
1093 /* REG has register number. Registers in pushl and leal have to
1095 if (reg
!= ((buf
[2] >> 3) & 7))
1101 /* Rigister can't be %esp nor %ebp. */
1102 if (reg
== 4 || reg
== 5)
1105 /* The next instruction has to be "andl $-XXX, %esp". */
1106 if (buf
[offset
+ 1] != 0xe4
1107 || (buf
[offset
] != 0x81 && buf
[offset
] != 0x83))
1110 offset_and
= offset
;
1111 offset
+= buf
[offset
] == 0x81 ? 6 : 3;
1113 /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is
1114 0xfc. REG must be binary 110 and MOD must be binary 01. */
1115 if (buf
[offset
] != 0xff
1116 || buf
[offset
+ 2] != 0xfc
1117 || (buf
[offset
+ 1] & 0xf8) != 0x70)
1120 /* R/M has register. Registers in leal and pushl have to be the
1122 if (reg
!= (buf
[offset
+ 1] & 7))
1125 if (current_pc
> pc
+ offset_and
)
1126 cache
->saved_sp_reg
= regnums
[reg
];
1128 return min (pc
+ offset
+ 3, current_pc
);
1131 /* Maximum instruction length we need to handle. */
1132 #define I386_MAX_MATCHED_INSN_LEN 6
1134 /* Instruction description. */
1138 gdb_byte insn
[I386_MAX_MATCHED_INSN_LEN
];
1139 gdb_byte mask
[I386_MAX_MATCHED_INSN_LEN
];
1142 /* Return whether instruction at PC matches PATTERN. */
1145 i386_match_pattern (CORE_ADDR pc
, struct i386_insn pattern
)
1149 if (target_read_memory (pc
, &op
, 1))
1152 if ((op
& pattern
.mask
[0]) == pattern
.insn
[0])
1154 gdb_byte buf
[I386_MAX_MATCHED_INSN_LEN
- 1];
1155 int insn_matched
= 1;
1158 gdb_assert (pattern
.len
> 1);
1159 gdb_assert (pattern
.len
<= I386_MAX_MATCHED_INSN_LEN
);
1161 if (target_read_memory (pc
+ 1, buf
, pattern
.len
- 1))
1164 for (i
= 1; i
< pattern
.len
; i
++)
1166 if ((buf
[i
- 1] & pattern
.mask
[i
]) != pattern
.insn
[i
])
1169 return insn_matched
;
1174 /* Search for the instruction at PC in the list INSN_PATTERNS. Return
1175 the first instruction description that matches. Otherwise, return
1178 static struct i386_insn
*
1179 i386_match_insn (CORE_ADDR pc
, struct i386_insn
*insn_patterns
)
1181 struct i386_insn
*pattern
;
1183 for (pattern
= insn_patterns
; pattern
->len
> 0; pattern
++)
1185 if (i386_match_pattern (pc
, *pattern
))
1192 /* Return whether PC points inside a sequence of instructions that
1193 matches INSN_PATTERNS. */
1196 i386_match_insn_block (CORE_ADDR pc
, struct i386_insn
*insn_patterns
)
1198 CORE_ADDR current_pc
;
1200 struct i386_insn
*insn
;
1202 insn
= i386_match_insn (pc
, insn_patterns
);
1207 ix
= insn
- insn_patterns
;
1208 for (i
= ix
- 1; i
>= 0; i
--)
1210 current_pc
-= insn_patterns
[i
].len
;
1212 if (!i386_match_pattern (current_pc
, insn_patterns
[i
]))
1216 current_pc
= pc
+ insn
->len
;
1217 for (insn
= insn_patterns
+ ix
+ 1; insn
->len
> 0; insn
++)
1219 if (!i386_match_pattern (current_pc
, *insn
))
1222 current_pc
+= insn
->len
;
1228 /* Some special instructions that might be migrated by GCC into the
1229 part of the prologue that sets up the new stack frame. Because the
1230 stack frame hasn't been setup yet, no registers have been saved
1231 yet, and only the scratch registers %eax, %ecx and %edx can be
1234 struct i386_insn i386_frame_setup_skip_insns
[] =
1236 /* Check for `movb imm8, r' and `movl imm32, r'.
1238 ??? Should we handle 16-bit operand-sizes here? */
1240 /* `movb imm8, %al' and `movb imm8, %ah' */
1241 /* `movb imm8, %cl' and `movb imm8, %ch' */
1242 { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } },
1243 /* `movb imm8, %dl' and `movb imm8, %dh' */
1244 { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } },
1245 /* `movl imm32, %eax' and `movl imm32, %ecx' */
1246 { 5, { 0xb8 }, { 0xfe } },
1247 /* `movl imm32, %edx' */
1248 { 5, { 0xba }, { 0xff } },
1250 /* Check for `mov imm32, r32'. Note that there is an alternative
1251 encoding for `mov m32, %eax'.
1253 ??? Should we handle SIB adressing here?
1254 ??? Should we handle 16-bit operand-sizes here? */
1256 /* `movl m32, %eax' */
1257 { 5, { 0xa1 }, { 0xff } },
1258 /* `movl m32, %eax' and `mov; m32, %ecx' */
1259 { 6, { 0x89, 0x05 }, {0xff, 0xf7 } },
1260 /* `movl m32, %edx' */
1261 { 6, { 0x89, 0x15 }, {0xff, 0xff } },
1263 /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'.
1264 Because of the symmetry, there are actually two ways to encode
1265 these instructions; opcode bytes 0x29 and 0x2b for `subl' and
1266 opcode bytes 0x31 and 0x33 for `xorl'. */
1268 /* `subl %eax, %eax' */
1269 { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } },
1270 /* `subl %ecx, %ecx' */
1271 { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } },
1272 /* `subl %edx, %edx' */
1273 { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } },
1274 /* `xorl %eax, %eax' */
1275 { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } },
1276 /* `xorl %ecx, %ecx' */
1277 { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } },
1278 /* `xorl %edx, %edx' */
1279 { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } },
1284 /* Check whether PC points to a no-op instruction. */
1286 i386_skip_noop (CORE_ADDR pc
)
1291 if (target_read_memory (pc
, &op
, 1))
1297 /* Ignore `nop' instruction. */
1301 if (target_read_memory (pc
, &op
, 1))
1305 /* Ignore no-op instruction `mov %edi, %edi'.
1306 Microsoft system dlls often start with
1307 a `mov %edi,%edi' instruction.
1308 The 5 bytes before the function start are
1309 filled with `nop' instructions.
1310 This pattern can be used for hot-patching:
1311 The `mov %edi, %edi' instruction can be replaced by a
1312 near jump to the location of the 5 `nop' instructions
1313 which can be replaced by a 32-bit jump to anywhere
1314 in the 32-bit address space. */
1316 else if (op
== 0x8b)
1318 if (target_read_memory (pc
+ 1, &op
, 1))
1324 if (target_read_memory (pc
, &op
, 1))
1334 /* Check whether PC points at a code that sets up a new stack frame.
1335 If so, it updates CACHE and returns the address of the first
1336 instruction after the sequence that sets up the frame or LIMIT,
1337 whichever is smaller. If we don't recognize the code, return PC. */
1340 i386_analyze_frame_setup (struct gdbarch
*gdbarch
,
1341 CORE_ADDR pc
, CORE_ADDR limit
,
1342 struct i386_frame_cache
*cache
)
1344 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1345 struct i386_insn
*insn
;
1352 if (target_read_memory (pc
, &op
, 1))
1355 if (op
== 0x55) /* pushl %ebp */
1357 /* Take into account that we've executed the `pushl %ebp' that
1358 starts this instruction sequence. */
1359 cache
->saved_regs
[I386_EBP_REGNUM
] = 0;
1360 cache
->sp_offset
+= 4;
1363 /* If that's all, return now. */
1367 /* Check for some special instructions that might be migrated by
1368 GCC into the prologue and skip them. At this point in the
1369 prologue, code should only touch the scratch registers %eax,
1370 %ecx and %edx, so while the number of posibilities is sheer,
1373 Make sure we only skip these instructions if we later see the
1374 `movl %esp, %ebp' that actually sets up the frame. */
1375 while (pc
+ skip
< limit
)
1377 insn
= i386_match_insn (pc
+ skip
, i386_frame_setup_skip_insns
);
1384 /* If that's all, return now. */
1385 if (limit
<= pc
+ skip
)
1388 if (target_read_memory (pc
+ skip
, &op
, 1))
1391 /* The i386 prologue looks like
1397 and a different prologue can be generated for atom.
1401 lea -0x10(%esp),%esp
1403 We handle both of them here. */
1407 /* Check for `movl %esp, %ebp' -- can be written in two ways. */
1409 if (read_memory_unsigned_integer (pc
+ skip
+ 1, 1, byte_order
)
1415 if (read_memory_unsigned_integer (pc
+ skip
+ 1, 1, byte_order
)
1420 case 0x8d: /* Check for 'lea (%ebp), %ebp'. */
1421 if (read_memory_unsigned_integer (pc
+ skip
+ 1, 2, byte_order
)
1430 /* OK, we actually have a frame. We just don't know how large
1431 it is yet. Set its size to zero. We'll adjust it if
1432 necessary. We also now commit to skipping the special
1433 instructions mentioned before. */
1436 /* If that's all, return now. */
1440 /* Check for stack adjustment
1446 NOTE: You can't subtract a 16-bit immediate from a 32-bit
1447 reg, so we don't have to worry about a data16 prefix. */
1448 if (target_read_memory (pc
, &op
, 1))
1452 /* `subl' with 8-bit immediate. */
1453 if (read_memory_unsigned_integer (pc
+ 1, 1, byte_order
) != 0xec)
1454 /* Some instruction starting with 0x83 other than `subl'. */
1457 /* `subl' with signed 8-bit immediate (though it wouldn't
1458 make sense to be negative). */
1459 cache
->locals
= read_memory_integer (pc
+ 2, 1, byte_order
);
1462 else if (op
== 0x81)
1464 /* Maybe it is `subl' with a 32-bit immediate. */
1465 if (read_memory_unsigned_integer (pc
+ 1, 1, byte_order
) != 0xec)
1466 /* Some instruction starting with 0x81 other than `subl'. */
1469 /* It is `subl' with a 32-bit immediate. */
1470 cache
->locals
= read_memory_integer (pc
+ 2, 4, byte_order
);
1473 else if (op
== 0x8d)
1475 /* The ModR/M byte is 0x64. */
1476 if (read_memory_unsigned_integer (pc
+ 1, 1, byte_order
) != 0x64)
1478 /* 'lea' with 8-bit displacement. */
1479 cache
->locals
= -1 * read_memory_integer (pc
+ 3, 1, byte_order
);
1484 /* Some instruction other than `subl' nor 'lea'. */
1488 else if (op
== 0xc8) /* enter */
1490 cache
->locals
= read_memory_unsigned_integer (pc
+ 1, 2, byte_order
);
1497 /* Check whether PC points at code that saves registers on the stack.
1498 If so, it updates CACHE and returns the address of the first
1499 instruction after the register saves or CURRENT_PC, whichever is
1500 smaller. Otherwise, return PC. */
1503 i386_analyze_register_saves (CORE_ADDR pc
, CORE_ADDR current_pc
,
1504 struct i386_frame_cache
*cache
)
1506 CORE_ADDR offset
= 0;
1510 if (cache
->locals
> 0)
1511 offset
-= cache
->locals
;
1512 for (i
= 0; i
< 8 && pc
< current_pc
; i
++)
1514 if (target_read_memory (pc
, &op
, 1))
1516 if (op
< 0x50 || op
> 0x57)
1520 cache
->saved_regs
[op
- 0x50] = offset
;
1521 cache
->sp_offset
+= 4;
1528 /* Do a full analysis of the prologue at PC and update CACHE
1529 accordingly. Bail out early if CURRENT_PC is reached. Return the
1530 address where the analysis stopped.
1532 We handle these cases:
1534 The startup sequence can be at the start of the function, or the
1535 function can start with a branch to startup code at the end.
1537 %ebp can be set up with either the 'enter' instruction, or "pushl
1538 %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was
1539 once used in the System V compiler).
1541 Local space is allocated just below the saved %ebp by either the
1542 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a
1543 16-bit unsigned argument for space to allocate, and the 'addl'
1544 instruction could have either a signed byte, or 32-bit immediate.
1546 Next, the registers used by this function are pushed. With the
1547 System V compiler they will always be in the order: %edi, %esi,
1548 %ebx (and sometimes a harmless bug causes it to also save but not
1549 restore %eax); however, the code below is willing to see the pushes
1550 in any order, and will handle up to 8 of them.
1552 If the setup sequence is at the end of the function, then the next
1553 instruction will be a branch back to the start. */
1556 i386_analyze_prologue (struct gdbarch
*gdbarch
,
1557 CORE_ADDR pc
, CORE_ADDR current_pc
,
1558 struct i386_frame_cache
*cache
)
1560 pc
= i386_skip_noop (pc
);
1561 pc
= i386_follow_jump (gdbarch
, pc
);
1562 pc
= i386_analyze_struct_return (pc
, current_pc
, cache
);
1563 pc
= i386_skip_probe (pc
);
1564 pc
= i386_analyze_stack_align (pc
, current_pc
, cache
);
1565 pc
= i386_analyze_frame_setup (gdbarch
, pc
, current_pc
, cache
);
1566 return i386_analyze_register_saves (pc
, current_pc
, cache
);
1569 /* Return PC of first real instruction. */
1572 i386_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
1574 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1576 static gdb_byte pic_pat
[6] =
1578 0xe8, 0, 0, 0, 0, /* call 0x0 */
1579 0x5b, /* popl %ebx */
1581 struct i386_frame_cache cache
;
1587 pc
= i386_analyze_prologue (gdbarch
, start_pc
, 0xffffffff, &cache
);
1588 if (cache
.locals
< 0)
1591 /* Found valid frame setup. */
1593 /* The native cc on SVR4 in -K PIC mode inserts the following code
1594 to get the address of the global offset table (GOT) into register
1599 movl %ebx,x(%ebp) (optional)
1602 This code is with the rest of the prologue (at the end of the
1603 function), so we have to skip it to get to the first real
1604 instruction at the start of the function. */
1606 for (i
= 0; i
< 6; i
++)
1608 if (target_read_memory (pc
+ i
, &op
, 1))
1611 if (pic_pat
[i
] != op
)
1618 if (target_read_memory (pc
+ delta
, &op
, 1))
1621 if (op
== 0x89) /* movl %ebx, x(%ebp) */
1623 op
= read_memory_unsigned_integer (pc
+ delta
+ 1, 1, byte_order
);
1625 if (op
== 0x5d) /* One byte offset from %ebp. */
1627 else if (op
== 0x9d) /* Four byte offset from %ebp. */
1629 else /* Unexpected instruction. */
1632 if (target_read_memory (pc
+ delta
, &op
, 1))
1637 if (delta
> 0 && op
== 0x81
1638 && read_memory_unsigned_integer (pc
+ delta
+ 1, 1, byte_order
)
1645 /* If the function starts with a branch (to startup code at the end)
1646 the last instruction should bring us back to the first
1647 instruction of the real code. */
1648 if (i386_follow_jump (gdbarch
, start_pc
) != start_pc
)
1649 pc
= i386_follow_jump (gdbarch
, pc
);
1654 /* Check that the code pointed to by PC corresponds to a call to
1655 __main, skip it if so. Return PC otherwise. */
1658 i386_skip_main_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1660 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1663 if (target_read_memory (pc
, &op
, 1))
1669 if (target_read_memory (pc
+ 1, buf
, sizeof buf
) == 0)
1671 /* Make sure address is computed correctly as a 32bit
1672 integer even if CORE_ADDR is 64 bit wide. */
1673 struct minimal_symbol
*s
;
1674 CORE_ADDR call_dest
;
1676 call_dest
= pc
+ 5 + extract_signed_integer (buf
, 4, byte_order
);
1677 call_dest
= call_dest
& 0xffffffffU
;
1678 s
= lookup_minimal_symbol_by_pc (call_dest
);
1680 && SYMBOL_LINKAGE_NAME (s
) != NULL
1681 && strcmp (SYMBOL_LINKAGE_NAME (s
), "__main") == 0)
1689 /* This function is 64-bit safe. */
1692 i386_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1696 frame_unwind_register (next_frame
, gdbarch_pc_regnum (gdbarch
), buf
);
1697 return extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
1701 /* Normal frames. */
1704 i386_frame_cache_1 (struct frame_info
*this_frame
,
1705 struct i386_frame_cache
*cache
)
1707 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1708 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1712 cache
->pc
= get_frame_func (this_frame
);
1714 /* In principle, for normal frames, %ebp holds the frame pointer,
1715 which holds the base address for the current stack frame.
1716 However, for functions that don't need it, the frame pointer is
1717 optional. For these "frameless" functions the frame pointer is
1718 actually the frame pointer of the calling frame. Signal
1719 trampolines are just a special case of a "frameless" function.
1720 They (usually) share their frame pointer with the frame that was
1721 in progress when the signal occurred. */
1723 get_frame_register (this_frame
, I386_EBP_REGNUM
, buf
);
1724 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
);
1725 if (cache
->base
== 0)
1731 /* For normal frames, %eip is stored at 4(%ebp). */
1732 cache
->saved_regs
[I386_EIP_REGNUM
] = 4;
1735 i386_analyze_prologue (gdbarch
, cache
->pc
, get_frame_pc (this_frame
),
1738 if (cache
->locals
< 0)
1740 /* We didn't find a valid frame, which means that CACHE->base
1741 currently holds the frame pointer for our calling frame. If
1742 we're at the start of a function, or somewhere half-way its
1743 prologue, the function's frame probably hasn't been fully
1744 setup yet. Try to reconstruct the base address for the stack
1745 frame by looking at the stack pointer. For truly "frameless"
1746 functions this might work too. */
1748 if (cache
->saved_sp_reg
!= -1)
1750 /* Saved stack pointer has been saved. */
1751 get_frame_register (this_frame
, cache
->saved_sp_reg
, buf
);
1752 cache
->saved_sp
= extract_unsigned_integer (buf
, 4, byte_order
);
1754 /* We're halfway aligning the stack. */
1755 cache
->base
= ((cache
->saved_sp
- 4) & 0xfffffff0) - 4;
1756 cache
->saved_regs
[I386_EIP_REGNUM
] = cache
->saved_sp
- 4;
1758 /* This will be added back below. */
1759 cache
->saved_regs
[I386_EIP_REGNUM
] -= cache
->base
;
1761 else if (cache
->pc
!= 0
1762 || target_read_memory (get_frame_pc (this_frame
), buf
, 1))
1764 /* We're in a known function, but did not find a frame
1765 setup. Assume that the function does not use %ebp.
1766 Alternatively, we may have jumped to an invalid
1767 address; in that case there is definitely no new
1769 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
1770 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
)
1774 /* We're in an unknown function. We could not find the start
1775 of the function to analyze the prologue; our best option is
1776 to assume a typical frame layout with the caller's %ebp
1778 cache
->saved_regs
[I386_EBP_REGNUM
] = 0;
1781 if (cache
->saved_sp_reg
!= -1)
1783 /* Saved stack pointer has been saved (but the SAVED_SP_REG
1784 register may be unavailable). */
1785 if (cache
->saved_sp
== 0
1786 && deprecated_frame_register_read (this_frame
,
1787 cache
->saved_sp_reg
, buf
))
1788 cache
->saved_sp
= extract_unsigned_integer (buf
, 4, byte_order
);
1790 /* Now that we have the base address for the stack frame we can
1791 calculate the value of %esp in the calling frame. */
1792 else if (cache
->saved_sp
== 0)
1793 cache
->saved_sp
= cache
->base
+ 8;
1795 /* Adjust all the saved registers such that they contain addresses
1796 instead of offsets. */
1797 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
1798 if (cache
->saved_regs
[i
] != -1)
1799 cache
->saved_regs
[i
] += cache
->base
;
1804 static struct i386_frame_cache
*
1805 i386_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1807 volatile struct gdb_exception ex
;
1808 struct i386_frame_cache
*cache
;
1813 cache
= i386_alloc_frame_cache ();
1814 *this_cache
= cache
;
1816 TRY_CATCH (ex
, RETURN_MASK_ERROR
)
1818 i386_frame_cache_1 (this_frame
, cache
);
1820 if (ex
.reason
< 0 && ex
.error
!= NOT_AVAILABLE_ERROR
)
1821 throw_exception (ex
);
1827 i386_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
1828 struct frame_id
*this_id
)
1830 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1832 /* This marks the outermost frame. */
1833 if (cache
->base
== 0)
1836 /* See the end of i386_push_dummy_call. */
1837 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
1840 static enum unwind_stop_reason
1841 i386_frame_unwind_stop_reason (struct frame_info
*this_frame
,
1844 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1847 return UNWIND_UNAVAILABLE
;
1849 /* This marks the outermost frame. */
1850 if (cache
->base
== 0)
1851 return UNWIND_OUTERMOST
;
1853 return UNWIND_NO_REASON
;
1856 static struct value
*
1857 i386_frame_prev_register (struct frame_info
*this_frame
, void **this_cache
,
1860 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1862 gdb_assert (regnum
>= 0);
1864 /* The System V ABI says that:
1866 "The flags register contains the system flags, such as the
1867 direction flag and the carry flag. The direction flag must be
1868 set to the forward (that is, zero) direction before entry and
1869 upon exit from a function. Other user flags have no specified
1870 role in the standard calling sequence and are not preserved."
1872 To guarantee the "upon exit" part of that statement we fake a
1873 saved flags register that has its direction flag cleared.
1875 Note that GCC doesn't seem to rely on the fact that the direction
1876 flag is cleared after a function return; it always explicitly
1877 clears the flag before operations where it matters.
1879 FIXME: kettenis/20030316: I'm not quite sure whether this is the
1880 right thing to do. The way we fake the flags register here makes
1881 it impossible to change it. */
1883 if (regnum
== I386_EFLAGS_REGNUM
)
1887 val
= get_frame_register_unsigned (this_frame
, regnum
);
1889 return frame_unwind_got_constant (this_frame
, regnum
, val
);
1892 if (regnum
== I386_EIP_REGNUM
&& cache
->pc_in_eax
)
1893 return frame_unwind_got_register (this_frame
, regnum
, I386_EAX_REGNUM
);
1895 if (regnum
== I386_ESP_REGNUM
1896 && (cache
->saved_sp
!= 0 || cache
->saved_sp_reg
!= -1))
1898 /* If the SP has been saved, but we don't know where, then this
1899 means that SAVED_SP_REG register was found unavailable back
1900 when we built the cache. */
1901 if (cache
->saved_sp
== 0)
1902 return frame_unwind_got_register (this_frame
, regnum
,
1903 cache
->saved_sp_reg
);
1905 return frame_unwind_got_constant (this_frame
, regnum
,
1909 if (regnum
< I386_NUM_SAVED_REGS
&& cache
->saved_regs
[regnum
] != -1)
1910 return frame_unwind_got_memory (this_frame
, regnum
,
1911 cache
->saved_regs
[regnum
]);
1913 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
1916 static const struct frame_unwind i386_frame_unwind
=
1919 i386_frame_unwind_stop_reason
,
1921 i386_frame_prev_register
,
1923 default_frame_sniffer
1926 /* Normal frames, but in a function epilogue. */
1928 /* The epilogue is defined here as the 'ret' instruction, which will
1929 follow any instruction such as 'leave' or 'pop %ebp' that destroys
1930 the function's stack frame. */
1933 i386_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1936 struct symtab
*symtab
;
1938 symtab
= find_pc_symtab (pc
);
1939 if (symtab
&& symtab
->epilogue_unwind_valid
)
1942 if (target_read_memory (pc
, &insn
, 1))
1943 return 0; /* Can't read memory at pc. */
1945 if (insn
!= 0xc3) /* 'ret' instruction. */
1952 i386_epilogue_frame_sniffer (const struct frame_unwind
*self
,
1953 struct frame_info
*this_frame
,
1954 void **this_prologue_cache
)
1956 if (frame_relative_level (this_frame
) == 0)
1957 return i386_in_function_epilogue_p (get_frame_arch (this_frame
),
1958 get_frame_pc (this_frame
));
1963 static struct i386_frame_cache
*
1964 i386_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1966 volatile struct gdb_exception ex
;
1967 struct i386_frame_cache
*cache
;
1973 cache
= i386_alloc_frame_cache ();
1974 *this_cache
= cache
;
1976 TRY_CATCH (ex
, RETURN_MASK_ERROR
)
1978 cache
->pc
= get_frame_func (this_frame
);
1980 /* At this point the stack looks as if we just entered the
1981 function, with the return address at the top of the
1983 sp
= get_frame_register_unsigned (this_frame
, I386_ESP_REGNUM
);
1984 cache
->base
= sp
+ cache
->sp_offset
;
1985 cache
->saved_sp
= cache
->base
+ 8;
1986 cache
->saved_regs
[I386_EIP_REGNUM
] = cache
->base
+ 4;
1990 if (ex
.reason
< 0 && ex
.error
!= NOT_AVAILABLE_ERROR
)
1991 throw_exception (ex
);
1996 static enum unwind_stop_reason
1997 i386_epilogue_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2000 struct i386_frame_cache
*cache
=
2001 i386_epilogue_frame_cache (this_frame
, this_cache
);
2004 return UNWIND_UNAVAILABLE
;
2006 return UNWIND_NO_REASON
;
2010 i386_epilogue_frame_this_id (struct frame_info
*this_frame
,
2012 struct frame_id
*this_id
)
2014 struct i386_frame_cache
*cache
=
2015 i386_epilogue_frame_cache (this_frame
, this_cache
);
2020 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
2023 static struct value
*
2024 i386_epilogue_frame_prev_register (struct frame_info
*this_frame
,
2025 void **this_cache
, int regnum
)
2027 /* Make sure we've initialized the cache. */
2028 i386_epilogue_frame_cache (this_frame
, this_cache
);
2030 return i386_frame_prev_register (this_frame
, this_cache
, regnum
);
2033 static const struct frame_unwind i386_epilogue_frame_unwind
=
2036 i386_epilogue_frame_unwind_stop_reason
,
2037 i386_epilogue_frame_this_id
,
2038 i386_epilogue_frame_prev_register
,
2040 i386_epilogue_frame_sniffer
2044 /* Stack-based trampolines. */
2046 /* These trampolines are used on cross x86 targets, when taking the
2047 address of a nested function. When executing these trampolines,
2048 no stack frame is set up, so we are in a similar situation as in
2049 epilogues and i386_epilogue_frame_this_id can be re-used. */
2051 /* Static chain passed in register. */
2053 struct i386_insn i386_tramp_chain_in_reg_insns
[] =
2055 /* `movl imm32, %eax' and `movl imm32, %ecx' */
2056 { 5, { 0xb8 }, { 0xfe } },
2059 { 5, { 0xe9 }, { 0xff } },
2064 /* Static chain passed on stack (when regparm=3). */
2066 struct i386_insn i386_tramp_chain_on_stack_insns
[] =
2069 { 5, { 0x68 }, { 0xff } },
2072 { 5, { 0xe9 }, { 0xff } },
2077 /* Return whether PC points inside a stack trampoline. */
2080 i386_in_stack_tramp_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2085 /* A stack trampoline is detected if no name is associated
2086 to the current pc and if it points inside a trampoline
2089 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
2093 if (target_read_memory (pc
, &insn
, 1))
2096 if (!i386_match_insn_block (pc
, i386_tramp_chain_in_reg_insns
)
2097 && !i386_match_insn_block (pc
, i386_tramp_chain_on_stack_insns
))
2104 i386_stack_tramp_frame_sniffer (const struct frame_unwind
*self
,
2105 struct frame_info
*this_frame
,
2108 if (frame_relative_level (this_frame
) == 0)
2109 return i386_in_stack_tramp_p (get_frame_arch (this_frame
),
2110 get_frame_pc (this_frame
));
2115 static const struct frame_unwind i386_stack_tramp_frame_unwind
=
2118 i386_epilogue_frame_unwind_stop_reason
,
2119 i386_epilogue_frame_this_id
,
2120 i386_epilogue_frame_prev_register
,
2122 i386_stack_tramp_frame_sniffer
2125 /* Generate a bytecode expression to get the value of the saved PC. */
2128 i386_gen_return_address (struct gdbarch
*gdbarch
,
2129 struct agent_expr
*ax
, struct axs_value
*value
,
2132 /* The following sequence assumes the traditional use of the base
2134 ax_reg (ax
, I386_EBP_REGNUM
);
2136 ax_simple (ax
, aop_add
);
2137 value
->type
= register_type (gdbarch
, I386_EIP_REGNUM
);
2138 value
->kind
= axs_lvalue_memory
;
2142 /* Signal trampolines. */
2144 static struct i386_frame_cache
*
2145 i386_sigtramp_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2147 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2148 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2149 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2150 volatile struct gdb_exception ex
;
2151 struct i386_frame_cache
*cache
;
2158 cache
= i386_alloc_frame_cache ();
2160 TRY_CATCH (ex
, RETURN_MASK_ERROR
)
2162 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
2163 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
) - 4;
2165 addr
= tdep
->sigcontext_addr (this_frame
);
2166 if (tdep
->sc_reg_offset
)
2170 gdb_assert (tdep
->sc_num_regs
<= I386_NUM_SAVED_REGS
);
2172 for (i
= 0; i
< tdep
->sc_num_regs
; i
++)
2173 if (tdep
->sc_reg_offset
[i
] != -1)
2174 cache
->saved_regs
[i
] = addr
+ tdep
->sc_reg_offset
[i
];
2178 cache
->saved_regs
[I386_EIP_REGNUM
] = addr
+ tdep
->sc_pc_offset
;
2179 cache
->saved_regs
[I386_ESP_REGNUM
] = addr
+ tdep
->sc_sp_offset
;
2184 if (ex
.reason
< 0 && ex
.error
!= NOT_AVAILABLE_ERROR
)
2185 throw_exception (ex
);
2187 *this_cache
= cache
;
2191 static enum unwind_stop_reason
2192 i386_sigtramp_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2195 struct i386_frame_cache
*cache
=
2196 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2199 return UNWIND_UNAVAILABLE
;
2201 return UNWIND_NO_REASON
;
2205 i386_sigtramp_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2206 struct frame_id
*this_id
)
2208 struct i386_frame_cache
*cache
=
2209 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2214 /* See the end of i386_push_dummy_call. */
2215 (*this_id
) = frame_id_build (cache
->base
+ 8, get_frame_pc (this_frame
));
2218 static struct value
*
2219 i386_sigtramp_frame_prev_register (struct frame_info
*this_frame
,
2220 void **this_cache
, int regnum
)
2222 /* Make sure we've initialized the cache. */
2223 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2225 return i386_frame_prev_register (this_frame
, this_cache
, regnum
);
2229 i386_sigtramp_frame_sniffer (const struct frame_unwind
*self
,
2230 struct frame_info
*this_frame
,
2231 void **this_prologue_cache
)
2233 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (this_frame
));
2235 /* We shouldn't even bother if we don't have a sigcontext_addr
2237 if (tdep
->sigcontext_addr
== NULL
)
2240 if (tdep
->sigtramp_p
!= NULL
)
2242 if (tdep
->sigtramp_p (this_frame
))
2246 if (tdep
->sigtramp_start
!= 0)
2248 CORE_ADDR pc
= get_frame_pc (this_frame
);
2250 gdb_assert (tdep
->sigtramp_end
!= 0);
2251 if (pc
>= tdep
->sigtramp_start
&& pc
< tdep
->sigtramp_end
)
2258 static const struct frame_unwind i386_sigtramp_frame_unwind
=
2261 i386_sigtramp_frame_unwind_stop_reason
,
2262 i386_sigtramp_frame_this_id
,
2263 i386_sigtramp_frame_prev_register
,
2265 i386_sigtramp_frame_sniffer
2270 i386_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
2272 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
2277 static const struct frame_base i386_frame_base
=
2280 i386_frame_base_address
,
2281 i386_frame_base_address
,
2282 i386_frame_base_address
2285 static struct frame_id
2286 i386_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
2290 fp
= get_frame_register_unsigned (this_frame
, I386_EBP_REGNUM
);
2292 /* See the end of i386_push_dummy_call. */
2293 return frame_id_build (fp
+ 8, get_frame_pc (this_frame
));
2296 /* _Decimal128 function return values need 16-byte alignment on the
2300 i386_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
2302 return sp
& -(CORE_ADDR
)16;
2306 /* Figure out where the longjmp will land. Slurp the args out of the
2307 stack. We expect the first arg to be a pointer to the jmp_buf
2308 structure from which we extract the address that we will land at.
2309 This address is copied into PC. This routine returns non-zero on
2313 i386_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
2316 CORE_ADDR sp
, jb_addr
;
2317 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2318 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2319 int jb_pc_offset
= gdbarch_tdep (gdbarch
)->jb_pc_offset
;
2321 /* If JB_PC_OFFSET is -1, we have no way to find out where the
2322 longjmp will land. */
2323 if (jb_pc_offset
== -1)
2326 get_frame_register (frame
, I386_ESP_REGNUM
, buf
);
2327 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
2328 if (target_read_memory (sp
+ 4, buf
, 4))
2331 jb_addr
= extract_unsigned_integer (buf
, 4, byte_order
);
2332 if (target_read_memory (jb_addr
+ jb_pc_offset
, buf
, 4))
2335 *pc
= extract_unsigned_integer (buf
, 4, byte_order
);
2340 /* Check whether TYPE must be 16-byte-aligned when passed as a
2341 function argument. 16-byte vectors, _Decimal128 and structures or
2342 unions containing such types must be 16-byte-aligned; other
2343 arguments are 4-byte-aligned. */
2346 i386_16_byte_align_p (struct type
*type
)
2348 type
= check_typedef (type
);
2349 if ((TYPE_CODE (type
) == TYPE_CODE_DECFLOAT
2350 || (TYPE_CODE (type
) == TYPE_CODE_ARRAY
&& TYPE_VECTOR (type
)))
2351 && TYPE_LENGTH (type
) == 16)
2353 if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
2354 return i386_16_byte_align_p (TYPE_TARGET_TYPE (type
));
2355 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
2356 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
2359 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
2361 if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type
, i
)))
2368 /* Implementation for set_gdbarch_push_dummy_code. */
2371 i386_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
, CORE_ADDR funaddr
,
2372 struct value
**args
, int nargs
, struct type
*value_type
,
2373 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
,
2374 struct regcache
*regcache
)
2376 /* Use 0xcc breakpoint - 1 byte. */
2380 /* Keep the stack aligned. */
2385 i386_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2386 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
2387 struct value
**args
, CORE_ADDR sp
, int struct_return
,
2388 CORE_ADDR struct_addr
)
2390 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2396 /* Determine the total space required for arguments and struct
2397 return address in a first pass (allowing for 16-byte-aligned
2398 arguments), then push arguments in a second pass. */
2400 for (write_pass
= 0; write_pass
< 2; write_pass
++)
2402 int args_space_used
= 0;
2408 /* Push value address. */
2409 store_unsigned_integer (buf
, 4, byte_order
, struct_addr
);
2410 write_memory (sp
, buf
, 4);
2411 args_space_used
+= 4;
2417 for (i
= 0; i
< nargs
; i
++)
2419 int len
= TYPE_LENGTH (value_enclosing_type (args
[i
]));
2423 if (i386_16_byte_align_p (value_enclosing_type (args
[i
])))
2424 args_space_used
= align_up (args_space_used
, 16);
2426 write_memory (sp
+ args_space_used
,
2427 value_contents_all (args
[i
]), len
);
2428 /* The System V ABI says that:
2430 "An argument's size is increased, if necessary, to make it a
2431 multiple of [32-bit] words. This may require tail padding,
2432 depending on the size of the argument."
2434 This makes sure the stack stays word-aligned. */
2435 args_space_used
+= align_up (len
, 4);
2439 if (i386_16_byte_align_p (value_enclosing_type (args
[i
])))
2440 args_space
= align_up (args_space
, 16);
2441 args_space
+= align_up (len
, 4);
2449 /* The original System V ABI only requires word alignment,
2450 but modern incarnations need 16-byte alignment in order
2451 to support SSE. Since wasting a few bytes here isn't
2452 harmful we unconditionally enforce 16-byte alignment. */
2457 /* Store return address. */
2459 store_unsigned_integer (buf
, 4, byte_order
, bp_addr
);
2460 write_memory (sp
, buf
, 4);
2462 /* Finally, update the stack pointer... */
2463 store_unsigned_integer (buf
, 4, byte_order
, sp
);
2464 regcache_cooked_write (regcache
, I386_ESP_REGNUM
, buf
);
2466 /* ...and fake a frame pointer. */
2467 regcache_cooked_write (regcache
, I386_EBP_REGNUM
, buf
);
2469 /* MarkK wrote: This "+ 8" is all over the place:
2470 (i386_frame_this_id, i386_sigtramp_frame_this_id,
2471 i386_dummy_id). It's there, since all frame unwinders for
2472 a given target have to agree (within a certain margin) on the
2473 definition of the stack address of a frame. Otherwise frame id
2474 comparison might not work correctly. Since DWARF2/GCC uses the
2475 stack address *before* the function call as a frame's CFA. On
2476 the i386, when %ebp is used as a frame pointer, the offset
2477 between the contents %ebp and the CFA as defined by GCC. */
2481 /* These registers are used for returning integers (and on some
2482 targets also for returning `struct' and `union' values when their
2483 size and alignment match an integer type). */
2484 #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */
2485 #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */
2487 /* Read, for architecture GDBARCH, a function return value of TYPE
2488 from REGCACHE, and copy that into VALBUF. */
2491 i386_extract_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
2492 struct regcache
*regcache
, gdb_byte
*valbuf
)
2494 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2495 int len
= TYPE_LENGTH (type
);
2496 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
2498 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2500 if (tdep
->st0_regnum
< 0)
2502 warning (_("Cannot find floating-point return value."));
2503 memset (valbuf
, 0, len
);
2507 /* Floating-point return values can be found in %st(0). Convert
2508 its contents to the desired type. This is probably not
2509 exactly how it would happen on the target itself, but it is
2510 the best we can do. */
2511 regcache_raw_read (regcache
, I386_ST0_REGNUM
, buf
);
2512 convert_typed_floating (buf
, i387_ext_type (gdbarch
), valbuf
, type
);
2516 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
2517 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
2519 if (len
<= low_size
)
2521 regcache_raw_read (regcache
, LOW_RETURN_REGNUM
, buf
);
2522 memcpy (valbuf
, buf
, len
);
2524 else if (len
<= (low_size
+ high_size
))
2526 regcache_raw_read (regcache
, LOW_RETURN_REGNUM
, buf
);
2527 memcpy (valbuf
, buf
, low_size
);
2528 regcache_raw_read (regcache
, HIGH_RETURN_REGNUM
, buf
);
2529 memcpy (valbuf
+ low_size
, buf
, len
- low_size
);
2532 internal_error (__FILE__
, __LINE__
,
2533 _("Cannot extract return value of %d bytes long."),
2538 /* Write, for architecture GDBARCH, a function return value of TYPE
2539 from VALBUF into REGCACHE. */
2542 i386_store_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
2543 struct regcache
*regcache
, const gdb_byte
*valbuf
)
2545 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2546 int len
= TYPE_LENGTH (type
);
2548 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2551 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
2553 if (tdep
->st0_regnum
< 0)
2555 warning (_("Cannot set floating-point return value."));
2559 /* Returning floating-point values is a bit tricky. Apart from
2560 storing the return value in %st(0), we have to simulate the
2561 state of the FPU at function return point. */
2563 /* Convert the value found in VALBUF to the extended
2564 floating-point format used by the FPU. This is probably
2565 not exactly how it would happen on the target itself, but
2566 it is the best we can do. */
2567 convert_typed_floating (valbuf
, type
, buf
, i387_ext_type (gdbarch
));
2568 regcache_raw_write (regcache
, I386_ST0_REGNUM
, buf
);
2570 /* Set the top of the floating-point register stack to 7. The
2571 actual value doesn't really matter, but 7 is what a normal
2572 function return would end up with if the program started out
2573 with a freshly initialized FPU. */
2574 regcache_raw_read_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), &fstat
);
2576 regcache_raw_write_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), fstat
);
2578 /* Mark %st(1) through %st(7) as empty. Since we set the top of
2579 the floating-point register stack to 7, the appropriate value
2580 for the tag word is 0x3fff. */
2581 regcache_raw_write_unsigned (regcache
, I387_FTAG_REGNUM (tdep
), 0x3fff);
2585 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
2586 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
2588 if (len
<= low_size
)
2589 regcache_raw_write_part (regcache
, LOW_RETURN_REGNUM
, 0, len
, valbuf
);
2590 else if (len
<= (low_size
+ high_size
))
2592 regcache_raw_write (regcache
, LOW_RETURN_REGNUM
, valbuf
);
2593 regcache_raw_write_part (regcache
, HIGH_RETURN_REGNUM
, 0,
2594 len
- low_size
, valbuf
+ low_size
);
2597 internal_error (__FILE__
, __LINE__
,
2598 _("Cannot store return value of %d bytes long."), len
);
2603 /* This is the variable that is set with "set struct-convention", and
2604 its legitimate values. */
2605 static const char default_struct_convention
[] = "default";
2606 static const char pcc_struct_convention
[] = "pcc";
2607 static const char reg_struct_convention
[] = "reg";
2608 static const char *const valid_conventions
[] =
2610 default_struct_convention
,
2611 pcc_struct_convention
,
2612 reg_struct_convention
,
2615 static const char *struct_convention
= default_struct_convention
;
2617 /* Return non-zero if TYPE, which is assumed to be a structure,
2618 a union type, or an array type, should be returned in registers
2619 for architecture GDBARCH. */
2622 i386_reg_struct_return_p (struct gdbarch
*gdbarch
, struct type
*type
)
2624 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2625 enum type_code code
= TYPE_CODE (type
);
2626 int len
= TYPE_LENGTH (type
);
2628 gdb_assert (code
== TYPE_CODE_STRUCT
2629 || code
== TYPE_CODE_UNION
2630 || code
== TYPE_CODE_ARRAY
);
2632 if (struct_convention
== pcc_struct_convention
2633 || (struct_convention
== default_struct_convention
2634 && tdep
->struct_return
== pcc_struct_return
))
2637 /* Structures consisting of a single `float', `double' or 'long
2638 double' member are returned in %st(0). */
2639 if (code
== TYPE_CODE_STRUCT
&& TYPE_NFIELDS (type
) == 1)
2641 type
= check_typedef (TYPE_FIELD_TYPE (type
, 0));
2642 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2643 return (len
== 4 || len
== 8 || len
== 12);
2646 return (len
== 1 || len
== 2 || len
== 4 || len
== 8);
2649 /* Determine, for architecture GDBARCH, how a return value of TYPE
2650 should be returned. If it is supposed to be returned in registers,
2651 and READBUF is non-zero, read the appropriate value from REGCACHE,
2652 and copy it into READBUF. If WRITEBUF is non-zero, write the value
2653 from WRITEBUF into REGCACHE. */
2655 static enum return_value_convention
2656 i386_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
2657 struct type
*type
, struct regcache
*regcache
,
2658 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2660 enum type_code code
= TYPE_CODE (type
);
2662 if (((code
== TYPE_CODE_STRUCT
2663 || code
== TYPE_CODE_UNION
2664 || code
== TYPE_CODE_ARRAY
)
2665 && !i386_reg_struct_return_p (gdbarch
, type
))
2666 /* Complex double and long double uses the struct return covention. */
2667 || (code
== TYPE_CODE_COMPLEX
&& TYPE_LENGTH (type
) == 16)
2668 || (code
== TYPE_CODE_COMPLEX
&& TYPE_LENGTH (type
) == 24)
2669 /* 128-bit decimal float uses the struct return convention. */
2670 || (code
== TYPE_CODE_DECFLOAT
&& TYPE_LENGTH (type
) == 16))
2672 /* The System V ABI says that:
2674 "A function that returns a structure or union also sets %eax
2675 to the value of the original address of the caller's area
2676 before it returns. Thus when the caller receives control
2677 again, the address of the returned object resides in register
2678 %eax and can be used to access the object."
2680 So the ABI guarantees that we can always find the return
2681 value just after the function has returned. */
2683 /* Note that the ABI doesn't mention functions returning arrays,
2684 which is something possible in certain languages such as Ada.
2685 In this case, the value is returned as if it was wrapped in
2686 a record, so the convention applied to records also applies
2693 regcache_raw_read_unsigned (regcache
, I386_EAX_REGNUM
, &addr
);
2694 read_memory (addr
, readbuf
, TYPE_LENGTH (type
));
2697 return RETURN_VALUE_ABI_RETURNS_ADDRESS
;
2700 /* This special case is for structures consisting of a single
2701 `float', `double' or 'long double' member. These structures are
2702 returned in %st(0). For these structures, we call ourselves
2703 recursively, changing TYPE into the type of the first member of
2704 the structure. Since that should work for all structures that
2705 have only one member, we don't bother to check the member's type
2707 if (code
== TYPE_CODE_STRUCT
&& TYPE_NFIELDS (type
) == 1)
2709 type
= check_typedef (TYPE_FIELD_TYPE (type
, 0));
2710 return i386_return_value (gdbarch
, function
, type
, regcache
,
2715 i386_extract_return_value (gdbarch
, type
, regcache
, readbuf
);
2717 i386_store_return_value (gdbarch
, type
, regcache
, writebuf
);
2719 return RETURN_VALUE_REGISTER_CONVENTION
;
2724 i387_ext_type (struct gdbarch
*gdbarch
)
2726 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2728 if (!tdep
->i387_ext_type
)
2730 tdep
->i387_ext_type
= tdesc_find_type (gdbarch
, "i387_ext");
2731 gdb_assert (tdep
->i387_ext_type
!= NULL
);
2734 return tdep
->i387_ext_type
;
2737 /* Construct vector type for pseudo YMM registers. We can't use
2738 tdesc_find_type since YMM isn't described in target description. */
2740 static struct type
*
2741 i386_ymm_type (struct gdbarch
*gdbarch
)
2743 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2745 if (!tdep
->i386_ymm_type
)
2747 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2749 /* The type we're building is this: */
2751 union __gdb_builtin_type_vec256i
2753 int128_t uint128
[2];
2754 int64_t v2_int64
[4];
2755 int32_t v4_int32
[8];
2756 int16_t v8_int16
[16];
2757 int8_t v16_int8
[32];
2758 double v2_double
[4];
2765 t
= arch_composite_type (gdbarch
,
2766 "__gdb_builtin_type_vec256i", TYPE_CODE_UNION
);
2767 append_composite_type_field (t
, "v8_float",
2768 init_vector_type (bt
->builtin_float
, 8));
2769 append_composite_type_field (t
, "v4_double",
2770 init_vector_type (bt
->builtin_double
, 4));
2771 append_composite_type_field (t
, "v32_int8",
2772 init_vector_type (bt
->builtin_int8
, 32));
2773 append_composite_type_field (t
, "v16_int16",
2774 init_vector_type (bt
->builtin_int16
, 16));
2775 append_composite_type_field (t
, "v8_int32",
2776 init_vector_type (bt
->builtin_int32
, 8));
2777 append_composite_type_field (t
, "v4_int64",
2778 init_vector_type (bt
->builtin_int64
, 4));
2779 append_composite_type_field (t
, "v2_int128",
2780 init_vector_type (bt
->builtin_int128
, 2));
2782 TYPE_VECTOR (t
) = 1;
2783 TYPE_NAME (t
) = "builtin_type_vec256i";
2784 tdep
->i386_ymm_type
= t
;
2787 return tdep
->i386_ymm_type
;
2790 /* Construct vector type for MMX registers. */
2791 static struct type
*
2792 i386_mmx_type (struct gdbarch
*gdbarch
)
2794 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2796 if (!tdep
->i386_mmx_type
)
2798 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2800 /* The type we're building is this: */
2802 union __gdb_builtin_type_vec64i
2805 int32_t v2_int32
[2];
2806 int16_t v4_int16
[4];
2813 t
= arch_composite_type (gdbarch
,
2814 "__gdb_builtin_type_vec64i", TYPE_CODE_UNION
);
2816 append_composite_type_field (t
, "uint64", bt
->builtin_int64
);
2817 append_composite_type_field (t
, "v2_int32",
2818 init_vector_type (bt
->builtin_int32
, 2));
2819 append_composite_type_field (t
, "v4_int16",
2820 init_vector_type (bt
->builtin_int16
, 4));
2821 append_composite_type_field (t
, "v8_int8",
2822 init_vector_type (bt
->builtin_int8
, 8));
2824 TYPE_VECTOR (t
) = 1;
2825 TYPE_NAME (t
) = "builtin_type_vec64i";
2826 tdep
->i386_mmx_type
= t
;
2829 return tdep
->i386_mmx_type
;
2832 /* Return the GDB type object for the "standard" data type of data in
2836 i386_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
2838 if (i386_mmx_regnum_p (gdbarch
, regnum
))
2839 return i386_mmx_type (gdbarch
);
2840 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
2841 return i386_ymm_type (gdbarch
);
2844 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2845 if (i386_byte_regnum_p (gdbarch
, regnum
))
2846 return bt
->builtin_int8
;
2847 else if (i386_word_regnum_p (gdbarch
, regnum
))
2848 return bt
->builtin_int16
;
2849 else if (i386_dword_regnum_p (gdbarch
, regnum
))
2850 return bt
->builtin_int32
;
2853 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
2856 /* Map a cooked register onto a raw register or memory. For the i386,
2857 the MMX registers need to be mapped onto floating point registers. */
2860 i386_mmx_regnum_to_fp_regnum (struct regcache
*regcache
, int regnum
)
2862 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_regcache_arch (regcache
));
2867 mmxreg
= regnum
- tdep
->mm0_regnum
;
2868 regcache_raw_read_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), &fstat
);
2869 tos
= (fstat
>> 11) & 0x7;
2870 fpreg
= (mmxreg
+ tos
) % 8;
2872 return (I387_ST0_REGNUM (tdep
) + fpreg
);
2875 /* A helper function for us by i386_pseudo_register_read_value and
2876 amd64_pseudo_register_read_value. It does all the work but reads
2877 the data into an already-allocated value. */
2880 i386_pseudo_register_read_into_value (struct gdbarch
*gdbarch
,
2881 struct regcache
*regcache
,
2883 struct value
*result_value
)
2885 gdb_byte raw_buf
[MAX_REGISTER_SIZE
];
2886 enum register_status status
;
2887 gdb_byte
*buf
= value_contents_raw (result_value
);
2889 if (i386_mmx_regnum_p (gdbarch
, regnum
))
2891 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
2893 /* Extract (always little endian). */
2894 status
= regcache_raw_read (regcache
, fpnum
, raw_buf
);
2895 if (status
!= REG_VALID
)
2896 mark_value_bytes_unavailable (result_value
, 0,
2897 TYPE_LENGTH (value_type (result_value
)));
2899 memcpy (buf
, raw_buf
, register_size (gdbarch
, regnum
));
2903 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2905 if (i386_ymm_regnum_p (gdbarch
, regnum
))
2907 regnum
-= tdep
->ymm0_regnum
;
2909 /* Extract (always little endian). Read lower 128bits. */
2910 status
= regcache_raw_read (regcache
,
2911 I387_XMM0_REGNUM (tdep
) + regnum
,
2913 if (status
!= REG_VALID
)
2914 mark_value_bytes_unavailable (result_value
, 0, 16);
2916 memcpy (buf
, raw_buf
, 16);
2917 /* Read upper 128bits. */
2918 status
= regcache_raw_read (regcache
,
2919 tdep
->ymm0h_regnum
+ regnum
,
2921 if (status
!= REG_VALID
)
2922 mark_value_bytes_unavailable (result_value
, 16, 32);
2924 memcpy (buf
+ 16, raw_buf
, 16);
2926 else if (i386_word_regnum_p (gdbarch
, regnum
))
2928 int gpnum
= regnum
- tdep
->ax_regnum
;
2930 /* Extract (always little endian). */
2931 status
= regcache_raw_read (regcache
, gpnum
, raw_buf
);
2932 if (status
!= REG_VALID
)
2933 mark_value_bytes_unavailable (result_value
, 0,
2934 TYPE_LENGTH (value_type (result_value
)));
2936 memcpy (buf
, raw_buf
, 2);
2938 else if (i386_byte_regnum_p (gdbarch
, regnum
))
2940 /* Check byte pseudo registers last since this function will
2941 be called from amd64_pseudo_register_read, which handles
2942 byte pseudo registers differently. */
2943 int gpnum
= regnum
- tdep
->al_regnum
;
2945 /* Extract (always little endian). We read both lower and
2947 status
= regcache_raw_read (regcache
, gpnum
% 4, raw_buf
);
2948 if (status
!= REG_VALID
)
2949 mark_value_bytes_unavailable (result_value
, 0,
2950 TYPE_LENGTH (value_type (result_value
)));
2951 else if (gpnum
>= 4)
2952 memcpy (buf
, raw_buf
+ 1, 1);
2954 memcpy (buf
, raw_buf
, 1);
2957 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
2961 static struct value
*
2962 i386_pseudo_register_read_value (struct gdbarch
*gdbarch
,
2963 struct regcache
*regcache
,
2966 struct value
*result
;
2968 result
= allocate_value (register_type (gdbarch
, regnum
));
2969 VALUE_LVAL (result
) = lval_register
;
2970 VALUE_REGNUM (result
) = regnum
;
2972 i386_pseudo_register_read_into_value (gdbarch
, regcache
, regnum
, result
);
2978 i386_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2979 int regnum
, const gdb_byte
*buf
)
2981 gdb_byte raw_buf
[MAX_REGISTER_SIZE
];
2983 if (i386_mmx_regnum_p (gdbarch
, regnum
))
2985 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
2988 regcache_raw_read (regcache
, fpnum
, raw_buf
);
2989 /* ... Modify ... (always little endian). */
2990 memcpy (raw_buf
, buf
, register_size (gdbarch
, regnum
));
2992 regcache_raw_write (regcache
, fpnum
, raw_buf
);
2996 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2998 if (i386_ymm_regnum_p (gdbarch
, regnum
))
3000 regnum
-= tdep
->ymm0_regnum
;
3002 /* ... Write lower 128bits. */
3003 regcache_raw_write (regcache
,
3004 I387_XMM0_REGNUM (tdep
) + regnum
,
3006 /* ... Write upper 128bits. */
3007 regcache_raw_write (regcache
,
3008 tdep
->ymm0h_regnum
+ regnum
,
3011 else if (i386_word_regnum_p (gdbarch
, regnum
))
3013 int gpnum
= regnum
- tdep
->ax_regnum
;
3016 regcache_raw_read (regcache
, gpnum
, raw_buf
);
3017 /* ... Modify ... (always little endian). */
3018 memcpy (raw_buf
, buf
, 2);
3020 regcache_raw_write (regcache
, gpnum
, raw_buf
);
3022 else if (i386_byte_regnum_p (gdbarch
, regnum
))
3024 /* Check byte pseudo registers last since this function will
3025 be called from amd64_pseudo_register_read, which handles
3026 byte pseudo registers differently. */
3027 int gpnum
= regnum
- tdep
->al_regnum
;
3029 /* Read ... We read both lower and upper registers. */
3030 regcache_raw_read (regcache
, gpnum
% 4, raw_buf
);
3031 /* ... Modify ... (always little endian). */
3033 memcpy (raw_buf
+ 1, buf
, 1);
3035 memcpy (raw_buf
, buf
, 1);
3037 regcache_raw_write (regcache
, gpnum
% 4, raw_buf
);
3040 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
3045 /* Return the register number of the register allocated by GCC after
3046 REGNUM, or -1 if there is no such register. */
3049 i386_next_regnum (int regnum
)
3051 /* GCC allocates the registers in the order:
3053 %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ...
3055 Since storing a variable in %esp doesn't make any sense we return
3056 -1 for %ebp and for %esp itself. */
3057 static int next_regnum
[] =
3059 I386_EDX_REGNUM
, /* Slot for %eax. */
3060 I386_EBX_REGNUM
, /* Slot for %ecx. */
3061 I386_ECX_REGNUM
, /* Slot for %edx. */
3062 I386_ESI_REGNUM
, /* Slot for %ebx. */
3063 -1, -1, /* Slots for %esp and %ebp. */
3064 I386_EDI_REGNUM
, /* Slot for %esi. */
3065 I386_EBP_REGNUM
/* Slot for %edi. */
3068 if (regnum
>= 0 && regnum
< sizeof (next_regnum
) / sizeof (next_regnum
[0]))
3069 return next_regnum
[regnum
];
3074 /* Return nonzero if a value of type TYPE stored in register REGNUM
3075 needs any special handling. */
3078 i386_convert_register_p (struct gdbarch
*gdbarch
,
3079 int regnum
, struct type
*type
)
3081 int len
= TYPE_LENGTH (type
);
3083 /* Values may be spread across multiple registers. Most debugging
3084 formats aren't expressive enough to specify the locations, so
3085 some heuristics is involved. Right now we only handle types that
3086 have a length that is a multiple of the word size, since GCC
3087 doesn't seem to put any other types into registers. */
3088 if (len
> 4 && len
% 4 == 0)
3090 int last_regnum
= regnum
;
3094 last_regnum
= i386_next_regnum (last_regnum
);
3098 if (last_regnum
!= -1)
3102 return i387_convert_register_p (gdbarch
, regnum
, type
);
3105 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
3106 return its contents in TO. */
3109 i386_register_to_value (struct frame_info
*frame
, int regnum
,
3110 struct type
*type
, gdb_byte
*to
,
3111 int *optimizedp
, int *unavailablep
)
3113 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3114 int len
= TYPE_LENGTH (type
);
3116 if (i386_fp_regnum_p (gdbarch
, regnum
))
3117 return i387_register_to_value (frame
, regnum
, type
, to
,
3118 optimizedp
, unavailablep
);
3120 /* Read a value spread across multiple registers. */
3122 gdb_assert (len
> 4 && len
% 4 == 0);
3126 gdb_assert (regnum
!= -1);
3127 gdb_assert (register_size (gdbarch
, regnum
) == 4);
3129 if (!get_frame_register_bytes (frame
, regnum
, 0,
3130 register_size (gdbarch
, regnum
),
3131 to
, optimizedp
, unavailablep
))
3134 regnum
= i386_next_regnum (regnum
);
3139 *optimizedp
= *unavailablep
= 0;
3143 /* Write the contents FROM of a value of type TYPE into register
3144 REGNUM in frame FRAME. */
3147 i386_value_to_register (struct frame_info
*frame
, int regnum
,
3148 struct type
*type
, const gdb_byte
*from
)
3150 int len
= TYPE_LENGTH (type
);
3152 if (i386_fp_regnum_p (get_frame_arch (frame
), regnum
))
3154 i387_value_to_register (frame
, regnum
, type
, from
);
3158 /* Write a value spread across multiple registers. */
3160 gdb_assert (len
> 4 && len
% 4 == 0);
3164 gdb_assert (regnum
!= -1);
3165 gdb_assert (register_size (get_frame_arch (frame
), regnum
) == 4);
3167 put_frame_register (frame
, regnum
, from
);
3168 regnum
= i386_next_regnum (regnum
);
3174 /* Supply register REGNUM from the buffer specified by GREGS and LEN
3175 in the general-purpose register set REGSET to register cache
3176 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3179 i386_supply_gregset (const struct regset
*regset
, struct regcache
*regcache
,
3180 int regnum
, const void *gregs
, size_t len
)
3182 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
3183 const gdb_byte
*regs
= gregs
;
3186 gdb_assert (len
== tdep
->sizeof_gregset
);
3188 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
3190 if ((regnum
== i
|| regnum
== -1)
3191 && tdep
->gregset_reg_offset
[i
] != -1)
3192 regcache_raw_supply (regcache
, i
, regs
+ tdep
->gregset_reg_offset
[i
]);
3196 /* Collect register REGNUM from the register cache REGCACHE and store
3197 it in the buffer specified by GREGS and LEN as described by the
3198 general-purpose register set REGSET. If REGNUM is -1, do this for
3199 all registers in REGSET. */
3202 i386_collect_gregset (const struct regset
*regset
,
3203 const struct regcache
*regcache
,
3204 int regnum
, void *gregs
, size_t len
)
3206 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
3207 gdb_byte
*regs
= gregs
;
3210 gdb_assert (len
== tdep
->sizeof_gregset
);
3212 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
3214 if ((regnum
== i
|| regnum
== -1)
3215 && tdep
->gregset_reg_offset
[i
] != -1)
3216 regcache_raw_collect (regcache
, i
, regs
+ tdep
->gregset_reg_offset
[i
]);
3220 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
3221 in the floating-point register set REGSET to register cache
3222 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3225 i386_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
3226 int regnum
, const void *fpregs
, size_t len
)
3228 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
3230 if (len
== I387_SIZEOF_FXSAVE
)
3232 i387_supply_fxsave (regcache
, regnum
, fpregs
);
3236 gdb_assert (len
== tdep
->sizeof_fpregset
);
3237 i387_supply_fsave (regcache
, regnum
, fpregs
);
3240 /* Collect register REGNUM from the register cache REGCACHE and store
3241 it in the buffer specified by FPREGS and LEN as described by the
3242 floating-point register set REGSET. If REGNUM is -1, do this for
3243 all registers in REGSET. */
3246 i386_collect_fpregset (const struct regset
*regset
,
3247 const struct regcache
*regcache
,
3248 int regnum
, void *fpregs
, size_t len
)
3250 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
3252 if (len
== I387_SIZEOF_FXSAVE
)
3254 i387_collect_fxsave (regcache
, regnum
, fpregs
);
3258 gdb_assert (len
== tdep
->sizeof_fpregset
);
3259 i387_collect_fsave (regcache
, regnum
, fpregs
);
3262 /* Similar to i386_supply_fpregset, but use XSAVE extended state. */
3265 i386_supply_xstateregset (const struct regset
*regset
,
3266 struct regcache
*regcache
, int regnum
,
3267 const void *xstateregs
, size_t len
)
3269 i387_supply_xsave (regcache
, regnum
, xstateregs
);
3272 /* Similar to i386_collect_fpregset , but use XSAVE extended state. */
3275 i386_collect_xstateregset (const struct regset
*regset
,
3276 const struct regcache
*regcache
,
3277 int regnum
, void *xstateregs
, size_t len
)
3279 i387_collect_xsave (regcache
, regnum
, xstateregs
, 1);
3282 /* Return the appropriate register set for the core section identified
3283 by SECT_NAME and SECT_SIZE. */
3285 const struct regset
*
3286 i386_regset_from_core_section (struct gdbarch
*gdbarch
,
3287 const char *sect_name
, size_t sect_size
)
3289 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3291 if (strcmp (sect_name
, ".reg") == 0 && sect_size
== tdep
->sizeof_gregset
)
3293 if (tdep
->gregset
== NULL
)
3294 tdep
->gregset
= regset_alloc (gdbarch
, i386_supply_gregset
,
3295 i386_collect_gregset
);
3296 return tdep
->gregset
;
3299 if ((strcmp (sect_name
, ".reg2") == 0 && sect_size
== tdep
->sizeof_fpregset
)
3300 || (strcmp (sect_name
, ".reg-xfp") == 0
3301 && sect_size
== I387_SIZEOF_FXSAVE
))
3303 if (tdep
->fpregset
== NULL
)
3304 tdep
->fpregset
= regset_alloc (gdbarch
, i386_supply_fpregset
,
3305 i386_collect_fpregset
);
3306 return tdep
->fpregset
;
3309 if (strcmp (sect_name
, ".reg-xstate") == 0)
3311 if (tdep
->xstateregset
== NULL
)
3312 tdep
->xstateregset
= regset_alloc (gdbarch
,
3313 i386_supply_xstateregset
,
3314 i386_collect_xstateregset
);
3316 return tdep
->xstateregset
;
3323 /* Stuff for WIN32 PE style DLL's but is pretty generic really. */
3326 i386_pe_skip_trampoline_code (struct frame_info
*frame
,
3327 CORE_ADDR pc
, char *name
)
3329 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3330 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3333 if (pc
&& read_memory_unsigned_integer (pc
, 2, byte_order
) == 0x25ff)
3335 unsigned long indirect
=
3336 read_memory_unsigned_integer (pc
+ 2, 4, byte_order
);
3337 struct minimal_symbol
*indsym
=
3338 indirect
? lookup_minimal_symbol_by_pc (indirect
) : 0;
3339 const char *symname
= indsym
? SYMBOL_LINKAGE_NAME (indsym
) : 0;
3343 if (strncmp (symname
, "__imp_", 6) == 0
3344 || strncmp (symname
, "_imp_", 5) == 0)
3346 read_memory_unsigned_integer (indirect
, 4, byte_order
);
3349 return 0; /* Not a trampoline. */
3353 /* Return whether the THIS_FRAME corresponds to a sigtramp
3357 i386_sigtramp_p (struct frame_info
*this_frame
)
3359 CORE_ADDR pc
= get_frame_pc (this_frame
);
3362 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
3363 return (name
&& strcmp ("_sigtramp", name
) == 0);
3367 /* We have two flavours of disassembly. The machinery on this page
3368 deals with switching between those. */
3371 i386_print_insn (bfd_vma pc
, struct disassemble_info
*info
)
3373 gdb_assert (disassembly_flavor
== att_flavor
3374 || disassembly_flavor
== intel_flavor
);
3376 /* FIXME: kettenis/20020915: Until disassembler_options is properly
3377 constified, cast to prevent a compiler warning. */
3378 info
->disassembler_options
= (char *) disassembly_flavor
;
3380 return print_insn_i386 (pc
, info
);
3384 /* There are a few i386 architecture variants that differ only
3385 slightly from the generic i386 target. For now, we don't give them
3386 their own source file, but include them here. As a consequence,
3387 they'll always be included. */
3389 /* System V Release 4 (SVR4). */
3391 /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp
3395 i386_svr4_sigtramp_p (struct frame_info
*this_frame
)
3397 CORE_ADDR pc
= get_frame_pc (this_frame
);
3400 /* UnixWare uses _sigacthandler. The origin of the other symbols is
3401 currently unknown. */
3402 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
3403 return (name
&& (strcmp ("_sigreturn", name
) == 0
3404 || strcmp ("_sigacthandler", name
) == 0
3405 || strcmp ("sigvechandler", name
) == 0));
3408 /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the
3409 address of the associated sigcontext (ucontext) structure. */
3412 i386_svr4_sigcontext_addr (struct frame_info
*this_frame
)
3414 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3415 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3419 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
3420 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
3422 return read_memory_unsigned_integer (sp
+ 8, 4, byte_order
);
3427 /* Implementation of `gdbarch_stap_is_single_operand', as defined in
3431 i386_stap_is_single_operand (struct gdbarch
*gdbarch
, const char *s
)
3433 return (*s
== '$' /* Literal number. */
3434 || (isdigit (*s
) && s
[1] == '(' && s
[2] == '%') /* Displacement. */
3435 || (*s
== '(' && s
[1] == '%') /* Register indirection. */
3436 || (*s
== '%' && isalpha (s
[1]))); /* Register access. */
3439 /* Implementation of `gdbarch_stap_parse_special_token', as defined in
3443 i386_stap_parse_special_token (struct gdbarch
*gdbarch
,
3444 struct stap_parse_info
*p
)
3446 /* In order to parse special tokens, we use a state-machine that go
3447 through every known token and try to get a match. */
3451 THREE_ARG_DISPLACEMENT
,
3455 current_state
= TRIPLET
;
3457 /* The special tokens to be parsed here are:
3459 - `register base + (register index * size) + offset', as represented
3460 in `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'.
3462 - Operands of the form `-8+3+1(%rbp)', which must be interpreted as
3463 `*(-8 + 3 - 1 + (void *) $eax)'. */
3465 while (current_state
!= DONE
)
3467 const char *s
= p
->arg
;
3469 switch (current_state
)
3473 if (isdigit (*s
) || *s
== '-' || *s
== '+')
3477 long displacements
[3];
3492 displacements
[0] = strtol (s
, (char **) &s
, 10);
3494 if (*s
!= '+' && *s
!= '-')
3496 /* We are not dealing with a triplet. */
3509 displacements
[1] = strtol (s
, (char **) &s
, 10);
3511 if (*s
!= '+' && *s
!= '-')
3513 /* We are not dealing with a triplet. */
3526 displacements
[2] = strtol (s
, (char **) &s
, 10);
3528 if (*s
!= '(' || s
[1] != '%')
3534 while (isalnum (*s
))
3541 regname
= alloca (len
+ 1);
3543 strncpy (regname
, start
, len
);
3544 regname
[len
] = '\0';
3546 if (user_reg_map_name_to_regnum (gdbarch
,
3547 regname
, len
) == -1)
3548 error (_("Invalid register name `%s' "
3549 "on expression `%s'."),
3550 regname
, p
->saved_arg
);
3552 for (i
= 0; i
< 3; i
++)
3554 write_exp_elt_opcode (OP_LONG
);
3556 (builtin_type (gdbarch
)->builtin_long
);
3557 write_exp_elt_longcst (displacements
[i
]);
3558 write_exp_elt_opcode (OP_LONG
);
3560 write_exp_elt_opcode (UNOP_NEG
);
3563 write_exp_elt_opcode (OP_REGISTER
);
3566 write_exp_string (str
);
3567 write_exp_elt_opcode (OP_REGISTER
);
3569 write_exp_elt_opcode (UNOP_CAST
);
3570 write_exp_elt_type (builtin_type (gdbarch
)->builtin_data_ptr
);
3571 write_exp_elt_opcode (UNOP_CAST
);
3573 write_exp_elt_opcode (BINOP_ADD
);
3574 write_exp_elt_opcode (BINOP_ADD
);
3575 write_exp_elt_opcode (BINOP_ADD
);
3577 write_exp_elt_opcode (UNOP_CAST
);
3578 write_exp_elt_type (lookup_pointer_type (p
->arg_type
));
3579 write_exp_elt_opcode (UNOP_CAST
);
3581 write_exp_elt_opcode (UNOP_IND
);
3589 case THREE_ARG_DISPLACEMENT
:
3591 if (isdigit (*s
) || *s
== '(' || *s
== '-' || *s
== '+')
3593 int offset_minus
= 0;
3602 struct stoken base_token
, index_token
;
3612 if (offset_minus
&& !isdigit (*s
))
3616 offset
= strtol (s
, (char **) &s
, 10);
3618 if (*s
!= '(' || s
[1] != '%')
3624 while (isalnum (*s
))
3627 if (*s
!= ',' || s
[1] != '%')
3630 len_base
= s
- start
;
3631 base
= alloca (len_base
+ 1);
3632 strncpy (base
, start
, len_base
);
3633 base
[len_base
] = '\0';
3635 if (user_reg_map_name_to_regnum (gdbarch
,
3636 base
, len_base
) == -1)
3637 error (_("Invalid register name `%s' "
3638 "on expression `%s'."),
3639 base
, p
->saved_arg
);
3644 while (isalnum (*s
))
3647 len_index
= s
- start
;
3648 index
= alloca (len_index
+ 1);
3649 strncpy (index
, start
, len_index
);
3650 index
[len_index
] = '\0';
3652 if (user_reg_map_name_to_regnum (gdbarch
,
3653 index
, len_index
) == -1)
3654 error (_("Invalid register name `%s' "
3655 "on expression `%s'."),
3656 index
, p
->saved_arg
);
3658 if (*s
!= ',' && *s
!= ')')
3672 size
= strtol (s
, (char **) &s
, 10);
3682 write_exp_elt_opcode (OP_LONG
);
3684 (builtin_type (gdbarch
)->builtin_long
);
3685 write_exp_elt_longcst (offset
);
3686 write_exp_elt_opcode (OP_LONG
);
3688 write_exp_elt_opcode (UNOP_NEG
);
3691 write_exp_elt_opcode (OP_REGISTER
);
3692 base_token
.ptr
= base
;
3693 base_token
.length
= len_base
;
3694 write_exp_string (base_token
);
3695 write_exp_elt_opcode (OP_REGISTER
);
3698 write_exp_elt_opcode (BINOP_ADD
);
3700 write_exp_elt_opcode (OP_REGISTER
);
3701 index_token
.ptr
= index
;
3702 index_token
.length
= len_index
;
3703 write_exp_string (index_token
);
3704 write_exp_elt_opcode (OP_REGISTER
);
3708 write_exp_elt_opcode (OP_LONG
);
3710 (builtin_type (gdbarch
)->builtin_long
);
3711 write_exp_elt_longcst (size
);
3712 write_exp_elt_opcode (OP_LONG
);
3714 write_exp_elt_opcode (UNOP_NEG
);
3715 write_exp_elt_opcode (BINOP_MUL
);
3718 write_exp_elt_opcode (BINOP_ADD
);
3720 write_exp_elt_opcode (UNOP_CAST
);
3721 write_exp_elt_type (lookup_pointer_type (p
->arg_type
));
3722 write_exp_elt_opcode (UNOP_CAST
);
3724 write_exp_elt_opcode (UNOP_IND
);
3734 /* Advancing to the next state. */
3746 i386_elf_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
3748 /* We typically use stabs-in-ELF with the SVR4 register numbering. */
3749 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
3751 /* Registering SystemTap handlers. */
3752 set_gdbarch_stap_integer_prefix (gdbarch
, "$");
3753 set_gdbarch_stap_register_prefix (gdbarch
, "%");
3754 set_gdbarch_stap_register_indirection_prefix (gdbarch
, "(");
3755 set_gdbarch_stap_register_indirection_suffix (gdbarch
, ")");
3756 set_gdbarch_stap_is_single_operand (gdbarch
,
3757 i386_stap_is_single_operand
);
3758 set_gdbarch_stap_parse_special_token (gdbarch
,
3759 i386_stap_parse_special_token
);
3762 /* System V Release 4 (SVR4). */
3765 i386_svr4_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
3767 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3769 /* System V Release 4 uses ELF. */
3770 i386_elf_init_abi (info
, gdbarch
);
3772 /* System V Release 4 has shared libraries. */
3773 set_gdbarch_skip_trampoline_code (gdbarch
, find_solib_trampoline_target
);
3775 tdep
->sigtramp_p
= i386_svr4_sigtramp_p
;
3776 tdep
->sigcontext_addr
= i386_svr4_sigcontext_addr
;
3777 tdep
->sc_pc_offset
= 36 + 14 * 4;
3778 tdep
->sc_sp_offset
= 36 + 17 * 4;
3780 tdep
->jb_pc_offset
= 20;
3786 i386_go32_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
3788 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3790 /* DJGPP doesn't have any special frames for signal handlers. */
3791 tdep
->sigtramp_p
= NULL
;
3793 tdep
->jb_pc_offset
= 36;
3795 /* DJGPP does not support the SSE registers. */
3796 if (! tdesc_has_registers (info
.target_desc
))
3797 tdep
->tdesc
= tdesc_i386_mmx
;
3799 /* Native compiler is GCC, which uses the SVR4 register numbering
3800 even in COFF and STABS. See the comment in i386_gdbarch_init,
3801 before the calls to set_gdbarch_stab_reg_to_regnum and
3802 set_gdbarch_sdb_reg_to_regnum. */
3803 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
3804 set_gdbarch_sdb_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
3806 set_gdbarch_has_dos_based_file_system (gdbarch
, 1);
3810 /* i386 register groups. In addition to the normal groups, add "mmx"
3813 static struct reggroup
*i386_sse_reggroup
;
3814 static struct reggroup
*i386_mmx_reggroup
;
3817 i386_init_reggroups (void)
3819 i386_sse_reggroup
= reggroup_new ("sse", USER_REGGROUP
);
3820 i386_mmx_reggroup
= reggroup_new ("mmx", USER_REGGROUP
);
3824 i386_add_reggroups (struct gdbarch
*gdbarch
)
3826 reggroup_add (gdbarch
, i386_sse_reggroup
);
3827 reggroup_add (gdbarch
, i386_mmx_reggroup
);
3828 reggroup_add (gdbarch
, general_reggroup
);
3829 reggroup_add (gdbarch
, float_reggroup
);
3830 reggroup_add (gdbarch
, all_reggroup
);
3831 reggroup_add (gdbarch
, save_reggroup
);
3832 reggroup_add (gdbarch
, restore_reggroup
);
3833 reggroup_add (gdbarch
, vector_reggroup
);
3834 reggroup_add (gdbarch
, system_reggroup
);
3838 i386_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
3839 struct reggroup
*group
)
3841 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3842 int fp_regnum_p
, mmx_regnum_p
, xmm_regnum_p
, mxcsr_regnum_p
,
3843 ymm_regnum_p
, ymmh_regnum_p
;
3845 /* Don't include pseudo registers, except for MMX, in any register
3847 if (i386_byte_regnum_p (gdbarch
, regnum
))
3850 if (i386_word_regnum_p (gdbarch
, regnum
))
3853 if (i386_dword_regnum_p (gdbarch
, regnum
))
3856 mmx_regnum_p
= i386_mmx_regnum_p (gdbarch
, regnum
);
3857 if (group
== i386_mmx_reggroup
)
3858 return mmx_regnum_p
;
3860 xmm_regnum_p
= i386_xmm_regnum_p (gdbarch
, regnum
);
3861 mxcsr_regnum_p
= i386_mxcsr_regnum_p (gdbarch
, regnum
);
3862 if (group
== i386_sse_reggroup
)
3863 return xmm_regnum_p
|| mxcsr_regnum_p
;
3865 ymm_regnum_p
= i386_ymm_regnum_p (gdbarch
, regnum
);
3866 if (group
== vector_reggroup
)
3867 return (mmx_regnum_p
3871 && ((tdep
->xcr0
& I386_XSTATE_AVX_MASK
)
3872 == I386_XSTATE_SSE_MASK
)));
3874 fp_regnum_p
= (i386_fp_regnum_p (gdbarch
, regnum
)
3875 || i386_fpc_regnum_p (gdbarch
, regnum
));
3876 if (group
== float_reggroup
)
3879 /* For "info reg all", don't include upper YMM registers nor XMM
3880 registers when AVX is supported. */
3881 ymmh_regnum_p
= i386_ymmh_regnum_p (gdbarch
, regnum
);
3882 if (group
== all_reggroup
3884 && (tdep
->xcr0
& I386_XSTATE_AVX
))
3888 if (group
== general_reggroup
)
3889 return (!fp_regnum_p
3896 return default_register_reggroup_p (gdbarch
, regnum
, group
);
3900 /* Get the ARGIth function argument for the current function. */
3903 i386_fetch_pointer_argument (struct frame_info
*frame
, int argi
,
3906 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3907 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3908 CORE_ADDR sp
= get_frame_register_unsigned (frame
, I386_ESP_REGNUM
);
3909 return read_memory_unsigned_integer (sp
+ (4 * (argi
+ 1)), 4, byte_order
);
3913 i386_skip_permanent_breakpoint (struct regcache
*regcache
)
3915 CORE_ADDR current_pc
= regcache_read_pc (regcache
);
3917 /* On i386, breakpoint is exactly 1 byte long, so we just
3918 adjust the PC in the regcache. */
3920 regcache_write_pc (regcache
, current_pc
);
3924 #define PREFIX_REPZ 0x01
3925 #define PREFIX_REPNZ 0x02
3926 #define PREFIX_LOCK 0x04
3927 #define PREFIX_DATA 0x08
3928 #define PREFIX_ADDR 0x10
3940 /* i386 arith/logic operations */
3953 struct i386_record_s
3955 struct gdbarch
*gdbarch
;
3956 struct regcache
*regcache
;
3957 CORE_ADDR orig_addr
;
3963 uint8_t mod
, reg
, rm
;
3972 /* Parse the "modrm" part of the memory address irp->addr points at.
3973 Returns -1 if something goes wrong, 0 otherwise. */
3976 i386_record_modrm (struct i386_record_s
*irp
)
3978 struct gdbarch
*gdbarch
= irp
->gdbarch
;
3980 if (record_read_memory (gdbarch
, irp
->addr
, &irp
->modrm
, 1))
3984 irp
->mod
= (irp
->modrm
>> 6) & 3;
3985 irp
->reg
= (irp
->modrm
>> 3) & 7;
3986 irp
->rm
= irp
->modrm
& 7;
3991 /* Extract the memory address that the current instruction writes to,
3992 and return it in *ADDR. Return -1 if something goes wrong. */
3995 i386_record_lea_modrm_addr (struct i386_record_s
*irp
, uint64_t *addr
)
3997 struct gdbarch
*gdbarch
= irp
->gdbarch
;
3998 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4010 uint8_t base
= irp
->rm
;
4015 if (record_read_memory (gdbarch
, irp
->addr
, &byte
, 1))
4018 scale
= (byte
>> 6) & 3;
4019 index
= ((byte
>> 3) & 7) | irp
->rex_x
;
4027 if ((base
& 7) == 5)
4030 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 4))
4033 *addr
= extract_signed_integer (buf
, 4, byte_order
);
4034 if (irp
->regmap
[X86_RECORD_R8_REGNUM
] && !havesib
)
4035 *addr
+= irp
->addr
+ irp
->rip_offset
;
4039 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 1))
4042 *addr
= (int8_t) buf
[0];
4045 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 4))
4047 *addr
= extract_signed_integer (buf
, 4, byte_order
);
4055 if (base
== 4 && irp
->popl_esp_hack
)
4056 *addr
+= irp
->popl_esp_hack
;
4057 regcache_raw_read_unsigned (irp
->regcache
, irp
->regmap
[base
],
4060 if (irp
->aflag
== 2)
4065 *addr
= (uint32_t) (offset64
+ *addr
);
4067 if (havesib
&& (index
!= 4 || scale
!= 0))
4069 regcache_raw_read_unsigned (irp
->regcache
, irp
->regmap
[index
],
4071 if (irp
->aflag
== 2)
4072 *addr
+= offset64
<< scale
;
4074 *addr
= (uint32_t) (*addr
+ (offset64
<< scale
));
4085 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 2))
4088 *addr
= extract_signed_integer (buf
, 2, byte_order
);
4094 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 1))
4097 *addr
= (int8_t) buf
[0];
4100 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 2))
4103 *addr
= extract_signed_integer (buf
, 2, byte_order
);
4110 regcache_raw_read_unsigned (irp
->regcache
,
4111 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
4113 *addr
= (uint32_t) (*addr
+ offset64
);
4114 regcache_raw_read_unsigned (irp
->regcache
,
4115 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
4117 *addr
= (uint32_t) (*addr
+ offset64
);
4120 regcache_raw_read_unsigned (irp
->regcache
,
4121 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
4123 *addr
= (uint32_t) (*addr
+ offset64
);
4124 regcache_raw_read_unsigned (irp
->regcache
,
4125 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
4127 *addr
= (uint32_t) (*addr
+ offset64
);
4130 regcache_raw_read_unsigned (irp
->regcache
,
4131 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
4133 *addr
= (uint32_t) (*addr
+ offset64
);
4134 regcache_raw_read_unsigned (irp
->regcache
,
4135 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
4137 *addr
= (uint32_t) (*addr
+ offset64
);
4140 regcache_raw_read_unsigned (irp
->regcache
,
4141 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
4143 *addr
= (uint32_t) (*addr
+ offset64
);
4144 regcache_raw_read_unsigned (irp
->regcache
,
4145 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
4147 *addr
= (uint32_t) (*addr
+ offset64
);
4150 regcache_raw_read_unsigned (irp
->regcache
,
4151 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
4153 *addr
= (uint32_t) (*addr
+ offset64
);
4156 regcache_raw_read_unsigned (irp
->regcache
,
4157 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
4159 *addr
= (uint32_t) (*addr
+ offset64
);
4162 regcache_raw_read_unsigned (irp
->regcache
,
4163 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
4165 *addr
= (uint32_t) (*addr
+ offset64
);
4168 regcache_raw_read_unsigned (irp
->regcache
,
4169 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
4171 *addr
= (uint32_t) (*addr
+ offset64
);
4181 /* Record the address and contents of the memory that will be changed
4182 by the current instruction. Return -1 if something goes wrong, 0
4186 i386_record_lea_modrm (struct i386_record_s
*irp
)
4188 struct gdbarch
*gdbarch
= irp
->gdbarch
;
4191 if (irp
->override
>= 0)
4193 if (record_memory_query
)
4197 target_terminal_ours ();
4199 Process record ignores the memory change of instruction at address %s\n\
4200 because it can't get the value of the segment register.\n\
4201 Do you want to stop the program?"),
4202 paddress (gdbarch
, irp
->orig_addr
));
4203 target_terminal_inferior ();
4211 if (i386_record_lea_modrm_addr (irp
, &addr
))
4214 if (record_arch_list_add_mem (addr
, 1 << irp
->ot
))
4220 /* Record the effects of a push operation. Return -1 if something
4221 goes wrong, 0 otherwise. */
4224 i386_record_push (struct i386_record_s
*irp
, int size
)
4228 if (record_arch_list_add_reg (irp
->regcache
,
4229 irp
->regmap
[X86_RECORD_RESP_REGNUM
]))
4231 regcache_raw_read_unsigned (irp
->regcache
,
4232 irp
->regmap
[X86_RECORD_RESP_REGNUM
],
4234 if (record_arch_list_add_mem ((CORE_ADDR
) addr
- size
, size
))
4241 /* Defines contents to record. */
4242 #define I386_SAVE_FPU_REGS 0xfffd
4243 #define I386_SAVE_FPU_ENV 0xfffe
4244 #define I386_SAVE_FPU_ENV_REG_STACK 0xffff
4246 /* Record the values of the floating point registers which will be
4247 changed by the current instruction. Returns -1 if something is
4248 wrong, 0 otherwise. */
4250 static int i386_record_floats (struct gdbarch
*gdbarch
,
4251 struct i386_record_s
*ir
,
4254 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4257 /* Oza: Because of floating point insn push/pop of fpu stack is going to
4258 happen. Currently we store st0-st7 registers, but we need not store all
4259 registers all the time, in future we use ftag register and record only
4260 those who are not marked as an empty. */
4262 if (I386_SAVE_FPU_REGS
== iregnum
)
4264 for (i
= I387_ST0_REGNUM (tdep
); i
<= I387_ST0_REGNUM (tdep
) + 7; i
++)
4266 if (record_arch_list_add_reg (ir
->regcache
, i
))
4270 else if (I386_SAVE_FPU_ENV
== iregnum
)
4272 for (i
= I387_FCTRL_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
4274 if (record_arch_list_add_reg (ir
->regcache
, i
))
4278 else if (I386_SAVE_FPU_ENV_REG_STACK
== iregnum
)
4280 for (i
= I387_ST0_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
4282 if (record_arch_list_add_reg (ir
->regcache
, i
))
4286 else if ((iregnum
>= I387_ST0_REGNUM (tdep
)) &&
4287 (iregnum
<= I387_FOP_REGNUM (tdep
)))
4289 if (record_arch_list_add_reg (ir
->regcache
,iregnum
))
4294 /* Parameter error. */
4297 if(I386_SAVE_FPU_ENV
!= iregnum
)
4299 for (i
= I387_FCTRL_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
4301 if (record_arch_list_add_reg (ir
->regcache
, i
))
4308 /* Parse the current instruction, and record the values of the
4309 registers and memory that will be changed by the current
4310 instruction. Returns -1 if something goes wrong, 0 otherwise. */
4312 #define I386_RECORD_ARCH_LIST_ADD_REG(regnum) \
4313 record_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)])
4316 i386_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4317 CORE_ADDR input_addr
)
4319 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4325 gdb_byte buf
[MAX_REGISTER_SIZE
];
4326 struct i386_record_s ir
;
4327 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4332 memset (&ir
, 0, sizeof (struct i386_record_s
));
4333 ir
.regcache
= regcache
;
4334 ir
.addr
= input_addr
;
4335 ir
.orig_addr
= input_addr
;
4339 ir
.popl_esp_hack
= 0;
4340 ir
.regmap
= tdep
->record_regmap
;
4341 ir
.gdbarch
= gdbarch
;
4343 if (record_debug
> 1)
4344 fprintf_unfiltered (gdb_stdlog
, "Process record: i386_process_record "
4346 paddress (gdbarch
, ir
.addr
));
4351 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
4354 switch (opcode8
) /* Instruction prefixes */
4356 case REPE_PREFIX_OPCODE
:
4357 prefixes
|= PREFIX_REPZ
;
4359 case REPNE_PREFIX_OPCODE
:
4360 prefixes
|= PREFIX_REPNZ
;
4362 case LOCK_PREFIX_OPCODE
:
4363 prefixes
|= PREFIX_LOCK
;
4365 case CS_PREFIX_OPCODE
:
4366 ir
.override
= X86_RECORD_CS_REGNUM
;
4368 case SS_PREFIX_OPCODE
:
4369 ir
.override
= X86_RECORD_SS_REGNUM
;
4371 case DS_PREFIX_OPCODE
:
4372 ir
.override
= X86_RECORD_DS_REGNUM
;
4374 case ES_PREFIX_OPCODE
:
4375 ir
.override
= X86_RECORD_ES_REGNUM
;
4377 case FS_PREFIX_OPCODE
:
4378 ir
.override
= X86_RECORD_FS_REGNUM
;
4380 case GS_PREFIX_OPCODE
:
4381 ir
.override
= X86_RECORD_GS_REGNUM
;
4383 case DATA_PREFIX_OPCODE
:
4384 prefixes
|= PREFIX_DATA
;
4386 case ADDR_PREFIX_OPCODE
:
4387 prefixes
|= PREFIX_ADDR
;
4389 case 0x40: /* i386 inc %eax */
4390 case 0x41: /* i386 inc %ecx */
4391 case 0x42: /* i386 inc %edx */
4392 case 0x43: /* i386 inc %ebx */
4393 case 0x44: /* i386 inc %esp */
4394 case 0x45: /* i386 inc %ebp */
4395 case 0x46: /* i386 inc %esi */
4396 case 0x47: /* i386 inc %edi */
4397 case 0x48: /* i386 dec %eax */
4398 case 0x49: /* i386 dec %ecx */
4399 case 0x4a: /* i386 dec %edx */
4400 case 0x4b: /* i386 dec %ebx */
4401 case 0x4c: /* i386 dec %esp */
4402 case 0x4d: /* i386 dec %ebp */
4403 case 0x4e: /* i386 dec %esi */
4404 case 0x4f: /* i386 dec %edi */
4405 if (ir
.regmap
[X86_RECORD_R8_REGNUM
]) /* 64 bit target */
4409 rex_w
= (opcode8
>> 3) & 1;
4410 rex_r
= (opcode8
& 0x4) << 1;
4411 ir
.rex_x
= (opcode8
& 0x2) << 2;
4412 ir
.rex_b
= (opcode8
& 0x1) << 3;
4414 else /* 32 bit target */
4423 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && rex_w
== 1)
4429 if (prefixes
& PREFIX_DATA
)
4432 if (prefixes
& PREFIX_ADDR
)
4434 else if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4437 /* Now check op code. */
4438 opcode
= (uint32_t) opcode8
;
4443 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
4446 opcode
= (uint32_t) opcode8
| 0x0f00;
4450 case 0x00: /* arith & logic */
4498 if (((opcode
>> 3) & 7) != OP_CMPL
)
4500 if ((opcode
& 1) == 0)
4503 ir
.ot
= ir
.dflag
+ OT_WORD
;
4505 switch ((opcode
>> 1) & 3)
4507 case 0: /* OP Ev, Gv */
4508 if (i386_record_modrm (&ir
))
4512 if (i386_record_lea_modrm (&ir
))
4518 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4520 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4523 case 1: /* OP Gv, Ev */
4524 if (i386_record_modrm (&ir
))
4527 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4529 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4531 case 2: /* OP A, Iv */
4532 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4536 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4539 case 0x80: /* GRP1 */
4543 if (i386_record_modrm (&ir
))
4546 if (ir
.reg
!= OP_CMPL
)
4548 if ((opcode
& 1) == 0)
4551 ir
.ot
= ir
.dflag
+ OT_WORD
;
4558 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
4559 if (i386_record_lea_modrm (&ir
))
4563 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
4565 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4568 case 0x40: /* inc */
4577 case 0x48: /* dec */
4586 I386_RECORD_ARCH_LIST_ADD_REG (opcode
& 7);
4587 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4590 case 0xf6: /* GRP3 */
4592 if ((opcode
& 1) == 0)
4595 ir
.ot
= ir
.dflag
+ OT_WORD
;
4596 if (i386_record_modrm (&ir
))
4599 if (ir
.mod
!= 3 && ir
.reg
== 0)
4600 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
4605 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4611 if (i386_record_lea_modrm (&ir
))
4617 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4619 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4621 if (ir
.reg
== 3) /* neg */
4622 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4628 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4629 if (ir
.ot
!= OT_BYTE
)
4630 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
4631 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4635 opcode
= opcode
<< 8 | ir
.modrm
;
4641 case 0xfe: /* GRP4 */
4642 case 0xff: /* GRP5 */
4643 if (i386_record_modrm (&ir
))
4645 if (ir
.reg
>= 2 && opcode
== 0xfe)
4648 opcode
= opcode
<< 8 | ir
.modrm
;
4655 if ((opcode
& 1) == 0)
4658 ir
.ot
= ir
.dflag
+ OT_WORD
;
4661 if (i386_record_lea_modrm (&ir
))
4667 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4669 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4671 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4674 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4676 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4678 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4681 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
4682 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4684 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4688 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4691 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4693 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4698 opcode
= opcode
<< 8 | ir
.modrm
;
4704 case 0x84: /* test */
4708 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4711 case 0x98: /* CWDE/CBW */
4712 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4715 case 0x99: /* CDQ/CWD */
4716 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4717 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
4720 case 0x0faf: /* imul */
4723 ir
.ot
= ir
.dflag
+ OT_WORD
;
4724 if (i386_record_modrm (&ir
))
4727 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
4728 else if (opcode
== 0x6b)
4731 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4733 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4734 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4737 case 0x0fc0: /* xadd */
4739 if ((opcode
& 1) == 0)
4742 ir
.ot
= ir
.dflag
+ OT_WORD
;
4743 if (i386_record_modrm (&ir
))
4748 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4750 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4751 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4753 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4757 if (i386_record_lea_modrm (&ir
))
4759 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4761 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4763 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4766 case 0x0fb0: /* cmpxchg */
4768 if ((opcode
& 1) == 0)
4771 ir
.ot
= ir
.dflag
+ OT_WORD
;
4772 if (i386_record_modrm (&ir
))
4777 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4778 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4780 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4784 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4785 if (i386_record_lea_modrm (&ir
))
4788 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4791 case 0x0fc7: /* cmpxchg8b */
4792 if (i386_record_modrm (&ir
))
4797 opcode
= opcode
<< 8 | ir
.modrm
;
4800 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4801 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
4802 if (i386_record_lea_modrm (&ir
))
4804 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4807 case 0x50: /* push */
4817 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4819 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4823 case 0x06: /* push es */
4824 case 0x0e: /* push cs */
4825 case 0x16: /* push ss */
4826 case 0x1e: /* push ds */
4827 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4832 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4836 case 0x0fa0: /* push fs */
4837 case 0x0fa8: /* push gs */
4838 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4843 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4847 case 0x60: /* pusha */
4848 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4853 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 4)))
4857 case 0x58: /* pop */
4865 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4866 I386_RECORD_ARCH_LIST_ADD_REG ((opcode
& 0x7) | ir
.rex_b
);
4869 case 0x61: /* popa */
4870 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4875 for (regnum
= X86_RECORD_REAX_REGNUM
;
4876 regnum
<= X86_RECORD_REDI_REGNUM
;
4878 I386_RECORD_ARCH_LIST_ADD_REG (regnum
);
4881 case 0x8f: /* pop */
4882 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4883 ir
.ot
= ir
.dflag
? OT_QUAD
: OT_WORD
;
4885 ir
.ot
= ir
.dflag
+ OT_WORD
;
4886 if (i386_record_modrm (&ir
))
4889 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
4892 ir
.popl_esp_hack
= 1 << ir
.ot
;
4893 if (i386_record_lea_modrm (&ir
))
4896 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4899 case 0xc8: /* enter */
4900 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
4901 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4903 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4907 case 0xc9: /* leave */
4908 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4909 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
4912 case 0x07: /* pop es */
4913 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4918 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4919 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM
);
4920 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4923 case 0x17: /* pop ss */
4924 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4929 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4930 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM
);
4931 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4934 case 0x1f: /* pop ds */
4935 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4940 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4941 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM
);
4942 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4945 case 0x0fa1: /* pop fs */
4946 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4947 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM
);
4948 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4951 case 0x0fa9: /* pop gs */
4952 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4953 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM
);
4954 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4957 case 0x88: /* mov */
4961 if ((opcode
& 1) == 0)
4964 ir
.ot
= ir
.dflag
+ OT_WORD
;
4966 if (i386_record_modrm (&ir
))
4971 if (opcode
== 0xc6 || opcode
== 0xc7)
4972 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
4973 if (i386_record_lea_modrm (&ir
))
4978 if (opcode
== 0xc6 || opcode
== 0xc7)
4980 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4982 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4986 case 0x8a: /* mov */
4988 if ((opcode
& 1) == 0)
4991 ir
.ot
= ir
.dflag
+ OT_WORD
;
4992 if (i386_record_modrm (&ir
))
4995 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4997 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
5000 case 0x8c: /* mov seg */
5001 if (i386_record_modrm (&ir
))
5006 opcode
= opcode
<< 8 | ir
.modrm
;
5011 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
5015 if (i386_record_lea_modrm (&ir
))
5020 case 0x8e: /* mov seg */
5021 if (i386_record_modrm (&ir
))
5026 regnum
= X86_RECORD_ES_REGNUM
;
5029 regnum
= X86_RECORD_SS_REGNUM
;
5032 regnum
= X86_RECORD_DS_REGNUM
;
5035 regnum
= X86_RECORD_FS_REGNUM
;
5038 regnum
= X86_RECORD_GS_REGNUM
;
5042 opcode
= opcode
<< 8 | ir
.modrm
;
5046 I386_RECORD_ARCH_LIST_ADD_REG (regnum
);
5047 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5050 case 0x0fb6: /* movzbS */
5051 case 0x0fb7: /* movzwS */
5052 case 0x0fbe: /* movsbS */
5053 case 0x0fbf: /* movswS */
5054 if (i386_record_modrm (&ir
))
5056 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
5059 case 0x8d: /* lea */
5060 if (i386_record_modrm (&ir
))
5065 opcode
= opcode
<< 8 | ir
.modrm
;
5070 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5072 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
5075 case 0xa0: /* mov EAX */
5078 case 0xd7: /* xlat */
5079 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5082 case 0xa2: /* mov EAX */
5084 if (ir
.override
>= 0)
5086 if (record_memory_query
)
5090 target_terminal_ours ();
5092 Process record ignores the memory change of instruction at address %s\n\
5093 because it can't get the value of the segment register.\n\
5094 Do you want to stop the program?"),
5095 paddress (gdbarch
, ir
.orig_addr
));
5096 target_terminal_inferior ();
5103 if ((opcode
& 1) == 0)
5106 ir
.ot
= ir
.dflag
+ OT_WORD
;
5109 if (record_read_memory (gdbarch
, ir
.addr
, buf
, 8))
5112 addr
= extract_unsigned_integer (buf
, 8, byte_order
);
5116 if (record_read_memory (gdbarch
, ir
.addr
, buf
, 4))
5119 addr
= extract_unsigned_integer (buf
, 4, byte_order
);
5123 if (record_read_memory (gdbarch
, ir
.addr
, buf
, 2))
5126 addr
= extract_unsigned_integer (buf
, 2, byte_order
);
5128 if (record_arch_list_add_mem (addr
, 1 << ir
.ot
))
5133 case 0xb0: /* mov R, Ib */
5141 I386_RECORD_ARCH_LIST_ADD_REG ((ir
.regmap
[X86_RECORD_R8_REGNUM
])
5142 ? ((opcode
& 0x7) | ir
.rex_b
)
5143 : ((opcode
& 0x7) & 0x3));
5146 case 0xb8: /* mov R, Iv */
5154 I386_RECORD_ARCH_LIST_ADD_REG ((opcode
& 0x7) | ir
.rex_b
);
5157 case 0x91: /* xchg R, EAX */
5164 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5165 I386_RECORD_ARCH_LIST_ADD_REG (opcode
& 0x7);
5168 case 0x86: /* xchg Ev, Gv */
5170 if ((opcode
& 1) == 0)
5173 ir
.ot
= ir
.dflag
+ OT_WORD
;
5174 if (i386_record_modrm (&ir
))
5179 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5181 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
5185 if (i386_record_lea_modrm (&ir
))
5189 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5191 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
5194 case 0xc4: /* les Gv */
5195 case 0xc5: /* lds Gv */
5196 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5202 case 0x0fb2: /* lss Gv */
5203 case 0x0fb4: /* lfs Gv */
5204 case 0x0fb5: /* lgs Gv */
5205 if (i386_record_modrm (&ir
))
5213 opcode
= opcode
<< 8 | ir
.modrm
;
5218 case 0xc4: /* les Gv */
5219 regnum
= X86_RECORD_ES_REGNUM
;
5221 case 0xc5: /* lds Gv */
5222 regnum
= X86_RECORD_DS_REGNUM
;
5224 case 0x0fb2: /* lss Gv */
5225 regnum
= X86_RECORD_SS_REGNUM
;
5227 case 0x0fb4: /* lfs Gv */
5228 regnum
= X86_RECORD_FS_REGNUM
;
5230 case 0x0fb5: /* lgs Gv */
5231 regnum
= X86_RECORD_GS_REGNUM
;
5234 I386_RECORD_ARCH_LIST_ADD_REG (regnum
);
5235 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
5236 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5239 case 0xc0: /* shifts */
5245 if ((opcode
& 1) == 0)
5248 ir
.ot
= ir
.dflag
+ OT_WORD
;
5249 if (i386_record_modrm (&ir
))
5251 if (ir
.mod
!= 3 && (opcode
== 0xd2 || opcode
== 0xd3))
5253 if (i386_record_lea_modrm (&ir
))
5259 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5261 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
5263 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5270 if (i386_record_modrm (&ir
))
5274 if (record_arch_list_add_reg (ir
.regcache
, ir
.rm
))
5279 if (i386_record_lea_modrm (&ir
))
5284 case 0xd8: /* Floats. */
5292 if (i386_record_modrm (&ir
))
5294 ir
.reg
|= ((opcode
& 7) << 3);
5300 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
5308 /* For fcom, ficom nothing to do. */
5314 /* For fcomp, ficomp pop FPU stack, store all. */
5315 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5342 /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul,
5343 fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension
5344 of code, always affects st(0) register. */
5345 if (i386_record_floats (gdbarch
, &ir
, I387_ST0_REGNUM (tdep
)))
5369 /* Handling fld, fild. */
5370 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5374 switch (ir
.reg
>> 4)
5377 if (record_arch_list_add_mem (addr64
, 4))
5381 if (record_arch_list_add_mem (addr64
, 8))
5387 if (record_arch_list_add_mem (addr64
, 2))
5393 switch (ir
.reg
>> 4)
5396 if (record_arch_list_add_mem (addr64
, 4))
5398 if (3 == (ir
.reg
& 7))
5400 /* For fstp m32fp. */
5401 if (i386_record_floats (gdbarch
, &ir
,
5402 I386_SAVE_FPU_REGS
))
5407 if (record_arch_list_add_mem (addr64
, 4))
5409 if ((3 == (ir
.reg
& 7))
5410 || (5 == (ir
.reg
& 7))
5411 || (7 == (ir
.reg
& 7)))
5413 /* For fstp insn. */
5414 if (i386_record_floats (gdbarch
, &ir
,
5415 I386_SAVE_FPU_REGS
))
5420 if (record_arch_list_add_mem (addr64
, 8))
5422 if (3 == (ir
.reg
& 7))
5424 /* For fstp m64fp. */
5425 if (i386_record_floats (gdbarch
, &ir
,
5426 I386_SAVE_FPU_REGS
))
5431 if ((3 <= (ir
.reg
& 7)) && (6 <= (ir
.reg
& 7)))
5433 /* For fistp, fbld, fild, fbstp. */
5434 if (i386_record_floats (gdbarch
, &ir
,
5435 I386_SAVE_FPU_REGS
))
5440 if (record_arch_list_add_mem (addr64
, 2))
5449 if (i386_record_floats (gdbarch
, &ir
,
5450 I386_SAVE_FPU_ENV_REG_STACK
))
5455 if (i386_record_floats (gdbarch
, &ir
, I387_FCTRL_REGNUM (tdep
)))
5460 if (i386_record_floats (gdbarch
, &ir
,
5461 I386_SAVE_FPU_ENV_REG_STACK
))
5467 if (record_arch_list_add_mem (addr64
, 28))
5472 if (record_arch_list_add_mem (addr64
, 14))
5478 if (record_arch_list_add_mem (addr64
, 2))
5480 /* Insn fstp, fbstp. */
5481 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5486 if (record_arch_list_add_mem (addr64
, 10))
5492 if (record_arch_list_add_mem (addr64
, 28))
5498 if (record_arch_list_add_mem (addr64
, 14))
5502 if (record_arch_list_add_mem (addr64
, 80))
5505 if (i386_record_floats (gdbarch
, &ir
,
5506 I386_SAVE_FPU_ENV_REG_STACK
))
5510 if (record_arch_list_add_mem (addr64
, 8))
5513 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5518 opcode
= opcode
<< 8 | ir
.modrm
;
5523 /* Opcode is an extension of modR/M byte. */
5529 if (i386_record_floats (gdbarch
, &ir
, I387_ST0_REGNUM (tdep
)))
5533 if (0x0c == (ir
.modrm
>> 4))
5535 if ((ir
.modrm
& 0x0f) <= 7)
5537 if (i386_record_floats (gdbarch
, &ir
,
5538 I386_SAVE_FPU_REGS
))
5543 if (i386_record_floats (gdbarch
, &ir
,
5544 I387_ST0_REGNUM (tdep
)))
5546 /* If only st(0) is changing, then we have already
5548 if ((ir
.modrm
& 0x0f) - 0x08)
5550 if (i386_record_floats (gdbarch
, &ir
,
5551 I387_ST0_REGNUM (tdep
) +
5552 ((ir
.modrm
& 0x0f) - 0x08)))
5570 if (i386_record_floats (gdbarch
, &ir
,
5571 I387_ST0_REGNUM (tdep
)))
5589 if (i386_record_floats (gdbarch
, &ir
,
5590 I386_SAVE_FPU_REGS
))
5594 if (i386_record_floats (gdbarch
, &ir
,
5595 I387_ST0_REGNUM (tdep
)))
5597 if (i386_record_floats (gdbarch
, &ir
,
5598 I387_ST0_REGNUM (tdep
) + 1))
5605 if (0xe9 == ir
.modrm
)
5607 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5610 else if ((0x0c == ir
.modrm
>> 4) || (0x0d == ir
.modrm
>> 4))
5612 if (i386_record_floats (gdbarch
, &ir
,
5613 I387_ST0_REGNUM (tdep
)))
5615 if (((ir
.modrm
& 0x0f) > 0) && ((ir
.modrm
& 0x0f) <= 7))
5617 if (i386_record_floats (gdbarch
, &ir
,
5618 I387_ST0_REGNUM (tdep
) +
5622 else if ((ir
.modrm
& 0x0f) - 0x08)
5624 if (i386_record_floats (gdbarch
, &ir
,
5625 I387_ST0_REGNUM (tdep
) +
5626 ((ir
.modrm
& 0x0f) - 0x08)))
5632 if (0xe3 == ir
.modrm
)
5634 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_ENV
))
5637 else if ((0x0c == ir
.modrm
>> 4) || (0x0d == ir
.modrm
>> 4))
5639 if (i386_record_floats (gdbarch
, &ir
,
5640 I387_ST0_REGNUM (tdep
)))
5642 if (((ir
.modrm
& 0x0f) > 0) && ((ir
.modrm
& 0x0f) <= 7))
5644 if (i386_record_floats (gdbarch
, &ir
,
5645 I387_ST0_REGNUM (tdep
) +
5649 else if ((ir
.modrm
& 0x0f) - 0x08)
5651 if (i386_record_floats (gdbarch
, &ir
,
5652 I387_ST0_REGNUM (tdep
) +
5653 ((ir
.modrm
& 0x0f) - 0x08)))
5659 if ((0x0c == ir
.modrm
>> 4)
5660 || (0x0d == ir
.modrm
>> 4)
5661 || (0x0f == ir
.modrm
>> 4))
5663 if ((ir
.modrm
& 0x0f) <= 7)
5665 if (i386_record_floats (gdbarch
, &ir
,
5666 I387_ST0_REGNUM (tdep
) +
5672 if (i386_record_floats (gdbarch
, &ir
,
5673 I387_ST0_REGNUM (tdep
) +
5674 ((ir
.modrm
& 0x0f) - 0x08)))
5680 if (0x0c == ir
.modrm
>> 4)
5682 if (i386_record_floats (gdbarch
, &ir
,
5683 I387_FTAG_REGNUM (tdep
)))
5686 else if ((0x0d == ir
.modrm
>> 4) || (0x0e == ir
.modrm
>> 4))
5688 if ((ir
.modrm
& 0x0f) <= 7)
5690 if (i386_record_floats (gdbarch
, &ir
,
5691 I387_ST0_REGNUM (tdep
) +
5697 if (i386_record_floats (gdbarch
, &ir
,
5698 I386_SAVE_FPU_REGS
))
5704 if ((0x0c == ir
.modrm
>> 4)
5705 || (0x0e == ir
.modrm
>> 4)
5706 || (0x0f == ir
.modrm
>> 4)
5707 || (0xd9 == ir
.modrm
))
5709 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5714 if (0xe0 == ir
.modrm
)
5716 if (record_arch_list_add_reg (ir
.regcache
, I386_EAX_REGNUM
))
5719 else if ((0x0f == ir
.modrm
>> 4) || (0x0e == ir
.modrm
>> 4))
5721 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5729 case 0xa4: /* movsS */
5731 case 0xaa: /* stosS */
5733 case 0x6c: /* insS */
5735 regcache_raw_read_unsigned (ir
.regcache
,
5736 ir
.regmap
[X86_RECORD_RECX_REGNUM
],
5742 if ((opcode
& 1) == 0)
5745 ir
.ot
= ir
.dflag
+ OT_WORD
;
5746 regcache_raw_read_unsigned (ir
.regcache
,
5747 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
5750 regcache_raw_read_unsigned (ir
.regcache
,
5751 ir
.regmap
[X86_RECORD_ES_REGNUM
],
5753 regcache_raw_read_unsigned (ir
.regcache
,
5754 ir
.regmap
[X86_RECORD_DS_REGNUM
],
5756 if (ir
.aflag
&& (es
!= ds
))
5758 /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */
5759 if (record_memory_query
)
5763 target_terminal_ours ();
5765 Process record ignores the memory change of instruction at address %s\n\
5766 because it can't get the value of the segment register.\n\
5767 Do you want to stop the program?"),
5768 paddress (gdbarch
, ir
.orig_addr
));
5769 target_terminal_inferior ();
5776 if (record_arch_list_add_mem (addr
, 1 << ir
.ot
))
5780 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5781 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5782 if (opcode
== 0xa4 || opcode
== 0xa5)
5783 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
5784 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
5785 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5789 case 0xa6: /* cmpsS */
5791 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
5792 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
5793 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5794 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5795 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5798 case 0xac: /* lodsS */
5800 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5801 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
5802 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5803 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5804 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5807 case 0xae: /* scasS */
5809 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
5810 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5811 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5812 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5815 case 0x6e: /* outsS */
5817 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
5818 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5819 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5820 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5823 case 0xe4: /* port I/O */
5827 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5828 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5838 case 0xc2: /* ret im */
5839 case 0xc3: /* ret */
5840 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5841 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5844 case 0xca: /* lret im */
5845 case 0xcb: /* lret */
5846 case 0xcf: /* iret */
5847 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
5848 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5849 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5852 case 0xe8: /* call im */
5853 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5855 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5859 case 0x9a: /* lcall im */
5860 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5865 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
5866 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5870 case 0xe9: /* jmp im */
5871 case 0xea: /* ljmp im */
5872 case 0xeb: /* jmp Jb */
5873 case 0x70: /* jcc Jb */
5889 case 0x0f80: /* jcc Jv */
5907 case 0x0f90: /* setcc Gv */
5923 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5925 if (i386_record_modrm (&ir
))
5928 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rex_b
? (ir
.rm
| ir
.rex_b
)
5932 if (i386_record_lea_modrm (&ir
))
5937 case 0x0f40: /* cmov Gv, Ev */
5953 if (i386_record_modrm (&ir
))
5956 if (ir
.dflag
== OT_BYTE
)
5958 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
5962 case 0x9c: /* pushf */
5963 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5964 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5966 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5970 case 0x9d: /* popf */
5971 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5972 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5975 case 0x9e: /* sahf */
5976 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5982 case 0xf5: /* cmc */
5983 case 0xf8: /* clc */
5984 case 0xf9: /* stc */
5985 case 0xfc: /* cld */
5986 case 0xfd: /* std */
5987 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5990 case 0x9f: /* lahf */
5991 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5996 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5997 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6000 /* bit operations */
6001 case 0x0fba: /* bt/bts/btr/btc Gv, im */
6002 ir
.ot
= ir
.dflag
+ OT_WORD
;
6003 if (i386_record_modrm (&ir
))
6008 opcode
= opcode
<< 8 | ir
.modrm
;
6014 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6017 if (i386_record_lea_modrm (&ir
))
6021 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6024 case 0x0fa3: /* bt Gv, Ev */
6025 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6028 case 0x0fab: /* bts */
6029 case 0x0fb3: /* btr */
6030 case 0x0fbb: /* btc */
6031 ir
.ot
= ir
.dflag
+ OT_WORD
;
6032 if (i386_record_modrm (&ir
))
6035 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6039 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
6041 regcache_raw_read_unsigned (ir
.regcache
,
6042 ir
.regmap
[ir
.reg
| rex_r
],
6047 addr64
+= ((int16_t) addr
>> 4) << 4;
6050 addr64
+= ((int32_t) addr
>> 5) << 5;
6053 addr64
+= ((int64_t) addr
>> 6) << 6;
6056 if (record_arch_list_add_mem (addr64
, 1 << ir
.ot
))
6058 if (i386_record_lea_modrm (&ir
))
6061 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6064 case 0x0fbc: /* bsf */
6065 case 0x0fbd: /* bsr */
6066 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
6067 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6071 case 0x27: /* daa */
6072 case 0x2f: /* das */
6073 case 0x37: /* aaa */
6074 case 0x3f: /* aas */
6075 case 0xd4: /* aam */
6076 case 0xd5: /* aad */
6077 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6082 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6083 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6087 case 0x90: /* nop */
6088 if (prefixes
& PREFIX_LOCK
)
6095 case 0x9b: /* fwait */
6096 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
6098 opcode
= (uint32_t) opcode8
;
6104 case 0xcc: /* int3 */
6105 printf_unfiltered (_("Process record does not support instruction "
6112 case 0xcd: /* int */
6116 if (record_read_memory (gdbarch
, ir
.addr
, &interrupt
, 1))
6119 if (interrupt
!= 0x80
6120 || tdep
->i386_intx80_record
== NULL
)
6122 printf_unfiltered (_("Process record does not support "
6123 "instruction int 0x%02x.\n"),
6128 ret
= tdep
->i386_intx80_record (ir
.regcache
);
6135 case 0xce: /* into */
6136 printf_unfiltered (_("Process record does not support "
6137 "instruction into.\n"));
6142 case 0xfa: /* cli */
6143 case 0xfb: /* sti */
6146 case 0x62: /* bound */
6147 printf_unfiltered (_("Process record does not support "
6148 "instruction bound.\n"));
6153 case 0x0fc8: /* bswap reg */
6161 I386_RECORD_ARCH_LIST_ADD_REG ((opcode
& 7) | ir
.rex_b
);
6164 case 0xd6: /* salc */
6165 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6170 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6171 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6174 case 0xe0: /* loopnz */
6175 case 0xe1: /* loopz */
6176 case 0xe2: /* loop */
6177 case 0xe3: /* jecxz */
6178 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6179 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6182 case 0x0f30: /* wrmsr */
6183 printf_unfiltered (_("Process record does not support "
6184 "instruction wrmsr.\n"));
6189 case 0x0f32: /* rdmsr */
6190 printf_unfiltered (_("Process record does not support "
6191 "instruction rdmsr.\n"));
6196 case 0x0f31: /* rdtsc */
6197 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6198 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
6201 case 0x0f34: /* sysenter */
6204 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6209 if (tdep
->i386_sysenter_record
== NULL
)
6211 printf_unfiltered (_("Process record does not support "
6212 "instruction sysenter.\n"));
6216 ret
= tdep
->i386_sysenter_record (ir
.regcache
);
6222 case 0x0f35: /* sysexit */
6223 printf_unfiltered (_("Process record does not support "
6224 "instruction sysexit.\n"));
6229 case 0x0f05: /* syscall */
6232 if (tdep
->i386_syscall_record
== NULL
)
6234 printf_unfiltered (_("Process record does not support "
6235 "instruction syscall.\n"));
6239 ret
= tdep
->i386_syscall_record (ir
.regcache
);
6245 case 0x0f07: /* sysret */
6246 printf_unfiltered (_("Process record does not support "
6247 "instruction sysret.\n"));
6252 case 0x0fa2: /* cpuid */
6253 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6254 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6255 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
6256 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM
);
6259 case 0xf4: /* hlt */
6260 printf_unfiltered (_("Process record does not support "
6261 "instruction hlt.\n"));
6267 if (i386_record_modrm (&ir
))
6274 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6278 if (i386_record_lea_modrm (&ir
))
6287 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6291 opcode
= opcode
<< 8 | ir
.modrm
;
6298 if (i386_record_modrm (&ir
))
6309 opcode
= opcode
<< 8 | ir
.modrm
;
6312 if (ir
.override
>= 0)
6314 if (record_memory_query
)
6318 target_terminal_ours ();
6320 Process record ignores the memory change of instruction at address %s\n\
6321 because it can't get the value of the segment register.\n\
6322 Do you want to stop the program?"),
6323 paddress (gdbarch
, ir
.orig_addr
));
6324 target_terminal_inferior ();
6331 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
6333 if (record_arch_list_add_mem (addr64
, 2))
6336 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6338 if (record_arch_list_add_mem (addr64
, 8))
6343 if (record_arch_list_add_mem (addr64
, 4))
6354 case 0: /* monitor */
6357 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6361 opcode
= opcode
<< 8 | ir
.modrm
;
6369 if (ir
.override
>= 0)
6371 if (record_memory_query
)
6375 target_terminal_ours ();
6377 Process record ignores the memory change of instruction at address %s\n\
6378 because it can't get the value of the segment register.\n\
6379 Do you want to stop the program?"),
6380 paddress (gdbarch
, ir
.orig_addr
));
6381 target_terminal_inferior ();
6390 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
6392 if (record_arch_list_add_mem (addr64
, 2))
6395 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6397 if (record_arch_list_add_mem (addr64
, 8))
6402 if (record_arch_list_add_mem (addr64
, 4))
6414 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6415 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
6419 else if (ir
.rm
== 1)
6426 opcode
= opcode
<< 8 | ir
.modrm
;
6433 if (record_arch_list_add_reg (ir
.regcache
, ir
.rm
| ir
.rex_b
))
6439 if (i386_record_lea_modrm (&ir
))
6442 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6445 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6447 case 7: /* invlpg */
6450 if (ir
.rm
== 0 && ir
.regmap
[X86_RECORD_R8_REGNUM
])
6451 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM
);
6455 opcode
= opcode
<< 8 | ir
.modrm
;
6460 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6464 opcode
= opcode
<< 8 | ir
.modrm
;
6470 case 0x0f08: /* invd */
6471 case 0x0f09: /* wbinvd */
6474 case 0x63: /* arpl */
6475 if (i386_record_modrm (&ir
))
6477 if (ir
.mod
== 3 || ir
.regmap
[X86_RECORD_R8_REGNUM
])
6479 I386_RECORD_ARCH_LIST_ADD_REG (ir
.regmap
[X86_RECORD_R8_REGNUM
]
6480 ? (ir
.reg
| rex_r
) : ir
.rm
);
6484 ir
.ot
= ir
.dflag
? OT_LONG
: OT_WORD
;
6485 if (i386_record_lea_modrm (&ir
))
6488 if (!ir
.regmap
[X86_RECORD_R8_REGNUM
])
6489 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6492 case 0x0f02: /* lar */
6493 case 0x0f03: /* lsl */
6494 if (i386_record_modrm (&ir
))
6496 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
6497 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6501 if (i386_record_modrm (&ir
))
6503 if (ir
.mod
== 3 && ir
.reg
== 3)
6506 opcode
= opcode
<< 8 | ir
.modrm
;
6518 /* nop (multi byte) */
6521 case 0x0f20: /* mov reg, crN */
6522 case 0x0f22: /* mov crN, reg */
6523 if (i386_record_modrm (&ir
))
6525 if ((ir
.modrm
& 0xc0) != 0xc0)
6528 opcode
= opcode
<< 8 | ir
.modrm
;
6539 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6541 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6545 opcode
= opcode
<< 8 | ir
.modrm
;
6551 case 0x0f21: /* mov reg, drN */
6552 case 0x0f23: /* mov drN, reg */
6553 if (i386_record_modrm (&ir
))
6555 if ((ir
.modrm
& 0xc0) != 0xc0 || ir
.reg
== 4
6556 || ir
.reg
== 5 || ir
.reg
>= 8)
6559 opcode
= opcode
<< 8 | ir
.modrm
;
6563 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6565 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6568 case 0x0f06: /* clts */
6569 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6572 /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */
6574 case 0x0f0d: /* 3DNow! prefetch */
6577 case 0x0f0e: /* 3DNow! femms */
6578 case 0x0f77: /* emms */
6579 if (i386_fpc_regnum_p (gdbarch
, I387_FTAG_REGNUM(tdep
)))
6581 record_arch_list_add_reg (ir
.regcache
, I387_FTAG_REGNUM(tdep
));
6584 case 0x0f0f: /* 3DNow! data */
6585 if (i386_record_modrm (&ir
))
6587 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
6592 case 0x0c: /* 3DNow! pi2fw */
6593 case 0x0d: /* 3DNow! pi2fd */
6594 case 0x1c: /* 3DNow! pf2iw */
6595 case 0x1d: /* 3DNow! pf2id */
6596 case 0x8a: /* 3DNow! pfnacc */
6597 case 0x8e: /* 3DNow! pfpnacc */
6598 case 0x90: /* 3DNow! pfcmpge */
6599 case 0x94: /* 3DNow! pfmin */
6600 case 0x96: /* 3DNow! pfrcp */
6601 case 0x97: /* 3DNow! pfrsqrt */
6602 case 0x9a: /* 3DNow! pfsub */
6603 case 0x9e: /* 3DNow! pfadd */
6604 case 0xa0: /* 3DNow! pfcmpgt */
6605 case 0xa4: /* 3DNow! pfmax */
6606 case 0xa6: /* 3DNow! pfrcpit1 */
6607 case 0xa7: /* 3DNow! pfrsqit1 */
6608 case 0xaa: /* 3DNow! pfsubr */
6609 case 0xae: /* 3DNow! pfacc */
6610 case 0xb0: /* 3DNow! pfcmpeq */
6611 case 0xb4: /* 3DNow! pfmul */
6612 case 0xb6: /* 3DNow! pfrcpit2 */
6613 case 0xb7: /* 3DNow! pmulhrw */
6614 case 0xbb: /* 3DNow! pswapd */
6615 case 0xbf: /* 3DNow! pavgusb */
6616 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.reg
))
6617 goto no_support_3dnow_data
;
6618 record_arch_list_add_reg (ir
.regcache
, ir
.reg
);
6622 no_support_3dnow_data
:
6623 opcode
= (opcode
<< 8) | opcode8
;
6629 case 0x0faa: /* rsm */
6630 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6631 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6632 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6633 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
6634 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM
);
6635 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
6636 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
6637 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
6638 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
6642 if (i386_record_modrm (&ir
))
6646 case 0: /* fxsave */
6650 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6651 if (i386_record_lea_modrm_addr (&ir
, &tmpu64
))
6653 if (record_arch_list_add_mem (tmpu64
, 512))
6658 case 1: /* fxrstor */
6662 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6664 for (i
= I387_MM0_REGNUM (tdep
);
6665 i386_mmx_regnum_p (gdbarch
, i
); i
++)
6666 record_arch_list_add_reg (ir
.regcache
, i
);
6668 for (i
= I387_XMM0_REGNUM (tdep
);
6669 i386_xmm_regnum_p (gdbarch
, i
); i
++)
6670 record_arch_list_add_reg (ir
.regcache
, i
);
6672 if (i386_mxcsr_regnum_p (gdbarch
, I387_MXCSR_REGNUM(tdep
)))
6673 record_arch_list_add_reg (ir
.regcache
, I387_MXCSR_REGNUM(tdep
));
6675 for (i
= I387_ST0_REGNUM (tdep
);
6676 i386_fp_regnum_p (gdbarch
, i
); i
++)
6677 record_arch_list_add_reg (ir
.regcache
, i
);
6679 for (i
= I387_FCTRL_REGNUM (tdep
);
6680 i386_fpc_regnum_p (gdbarch
, i
); i
++)
6681 record_arch_list_add_reg (ir
.regcache
, i
);
6685 case 2: /* ldmxcsr */
6686 if (!i386_mxcsr_regnum_p (gdbarch
, I387_MXCSR_REGNUM(tdep
)))
6688 record_arch_list_add_reg (ir
.regcache
, I387_MXCSR_REGNUM(tdep
));
6691 case 3: /* stmxcsr */
6693 if (i386_record_lea_modrm (&ir
))
6697 case 5: /* lfence */
6698 case 6: /* mfence */
6699 case 7: /* sfence clflush */
6703 opcode
= (opcode
<< 8) | ir
.modrm
;
6709 case 0x0fc3: /* movnti */
6710 ir
.ot
= (ir
.dflag
== 2) ? OT_QUAD
: OT_LONG
;
6711 if (i386_record_modrm (&ir
))
6716 if (i386_record_lea_modrm (&ir
))
6720 /* Add prefix to opcode. */
6847 reswitch_prefix_add
:
6855 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
6858 opcode
= (uint32_t) opcode8
| opcode
<< 8;
6859 goto reswitch_prefix_add
;
6862 case 0x0f10: /* movups */
6863 case 0x660f10: /* movupd */
6864 case 0xf30f10: /* movss */
6865 case 0xf20f10: /* movsd */
6866 case 0x0f12: /* movlps */
6867 case 0x660f12: /* movlpd */
6868 case 0xf30f12: /* movsldup */
6869 case 0xf20f12: /* movddup */
6870 case 0x0f14: /* unpcklps */
6871 case 0x660f14: /* unpcklpd */
6872 case 0x0f15: /* unpckhps */
6873 case 0x660f15: /* unpckhpd */
6874 case 0x0f16: /* movhps */
6875 case 0x660f16: /* movhpd */
6876 case 0xf30f16: /* movshdup */
6877 case 0x0f28: /* movaps */
6878 case 0x660f28: /* movapd */
6879 case 0x0f2a: /* cvtpi2ps */
6880 case 0x660f2a: /* cvtpi2pd */
6881 case 0xf30f2a: /* cvtsi2ss */
6882 case 0xf20f2a: /* cvtsi2sd */
6883 case 0x0f2c: /* cvttps2pi */
6884 case 0x660f2c: /* cvttpd2pi */
6885 case 0x0f2d: /* cvtps2pi */
6886 case 0x660f2d: /* cvtpd2pi */
6887 case 0x660f3800: /* pshufb */
6888 case 0x660f3801: /* phaddw */
6889 case 0x660f3802: /* phaddd */
6890 case 0x660f3803: /* phaddsw */
6891 case 0x660f3804: /* pmaddubsw */
6892 case 0x660f3805: /* phsubw */
6893 case 0x660f3806: /* phsubd */
6894 case 0x660f3807: /* phsubsw */
6895 case 0x660f3808: /* psignb */
6896 case 0x660f3809: /* psignw */
6897 case 0x660f380a: /* psignd */
6898 case 0x660f380b: /* pmulhrsw */
6899 case 0x660f3810: /* pblendvb */
6900 case 0x660f3814: /* blendvps */
6901 case 0x660f3815: /* blendvpd */
6902 case 0x660f381c: /* pabsb */
6903 case 0x660f381d: /* pabsw */
6904 case 0x660f381e: /* pabsd */
6905 case 0x660f3820: /* pmovsxbw */
6906 case 0x660f3821: /* pmovsxbd */
6907 case 0x660f3822: /* pmovsxbq */
6908 case 0x660f3823: /* pmovsxwd */
6909 case 0x660f3824: /* pmovsxwq */
6910 case 0x660f3825: /* pmovsxdq */
6911 case 0x660f3828: /* pmuldq */
6912 case 0x660f3829: /* pcmpeqq */
6913 case 0x660f382a: /* movntdqa */
6914 case 0x660f3a08: /* roundps */
6915 case 0x660f3a09: /* roundpd */
6916 case 0x660f3a0a: /* roundss */
6917 case 0x660f3a0b: /* roundsd */
6918 case 0x660f3a0c: /* blendps */
6919 case 0x660f3a0d: /* blendpd */
6920 case 0x660f3a0e: /* pblendw */
6921 case 0x660f3a0f: /* palignr */
6922 case 0x660f3a20: /* pinsrb */
6923 case 0x660f3a21: /* insertps */
6924 case 0x660f3a22: /* pinsrd pinsrq */
6925 case 0x660f3a40: /* dpps */
6926 case 0x660f3a41: /* dppd */
6927 case 0x660f3a42: /* mpsadbw */
6928 case 0x660f3a60: /* pcmpestrm */
6929 case 0x660f3a61: /* pcmpestri */
6930 case 0x660f3a62: /* pcmpistrm */
6931 case 0x660f3a63: /* pcmpistri */
6932 case 0x0f51: /* sqrtps */
6933 case 0x660f51: /* sqrtpd */
6934 case 0xf20f51: /* sqrtsd */
6935 case 0xf30f51: /* sqrtss */
6936 case 0x0f52: /* rsqrtps */
6937 case 0xf30f52: /* rsqrtss */
6938 case 0x0f53: /* rcpps */
6939 case 0xf30f53: /* rcpss */
6940 case 0x0f54: /* andps */
6941 case 0x660f54: /* andpd */
6942 case 0x0f55: /* andnps */
6943 case 0x660f55: /* andnpd */
6944 case 0x0f56: /* orps */
6945 case 0x660f56: /* orpd */
6946 case 0x0f57: /* xorps */
6947 case 0x660f57: /* xorpd */
6948 case 0x0f58: /* addps */
6949 case 0x660f58: /* addpd */
6950 case 0xf20f58: /* addsd */
6951 case 0xf30f58: /* addss */
6952 case 0x0f59: /* mulps */
6953 case 0x660f59: /* mulpd */
6954 case 0xf20f59: /* mulsd */
6955 case 0xf30f59: /* mulss */
6956 case 0x0f5a: /* cvtps2pd */
6957 case 0x660f5a: /* cvtpd2ps */
6958 case 0xf20f5a: /* cvtsd2ss */
6959 case 0xf30f5a: /* cvtss2sd */
6960 case 0x0f5b: /* cvtdq2ps */
6961 case 0x660f5b: /* cvtps2dq */
6962 case 0xf30f5b: /* cvttps2dq */
6963 case 0x0f5c: /* subps */
6964 case 0x660f5c: /* subpd */
6965 case 0xf20f5c: /* subsd */
6966 case 0xf30f5c: /* subss */
6967 case 0x0f5d: /* minps */
6968 case 0x660f5d: /* minpd */
6969 case 0xf20f5d: /* minsd */
6970 case 0xf30f5d: /* minss */
6971 case 0x0f5e: /* divps */
6972 case 0x660f5e: /* divpd */
6973 case 0xf20f5e: /* divsd */
6974 case 0xf30f5e: /* divss */
6975 case 0x0f5f: /* maxps */
6976 case 0x660f5f: /* maxpd */
6977 case 0xf20f5f: /* maxsd */
6978 case 0xf30f5f: /* maxss */
6979 case 0x660f60: /* punpcklbw */
6980 case 0x660f61: /* punpcklwd */
6981 case 0x660f62: /* punpckldq */
6982 case 0x660f63: /* packsswb */
6983 case 0x660f64: /* pcmpgtb */
6984 case 0x660f65: /* pcmpgtw */
6985 case 0x660f66: /* pcmpgtd */
6986 case 0x660f67: /* packuswb */
6987 case 0x660f68: /* punpckhbw */
6988 case 0x660f69: /* punpckhwd */
6989 case 0x660f6a: /* punpckhdq */
6990 case 0x660f6b: /* packssdw */
6991 case 0x660f6c: /* punpcklqdq */
6992 case 0x660f6d: /* punpckhqdq */
6993 case 0x660f6e: /* movd */
6994 case 0x660f6f: /* movdqa */
6995 case 0xf30f6f: /* movdqu */
6996 case 0x660f70: /* pshufd */
6997 case 0xf20f70: /* pshuflw */
6998 case 0xf30f70: /* pshufhw */
6999 case 0x660f74: /* pcmpeqb */
7000 case 0x660f75: /* pcmpeqw */
7001 case 0x660f76: /* pcmpeqd */
7002 case 0x660f7c: /* haddpd */
7003 case 0xf20f7c: /* haddps */
7004 case 0x660f7d: /* hsubpd */
7005 case 0xf20f7d: /* hsubps */
7006 case 0xf30f7e: /* movq */
7007 case 0x0fc2: /* cmpps */
7008 case 0x660fc2: /* cmppd */
7009 case 0xf20fc2: /* cmpsd */
7010 case 0xf30fc2: /* cmpss */
7011 case 0x660fc4: /* pinsrw */
7012 case 0x0fc6: /* shufps */
7013 case 0x660fc6: /* shufpd */
7014 case 0x660fd0: /* addsubpd */
7015 case 0xf20fd0: /* addsubps */
7016 case 0x660fd1: /* psrlw */
7017 case 0x660fd2: /* psrld */
7018 case 0x660fd3: /* psrlq */
7019 case 0x660fd4: /* paddq */
7020 case 0x660fd5: /* pmullw */
7021 case 0xf30fd6: /* movq2dq */
7022 case 0x660fd8: /* psubusb */
7023 case 0x660fd9: /* psubusw */
7024 case 0x660fda: /* pminub */
7025 case 0x660fdb: /* pand */
7026 case 0x660fdc: /* paddusb */
7027 case 0x660fdd: /* paddusw */
7028 case 0x660fde: /* pmaxub */
7029 case 0x660fdf: /* pandn */
7030 case 0x660fe0: /* pavgb */
7031 case 0x660fe1: /* psraw */
7032 case 0x660fe2: /* psrad */
7033 case 0x660fe3: /* pavgw */
7034 case 0x660fe4: /* pmulhuw */
7035 case 0x660fe5: /* pmulhw */
7036 case 0x660fe6: /* cvttpd2dq */
7037 case 0xf20fe6: /* cvtpd2dq */
7038 case 0xf30fe6: /* cvtdq2pd */
7039 case 0x660fe8: /* psubsb */
7040 case 0x660fe9: /* psubsw */
7041 case 0x660fea: /* pminsw */
7042 case 0x660feb: /* por */
7043 case 0x660fec: /* paddsb */
7044 case 0x660fed: /* paddsw */
7045 case 0x660fee: /* pmaxsw */
7046 case 0x660fef: /* pxor */
7047 case 0xf20ff0: /* lddqu */
7048 case 0x660ff1: /* psllw */
7049 case 0x660ff2: /* pslld */
7050 case 0x660ff3: /* psllq */
7051 case 0x660ff4: /* pmuludq */
7052 case 0x660ff5: /* pmaddwd */
7053 case 0x660ff6: /* psadbw */
7054 case 0x660ff8: /* psubb */
7055 case 0x660ff9: /* psubw */
7056 case 0x660ffa: /* psubd */
7057 case 0x660ffb: /* psubq */
7058 case 0x660ffc: /* paddb */
7059 case 0x660ffd: /* paddw */
7060 case 0x660ffe: /* paddd */
7061 if (i386_record_modrm (&ir
))
7064 if (!i386_xmm_regnum_p (gdbarch
, I387_XMM0_REGNUM (tdep
) + ir
.reg
))
7066 record_arch_list_add_reg (ir
.regcache
,
7067 I387_XMM0_REGNUM (tdep
) + ir
.reg
);
7068 if ((opcode
& 0xfffffffc) == 0x660f3a60)
7069 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7072 case 0x0f11: /* movups */
7073 case 0x660f11: /* movupd */
7074 case 0xf30f11: /* movss */
7075 case 0xf20f11: /* movsd */
7076 case 0x0f13: /* movlps */
7077 case 0x660f13: /* movlpd */
7078 case 0x0f17: /* movhps */
7079 case 0x660f17: /* movhpd */
7080 case 0x0f29: /* movaps */
7081 case 0x660f29: /* movapd */
7082 case 0x660f3a14: /* pextrb */
7083 case 0x660f3a15: /* pextrw */
7084 case 0x660f3a16: /* pextrd pextrq */
7085 case 0x660f3a17: /* extractps */
7086 case 0x660f7f: /* movdqa */
7087 case 0xf30f7f: /* movdqu */
7088 if (i386_record_modrm (&ir
))
7092 if (opcode
== 0x0f13 || opcode
== 0x660f13
7093 || opcode
== 0x0f17 || opcode
== 0x660f17)
7096 if (!i386_xmm_regnum_p (gdbarch
,
7097 I387_XMM0_REGNUM (tdep
) + ir
.rm
))
7099 record_arch_list_add_reg (ir
.regcache
,
7100 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
7122 if (i386_record_lea_modrm (&ir
))
7127 case 0x0f2b: /* movntps */
7128 case 0x660f2b: /* movntpd */
7129 case 0x0fe7: /* movntq */
7130 case 0x660fe7: /* movntdq */
7133 if (opcode
== 0x0fe7)
7137 if (i386_record_lea_modrm (&ir
))
7141 case 0xf30f2c: /* cvttss2si */
7142 case 0xf20f2c: /* cvttsd2si */
7143 case 0xf30f2d: /* cvtss2si */
7144 case 0xf20f2d: /* cvtsd2si */
7145 case 0xf20f38f0: /* crc32 */
7146 case 0xf20f38f1: /* crc32 */
7147 case 0x0f50: /* movmskps */
7148 case 0x660f50: /* movmskpd */
7149 case 0x0fc5: /* pextrw */
7150 case 0x660fc5: /* pextrw */
7151 case 0x0fd7: /* pmovmskb */
7152 case 0x660fd7: /* pmovmskb */
7153 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
7156 case 0x0f3800: /* pshufb */
7157 case 0x0f3801: /* phaddw */
7158 case 0x0f3802: /* phaddd */
7159 case 0x0f3803: /* phaddsw */
7160 case 0x0f3804: /* pmaddubsw */
7161 case 0x0f3805: /* phsubw */
7162 case 0x0f3806: /* phsubd */
7163 case 0x0f3807: /* phsubsw */
7164 case 0x0f3808: /* psignb */
7165 case 0x0f3809: /* psignw */
7166 case 0x0f380a: /* psignd */
7167 case 0x0f380b: /* pmulhrsw */
7168 case 0x0f381c: /* pabsb */
7169 case 0x0f381d: /* pabsw */
7170 case 0x0f381e: /* pabsd */
7171 case 0x0f382b: /* packusdw */
7172 case 0x0f3830: /* pmovzxbw */
7173 case 0x0f3831: /* pmovzxbd */
7174 case 0x0f3832: /* pmovzxbq */
7175 case 0x0f3833: /* pmovzxwd */
7176 case 0x0f3834: /* pmovzxwq */
7177 case 0x0f3835: /* pmovzxdq */
7178 case 0x0f3837: /* pcmpgtq */
7179 case 0x0f3838: /* pminsb */
7180 case 0x0f3839: /* pminsd */
7181 case 0x0f383a: /* pminuw */
7182 case 0x0f383b: /* pminud */
7183 case 0x0f383c: /* pmaxsb */
7184 case 0x0f383d: /* pmaxsd */
7185 case 0x0f383e: /* pmaxuw */
7186 case 0x0f383f: /* pmaxud */
7187 case 0x0f3840: /* pmulld */
7188 case 0x0f3841: /* phminposuw */
7189 case 0x0f3a0f: /* palignr */
7190 case 0x0f60: /* punpcklbw */
7191 case 0x0f61: /* punpcklwd */
7192 case 0x0f62: /* punpckldq */
7193 case 0x0f63: /* packsswb */
7194 case 0x0f64: /* pcmpgtb */
7195 case 0x0f65: /* pcmpgtw */
7196 case 0x0f66: /* pcmpgtd */
7197 case 0x0f67: /* packuswb */
7198 case 0x0f68: /* punpckhbw */
7199 case 0x0f69: /* punpckhwd */
7200 case 0x0f6a: /* punpckhdq */
7201 case 0x0f6b: /* packssdw */
7202 case 0x0f6e: /* movd */
7203 case 0x0f6f: /* movq */
7204 case 0x0f70: /* pshufw */
7205 case 0x0f74: /* pcmpeqb */
7206 case 0x0f75: /* pcmpeqw */
7207 case 0x0f76: /* pcmpeqd */
7208 case 0x0fc4: /* pinsrw */
7209 case 0x0fd1: /* psrlw */
7210 case 0x0fd2: /* psrld */
7211 case 0x0fd3: /* psrlq */
7212 case 0x0fd4: /* paddq */
7213 case 0x0fd5: /* pmullw */
7214 case 0xf20fd6: /* movdq2q */
7215 case 0x0fd8: /* psubusb */
7216 case 0x0fd9: /* psubusw */
7217 case 0x0fda: /* pminub */
7218 case 0x0fdb: /* pand */
7219 case 0x0fdc: /* paddusb */
7220 case 0x0fdd: /* paddusw */
7221 case 0x0fde: /* pmaxub */
7222 case 0x0fdf: /* pandn */
7223 case 0x0fe0: /* pavgb */
7224 case 0x0fe1: /* psraw */
7225 case 0x0fe2: /* psrad */
7226 case 0x0fe3: /* pavgw */
7227 case 0x0fe4: /* pmulhuw */
7228 case 0x0fe5: /* pmulhw */
7229 case 0x0fe8: /* psubsb */
7230 case 0x0fe9: /* psubsw */
7231 case 0x0fea: /* pminsw */
7232 case 0x0feb: /* por */
7233 case 0x0fec: /* paddsb */
7234 case 0x0fed: /* paddsw */
7235 case 0x0fee: /* pmaxsw */
7236 case 0x0fef: /* pxor */
7237 case 0x0ff1: /* psllw */
7238 case 0x0ff2: /* pslld */
7239 case 0x0ff3: /* psllq */
7240 case 0x0ff4: /* pmuludq */
7241 case 0x0ff5: /* pmaddwd */
7242 case 0x0ff6: /* psadbw */
7243 case 0x0ff8: /* psubb */
7244 case 0x0ff9: /* psubw */
7245 case 0x0ffa: /* psubd */
7246 case 0x0ffb: /* psubq */
7247 case 0x0ffc: /* paddb */
7248 case 0x0ffd: /* paddw */
7249 case 0x0ffe: /* paddd */
7250 if (i386_record_modrm (&ir
))
7252 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.reg
))
7254 record_arch_list_add_reg (ir
.regcache
,
7255 I387_MM0_REGNUM (tdep
) + ir
.reg
);
7258 case 0x0f71: /* psllw */
7259 case 0x0f72: /* pslld */
7260 case 0x0f73: /* psllq */
7261 if (i386_record_modrm (&ir
))
7263 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.rm
))
7265 record_arch_list_add_reg (ir
.regcache
,
7266 I387_MM0_REGNUM (tdep
) + ir
.rm
);
7269 case 0x660f71: /* psllw */
7270 case 0x660f72: /* pslld */
7271 case 0x660f73: /* psllq */
7272 if (i386_record_modrm (&ir
))
7275 if (!i386_xmm_regnum_p (gdbarch
, I387_XMM0_REGNUM (tdep
) + ir
.rm
))
7277 record_arch_list_add_reg (ir
.regcache
,
7278 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
7281 case 0x0f7e: /* movd */
7282 case 0x660f7e: /* movd */
7283 if (i386_record_modrm (&ir
))
7286 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
7293 if (i386_record_lea_modrm (&ir
))
7298 case 0x0f7f: /* movq */
7299 if (i386_record_modrm (&ir
))
7303 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.rm
))
7305 record_arch_list_add_reg (ir
.regcache
,
7306 I387_MM0_REGNUM (tdep
) + ir
.rm
);
7311 if (i386_record_lea_modrm (&ir
))
7316 case 0xf30fb8: /* popcnt */
7317 if (i386_record_modrm (&ir
))
7319 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
7320 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7323 case 0x660fd6: /* movq */
7324 if (i386_record_modrm (&ir
))
7329 if (!i386_xmm_regnum_p (gdbarch
,
7330 I387_XMM0_REGNUM (tdep
) + ir
.rm
))
7332 record_arch_list_add_reg (ir
.regcache
,
7333 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
7338 if (i386_record_lea_modrm (&ir
))
7343 case 0x660f3817: /* ptest */
7344 case 0x0f2e: /* ucomiss */
7345 case 0x660f2e: /* ucomisd */
7346 case 0x0f2f: /* comiss */
7347 case 0x660f2f: /* comisd */
7348 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7351 case 0x0ff7: /* maskmovq */
7352 regcache_raw_read_unsigned (ir
.regcache
,
7353 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
7355 if (record_arch_list_add_mem (addr
, 64))
7359 case 0x660ff7: /* maskmovdqu */
7360 regcache_raw_read_unsigned (ir
.regcache
,
7361 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
7363 if (record_arch_list_add_mem (addr
, 128))
7378 /* In the future, maybe still need to deal with need_dasm. */
7379 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM
);
7380 if (record_arch_list_add_end ())
7386 printf_unfiltered (_("Process record does not support instruction 0x%02x "
7387 "at address %s.\n"),
7388 (unsigned int) (opcode
),
7389 paddress (gdbarch
, ir
.orig_addr
));
7393 static const int i386_record_regmap
[] =
7395 I386_EAX_REGNUM
, I386_ECX_REGNUM
, I386_EDX_REGNUM
, I386_EBX_REGNUM
,
7396 I386_ESP_REGNUM
, I386_EBP_REGNUM
, I386_ESI_REGNUM
, I386_EDI_REGNUM
,
7397 0, 0, 0, 0, 0, 0, 0, 0,
7398 I386_EIP_REGNUM
, I386_EFLAGS_REGNUM
, I386_CS_REGNUM
, I386_SS_REGNUM
,
7399 I386_DS_REGNUM
, I386_ES_REGNUM
, I386_FS_REGNUM
, I386_GS_REGNUM
7402 /* Check that the given address appears suitable for a fast
7403 tracepoint, which on x86-64 means that we need an instruction of at
7404 least 5 bytes, so that we can overwrite it with a 4-byte-offset
7405 jump and not have to worry about program jumps to an address in the
7406 middle of the tracepoint jump. On x86, it may be possible to use
7407 4-byte jumps with a 2-byte offset to a trampoline located in the
7408 bottom 64 KiB of memory. Returns 1 if OK, and writes a size
7409 of instruction to replace, and 0 if not, plus an explanatory
7413 i386_fast_tracepoint_valid_at (struct gdbarch
*gdbarch
,
7414 CORE_ADDR addr
, int *isize
, char **msg
)
7417 static struct ui_file
*gdb_null
= NULL
;
7419 /* Ask the target for the minimum instruction length supported. */
7420 jumplen
= target_get_min_fast_tracepoint_insn_len ();
7424 /* If the target does not support the get_min_fast_tracepoint_insn_len
7425 operation, assume that fast tracepoints will always be implemented
7426 using 4-byte relative jumps on both x86 and x86-64. */
7429 else if (jumplen
== 0)
7431 /* If the target does support get_min_fast_tracepoint_insn_len but
7432 returns zero, then the IPA has not loaded yet. In this case,
7433 we optimistically assume that truncated 2-byte relative jumps
7434 will be available on x86, and compensate later if this assumption
7435 turns out to be incorrect. On x86-64 architectures, 4-byte relative
7436 jumps will always be used. */
7437 jumplen
= (register_size (gdbarch
, 0) == 8) ? 5 : 4;
7440 /* Dummy file descriptor for the disassembler. */
7442 gdb_null
= ui_file_new ();
7444 /* Check for fit. */
7445 len
= gdb_print_insn (gdbarch
, addr
, gdb_null
, NULL
);
7451 /* Return a bit of target-specific detail to add to the caller's
7452 generic failure message. */
7454 *msg
= xstrprintf (_("; instruction is only %d bytes long, "
7455 "need at least %d bytes for the jump"),
7468 i386_validate_tdesc_p (struct gdbarch_tdep
*tdep
,
7469 struct tdesc_arch_data
*tdesc_data
)
7471 const struct target_desc
*tdesc
= tdep
->tdesc
;
7472 const struct tdesc_feature
*feature_core
;
7473 const struct tdesc_feature
*feature_sse
, *feature_avx
;
7474 int i
, num_regs
, valid_p
;
7476 if (! tdesc_has_registers (tdesc
))
7479 /* Get core registers. */
7480 feature_core
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.core");
7481 if (feature_core
== NULL
)
7484 /* Get SSE registers. */
7485 feature_sse
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.sse");
7487 /* Try AVX registers. */
7488 feature_avx
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx");
7492 /* The XCR0 bits. */
7495 /* AVX register description requires SSE register description. */
7499 tdep
->xcr0
= I386_XSTATE_AVX_MASK
;
7501 /* It may have been set by OSABI initialization function. */
7502 if (tdep
->num_ymm_regs
== 0)
7504 tdep
->ymmh_register_names
= i386_ymmh_names
;
7505 tdep
->num_ymm_regs
= 8;
7506 tdep
->ymm0h_regnum
= I386_YMM0H_REGNUM
;
7509 for (i
= 0; i
< tdep
->num_ymm_regs
; i
++)
7510 valid_p
&= tdesc_numbered_register (feature_avx
, tdesc_data
,
7511 tdep
->ymm0h_regnum
+ i
,
7512 tdep
->ymmh_register_names
[i
]);
7514 else if (feature_sse
)
7515 tdep
->xcr0
= I386_XSTATE_SSE_MASK
;
7518 tdep
->xcr0
= I386_XSTATE_X87_MASK
;
7519 tdep
->num_xmm_regs
= 0;
7522 num_regs
= tdep
->num_core_regs
;
7523 for (i
= 0; i
< num_regs
; i
++)
7524 valid_p
&= tdesc_numbered_register (feature_core
, tdesc_data
, i
,
7525 tdep
->register_names
[i
]);
7529 /* Need to include %mxcsr, so add one. */
7530 num_regs
+= tdep
->num_xmm_regs
+ 1;
7531 for (; i
< num_regs
; i
++)
7532 valid_p
&= tdesc_numbered_register (feature_sse
, tdesc_data
, i
,
7533 tdep
->register_names
[i
]);
7540 static struct gdbarch
*
7541 i386_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
7543 struct gdbarch_tdep
*tdep
;
7544 struct gdbarch
*gdbarch
;
7545 struct tdesc_arch_data
*tdesc_data
;
7546 const struct target_desc
*tdesc
;
7550 /* If there is already a candidate, use it. */
7551 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
7553 return arches
->gdbarch
;
7555 /* Allocate space for the new architecture. */
7556 tdep
= XCALLOC (1, struct gdbarch_tdep
);
7557 gdbarch
= gdbarch_alloc (&info
, tdep
);
7559 /* General-purpose registers. */
7560 tdep
->gregset
= NULL
;
7561 tdep
->gregset_reg_offset
= NULL
;
7562 tdep
->gregset_num_regs
= I386_NUM_GREGS
;
7563 tdep
->sizeof_gregset
= 0;
7565 /* Floating-point registers. */
7566 tdep
->fpregset
= NULL
;
7567 tdep
->sizeof_fpregset
= I387_SIZEOF_FSAVE
;
7569 tdep
->xstateregset
= NULL
;
7571 /* The default settings include the FPU registers, the MMX registers
7572 and the SSE registers. This can be overridden for a specific ABI
7573 by adjusting the members `st0_regnum', `mm0_regnum' and
7574 `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers
7575 will show up in the output of "info all-registers". */
7577 tdep
->st0_regnum
= I386_ST0_REGNUM
;
7579 /* I386_NUM_XREGS includes %mxcsr, so substract one. */
7580 tdep
->num_xmm_regs
= I386_NUM_XREGS
- 1;
7582 tdep
->jb_pc_offset
= -1;
7583 tdep
->struct_return
= pcc_struct_return
;
7584 tdep
->sigtramp_start
= 0;
7585 tdep
->sigtramp_end
= 0;
7586 tdep
->sigtramp_p
= i386_sigtramp_p
;
7587 tdep
->sigcontext_addr
= NULL
;
7588 tdep
->sc_reg_offset
= NULL
;
7589 tdep
->sc_pc_offset
= -1;
7590 tdep
->sc_sp_offset
= -1;
7592 tdep
->xsave_xcr0_offset
= -1;
7594 tdep
->record_regmap
= i386_record_regmap
;
7596 set_gdbarch_long_long_align_bit (gdbarch
, 32);
7598 /* The format used for `long double' on almost all i386 targets is
7599 the i387 extended floating-point format. In fact, of all targets
7600 in the GCC 2.95 tree, only OSF/1 does it different, and insists
7601 on having a `long double' that's not `long' at all. */
7602 set_gdbarch_long_double_format (gdbarch
, floatformats_i387_ext
);
7604 /* Although the i387 extended floating-point has only 80 significant
7605 bits, a `long double' actually takes up 96, probably to enforce
7607 set_gdbarch_long_double_bit (gdbarch
, 96);
7609 /* Register numbers of various important registers. */
7610 set_gdbarch_sp_regnum (gdbarch
, I386_ESP_REGNUM
); /* %esp */
7611 set_gdbarch_pc_regnum (gdbarch
, I386_EIP_REGNUM
); /* %eip */
7612 set_gdbarch_ps_regnum (gdbarch
, I386_EFLAGS_REGNUM
); /* %eflags */
7613 set_gdbarch_fp0_regnum (gdbarch
, I386_ST0_REGNUM
); /* %st(0) */
7615 /* NOTE: kettenis/20040418: GCC does have two possible register
7616 numbering schemes on the i386: dbx and SVR4. These schemes
7617 differ in how they number %ebp, %esp, %eflags, and the
7618 floating-point registers, and are implemented by the arrays
7619 dbx_register_map[] and svr4_dbx_register_map in
7620 gcc/config/i386.c. GCC also defines a third numbering scheme in
7621 gcc/config/i386.c, which it designates as the "default" register
7622 map used in 64bit mode. This last register numbering scheme is
7623 implemented in dbx64_register_map, and is used for AMD64; see
7626 Currently, each GCC i386 target always uses the same register
7627 numbering scheme across all its supported debugging formats
7628 i.e. SDB (COFF), stabs and DWARF 2. This is because
7629 gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the
7630 DBX_REGISTER_NUMBER macro which is defined by each target's
7631 respective config header in a manner independent of the requested
7632 output debugging format.
7634 This does not match the arrangement below, which presumes that
7635 the SDB and stabs numbering schemes differ from the DWARF and
7636 DWARF 2 ones. The reason for this arrangement is that it is
7637 likely to get the numbering scheme for the target's
7638 default/native debug format right. For targets where GCC is the
7639 native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for
7640 targets where the native toolchain uses a different numbering
7641 scheme for a particular debug format (stabs-in-ELF on Solaris)
7642 the defaults below will have to be overridden, like
7643 i386_elf_init_abi() does. */
7645 /* Use the dbx register numbering scheme for stabs and COFF. */
7646 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
7647 set_gdbarch_sdb_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
7649 /* Use the SVR4 register numbering scheme for DWARF 2. */
7650 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
7652 /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to
7653 be in use on any of the supported i386 targets. */
7655 set_gdbarch_print_float_info (gdbarch
, i387_print_float_info
);
7657 set_gdbarch_get_longjmp_target (gdbarch
, i386_get_longjmp_target
);
7659 /* Call dummy code. */
7660 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
7661 set_gdbarch_push_dummy_code (gdbarch
, i386_push_dummy_code
);
7662 set_gdbarch_push_dummy_call (gdbarch
, i386_push_dummy_call
);
7663 set_gdbarch_frame_align (gdbarch
, i386_frame_align
);
7665 set_gdbarch_convert_register_p (gdbarch
, i386_convert_register_p
);
7666 set_gdbarch_register_to_value (gdbarch
, i386_register_to_value
);
7667 set_gdbarch_value_to_register (gdbarch
, i386_value_to_register
);
7669 set_gdbarch_return_value (gdbarch
, i386_return_value
);
7671 set_gdbarch_skip_prologue (gdbarch
, i386_skip_prologue
);
7673 /* Stack grows downward. */
7674 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
7676 set_gdbarch_breakpoint_from_pc (gdbarch
, i386_breakpoint_from_pc
);
7677 set_gdbarch_decr_pc_after_break (gdbarch
, 1);
7678 set_gdbarch_max_insn_length (gdbarch
, I386_MAX_INSN_LEN
);
7680 set_gdbarch_frame_args_skip (gdbarch
, 8);
7682 set_gdbarch_print_insn (gdbarch
, i386_print_insn
);
7684 set_gdbarch_dummy_id (gdbarch
, i386_dummy_id
);
7686 set_gdbarch_unwind_pc (gdbarch
, i386_unwind_pc
);
7688 /* Add the i386 register groups. */
7689 i386_add_reggroups (gdbarch
);
7690 tdep
->register_reggroup_p
= i386_register_reggroup_p
;
7692 /* Helper for function argument information. */
7693 set_gdbarch_fetch_pointer_argument (gdbarch
, i386_fetch_pointer_argument
);
7695 /* Hook the function epilogue frame unwinder. This unwinder is
7696 appended to the list first, so that it supercedes the DWARF
7697 unwinder in function epilogues (where the DWARF unwinder
7698 currently fails). */
7699 frame_unwind_append_unwinder (gdbarch
, &i386_epilogue_frame_unwind
);
7701 /* Hook in the DWARF CFI frame unwinder. This unwinder is appended
7702 to the list before the prologue-based unwinders, so that DWARF
7703 CFI info will be used if it is available. */
7704 dwarf2_append_unwinders (gdbarch
);
7706 frame_base_set_default (gdbarch
, &i386_frame_base
);
7708 /* Pseudo registers may be changed by amd64_init_abi. */
7709 set_gdbarch_pseudo_register_read_value (gdbarch
,
7710 i386_pseudo_register_read_value
);
7711 set_gdbarch_pseudo_register_write (gdbarch
, i386_pseudo_register_write
);
7713 set_tdesc_pseudo_register_type (gdbarch
, i386_pseudo_register_type
);
7714 set_tdesc_pseudo_register_name (gdbarch
, i386_pseudo_register_name
);
7716 /* Override the normal target description method to make the AVX
7717 upper halves anonymous. */
7718 set_gdbarch_register_name (gdbarch
, i386_register_name
);
7720 /* Even though the default ABI only includes general-purpose registers,
7721 floating-point registers and the SSE registers, we have to leave a
7722 gap for the upper AVX registers. */
7723 set_gdbarch_num_regs (gdbarch
, I386_AVX_NUM_REGS
);
7725 /* Get the x86 target description from INFO. */
7726 tdesc
= info
.target_desc
;
7727 if (! tdesc_has_registers (tdesc
))
7729 tdep
->tdesc
= tdesc
;
7731 tdep
->num_core_regs
= I386_NUM_GREGS
+ I387_NUM_REGS
;
7732 tdep
->register_names
= i386_register_names
;
7734 /* No upper YMM registers. */
7735 tdep
->ymmh_register_names
= NULL
;
7736 tdep
->ymm0h_regnum
= -1;
7738 tdep
->num_byte_regs
= 8;
7739 tdep
->num_word_regs
= 8;
7740 tdep
->num_dword_regs
= 0;
7741 tdep
->num_mmx_regs
= 8;
7742 tdep
->num_ymm_regs
= 0;
7744 tdesc_data
= tdesc_data_alloc ();
7746 set_gdbarch_relocate_instruction (gdbarch
, i386_relocate_instruction
);
7748 set_gdbarch_gen_return_address (gdbarch
, i386_gen_return_address
);
7750 /* Hook in ABI-specific overrides, if they have been registered. */
7751 info
.tdep_info
= (void *) tdesc_data
;
7752 gdbarch_init_osabi (info
, gdbarch
);
7754 if (!i386_validate_tdesc_p (tdep
, tdesc_data
))
7756 tdesc_data_cleanup (tdesc_data
);
7758 gdbarch_free (gdbarch
);
7762 /* Wire in pseudo registers. Number of pseudo registers may be
7764 set_gdbarch_num_pseudo_regs (gdbarch
, (tdep
->num_byte_regs
7765 + tdep
->num_word_regs
7766 + tdep
->num_dword_regs
7767 + tdep
->num_mmx_regs
7768 + tdep
->num_ymm_regs
));
7770 /* Target description may be changed. */
7771 tdesc
= tdep
->tdesc
;
7773 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
7775 /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */
7776 set_gdbarch_register_reggroup_p (gdbarch
, tdep
->register_reggroup_p
);
7778 /* Make %al the first pseudo-register. */
7779 tdep
->al_regnum
= gdbarch_num_regs (gdbarch
);
7780 tdep
->ax_regnum
= tdep
->al_regnum
+ tdep
->num_byte_regs
;
7782 ymm0_regnum
= tdep
->ax_regnum
+ tdep
->num_word_regs
;
7783 if (tdep
->num_dword_regs
)
7785 /* Support dword pseudo-register if it hasn't been disabled. */
7786 tdep
->eax_regnum
= ymm0_regnum
;
7787 ymm0_regnum
+= tdep
->num_dword_regs
;
7790 tdep
->eax_regnum
= -1;
7792 mm0_regnum
= ymm0_regnum
;
7793 if (tdep
->num_ymm_regs
)
7795 /* Support YMM pseudo-register if it is available. */
7796 tdep
->ymm0_regnum
= ymm0_regnum
;
7797 mm0_regnum
+= tdep
->num_ymm_regs
;
7800 tdep
->ymm0_regnum
= -1;
7802 if (tdep
->num_mmx_regs
!= 0)
7804 /* Support MMX pseudo-register if MMX hasn't been disabled. */
7805 tdep
->mm0_regnum
= mm0_regnum
;
7808 tdep
->mm0_regnum
= -1;
7810 /* Hook in the legacy prologue-based unwinders last (fallback). */
7811 frame_unwind_append_unwinder (gdbarch
, &i386_stack_tramp_frame_unwind
);
7812 frame_unwind_append_unwinder (gdbarch
, &i386_sigtramp_frame_unwind
);
7813 frame_unwind_append_unwinder (gdbarch
, &i386_frame_unwind
);
7815 /* If we have a register mapping, enable the generic core file
7816 support, unless it has already been enabled. */
7817 if (tdep
->gregset_reg_offset
7818 && !gdbarch_regset_from_core_section_p (gdbarch
))
7819 set_gdbarch_regset_from_core_section (gdbarch
,
7820 i386_regset_from_core_section
);
7822 set_gdbarch_skip_permanent_breakpoint (gdbarch
,
7823 i386_skip_permanent_breakpoint
);
7825 set_gdbarch_fast_tracepoint_valid_at (gdbarch
,
7826 i386_fast_tracepoint_valid_at
);
7831 static enum gdb_osabi
7832 i386_coff_osabi_sniffer (bfd
*abfd
)
7834 if (strcmp (bfd_get_target (abfd
), "coff-go32-exe") == 0
7835 || strcmp (bfd_get_target (abfd
), "coff-go32") == 0)
7836 return GDB_OSABI_GO32
;
7838 return GDB_OSABI_UNKNOWN
;
7842 /* Provide a prototype to silence -Wmissing-prototypes. */
7843 void _initialize_i386_tdep (void);
7846 _initialize_i386_tdep (void)
7848 register_gdbarch_init (bfd_arch_i386
, i386_gdbarch_init
);
7850 /* Add the variable that controls the disassembly flavor. */
7851 add_setshow_enum_cmd ("disassembly-flavor", no_class
, valid_flavors
,
7852 &disassembly_flavor
, _("\
7853 Set the disassembly flavor."), _("\
7854 Show the disassembly flavor."), _("\
7855 The valid values are \"att\" and \"intel\", and the default value is \"att\"."),
7857 NULL
, /* FIXME: i18n: */
7858 &setlist
, &showlist
);
7860 /* Add the variable that controls the convention for returning
7862 add_setshow_enum_cmd ("struct-convention", no_class
, valid_conventions
,
7863 &struct_convention
, _("\
7864 Set the convention for returning small structs."), _("\
7865 Show the convention for returning small structs."), _("\
7866 Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\
7869 NULL
, /* FIXME: i18n: */
7870 &setlist
, &showlist
);
7872 gdbarch_register_osabi_sniffer (bfd_arch_i386
, bfd_target_coff_flavour
,
7873 i386_coff_osabi_sniffer
);
7875 gdbarch_register_osabi (bfd_arch_i386
, 0, GDB_OSABI_SVR4
,
7876 i386_svr4_init_abi
);
7877 gdbarch_register_osabi (bfd_arch_i386
, 0, GDB_OSABI_GO32
,
7878 i386_go32_init_abi
);
7880 /* Initialize the i386-specific register groups. */
7881 i386_init_reggroups ();
7883 /* Initialize the standard target descriptions. */
7884 initialize_tdesc_i386 ();
7885 initialize_tdesc_i386_mmx ();
7886 initialize_tdesc_i386_avx ();
7888 /* Tell remote stub that we support XML target description. */
7889 register_remote_support_xml ("i386");