1 /* Intel 386 target-dependent stuff.
3 Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009,
5 2010, 2011 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "opcode/i386.h"
24 #include "arch-utils.h"
26 #include "dummy-frame.h"
27 #include "dwarf2-frame.h"
30 #include "frame-base.h"
31 #include "frame-unwind.h"
39 #include "reggroups.h"
48 #include "exceptions.h"
49 #include "gdb_assert.h"
50 #include "gdb_string.h"
52 #include "i386-tdep.h"
53 #include "i387-tdep.h"
54 #include "i386-xstate.h"
59 #include "features/i386/i386.c"
60 #include "features/i386/i386-avx.c"
61 #include "features/i386/i386-mmx.c"
65 static const char *i386_register_names
[] =
67 "eax", "ecx", "edx", "ebx",
68 "esp", "ebp", "esi", "edi",
69 "eip", "eflags", "cs", "ss",
70 "ds", "es", "fs", "gs",
71 "st0", "st1", "st2", "st3",
72 "st4", "st5", "st6", "st7",
73 "fctrl", "fstat", "ftag", "fiseg",
74 "fioff", "foseg", "fooff", "fop",
75 "xmm0", "xmm1", "xmm2", "xmm3",
76 "xmm4", "xmm5", "xmm6", "xmm7",
80 static const char *i386_ymm_names
[] =
82 "ymm0", "ymm1", "ymm2", "ymm3",
83 "ymm4", "ymm5", "ymm6", "ymm7",
86 static const char *i386_ymmh_names
[] =
88 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
89 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
92 /* Register names for MMX pseudo-registers. */
94 static const char *i386_mmx_names
[] =
96 "mm0", "mm1", "mm2", "mm3",
97 "mm4", "mm5", "mm6", "mm7"
100 /* Register names for byte pseudo-registers. */
102 static const char *i386_byte_names
[] =
104 "al", "cl", "dl", "bl",
105 "ah", "ch", "dh", "bh"
108 /* Register names for word pseudo-registers. */
110 static const char *i386_word_names
[] =
112 "ax", "cx", "dx", "bx",
119 i386_mmx_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
121 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
122 int mm0_regnum
= tdep
->mm0_regnum
;
127 regnum
-= mm0_regnum
;
128 return regnum
>= 0 && regnum
< tdep
->num_mmx_regs
;
134 i386_byte_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
136 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
138 regnum
-= tdep
->al_regnum
;
139 return regnum
>= 0 && regnum
< tdep
->num_byte_regs
;
145 i386_word_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
147 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
149 regnum
-= tdep
->ax_regnum
;
150 return regnum
>= 0 && regnum
< tdep
->num_word_regs
;
153 /* Dword register? */
156 i386_dword_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
158 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
159 int eax_regnum
= tdep
->eax_regnum
;
164 regnum
-= eax_regnum
;
165 return regnum
>= 0 && regnum
< tdep
->num_dword_regs
;
169 i386_ymmh_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
171 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
172 int ymm0h_regnum
= tdep
->ymm0h_regnum
;
174 if (ymm0h_regnum
< 0)
177 regnum
-= ymm0h_regnum
;
178 return regnum
>= 0 && regnum
< tdep
->num_ymm_regs
;
184 i386_ymm_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
186 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
187 int ymm0_regnum
= tdep
->ymm0_regnum
;
192 regnum
-= ymm0_regnum
;
193 return regnum
>= 0 && regnum
< tdep
->num_ymm_regs
;
199 i386_xmm_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
201 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
202 int num_xmm_regs
= I387_NUM_XMM_REGS (tdep
);
204 if (num_xmm_regs
== 0)
207 regnum
-= I387_XMM0_REGNUM (tdep
);
208 return regnum
>= 0 && regnum
< num_xmm_regs
;
212 i386_mxcsr_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
214 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
216 if (I387_NUM_XMM_REGS (tdep
) == 0)
219 return (regnum
== I387_MXCSR_REGNUM (tdep
));
225 i386_fp_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
227 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
229 if (I387_ST0_REGNUM (tdep
) < 0)
232 return (I387_ST0_REGNUM (tdep
) <= regnum
233 && regnum
< I387_FCTRL_REGNUM (tdep
));
237 i386_fpc_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
239 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
241 if (I387_ST0_REGNUM (tdep
) < 0)
244 return (I387_FCTRL_REGNUM (tdep
) <= regnum
245 && regnum
< I387_XMM0_REGNUM (tdep
));
248 /* Return the name of register REGNUM, or the empty string if it is
249 an anonymous register. */
252 i386_register_name (struct gdbarch
*gdbarch
, int regnum
)
254 /* Hide the upper YMM registers. */
255 if (i386_ymmh_regnum_p (gdbarch
, regnum
))
258 return tdesc_register_name (gdbarch
, regnum
);
261 /* Return the name of register REGNUM. */
264 i386_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
266 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
267 if (i386_mmx_regnum_p (gdbarch
, regnum
))
268 return i386_mmx_names
[regnum
- I387_MM0_REGNUM (tdep
)];
269 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
270 return i386_ymm_names
[regnum
- tdep
->ymm0_regnum
];
271 else if (i386_byte_regnum_p (gdbarch
, regnum
))
272 return i386_byte_names
[regnum
- tdep
->al_regnum
];
273 else if (i386_word_regnum_p (gdbarch
, regnum
))
274 return i386_word_names
[regnum
- tdep
->ax_regnum
];
276 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
279 /* Convert a dbx register number REG to the appropriate register
280 number used by GDB. */
283 i386_dbx_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
285 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
287 /* This implements what GCC calls the "default" register map
288 (dbx_register_map[]). */
290 if (reg
>= 0 && reg
<= 7)
292 /* General-purpose registers. The debug info calls %ebp
293 register 4, and %esp register 5. */
300 else if (reg
>= 12 && reg
<= 19)
302 /* Floating-point registers. */
303 return reg
- 12 + I387_ST0_REGNUM (tdep
);
305 else if (reg
>= 21 && reg
<= 28)
308 int ymm0_regnum
= tdep
->ymm0_regnum
;
311 && i386_xmm_regnum_p (gdbarch
, reg
))
312 return reg
- 21 + ymm0_regnum
;
314 return reg
- 21 + I387_XMM0_REGNUM (tdep
);
316 else if (reg
>= 29 && reg
<= 36)
319 return reg
- 29 + I387_MM0_REGNUM (tdep
);
322 /* This will hopefully provoke a warning. */
323 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
326 /* Convert SVR4 register number REG to the appropriate register number
330 i386_svr4_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
332 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
334 /* This implements the GCC register map that tries to be compatible
335 with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */
337 /* The SVR4 register numbering includes %eip and %eflags, and
338 numbers the floating point registers differently. */
339 if (reg
>= 0 && reg
<= 9)
341 /* General-purpose registers. */
344 else if (reg
>= 11 && reg
<= 18)
346 /* Floating-point registers. */
347 return reg
- 11 + I387_ST0_REGNUM (tdep
);
349 else if (reg
>= 21 && reg
<= 36)
351 /* The SSE and MMX registers have the same numbers as with dbx. */
352 return i386_dbx_reg_to_regnum (gdbarch
, reg
);
357 case 37: return I387_FCTRL_REGNUM (tdep
);
358 case 38: return I387_FSTAT_REGNUM (tdep
);
359 case 39: return I387_MXCSR_REGNUM (tdep
);
360 case 40: return I386_ES_REGNUM
;
361 case 41: return I386_CS_REGNUM
;
362 case 42: return I386_SS_REGNUM
;
363 case 43: return I386_DS_REGNUM
;
364 case 44: return I386_FS_REGNUM
;
365 case 45: return I386_GS_REGNUM
;
368 /* This will hopefully provoke a warning. */
369 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
374 /* This is the variable that is set with "set disassembly-flavor", and
375 its legitimate values. */
376 static const char att_flavor
[] = "att";
377 static const char intel_flavor
[] = "intel";
378 static const char *valid_flavors
[] =
384 static const char *disassembly_flavor
= att_flavor
;
387 /* Use the program counter to determine the contents and size of a
388 breakpoint instruction. Return a pointer to a string of bytes that
389 encode a breakpoint instruction, store the length of the string in
390 *LEN and optionally adjust *PC to point to the correct memory
391 location for inserting the breakpoint.
393 On the i386 we have a single breakpoint that fits in a single byte
394 and can be inserted anywhere.
396 This function is 64-bit safe. */
398 static const gdb_byte
*
399 i386_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pc
, int *len
)
401 static gdb_byte break_insn
[] = { 0xcc }; /* int 3 */
403 *len
= sizeof (break_insn
);
407 /* Displaced instruction handling. */
409 /* Skip the legacy instruction prefixes in INSN.
410 Not all prefixes are valid for any particular insn
411 but we needn't care, the insn will fault if it's invalid.
412 The result is a pointer to the first opcode byte,
413 or NULL if we run off the end of the buffer. */
416 i386_skip_prefixes (gdb_byte
*insn
, size_t max_len
)
418 gdb_byte
*end
= insn
+ max_len
;
424 case DATA_PREFIX_OPCODE
:
425 case ADDR_PREFIX_OPCODE
:
426 case CS_PREFIX_OPCODE
:
427 case DS_PREFIX_OPCODE
:
428 case ES_PREFIX_OPCODE
:
429 case FS_PREFIX_OPCODE
:
430 case GS_PREFIX_OPCODE
:
431 case SS_PREFIX_OPCODE
:
432 case LOCK_PREFIX_OPCODE
:
433 case REPE_PREFIX_OPCODE
:
434 case REPNE_PREFIX_OPCODE
:
446 i386_absolute_jmp_p (const gdb_byte
*insn
)
448 /* jmp far (absolute address in operand). */
454 /* jump near, absolute indirect (/4). */
455 if ((insn
[1] & 0x38) == 0x20)
458 /* jump far, absolute indirect (/5). */
459 if ((insn
[1] & 0x38) == 0x28)
467 i386_absolute_call_p (const gdb_byte
*insn
)
469 /* call far, absolute. */
475 /* Call near, absolute indirect (/2). */
476 if ((insn
[1] & 0x38) == 0x10)
479 /* Call far, absolute indirect (/3). */
480 if ((insn
[1] & 0x38) == 0x18)
488 i386_ret_p (const gdb_byte
*insn
)
492 case 0xc2: /* ret near, pop N bytes. */
493 case 0xc3: /* ret near */
494 case 0xca: /* ret far, pop N bytes. */
495 case 0xcb: /* ret far */
496 case 0xcf: /* iret */
505 i386_call_p (const gdb_byte
*insn
)
507 if (i386_absolute_call_p (insn
))
510 /* call near, relative. */
517 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
518 length in bytes. Otherwise, return zero. */
521 i386_syscall_p (const gdb_byte
*insn
, int *lengthp
)
532 /* Some kernels may run one past a syscall insn, so we have to cope.
533 Otherwise this is just simple_displaced_step_copy_insn. */
535 struct displaced_step_closure
*
536 i386_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
537 CORE_ADDR from
, CORE_ADDR to
,
538 struct regcache
*regs
)
540 size_t len
= gdbarch_max_insn_length (gdbarch
);
541 gdb_byte
*buf
= xmalloc (len
);
543 read_memory (from
, buf
, len
);
545 /* GDB may get control back after the insn after the syscall.
546 Presumably this is a kernel bug.
547 If this is a syscall, make sure there's a nop afterwards. */
552 insn
= i386_skip_prefixes (buf
, len
);
553 if (insn
!= NULL
&& i386_syscall_p (insn
, &syscall_length
))
554 insn
[syscall_length
] = NOP_OPCODE
;
557 write_memory (to
, buf
, len
);
561 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
562 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
563 displaced_step_dump_bytes (gdb_stdlog
, buf
, len
);
566 return (struct displaced_step_closure
*) buf
;
569 /* Fix up the state of registers and memory after having single-stepped
570 a displaced instruction. */
573 i386_displaced_step_fixup (struct gdbarch
*gdbarch
,
574 struct displaced_step_closure
*closure
,
575 CORE_ADDR from
, CORE_ADDR to
,
576 struct regcache
*regs
)
578 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
580 /* The offset we applied to the instruction's address.
581 This could well be negative (when viewed as a signed 32-bit
582 value), but ULONGEST won't reflect that, so take care when
584 ULONGEST insn_offset
= to
- from
;
586 /* Since we use simple_displaced_step_copy_insn, our closure is a
587 copy of the instruction. */
588 gdb_byte
*insn
= (gdb_byte
*) closure
;
589 /* The start of the insn, needed in case we see some prefixes. */
590 gdb_byte
*insn_start
= insn
;
593 fprintf_unfiltered (gdb_stdlog
,
594 "displaced: fixup (%s, %s), "
595 "insn = 0x%02x 0x%02x ...\n",
596 paddress (gdbarch
, from
), paddress (gdbarch
, to
),
599 /* The list of issues to contend with here is taken from
600 resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20.
601 Yay for Free Software! */
603 /* Relocate the %eip, if necessary. */
605 /* The instruction recognizers we use assume any leading prefixes
606 have been skipped. */
608 /* This is the size of the buffer in closure. */
609 size_t max_insn_len
= gdbarch_max_insn_length (gdbarch
);
610 gdb_byte
*opcode
= i386_skip_prefixes (insn
, max_insn_len
);
611 /* If there are too many prefixes, just ignore the insn.
612 It will fault when run. */
617 /* Except in the case of absolute or indirect jump or call
618 instructions, or a return instruction, the new eip is relative to
619 the displaced instruction; make it relative. Well, signal
620 handler returns don't need relocation either, but we use the
621 value of %eip to recognize those; see below. */
622 if (! i386_absolute_jmp_p (insn
)
623 && ! i386_absolute_call_p (insn
)
624 && ! i386_ret_p (insn
))
629 regcache_cooked_read_unsigned (regs
, I386_EIP_REGNUM
, &orig_eip
);
631 /* A signal trampoline system call changes the %eip, resuming
632 execution of the main program after the signal handler has
633 returned. That makes them like 'return' instructions; we
634 shouldn't relocate %eip.
636 But most system calls don't, and we do need to relocate %eip.
638 Our heuristic for distinguishing these cases: if stepping
639 over the system call instruction left control directly after
640 the instruction, the we relocate --- control almost certainly
641 doesn't belong in the displaced copy. Otherwise, we assume
642 the instruction has put control where it belongs, and leave
643 it unrelocated. Goodness help us if there are PC-relative
645 if (i386_syscall_p (insn
, &insn_len
)
646 && orig_eip
!= to
+ (insn
- insn_start
) + insn_len
647 /* GDB can get control back after the insn after the syscall.
648 Presumably this is a kernel bug.
649 i386_displaced_step_copy_insn ensures its a nop,
650 we add one to the length for it. */
651 && orig_eip
!= to
+ (insn
- insn_start
) + insn_len
+ 1)
654 fprintf_unfiltered (gdb_stdlog
,
655 "displaced: syscall changed %%eip; "
660 ULONGEST eip
= (orig_eip
- insn_offset
) & 0xffffffffUL
;
662 /* If we just stepped over a breakpoint insn, we don't backup
663 the pc on purpose; this is to match behaviour without
666 regcache_cooked_write_unsigned (regs
, I386_EIP_REGNUM
, eip
);
669 fprintf_unfiltered (gdb_stdlog
,
671 "relocated %%eip from %s to %s\n",
672 paddress (gdbarch
, orig_eip
),
673 paddress (gdbarch
, eip
));
677 /* If the instruction was PUSHFL, then the TF bit will be set in the
678 pushed value, and should be cleared. We'll leave this for later,
679 since GDB already messes up the TF flag when stepping over a
682 /* If the instruction was a call, the return address now atop the
683 stack is the address following the copied instruction. We need
684 to make it the address following the original instruction. */
685 if (i386_call_p (insn
))
689 const ULONGEST retaddr_len
= 4;
691 regcache_cooked_read_unsigned (regs
, I386_ESP_REGNUM
, &esp
);
692 retaddr
= read_memory_unsigned_integer (esp
, retaddr_len
, byte_order
);
693 retaddr
= (retaddr
- insn_offset
) & 0xffffffffUL
;
694 write_memory_unsigned_integer (esp
, retaddr_len
, byte_order
, retaddr
);
697 fprintf_unfiltered (gdb_stdlog
,
698 "displaced: relocated return addr at %s to %s\n",
699 paddress (gdbarch
, esp
),
700 paddress (gdbarch
, retaddr
));
705 append_insns (CORE_ADDR
*to
, ULONGEST len
, const gdb_byte
*buf
)
707 target_write_memory (*to
, buf
, len
);
712 i386_relocate_instruction (struct gdbarch
*gdbarch
,
713 CORE_ADDR
*to
, CORE_ADDR oldloc
)
715 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
716 gdb_byte buf
[I386_MAX_INSN_LEN
];
717 int offset
= 0, rel32
, newrel
;
719 gdb_byte
*insn
= buf
;
721 read_memory (oldloc
, buf
, I386_MAX_INSN_LEN
);
723 insn_length
= gdb_buffered_insn_length (gdbarch
, insn
,
724 I386_MAX_INSN_LEN
, oldloc
);
726 /* Get past the prefixes. */
727 insn
= i386_skip_prefixes (insn
, I386_MAX_INSN_LEN
);
729 /* Adjust calls with 32-bit relative addresses as push/jump, with
730 the address pushed being the location where the original call in
731 the user program would return to. */
734 gdb_byte push_buf
[16];
735 unsigned int ret_addr
;
737 /* Where "ret" in the original code will return to. */
738 ret_addr
= oldloc
+ insn_length
;
739 push_buf
[0] = 0x68; /* pushq $... */
740 memcpy (&push_buf
[1], &ret_addr
, 4);
742 append_insns (to
, 5, push_buf
);
744 /* Convert the relative call to a relative jump. */
747 /* Adjust the destination offset. */
748 rel32
= extract_signed_integer (insn
+ 1, 4, byte_order
);
749 newrel
= (oldloc
- *to
) + rel32
;
750 store_signed_integer (insn
+ 1, 4, byte_order
, newrel
);
753 fprintf_unfiltered (gdb_stdlog
,
754 "Adjusted insn rel32=%s at %s to"
756 hex_string (rel32
), paddress (gdbarch
, oldloc
),
757 hex_string (newrel
), paddress (gdbarch
, *to
));
759 /* Write the adjusted jump into its displaced location. */
760 append_insns (to
, 5, insn
);
764 /* Adjust jumps with 32-bit relative addresses. Calls are already
768 /* Adjust conditional jumps. */
769 else if (insn
[0] == 0x0f && (insn
[1] & 0xf0) == 0x80)
774 rel32
= extract_signed_integer (insn
+ offset
, 4, byte_order
);
775 newrel
= (oldloc
- *to
) + rel32
;
776 store_signed_integer (insn
+ offset
, 4, byte_order
, newrel
);
778 fprintf_unfiltered (gdb_stdlog
,
779 "Adjusted insn rel32=%s at %s to"
781 hex_string (rel32
), paddress (gdbarch
, oldloc
),
782 hex_string (newrel
), paddress (gdbarch
, *to
));
785 /* Write the adjusted instructions into their displaced
787 append_insns (to
, insn_length
, buf
);
791 #ifdef I386_REGNO_TO_SYMMETRY
792 #error "The Sequent Symmetry is no longer supported."
795 /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi
796 and %esp "belong" to the calling function. Therefore these
797 registers should be saved if they're going to be modified. */
799 /* The maximum number of saved registers. This should include all
800 registers mentioned above, and %eip. */
801 #define I386_NUM_SAVED_REGS I386_NUM_GREGS
803 struct i386_frame_cache
811 /* Saved registers. */
812 CORE_ADDR saved_regs
[I386_NUM_SAVED_REGS
];
817 /* Stack space reserved for local variables. */
821 /* Allocate and initialize a frame cache. */
823 static struct i386_frame_cache
*
824 i386_alloc_frame_cache (void)
826 struct i386_frame_cache
*cache
;
829 cache
= FRAME_OBSTACK_ZALLOC (struct i386_frame_cache
);
834 cache
->sp_offset
= -4;
837 /* Saved registers. We initialize these to -1 since zero is a valid
838 offset (that's where %ebp is supposed to be stored). */
839 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
840 cache
->saved_regs
[i
] = -1;
842 cache
->saved_sp_reg
= -1;
843 cache
->pc_in_eax
= 0;
845 /* Frameless until proven otherwise. */
851 /* If the instruction at PC is a jump, return the address of its
852 target. Otherwise, return PC. */
855 i386_follow_jump (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
857 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
862 if (target_read_memory (pc
, &op
, 1))
868 op
= read_memory_unsigned_integer (pc
+ 1, 1, byte_order
);
874 /* Relative jump: if data16 == 0, disp32, else disp16. */
877 delta
= read_memory_integer (pc
+ 2, 2, byte_order
);
879 /* Include the size of the jmp instruction (including the
885 delta
= read_memory_integer (pc
+ 1, 4, byte_order
);
887 /* Include the size of the jmp instruction. */
892 /* Relative jump, disp8 (ignore data16). */
893 delta
= read_memory_integer (pc
+ data16
+ 1, 1, byte_order
);
902 /* Check whether PC points at a prologue for a function returning a
903 structure or union. If so, it updates CACHE and returns the
904 address of the first instruction after the code sequence that
905 removes the "hidden" argument from the stack or CURRENT_PC,
906 whichever is smaller. Otherwise, return PC. */
909 i386_analyze_struct_return (CORE_ADDR pc
, CORE_ADDR current_pc
,
910 struct i386_frame_cache
*cache
)
912 /* Functions that return a structure or union start with:
915 xchgl %eax, (%esp) 0x87 0x04 0x24
916 or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00
918 (the System V compiler puts out the second `xchg' instruction,
919 and the assembler doesn't try to optimize it, so the 'sib' form
920 gets generated). This sequence is used to get the address of the
921 return buffer for a function that returns a structure. */
922 static gdb_byte proto1
[3] = { 0x87, 0x04, 0x24 };
923 static gdb_byte proto2
[4] = { 0x87, 0x44, 0x24, 0x00 };
927 if (current_pc
<= pc
)
930 if (target_read_memory (pc
, &op
, 1))
933 if (op
!= 0x58) /* popl %eax */
936 if (target_read_memory (pc
+ 1, buf
, 4))
939 if (memcmp (buf
, proto1
, 3) != 0 && memcmp (buf
, proto2
, 4) != 0)
942 if (current_pc
== pc
)
944 cache
->sp_offset
+= 4;
948 if (current_pc
== pc
+ 1)
950 cache
->pc_in_eax
= 1;
954 if (buf
[1] == proto1
[1])
961 i386_skip_probe (CORE_ADDR pc
)
963 /* A function may start with
977 if (target_read_memory (pc
, &op
, 1))
980 if (op
== 0x68 || op
== 0x6a)
984 /* Skip past the `pushl' instruction; it has either a one-byte or a
985 four-byte operand, depending on the opcode. */
991 /* Read the following 8 bytes, which should be `call _probe' (6
992 bytes) followed by `addl $4,%esp' (2 bytes). */
993 read_memory (pc
+ delta
, buf
, sizeof (buf
));
994 if (buf
[0] == 0xe8 && buf
[6] == 0xc4 && buf
[7] == 0x4)
995 pc
+= delta
+ sizeof (buf
);
1001 /* GCC 4.1 and later, can put code in the prologue to realign the
1002 stack pointer. Check whether PC points to such code, and update
1003 CACHE accordingly. Return the first instruction after the code
1004 sequence or CURRENT_PC, whichever is smaller. If we don't
1005 recognize the code, return PC. */
1008 i386_analyze_stack_align (CORE_ADDR pc
, CORE_ADDR current_pc
,
1009 struct i386_frame_cache
*cache
)
1011 /* There are 2 code sequences to re-align stack before the frame
1014 1. Use a caller-saved saved register:
1020 2. Use a callee-saved saved register:
1027 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
1029 0x83 0xe4 0xf0 andl $-16, %esp
1030 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
1035 int offset
, offset_and
;
1036 static int regnums
[8] = {
1037 I386_EAX_REGNUM
, /* %eax */
1038 I386_ECX_REGNUM
, /* %ecx */
1039 I386_EDX_REGNUM
, /* %edx */
1040 I386_EBX_REGNUM
, /* %ebx */
1041 I386_ESP_REGNUM
, /* %esp */
1042 I386_EBP_REGNUM
, /* %ebp */
1043 I386_ESI_REGNUM
, /* %esi */
1044 I386_EDI_REGNUM
/* %edi */
1047 if (target_read_memory (pc
, buf
, sizeof buf
))
1050 /* Check caller-saved saved register. The first instruction has
1051 to be "leal 4(%esp), %reg". */
1052 if (buf
[0] == 0x8d && buf
[2] == 0x24 && buf
[3] == 0x4)
1054 /* MOD must be binary 10 and R/M must be binary 100. */
1055 if ((buf
[1] & 0xc7) != 0x44)
1058 /* REG has register number. */
1059 reg
= (buf
[1] >> 3) & 7;
1064 /* Check callee-saved saved register. The first instruction
1065 has to be "pushl %reg". */
1066 if ((buf
[0] & 0xf8) != 0x50)
1072 /* The next instruction has to be "leal 8(%esp), %reg". */
1073 if (buf
[1] != 0x8d || buf
[3] != 0x24 || buf
[4] != 0x8)
1076 /* MOD must be binary 10 and R/M must be binary 100. */
1077 if ((buf
[2] & 0xc7) != 0x44)
1080 /* REG has register number. Registers in pushl and leal have to
1082 if (reg
!= ((buf
[2] >> 3) & 7))
1088 /* Rigister can't be %esp nor %ebp. */
1089 if (reg
== 4 || reg
== 5)
1092 /* The next instruction has to be "andl $-XXX, %esp". */
1093 if (buf
[offset
+ 1] != 0xe4
1094 || (buf
[offset
] != 0x81 && buf
[offset
] != 0x83))
1097 offset_and
= offset
;
1098 offset
+= buf
[offset
] == 0x81 ? 6 : 3;
1100 /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is
1101 0xfc. REG must be binary 110 and MOD must be binary 01. */
1102 if (buf
[offset
] != 0xff
1103 || buf
[offset
+ 2] != 0xfc
1104 || (buf
[offset
+ 1] & 0xf8) != 0x70)
1107 /* R/M has register. Registers in leal and pushl have to be the
1109 if (reg
!= (buf
[offset
+ 1] & 7))
1112 if (current_pc
> pc
+ offset_and
)
1113 cache
->saved_sp_reg
= regnums
[reg
];
1115 return min (pc
+ offset
+ 3, current_pc
);
1118 /* Maximum instruction length we need to handle. */
1119 #define I386_MAX_MATCHED_INSN_LEN 6
1121 /* Instruction description. */
1125 gdb_byte insn
[I386_MAX_MATCHED_INSN_LEN
];
1126 gdb_byte mask
[I386_MAX_MATCHED_INSN_LEN
];
1129 /* Return whether instruction at PC matches PATTERN. */
1132 i386_match_pattern (CORE_ADDR pc
, struct i386_insn pattern
)
1136 if (target_read_memory (pc
, &op
, 1))
1139 if ((op
& pattern
.mask
[0]) == pattern
.insn
[0])
1141 gdb_byte buf
[I386_MAX_MATCHED_INSN_LEN
- 1];
1142 int insn_matched
= 1;
1145 gdb_assert (pattern
.len
> 1);
1146 gdb_assert (pattern
.len
<= I386_MAX_MATCHED_INSN_LEN
);
1148 if (target_read_memory (pc
+ 1, buf
, pattern
.len
- 1))
1151 for (i
= 1; i
< pattern
.len
; i
++)
1153 if ((buf
[i
- 1] & pattern
.mask
[i
]) != pattern
.insn
[i
])
1156 return insn_matched
;
1161 /* Search for the instruction at PC in the list INSN_PATTERNS. Return
1162 the first instruction description that matches. Otherwise, return
1165 static struct i386_insn
*
1166 i386_match_insn (CORE_ADDR pc
, struct i386_insn
*insn_patterns
)
1168 struct i386_insn
*pattern
;
1170 for (pattern
= insn_patterns
; pattern
->len
> 0; pattern
++)
1172 if (i386_match_pattern (pc
, *pattern
))
1179 /* Return whether PC points inside a sequence of instructions that
1180 matches INSN_PATTERNS. */
1183 i386_match_insn_block (CORE_ADDR pc
, struct i386_insn
*insn_patterns
)
1185 CORE_ADDR current_pc
;
1188 struct i386_insn
*insn
;
1190 insn
= i386_match_insn (pc
, insn_patterns
);
1194 current_pc
= pc
- insn
->len
;
1195 ix
= insn
- insn_patterns
;
1196 for (i
= ix
- 1; i
>= 0; i
--)
1198 if (!i386_match_pattern (current_pc
, insn_patterns
[i
]))
1201 current_pc
-= insn_patterns
[i
].len
;
1204 current_pc
= pc
+ insn
->len
;
1205 for (insn
= insn_patterns
+ ix
+ 1; insn
->len
> 0; insn
++)
1207 if (!i386_match_pattern (current_pc
, *insn
))
1210 current_pc
+= insn
->len
;
1216 /* Some special instructions that might be migrated by GCC into the
1217 part of the prologue that sets up the new stack frame. Because the
1218 stack frame hasn't been setup yet, no registers have been saved
1219 yet, and only the scratch registers %eax, %ecx and %edx can be
1222 struct i386_insn i386_frame_setup_skip_insns
[] =
1224 /* Check for `movb imm8, r' and `movl imm32, r'.
1226 ??? Should we handle 16-bit operand-sizes here? */
1228 /* `movb imm8, %al' and `movb imm8, %ah' */
1229 /* `movb imm8, %cl' and `movb imm8, %ch' */
1230 { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } },
1231 /* `movb imm8, %dl' and `movb imm8, %dh' */
1232 { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } },
1233 /* `movl imm32, %eax' and `movl imm32, %ecx' */
1234 { 5, { 0xb8 }, { 0xfe } },
1235 /* `movl imm32, %edx' */
1236 { 5, { 0xba }, { 0xff } },
1238 /* Check for `mov imm32, r32'. Note that there is an alternative
1239 encoding for `mov m32, %eax'.
1241 ??? Should we handle SIB adressing here?
1242 ??? Should we handle 16-bit operand-sizes here? */
1244 /* `movl m32, %eax' */
1245 { 5, { 0xa1 }, { 0xff } },
1246 /* `movl m32, %eax' and `mov; m32, %ecx' */
1247 { 6, { 0x89, 0x05 }, {0xff, 0xf7 } },
1248 /* `movl m32, %edx' */
1249 { 6, { 0x89, 0x15 }, {0xff, 0xff } },
1251 /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'.
1252 Because of the symmetry, there are actually two ways to encode
1253 these instructions; opcode bytes 0x29 and 0x2b for `subl' and
1254 opcode bytes 0x31 and 0x33 for `xorl'. */
1256 /* `subl %eax, %eax' */
1257 { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } },
1258 /* `subl %ecx, %ecx' */
1259 { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } },
1260 /* `subl %edx, %edx' */
1261 { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } },
1262 /* `xorl %eax, %eax' */
1263 { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } },
1264 /* `xorl %ecx, %ecx' */
1265 { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } },
1266 /* `xorl %edx, %edx' */
1267 { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } },
1272 /* Check whether PC points to a no-op instruction. */
1274 i386_skip_noop (CORE_ADDR pc
)
1279 if (target_read_memory (pc
, &op
, 1))
1285 /* Ignore `nop' instruction. */
1289 if (target_read_memory (pc
, &op
, 1))
1293 /* Ignore no-op instruction `mov %edi, %edi'.
1294 Microsoft system dlls often start with
1295 a `mov %edi,%edi' instruction.
1296 The 5 bytes before the function start are
1297 filled with `nop' instructions.
1298 This pattern can be used for hot-patching:
1299 The `mov %edi, %edi' instruction can be replaced by a
1300 near jump to the location of the 5 `nop' instructions
1301 which can be replaced by a 32-bit jump to anywhere
1302 in the 32-bit address space. */
1304 else if (op
== 0x8b)
1306 if (target_read_memory (pc
+ 1, &op
, 1))
1312 if (target_read_memory (pc
, &op
, 1))
1322 /* Check whether PC points at a code that sets up a new stack frame.
1323 If so, it updates CACHE and returns the address of the first
1324 instruction after the sequence that sets up the frame or LIMIT,
1325 whichever is smaller. If we don't recognize the code, return PC. */
1328 i386_analyze_frame_setup (struct gdbarch
*gdbarch
,
1329 CORE_ADDR pc
, CORE_ADDR limit
,
1330 struct i386_frame_cache
*cache
)
1332 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1333 struct i386_insn
*insn
;
1340 if (target_read_memory (pc
, &op
, 1))
1343 if (op
== 0x55) /* pushl %ebp */
1345 /* Take into account that we've executed the `pushl %ebp' that
1346 starts this instruction sequence. */
1347 cache
->saved_regs
[I386_EBP_REGNUM
] = 0;
1348 cache
->sp_offset
+= 4;
1351 /* If that's all, return now. */
1355 /* Check for some special instructions that might be migrated by
1356 GCC into the prologue and skip them. At this point in the
1357 prologue, code should only touch the scratch registers %eax,
1358 %ecx and %edx, so while the number of posibilities is sheer,
1361 Make sure we only skip these instructions if we later see the
1362 `movl %esp, %ebp' that actually sets up the frame. */
1363 while (pc
+ skip
< limit
)
1365 insn
= i386_match_insn (pc
+ skip
, i386_frame_setup_skip_insns
);
1372 /* If that's all, return now. */
1373 if (limit
<= pc
+ skip
)
1376 if (target_read_memory (pc
+ skip
, &op
, 1))
1379 /* Check for `movl %esp, %ebp' -- can be written in two ways. */
1383 if (read_memory_unsigned_integer (pc
+ skip
+ 1, 1, byte_order
)
1388 if (read_memory_unsigned_integer (pc
+ skip
+ 1, 1, byte_order
)
1396 /* OK, we actually have a frame. We just don't know how large
1397 it is yet. Set its size to zero. We'll adjust it if
1398 necessary. We also now commit to skipping the special
1399 instructions mentioned before. */
1403 /* If that's all, return now. */
1407 /* Check for stack adjustment
1411 NOTE: You can't subtract a 16-bit immediate from a 32-bit
1412 reg, so we don't have to worry about a data16 prefix. */
1413 if (target_read_memory (pc
, &op
, 1))
1417 /* `subl' with 8-bit immediate. */
1418 if (read_memory_unsigned_integer (pc
+ 1, 1, byte_order
) != 0xec)
1419 /* Some instruction starting with 0x83 other than `subl'. */
1422 /* `subl' with signed 8-bit immediate (though it wouldn't
1423 make sense to be negative). */
1424 cache
->locals
= read_memory_integer (pc
+ 2, 1, byte_order
);
1427 else if (op
== 0x81)
1429 /* Maybe it is `subl' with a 32-bit immediate. */
1430 if (read_memory_unsigned_integer (pc
+ 1, 1, byte_order
) != 0xec)
1431 /* Some instruction starting with 0x81 other than `subl'. */
1434 /* It is `subl' with a 32-bit immediate. */
1435 cache
->locals
= read_memory_integer (pc
+ 2, 4, byte_order
);
1440 /* Some instruction other than `subl'. */
1444 else if (op
== 0xc8) /* enter */
1446 cache
->locals
= read_memory_unsigned_integer (pc
+ 1, 2, byte_order
);
1453 /* Check whether PC points at code that saves registers on the stack.
1454 If so, it updates CACHE and returns the address of the first
1455 instruction after the register saves or CURRENT_PC, whichever is
1456 smaller. Otherwise, return PC. */
1459 i386_analyze_register_saves (CORE_ADDR pc
, CORE_ADDR current_pc
,
1460 struct i386_frame_cache
*cache
)
1462 CORE_ADDR offset
= 0;
1466 if (cache
->locals
> 0)
1467 offset
-= cache
->locals
;
1468 for (i
= 0; i
< 8 && pc
< current_pc
; i
++)
1470 if (target_read_memory (pc
, &op
, 1))
1472 if (op
< 0x50 || op
> 0x57)
1476 cache
->saved_regs
[op
- 0x50] = offset
;
1477 cache
->sp_offset
+= 4;
1484 /* Do a full analysis of the prologue at PC and update CACHE
1485 accordingly. Bail out early if CURRENT_PC is reached. Return the
1486 address where the analysis stopped.
1488 We handle these cases:
1490 The startup sequence can be at the start of the function, or the
1491 function can start with a branch to startup code at the end.
1493 %ebp can be set up with either the 'enter' instruction, or "pushl
1494 %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was
1495 once used in the System V compiler).
1497 Local space is allocated just below the saved %ebp by either the
1498 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a
1499 16-bit unsigned argument for space to allocate, and the 'addl'
1500 instruction could have either a signed byte, or 32-bit immediate.
1502 Next, the registers used by this function are pushed. With the
1503 System V compiler they will always be in the order: %edi, %esi,
1504 %ebx (and sometimes a harmless bug causes it to also save but not
1505 restore %eax); however, the code below is willing to see the pushes
1506 in any order, and will handle up to 8 of them.
1508 If the setup sequence is at the end of the function, then the next
1509 instruction will be a branch back to the start. */
1512 i386_analyze_prologue (struct gdbarch
*gdbarch
,
1513 CORE_ADDR pc
, CORE_ADDR current_pc
,
1514 struct i386_frame_cache
*cache
)
1516 pc
= i386_skip_noop (pc
);
1517 pc
= i386_follow_jump (gdbarch
, pc
);
1518 pc
= i386_analyze_struct_return (pc
, current_pc
, cache
);
1519 pc
= i386_skip_probe (pc
);
1520 pc
= i386_analyze_stack_align (pc
, current_pc
, cache
);
1521 pc
= i386_analyze_frame_setup (gdbarch
, pc
, current_pc
, cache
);
1522 return i386_analyze_register_saves (pc
, current_pc
, cache
);
1525 /* Return PC of first real instruction. */
1528 i386_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
1530 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1532 static gdb_byte pic_pat
[6] =
1534 0xe8, 0, 0, 0, 0, /* call 0x0 */
1535 0x5b, /* popl %ebx */
1537 struct i386_frame_cache cache
;
1543 pc
= i386_analyze_prologue (gdbarch
, start_pc
, 0xffffffff, &cache
);
1544 if (cache
.locals
< 0)
1547 /* Found valid frame setup. */
1549 /* The native cc on SVR4 in -K PIC mode inserts the following code
1550 to get the address of the global offset table (GOT) into register
1555 movl %ebx,x(%ebp) (optional)
1558 This code is with the rest of the prologue (at the end of the
1559 function), so we have to skip it to get to the first real
1560 instruction at the start of the function. */
1562 for (i
= 0; i
< 6; i
++)
1564 if (target_read_memory (pc
+ i
, &op
, 1))
1567 if (pic_pat
[i
] != op
)
1574 if (target_read_memory (pc
+ delta
, &op
, 1))
1577 if (op
== 0x89) /* movl %ebx, x(%ebp) */
1579 op
= read_memory_unsigned_integer (pc
+ delta
+ 1, 1, byte_order
);
1581 if (op
== 0x5d) /* One byte offset from %ebp. */
1583 else if (op
== 0x9d) /* Four byte offset from %ebp. */
1585 else /* Unexpected instruction. */
1588 if (target_read_memory (pc
+ delta
, &op
, 1))
1593 if (delta
> 0 && op
== 0x81
1594 && read_memory_unsigned_integer (pc
+ delta
+ 1, 1, byte_order
)
1601 /* If the function starts with a branch (to startup code at the end)
1602 the last instruction should bring us back to the first
1603 instruction of the real code. */
1604 if (i386_follow_jump (gdbarch
, start_pc
) != start_pc
)
1605 pc
= i386_follow_jump (gdbarch
, pc
);
1610 /* Check that the code pointed to by PC corresponds to a call to
1611 __main, skip it if so. Return PC otherwise. */
1614 i386_skip_main_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1616 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1619 if (target_read_memory (pc
, &op
, 1))
1625 if (target_read_memory (pc
+ 1, buf
, sizeof buf
) == 0)
1627 /* Make sure address is computed correctly as a 32bit
1628 integer even if CORE_ADDR is 64 bit wide. */
1629 struct minimal_symbol
*s
;
1630 CORE_ADDR call_dest
;
1632 call_dest
= pc
+ 5 + extract_signed_integer (buf
, 4, byte_order
);
1633 call_dest
= call_dest
& 0xffffffffU
;
1634 s
= lookup_minimal_symbol_by_pc (call_dest
);
1636 && SYMBOL_LINKAGE_NAME (s
) != NULL
1637 && strcmp (SYMBOL_LINKAGE_NAME (s
), "__main") == 0)
1645 /* This function is 64-bit safe. */
1648 i386_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1652 frame_unwind_register (next_frame
, gdbarch_pc_regnum (gdbarch
), buf
);
1653 return extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
1657 /* Normal frames. */
1660 i386_frame_cache_1 (struct frame_info
*this_frame
,
1661 struct i386_frame_cache
*cache
)
1663 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1664 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1668 cache
->pc
= get_frame_func (this_frame
);
1670 /* In principle, for normal frames, %ebp holds the frame pointer,
1671 which holds the base address for the current stack frame.
1672 However, for functions that don't need it, the frame pointer is
1673 optional. For these "frameless" functions the frame pointer is
1674 actually the frame pointer of the calling frame. Signal
1675 trampolines are just a special case of a "frameless" function.
1676 They (usually) share their frame pointer with the frame that was
1677 in progress when the signal occurred. */
1679 get_frame_register (this_frame
, I386_EBP_REGNUM
, buf
);
1680 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
);
1681 if (cache
->base
== 0)
1684 /* For normal frames, %eip is stored at 4(%ebp). */
1685 cache
->saved_regs
[I386_EIP_REGNUM
] = 4;
1688 i386_analyze_prologue (gdbarch
, cache
->pc
, get_frame_pc (this_frame
),
1691 if (cache
->locals
< 0)
1693 /* We didn't find a valid frame, which means that CACHE->base
1694 currently holds the frame pointer for our calling frame. If
1695 we're at the start of a function, or somewhere half-way its
1696 prologue, the function's frame probably hasn't been fully
1697 setup yet. Try to reconstruct the base address for the stack
1698 frame by looking at the stack pointer. For truly "frameless"
1699 functions this might work too. */
1701 if (cache
->saved_sp_reg
!= -1)
1703 /* Saved stack pointer has been saved. */
1704 get_frame_register (this_frame
, cache
->saved_sp_reg
, buf
);
1705 cache
->saved_sp
= extract_unsigned_integer (buf
, 4, byte_order
);
1707 /* We're halfway aligning the stack. */
1708 cache
->base
= ((cache
->saved_sp
- 4) & 0xfffffff0) - 4;
1709 cache
->saved_regs
[I386_EIP_REGNUM
] = cache
->saved_sp
- 4;
1711 /* This will be added back below. */
1712 cache
->saved_regs
[I386_EIP_REGNUM
] -= cache
->base
;
1714 else if (cache
->pc
!= 0
1715 || target_read_memory (get_frame_pc (this_frame
), buf
, 1))
1717 /* We're in a known function, but did not find a frame
1718 setup. Assume that the function does not use %ebp.
1719 Alternatively, we may have jumped to an invalid
1720 address; in that case there is definitely no new
1722 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
1723 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
)
1727 /* We're in an unknown function. We could not find the start
1728 of the function to analyze the prologue; our best option is
1729 to assume a typical frame layout with the caller's %ebp
1731 cache
->saved_regs
[I386_EBP_REGNUM
] = 0;
1734 if (cache
->saved_sp_reg
!= -1)
1736 /* Saved stack pointer has been saved (but the SAVED_SP_REG
1737 register may be unavailable). */
1738 if (cache
->saved_sp
== 0
1739 && frame_register_read (this_frame
, cache
->saved_sp_reg
, buf
))
1740 cache
->saved_sp
= extract_unsigned_integer (buf
, 4, byte_order
);
1742 /* Now that we have the base address for the stack frame we can
1743 calculate the value of %esp in the calling frame. */
1744 else if (cache
->saved_sp
== 0)
1745 cache
->saved_sp
= cache
->base
+ 8;
1747 /* Adjust all the saved registers such that they contain addresses
1748 instead of offsets. */
1749 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
1750 if (cache
->saved_regs
[i
] != -1)
1751 cache
->saved_regs
[i
] += cache
->base
;
1756 static struct i386_frame_cache
*
1757 i386_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1759 volatile struct gdb_exception ex
;
1760 struct i386_frame_cache
*cache
;
1765 cache
= i386_alloc_frame_cache ();
1766 *this_cache
= cache
;
1768 TRY_CATCH (ex
, RETURN_MASK_ERROR
)
1770 i386_frame_cache_1 (this_frame
, cache
);
1772 if (ex
.reason
< 0 && ex
.error
!= NOT_AVAILABLE_ERROR
)
1773 throw_exception (ex
);
1779 i386_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
1780 struct frame_id
*this_id
)
1782 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1784 /* This marks the outermost frame. */
1785 if (cache
->base
== 0)
1788 /* See the end of i386_push_dummy_call. */
1789 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
1792 static enum unwind_stop_reason
1793 i386_frame_unwind_stop_reason (struct frame_info
*this_frame
,
1796 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1799 return UNWIND_UNAVAILABLE
;
1801 /* This marks the outermost frame. */
1802 if (cache
->base
== 0)
1803 return UNWIND_OUTERMOST
;
1805 return UNWIND_NO_REASON
;
1808 static struct value
*
1809 i386_frame_prev_register (struct frame_info
*this_frame
, void **this_cache
,
1812 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1814 gdb_assert (regnum
>= 0);
1816 /* The System V ABI says that:
1818 "The flags register contains the system flags, such as the
1819 direction flag and the carry flag. The direction flag must be
1820 set to the forward (that is, zero) direction before entry and
1821 upon exit from a function. Other user flags have no specified
1822 role in the standard calling sequence and are not preserved."
1824 To guarantee the "upon exit" part of that statement we fake a
1825 saved flags register that has its direction flag cleared.
1827 Note that GCC doesn't seem to rely on the fact that the direction
1828 flag is cleared after a function return; it always explicitly
1829 clears the flag before operations where it matters.
1831 FIXME: kettenis/20030316: I'm not quite sure whether this is the
1832 right thing to do. The way we fake the flags register here makes
1833 it impossible to change it. */
1835 if (regnum
== I386_EFLAGS_REGNUM
)
1839 val
= get_frame_register_unsigned (this_frame
, regnum
);
1841 return frame_unwind_got_constant (this_frame
, regnum
, val
);
1844 if (regnum
== I386_EIP_REGNUM
&& cache
->pc_in_eax
)
1845 return frame_unwind_got_register (this_frame
, regnum
, I386_EAX_REGNUM
);
1847 if (regnum
== I386_ESP_REGNUM
1848 && (cache
->saved_sp
!= 0 || cache
->saved_sp_reg
!= -1))
1850 /* If the SP has been saved, but we don't know where, then this
1851 means that SAVED_SP_REG register was found unavailable back
1852 when we built the cache. */
1853 if (cache
->saved_sp
== 0)
1854 return frame_unwind_got_register (this_frame
, regnum
,
1855 cache
->saved_sp_reg
);
1857 return frame_unwind_got_constant (this_frame
, regnum
,
1861 if (regnum
< I386_NUM_SAVED_REGS
&& cache
->saved_regs
[regnum
] != -1)
1862 return frame_unwind_got_memory (this_frame
, regnum
,
1863 cache
->saved_regs
[regnum
]);
1865 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
1868 static const struct frame_unwind i386_frame_unwind
=
1871 i386_frame_unwind_stop_reason
,
1873 i386_frame_prev_register
,
1875 default_frame_sniffer
1878 /* Normal frames, but in a function epilogue. */
1880 /* The epilogue is defined here as the 'ret' instruction, which will
1881 follow any instruction such as 'leave' or 'pop %ebp' that destroys
1882 the function's stack frame. */
1885 i386_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1889 if (target_read_memory (pc
, &insn
, 1))
1890 return 0; /* Can't read memory at pc. */
1892 if (insn
!= 0xc3) /* 'ret' instruction. */
1899 i386_epilogue_frame_sniffer (const struct frame_unwind
*self
,
1900 struct frame_info
*this_frame
,
1901 void **this_prologue_cache
)
1903 if (frame_relative_level (this_frame
) == 0)
1904 return i386_in_function_epilogue_p (get_frame_arch (this_frame
),
1905 get_frame_pc (this_frame
));
1910 static struct i386_frame_cache
*
1911 i386_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1913 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1914 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1915 volatile struct gdb_exception ex
;
1916 struct i386_frame_cache
*cache
;
1922 cache
= i386_alloc_frame_cache ();
1923 *this_cache
= cache
;
1925 TRY_CATCH (ex
, RETURN_MASK_ERROR
)
1927 /* Cache base will be %esp plus cache->sp_offset (-4). */
1928 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
1929 cache
->base
= extract_unsigned_integer (buf
, 4,
1930 byte_order
) + cache
->sp_offset
;
1932 /* Cache pc will be the frame func. */
1933 cache
->pc
= get_frame_pc (this_frame
);
1935 /* The saved %esp will be at cache->base plus 8. */
1936 cache
->saved_sp
= cache
->base
+ 8;
1938 /* The saved %eip will be at cache->base plus 4. */
1939 cache
->saved_regs
[I386_EIP_REGNUM
] = cache
->base
+ 4;
1943 if (ex
.reason
< 0 && ex
.error
!= NOT_AVAILABLE_ERROR
)
1944 throw_exception (ex
);
1949 static enum unwind_stop_reason
1950 i386_epilogue_frame_unwind_stop_reason (struct frame_info
*this_frame
,
1953 struct i386_frame_cache
*cache
1954 = i386_epilogue_frame_cache (this_frame
, this_cache
);
1957 return UNWIND_UNAVAILABLE
;
1959 return UNWIND_NO_REASON
;
1963 i386_epilogue_frame_this_id (struct frame_info
*this_frame
,
1965 struct frame_id
*this_id
)
1967 struct i386_frame_cache
*cache
= i386_epilogue_frame_cache (this_frame
,
1973 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
1976 static const struct frame_unwind i386_epilogue_frame_unwind
=
1979 i386_epilogue_frame_unwind_stop_reason
,
1980 i386_epilogue_frame_this_id
,
1981 i386_frame_prev_register
,
1983 i386_epilogue_frame_sniffer
1987 /* Stack-based trampolines. */
1989 /* These trampolines are used on cross x86 targets, when taking the
1990 address of a nested function. When executing these trampolines,
1991 no stack frame is set up, so we are in a similar situation as in
1992 epilogues and i386_epilogue_frame_this_id can be re-used. */
1994 /* Static chain passed in register. */
1996 struct i386_insn i386_tramp_chain_in_reg_insns
[] =
1998 /* `movl imm32, %eax' and `movl imm32, %ecx' */
1999 { 5, { 0xb8 }, { 0xfe } },
2002 { 5, { 0xe9 }, { 0xff } },
2007 /* Static chain passed on stack (when regparm=3). */
2009 struct i386_insn i386_tramp_chain_on_stack_insns
[] =
2012 { 5, { 0x68 }, { 0xff } },
2015 { 5, { 0xe9 }, { 0xff } },
2020 /* Return whether PC points inside a stack trampoline. */
2023 i386_in_stack_tramp_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2028 /* A stack trampoline is detected if no name is associated
2029 to the current pc and if it points inside a trampoline
2032 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
2036 if (target_read_memory (pc
, &insn
, 1))
2039 if (!i386_match_insn_block (pc
, i386_tramp_chain_in_reg_insns
)
2040 && !i386_match_insn_block (pc
, i386_tramp_chain_on_stack_insns
))
2047 i386_stack_tramp_frame_sniffer (const struct frame_unwind
*self
,
2048 struct frame_info
*this_frame
,
2049 void **this_prologue_cache
)
2051 if (frame_relative_level (this_frame
) == 0)
2052 return i386_in_stack_tramp_p (get_frame_arch (this_frame
),
2053 get_frame_pc (this_frame
));
2058 static const struct frame_unwind i386_stack_tramp_frame_unwind
=
2061 i386_epilogue_frame_unwind_stop_reason
,
2062 i386_epilogue_frame_this_id
,
2063 i386_frame_prev_register
,
2065 i386_stack_tramp_frame_sniffer
2069 /* Signal trampolines. */
2071 static struct i386_frame_cache
*
2072 i386_sigtramp_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2074 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2075 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2076 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2077 volatile struct gdb_exception ex
;
2078 struct i386_frame_cache
*cache
;
2085 cache
= i386_alloc_frame_cache ();
2087 TRY_CATCH (ex
, RETURN_MASK_ERROR
)
2089 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
2090 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
) - 4;
2092 addr
= tdep
->sigcontext_addr (this_frame
);
2093 if (tdep
->sc_reg_offset
)
2097 gdb_assert (tdep
->sc_num_regs
<= I386_NUM_SAVED_REGS
);
2099 for (i
= 0; i
< tdep
->sc_num_regs
; i
++)
2100 if (tdep
->sc_reg_offset
[i
] != -1)
2101 cache
->saved_regs
[i
] = addr
+ tdep
->sc_reg_offset
[i
];
2105 cache
->saved_regs
[I386_EIP_REGNUM
] = addr
+ tdep
->sc_pc_offset
;
2106 cache
->saved_regs
[I386_ESP_REGNUM
] = addr
+ tdep
->sc_sp_offset
;
2111 if (ex
.reason
< 0 && ex
.error
!= NOT_AVAILABLE_ERROR
)
2112 throw_exception (ex
);
2114 *this_cache
= cache
;
2118 static enum unwind_stop_reason
2119 i386_sigtramp_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2122 struct i386_frame_cache
*cache
=
2123 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2126 return UNWIND_UNAVAILABLE
;
2128 return UNWIND_NO_REASON
;
2132 i386_sigtramp_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2133 struct frame_id
*this_id
)
2135 struct i386_frame_cache
*cache
=
2136 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2141 /* See the end of i386_push_dummy_call. */
2142 (*this_id
) = frame_id_build (cache
->base
+ 8, get_frame_pc (this_frame
));
2145 static struct value
*
2146 i386_sigtramp_frame_prev_register (struct frame_info
*this_frame
,
2147 void **this_cache
, int regnum
)
2149 /* Make sure we've initialized the cache. */
2150 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2152 return i386_frame_prev_register (this_frame
, this_cache
, regnum
);
2156 i386_sigtramp_frame_sniffer (const struct frame_unwind
*self
,
2157 struct frame_info
*this_frame
,
2158 void **this_prologue_cache
)
2160 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (this_frame
));
2162 /* We shouldn't even bother if we don't have a sigcontext_addr
2164 if (tdep
->sigcontext_addr
== NULL
)
2167 if (tdep
->sigtramp_p
!= NULL
)
2169 if (tdep
->sigtramp_p (this_frame
))
2173 if (tdep
->sigtramp_start
!= 0)
2175 CORE_ADDR pc
= get_frame_pc (this_frame
);
2177 gdb_assert (tdep
->sigtramp_end
!= 0);
2178 if (pc
>= tdep
->sigtramp_start
&& pc
< tdep
->sigtramp_end
)
2185 static const struct frame_unwind i386_sigtramp_frame_unwind
=
2188 i386_sigtramp_frame_unwind_stop_reason
,
2189 i386_sigtramp_frame_this_id
,
2190 i386_sigtramp_frame_prev_register
,
2192 i386_sigtramp_frame_sniffer
2197 i386_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
2199 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
2204 static const struct frame_base i386_frame_base
=
2207 i386_frame_base_address
,
2208 i386_frame_base_address
,
2209 i386_frame_base_address
2212 static struct frame_id
2213 i386_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
2217 fp
= get_frame_register_unsigned (this_frame
, I386_EBP_REGNUM
);
2219 /* See the end of i386_push_dummy_call. */
2220 return frame_id_build (fp
+ 8, get_frame_pc (this_frame
));
2224 /* Figure out where the longjmp will land. Slurp the args out of the
2225 stack. We expect the first arg to be a pointer to the jmp_buf
2226 structure from which we extract the address that we will land at.
2227 This address is copied into PC. This routine returns non-zero on
2231 i386_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
2234 CORE_ADDR sp
, jb_addr
;
2235 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2236 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2237 int jb_pc_offset
= gdbarch_tdep (gdbarch
)->jb_pc_offset
;
2239 /* If JB_PC_OFFSET is -1, we have no way to find out where the
2240 longjmp will land. */
2241 if (jb_pc_offset
== -1)
2244 get_frame_register (frame
, I386_ESP_REGNUM
, buf
);
2245 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
2246 if (target_read_memory (sp
+ 4, buf
, 4))
2249 jb_addr
= extract_unsigned_integer (buf
, 4, byte_order
);
2250 if (target_read_memory (jb_addr
+ jb_pc_offset
, buf
, 4))
2253 *pc
= extract_unsigned_integer (buf
, 4, byte_order
);
2258 /* Check whether TYPE must be 16-byte-aligned when passed as a
2259 function argument. 16-byte vectors, _Decimal128 and structures or
2260 unions containing such types must be 16-byte-aligned; other
2261 arguments are 4-byte-aligned. */
2264 i386_16_byte_align_p (struct type
*type
)
2266 type
= check_typedef (type
);
2267 if ((TYPE_CODE (type
) == TYPE_CODE_DECFLOAT
2268 || (TYPE_CODE (type
) == TYPE_CODE_ARRAY
&& TYPE_VECTOR (type
)))
2269 && TYPE_LENGTH (type
) == 16)
2271 if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
2272 return i386_16_byte_align_p (TYPE_TARGET_TYPE (type
));
2273 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
2274 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
2277 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
2279 if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type
, i
)))
2287 i386_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2288 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
2289 struct value
**args
, CORE_ADDR sp
, int struct_return
,
2290 CORE_ADDR struct_addr
)
2292 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2298 /* Determine the total space required for arguments and struct
2299 return address in a first pass (allowing for 16-byte-aligned
2300 arguments), then push arguments in a second pass. */
2302 for (write_pass
= 0; write_pass
< 2; write_pass
++)
2304 int args_space_used
= 0;
2305 int have_16_byte_aligned_arg
= 0;
2311 /* Push value address. */
2312 store_unsigned_integer (buf
, 4, byte_order
, struct_addr
);
2313 write_memory (sp
, buf
, 4);
2314 args_space_used
+= 4;
2320 for (i
= 0; i
< nargs
; i
++)
2322 int len
= TYPE_LENGTH (value_enclosing_type (args
[i
]));
2326 if (i386_16_byte_align_p (value_enclosing_type (args
[i
])))
2327 args_space_used
= align_up (args_space_used
, 16);
2329 write_memory (sp
+ args_space_used
,
2330 value_contents_all (args
[i
]), len
);
2331 /* The System V ABI says that:
2333 "An argument's size is increased, if necessary, to make it a
2334 multiple of [32-bit] words. This may require tail padding,
2335 depending on the size of the argument."
2337 This makes sure the stack stays word-aligned. */
2338 args_space_used
+= align_up (len
, 4);
2342 if (i386_16_byte_align_p (value_enclosing_type (args
[i
])))
2344 args_space
= align_up (args_space
, 16);
2345 have_16_byte_aligned_arg
= 1;
2347 args_space
+= align_up (len
, 4);
2353 if (have_16_byte_aligned_arg
)
2354 args_space
= align_up (args_space
, 16);
2359 /* Store return address. */
2361 store_unsigned_integer (buf
, 4, byte_order
, bp_addr
);
2362 write_memory (sp
, buf
, 4);
2364 /* Finally, update the stack pointer... */
2365 store_unsigned_integer (buf
, 4, byte_order
, sp
);
2366 regcache_cooked_write (regcache
, I386_ESP_REGNUM
, buf
);
2368 /* ...and fake a frame pointer. */
2369 regcache_cooked_write (regcache
, I386_EBP_REGNUM
, buf
);
2371 /* MarkK wrote: This "+ 8" is all over the place:
2372 (i386_frame_this_id, i386_sigtramp_frame_this_id,
2373 i386_dummy_id). It's there, since all frame unwinders for
2374 a given target have to agree (within a certain margin) on the
2375 definition of the stack address of a frame. Otherwise frame id
2376 comparison might not work correctly. Since DWARF2/GCC uses the
2377 stack address *before* the function call as a frame's CFA. On
2378 the i386, when %ebp is used as a frame pointer, the offset
2379 between the contents %ebp and the CFA as defined by GCC. */
2383 /* These registers are used for returning integers (and on some
2384 targets also for returning `struct' and `union' values when their
2385 size and alignment match an integer type). */
2386 #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */
2387 #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */
2389 /* Read, for architecture GDBARCH, a function return value of TYPE
2390 from REGCACHE, and copy that into VALBUF. */
2393 i386_extract_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
2394 struct regcache
*regcache
, gdb_byte
*valbuf
)
2396 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2397 int len
= TYPE_LENGTH (type
);
2398 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
2400 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2402 if (tdep
->st0_regnum
< 0)
2404 warning (_("Cannot find floating-point return value."));
2405 memset (valbuf
, 0, len
);
2409 /* Floating-point return values can be found in %st(0). Convert
2410 its contents to the desired type. This is probably not
2411 exactly how it would happen on the target itself, but it is
2412 the best we can do. */
2413 regcache_raw_read (regcache
, I386_ST0_REGNUM
, buf
);
2414 convert_typed_floating (buf
, i387_ext_type (gdbarch
), valbuf
, type
);
2418 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
2419 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
2421 if (len
<= low_size
)
2423 regcache_raw_read (regcache
, LOW_RETURN_REGNUM
, buf
);
2424 memcpy (valbuf
, buf
, len
);
2426 else if (len
<= (low_size
+ high_size
))
2428 regcache_raw_read (regcache
, LOW_RETURN_REGNUM
, buf
);
2429 memcpy (valbuf
, buf
, low_size
);
2430 regcache_raw_read (regcache
, HIGH_RETURN_REGNUM
, buf
);
2431 memcpy (valbuf
+ low_size
, buf
, len
- low_size
);
2434 internal_error (__FILE__
, __LINE__
,
2435 _("Cannot extract return value of %d bytes long."),
2440 /* Write, for architecture GDBARCH, a function return value of TYPE
2441 from VALBUF into REGCACHE. */
2444 i386_store_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
2445 struct regcache
*regcache
, const gdb_byte
*valbuf
)
2447 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2448 int len
= TYPE_LENGTH (type
);
2450 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2453 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
2455 if (tdep
->st0_regnum
< 0)
2457 warning (_("Cannot set floating-point return value."));
2461 /* Returning floating-point values is a bit tricky. Apart from
2462 storing the return value in %st(0), we have to simulate the
2463 state of the FPU at function return point. */
2465 /* Convert the value found in VALBUF to the extended
2466 floating-point format used by the FPU. This is probably
2467 not exactly how it would happen on the target itself, but
2468 it is the best we can do. */
2469 convert_typed_floating (valbuf
, type
, buf
, i387_ext_type (gdbarch
));
2470 regcache_raw_write (regcache
, I386_ST0_REGNUM
, buf
);
2472 /* Set the top of the floating-point register stack to 7. The
2473 actual value doesn't really matter, but 7 is what a normal
2474 function return would end up with if the program started out
2475 with a freshly initialized FPU. */
2476 regcache_raw_read_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), &fstat
);
2478 regcache_raw_write_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), fstat
);
2480 /* Mark %st(1) through %st(7) as empty. Since we set the top of
2481 the floating-point register stack to 7, the appropriate value
2482 for the tag word is 0x3fff. */
2483 regcache_raw_write_unsigned (regcache
, I387_FTAG_REGNUM (tdep
), 0x3fff);
2487 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
2488 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
2490 if (len
<= low_size
)
2491 regcache_raw_write_part (regcache
, LOW_RETURN_REGNUM
, 0, len
, valbuf
);
2492 else if (len
<= (low_size
+ high_size
))
2494 regcache_raw_write (regcache
, LOW_RETURN_REGNUM
, valbuf
);
2495 regcache_raw_write_part (regcache
, HIGH_RETURN_REGNUM
, 0,
2496 len
- low_size
, valbuf
+ low_size
);
2499 internal_error (__FILE__
, __LINE__
,
2500 _("Cannot store return value of %d bytes long."), len
);
2505 /* This is the variable that is set with "set struct-convention", and
2506 its legitimate values. */
2507 static const char default_struct_convention
[] = "default";
2508 static const char pcc_struct_convention
[] = "pcc";
2509 static const char reg_struct_convention
[] = "reg";
2510 static const char *valid_conventions
[] =
2512 default_struct_convention
,
2513 pcc_struct_convention
,
2514 reg_struct_convention
,
2517 static const char *struct_convention
= default_struct_convention
;
2519 /* Return non-zero if TYPE, which is assumed to be a structure,
2520 a union type, or an array type, should be returned in registers
2521 for architecture GDBARCH. */
2524 i386_reg_struct_return_p (struct gdbarch
*gdbarch
, struct type
*type
)
2526 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2527 enum type_code code
= TYPE_CODE (type
);
2528 int len
= TYPE_LENGTH (type
);
2530 gdb_assert (code
== TYPE_CODE_STRUCT
2531 || code
== TYPE_CODE_UNION
2532 || code
== TYPE_CODE_ARRAY
);
2534 if (struct_convention
== pcc_struct_convention
2535 || (struct_convention
== default_struct_convention
2536 && tdep
->struct_return
== pcc_struct_return
))
2539 /* Structures consisting of a single `float', `double' or 'long
2540 double' member are returned in %st(0). */
2541 if (code
== TYPE_CODE_STRUCT
&& TYPE_NFIELDS (type
) == 1)
2543 type
= check_typedef (TYPE_FIELD_TYPE (type
, 0));
2544 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2545 return (len
== 4 || len
== 8 || len
== 12);
2548 return (len
== 1 || len
== 2 || len
== 4 || len
== 8);
2551 /* Determine, for architecture GDBARCH, how a return value of TYPE
2552 should be returned. If it is supposed to be returned in registers,
2553 and READBUF is non-zero, read the appropriate value from REGCACHE,
2554 and copy it into READBUF. If WRITEBUF is non-zero, write the value
2555 from WRITEBUF into REGCACHE. */
2557 static enum return_value_convention
2558 i386_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
2559 struct type
*type
, struct regcache
*regcache
,
2560 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2562 enum type_code code
= TYPE_CODE (type
);
2564 if (((code
== TYPE_CODE_STRUCT
2565 || code
== TYPE_CODE_UNION
2566 || code
== TYPE_CODE_ARRAY
)
2567 && !i386_reg_struct_return_p (gdbarch
, type
))
2568 /* 128-bit decimal float uses the struct return convention. */
2569 || (code
== TYPE_CODE_DECFLOAT
&& TYPE_LENGTH (type
) == 16))
2571 /* The System V ABI says that:
2573 "A function that returns a structure or union also sets %eax
2574 to the value of the original address of the caller's area
2575 before it returns. Thus when the caller receives control
2576 again, the address of the returned object resides in register
2577 %eax and can be used to access the object."
2579 So the ABI guarantees that we can always find the return
2580 value just after the function has returned. */
2582 /* Note that the ABI doesn't mention functions returning arrays,
2583 which is something possible in certain languages such as Ada.
2584 In this case, the value is returned as if it was wrapped in
2585 a record, so the convention applied to records also applies
2592 regcache_raw_read_unsigned (regcache
, I386_EAX_REGNUM
, &addr
);
2593 read_memory (addr
, readbuf
, TYPE_LENGTH (type
));
2596 return RETURN_VALUE_ABI_RETURNS_ADDRESS
;
2599 /* This special case is for structures consisting of a single
2600 `float', `double' or 'long double' member. These structures are
2601 returned in %st(0). For these structures, we call ourselves
2602 recursively, changing TYPE into the type of the first member of
2603 the structure. Since that should work for all structures that
2604 have only one member, we don't bother to check the member's type
2606 if (code
== TYPE_CODE_STRUCT
&& TYPE_NFIELDS (type
) == 1)
2608 type
= check_typedef (TYPE_FIELD_TYPE (type
, 0));
2609 return i386_return_value (gdbarch
, func_type
, type
, regcache
,
2614 i386_extract_return_value (gdbarch
, type
, regcache
, readbuf
);
2616 i386_store_return_value (gdbarch
, type
, regcache
, writebuf
);
2618 return RETURN_VALUE_REGISTER_CONVENTION
;
2623 i387_ext_type (struct gdbarch
*gdbarch
)
2625 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2627 if (!tdep
->i387_ext_type
)
2629 tdep
->i387_ext_type
= tdesc_find_type (gdbarch
, "i387_ext");
2630 gdb_assert (tdep
->i387_ext_type
!= NULL
);
2633 return tdep
->i387_ext_type
;
2636 /* Construct vector type for pseudo YMM registers. We can't use
2637 tdesc_find_type since YMM isn't described in target description. */
2639 static struct type
*
2640 i386_ymm_type (struct gdbarch
*gdbarch
)
2642 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2644 if (!tdep
->i386_ymm_type
)
2646 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2648 /* The type we're building is this: */
2650 union __gdb_builtin_type_vec256i
2652 int128_t uint128
[2];
2653 int64_t v2_int64
[4];
2654 int32_t v4_int32
[8];
2655 int16_t v8_int16
[16];
2656 int8_t v16_int8
[32];
2657 double v2_double
[4];
2664 t
= arch_composite_type (gdbarch
,
2665 "__gdb_builtin_type_vec256i", TYPE_CODE_UNION
);
2666 append_composite_type_field (t
, "v8_float",
2667 init_vector_type (bt
->builtin_float
, 8));
2668 append_composite_type_field (t
, "v4_double",
2669 init_vector_type (bt
->builtin_double
, 4));
2670 append_composite_type_field (t
, "v32_int8",
2671 init_vector_type (bt
->builtin_int8
, 32));
2672 append_composite_type_field (t
, "v16_int16",
2673 init_vector_type (bt
->builtin_int16
, 16));
2674 append_composite_type_field (t
, "v8_int32",
2675 init_vector_type (bt
->builtin_int32
, 8));
2676 append_composite_type_field (t
, "v4_int64",
2677 init_vector_type (bt
->builtin_int64
, 4));
2678 append_composite_type_field (t
, "v2_int128",
2679 init_vector_type (bt
->builtin_int128
, 2));
2681 TYPE_VECTOR (t
) = 1;
2682 TYPE_NAME (t
) = "builtin_type_vec256i";
2683 tdep
->i386_ymm_type
= t
;
2686 return tdep
->i386_ymm_type
;
2689 /* Construct vector type for MMX registers. */
2690 static struct type
*
2691 i386_mmx_type (struct gdbarch
*gdbarch
)
2693 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2695 if (!tdep
->i386_mmx_type
)
2697 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2699 /* The type we're building is this: */
2701 union __gdb_builtin_type_vec64i
2704 int32_t v2_int32
[2];
2705 int16_t v4_int16
[4];
2712 t
= arch_composite_type (gdbarch
,
2713 "__gdb_builtin_type_vec64i", TYPE_CODE_UNION
);
2715 append_composite_type_field (t
, "uint64", bt
->builtin_int64
);
2716 append_composite_type_field (t
, "v2_int32",
2717 init_vector_type (bt
->builtin_int32
, 2));
2718 append_composite_type_field (t
, "v4_int16",
2719 init_vector_type (bt
->builtin_int16
, 4));
2720 append_composite_type_field (t
, "v8_int8",
2721 init_vector_type (bt
->builtin_int8
, 8));
2723 TYPE_VECTOR (t
) = 1;
2724 TYPE_NAME (t
) = "builtin_type_vec64i";
2725 tdep
->i386_mmx_type
= t
;
2728 return tdep
->i386_mmx_type
;
2731 /* Return the GDB type object for the "standard" data type of data in
2734 static struct type
*
2735 i386_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
2737 if (i386_mmx_regnum_p (gdbarch
, regnum
))
2738 return i386_mmx_type (gdbarch
);
2739 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
2740 return i386_ymm_type (gdbarch
);
2743 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2744 if (i386_byte_regnum_p (gdbarch
, regnum
))
2745 return bt
->builtin_int8
;
2746 else if (i386_word_regnum_p (gdbarch
, regnum
))
2747 return bt
->builtin_int16
;
2748 else if (i386_dword_regnum_p (gdbarch
, regnum
))
2749 return bt
->builtin_int32
;
2752 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
2755 /* Map a cooked register onto a raw register or memory. For the i386,
2756 the MMX registers need to be mapped onto floating point registers. */
2759 i386_mmx_regnum_to_fp_regnum (struct regcache
*regcache
, int regnum
)
2761 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_regcache_arch (regcache
));
2766 mmxreg
= regnum
- tdep
->mm0_regnum
;
2767 regcache_raw_read_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), &fstat
);
2768 tos
= (fstat
>> 11) & 0x7;
2769 fpreg
= (mmxreg
+ tos
) % 8;
2771 return (I387_ST0_REGNUM (tdep
) + fpreg
);
2774 enum register_status
2775 i386_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2776 int regnum
, gdb_byte
*buf
)
2778 gdb_byte raw_buf
[MAX_REGISTER_SIZE
];
2779 enum register_status status
;
2781 if (i386_mmx_regnum_p (gdbarch
, regnum
))
2783 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
2785 /* Extract (always little endian). */
2786 status
= regcache_raw_read (regcache
, fpnum
, raw_buf
);
2787 if (status
!= REG_VALID
)
2789 memcpy (buf
, raw_buf
, register_size (gdbarch
, regnum
));
2793 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2795 if (i386_ymm_regnum_p (gdbarch
, regnum
))
2797 regnum
-= tdep
->ymm0_regnum
;
2799 /* Extract (always little endian). Read lower 128bits. */
2800 status
= regcache_raw_read (regcache
,
2801 I387_XMM0_REGNUM (tdep
) + regnum
,
2803 if (status
!= REG_VALID
)
2805 memcpy (buf
, raw_buf
, 16);
2806 /* Read upper 128bits. */
2807 status
= regcache_raw_read (regcache
,
2808 tdep
->ymm0h_regnum
+ regnum
,
2810 if (status
!= REG_VALID
)
2812 memcpy (buf
+ 16, raw_buf
, 16);
2814 else if (i386_word_regnum_p (gdbarch
, regnum
))
2816 int gpnum
= regnum
- tdep
->ax_regnum
;
2818 /* Extract (always little endian). */
2819 status
= regcache_raw_read (regcache
, gpnum
, raw_buf
);
2820 if (status
!= REG_VALID
)
2822 memcpy (buf
, raw_buf
, 2);
2824 else if (i386_byte_regnum_p (gdbarch
, regnum
))
2826 /* Check byte pseudo registers last since this function will
2827 be called from amd64_pseudo_register_read, which handles
2828 byte pseudo registers differently. */
2829 int gpnum
= regnum
- tdep
->al_regnum
;
2831 /* Extract (always little endian). We read both lower and
2833 status
= regcache_raw_read (regcache
, gpnum
% 4, raw_buf
);
2834 if (status
!= REG_VALID
)
2837 memcpy (buf
, raw_buf
+ 1, 1);
2839 memcpy (buf
, raw_buf
, 1);
2842 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
2849 i386_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2850 int regnum
, const gdb_byte
*buf
)
2852 gdb_byte raw_buf
[MAX_REGISTER_SIZE
];
2854 if (i386_mmx_regnum_p (gdbarch
, regnum
))
2856 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
2859 regcache_raw_read (regcache
, fpnum
, raw_buf
);
2860 /* ... Modify ... (always little endian). */
2861 memcpy (raw_buf
, buf
, register_size (gdbarch
, regnum
));
2863 regcache_raw_write (regcache
, fpnum
, raw_buf
);
2867 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2869 if (i386_ymm_regnum_p (gdbarch
, regnum
))
2871 regnum
-= tdep
->ymm0_regnum
;
2873 /* ... Write lower 128bits. */
2874 regcache_raw_write (regcache
,
2875 I387_XMM0_REGNUM (tdep
) + regnum
,
2877 /* ... Write upper 128bits. */
2878 regcache_raw_write (regcache
,
2879 tdep
->ymm0h_regnum
+ regnum
,
2882 else if (i386_word_regnum_p (gdbarch
, regnum
))
2884 int gpnum
= regnum
- tdep
->ax_regnum
;
2887 regcache_raw_read (regcache
, gpnum
, raw_buf
);
2888 /* ... Modify ... (always little endian). */
2889 memcpy (raw_buf
, buf
, 2);
2891 regcache_raw_write (regcache
, gpnum
, raw_buf
);
2893 else if (i386_byte_regnum_p (gdbarch
, regnum
))
2895 /* Check byte pseudo registers last since this function will
2896 be called from amd64_pseudo_register_read, which handles
2897 byte pseudo registers differently. */
2898 int gpnum
= regnum
- tdep
->al_regnum
;
2900 /* Read ... We read both lower and upper registers. */
2901 regcache_raw_read (regcache
, gpnum
% 4, raw_buf
);
2902 /* ... Modify ... (always little endian). */
2904 memcpy (raw_buf
+ 1, buf
, 1);
2906 memcpy (raw_buf
, buf
, 1);
2908 regcache_raw_write (regcache
, gpnum
% 4, raw_buf
);
2911 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
2916 /* Return the register number of the register allocated by GCC after
2917 REGNUM, or -1 if there is no such register. */
2920 i386_next_regnum (int regnum
)
2922 /* GCC allocates the registers in the order:
2924 %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ...
2926 Since storing a variable in %esp doesn't make any sense we return
2927 -1 for %ebp and for %esp itself. */
2928 static int next_regnum
[] =
2930 I386_EDX_REGNUM
, /* Slot for %eax. */
2931 I386_EBX_REGNUM
, /* Slot for %ecx. */
2932 I386_ECX_REGNUM
, /* Slot for %edx. */
2933 I386_ESI_REGNUM
, /* Slot for %ebx. */
2934 -1, -1, /* Slots for %esp and %ebp. */
2935 I386_EDI_REGNUM
, /* Slot for %esi. */
2936 I386_EBP_REGNUM
/* Slot for %edi. */
2939 if (regnum
>= 0 && regnum
< sizeof (next_regnum
) / sizeof (next_regnum
[0]))
2940 return next_regnum
[regnum
];
2945 /* Return nonzero if a value of type TYPE stored in register REGNUM
2946 needs any special handling. */
2949 i386_convert_register_p (struct gdbarch
*gdbarch
,
2950 int regnum
, struct type
*type
)
2952 int len
= TYPE_LENGTH (type
);
2954 /* Values may be spread across multiple registers. Most debugging
2955 formats aren't expressive enough to specify the locations, so
2956 some heuristics is involved. Right now we only handle types that
2957 have a length that is a multiple of the word size, since GCC
2958 doesn't seem to put any other types into registers. */
2959 if (len
> 4 && len
% 4 == 0)
2961 int last_regnum
= regnum
;
2965 last_regnum
= i386_next_regnum (last_regnum
);
2969 if (last_regnum
!= -1)
2973 return i387_convert_register_p (gdbarch
, regnum
, type
);
2976 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
2977 return its contents in TO. */
2980 i386_register_to_value (struct frame_info
*frame
, int regnum
,
2981 struct type
*type
, gdb_byte
*to
,
2982 int *optimizedp
, int *unavailablep
)
2984 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2985 int len
= TYPE_LENGTH (type
);
2987 if (i386_fp_regnum_p (gdbarch
, regnum
))
2988 return i387_register_to_value (frame
, regnum
, type
, to
,
2989 optimizedp
, unavailablep
);
2991 /* Read a value spread across multiple registers. */
2993 gdb_assert (len
> 4 && len
% 4 == 0);
2997 gdb_assert (regnum
!= -1);
2998 gdb_assert (register_size (gdbarch
, regnum
) == 4);
3000 if (!get_frame_register_bytes (frame
, regnum
, 0,
3001 register_size (gdbarch
, regnum
),
3002 to
, optimizedp
, unavailablep
))
3005 regnum
= i386_next_regnum (regnum
);
3010 *optimizedp
= *unavailablep
= 0;
3014 /* Write the contents FROM of a value of type TYPE into register
3015 REGNUM in frame FRAME. */
3018 i386_value_to_register (struct frame_info
*frame
, int regnum
,
3019 struct type
*type
, const gdb_byte
*from
)
3021 int len
= TYPE_LENGTH (type
);
3023 if (i386_fp_regnum_p (get_frame_arch (frame
), regnum
))
3025 i387_value_to_register (frame
, regnum
, type
, from
);
3029 /* Write a value spread across multiple registers. */
3031 gdb_assert (len
> 4 && len
% 4 == 0);
3035 gdb_assert (regnum
!= -1);
3036 gdb_assert (register_size (get_frame_arch (frame
), regnum
) == 4);
3038 put_frame_register (frame
, regnum
, from
);
3039 regnum
= i386_next_regnum (regnum
);
3045 /* Supply register REGNUM from the buffer specified by GREGS and LEN
3046 in the general-purpose register set REGSET to register cache
3047 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3050 i386_supply_gregset (const struct regset
*regset
, struct regcache
*regcache
,
3051 int regnum
, const void *gregs
, size_t len
)
3053 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
3054 const gdb_byte
*regs
= gregs
;
3057 gdb_assert (len
== tdep
->sizeof_gregset
);
3059 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
3061 if ((regnum
== i
|| regnum
== -1)
3062 && tdep
->gregset_reg_offset
[i
] != -1)
3063 regcache_raw_supply (regcache
, i
, regs
+ tdep
->gregset_reg_offset
[i
]);
3067 /* Collect register REGNUM from the register cache REGCACHE and store
3068 it in the buffer specified by GREGS and LEN as described by the
3069 general-purpose register set REGSET. If REGNUM is -1, do this for
3070 all registers in REGSET. */
3073 i386_collect_gregset (const struct regset
*regset
,
3074 const struct regcache
*regcache
,
3075 int regnum
, void *gregs
, size_t len
)
3077 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
3078 gdb_byte
*regs
= gregs
;
3081 gdb_assert (len
== tdep
->sizeof_gregset
);
3083 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
3085 if ((regnum
== i
|| regnum
== -1)
3086 && tdep
->gregset_reg_offset
[i
] != -1)
3087 regcache_raw_collect (regcache
, i
, regs
+ tdep
->gregset_reg_offset
[i
]);
3091 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
3092 in the floating-point register set REGSET to register cache
3093 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3096 i386_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
3097 int regnum
, const void *fpregs
, size_t len
)
3099 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
3101 if (len
== I387_SIZEOF_FXSAVE
)
3103 i387_supply_fxsave (regcache
, regnum
, fpregs
);
3107 gdb_assert (len
== tdep
->sizeof_fpregset
);
3108 i387_supply_fsave (regcache
, regnum
, fpregs
);
3111 /* Collect register REGNUM from the register cache REGCACHE and store
3112 it in the buffer specified by FPREGS and LEN as described by the
3113 floating-point register set REGSET. If REGNUM is -1, do this for
3114 all registers in REGSET. */
3117 i386_collect_fpregset (const struct regset
*regset
,
3118 const struct regcache
*regcache
,
3119 int regnum
, void *fpregs
, size_t len
)
3121 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
3123 if (len
== I387_SIZEOF_FXSAVE
)
3125 i387_collect_fxsave (regcache
, regnum
, fpregs
);
3129 gdb_assert (len
== tdep
->sizeof_fpregset
);
3130 i387_collect_fsave (regcache
, regnum
, fpregs
);
3133 /* Similar to i386_supply_fpregset, but use XSAVE extended state. */
3136 i386_supply_xstateregset (const struct regset
*regset
,
3137 struct regcache
*regcache
, int regnum
,
3138 const void *xstateregs
, size_t len
)
3140 i387_supply_xsave (regcache
, regnum
, xstateregs
);
3143 /* Similar to i386_collect_fpregset , but use XSAVE extended state. */
3146 i386_collect_xstateregset (const struct regset
*regset
,
3147 const struct regcache
*regcache
,
3148 int regnum
, void *xstateregs
, size_t len
)
3150 i387_collect_xsave (regcache
, regnum
, xstateregs
, 1);
3153 /* Return the appropriate register set for the core section identified
3154 by SECT_NAME and SECT_SIZE. */
3156 const struct regset
*
3157 i386_regset_from_core_section (struct gdbarch
*gdbarch
,
3158 const char *sect_name
, size_t sect_size
)
3160 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3162 if (strcmp (sect_name
, ".reg") == 0 && sect_size
== tdep
->sizeof_gregset
)
3164 if (tdep
->gregset
== NULL
)
3165 tdep
->gregset
= regset_alloc (gdbarch
, i386_supply_gregset
,
3166 i386_collect_gregset
);
3167 return tdep
->gregset
;
3170 if ((strcmp (sect_name
, ".reg2") == 0 && sect_size
== tdep
->sizeof_fpregset
)
3171 || (strcmp (sect_name
, ".reg-xfp") == 0
3172 && sect_size
== I387_SIZEOF_FXSAVE
))
3174 if (tdep
->fpregset
== NULL
)
3175 tdep
->fpregset
= regset_alloc (gdbarch
, i386_supply_fpregset
,
3176 i386_collect_fpregset
);
3177 return tdep
->fpregset
;
3180 if (strcmp (sect_name
, ".reg-xstate") == 0)
3182 if (tdep
->xstateregset
== NULL
)
3183 tdep
->xstateregset
= regset_alloc (gdbarch
,
3184 i386_supply_xstateregset
,
3185 i386_collect_xstateregset
);
3187 return tdep
->xstateregset
;
3194 /* Stuff for WIN32 PE style DLL's but is pretty generic really. */
3197 i386_pe_skip_trampoline_code (struct frame_info
*frame
,
3198 CORE_ADDR pc
, char *name
)
3200 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3201 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3204 if (pc
&& read_memory_unsigned_integer (pc
, 2, byte_order
) == 0x25ff)
3206 unsigned long indirect
=
3207 read_memory_unsigned_integer (pc
+ 2, 4, byte_order
);
3208 struct minimal_symbol
*indsym
=
3209 indirect
? lookup_minimal_symbol_by_pc (indirect
) : 0;
3210 char *symname
= indsym
? SYMBOL_LINKAGE_NAME (indsym
) : 0;
3214 if (strncmp (symname
, "__imp_", 6) == 0
3215 || strncmp (symname
, "_imp_", 5) == 0)
3217 read_memory_unsigned_integer (indirect
, 4, byte_order
);
3220 return 0; /* Not a trampoline. */
3224 /* Return whether the THIS_FRAME corresponds to a sigtramp
3228 i386_sigtramp_p (struct frame_info
*this_frame
)
3230 CORE_ADDR pc
= get_frame_pc (this_frame
);
3233 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
3234 return (name
&& strcmp ("_sigtramp", name
) == 0);
3238 /* We have two flavours of disassembly. The machinery on this page
3239 deals with switching between those. */
3242 i386_print_insn (bfd_vma pc
, struct disassemble_info
*info
)
3244 gdb_assert (disassembly_flavor
== att_flavor
3245 || disassembly_flavor
== intel_flavor
);
3247 /* FIXME: kettenis/20020915: Until disassembler_options is properly
3248 constified, cast to prevent a compiler warning. */
3249 info
->disassembler_options
= (char *) disassembly_flavor
;
3251 return print_insn_i386 (pc
, info
);
3255 /* There are a few i386 architecture variants that differ only
3256 slightly from the generic i386 target. For now, we don't give them
3257 their own source file, but include them here. As a consequence,
3258 they'll always be included. */
3260 /* System V Release 4 (SVR4). */
3262 /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp
3266 i386_svr4_sigtramp_p (struct frame_info
*this_frame
)
3268 CORE_ADDR pc
= get_frame_pc (this_frame
);
3271 /* UnixWare uses _sigacthandler. The origin of the other symbols is
3272 currently unknown. */
3273 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
3274 return (name
&& (strcmp ("_sigreturn", name
) == 0
3275 || strcmp ("_sigacthandler", name
) == 0
3276 || strcmp ("sigvechandler", name
) == 0));
3279 /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the
3280 address of the associated sigcontext (ucontext) structure. */
3283 i386_svr4_sigcontext_addr (struct frame_info
*this_frame
)
3285 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3286 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3290 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
3291 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
3293 return read_memory_unsigned_integer (sp
+ 8, 4, byte_order
);
3300 i386_elf_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
3302 /* We typically use stabs-in-ELF with the SVR4 register numbering. */
3303 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
3306 /* System V Release 4 (SVR4). */
3309 i386_svr4_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
3311 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3313 /* System V Release 4 uses ELF. */
3314 i386_elf_init_abi (info
, gdbarch
);
3316 /* System V Release 4 has shared libraries. */
3317 set_gdbarch_skip_trampoline_code (gdbarch
, find_solib_trampoline_target
);
3319 tdep
->sigtramp_p
= i386_svr4_sigtramp_p
;
3320 tdep
->sigcontext_addr
= i386_svr4_sigcontext_addr
;
3321 tdep
->sc_pc_offset
= 36 + 14 * 4;
3322 tdep
->sc_sp_offset
= 36 + 17 * 4;
3324 tdep
->jb_pc_offset
= 20;
3330 i386_go32_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
3332 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3334 /* DJGPP doesn't have any special frames for signal handlers. */
3335 tdep
->sigtramp_p
= NULL
;
3337 tdep
->jb_pc_offset
= 36;
3339 /* DJGPP does not support the SSE registers. */
3340 if (! tdesc_has_registers (info
.target_desc
))
3341 tdep
->tdesc
= tdesc_i386_mmx
;
3343 /* Native compiler is GCC, which uses the SVR4 register numbering
3344 even in COFF and STABS. See the comment in i386_gdbarch_init,
3345 before the calls to set_gdbarch_stab_reg_to_regnum and
3346 set_gdbarch_sdb_reg_to_regnum. */
3347 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
3348 set_gdbarch_sdb_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
3350 set_gdbarch_has_dos_based_file_system (gdbarch
, 1);
3354 /* i386 register groups. In addition to the normal groups, add "mmx"
3357 static struct reggroup
*i386_sse_reggroup
;
3358 static struct reggroup
*i386_mmx_reggroup
;
3361 i386_init_reggroups (void)
3363 i386_sse_reggroup
= reggroup_new ("sse", USER_REGGROUP
);
3364 i386_mmx_reggroup
= reggroup_new ("mmx", USER_REGGROUP
);
3368 i386_add_reggroups (struct gdbarch
*gdbarch
)
3370 reggroup_add (gdbarch
, i386_sse_reggroup
);
3371 reggroup_add (gdbarch
, i386_mmx_reggroup
);
3372 reggroup_add (gdbarch
, general_reggroup
);
3373 reggroup_add (gdbarch
, float_reggroup
);
3374 reggroup_add (gdbarch
, all_reggroup
);
3375 reggroup_add (gdbarch
, save_reggroup
);
3376 reggroup_add (gdbarch
, restore_reggroup
);
3377 reggroup_add (gdbarch
, vector_reggroup
);
3378 reggroup_add (gdbarch
, system_reggroup
);
3382 i386_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
3383 struct reggroup
*group
)
3385 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3386 int fp_regnum_p
, mmx_regnum_p
, xmm_regnum_p
, mxcsr_regnum_p
,
3387 ymm_regnum_p
, ymmh_regnum_p
;
3389 /* Don't include pseudo registers, except for MMX, in any register
3391 if (i386_byte_regnum_p (gdbarch
, regnum
))
3394 if (i386_word_regnum_p (gdbarch
, regnum
))
3397 if (i386_dword_regnum_p (gdbarch
, regnum
))
3400 mmx_regnum_p
= i386_mmx_regnum_p (gdbarch
, regnum
);
3401 if (group
== i386_mmx_reggroup
)
3402 return mmx_regnum_p
;
3404 xmm_regnum_p
= i386_xmm_regnum_p (gdbarch
, regnum
);
3405 mxcsr_regnum_p
= i386_mxcsr_regnum_p (gdbarch
, regnum
);
3406 if (group
== i386_sse_reggroup
)
3407 return xmm_regnum_p
|| mxcsr_regnum_p
;
3409 ymm_regnum_p
= i386_ymm_regnum_p (gdbarch
, regnum
);
3410 if (group
== vector_reggroup
)
3411 return (mmx_regnum_p
3415 && ((tdep
->xcr0
& I386_XSTATE_AVX_MASK
)
3416 == I386_XSTATE_SSE_MASK
)));
3418 fp_regnum_p
= (i386_fp_regnum_p (gdbarch
, regnum
)
3419 || i386_fpc_regnum_p (gdbarch
, regnum
));
3420 if (group
== float_reggroup
)
3423 /* For "info reg all", don't include upper YMM registers nor XMM
3424 registers when AVX is supported. */
3425 ymmh_regnum_p
= i386_ymmh_regnum_p (gdbarch
, regnum
);
3426 if (group
== all_reggroup
3428 && (tdep
->xcr0
& I386_XSTATE_AVX
))
3432 if (group
== general_reggroup
)
3433 return (!fp_regnum_p
3440 return default_register_reggroup_p (gdbarch
, regnum
, group
);
3444 /* Get the ARGIth function argument for the current function. */
3447 i386_fetch_pointer_argument (struct frame_info
*frame
, int argi
,
3450 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3451 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3452 CORE_ADDR sp
= get_frame_register_unsigned (frame
, I386_ESP_REGNUM
);
3453 return read_memory_unsigned_integer (sp
+ (4 * (argi
+ 1)), 4, byte_order
);
3457 i386_skip_permanent_breakpoint (struct regcache
*regcache
)
3459 CORE_ADDR current_pc
= regcache_read_pc (regcache
);
3461 /* On i386, breakpoint is exactly 1 byte long, so we just
3462 adjust the PC in the regcache. */
3464 regcache_write_pc (regcache
, current_pc
);
3468 #define PREFIX_REPZ 0x01
3469 #define PREFIX_REPNZ 0x02
3470 #define PREFIX_LOCK 0x04
3471 #define PREFIX_DATA 0x08
3472 #define PREFIX_ADDR 0x10
3484 /* i386 arith/logic operations */
3497 struct i386_record_s
3499 struct gdbarch
*gdbarch
;
3500 struct regcache
*regcache
;
3501 CORE_ADDR orig_addr
;
3507 uint8_t mod
, reg
, rm
;
3516 /* Parse "modrm" part in current memory address that irp->addr point to
3517 Return -1 if something wrong. */
3520 i386_record_modrm (struct i386_record_s
*irp
)
3522 struct gdbarch
*gdbarch
= irp
->gdbarch
;
3524 if (target_read_memory (irp
->addr
, &irp
->modrm
, 1))
3527 printf_unfiltered (_("Process record: error reading memory at "
3528 "addr %s len = 1.\n"),
3529 paddress (gdbarch
, irp
->addr
));
3533 irp
->mod
= (irp
->modrm
>> 6) & 3;
3534 irp
->reg
= (irp
->modrm
>> 3) & 7;
3535 irp
->rm
= irp
->modrm
& 7;
3540 /* Get the memory address that current instruction write to and set it to
3541 the argument "addr".
3542 Return -1 if something wrong. */
3545 i386_record_lea_modrm_addr (struct i386_record_s
*irp
, uint64_t *addr
)
3547 struct gdbarch
*gdbarch
= irp
->gdbarch
;
3548 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3560 uint8_t base
= irp
->rm
;
3565 if (target_read_memory (irp
->addr
, &byte
, 1))
3568 printf_unfiltered (_("Process record: error reading memory "
3569 "at addr %s len = 1.\n"),
3570 paddress (gdbarch
, irp
->addr
));
3574 scale
= (byte
>> 6) & 3;
3575 index
= ((byte
>> 3) & 7) | irp
->rex_x
;
3583 if ((base
& 7) == 5)
3586 if (target_read_memory (irp
->addr
, buf
, 4))
3589 printf_unfiltered (_("Process record: error reading "
3590 "memory at addr %s len = 4.\n"),
3591 paddress (gdbarch
, irp
->addr
));
3595 *addr
= extract_signed_integer (buf
, 4, byte_order
);
3596 if (irp
->regmap
[X86_RECORD_R8_REGNUM
] && !havesib
)
3597 *addr
+= irp
->addr
+ irp
->rip_offset
;
3601 if (target_read_memory (irp
->addr
, buf
, 1))
3604 printf_unfiltered (_("Process record: error reading memory "
3605 "at addr %s len = 1.\n"),
3606 paddress (gdbarch
, irp
->addr
));
3610 *addr
= (int8_t) buf
[0];
3613 if (target_read_memory (irp
->addr
, buf
, 4))
3616 printf_unfiltered (_("Process record: error reading memory "
3617 "at addr %s len = 4.\n"),
3618 paddress (gdbarch
, irp
->addr
));
3621 *addr
= extract_signed_integer (buf
, 4, byte_order
);
3629 if (base
== 4 && irp
->popl_esp_hack
)
3630 *addr
+= irp
->popl_esp_hack
;
3631 regcache_raw_read_unsigned (irp
->regcache
, irp
->regmap
[base
],
3634 if (irp
->aflag
== 2)
3639 *addr
= (uint32_t) (offset64
+ *addr
);
3641 if (havesib
&& (index
!= 4 || scale
!= 0))
3643 regcache_raw_read_unsigned (irp
->regcache
, irp
->regmap
[index
],
3645 if (irp
->aflag
== 2)
3646 *addr
+= offset64
<< scale
;
3648 *addr
= (uint32_t) (*addr
+ (offset64
<< scale
));
3659 if (target_read_memory (irp
->addr
, buf
, 2))
3662 printf_unfiltered (_("Process record: error reading "
3663 "memory at addr %s len = 2.\n"),
3664 paddress (gdbarch
, irp
->addr
));
3668 *addr
= extract_signed_integer (buf
, 2, byte_order
);
3674 if (target_read_memory (irp
->addr
, buf
, 1))
3677 printf_unfiltered (_("Process record: error reading memory "
3678 "at addr %s len = 1.\n"),
3679 paddress (gdbarch
, irp
->addr
));
3683 *addr
= (int8_t) buf
[0];
3686 if (target_read_memory (irp
->addr
, buf
, 2))
3689 printf_unfiltered (_("Process record: error reading memory "
3690 "at addr %s len = 2.\n"),
3691 paddress (gdbarch
, irp
->addr
));
3695 *addr
= extract_signed_integer (buf
, 2, byte_order
);
3702 regcache_raw_read_unsigned (irp
->regcache
,
3703 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
3705 *addr
= (uint32_t) (*addr
+ offset64
);
3706 regcache_raw_read_unsigned (irp
->regcache
,
3707 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
3709 *addr
= (uint32_t) (*addr
+ offset64
);
3712 regcache_raw_read_unsigned (irp
->regcache
,
3713 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
3715 *addr
= (uint32_t) (*addr
+ offset64
);
3716 regcache_raw_read_unsigned (irp
->regcache
,
3717 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
3719 *addr
= (uint32_t) (*addr
+ offset64
);
3722 regcache_raw_read_unsigned (irp
->regcache
,
3723 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
3725 *addr
= (uint32_t) (*addr
+ offset64
);
3726 regcache_raw_read_unsigned (irp
->regcache
,
3727 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
3729 *addr
= (uint32_t) (*addr
+ offset64
);
3732 regcache_raw_read_unsigned (irp
->regcache
,
3733 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
3735 *addr
= (uint32_t) (*addr
+ offset64
);
3736 regcache_raw_read_unsigned (irp
->regcache
,
3737 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
3739 *addr
= (uint32_t) (*addr
+ offset64
);
3742 regcache_raw_read_unsigned (irp
->regcache
,
3743 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
3745 *addr
= (uint32_t) (*addr
+ offset64
);
3748 regcache_raw_read_unsigned (irp
->regcache
,
3749 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
3751 *addr
= (uint32_t) (*addr
+ offset64
);
3754 regcache_raw_read_unsigned (irp
->regcache
,
3755 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
3757 *addr
= (uint32_t) (*addr
+ offset64
);
3760 regcache_raw_read_unsigned (irp
->regcache
,
3761 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
3763 *addr
= (uint32_t) (*addr
+ offset64
);
3773 /* Record the value of the memory that willbe changed in current instruction
3774 to "record_arch_list".
3775 Return -1 if something wrong. */
3778 i386_record_lea_modrm (struct i386_record_s
*irp
)
3780 struct gdbarch
*gdbarch
= irp
->gdbarch
;
3783 if (irp
->override
>= 0)
3785 if (record_memory_query
)
3789 target_terminal_ours ();
3791 Process record ignores the memory change of instruction at address %s\n\
3792 because it can't get the value of the segment register.\n\
3793 Do you want to stop the program?"),
3794 paddress (gdbarch
, irp
->orig_addr
));
3795 target_terminal_inferior ();
3803 if (i386_record_lea_modrm_addr (irp
, &addr
))
3806 if (record_arch_list_add_mem (addr
, 1 << irp
->ot
))
3812 /* Record the push operation to "record_arch_list".
3813 Return -1 if something wrong. */
3816 i386_record_push (struct i386_record_s
*irp
, int size
)
3820 if (record_arch_list_add_reg (irp
->regcache
,
3821 irp
->regmap
[X86_RECORD_RESP_REGNUM
]))
3823 regcache_raw_read_unsigned (irp
->regcache
,
3824 irp
->regmap
[X86_RECORD_RESP_REGNUM
],
3826 if (record_arch_list_add_mem ((CORE_ADDR
) addr
- size
, size
))
3833 /* Defines contents to record. */
3834 #define I386_SAVE_FPU_REGS 0xfffd
3835 #define I386_SAVE_FPU_ENV 0xfffe
3836 #define I386_SAVE_FPU_ENV_REG_STACK 0xffff
3838 /* Record the value of floating point registers which will be changed
3839 by the current instruction to "record_arch_list". Return -1 if
3840 something is wrong. */
3842 static int i386_record_floats (struct gdbarch
*gdbarch
,
3843 struct i386_record_s
*ir
,
3846 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3849 /* Oza: Because of floating point insn push/pop of fpu stack is going to
3850 happen. Currently we store st0-st7 registers, but we need not store all
3851 registers all the time, in future we use ftag register and record only
3852 those who are not marked as an empty. */
3854 if (I386_SAVE_FPU_REGS
== iregnum
)
3856 for (i
= I387_ST0_REGNUM (tdep
); i
<= I387_ST0_REGNUM (tdep
) + 7; i
++)
3858 if (record_arch_list_add_reg (ir
->regcache
, i
))
3862 else if (I386_SAVE_FPU_ENV
== iregnum
)
3864 for (i
= I387_FCTRL_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
3866 if (record_arch_list_add_reg (ir
->regcache
, i
))
3870 else if (I386_SAVE_FPU_ENV_REG_STACK
== iregnum
)
3872 for (i
= I387_ST0_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
3874 if (record_arch_list_add_reg (ir
->regcache
, i
))
3878 else if ((iregnum
>= I387_ST0_REGNUM (tdep
)) &&
3879 (iregnum
<= I387_FOP_REGNUM (tdep
)))
3881 if (record_arch_list_add_reg (ir
->regcache
,iregnum
))
3886 /* Parameter error. */
3889 if(I386_SAVE_FPU_ENV
!= iregnum
)
3891 for (i
= I387_FCTRL_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
3893 if (record_arch_list_add_reg (ir
->regcache
, i
))
3900 /* Parse the current instruction and record the values of the registers and
3901 memory that will be changed in current instruction to "record_arch_list".
3902 Return -1 if something wrong. */
3904 #define I386_RECORD_ARCH_LIST_ADD_REG(regnum) \
3905 record_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)])
3908 i386_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
3909 CORE_ADDR input_addr
)
3911 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3917 gdb_byte buf
[MAX_REGISTER_SIZE
];
3918 struct i386_record_s ir
;
3919 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3924 memset (&ir
, 0, sizeof (struct i386_record_s
));
3925 ir
.regcache
= regcache
;
3926 ir
.addr
= input_addr
;
3927 ir
.orig_addr
= input_addr
;
3931 ir
.popl_esp_hack
= 0;
3932 ir
.regmap
= tdep
->record_regmap
;
3933 ir
.gdbarch
= gdbarch
;
3935 if (record_debug
> 1)
3936 fprintf_unfiltered (gdb_stdlog
, "Process record: i386_process_record "
3938 paddress (gdbarch
, ir
.addr
));
3943 if (target_read_memory (ir
.addr
, &opcode8
, 1))
3946 printf_unfiltered (_("Process record: error reading memory at "
3947 "addr %s len = 1.\n"),
3948 paddress (gdbarch
, ir
.addr
));
3952 switch (opcode8
) /* Instruction prefixes */
3954 case REPE_PREFIX_OPCODE
:
3955 prefixes
|= PREFIX_REPZ
;
3957 case REPNE_PREFIX_OPCODE
:
3958 prefixes
|= PREFIX_REPNZ
;
3960 case LOCK_PREFIX_OPCODE
:
3961 prefixes
|= PREFIX_LOCK
;
3963 case CS_PREFIX_OPCODE
:
3964 ir
.override
= X86_RECORD_CS_REGNUM
;
3966 case SS_PREFIX_OPCODE
:
3967 ir
.override
= X86_RECORD_SS_REGNUM
;
3969 case DS_PREFIX_OPCODE
:
3970 ir
.override
= X86_RECORD_DS_REGNUM
;
3972 case ES_PREFIX_OPCODE
:
3973 ir
.override
= X86_RECORD_ES_REGNUM
;
3975 case FS_PREFIX_OPCODE
:
3976 ir
.override
= X86_RECORD_FS_REGNUM
;
3978 case GS_PREFIX_OPCODE
:
3979 ir
.override
= X86_RECORD_GS_REGNUM
;
3981 case DATA_PREFIX_OPCODE
:
3982 prefixes
|= PREFIX_DATA
;
3984 case ADDR_PREFIX_OPCODE
:
3985 prefixes
|= PREFIX_ADDR
;
3987 case 0x40: /* i386 inc %eax */
3988 case 0x41: /* i386 inc %ecx */
3989 case 0x42: /* i386 inc %edx */
3990 case 0x43: /* i386 inc %ebx */
3991 case 0x44: /* i386 inc %esp */
3992 case 0x45: /* i386 inc %ebp */
3993 case 0x46: /* i386 inc %esi */
3994 case 0x47: /* i386 inc %edi */
3995 case 0x48: /* i386 dec %eax */
3996 case 0x49: /* i386 dec %ecx */
3997 case 0x4a: /* i386 dec %edx */
3998 case 0x4b: /* i386 dec %ebx */
3999 case 0x4c: /* i386 dec %esp */
4000 case 0x4d: /* i386 dec %ebp */
4001 case 0x4e: /* i386 dec %esi */
4002 case 0x4f: /* i386 dec %edi */
4003 if (ir
.regmap
[X86_RECORD_R8_REGNUM
]) /* 64 bit target */
4007 rex_w
= (opcode8
>> 3) & 1;
4008 rex_r
= (opcode8
& 0x4) << 1;
4009 ir
.rex_x
= (opcode8
& 0x2) << 2;
4010 ir
.rex_b
= (opcode8
& 0x1) << 3;
4012 else /* 32 bit target */
4021 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && rex_w
== 1)
4027 if (prefixes
& PREFIX_DATA
)
4030 if (prefixes
& PREFIX_ADDR
)
4032 else if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4035 /* Now check op code. */
4036 opcode
= (uint32_t) opcode8
;
4041 if (target_read_memory (ir
.addr
, &opcode8
, 1))
4044 printf_unfiltered (_("Process record: error reading memory at "
4045 "addr %s len = 1.\n"),
4046 paddress (gdbarch
, ir
.addr
));
4050 opcode
= (uint32_t) opcode8
| 0x0f00;
4054 case 0x00: /* arith & logic */
4102 if (((opcode
>> 3) & 7) != OP_CMPL
)
4104 if ((opcode
& 1) == 0)
4107 ir
.ot
= ir
.dflag
+ OT_WORD
;
4109 switch ((opcode
>> 1) & 3)
4111 case 0: /* OP Ev, Gv */
4112 if (i386_record_modrm (&ir
))
4116 if (i386_record_lea_modrm (&ir
))
4122 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4124 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4127 case 1: /* OP Gv, Ev */
4128 if (i386_record_modrm (&ir
))
4131 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4133 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4135 case 2: /* OP A, Iv */
4136 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4140 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4143 case 0x80: /* GRP1 */
4147 if (i386_record_modrm (&ir
))
4150 if (ir
.reg
!= OP_CMPL
)
4152 if ((opcode
& 1) == 0)
4155 ir
.ot
= ir
.dflag
+ OT_WORD
;
4162 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
4163 if (i386_record_lea_modrm (&ir
))
4167 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
4169 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4172 case 0x40: /* inc */
4181 case 0x48: /* dec */
4190 I386_RECORD_ARCH_LIST_ADD_REG (opcode
& 7);
4191 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4194 case 0xf6: /* GRP3 */
4196 if ((opcode
& 1) == 0)
4199 ir
.ot
= ir
.dflag
+ OT_WORD
;
4200 if (i386_record_modrm (&ir
))
4203 if (ir
.mod
!= 3 && ir
.reg
== 0)
4204 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
4209 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4215 if (i386_record_lea_modrm (&ir
))
4221 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4223 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4225 if (ir
.reg
== 3) /* neg */
4226 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4232 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4233 if (ir
.ot
!= OT_BYTE
)
4234 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
4235 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4239 opcode
= opcode
<< 8 | ir
.modrm
;
4245 case 0xfe: /* GRP4 */
4246 case 0xff: /* GRP5 */
4247 if (i386_record_modrm (&ir
))
4249 if (ir
.reg
>= 2 && opcode
== 0xfe)
4252 opcode
= opcode
<< 8 | ir
.modrm
;
4259 if ((opcode
& 1) == 0)
4262 ir
.ot
= ir
.dflag
+ OT_WORD
;
4265 if (i386_record_lea_modrm (&ir
))
4271 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4273 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4275 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4278 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4280 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4282 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4285 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
4286 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4288 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4292 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4295 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4297 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4302 opcode
= opcode
<< 8 | ir
.modrm
;
4308 case 0x84: /* test */
4312 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4315 case 0x98: /* CWDE/CBW */
4316 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4319 case 0x99: /* CDQ/CWD */
4320 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4321 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
4324 case 0x0faf: /* imul */
4327 ir
.ot
= ir
.dflag
+ OT_WORD
;
4328 if (i386_record_modrm (&ir
))
4331 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
4332 else if (opcode
== 0x6b)
4335 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4337 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4338 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4341 case 0x0fc0: /* xadd */
4343 if ((opcode
& 1) == 0)
4346 ir
.ot
= ir
.dflag
+ OT_WORD
;
4347 if (i386_record_modrm (&ir
))
4352 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4354 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4355 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4357 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4361 if (i386_record_lea_modrm (&ir
))
4363 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4365 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4367 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4370 case 0x0fb0: /* cmpxchg */
4372 if ((opcode
& 1) == 0)
4375 ir
.ot
= ir
.dflag
+ OT_WORD
;
4376 if (i386_record_modrm (&ir
))
4381 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4382 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4384 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4388 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4389 if (i386_record_lea_modrm (&ir
))
4392 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4395 case 0x0fc7: /* cmpxchg8b */
4396 if (i386_record_modrm (&ir
))
4401 opcode
= opcode
<< 8 | ir
.modrm
;
4404 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4405 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
4406 if (i386_record_lea_modrm (&ir
))
4408 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4411 case 0x50: /* push */
4421 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4423 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4427 case 0x06: /* push es */
4428 case 0x0e: /* push cs */
4429 case 0x16: /* push ss */
4430 case 0x1e: /* push ds */
4431 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4436 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4440 case 0x0fa0: /* push fs */
4441 case 0x0fa8: /* push gs */
4442 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4447 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4451 case 0x60: /* pusha */
4452 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4457 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 4)))
4461 case 0x58: /* pop */
4469 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4470 I386_RECORD_ARCH_LIST_ADD_REG ((opcode
& 0x7) | ir
.rex_b
);
4473 case 0x61: /* popa */
4474 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4479 for (regnum
= X86_RECORD_REAX_REGNUM
;
4480 regnum
<= X86_RECORD_REDI_REGNUM
;
4482 I386_RECORD_ARCH_LIST_ADD_REG (regnum
);
4485 case 0x8f: /* pop */
4486 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4487 ir
.ot
= ir
.dflag
? OT_QUAD
: OT_WORD
;
4489 ir
.ot
= ir
.dflag
+ OT_WORD
;
4490 if (i386_record_modrm (&ir
))
4493 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
4496 ir
.popl_esp_hack
= 1 << ir
.ot
;
4497 if (i386_record_lea_modrm (&ir
))
4500 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4503 case 0xc8: /* enter */
4504 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
4505 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4507 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4511 case 0xc9: /* leave */
4512 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4513 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
4516 case 0x07: /* pop es */
4517 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4522 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4523 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM
);
4524 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4527 case 0x17: /* pop ss */
4528 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4533 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4534 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM
);
4535 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4538 case 0x1f: /* pop ds */
4539 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4544 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4545 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM
);
4546 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4549 case 0x0fa1: /* pop fs */
4550 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4551 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM
);
4552 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4555 case 0x0fa9: /* pop gs */
4556 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4557 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM
);
4558 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4561 case 0x88: /* mov */
4565 if ((opcode
& 1) == 0)
4568 ir
.ot
= ir
.dflag
+ OT_WORD
;
4570 if (i386_record_modrm (&ir
))
4575 if (opcode
== 0xc6 || opcode
== 0xc7)
4576 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
4577 if (i386_record_lea_modrm (&ir
))
4582 if (opcode
== 0xc6 || opcode
== 0xc7)
4584 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4586 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4590 case 0x8a: /* mov */
4592 if ((opcode
& 1) == 0)
4595 ir
.ot
= ir
.dflag
+ OT_WORD
;
4596 if (i386_record_modrm (&ir
))
4599 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4601 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4604 case 0x8c: /* mov seg */
4605 if (i386_record_modrm (&ir
))
4610 opcode
= opcode
<< 8 | ir
.modrm
;
4615 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4619 if (i386_record_lea_modrm (&ir
))
4624 case 0x8e: /* mov seg */
4625 if (i386_record_modrm (&ir
))
4630 regnum
= X86_RECORD_ES_REGNUM
;
4633 regnum
= X86_RECORD_SS_REGNUM
;
4636 regnum
= X86_RECORD_DS_REGNUM
;
4639 regnum
= X86_RECORD_FS_REGNUM
;
4642 regnum
= X86_RECORD_GS_REGNUM
;
4646 opcode
= opcode
<< 8 | ir
.modrm
;
4650 I386_RECORD_ARCH_LIST_ADD_REG (regnum
);
4651 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4654 case 0x0fb6: /* movzbS */
4655 case 0x0fb7: /* movzwS */
4656 case 0x0fbe: /* movsbS */
4657 case 0x0fbf: /* movswS */
4658 if (i386_record_modrm (&ir
))
4660 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
4663 case 0x8d: /* lea */
4664 if (i386_record_modrm (&ir
))
4669 opcode
= opcode
<< 8 | ir
.modrm
;
4674 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4676 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4679 case 0xa0: /* mov EAX */
4682 case 0xd7: /* xlat */
4683 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4686 case 0xa2: /* mov EAX */
4688 if (ir
.override
>= 0)
4690 if (record_memory_query
)
4694 target_terminal_ours ();
4696 Process record ignores the memory change of instruction at address %s\n\
4697 because it can't get the value of the segment register.\n\
4698 Do you want to stop the program?"),
4699 paddress (gdbarch
, ir
.orig_addr
));
4700 target_terminal_inferior ();
4707 if ((opcode
& 1) == 0)
4710 ir
.ot
= ir
.dflag
+ OT_WORD
;
4713 if (target_read_memory (ir
.addr
, buf
, 8))
4716 printf_unfiltered (_("Process record: error reading "
4717 "memory at addr 0x%s len = 8.\n"),
4718 paddress (gdbarch
, ir
.addr
));
4722 addr
= extract_unsigned_integer (buf
, 8, byte_order
);
4726 if (target_read_memory (ir
.addr
, buf
, 4))
4729 printf_unfiltered (_("Process record: error reading "
4730 "memory at addr 0x%s len = 4.\n"),
4731 paddress (gdbarch
, ir
.addr
));
4735 addr
= extract_unsigned_integer (buf
, 4, byte_order
);
4739 if (target_read_memory (ir
.addr
, buf
, 2))
4742 printf_unfiltered (_("Process record: error reading "
4743 "memory at addr 0x%s len = 2.\n"),
4744 paddress (gdbarch
, ir
.addr
));
4748 addr
= extract_unsigned_integer (buf
, 2, byte_order
);
4750 if (record_arch_list_add_mem (addr
, 1 << ir
.ot
))
4755 case 0xb0: /* mov R, Ib */
4763 I386_RECORD_ARCH_LIST_ADD_REG ((ir
.regmap
[X86_RECORD_R8_REGNUM
])
4764 ? ((opcode
& 0x7) | ir
.rex_b
)
4765 : ((opcode
& 0x7) & 0x3));
4768 case 0xb8: /* mov R, Iv */
4776 I386_RECORD_ARCH_LIST_ADD_REG ((opcode
& 0x7) | ir
.rex_b
);
4779 case 0x91: /* xchg R, EAX */
4786 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4787 I386_RECORD_ARCH_LIST_ADD_REG (opcode
& 0x7);
4790 case 0x86: /* xchg Ev, Gv */
4792 if ((opcode
& 1) == 0)
4795 ir
.ot
= ir
.dflag
+ OT_WORD
;
4796 if (i386_record_modrm (&ir
))
4801 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4803 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4807 if (i386_record_lea_modrm (&ir
))
4811 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4813 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4816 case 0xc4: /* les Gv */
4817 case 0xc5: /* lds Gv */
4818 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4824 case 0x0fb2: /* lss Gv */
4825 case 0x0fb4: /* lfs Gv */
4826 case 0x0fb5: /* lgs Gv */
4827 if (i386_record_modrm (&ir
))
4835 opcode
= opcode
<< 8 | ir
.modrm
;
4840 case 0xc4: /* les Gv */
4841 regnum
= X86_RECORD_ES_REGNUM
;
4843 case 0xc5: /* lds Gv */
4844 regnum
= X86_RECORD_DS_REGNUM
;
4846 case 0x0fb2: /* lss Gv */
4847 regnum
= X86_RECORD_SS_REGNUM
;
4849 case 0x0fb4: /* lfs Gv */
4850 regnum
= X86_RECORD_FS_REGNUM
;
4852 case 0x0fb5: /* lgs Gv */
4853 regnum
= X86_RECORD_GS_REGNUM
;
4856 I386_RECORD_ARCH_LIST_ADD_REG (regnum
);
4857 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
4858 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4861 case 0xc0: /* shifts */
4867 if ((opcode
& 1) == 0)
4870 ir
.ot
= ir
.dflag
+ OT_WORD
;
4871 if (i386_record_modrm (&ir
))
4873 if (ir
.mod
!= 3 && (opcode
== 0xd2 || opcode
== 0xd3))
4875 if (i386_record_lea_modrm (&ir
))
4881 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4883 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4885 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4892 if (i386_record_modrm (&ir
))
4896 if (record_arch_list_add_reg (ir
.regcache
, ir
.rm
))
4901 if (i386_record_lea_modrm (&ir
))
4906 case 0xd8: /* Floats. */
4914 if (i386_record_modrm (&ir
))
4916 ir
.reg
|= ((opcode
& 7) << 3);
4922 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
4930 /* For fcom, ficom nothing to do. */
4936 /* For fcomp, ficomp pop FPU stack, store all. */
4937 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
4964 /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul,
4965 fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension
4966 of code, always affects st(0) register. */
4967 if (i386_record_floats (gdbarch
, &ir
, I387_ST0_REGNUM (tdep
)))
4991 /* Handling fld, fild. */
4992 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
4996 switch (ir
.reg
>> 4)
4999 if (record_arch_list_add_mem (addr64
, 4))
5003 if (record_arch_list_add_mem (addr64
, 8))
5009 if (record_arch_list_add_mem (addr64
, 2))
5015 switch (ir
.reg
>> 4)
5018 if (record_arch_list_add_mem (addr64
, 4))
5020 if (3 == (ir
.reg
& 7))
5022 /* For fstp m32fp. */
5023 if (i386_record_floats (gdbarch
, &ir
,
5024 I386_SAVE_FPU_REGS
))
5029 if (record_arch_list_add_mem (addr64
, 4))
5031 if ((3 == (ir
.reg
& 7))
5032 || (5 == (ir
.reg
& 7))
5033 || (7 == (ir
.reg
& 7)))
5035 /* For fstp insn. */
5036 if (i386_record_floats (gdbarch
, &ir
,
5037 I386_SAVE_FPU_REGS
))
5042 if (record_arch_list_add_mem (addr64
, 8))
5044 if (3 == (ir
.reg
& 7))
5046 /* For fstp m64fp. */
5047 if (i386_record_floats (gdbarch
, &ir
,
5048 I386_SAVE_FPU_REGS
))
5053 if ((3 <= (ir
.reg
& 7)) && (6 <= (ir
.reg
& 7)))
5055 /* For fistp, fbld, fild, fbstp. */
5056 if (i386_record_floats (gdbarch
, &ir
,
5057 I386_SAVE_FPU_REGS
))
5062 if (record_arch_list_add_mem (addr64
, 2))
5071 if (i386_record_floats (gdbarch
, &ir
,
5072 I386_SAVE_FPU_ENV_REG_STACK
))
5077 if (i386_record_floats (gdbarch
, &ir
, I387_FCTRL_REGNUM (tdep
)))
5082 if (i386_record_floats (gdbarch
, &ir
,
5083 I386_SAVE_FPU_ENV_REG_STACK
))
5089 if (record_arch_list_add_mem (addr64
, 28))
5094 if (record_arch_list_add_mem (addr64
, 14))
5100 if (record_arch_list_add_mem (addr64
, 2))
5102 /* Insn fstp, fbstp. */
5103 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5108 if (record_arch_list_add_mem (addr64
, 10))
5114 if (record_arch_list_add_mem (addr64
, 28))
5120 if (record_arch_list_add_mem (addr64
, 14))
5124 if (record_arch_list_add_mem (addr64
, 80))
5127 if (i386_record_floats (gdbarch
, &ir
,
5128 I386_SAVE_FPU_ENV_REG_STACK
))
5132 if (record_arch_list_add_mem (addr64
, 8))
5135 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5140 opcode
= opcode
<< 8 | ir
.modrm
;
5145 /* Opcode is an extension of modR/M byte. */
5151 if (i386_record_floats (gdbarch
, &ir
, I387_ST0_REGNUM (tdep
)))
5155 if (0x0c == (ir
.modrm
>> 4))
5157 if ((ir
.modrm
& 0x0f) <= 7)
5159 if (i386_record_floats (gdbarch
, &ir
,
5160 I386_SAVE_FPU_REGS
))
5165 if (i386_record_floats (gdbarch
, &ir
,
5166 I387_ST0_REGNUM (tdep
)))
5168 /* If only st(0) is changing, then we have already
5170 if ((ir
.modrm
& 0x0f) - 0x08)
5172 if (i386_record_floats (gdbarch
, &ir
,
5173 I387_ST0_REGNUM (tdep
) +
5174 ((ir
.modrm
& 0x0f) - 0x08)))
5192 if (i386_record_floats (gdbarch
, &ir
,
5193 I387_ST0_REGNUM (tdep
)))
5211 if (i386_record_floats (gdbarch
, &ir
,
5212 I386_SAVE_FPU_REGS
))
5216 if (i386_record_floats (gdbarch
, &ir
,
5217 I387_ST0_REGNUM (tdep
)))
5219 if (i386_record_floats (gdbarch
, &ir
,
5220 I387_ST0_REGNUM (tdep
) + 1))
5227 if (0xe9 == ir
.modrm
)
5229 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5232 else if ((0x0c == ir
.modrm
>> 4) || (0x0d == ir
.modrm
>> 4))
5234 if (i386_record_floats (gdbarch
, &ir
,
5235 I387_ST0_REGNUM (tdep
)))
5237 if (((ir
.modrm
& 0x0f) > 0) && ((ir
.modrm
& 0x0f) <= 7))
5239 if (i386_record_floats (gdbarch
, &ir
,
5240 I387_ST0_REGNUM (tdep
) +
5244 else if ((ir
.modrm
& 0x0f) - 0x08)
5246 if (i386_record_floats (gdbarch
, &ir
,
5247 I387_ST0_REGNUM (tdep
) +
5248 ((ir
.modrm
& 0x0f) - 0x08)))
5254 if (0xe3 == ir
.modrm
)
5256 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_ENV
))
5259 else if ((0x0c == ir
.modrm
>> 4) || (0x0d == ir
.modrm
>> 4))
5261 if (i386_record_floats (gdbarch
, &ir
,
5262 I387_ST0_REGNUM (tdep
)))
5264 if (((ir
.modrm
& 0x0f) > 0) && ((ir
.modrm
& 0x0f) <= 7))
5266 if (i386_record_floats (gdbarch
, &ir
,
5267 I387_ST0_REGNUM (tdep
) +
5271 else if ((ir
.modrm
& 0x0f) - 0x08)
5273 if (i386_record_floats (gdbarch
, &ir
,
5274 I387_ST0_REGNUM (tdep
) +
5275 ((ir
.modrm
& 0x0f) - 0x08)))
5281 if ((0x0c == ir
.modrm
>> 4)
5282 || (0x0d == ir
.modrm
>> 4)
5283 || (0x0f == ir
.modrm
>> 4))
5285 if ((ir
.modrm
& 0x0f) <= 7)
5287 if (i386_record_floats (gdbarch
, &ir
,
5288 I387_ST0_REGNUM (tdep
) +
5294 if (i386_record_floats (gdbarch
, &ir
,
5295 I387_ST0_REGNUM (tdep
) +
5296 ((ir
.modrm
& 0x0f) - 0x08)))
5302 if (0x0c == ir
.modrm
>> 4)
5304 if (i386_record_floats (gdbarch
, &ir
,
5305 I387_FTAG_REGNUM (tdep
)))
5308 else if ((0x0d == ir
.modrm
>> 4) || (0x0e == ir
.modrm
>> 4))
5310 if ((ir
.modrm
& 0x0f) <= 7)
5312 if (i386_record_floats (gdbarch
, &ir
,
5313 I387_ST0_REGNUM (tdep
) +
5319 if (i386_record_floats (gdbarch
, &ir
,
5320 I386_SAVE_FPU_REGS
))
5326 if ((0x0c == ir
.modrm
>> 4)
5327 || (0x0e == ir
.modrm
>> 4)
5328 || (0x0f == ir
.modrm
>> 4)
5329 || (0xd9 == ir
.modrm
))
5331 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5336 if (0xe0 == ir
.modrm
)
5338 if (record_arch_list_add_reg (ir
.regcache
, I386_EAX_REGNUM
))
5341 else if ((0x0f == ir
.modrm
>> 4) || (0x0e == ir
.modrm
>> 4))
5343 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
5351 case 0xa4: /* movsS */
5353 case 0xaa: /* stosS */
5355 case 0x6c: /* insS */
5357 regcache_raw_read_unsigned (ir
.regcache
,
5358 ir
.regmap
[X86_RECORD_RECX_REGNUM
],
5364 if ((opcode
& 1) == 0)
5367 ir
.ot
= ir
.dflag
+ OT_WORD
;
5368 regcache_raw_read_unsigned (ir
.regcache
,
5369 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
5372 regcache_raw_read_unsigned (ir
.regcache
,
5373 ir
.regmap
[X86_RECORD_ES_REGNUM
],
5375 regcache_raw_read_unsigned (ir
.regcache
,
5376 ir
.regmap
[X86_RECORD_DS_REGNUM
],
5378 if (ir
.aflag
&& (es
!= ds
))
5380 /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */
5381 if (record_memory_query
)
5385 target_terminal_ours ();
5387 Process record ignores the memory change of instruction at address %s\n\
5388 because it can't get the value of the segment register.\n\
5389 Do you want to stop the program?"),
5390 paddress (gdbarch
, ir
.orig_addr
));
5391 target_terminal_inferior ();
5398 if (record_arch_list_add_mem (addr
, 1 << ir
.ot
))
5402 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5403 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5404 if (opcode
== 0xa4 || opcode
== 0xa5)
5405 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
5406 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
5407 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5411 case 0xa6: /* cmpsS */
5413 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
5414 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
5415 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5416 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5417 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5420 case 0xac: /* lodsS */
5422 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5423 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
5424 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5425 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5426 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5429 case 0xae: /* scasS */
5431 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
5432 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5433 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5434 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5437 case 0x6e: /* outsS */
5439 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
5440 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
5441 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5442 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5445 case 0xe4: /* port I/O */
5449 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5450 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5460 case 0xc2: /* ret im */
5461 case 0xc3: /* ret */
5462 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5463 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5466 case 0xca: /* lret im */
5467 case 0xcb: /* lret */
5468 case 0xcf: /* iret */
5469 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
5470 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5471 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5474 case 0xe8: /* call im */
5475 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5477 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5481 case 0x9a: /* lcall im */
5482 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5487 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
5488 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5492 case 0xe9: /* jmp im */
5493 case 0xea: /* ljmp im */
5494 case 0xeb: /* jmp Jb */
5495 case 0x70: /* jcc Jb */
5511 case 0x0f80: /* jcc Jv */
5529 case 0x0f90: /* setcc Gv */
5545 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5547 if (i386_record_modrm (&ir
))
5550 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rex_b
? (ir
.rm
| ir
.rex_b
)
5554 if (i386_record_lea_modrm (&ir
))
5559 case 0x0f40: /* cmov Gv, Ev */
5575 if (i386_record_modrm (&ir
))
5578 if (ir
.dflag
== OT_BYTE
)
5580 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
5584 case 0x9c: /* pushf */
5585 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5586 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5588 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5592 case 0x9d: /* popf */
5593 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5594 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5597 case 0x9e: /* sahf */
5598 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5604 case 0xf5: /* cmc */
5605 case 0xf8: /* clc */
5606 case 0xf9: /* stc */
5607 case 0xfc: /* cld */
5608 case 0xfd: /* std */
5609 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5612 case 0x9f: /* lahf */
5613 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5618 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5619 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5622 /* bit operations */
5623 case 0x0fba: /* bt/bts/btr/btc Gv, im */
5624 ir
.ot
= ir
.dflag
+ OT_WORD
;
5625 if (i386_record_modrm (&ir
))
5630 opcode
= opcode
<< 8 | ir
.modrm
;
5636 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5639 if (i386_record_lea_modrm (&ir
))
5643 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5646 case 0x0fa3: /* bt Gv, Ev */
5647 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5650 case 0x0fab: /* bts */
5651 case 0x0fb3: /* btr */
5652 case 0x0fbb: /* btc */
5653 ir
.ot
= ir
.dflag
+ OT_WORD
;
5654 if (i386_record_modrm (&ir
))
5657 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5661 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
5663 regcache_raw_read_unsigned (ir
.regcache
,
5664 ir
.regmap
[ir
.reg
| rex_r
],
5669 addr64
+= ((int16_t) addr
>> 4) << 4;
5672 addr64
+= ((int32_t) addr
>> 5) << 5;
5675 addr64
+= ((int64_t) addr
>> 6) << 6;
5678 if (record_arch_list_add_mem (addr64
, 1 << ir
.ot
))
5680 if (i386_record_lea_modrm (&ir
))
5683 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5686 case 0x0fbc: /* bsf */
5687 case 0x0fbd: /* bsr */
5688 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
5689 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5693 case 0x27: /* daa */
5694 case 0x2f: /* das */
5695 case 0x37: /* aaa */
5696 case 0x3f: /* aas */
5697 case 0xd4: /* aam */
5698 case 0xd5: /* aad */
5699 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5704 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5705 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5709 case 0x90: /* nop */
5710 if (prefixes
& PREFIX_LOCK
)
5717 case 0x9b: /* fwait */
5718 if (target_read_memory (ir
.addr
, &opcode8
, 1))
5721 printf_unfiltered (_("Process record: error reading memory at "
5722 "addr 0x%s len = 1.\n"),
5723 paddress (gdbarch
, ir
.addr
));
5726 opcode
= (uint32_t) opcode8
;
5732 case 0xcc: /* int3 */
5733 printf_unfiltered (_("Process record does not support instruction "
5740 case 0xcd: /* int */
5744 if (target_read_memory (ir
.addr
, &interrupt
, 1))
5747 printf_unfiltered (_("Process record: error reading memory "
5748 "at addr %s len = 1.\n"),
5749 paddress (gdbarch
, ir
.addr
));
5753 if (interrupt
!= 0x80
5754 || tdep
->i386_intx80_record
== NULL
)
5756 printf_unfiltered (_("Process record does not support "
5757 "instruction int 0x%02x.\n"),
5762 ret
= tdep
->i386_intx80_record (ir
.regcache
);
5769 case 0xce: /* into */
5770 printf_unfiltered (_("Process record does not support "
5771 "instruction into.\n"));
5776 case 0xfa: /* cli */
5777 case 0xfb: /* sti */
5780 case 0x62: /* bound */
5781 printf_unfiltered (_("Process record does not support "
5782 "instruction bound.\n"));
5787 case 0x0fc8: /* bswap reg */
5795 I386_RECORD_ARCH_LIST_ADD_REG ((opcode
& 7) | ir
.rex_b
);
5798 case 0xd6: /* salc */
5799 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5804 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5805 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5808 case 0xe0: /* loopnz */
5809 case 0xe1: /* loopz */
5810 case 0xe2: /* loop */
5811 case 0xe3: /* jecxz */
5812 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5813 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5816 case 0x0f30: /* wrmsr */
5817 printf_unfiltered (_("Process record does not support "
5818 "instruction wrmsr.\n"));
5823 case 0x0f32: /* rdmsr */
5824 printf_unfiltered (_("Process record does not support "
5825 "instruction rdmsr.\n"));
5830 case 0x0f31: /* rdtsc */
5831 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5832 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5835 case 0x0f34: /* sysenter */
5838 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5843 if (tdep
->i386_sysenter_record
== NULL
)
5845 printf_unfiltered (_("Process record does not support "
5846 "instruction sysenter.\n"));
5850 ret
= tdep
->i386_sysenter_record (ir
.regcache
);
5856 case 0x0f35: /* sysexit */
5857 printf_unfiltered (_("Process record does not support "
5858 "instruction sysexit.\n"));
5863 case 0x0f05: /* syscall */
5866 if (tdep
->i386_syscall_record
== NULL
)
5868 printf_unfiltered (_("Process record does not support "
5869 "instruction syscall.\n"));
5873 ret
= tdep
->i386_syscall_record (ir
.regcache
);
5879 case 0x0f07: /* sysret */
5880 printf_unfiltered (_("Process record does not support "
5881 "instruction sysret.\n"));
5886 case 0x0fa2: /* cpuid */
5887 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5888 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5889 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5890 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM
);
5893 case 0xf4: /* hlt */
5894 printf_unfiltered (_("Process record does not support "
5895 "instruction hlt.\n"));
5901 if (i386_record_modrm (&ir
))
5908 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5912 if (i386_record_lea_modrm (&ir
))
5921 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5925 opcode
= opcode
<< 8 | ir
.modrm
;
5932 if (i386_record_modrm (&ir
))
5943 opcode
= opcode
<< 8 | ir
.modrm
;
5946 if (ir
.override
>= 0)
5948 if (record_memory_query
)
5952 target_terminal_ours ();
5954 Process record ignores the memory change of instruction at address %s\n\
5955 because it can't get the value of the segment register.\n\
5956 Do you want to stop the program?"),
5957 paddress (gdbarch
, ir
.orig_addr
));
5958 target_terminal_inferior ();
5965 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
5967 if (record_arch_list_add_mem (addr64
, 2))
5970 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5972 if (record_arch_list_add_mem (addr64
, 8))
5977 if (record_arch_list_add_mem (addr64
, 4))
5988 case 0: /* monitor */
5991 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5995 opcode
= opcode
<< 8 | ir
.modrm
;
6003 if (ir
.override
>= 0)
6005 if (record_memory_query
)
6009 target_terminal_ours ();
6011 Process record ignores the memory change of instruction at address %s\n\
6012 because it can't get the value of the segment register.\n\
6013 Do you want to stop the program?"),
6014 paddress (gdbarch
, ir
.orig_addr
));
6015 target_terminal_inferior ();
6024 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
6026 if (record_arch_list_add_mem (addr64
, 2))
6029 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6031 if (record_arch_list_add_mem (addr64
, 8))
6036 if (record_arch_list_add_mem (addr64
, 4))
6048 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6049 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
6053 else if (ir
.rm
== 1)
6060 opcode
= opcode
<< 8 | ir
.modrm
;
6067 if (record_arch_list_add_reg (ir
.regcache
, ir
.rm
| ir
.rex_b
))
6073 if (i386_record_lea_modrm (&ir
))
6076 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6079 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6081 case 7: /* invlpg */
6084 if (ir
.rm
== 0 && ir
.regmap
[X86_RECORD_R8_REGNUM
])
6085 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM
);
6089 opcode
= opcode
<< 8 | ir
.modrm
;
6094 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6098 opcode
= opcode
<< 8 | ir
.modrm
;
6104 case 0x0f08: /* invd */
6105 case 0x0f09: /* wbinvd */
6108 case 0x63: /* arpl */
6109 if (i386_record_modrm (&ir
))
6111 if (ir
.mod
== 3 || ir
.regmap
[X86_RECORD_R8_REGNUM
])
6113 I386_RECORD_ARCH_LIST_ADD_REG (ir
.regmap
[X86_RECORD_R8_REGNUM
]
6114 ? (ir
.reg
| rex_r
) : ir
.rm
);
6118 ir
.ot
= ir
.dflag
? OT_LONG
: OT_WORD
;
6119 if (i386_record_lea_modrm (&ir
))
6122 if (!ir
.regmap
[X86_RECORD_R8_REGNUM
])
6123 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6126 case 0x0f02: /* lar */
6127 case 0x0f03: /* lsl */
6128 if (i386_record_modrm (&ir
))
6130 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
6131 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6135 if (i386_record_modrm (&ir
))
6137 if (ir
.mod
== 3 && ir
.reg
== 3)
6140 opcode
= opcode
<< 8 | ir
.modrm
;
6152 /* nop (multi byte) */
6155 case 0x0f20: /* mov reg, crN */
6156 case 0x0f22: /* mov crN, reg */
6157 if (i386_record_modrm (&ir
))
6159 if ((ir
.modrm
& 0xc0) != 0xc0)
6162 opcode
= opcode
<< 8 | ir
.modrm
;
6173 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6175 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6179 opcode
= opcode
<< 8 | ir
.modrm
;
6185 case 0x0f21: /* mov reg, drN */
6186 case 0x0f23: /* mov drN, reg */
6187 if (i386_record_modrm (&ir
))
6189 if ((ir
.modrm
& 0xc0) != 0xc0 || ir
.reg
== 4
6190 || ir
.reg
== 5 || ir
.reg
>= 8)
6193 opcode
= opcode
<< 8 | ir
.modrm
;
6197 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6199 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6202 case 0x0f06: /* clts */
6203 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6206 /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */
6208 case 0x0f0d: /* 3DNow! prefetch */
6211 case 0x0f0e: /* 3DNow! femms */
6212 case 0x0f77: /* emms */
6213 if (i386_fpc_regnum_p (gdbarch
, I387_FTAG_REGNUM(tdep
)))
6215 record_arch_list_add_reg (ir
.regcache
, I387_FTAG_REGNUM(tdep
));
6218 case 0x0f0f: /* 3DNow! data */
6219 if (i386_record_modrm (&ir
))
6221 if (target_read_memory (ir
.addr
, &opcode8
, 1))
6223 printf_unfiltered (_("Process record: error reading memory at "
6224 "addr %s len = 1.\n"),
6225 paddress (gdbarch
, ir
.addr
));
6231 case 0x0c: /* 3DNow! pi2fw */
6232 case 0x0d: /* 3DNow! pi2fd */
6233 case 0x1c: /* 3DNow! pf2iw */
6234 case 0x1d: /* 3DNow! pf2id */
6235 case 0x8a: /* 3DNow! pfnacc */
6236 case 0x8e: /* 3DNow! pfpnacc */
6237 case 0x90: /* 3DNow! pfcmpge */
6238 case 0x94: /* 3DNow! pfmin */
6239 case 0x96: /* 3DNow! pfrcp */
6240 case 0x97: /* 3DNow! pfrsqrt */
6241 case 0x9a: /* 3DNow! pfsub */
6242 case 0x9e: /* 3DNow! pfadd */
6243 case 0xa0: /* 3DNow! pfcmpgt */
6244 case 0xa4: /* 3DNow! pfmax */
6245 case 0xa6: /* 3DNow! pfrcpit1 */
6246 case 0xa7: /* 3DNow! pfrsqit1 */
6247 case 0xaa: /* 3DNow! pfsubr */
6248 case 0xae: /* 3DNow! pfacc */
6249 case 0xb0: /* 3DNow! pfcmpeq */
6250 case 0xb4: /* 3DNow! pfmul */
6251 case 0xb6: /* 3DNow! pfrcpit2 */
6252 case 0xb7: /* 3DNow! pmulhrw */
6253 case 0xbb: /* 3DNow! pswapd */
6254 case 0xbf: /* 3DNow! pavgusb */
6255 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.reg
))
6256 goto no_support_3dnow_data
;
6257 record_arch_list_add_reg (ir
.regcache
, ir
.reg
);
6261 no_support_3dnow_data
:
6262 opcode
= (opcode
<< 8) | opcode8
;
6268 case 0x0faa: /* rsm */
6269 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6270 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6271 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6272 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
6273 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM
);
6274 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
6275 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
6276 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
6277 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
6281 if (i386_record_modrm (&ir
))
6285 case 0: /* fxsave */
6289 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6290 if (i386_record_lea_modrm_addr (&ir
, &tmpu64
))
6292 if (record_arch_list_add_mem (tmpu64
, 512))
6297 case 1: /* fxrstor */
6301 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6303 for (i
= I387_MM0_REGNUM (tdep
);
6304 i386_mmx_regnum_p (gdbarch
, i
); i
++)
6305 record_arch_list_add_reg (ir
.regcache
, i
);
6307 for (i
= I387_XMM0_REGNUM (tdep
);
6308 i386_xmm_regnum_p (gdbarch
, i
); i
++)
6309 record_arch_list_add_reg (ir
.regcache
, i
);
6311 if (i386_mxcsr_regnum_p (gdbarch
, I387_MXCSR_REGNUM(tdep
)))
6312 record_arch_list_add_reg (ir
.regcache
, I387_MXCSR_REGNUM(tdep
));
6314 for (i
= I387_ST0_REGNUM (tdep
);
6315 i386_fp_regnum_p (gdbarch
, i
); i
++)
6316 record_arch_list_add_reg (ir
.regcache
, i
);
6318 for (i
= I387_FCTRL_REGNUM (tdep
);
6319 i386_fpc_regnum_p (gdbarch
, i
); i
++)
6320 record_arch_list_add_reg (ir
.regcache
, i
);
6324 case 2: /* ldmxcsr */
6325 if (!i386_mxcsr_regnum_p (gdbarch
, I387_MXCSR_REGNUM(tdep
)))
6327 record_arch_list_add_reg (ir
.regcache
, I387_MXCSR_REGNUM(tdep
));
6330 case 3: /* stmxcsr */
6332 if (i386_record_lea_modrm (&ir
))
6336 case 5: /* lfence */
6337 case 6: /* mfence */
6338 case 7: /* sfence clflush */
6342 opcode
= (opcode
<< 8) | ir
.modrm
;
6348 case 0x0fc3: /* movnti */
6349 ir
.ot
= (ir
.dflag
== 2) ? OT_QUAD
: OT_LONG
;
6350 if (i386_record_modrm (&ir
))
6355 if (i386_record_lea_modrm (&ir
))
6359 /* Add prefix to opcode. */
6486 reswitch_prefix_add
:
6494 if (target_read_memory (ir
.addr
, &opcode8
, 1))
6496 printf_unfiltered (_("Process record: error reading memory at "
6497 "addr %s len = 1.\n"),
6498 paddress (gdbarch
, ir
.addr
));
6502 opcode
= (uint32_t) opcode8
| opcode
<< 8;
6503 goto reswitch_prefix_add
;
6506 case 0x0f10: /* movups */
6507 case 0x660f10: /* movupd */
6508 case 0xf30f10: /* movss */
6509 case 0xf20f10: /* movsd */
6510 case 0x0f12: /* movlps */
6511 case 0x660f12: /* movlpd */
6512 case 0xf30f12: /* movsldup */
6513 case 0xf20f12: /* movddup */
6514 case 0x0f14: /* unpcklps */
6515 case 0x660f14: /* unpcklpd */
6516 case 0x0f15: /* unpckhps */
6517 case 0x660f15: /* unpckhpd */
6518 case 0x0f16: /* movhps */
6519 case 0x660f16: /* movhpd */
6520 case 0xf30f16: /* movshdup */
6521 case 0x0f28: /* movaps */
6522 case 0x660f28: /* movapd */
6523 case 0x0f2a: /* cvtpi2ps */
6524 case 0x660f2a: /* cvtpi2pd */
6525 case 0xf30f2a: /* cvtsi2ss */
6526 case 0xf20f2a: /* cvtsi2sd */
6527 case 0x0f2c: /* cvttps2pi */
6528 case 0x660f2c: /* cvttpd2pi */
6529 case 0x0f2d: /* cvtps2pi */
6530 case 0x660f2d: /* cvtpd2pi */
6531 case 0x660f3800: /* pshufb */
6532 case 0x660f3801: /* phaddw */
6533 case 0x660f3802: /* phaddd */
6534 case 0x660f3803: /* phaddsw */
6535 case 0x660f3804: /* pmaddubsw */
6536 case 0x660f3805: /* phsubw */
6537 case 0x660f3806: /* phsubd */
6538 case 0x660f3807: /* phsubsw */
6539 case 0x660f3808: /* psignb */
6540 case 0x660f3809: /* psignw */
6541 case 0x660f380a: /* psignd */
6542 case 0x660f380b: /* pmulhrsw */
6543 case 0x660f3810: /* pblendvb */
6544 case 0x660f3814: /* blendvps */
6545 case 0x660f3815: /* blendvpd */
6546 case 0x660f381c: /* pabsb */
6547 case 0x660f381d: /* pabsw */
6548 case 0x660f381e: /* pabsd */
6549 case 0x660f3820: /* pmovsxbw */
6550 case 0x660f3821: /* pmovsxbd */
6551 case 0x660f3822: /* pmovsxbq */
6552 case 0x660f3823: /* pmovsxwd */
6553 case 0x660f3824: /* pmovsxwq */
6554 case 0x660f3825: /* pmovsxdq */
6555 case 0x660f3828: /* pmuldq */
6556 case 0x660f3829: /* pcmpeqq */
6557 case 0x660f382a: /* movntdqa */
6558 case 0x660f3a08: /* roundps */
6559 case 0x660f3a09: /* roundpd */
6560 case 0x660f3a0a: /* roundss */
6561 case 0x660f3a0b: /* roundsd */
6562 case 0x660f3a0c: /* blendps */
6563 case 0x660f3a0d: /* blendpd */
6564 case 0x660f3a0e: /* pblendw */
6565 case 0x660f3a0f: /* palignr */
6566 case 0x660f3a20: /* pinsrb */
6567 case 0x660f3a21: /* insertps */
6568 case 0x660f3a22: /* pinsrd pinsrq */
6569 case 0x660f3a40: /* dpps */
6570 case 0x660f3a41: /* dppd */
6571 case 0x660f3a42: /* mpsadbw */
6572 case 0x660f3a60: /* pcmpestrm */
6573 case 0x660f3a61: /* pcmpestri */
6574 case 0x660f3a62: /* pcmpistrm */
6575 case 0x660f3a63: /* pcmpistri */
6576 case 0x0f51: /* sqrtps */
6577 case 0x660f51: /* sqrtpd */
6578 case 0xf20f51: /* sqrtsd */
6579 case 0xf30f51: /* sqrtss */
6580 case 0x0f52: /* rsqrtps */
6581 case 0xf30f52: /* rsqrtss */
6582 case 0x0f53: /* rcpps */
6583 case 0xf30f53: /* rcpss */
6584 case 0x0f54: /* andps */
6585 case 0x660f54: /* andpd */
6586 case 0x0f55: /* andnps */
6587 case 0x660f55: /* andnpd */
6588 case 0x0f56: /* orps */
6589 case 0x660f56: /* orpd */
6590 case 0x0f57: /* xorps */
6591 case 0x660f57: /* xorpd */
6592 case 0x0f58: /* addps */
6593 case 0x660f58: /* addpd */
6594 case 0xf20f58: /* addsd */
6595 case 0xf30f58: /* addss */
6596 case 0x0f59: /* mulps */
6597 case 0x660f59: /* mulpd */
6598 case 0xf20f59: /* mulsd */
6599 case 0xf30f59: /* mulss */
6600 case 0x0f5a: /* cvtps2pd */
6601 case 0x660f5a: /* cvtpd2ps */
6602 case 0xf20f5a: /* cvtsd2ss */
6603 case 0xf30f5a: /* cvtss2sd */
6604 case 0x0f5b: /* cvtdq2ps */
6605 case 0x660f5b: /* cvtps2dq */
6606 case 0xf30f5b: /* cvttps2dq */
6607 case 0x0f5c: /* subps */
6608 case 0x660f5c: /* subpd */
6609 case 0xf20f5c: /* subsd */
6610 case 0xf30f5c: /* subss */
6611 case 0x0f5d: /* minps */
6612 case 0x660f5d: /* minpd */
6613 case 0xf20f5d: /* minsd */
6614 case 0xf30f5d: /* minss */
6615 case 0x0f5e: /* divps */
6616 case 0x660f5e: /* divpd */
6617 case 0xf20f5e: /* divsd */
6618 case 0xf30f5e: /* divss */
6619 case 0x0f5f: /* maxps */
6620 case 0x660f5f: /* maxpd */
6621 case 0xf20f5f: /* maxsd */
6622 case 0xf30f5f: /* maxss */
6623 case 0x660f60: /* punpcklbw */
6624 case 0x660f61: /* punpcklwd */
6625 case 0x660f62: /* punpckldq */
6626 case 0x660f63: /* packsswb */
6627 case 0x660f64: /* pcmpgtb */
6628 case 0x660f65: /* pcmpgtw */
6629 case 0x660f66: /* pcmpgtd */
6630 case 0x660f67: /* packuswb */
6631 case 0x660f68: /* punpckhbw */
6632 case 0x660f69: /* punpckhwd */
6633 case 0x660f6a: /* punpckhdq */
6634 case 0x660f6b: /* packssdw */
6635 case 0x660f6c: /* punpcklqdq */
6636 case 0x660f6d: /* punpckhqdq */
6637 case 0x660f6e: /* movd */
6638 case 0x660f6f: /* movdqa */
6639 case 0xf30f6f: /* movdqu */
6640 case 0x660f70: /* pshufd */
6641 case 0xf20f70: /* pshuflw */
6642 case 0xf30f70: /* pshufhw */
6643 case 0x660f74: /* pcmpeqb */
6644 case 0x660f75: /* pcmpeqw */
6645 case 0x660f76: /* pcmpeqd */
6646 case 0x660f7c: /* haddpd */
6647 case 0xf20f7c: /* haddps */
6648 case 0x660f7d: /* hsubpd */
6649 case 0xf20f7d: /* hsubps */
6650 case 0xf30f7e: /* movq */
6651 case 0x0fc2: /* cmpps */
6652 case 0x660fc2: /* cmppd */
6653 case 0xf20fc2: /* cmpsd */
6654 case 0xf30fc2: /* cmpss */
6655 case 0x660fc4: /* pinsrw */
6656 case 0x0fc6: /* shufps */
6657 case 0x660fc6: /* shufpd */
6658 case 0x660fd0: /* addsubpd */
6659 case 0xf20fd0: /* addsubps */
6660 case 0x660fd1: /* psrlw */
6661 case 0x660fd2: /* psrld */
6662 case 0x660fd3: /* psrlq */
6663 case 0x660fd4: /* paddq */
6664 case 0x660fd5: /* pmullw */
6665 case 0xf30fd6: /* movq2dq */
6666 case 0x660fd8: /* psubusb */
6667 case 0x660fd9: /* psubusw */
6668 case 0x660fda: /* pminub */
6669 case 0x660fdb: /* pand */
6670 case 0x660fdc: /* paddusb */
6671 case 0x660fdd: /* paddusw */
6672 case 0x660fde: /* pmaxub */
6673 case 0x660fdf: /* pandn */
6674 case 0x660fe0: /* pavgb */
6675 case 0x660fe1: /* psraw */
6676 case 0x660fe2: /* psrad */
6677 case 0x660fe3: /* pavgw */
6678 case 0x660fe4: /* pmulhuw */
6679 case 0x660fe5: /* pmulhw */
6680 case 0x660fe6: /* cvttpd2dq */
6681 case 0xf20fe6: /* cvtpd2dq */
6682 case 0xf30fe6: /* cvtdq2pd */
6683 case 0x660fe8: /* psubsb */
6684 case 0x660fe9: /* psubsw */
6685 case 0x660fea: /* pminsw */
6686 case 0x660feb: /* por */
6687 case 0x660fec: /* paddsb */
6688 case 0x660fed: /* paddsw */
6689 case 0x660fee: /* pmaxsw */
6690 case 0x660fef: /* pxor */
6691 case 0xf20ff0: /* lddqu */
6692 case 0x660ff1: /* psllw */
6693 case 0x660ff2: /* pslld */
6694 case 0x660ff3: /* psllq */
6695 case 0x660ff4: /* pmuludq */
6696 case 0x660ff5: /* pmaddwd */
6697 case 0x660ff6: /* psadbw */
6698 case 0x660ff8: /* psubb */
6699 case 0x660ff9: /* psubw */
6700 case 0x660ffa: /* psubd */
6701 case 0x660ffb: /* psubq */
6702 case 0x660ffc: /* paddb */
6703 case 0x660ffd: /* paddw */
6704 case 0x660ffe: /* paddd */
6705 if (i386_record_modrm (&ir
))
6708 if (!i386_xmm_regnum_p (gdbarch
, I387_XMM0_REGNUM (tdep
) + ir
.reg
))
6710 record_arch_list_add_reg (ir
.regcache
,
6711 I387_XMM0_REGNUM (tdep
) + ir
.reg
);
6712 if ((opcode
& 0xfffffffc) == 0x660f3a60)
6713 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6716 case 0x0f11: /* movups */
6717 case 0x660f11: /* movupd */
6718 case 0xf30f11: /* movss */
6719 case 0xf20f11: /* movsd */
6720 case 0x0f13: /* movlps */
6721 case 0x660f13: /* movlpd */
6722 case 0x0f17: /* movhps */
6723 case 0x660f17: /* movhpd */
6724 case 0x0f29: /* movaps */
6725 case 0x660f29: /* movapd */
6726 case 0x660f3a14: /* pextrb */
6727 case 0x660f3a15: /* pextrw */
6728 case 0x660f3a16: /* pextrd pextrq */
6729 case 0x660f3a17: /* extractps */
6730 case 0x660f7f: /* movdqa */
6731 case 0xf30f7f: /* movdqu */
6732 if (i386_record_modrm (&ir
))
6736 if (opcode
== 0x0f13 || opcode
== 0x660f13
6737 || opcode
== 0x0f17 || opcode
== 0x660f17)
6740 if (!i386_xmm_regnum_p (gdbarch
,
6741 I387_XMM0_REGNUM (tdep
) + ir
.rm
))
6743 record_arch_list_add_reg (ir
.regcache
,
6744 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
6766 if (i386_record_lea_modrm (&ir
))
6771 case 0x0f2b: /* movntps */
6772 case 0x660f2b: /* movntpd */
6773 case 0x0fe7: /* movntq */
6774 case 0x660fe7: /* movntdq */
6777 if (opcode
== 0x0fe7)
6781 if (i386_record_lea_modrm (&ir
))
6785 case 0xf30f2c: /* cvttss2si */
6786 case 0xf20f2c: /* cvttsd2si */
6787 case 0xf30f2d: /* cvtss2si */
6788 case 0xf20f2d: /* cvtsd2si */
6789 case 0xf20f38f0: /* crc32 */
6790 case 0xf20f38f1: /* crc32 */
6791 case 0x0f50: /* movmskps */
6792 case 0x660f50: /* movmskpd */
6793 case 0x0fc5: /* pextrw */
6794 case 0x660fc5: /* pextrw */
6795 case 0x0fd7: /* pmovmskb */
6796 case 0x660fd7: /* pmovmskb */
6797 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
6800 case 0x0f3800: /* pshufb */
6801 case 0x0f3801: /* phaddw */
6802 case 0x0f3802: /* phaddd */
6803 case 0x0f3803: /* phaddsw */
6804 case 0x0f3804: /* pmaddubsw */
6805 case 0x0f3805: /* phsubw */
6806 case 0x0f3806: /* phsubd */
6807 case 0x0f3807: /* phsubsw */
6808 case 0x0f3808: /* psignb */
6809 case 0x0f3809: /* psignw */
6810 case 0x0f380a: /* psignd */
6811 case 0x0f380b: /* pmulhrsw */
6812 case 0x0f381c: /* pabsb */
6813 case 0x0f381d: /* pabsw */
6814 case 0x0f381e: /* pabsd */
6815 case 0x0f382b: /* packusdw */
6816 case 0x0f3830: /* pmovzxbw */
6817 case 0x0f3831: /* pmovzxbd */
6818 case 0x0f3832: /* pmovzxbq */
6819 case 0x0f3833: /* pmovzxwd */
6820 case 0x0f3834: /* pmovzxwq */
6821 case 0x0f3835: /* pmovzxdq */
6822 case 0x0f3837: /* pcmpgtq */
6823 case 0x0f3838: /* pminsb */
6824 case 0x0f3839: /* pminsd */
6825 case 0x0f383a: /* pminuw */
6826 case 0x0f383b: /* pminud */
6827 case 0x0f383c: /* pmaxsb */
6828 case 0x0f383d: /* pmaxsd */
6829 case 0x0f383e: /* pmaxuw */
6830 case 0x0f383f: /* pmaxud */
6831 case 0x0f3840: /* pmulld */
6832 case 0x0f3841: /* phminposuw */
6833 case 0x0f3a0f: /* palignr */
6834 case 0x0f60: /* punpcklbw */
6835 case 0x0f61: /* punpcklwd */
6836 case 0x0f62: /* punpckldq */
6837 case 0x0f63: /* packsswb */
6838 case 0x0f64: /* pcmpgtb */
6839 case 0x0f65: /* pcmpgtw */
6840 case 0x0f66: /* pcmpgtd */
6841 case 0x0f67: /* packuswb */
6842 case 0x0f68: /* punpckhbw */
6843 case 0x0f69: /* punpckhwd */
6844 case 0x0f6a: /* punpckhdq */
6845 case 0x0f6b: /* packssdw */
6846 case 0x0f6e: /* movd */
6847 case 0x0f6f: /* movq */
6848 case 0x0f70: /* pshufw */
6849 case 0x0f74: /* pcmpeqb */
6850 case 0x0f75: /* pcmpeqw */
6851 case 0x0f76: /* pcmpeqd */
6852 case 0x0fc4: /* pinsrw */
6853 case 0x0fd1: /* psrlw */
6854 case 0x0fd2: /* psrld */
6855 case 0x0fd3: /* psrlq */
6856 case 0x0fd4: /* paddq */
6857 case 0x0fd5: /* pmullw */
6858 case 0xf20fd6: /* movdq2q */
6859 case 0x0fd8: /* psubusb */
6860 case 0x0fd9: /* psubusw */
6861 case 0x0fda: /* pminub */
6862 case 0x0fdb: /* pand */
6863 case 0x0fdc: /* paddusb */
6864 case 0x0fdd: /* paddusw */
6865 case 0x0fde: /* pmaxub */
6866 case 0x0fdf: /* pandn */
6867 case 0x0fe0: /* pavgb */
6868 case 0x0fe1: /* psraw */
6869 case 0x0fe2: /* psrad */
6870 case 0x0fe3: /* pavgw */
6871 case 0x0fe4: /* pmulhuw */
6872 case 0x0fe5: /* pmulhw */
6873 case 0x0fe8: /* psubsb */
6874 case 0x0fe9: /* psubsw */
6875 case 0x0fea: /* pminsw */
6876 case 0x0feb: /* por */
6877 case 0x0fec: /* paddsb */
6878 case 0x0fed: /* paddsw */
6879 case 0x0fee: /* pmaxsw */
6880 case 0x0fef: /* pxor */
6881 case 0x0ff1: /* psllw */
6882 case 0x0ff2: /* pslld */
6883 case 0x0ff3: /* psllq */
6884 case 0x0ff4: /* pmuludq */
6885 case 0x0ff5: /* pmaddwd */
6886 case 0x0ff6: /* psadbw */
6887 case 0x0ff8: /* psubb */
6888 case 0x0ff9: /* psubw */
6889 case 0x0ffa: /* psubd */
6890 case 0x0ffb: /* psubq */
6891 case 0x0ffc: /* paddb */
6892 case 0x0ffd: /* paddw */
6893 case 0x0ffe: /* paddd */
6894 if (i386_record_modrm (&ir
))
6896 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.reg
))
6898 record_arch_list_add_reg (ir
.regcache
,
6899 I387_MM0_REGNUM (tdep
) + ir
.reg
);
6902 case 0x0f71: /* psllw */
6903 case 0x0f72: /* pslld */
6904 case 0x0f73: /* psllq */
6905 if (i386_record_modrm (&ir
))
6907 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.rm
))
6909 record_arch_list_add_reg (ir
.regcache
,
6910 I387_MM0_REGNUM (tdep
) + ir
.rm
);
6913 case 0x660f71: /* psllw */
6914 case 0x660f72: /* pslld */
6915 case 0x660f73: /* psllq */
6916 if (i386_record_modrm (&ir
))
6919 if (!i386_xmm_regnum_p (gdbarch
, I387_XMM0_REGNUM (tdep
) + ir
.rm
))
6921 record_arch_list_add_reg (ir
.regcache
,
6922 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
6925 case 0x0f7e: /* movd */
6926 case 0x660f7e: /* movd */
6927 if (i386_record_modrm (&ir
))
6930 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6937 if (i386_record_lea_modrm (&ir
))
6942 case 0x0f7f: /* movq */
6943 if (i386_record_modrm (&ir
))
6947 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.rm
))
6949 record_arch_list_add_reg (ir
.regcache
,
6950 I387_MM0_REGNUM (tdep
) + ir
.rm
);
6955 if (i386_record_lea_modrm (&ir
))
6960 case 0xf30fb8: /* popcnt */
6961 if (i386_record_modrm (&ir
))
6963 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
6964 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6967 case 0x660fd6: /* movq */
6968 if (i386_record_modrm (&ir
))
6973 if (!i386_xmm_regnum_p (gdbarch
,
6974 I387_XMM0_REGNUM (tdep
) + ir
.rm
))
6976 record_arch_list_add_reg (ir
.regcache
,
6977 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
6982 if (i386_record_lea_modrm (&ir
))
6987 case 0x660f3817: /* ptest */
6988 case 0x0f2e: /* ucomiss */
6989 case 0x660f2e: /* ucomisd */
6990 case 0x0f2f: /* comiss */
6991 case 0x660f2f: /* comisd */
6992 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6995 case 0x0ff7: /* maskmovq */
6996 regcache_raw_read_unsigned (ir
.regcache
,
6997 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
6999 if (record_arch_list_add_mem (addr
, 64))
7003 case 0x660ff7: /* maskmovdqu */
7004 regcache_raw_read_unsigned (ir
.regcache
,
7005 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
7007 if (record_arch_list_add_mem (addr
, 128))
7022 /* In the future, maybe still need to deal with need_dasm. */
7023 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM
);
7024 if (record_arch_list_add_end ())
7030 printf_unfiltered (_("Process record does not support instruction 0x%02x "
7031 "at address %s.\n"),
7032 (unsigned int) (opcode
),
7033 paddress (gdbarch
, ir
.orig_addr
));
7037 static const int i386_record_regmap
[] =
7039 I386_EAX_REGNUM
, I386_ECX_REGNUM
, I386_EDX_REGNUM
, I386_EBX_REGNUM
,
7040 I386_ESP_REGNUM
, I386_EBP_REGNUM
, I386_ESI_REGNUM
, I386_EDI_REGNUM
,
7041 0, 0, 0, 0, 0, 0, 0, 0,
7042 I386_EIP_REGNUM
, I386_EFLAGS_REGNUM
, I386_CS_REGNUM
, I386_SS_REGNUM
,
7043 I386_DS_REGNUM
, I386_ES_REGNUM
, I386_FS_REGNUM
, I386_GS_REGNUM
7046 /* Check that the given address appears suitable for a fast
7047 tracepoint, which on x86 means that we need an instruction of at
7048 least 5 bytes, so that we can overwrite it with a 4-byte-offset
7049 jump and not have to worry about program jumps to an address in the
7050 middle of the tracepoint jump. Returns 1 if OK, and writes a size
7051 of instruction to replace, and 0 if not, plus an explanatory
7055 i386_fast_tracepoint_valid_at (struct gdbarch
*gdbarch
,
7056 CORE_ADDR addr
, int *isize
, char **msg
)
7059 static struct ui_file
*gdb_null
= NULL
;
7061 /* This is based on the target agent using a 4-byte relative jump.
7062 Alternate future possibilities include 8-byte offset for x86-84,
7063 or 3-byte jumps if the program has trampoline space close by. */
7066 /* Dummy file descriptor for the disassembler. */
7068 gdb_null
= ui_file_new ();
7070 /* Check for fit. */
7071 len
= gdb_print_insn (gdbarch
, addr
, gdb_null
, NULL
);
7074 /* Return a bit of target-specific detail to add to the caller's
7075 generic failure message. */
7077 *msg
= xstrprintf (_("; instruction is only %d bytes long, "
7078 "need at least %d bytes for the jump"),
7091 i386_validate_tdesc_p (struct gdbarch_tdep
*tdep
,
7092 struct tdesc_arch_data
*tdesc_data
)
7094 const struct target_desc
*tdesc
= tdep
->tdesc
;
7095 const struct tdesc_feature
*feature_core
;
7096 const struct tdesc_feature
*feature_sse
, *feature_avx
;
7097 int i
, num_regs
, valid_p
;
7099 if (! tdesc_has_registers (tdesc
))
7102 /* Get core registers. */
7103 feature_core
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.core");
7104 if (feature_core
== NULL
)
7107 /* Get SSE registers. */
7108 feature_sse
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.sse");
7110 /* Try AVX registers. */
7111 feature_avx
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx");
7115 /* The XCR0 bits. */
7118 /* AVX register description requires SSE register description. */
7122 tdep
->xcr0
= I386_XSTATE_AVX_MASK
;
7124 /* It may have been set by OSABI initialization function. */
7125 if (tdep
->num_ymm_regs
== 0)
7127 tdep
->ymmh_register_names
= i386_ymmh_names
;
7128 tdep
->num_ymm_regs
= 8;
7129 tdep
->ymm0h_regnum
= I386_YMM0H_REGNUM
;
7132 for (i
= 0; i
< tdep
->num_ymm_regs
; i
++)
7133 valid_p
&= tdesc_numbered_register (feature_avx
, tdesc_data
,
7134 tdep
->ymm0h_regnum
+ i
,
7135 tdep
->ymmh_register_names
[i
]);
7137 else if (feature_sse
)
7138 tdep
->xcr0
= I386_XSTATE_SSE_MASK
;
7141 tdep
->xcr0
= I386_XSTATE_X87_MASK
;
7142 tdep
->num_xmm_regs
= 0;
7145 num_regs
= tdep
->num_core_regs
;
7146 for (i
= 0; i
< num_regs
; i
++)
7147 valid_p
&= tdesc_numbered_register (feature_core
, tdesc_data
, i
,
7148 tdep
->register_names
[i
]);
7152 /* Need to include %mxcsr, so add one. */
7153 num_regs
+= tdep
->num_xmm_regs
+ 1;
7154 for (; i
< num_regs
; i
++)
7155 valid_p
&= tdesc_numbered_register (feature_sse
, tdesc_data
, i
,
7156 tdep
->register_names
[i
]);
7163 static struct gdbarch
*
7164 i386_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
7166 struct gdbarch_tdep
*tdep
;
7167 struct gdbarch
*gdbarch
;
7168 struct tdesc_arch_data
*tdesc_data
;
7169 const struct target_desc
*tdesc
;
7173 /* If there is already a candidate, use it. */
7174 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
7176 return arches
->gdbarch
;
7178 /* Allocate space for the new architecture. */
7179 tdep
= XCALLOC (1, struct gdbarch_tdep
);
7180 gdbarch
= gdbarch_alloc (&info
, tdep
);
7182 /* General-purpose registers. */
7183 tdep
->gregset
= NULL
;
7184 tdep
->gregset_reg_offset
= NULL
;
7185 tdep
->gregset_num_regs
= I386_NUM_GREGS
;
7186 tdep
->sizeof_gregset
= 0;
7188 /* Floating-point registers. */
7189 tdep
->fpregset
= NULL
;
7190 tdep
->sizeof_fpregset
= I387_SIZEOF_FSAVE
;
7192 tdep
->xstateregset
= NULL
;
7194 /* The default settings include the FPU registers, the MMX registers
7195 and the SSE registers. This can be overridden for a specific ABI
7196 by adjusting the members `st0_regnum', `mm0_regnum' and
7197 `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers
7198 will show up in the output of "info all-registers". */
7200 tdep
->st0_regnum
= I386_ST0_REGNUM
;
7202 /* I386_NUM_XREGS includes %mxcsr, so substract one. */
7203 tdep
->num_xmm_regs
= I386_NUM_XREGS
- 1;
7205 tdep
->jb_pc_offset
= -1;
7206 tdep
->struct_return
= pcc_struct_return
;
7207 tdep
->sigtramp_start
= 0;
7208 tdep
->sigtramp_end
= 0;
7209 tdep
->sigtramp_p
= i386_sigtramp_p
;
7210 tdep
->sigcontext_addr
= NULL
;
7211 tdep
->sc_reg_offset
= NULL
;
7212 tdep
->sc_pc_offset
= -1;
7213 tdep
->sc_sp_offset
= -1;
7215 tdep
->xsave_xcr0_offset
= -1;
7217 tdep
->record_regmap
= i386_record_regmap
;
7219 /* The format used for `long double' on almost all i386 targets is
7220 the i387 extended floating-point format. In fact, of all targets
7221 in the GCC 2.95 tree, only OSF/1 does it different, and insists
7222 on having a `long double' that's not `long' at all. */
7223 set_gdbarch_long_double_format (gdbarch
, floatformats_i387_ext
);
7225 /* Although the i387 extended floating-point has only 80 significant
7226 bits, a `long double' actually takes up 96, probably to enforce
7228 set_gdbarch_long_double_bit (gdbarch
, 96);
7230 /* Register numbers of various important registers. */
7231 set_gdbarch_sp_regnum (gdbarch
, I386_ESP_REGNUM
); /* %esp */
7232 set_gdbarch_pc_regnum (gdbarch
, I386_EIP_REGNUM
); /* %eip */
7233 set_gdbarch_ps_regnum (gdbarch
, I386_EFLAGS_REGNUM
); /* %eflags */
7234 set_gdbarch_fp0_regnum (gdbarch
, I386_ST0_REGNUM
); /* %st(0) */
7236 /* NOTE: kettenis/20040418: GCC does have two possible register
7237 numbering schemes on the i386: dbx and SVR4. These schemes
7238 differ in how they number %ebp, %esp, %eflags, and the
7239 floating-point registers, and are implemented by the arrays
7240 dbx_register_map[] and svr4_dbx_register_map in
7241 gcc/config/i386.c. GCC also defines a third numbering scheme in
7242 gcc/config/i386.c, which it designates as the "default" register
7243 map used in 64bit mode. This last register numbering scheme is
7244 implemented in dbx64_register_map, and is used for AMD64; see
7247 Currently, each GCC i386 target always uses the same register
7248 numbering scheme across all its supported debugging formats
7249 i.e. SDB (COFF), stabs and DWARF 2. This is because
7250 gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the
7251 DBX_REGISTER_NUMBER macro which is defined by each target's
7252 respective config header in a manner independent of the requested
7253 output debugging format.
7255 This does not match the arrangement below, which presumes that
7256 the SDB and stabs numbering schemes differ from the DWARF and
7257 DWARF 2 ones. The reason for this arrangement is that it is
7258 likely to get the numbering scheme for the target's
7259 default/native debug format right. For targets where GCC is the
7260 native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for
7261 targets where the native toolchain uses a different numbering
7262 scheme for a particular debug format (stabs-in-ELF on Solaris)
7263 the defaults below will have to be overridden, like
7264 i386_elf_init_abi() does. */
7266 /* Use the dbx register numbering scheme for stabs and COFF. */
7267 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
7268 set_gdbarch_sdb_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
7270 /* Use the SVR4 register numbering scheme for DWARF 2. */
7271 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
7273 /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to
7274 be in use on any of the supported i386 targets. */
7276 set_gdbarch_print_float_info (gdbarch
, i387_print_float_info
);
7278 set_gdbarch_get_longjmp_target (gdbarch
, i386_get_longjmp_target
);
7280 /* Call dummy code. */
7281 set_gdbarch_push_dummy_call (gdbarch
, i386_push_dummy_call
);
7283 set_gdbarch_convert_register_p (gdbarch
, i386_convert_register_p
);
7284 set_gdbarch_register_to_value (gdbarch
, i386_register_to_value
);
7285 set_gdbarch_value_to_register (gdbarch
, i386_value_to_register
);
7287 set_gdbarch_return_value (gdbarch
, i386_return_value
);
7289 set_gdbarch_skip_prologue (gdbarch
, i386_skip_prologue
);
7291 /* Stack grows downward. */
7292 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
7294 set_gdbarch_breakpoint_from_pc (gdbarch
, i386_breakpoint_from_pc
);
7295 set_gdbarch_decr_pc_after_break (gdbarch
, 1);
7296 set_gdbarch_max_insn_length (gdbarch
, I386_MAX_INSN_LEN
);
7298 set_gdbarch_frame_args_skip (gdbarch
, 8);
7300 set_gdbarch_print_insn (gdbarch
, i386_print_insn
);
7302 set_gdbarch_dummy_id (gdbarch
, i386_dummy_id
);
7304 set_gdbarch_unwind_pc (gdbarch
, i386_unwind_pc
);
7306 /* Add the i386 register groups. */
7307 i386_add_reggroups (gdbarch
);
7308 tdep
->register_reggroup_p
= i386_register_reggroup_p
;
7310 /* Helper for function argument information. */
7311 set_gdbarch_fetch_pointer_argument (gdbarch
, i386_fetch_pointer_argument
);
7313 /* Hook the function epilogue frame unwinder. This unwinder is
7314 appended to the list first, so that it supercedes the Dwarf
7315 unwinder in function epilogues (where the Dwarf unwinder
7316 currently fails). */
7317 frame_unwind_append_unwinder (gdbarch
, &i386_epilogue_frame_unwind
);
7319 /* Hook in the DWARF CFI frame unwinder. This unwinder is appended
7320 to the list before the prologue-based unwinders, so that Dwarf
7321 CFI info will be used if it is available. */
7322 dwarf2_append_unwinders (gdbarch
);
7324 frame_base_set_default (gdbarch
, &i386_frame_base
);
7326 /* Pseudo registers may be changed by amd64_init_abi. */
7327 set_gdbarch_pseudo_register_read (gdbarch
, i386_pseudo_register_read
);
7328 set_gdbarch_pseudo_register_write (gdbarch
, i386_pseudo_register_write
);
7330 set_tdesc_pseudo_register_type (gdbarch
, i386_pseudo_register_type
);
7331 set_tdesc_pseudo_register_name (gdbarch
, i386_pseudo_register_name
);
7333 /* Override the normal target description method to make the AVX
7334 upper halves anonymous. */
7335 set_gdbarch_register_name (gdbarch
, i386_register_name
);
7337 /* Even though the default ABI only includes general-purpose registers,
7338 floating-point registers and the SSE registers, we have to leave a
7339 gap for the upper AVX registers. */
7340 set_gdbarch_num_regs (gdbarch
, I386_AVX_NUM_REGS
);
7342 /* Get the x86 target description from INFO. */
7343 tdesc
= info
.target_desc
;
7344 if (! tdesc_has_registers (tdesc
))
7346 tdep
->tdesc
= tdesc
;
7348 tdep
->num_core_regs
= I386_NUM_GREGS
+ I387_NUM_REGS
;
7349 tdep
->register_names
= i386_register_names
;
7351 /* No upper YMM registers. */
7352 tdep
->ymmh_register_names
= NULL
;
7353 tdep
->ymm0h_regnum
= -1;
7355 tdep
->num_byte_regs
= 8;
7356 tdep
->num_word_regs
= 8;
7357 tdep
->num_dword_regs
= 0;
7358 tdep
->num_mmx_regs
= 8;
7359 tdep
->num_ymm_regs
= 0;
7361 tdesc_data
= tdesc_data_alloc ();
7363 set_gdbarch_relocate_instruction (gdbarch
, i386_relocate_instruction
);
7365 /* Hook in ABI-specific overrides, if they have been registered. */
7366 info
.tdep_info
= (void *) tdesc_data
;
7367 gdbarch_init_osabi (info
, gdbarch
);
7369 if (!i386_validate_tdesc_p (tdep
, tdesc_data
))
7371 tdesc_data_cleanup (tdesc_data
);
7373 gdbarch_free (gdbarch
);
7377 /* Wire in pseudo registers. Number of pseudo registers may be
7379 set_gdbarch_num_pseudo_regs (gdbarch
, (tdep
->num_byte_regs
7380 + tdep
->num_word_regs
7381 + tdep
->num_dword_regs
7382 + tdep
->num_mmx_regs
7383 + tdep
->num_ymm_regs
));
7385 /* Target description may be changed. */
7386 tdesc
= tdep
->tdesc
;
7388 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
7390 /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */
7391 set_gdbarch_register_reggroup_p (gdbarch
, tdep
->register_reggroup_p
);
7393 /* Make %al the first pseudo-register. */
7394 tdep
->al_regnum
= gdbarch_num_regs (gdbarch
);
7395 tdep
->ax_regnum
= tdep
->al_regnum
+ tdep
->num_byte_regs
;
7397 ymm0_regnum
= tdep
->ax_regnum
+ tdep
->num_word_regs
;
7398 if (tdep
->num_dword_regs
)
7400 /* Support dword pseudo-register if it hasn't been disabled. */
7401 tdep
->eax_regnum
= ymm0_regnum
;
7402 ymm0_regnum
+= tdep
->num_dword_regs
;
7405 tdep
->eax_regnum
= -1;
7407 mm0_regnum
= ymm0_regnum
;
7408 if (tdep
->num_ymm_regs
)
7410 /* Support YMM pseudo-register if it is available. */
7411 tdep
->ymm0_regnum
= ymm0_regnum
;
7412 mm0_regnum
+= tdep
->num_ymm_regs
;
7415 tdep
->ymm0_regnum
= -1;
7417 if (tdep
->num_mmx_regs
!= 0)
7419 /* Support MMX pseudo-register if MMX hasn't been disabled. */
7420 tdep
->mm0_regnum
= mm0_regnum
;
7423 tdep
->mm0_regnum
= -1;
7425 /* Hook in the legacy prologue-based unwinders last (fallback). */
7426 frame_unwind_append_unwinder (gdbarch
, &i386_stack_tramp_frame_unwind
);
7427 frame_unwind_append_unwinder (gdbarch
, &i386_sigtramp_frame_unwind
);
7428 frame_unwind_append_unwinder (gdbarch
, &i386_frame_unwind
);
7430 /* If we have a register mapping, enable the generic core file
7431 support, unless it has already been enabled. */
7432 if (tdep
->gregset_reg_offset
7433 && !gdbarch_regset_from_core_section_p (gdbarch
))
7434 set_gdbarch_regset_from_core_section (gdbarch
,
7435 i386_regset_from_core_section
);
7437 set_gdbarch_skip_permanent_breakpoint (gdbarch
,
7438 i386_skip_permanent_breakpoint
);
7440 set_gdbarch_fast_tracepoint_valid_at (gdbarch
,
7441 i386_fast_tracepoint_valid_at
);
7446 static enum gdb_osabi
7447 i386_coff_osabi_sniffer (bfd
*abfd
)
7449 if (strcmp (bfd_get_target (abfd
), "coff-go32-exe") == 0
7450 || strcmp (bfd_get_target (abfd
), "coff-go32") == 0)
7451 return GDB_OSABI_GO32
;
7453 return GDB_OSABI_UNKNOWN
;
7457 /* Provide a prototype to silence -Wmissing-prototypes. */
7458 void _initialize_i386_tdep (void);
7461 _initialize_i386_tdep (void)
7463 register_gdbarch_init (bfd_arch_i386
, i386_gdbarch_init
);
7465 /* Add the variable that controls the disassembly flavor. */
7466 add_setshow_enum_cmd ("disassembly-flavor", no_class
, valid_flavors
,
7467 &disassembly_flavor
, _("\
7468 Set the disassembly flavor."), _("\
7469 Show the disassembly flavor."), _("\
7470 The valid values are \"att\" and \"intel\", and the default value is \"att\"."),
7472 NULL
, /* FIXME: i18n: */
7473 &setlist
, &showlist
);
7475 /* Add the variable that controls the convention for returning
7477 add_setshow_enum_cmd ("struct-convention", no_class
, valid_conventions
,
7478 &struct_convention
, _("\
7479 Set the convention for returning small structs."), _("\
7480 Show the convention for returning small structs."), _("\
7481 Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\
7484 NULL
, /* FIXME: i18n: */
7485 &setlist
, &showlist
);
7487 gdbarch_register_osabi_sniffer (bfd_arch_i386
, bfd_target_coff_flavour
,
7488 i386_coff_osabi_sniffer
);
7490 gdbarch_register_osabi (bfd_arch_i386
, 0, GDB_OSABI_SVR4
,
7491 i386_svr4_init_abi
);
7492 gdbarch_register_osabi (bfd_arch_i386
, 0, GDB_OSABI_GO32
,
7493 i386_go32_init_abi
);
7495 /* Initialize the i386-specific register groups. */
7496 i386_init_reggroups ();
7498 /* Initialize the standard target descriptions. */
7499 initialize_tdesc_i386 ();
7500 initialize_tdesc_i386_mmx ();
7501 initialize_tdesc_i386_avx ();
7503 /* Tell remote stub that we support XML target description. */
7504 register_remote_support_xml ("i386");