projects / deliverable / binutils-gdb.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
cris: Check UNDEFWEAK_NO_DYNAMIC_RELOC
[deliverable/binutils-gdb.git] / gdb / i387-tdep.c
1 /* Intel 387 floating point stuff.
2
3 Copyright (C) 1988-2017 Free Software Foundation, Inc.
4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
19
20 #include "defs.h"
21 #include "doublest.h"
22 #include "frame.h"
23 #include "gdbcore.h"
24 #include "inferior.h"
25 #include "language.h"
26 #include "regcache.h"
27 #include "value.h"
28
29 #include "i386-tdep.h"
30 #include "i387-tdep.h"
31 #include "x86-xstate.h"
32
33 /* Print the floating point number specified by RAW. */
34
35 static void
36 print_i387_value (struct gdbarch *gdbarch,
37 const gdb_byte *raw, struct ui_file *file)
38 {
39 DOUBLEST value;
40
41 /* Using extract_typed_floating here might affect the representation
42 of certain numbers such as NaNs, even if GDB is running natively.
43 This is fine since our caller already detects such special
44 numbers and we print the hexadecimal representation anyway. */
45 value = extract_typed_floating (raw, i387_ext_type (gdbarch));
46
47 /* We try to print 19 digits. The last digit may or may not contain
48 garbage, but we'd better print one too many. We need enough room
49 to print the value, 1 position for the sign, 1 for the decimal
50 point, 19 for the digits and 6 for the exponent adds up to 27. */
51 #ifdef PRINTF_HAS_LONG_DOUBLE
52 fprintf_filtered (file, " %-+27.19Lg", (long double) value);
53 #else
54 fprintf_filtered (file, " %-+27.19g", (double) value);
55 #endif
56 }
57
58 /* Print the classification for the register contents RAW. */
59
60 static void
61 print_i387_ext (struct gdbarch *gdbarch,
62 const gdb_byte *raw, struct ui_file *file)
63 {
64 int sign;
65 int integer;
66 unsigned int exponent;
67 unsigned long fraction[2];
68
69 sign = raw[9] & 0x80;
70 integer = raw[7] & 0x80;
71 exponent = (((raw[9] & 0x7f) << 8) | raw[8]);
72 fraction[0] = ((raw[3] << 24) | (raw[2] << 16) | (raw[1] << 8) | raw[0]);
73 fraction[1] = (((raw[7] & 0x7f) << 24) | (raw[6] << 16)
74 | (raw[5] << 8) | raw[4]);
75
76 if (exponent == 0x7fff && integer)
77 {
78 if (fraction[0] == 0x00000000 && fraction[1] == 0x00000000)
79 /* Infinity. */
80 fprintf_filtered (file, " %cInf", (sign ? '-' : '+'));
81 else if (sign && fraction[0] == 0x00000000 && fraction[1] == 0x40000000)
82 /* Real Indefinite (QNaN). */
83 fputs_unfiltered (" Real Indefinite (QNaN)", file);
84 else if (fraction[1] & 0x40000000)
85 /* QNaN. */
86 fputs_filtered (" QNaN", file);
87 else
88 /* SNaN. */
89 fputs_filtered (" SNaN", file);
90 }
91 else if (exponent < 0x7fff && exponent > 0x0000 && integer)
92 /* Normal. */
93 print_i387_value (gdbarch, raw, file);
94 else if (exponent == 0x0000)
95 {
96 /* Denormal or zero. */
97 print_i387_value (gdbarch, raw, file);
98
99 if (integer)
100 /* Pseudo-denormal. */
101 fputs_filtered (" Pseudo-denormal", file);
102 else if (fraction[0] || fraction[1])
103 /* Denormal. */
104 fputs_filtered (" Denormal", file);
105 }
106 else
107 /* Unsupported. */
108 fputs_filtered (" Unsupported", file);
109 }
110
111 /* Print the status word STATUS. If STATUS_P is false, then STATUS
112 was unavailable. */
113
114 static void
115 print_i387_status_word (int status_p,
116 unsigned int status, struct ui_file *file)
117 {
118 fprintf_filtered (file, "Status Word: ");
119 if (!status_p)
120 {
121 fprintf_filtered (file, "%s\n", _("<unavailable>"));
122 return;
123 }
124
125 fprintf_filtered (file, "%s", hex_string_custom (status, 4));
126 fputs_filtered (" ", file);
127 fprintf_filtered (file, " %s", (status & 0x0001) ? "IE" : " ");
128 fprintf_filtered (file, " %s", (status & 0x0002) ? "DE" : " ");
129 fprintf_filtered (file, " %s", (status & 0x0004) ? "ZE" : " ");
130 fprintf_filtered (file, " %s", (status & 0x0008) ? "OE" : " ");
131 fprintf_filtered (file, " %s", (status & 0x0010) ? "UE" : " ");
132 fprintf_filtered (file, " %s", (status & 0x0020) ? "PE" : " ");
133 fputs_filtered (" ", file);
134 fprintf_filtered (file, " %s", (status & 0x0080) ? "ES" : " ");
135 fputs_filtered (" ", file);
136 fprintf_filtered (file, " %s", (status & 0x0040) ? "SF" : " ");
137 fputs_filtered (" ", file);
138 fprintf_filtered (file, " %s", (status & 0x0100) ? "C0" : " ");
139 fprintf_filtered (file, " %s", (status & 0x0200) ? "C1" : " ");
140 fprintf_filtered (file, " %s", (status & 0x0400) ? "C2" : " ");
141 fprintf_filtered (file, " %s", (status & 0x4000) ? "C3" : " ");
142
143 fputs_filtered ("\n", file);
144
145 fprintf_filtered (file,
146 " TOP: %d\n", ((status >> 11) & 7));
147 }
148
149 /* Print the control word CONTROL. If CONTROL_P is false, then
150 CONTROL was unavailable. */
151
152 static void
153 print_i387_control_word (int control_p,
154 unsigned int control, struct ui_file *file)
155 {
156 fprintf_filtered (file, "Control Word: ");
157 if (!control_p)
158 {
159 fprintf_filtered (file, "%s\n", _("<unavailable>"));
160 return;
161 }
162
163 fprintf_filtered (file, "%s", hex_string_custom (control, 4));
164 fputs_filtered (" ", file);
165 fprintf_filtered (file, " %s", (control & 0x0001) ? "IM" : " ");
166 fprintf_filtered (file, " %s", (control & 0x0002) ? "DM" : " ");
167 fprintf_filtered (file, " %s", (control & 0x0004) ? "ZM" : " ");
168 fprintf_filtered (file, " %s", (control & 0x0008) ? "OM" : " ");
169 fprintf_filtered (file, " %s", (control & 0x0010) ? "UM" : " ");
170 fprintf_filtered (file, " %s", (control & 0x0020) ? "PM" : " ");
171
172 fputs_filtered ("\n", file);
173
174 fputs_filtered (" PC: ", file);
175 switch ((control >> 8) & 3)
176 {
177 case 0:
178 fputs_filtered ("Single Precision (24-bits)\n", file);
179 break;
180 case 1:
181 fputs_filtered ("Reserved\n", file);
182 break;
183 case 2:
184 fputs_filtered ("Double Precision (53-bits)\n", file);
185 break;
186 case 3:
187 fputs_filtered ("Extended Precision (64-bits)\n", file);
188 break;
189 }
190
191 fputs_filtered (" RC: ", file);
192 switch ((control >> 10) & 3)
193 {
194 case 0:
195 fputs_filtered ("Round to nearest\n", file);
196 break;
197 case 1:
198 fputs_filtered ("Round down\n", file);
199 break;
200 case 2:
201 fputs_filtered ("Round up\n", file);
202 break;
203 case 3:
204 fputs_filtered ("Round toward zero\n", file);
205 break;
206 }
207 }
208
209 /* Print out the i387 floating point state. Note that we ignore FRAME
210 in the code below. That's OK since floating-point registers are
211 never saved on the stack. */
212
213 void
214 i387_print_float_info (struct gdbarch *gdbarch, struct ui_file *file,
215 struct frame_info *frame, const char *args)
216 {
217 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (frame));
218 ULONGEST fctrl;
219 int fctrl_p;
220 ULONGEST fstat;
221 int fstat_p;
222 ULONGEST ftag;
223 int ftag_p;
224 ULONGEST fiseg;
225 int fiseg_p;
226 ULONGEST fioff;
227 int fioff_p;
228 ULONGEST foseg;
229 int foseg_p;
230 ULONGEST fooff;
231 int fooff_p;
232 ULONGEST fop;
233 int fop_p;
234 int fpreg;
235 int top;
236
237 gdb_assert (gdbarch == get_frame_arch (frame));
238
239 fctrl_p = read_frame_register_unsigned (frame,
240 I387_FCTRL_REGNUM (tdep), &fctrl);
241 fstat_p = read_frame_register_unsigned (frame,
242 I387_FSTAT_REGNUM (tdep), &fstat);
243 ftag_p = read_frame_register_unsigned (frame,
244 I387_FTAG_REGNUM (tdep), &ftag);
245 fiseg_p = read_frame_register_unsigned (frame,
246 I387_FISEG_REGNUM (tdep), &fiseg);
247 fioff_p = read_frame_register_unsigned (frame,
248 I387_FIOFF_REGNUM (tdep), &fioff);
249 foseg_p = read_frame_register_unsigned (frame,
250 I387_FOSEG_REGNUM (tdep), &foseg);
251 fooff_p = read_frame_register_unsigned (frame,
252 I387_FOOFF_REGNUM (tdep), &fooff);
253 fop_p = read_frame_register_unsigned (frame,
254 I387_FOP_REGNUM (tdep), &fop);
255
256 if (fstat_p)
257 {
258 top = ((fstat >> 11) & 7);
259
260 for (fpreg = 7; fpreg >= 0; fpreg--)
261 {
262 struct value *regval;
263 int regnum;
264 int i;
265 int tag = -1;
266
267 fprintf_filtered (file, "%sR%d: ", fpreg == top ? "=>" : " ", fpreg);
268
269 if (ftag_p)
270 {
271 tag = (ftag >> (fpreg * 2)) & 3;
272
273 switch (tag)
274 {
275 case 0:
276 fputs_filtered ("Valid ", file);
277 break;
278 case 1:
279 fputs_filtered ("Zero ", file);
280 break;
281 case 2:
282 fputs_filtered ("Special ", file);
283 break;
284 case 3:
285 fputs_filtered ("Empty ", file);
286 break;
287 }
288 }
289 else
290 fputs_filtered ("Unknown ", file);
291
292 regnum = (fpreg + 8 - top) % 8 + I387_ST0_REGNUM (tdep);
293 regval = get_frame_register_value (frame, regnum);
294
295 if (value_entirely_available (regval))
296 {
297 const gdb_byte *raw = value_contents (regval);
298
299 fputs_filtered ("0x", file);
300 for (i = 9; i >= 0; i--)
301 fprintf_filtered (file, "%02x", raw[i]);
302
303 if (tag != -1 && tag != 3)
304 print_i387_ext (gdbarch, raw, file);
305 }
306 else
307 fprintf_filtered (file, "%s", _("<unavailable>"));
308
309 fputs_filtered ("\n", file);
310 }
311 }
312
313 fputs_filtered ("\n", file);
314 print_i387_status_word (fstat_p, fstat, file);
315 print_i387_control_word (fctrl_p, fctrl, file);
316 fprintf_filtered (file, "Tag Word: %s\n",
317 ftag_p ? hex_string_custom (ftag, 4) : _("<unavailable>"));
318 fprintf_filtered (file, "Instruction Pointer: %s:",
319 fiseg_p ? hex_string_custom (fiseg, 2) : _("<unavailable>"));
320 fprintf_filtered (file, "%s\n",
321 fioff_p ? hex_string_custom (fioff, 8) : _("<unavailable>"));
322 fprintf_filtered (file, "Operand Pointer: %s:",
323 foseg_p ? hex_string_custom (foseg, 2) : _("<unavailable>"));
324 fprintf_filtered (file, "%s\n",
325 fooff_p ? hex_string_custom (fooff, 8) : _("<unavailable>"));
326 fprintf_filtered (file, "Opcode: %s\n",
327 fop_p
328 ? (hex_string_custom (fop ? (fop | 0xd800) : 0, 4))
329 : _("<unavailable>"));
330 }
331 \f
332
333 /* Return nonzero if a value of type TYPE stored in register REGNUM
334 needs any special handling. */
335
336 int
337 i387_convert_register_p (struct gdbarch *gdbarch, int regnum,
338 struct type *type)
339 {
340 if (i386_fp_regnum_p (gdbarch, regnum))
341 {
342 /* Floating point registers must be converted unless we are
343 accessing them in their hardware type or TYPE is not float. */
344 if (type == i387_ext_type (gdbarch)
345 || TYPE_CODE (type) != TYPE_CODE_FLT)
346 return 0;
347 else
348 return 1;
349 }
350
351 return 0;
352 }
353
354 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
355 return its contents in TO. */
356
357 int
358 i387_register_to_value (struct frame_info *frame, int regnum,
359 struct type *type, gdb_byte *to,
360 int *optimizedp, int *unavailablep)
361 {
362 struct gdbarch *gdbarch = get_frame_arch (frame);
363 gdb_byte from[I386_MAX_REGISTER_SIZE];
364
365 gdb_assert (i386_fp_regnum_p (gdbarch, regnum));
366
367 /* We only support floating-point values. */
368 if (TYPE_CODE (type) != TYPE_CODE_FLT)
369 {
370 warning (_("Cannot convert floating-point register value "
371 "to non-floating-point type."));
372 *optimizedp = *unavailablep = 0;
373 return 0;
374 }
375
376 /* Convert to TYPE. */
377 if (!get_frame_register_bytes (frame, regnum, 0,
378 register_size (gdbarch, regnum),
379 from, optimizedp, unavailablep))
380 return 0;
381
382 convert_typed_floating (from, i387_ext_type (gdbarch), to, type);
383 *optimizedp = *unavailablep = 0;
384 return 1;
385 }
386
387 /* Write the contents FROM of a value of type TYPE into register
388 REGNUM in frame FRAME. */
389
390 void
391 i387_value_to_register (struct frame_info *frame, int regnum,
392 struct type *type, const gdb_byte *from)
393 {
394 struct gdbarch *gdbarch = get_frame_arch (frame);
395 gdb_byte to[I386_MAX_REGISTER_SIZE];
396
397 gdb_assert (i386_fp_regnum_p (gdbarch, regnum));
398
399 /* We only support floating-point values. */
400 if (TYPE_CODE (type) != TYPE_CODE_FLT)
401 {
402 warning (_("Cannot convert non-floating-point type "
403 "to floating-point register value."));
404 return;
405 }
406
407 /* Convert from TYPE. */
408 convert_typed_floating (from, type, to, i387_ext_type (gdbarch));
409 put_frame_register (frame, regnum, to);
410 }
411 \f
412
413 /* Handle FSAVE and FXSAVE formats. */
414
415 /* At fsave_offset[REGNUM] you'll find the offset to the location in
416 the data structure used by the "fsave" instruction where GDB
417 register REGNUM is stored. */
418
419 static int fsave_offset[] =
420 {
421 28 + 0 * 10, /* %st(0) ... */
422 28 + 1 * 10,
423 28 + 2 * 10,
424 28 + 3 * 10,
425 28 + 4 * 10,
426 28 + 5 * 10,
427 28 + 6 * 10,
428 28 + 7 * 10, /* ... %st(7). */
429 0, /* `fctrl' (16 bits). */
430 4, /* `fstat' (16 bits). */
431 8, /* `ftag' (16 bits). */
432 16, /* `fiseg' (16 bits). */
433 12, /* `fioff'. */
434 24, /* `foseg' (16 bits). */
435 20, /* `fooff'. */
436 18 /* `fop' (bottom 11 bits). */
437 };
438
439 #define FSAVE_ADDR(tdep, fsave, regnum) \
440 (fsave + fsave_offset[regnum - I387_ST0_REGNUM (tdep)])
441 \f
442
443 /* Fill register REGNUM in REGCACHE with the appropriate value from
444 *FSAVE. This function masks off any of the reserved bits in
445 *FSAVE. */
446
447 void
448 i387_supply_fsave (struct regcache *regcache, int regnum, const void *fsave)
449 {
450 struct gdbarch *gdbarch = get_regcache_arch (regcache);
451 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
452 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
453 const gdb_byte *regs = (const gdb_byte *) fsave;
454 int i;
455
456 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
457
458 for (i = I387_ST0_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++)
459 if (regnum == -1 || regnum == i)
460 {
461 if (fsave == NULL)
462 {
463 regcache_raw_supply (regcache, i, NULL);
464 continue;
465 }
466
467 /* Most of the FPU control registers occupy only 16 bits in the
468 fsave area. Give those a special treatment. */
469 if (i >= I387_FCTRL_REGNUM (tdep)
470 && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep))
471 {
472 gdb_byte val[4];
473
474 memcpy (val, FSAVE_ADDR (tdep, regs, i), 2);
475 val[2] = val[3] = 0;
476 if (i == I387_FOP_REGNUM (tdep))
477 val[1] &= ((1 << 3) - 1);
478 regcache_raw_supply (regcache, i, val);
479 }
480 else
481 regcache_raw_supply (regcache, i, FSAVE_ADDR (tdep, regs, i));
482 }
483
484 /* Provide dummy values for the SSE registers. */
485 for (i = I387_XMM0_REGNUM (tdep); i < I387_MXCSR_REGNUM (tdep); i++)
486 if (regnum == -1 || regnum == i)
487 regcache_raw_supply (regcache, i, NULL);
488 if (regnum == -1 || regnum == I387_MXCSR_REGNUM (tdep))
489 {
490 gdb_byte buf[4];
491
492 store_unsigned_integer (buf, 4, byte_order, 0x1f80);
493 regcache_raw_supply (regcache, I387_MXCSR_REGNUM (tdep), buf);
494 }
495 }
496
497 /* Fill register REGNUM (if it is a floating-point register) in *FSAVE
498 with the value from REGCACHE. If REGNUM is -1, do this for all
499 registers. This function doesn't touch any of the reserved bits in
500 *FSAVE. */
501
502 void
503 i387_collect_fsave (const struct regcache *regcache, int regnum, void *fsave)
504 {
505 struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache));
506 gdb_byte *regs = (gdb_byte *) fsave;
507 int i;
508
509 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
510
511 for (i = I387_ST0_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++)
512 if (regnum == -1 || regnum == i)
513 {
514 /* Most of the FPU control registers occupy only 16 bits in
515 the fsave area. Give those a special treatment. */
516 if (i >= I387_FCTRL_REGNUM (tdep)
517 && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep))
518 {
519 gdb_byte buf[4];
520
521 regcache_raw_collect (regcache, i, buf);
522
523 if (i == I387_FOP_REGNUM (tdep))
524 {
525 /* The opcode occupies only 11 bits. Make sure we
526 don't touch the other bits. */
527 buf[1] &= ((1 << 3) - 1);
528 buf[1] |= ((FSAVE_ADDR (tdep, regs, i))[1] & ~((1 << 3) - 1));
529 }
530 memcpy (FSAVE_ADDR (tdep, regs, i), buf, 2);
531 }
532 else
533 regcache_raw_collect (regcache, i, FSAVE_ADDR (tdep, regs, i));
534 }
535 }
536 \f
537
538 /* At fxsave_offset[REGNUM] you'll find the offset to the location in
539 the data structure used by the "fxsave" instruction where GDB
540 register REGNUM is stored. */
541
542 static int fxsave_offset[] =
543 {
544 32, /* %st(0) through ... */
545 48,
546 64,
547 80,
548 96,
549 112,
550 128,
551 144, /* ... %st(7) (80 bits each). */
552 0, /* `fctrl' (16 bits). */
553 2, /* `fstat' (16 bits). */
554 4, /* `ftag' (16 bits). */
555 12, /* `fiseg' (16 bits). */
556 8, /* `fioff'. */
557 20, /* `foseg' (16 bits). */
558 16, /* `fooff'. */
559 6, /* `fop' (bottom 11 bits). */
560 160 + 0 * 16, /* %xmm0 through ... */
561 160 + 1 * 16,
562 160 + 2 * 16,
563 160 + 3 * 16,
564 160 + 4 * 16,
565 160 + 5 * 16,
566 160 + 6 * 16,
567 160 + 7 * 16,
568 160 + 8 * 16,
569 160 + 9 * 16,
570 160 + 10 * 16,
571 160 + 11 * 16,
572 160 + 12 * 16,
573 160 + 13 * 16,
574 160 + 14 * 16,
575 160 + 15 * 16, /* ... %xmm15 (128 bits each). */
576 };
577
578 #define FXSAVE_ADDR(tdep, fxsave, regnum) \
579 (fxsave + fxsave_offset[regnum - I387_ST0_REGNUM (tdep)])
580
581 /* We made an unfortunate choice in putting %mxcsr after the SSE
582 registers %xmm0-%xmm7 instead of before, since it makes supporting
583 the registers %xmm8-%xmm15 on AMD64 a bit involved. Therefore we
584 don't include the offset for %mxcsr here above. */
585
586 #define FXSAVE_MXCSR_ADDR(fxsave) (fxsave + 24)
587
588 static int i387_tag (const gdb_byte *raw);
589 \f
590
591 /* Fill register REGNUM in REGCACHE with the appropriate
592 floating-point or SSE register value from *FXSAVE. This function
593 masks off any of the reserved bits in *FXSAVE. */
594
595 void
596 i387_supply_fxsave (struct regcache *regcache, int regnum, const void *fxsave)
597 {
598 struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache));
599 const gdb_byte *regs = (const gdb_byte *) fxsave;
600 int i;
601
602 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
603 gdb_assert (tdep->num_xmm_regs > 0);
604
605 for (i = I387_ST0_REGNUM (tdep); i < I387_MXCSR_REGNUM (tdep); i++)
606 if (regnum == -1 || regnum == i)
607 {
608 if (regs == NULL)
609 {
610 regcache_raw_supply (regcache, i, NULL);
611 continue;
612 }
613
614 /* Most of the FPU control registers occupy only 16 bits in
615 the fxsave area. Give those a special treatment. */
616 if (i >= I387_FCTRL_REGNUM (tdep) && i < I387_XMM0_REGNUM (tdep)
617 && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep))
618 {
619 gdb_byte val[4];
620
621 memcpy (val, FXSAVE_ADDR (tdep, regs, i), 2);
622 val[2] = val[3] = 0;
623 if (i == I387_FOP_REGNUM (tdep))
624 val[1] &= ((1 << 3) - 1);
625 else if (i== I387_FTAG_REGNUM (tdep))
626 {
627 /* The fxsave area contains a simplified version of
628 the tag word. We have to look at the actual 80-bit
629 FP data to recreate the traditional i387 tag word. */
630
631 unsigned long ftag = 0;
632 int fpreg;
633 int top;
634
635 top = ((FXSAVE_ADDR (tdep, regs,
636 I387_FSTAT_REGNUM (tdep)))[1] >> 3);
637 top &= 0x7;
638
639 for (fpreg = 7; fpreg >= 0; fpreg--)
640 {
641 int tag;
642
643 if (val[0] & (1 << fpreg))
644 {
645 int thisreg = (fpreg + 8 - top) % 8
646 + I387_ST0_REGNUM (tdep);
647 tag = i387_tag (FXSAVE_ADDR (tdep, regs, thisreg));
648 }
649 else
650 tag = 3; /* Empty */
651
652 ftag |= tag << (2 * fpreg);
653 }
654 val[0] = ftag & 0xff;
655 val[1] = (ftag >> 8) & 0xff;
656 }
657 regcache_raw_supply (regcache, i, val);
658 }
659 else
660 regcache_raw_supply (regcache, i, FXSAVE_ADDR (tdep, regs, i));
661 }
662
663 if (regnum == I387_MXCSR_REGNUM (tdep) || regnum == -1)
664 {
665 if (regs == NULL)
666 regcache_raw_supply (regcache, I387_MXCSR_REGNUM (tdep), NULL);
667 else
668 regcache_raw_supply (regcache, I387_MXCSR_REGNUM (tdep),
669 FXSAVE_MXCSR_ADDR (regs));
670 }
671 }
672
673 /* Fill register REGNUM (if it is a floating-point or SSE register) in
674 *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for
675 all registers. This function doesn't touch any of the reserved
676 bits in *FXSAVE. */
677
678 void
679 i387_collect_fxsave (const struct regcache *regcache, int regnum, void *fxsave)
680 {
681 struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache));
682 gdb_byte *regs = (gdb_byte *) fxsave;
683 int i;
684
685 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
686 gdb_assert (tdep->num_xmm_regs > 0);
687
688 for (i = I387_ST0_REGNUM (tdep); i < I387_MXCSR_REGNUM (tdep); i++)
689 if (regnum == -1 || regnum == i)
690 {
691 /* Most of the FPU control registers occupy only 16 bits in
692 the fxsave area. Give those a special treatment. */
693 if (i >= I387_FCTRL_REGNUM (tdep) && i < I387_XMM0_REGNUM (tdep)
694 && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep))
695 {
696 gdb_byte buf[4];
697
698 regcache_raw_collect (regcache, i, buf);
699
700 if (i == I387_FOP_REGNUM (tdep))
701 {
702 /* The opcode occupies only 11 bits. Make sure we
703 don't touch the other bits. */
704 buf[1] &= ((1 << 3) - 1);
705 buf[1] |= ((FXSAVE_ADDR (tdep, regs, i))[1] & ~((1 << 3) - 1));
706 }
707 else if (i == I387_FTAG_REGNUM (tdep))
708 {
709 /* Converting back is much easier. */
710
711 unsigned short ftag;
712 int fpreg;
713
714 ftag = (buf[1] << 8) | buf[0];
715 buf[0] = 0;
716 buf[1] = 0;
717
718 for (fpreg = 7; fpreg >= 0; fpreg--)
719 {
720 int tag = (ftag >> (fpreg * 2)) & 3;
721
722 if (tag != 3)
723 buf[0] |= (1 << fpreg);
724 }
725 }
726 memcpy (FXSAVE_ADDR (tdep, regs, i), buf, 2);
727 }
728 else
729 regcache_raw_collect (regcache, i, FXSAVE_ADDR (tdep, regs, i));
730 }
731
732 if (regnum == I387_MXCSR_REGNUM (tdep) || regnum == -1)
733 regcache_raw_collect (regcache, I387_MXCSR_REGNUM (tdep),
734 FXSAVE_MXCSR_ADDR (regs));
735 }
736
737 /* `xstate_bv' is at byte offset 512. */
738 #define XSAVE_XSTATE_BV_ADDR(xsave) (xsave + 512)
739
740 /* At xsave_avxh_offset[REGNUM] you'll find the offset to the location in
741 the upper 128bit of AVX register data structure used by the "xsave"
742 instruction where GDB register REGNUM is stored. */
743
744 static int xsave_avxh_offset[] =
745 {
746 576 + 0 * 16, /* Upper 128bit of %ymm0 through ... */
747 576 + 1 * 16,
748 576 + 2 * 16,
749 576 + 3 * 16,
750 576 + 4 * 16,
751 576 + 5 * 16,
752 576 + 6 * 16,
753 576 + 7 * 16,
754 576 + 8 * 16,
755 576 + 9 * 16,
756 576 + 10 * 16,
757 576 + 11 * 16,
758 576 + 12 * 16,
759 576 + 13 * 16,
760 576 + 14 * 16,
761 576 + 15 * 16 /* Upper 128bit of ... %ymm15 (128 bits each). */
762 };
763
764 #define XSAVE_AVXH_ADDR(tdep, xsave, regnum) \
765 (xsave + xsave_avxh_offset[regnum - I387_YMM0H_REGNUM (tdep)])
766
767 /* At xsave_ymm_avx512_offset[REGNUM] you'll find the offset to the location in
768 the upper 128bit of ZMM register data structure used by the "xsave"
769 instruction where GDB register REGNUM is stored. */
770
771 static int xsave_ymm_avx512_offset[] =
772 {
773 /* HI16_ZMM_area + 16 bytes + regnum* 64 bytes. */
774 1664 + 16 + 0 * 64, /* %ymm16 through... */
775 1664 + 16 + 1 * 64,
776 1664 + 16 + 2 * 64,
777 1664 + 16 + 3 * 64,
778 1664 + 16 + 4 * 64,
779 1664 + 16 + 5 * 64,
780 1664 + 16 + 6 * 64,
781 1664 + 16 + 7 * 64,
782 1664 + 16 + 8 * 64,
783 1664 + 16 + 9 * 64,
784 1664 + 16 + 10 * 64,
785 1664 + 16 + 11 * 64,
786 1664 + 16 + 12 * 64,
787 1664 + 16 + 13 * 64,
788 1664 + 16 + 14 * 64,
789 1664 + 16 + 15 * 64 /* ... %ymm31 (128 bits each). */
790 };
791
792 #define XSAVE_YMM_AVX512_ADDR(tdep, xsave, regnum) \
793 (xsave + xsave_ymm_avx512_offset[regnum - I387_YMM16H_REGNUM (tdep)])
794
795 static int xsave_xmm_avx512_offset[] =
796 {
797 1664 + 0 * 64, /* %ymm16 through... */
798 1664 + 1 * 64,
799 1664 + 2 * 64,
800 1664 + 3 * 64,
801 1664 + 4 * 64,
802 1664 + 5 * 64,
803 1664 + 6 * 64,
804 1664 + 7 * 64,
805 1664 + 8 * 64,
806 1664 + 9 * 64,
807 1664 + 10 * 64,
808 1664 + 11 * 64,
809 1664 + 12 * 64,
810 1664 + 13 * 64,
811 1664 + 14 * 64,
812 1664 + 15 * 64 /* ... %ymm31 (128 bits each). */
813 };
814
815 #define XSAVE_XMM_AVX512_ADDR(tdep, xsave, regnum) \
816 (xsave + xsave_xmm_avx512_offset[regnum - I387_XMM16_REGNUM (tdep)])
817
818 static int xsave_mpx_offset[] = {
819 960 + 0 * 16, /* bnd0r...bnd3r registers. */
820 960 + 1 * 16,
821 960 + 2 * 16,
822 960 + 3 * 16,
823 1024 + 0 * 8, /* bndcfg ... bndstatus. */
824 1024 + 1 * 8,
825 };
826
827 #define XSAVE_MPX_ADDR(tdep, xsave, regnum) \
828 (xsave + xsave_mpx_offset[regnum - I387_BND0R_REGNUM (tdep)])
829
830 /* At xsave_avx512__h_offset[REGNUM] you find the offset to the location
831 of the AVX512 opmask register data structure used by the "xsave"
832 instruction where GDB register REGNUM is stored. */
833
834 static int xsave_avx512_k_offset[] =
835 {
836 1088 + 0 * 8, /* %k0 through... */
837 1088 + 1 * 8,
838 1088 + 2 * 8,
839 1088 + 3 * 8,
840 1088 + 4 * 8,
841 1088 + 5 * 8,
842 1088 + 6 * 8,
843 1088 + 7 * 8 /* %k7 (64 bits each). */
844 };
845
846 #define XSAVE_AVX512_K_ADDR(tdep, xsave, regnum) \
847 (xsave + xsave_avx512_k_offset[regnum - I387_K0_REGNUM (tdep)])
848
849 /* At xsave_avx512_zmm_h_offset[REGNUM] you find the offset to the location in
850 the upper 256bit of AVX512 ZMMH register data structure used by the "xsave"
851 instruction where GDB register REGNUM is stored. */
852
853 static int xsave_avx512_zmm_h_offset[] =
854 {
855 1152 + 0 * 32,
856 1152 + 1 * 32, /* Upper 256bit of %zmmh0 through... */
857 1152 + 2 * 32,
858 1152 + 3 * 32,
859 1152 + 4 * 32,
860 1152 + 5 * 32,
861 1152 + 6 * 32,
862 1152 + 7 * 32,
863 1152 + 8 * 32,
864 1152 + 9 * 32,
865 1152 + 10 * 32,
866 1152 + 11 * 32,
867 1152 + 12 * 32,
868 1152 + 13 * 32,
869 1152 + 14 * 32,
870 1152 + 15 * 32, /* Upper 256bit of... %zmmh15 (256 bits each). */
871 1664 + 32 + 0 * 64, /* Upper 256bit of... %zmmh16 (256 bits each). */
872 1664 + 32 + 1 * 64,
873 1664 + 32 + 2 * 64,
874 1664 + 32 + 3 * 64,
875 1664 + 32 + 4 * 64,
876 1664 + 32 + 5 * 64,
877 1664 + 32 + 6 * 64,
878 1664 + 32 + 7 * 64,
879 1664 + 32 + 8 * 64,
880 1664 + 32 + 9 * 64,
881 1664 + 32 + 10 * 64,
882 1664 + 32 + 11 * 64,
883 1664 + 32 + 12 * 64,
884 1664 + 32 + 13 * 64,
885 1664 + 32 + 14 * 64,
886 1664 + 32 + 15 * 64 /* Upper 256bit of... %zmmh31 (256 bits each). */
887 };
888
889 #define XSAVE_AVX512_ZMM_H_ADDR(tdep, xsave, regnum) \
890 (xsave + xsave_avx512_zmm_h_offset[regnum - I387_ZMM0H_REGNUM (tdep)])
891
892 /* At xsave_pkeys_offset[REGNUM] you find the offset to the location
893 of the PKRU register data structure used by the "xsave"
894 instruction where GDB register REGNUM is stored. */
895
896 static int xsave_pkeys_offset[] =
897 {
898 2688 + 0 * 8 /* %pkru (64 bits in XSTATE, 32-bit actually used by
899 instructions and applications). */
900 };
901
902 #define XSAVE_PKEYS_ADDR(tdep, xsave, regnum) \
903 (xsave + xsave_pkeys_offset[regnum - I387_PKRU_REGNUM (tdep)])
904
905 /* Similar to i387_supply_fxsave, but use XSAVE extended state. */
906
907 void
908 i387_supply_xsave (struct regcache *regcache, int regnum,
909 const void *xsave)
910 {
911 struct gdbarch *gdbarch = get_regcache_arch (regcache);
912 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
913 const gdb_byte *regs = (const gdb_byte *) xsave;
914 int i;
915 ULONGEST clear_bv;
916 static const gdb_byte zero[I386_MAX_REGISTER_SIZE] = { 0 };
917 enum
918 {
919 none = 0x0,
920 x87 = 0x1,
921 sse = 0x2,
922 avxh = 0x4,
923 mpx = 0x8,
924 avx512_k = 0x10,
925 avx512_zmm_h = 0x20,
926 avx512_ymmh_avx512 = 0x40,
927 avx512_xmm_avx512 = 0x80,
928 pkeys = 0x100,
929 all = x87 | sse | avxh | mpx | avx512_k | avx512_zmm_h
930 | avx512_ymmh_avx512 | avx512_xmm_avx512 | pkeys
931 } regclass;
932
933 gdb_assert (regs != NULL);
934 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
935 gdb_assert (tdep->num_xmm_regs > 0);
936
937 if (regnum == -1)
938 regclass = all;
939 else if (regnum >= I387_PKRU_REGNUM (tdep)
940 && regnum < I387_PKEYSEND_REGNUM (tdep))
941 regclass = pkeys;
942 else if (regnum >= I387_ZMM0H_REGNUM (tdep)
943 && regnum < I387_ZMMENDH_REGNUM (tdep))
944 regclass = avx512_zmm_h;
945 else if (regnum >= I387_K0_REGNUM (tdep)
946 && regnum < I387_KEND_REGNUM (tdep))
947 regclass = avx512_k;
948 else if (regnum >= I387_YMM16H_REGNUM (tdep)
949 && regnum < I387_YMMH_AVX512_END_REGNUM (tdep))
950 regclass = avx512_ymmh_avx512;
951 else if (regnum >= I387_XMM16_REGNUM (tdep)
952 && regnum < I387_XMM_AVX512_END_REGNUM (tdep))
953 regclass = avx512_xmm_avx512;
954 else if (regnum >= I387_YMM0H_REGNUM (tdep)
955 && regnum < I387_YMMENDH_REGNUM (tdep))
956 regclass = avxh;
957 else if (regnum >= I387_BND0R_REGNUM (tdep)
958 && regnum < I387_MPXEND_REGNUM (tdep))
959 regclass = mpx;
960 else if (regnum >= I387_XMM0_REGNUM (tdep)
961 && regnum < I387_MXCSR_REGNUM (tdep))
962 regclass = sse;
963 else if (regnum >= I387_ST0_REGNUM (tdep)
964 && regnum < I387_FCTRL_REGNUM (tdep))
965 regclass = x87;
966 else
967 regclass = none;
968
969 if (regclass != none)
970 {
971 /* Get `xstat_bv'. The supported bits in `xstat_bv' are 8 bytes. */
972 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
973 ULONGEST xstate_bv = 0;
974
975 xstate_bv = extract_unsigned_integer (XSAVE_XSTATE_BV_ADDR (regs),
976 8, byte_order);
977
978 /* Clear part in vector registers if its bit in xstat_bv is zero. */
979 clear_bv = (~(xstate_bv)) & tdep->xcr0;
980 }
981 else
982 clear_bv = X86_XSTATE_ALL_MASK;
983
984 /* With the delayed xsave mechanism, in between the program
985 starting, and the program accessing the vector registers for the
986 first time, the register's values are invalid. The kernel
987 initializes register states to zero when they are set the first
988 time in a program. This means that from the user-space programs'
989 perspective, it's the same as if the registers have always been
990 zero from the start of the program. Therefore, the debugger
991 should provide the same illusion to the user. */
992
993 switch (regclass)
994 {
995 case none:
996 break;
997
998 case pkeys:
999 if ((clear_bv & X86_XSTATE_PKRU))
1000 regcache_raw_supply (regcache, regnum, zero);
1001 else
1002 regcache_raw_supply (regcache, regnum,
1003 XSAVE_PKEYS_ADDR (tdep, regs, regnum));
1004 return;
1005
1006 case avx512_zmm_h:
1007 if ((clear_bv & (X86_XSTATE_ZMM_H | X86_XSTATE_ZMM)))
1008 regcache_raw_supply (regcache, regnum, zero);
1009 else
1010 regcache_raw_supply (regcache, regnum,
1011 XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, regnum));
1012 return;
1013
1014 case avx512_k:
1015 if ((clear_bv & X86_XSTATE_K))
1016 regcache_raw_supply (regcache, regnum, zero);
1017 else
1018 regcache_raw_supply (regcache, regnum,
1019 XSAVE_AVX512_K_ADDR (tdep, regs, regnum));
1020 return;
1021
1022 case avx512_ymmh_avx512:
1023 if ((clear_bv & X86_XSTATE_ZMM))
1024 regcache_raw_supply (regcache, regnum, zero);
1025 else
1026 regcache_raw_supply (regcache, regnum,
1027 XSAVE_YMM_AVX512_ADDR (tdep, regs, regnum));
1028 return;
1029
1030 case avx512_xmm_avx512:
1031 if ((clear_bv & X86_XSTATE_ZMM))
1032 regcache_raw_supply (regcache, regnum, zero);
1033 else
1034 regcache_raw_supply (regcache, regnum,
1035 XSAVE_XMM_AVX512_ADDR (tdep, regs, regnum));
1036 return;
1037
1038 case avxh:
1039 if ((clear_bv & X86_XSTATE_AVX))
1040 regcache_raw_supply (regcache, regnum, zero);
1041 else
1042 regcache_raw_supply (regcache, regnum,
1043 XSAVE_AVXH_ADDR (tdep, regs, regnum));
1044 return;
1045
1046 case mpx:
1047 if ((clear_bv & X86_XSTATE_BNDREGS))
1048 regcache_raw_supply (regcache, regnum, zero);
1049 else
1050 regcache_raw_supply (regcache, regnum,
1051 XSAVE_MPX_ADDR (tdep, regs, regnum));
1052 return;
1053
1054 case sse:
1055 if ((clear_bv & X86_XSTATE_SSE))
1056 regcache_raw_supply (regcache, regnum, zero);
1057 else
1058 regcache_raw_supply (regcache, regnum,
1059 FXSAVE_ADDR (tdep, regs, regnum));
1060 return;
1061
1062 case x87:
1063 if ((clear_bv & X86_XSTATE_X87))
1064 regcache_raw_supply (regcache, regnum, zero);
1065 else
1066 regcache_raw_supply (regcache, regnum,
1067 FXSAVE_ADDR (tdep, regs, regnum));
1068 return;
1069
1070 case all:
1071 /* Handle PKEYS registers. */
1072 if ((tdep->xcr0 & X86_XSTATE_PKRU))
1073 {
1074 if ((clear_bv & X86_XSTATE_PKRU))
1075 {
1076 for (i = I387_PKRU_REGNUM (tdep);
1077 i < I387_PKEYSEND_REGNUM (tdep);
1078 i++)
1079 regcache_raw_supply (regcache, i, zero);
1080 }
1081 else
1082 {
1083 for (i = I387_PKRU_REGNUM (tdep);
1084 i < I387_PKEYSEND_REGNUM (tdep);
1085 i++)
1086 regcache_raw_supply (regcache, i,
1087 XSAVE_PKEYS_ADDR (tdep, regs, i));
1088 }
1089 }
1090
1091 /* Handle the upper ZMM registers. */
1092 if ((tdep->xcr0 & (X86_XSTATE_ZMM_H | X86_XSTATE_ZMM)))
1093 {
1094 if ((clear_bv & (X86_XSTATE_ZMM_H | X86_XSTATE_ZMM)))
1095 {
1096 for (i = I387_ZMM0H_REGNUM (tdep);
1097 i < I387_ZMMENDH_REGNUM (tdep);
1098 i++)
1099 regcache_raw_supply (regcache, i, zero);
1100 }
1101 else
1102 {
1103 for (i = I387_ZMM0H_REGNUM (tdep);
1104 i < I387_ZMMENDH_REGNUM (tdep);
1105 i++)
1106 regcache_raw_supply (regcache, i,
1107 XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, i));
1108 }
1109 }
1110
1111 /* Handle AVX512 OpMask registers. */
1112 if ((tdep->xcr0 & X86_XSTATE_K))
1113 {
1114 if ((clear_bv & X86_XSTATE_K))
1115 {
1116 for (i = I387_K0_REGNUM (tdep);
1117 i < I387_KEND_REGNUM (tdep);
1118 i++)
1119 regcache_raw_supply (regcache, i, zero);
1120 }
1121 else
1122 {
1123 for (i = I387_K0_REGNUM (tdep);
1124 i < I387_KEND_REGNUM (tdep);
1125 i++)
1126 regcache_raw_supply (regcache, i,
1127 XSAVE_AVX512_K_ADDR (tdep, regs, i));
1128 }
1129 }
1130
1131 /* Handle the YMM_AVX512 registers. */
1132 if ((tdep->xcr0 & X86_XSTATE_ZMM))
1133 {
1134 if ((clear_bv & X86_XSTATE_ZMM))
1135 {
1136 for (i = I387_YMM16H_REGNUM (tdep);
1137 i < I387_YMMH_AVX512_END_REGNUM (tdep);
1138 i++)
1139 regcache_raw_supply (regcache, i, zero);
1140 for (i = I387_XMM16_REGNUM (tdep);
1141 i < I387_XMM_AVX512_END_REGNUM (tdep);
1142 i++)
1143 regcache_raw_supply (regcache, i, zero);
1144 }
1145 else
1146 {
1147 for (i = I387_YMM16H_REGNUM (tdep);
1148 i < I387_YMMH_AVX512_END_REGNUM (tdep);
1149 i++)
1150 regcache_raw_supply (regcache, i,
1151 XSAVE_YMM_AVX512_ADDR (tdep, regs, i));
1152 for (i = I387_XMM16_REGNUM (tdep);
1153 i < I387_XMM_AVX512_END_REGNUM (tdep);
1154 i++)
1155 regcache_raw_supply (regcache, i,
1156 XSAVE_XMM_AVX512_ADDR (tdep, regs, i));
1157 }
1158 }
1159 /* Handle the upper YMM registers. */
1160 if ((tdep->xcr0 & X86_XSTATE_AVX))
1161 {
1162 if ((clear_bv & X86_XSTATE_AVX))
1163 {
1164 for (i = I387_YMM0H_REGNUM (tdep);
1165 i < I387_YMMENDH_REGNUM (tdep);
1166 i++)
1167 regcache_raw_supply (regcache, i, zero);
1168 }
1169 else
1170 {
1171 for (i = I387_YMM0H_REGNUM (tdep);
1172 i < I387_YMMENDH_REGNUM (tdep);
1173 i++)
1174 regcache_raw_supply (regcache, i,
1175 XSAVE_AVXH_ADDR (tdep, regs, i));
1176 }
1177 }
1178
1179 /* Handle the MPX registers. */
1180 if ((tdep->xcr0 & X86_XSTATE_BNDREGS))
1181 {
1182 if (clear_bv & X86_XSTATE_BNDREGS)
1183 {
1184 for (i = I387_BND0R_REGNUM (tdep);
1185 i < I387_BNDCFGU_REGNUM (tdep); i++)
1186 regcache_raw_supply (regcache, i, zero);
1187 }
1188 else
1189 {
1190 for (i = I387_BND0R_REGNUM (tdep);
1191 i < I387_BNDCFGU_REGNUM (tdep); i++)
1192 regcache_raw_supply (regcache, i,
1193 XSAVE_MPX_ADDR (tdep, regs, i));
1194 }
1195 }
1196
1197 /* Handle the MPX registers. */
1198 if ((tdep->xcr0 & X86_XSTATE_BNDCFG))
1199 {
1200 if (clear_bv & X86_XSTATE_BNDCFG)
1201 {
1202 for (i = I387_BNDCFGU_REGNUM (tdep);
1203 i < I387_MPXEND_REGNUM (tdep); i++)
1204 regcache_raw_supply (regcache, i, zero);
1205 }
1206 else
1207 {
1208 for (i = I387_BNDCFGU_REGNUM (tdep);
1209 i < I387_MPXEND_REGNUM (tdep); i++)
1210 regcache_raw_supply (regcache, i,
1211 XSAVE_MPX_ADDR (tdep, regs, i));
1212 }
1213 }
1214
1215 /* Handle the XMM registers. */
1216 if ((tdep->xcr0 & X86_XSTATE_SSE))
1217 {
1218 if ((clear_bv & X86_XSTATE_SSE))
1219 {
1220 for (i = I387_XMM0_REGNUM (tdep);
1221 i < I387_MXCSR_REGNUM (tdep);
1222 i++)
1223 regcache_raw_supply (regcache, i, zero);
1224 }
1225 else
1226 {
1227 for (i = I387_XMM0_REGNUM (tdep);
1228 i < I387_MXCSR_REGNUM (tdep); i++)
1229 regcache_raw_supply (regcache, i,
1230 FXSAVE_ADDR (tdep, regs, i));
1231 }
1232 }
1233
1234 /* Handle the x87 registers. */
1235 if ((tdep->xcr0 & X86_XSTATE_X87))
1236 {
1237 if ((clear_bv & X86_XSTATE_X87))
1238 {
1239 for (i = I387_ST0_REGNUM (tdep);
1240 i < I387_FCTRL_REGNUM (tdep);
1241 i++)
1242 regcache_raw_supply (regcache, i, zero);
1243 }
1244 else
1245 {
1246 for (i = I387_ST0_REGNUM (tdep);
1247 i < I387_FCTRL_REGNUM (tdep);
1248 i++)
1249 regcache_raw_supply (regcache, i, FXSAVE_ADDR (tdep, regs, i));
1250 }
1251 }
1252 break;
1253 }
1254
1255 /* Only handle x87 control registers. */
1256 for (i = I387_FCTRL_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++)
1257 if (regnum == -1 || regnum == i)
1258 {
1259 /* Most of the FPU control registers occupy only 16 bits in
1260 the xsave extended state. Give those a special treatment. */
1261 if (i != I387_FIOFF_REGNUM (tdep)
1262 && i != I387_FOOFF_REGNUM (tdep))
1263 {
1264 gdb_byte val[4];
1265
1266 memcpy (val, FXSAVE_ADDR (tdep, regs, i), 2);
1267 val[2] = val[3] = 0;
1268 if (i == I387_FOP_REGNUM (tdep))
1269 val[1] &= ((1 << 3) - 1);
1270 else if (i== I387_FTAG_REGNUM (tdep))
1271 {
1272 /* The fxsave area contains a simplified version of
1273 the tag word. We have to look at the actual 80-bit
1274 FP data to recreate the traditional i387 tag word. */
1275
1276 unsigned long ftag = 0;
1277 int fpreg;
1278 int top;
1279
1280 top = ((FXSAVE_ADDR (tdep, regs,
1281 I387_FSTAT_REGNUM (tdep)))[1] >> 3);
1282 top &= 0x7;
1283
1284 for (fpreg = 7; fpreg >= 0; fpreg--)
1285 {
1286 int tag;
1287
1288 if (val[0] & (1 << fpreg))
1289 {
1290 int thisreg = (fpreg + 8 - top) % 8
1291 + I387_ST0_REGNUM (tdep);
1292 tag = i387_tag (FXSAVE_ADDR (tdep, regs, thisreg));
1293 }
1294 else
1295 tag = 3; /* Empty */
1296
1297 ftag |= tag << (2 * fpreg);
1298 }
1299 val[0] = ftag & 0xff;
1300 val[1] = (ftag >> 8) & 0xff;
1301 }
1302 regcache_raw_supply (regcache, i, val);
1303 }
1304 else
1305 regcache_raw_supply (regcache, i, FXSAVE_ADDR (tdep, regs, i));
1306 }
1307
1308 if (regnum == I387_MXCSR_REGNUM (tdep) || regnum == -1)
1309 regcache_raw_supply (regcache, I387_MXCSR_REGNUM (tdep),
1310 FXSAVE_MXCSR_ADDR (regs));
1311 }
1312
1313 /* Similar to i387_collect_fxsave, but use XSAVE extended state. */
1314
1315 void
1316 i387_collect_xsave (const struct regcache *regcache, int regnum,
1317 void *xsave, int gcore)
1318 {
1319 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1320 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1321 gdb_byte *regs = (gdb_byte *) xsave;
1322 int i;
1323 enum
1324 {
1325 none = 0x0,
1326 check = 0x1,
1327 x87 = 0x2 | check,
1328 sse = 0x4 | check,
1329 avxh = 0x8 | check,
1330 mpx = 0x10 | check,
1331 avx512_k = 0x20 | check,
1332 avx512_zmm_h = 0x40 | check,
1333 avx512_ymmh_avx512 = 0x80 | check,
1334 avx512_xmm_avx512 = 0x100 | check,
1335 pkeys = 0x200 | check,
1336 all = x87 | sse | avxh | mpx | avx512_k | avx512_zmm_h
1337 | avx512_ymmh_avx512 | avx512_xmm_avx512 | pkeys
1338 } regclass;
1339
1340 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
1341 gdb_assert (tdep->num_xmm_regs > 0);
1342
1343 if (regnum == -1)
1344 regclass = all;
1345 else if (regnum >= I387_PKRU_REGNUM (tdep)
1346 && regnum < I387_PKEYSEND_REGNUM (tdep))
1347 regclass = pkeys;
1348 else if (regnum >= I387_ZMM0H_REGNUM (tdep)
1349 && regnum < I387_ZMMENDH_REGNUM (tdep))
1350 regclass = avx512_zmm_h;
1351 else if (regnum >= I387_K0_REGNUM (tdep)
1352 && regnum < I387_KEND_REGNUM (tdep))
1353 regclass = avx512_k;
1354 else if (regnum >= I387_YMM16H_REGNUM (tdep)
1355 && regnum < I387_YMMH_AVX512_END_REGNUM (tdep))
1356 regclass = avx512_ymmh_avx512;
1357 else if (regnum >= I387_XMM16_REGNUM (tdep)
1358 && regnum < I387_XMM_AVX512_END_REGNUM (tdep))
1359 regclass = avx512_xmm_avx512;
1360 else if (regnum >= I387_YMM0H_REGNUM (tdep)
1361 && regnum < I387_YMMENDH_REGNUM (tdep))
1362 regclass = avxh;
1363 else if (regnum >= I387_BND0R_REGNUM (tdep)
1364 && regnum < I387_MPXEND_REGNUM (tdep))
1365 regclass = mpx;
1366 else if (regnum >= I387_XMM0_REGNUM (tdep)
1367 && regnum < I387_MXCSR_REGNUM (tdep))
1368 regclass = sse;
1369 else if (regnum >= I387_ST0_REGNUM (tdep)
1370 && regnum < I387_FCTRL_REGNUM (tdep))
1371 regclass = x87;
1372 else
1373 regclass = none;
1374
1375 if (gcore)
1376 {
1377 /* Clear XSAVE extended state. */
1378 memset (regs, 0, X86_XSTATE_SIZE (tdep->xcr0));
1379
1380 /* Update XCR0 and `xstate_bv' with XCR0 for gcore. */
1381 if (tdep->xsave_xcr0_offset != -1)
1382 memcpy (regs + tdep->xsave_xcr0_offset, &tdep->xcr0, 8);
1383 memcpy (XSAVE_XSTATE_BV_ADDR (regs), &tdep->xcr0, 8);
1384 }
1385
1386 if ((regclass & check))
1387 {
1388 gdb_byte raw[I386_MAX_REGISTER_SIZE];
1389 ULONGEST initial_xstate_bv, clear_bv, xstate_bv = 0;
1390 gdb_byte *p;
1391 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1392
1393 /* The supported bits in `xstat_bv' are 8 bytes. */
1394 initial_xstate_bv = extract_unsigned_integer (XSAVE_XSTATE_BV_ADDR (regs),
1395 8, byte_order);
1396 clear_bv = (~(initial_xstate_bv)) & tdep->xcr0;
1397
1398 /* Clear register set if its bit in xstat_bv is zero. */
1399 if (clear_bv)
1400 {
1401 if ((clear_bv & X86_XSTATE_PKRU))
1402 for (i = I387_PKRU_REGNUM (tdep);
1403 i < I387_PKEYSEND_REGNUM (tdep); i++)
1404 memset (XSAVE_PKEYS_ADDR (tdep, regs, i), 0, 4);
1405
1406 if ((clear_bv & X86_XSTATE_BNDREGS))
1407 for (i = I387_BND0R_REGNUM (tdep);
1408 i < I387_BNDCFGU_REGNUM (tdep); i++)
1409 memset (XSAVE_MPX_ADDR (tdep, regs, i), 0, 16);
1410
1411 if ((clear_bv & X86_XSTATE_BNDCFG))
1412 for (i = I387_BNDCFGU_REGNUM (tdep);
1413 i < I387_MPXEND_REGNUM (tdep); i++)
1414 memset (XSAVE_MPX_ADDR (tdep, regs, i), 0, 8);
1415
1416 if ((clear_bv & (X86_XSTATE_ZMM_H | X86_XSTATE_ZMM)))
1417 for (i = I387_ZMM0H_REGNUM (tdep);
1418 i < I387_ZMMENDH_REGNUM (tdep); i++)
1419 memset (XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, i), 0, 32);
1420
1421 if ((clear_bv & X86_XSTATE_K))
1422 for (i = I387_K0_REGNUM (tdep);
1423 i < I387_KEND_REGNUM (tdep); i++)
1424 memset (XSAVE_AVX512_K_ADDR (tdep, regs, i), 0, 8);
1425
1426 if ((clear_bv & X86_XSTATE_ZMM))
1427 {
1428 for (i = I387_YMM16H_REGNUM (tdep);
1429 i < I387_YMMH_AVX512_END_REGNUM (tdep); i++)
1430 memset (XSAVE_YMM_AVX512_ADDR (tdep, regs, i), 0, 16);
1431 for (i = I387_XMM16_REGNUM (tdep);
1432 i < I387_XMM_AVX512_END_REGNUM (tdep); i++)
1433 memset (XSAVE_XMM_AVX512_ADDR (tdep, regs, i), 0, 16);
1434 }
1435
1436 if ((clear_bv & X86_XSTATE_AVX))
1437 for (i = I387_YMM0H_REGNUM (tdep);
1438 i < I387_YMMENDH_REGNUM (tdep); i++)
1439 memset (XSAVE_AVXH_ADDR (tdep, regs, i), 0, 16);
1440
1441 if ((clear_bv & X86_XSTATE_SSE))
1442 for (i = I387_XMM0_REGNUM (tdep);
1443 i < I387_MXCSR_REGNUM (tdep); i++)
1444 memset (FXSAVE_ADDR (tdep, regs, i), 0, 16);
1445
1446 if ((clear_bv & X86_XSTATE_X87))
1447 for (i = I387_ST0_REGNUM (tdep);
1448 i < I387_FCTRL_REGNUM (tdep); i++)
1449 memset (FXSAVE_ADDR (tdep, regs, i), 0, 10);
1450 }
1451
1452 if (regclass == all)
1453 {
1454 /* Check if any PKEYS registers are changed. */
1455 if ((tdep->xcr0 & X86_XSTATE_PKRU))
1456 for (i = I387_PKRU_REGNUM (tdep);
1457 i < I387_PKEYSEND_REGNUM (tdep); i++)
1458 {
1459 regcache_raw_collect (regcache, i, raw);
1460 p = XSAVE_PKEYS_ADDR (tdep, regs, i);
1461 if (memcmp (raw, p, 4) != 0)
1462 {
1463 xstate_bv |= X86_XSTATE_PKRU;
1464 memcpy (p, raw, 4);
1465 }
1466 }
1467
1468 /* Check if any ZMMH registers are changed. */
1469 if ((tdep->xcr0 & (X86_XSTATE_ZMM_H | X86_XSTATE_ZMM)))
1470 for (i = I387_ZMM0H_REGNUM (tdep);
1471 i < I387_ZMMENDH_REGNUM (tdep); i++)
1472 {
1473 regcache_raw_collect (regcache, i, raw);
1474 p = XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, i);
1475 if (memcmp (raw, p, 32) != 0)
1476 {
1477 xstate_bv |= (X86_XSTATE_ZMM_H | X86_XSTATE_ZMM);
1478 memcpy (p, raw, 32);
1479 }
1480 }
1481
1482 /* Check if any K registers are changed. */
1483 if ((tdep->xcr0 & X86_XSTATE_K))
1484 for (i = I387_K0_REGNUM (tdep);
1485 i < I387_KEND_REGNUM (tdep); i++)
1486 {
1487 regcache_raw_collect (regcache, i, raw);
1488 p = XSAVE_AVX512_K_ADDR (tdep, regs, i);
1489 if (memcmp (raw, p, 8) != 0)
1490 {
1491 xstate_bv |= X86_XSTATE_K;
1492 memcpy (p, raw, 8);
1493 }
1494 }
1495
1496 /* Check if any XMM or upper YMM registers are changed. */
1497 if ((tdep->xcr0 & X86_XSTATE_ZMM))
1498 {
1499 for (i = I387_YMM16H_REGNUM (tdep);
1500 i < I387_YMMH_AVX512_END_REGNUM (tdep); i++)
1501 {
1502 regcache_raw_collect (regcache, i, raw);
1503 p = XSAVE_YMM_AVX512_ADDR (tdep, regs, i);
1504 if (memcmp (raw, p, 16) != 0)
1505 {
1506 xstate_bv |= X86_XSTATE_ZMM;
1507 memcpy (p, raw, 16);
1508 }
1509 }
1510 for (i = I387_XMM16_REGNUM (tdep);
1511 i < I387_XMM_AVX512_END_REGNUM (tdep); i++)
1512 {
1513 regcache_raw_collect (regcache, i, raw);
1514 p = XSAVE_XMM_AVX512_ADDR (tdep, regs, i);
1515 if (memcmp (raw, p, 16) != 0)
1516 {
1517 xstate_bv |= X86_XSTATE_ZMM;
1518 memcpy (p, raw, 16);
1519 }
1520 }
1521 }
1522
1523 /* Check if any upper YMM registers are changed. */
1524 if ((tdep->xcr0 & X86_XSTATE_AVX))
1525 for (i = I387_YMM0H_REGNUM (tdep);
1526 i < I387_YMMENDH_REGNUM (tdep); i++)
1527 {
1528 regcache_raw_collect (regcache, i, raw);
1529 p = XSAVE_AVXH_ADDR (tdep, regs, i);
1530 if (memcmp (raw, p, 16))
1531 {
1532 xstate_bv |= X86_XSTATE_AVX;
1533 memcpy (p, raw, 16);
1534 }
1535 }
1536 /* Check if any upper MPX registers are changed. */
1537 if ((tdep->xcr0 & X86_XSTATE_BNDREGS))
1538 for (i = I387_BND0R_REGNUM (tdep);
1539 i < I387_BNDCFGU_REGNUM (tdep); i++)
1540 {
1541 regcache_raw_collect (regcache, i, raw);
1542 p = XSAVE_MPX_ADDR (tdep, regs, i);
1543 if (memcmp (raw, p, 16))
1544 {
1545 xstate_bv |= X86_XSTATE_BNDREGS;
1546 memcpy (p, raw, 16);
1547 }
1548 }
1549
1550 /* Check if any upper MPX registers are changed. */
1551 if ((tdep->xcr0 & X86_XSTATE_BNDCFG))
1552 for (i = I387_BNDCFGU_REGNUM (tdep);
1553 i < I387_MPXEND_REGNUM (tdep); i++)
1554 {
1555 regcache_raw_collect (regcache, i, raw);
1556 p = XSAVE_MPX_ADDR (tdep, regs, i);
1557 if (memcmp (raw, p, 8))
1558 {
1559 xstate_bv |= X86_XSTATE_BNDCFG;
1560 memcpy (p, raw, 8);
1561 }
1562 }
1563
1564 /* Check if any SSE registers are changed. */
1565 if ((tdep->xcr0 & X86_XSTATE_SSE))
1566 for (i = I387_XMM0_REGNUM (tdep);
1567 i < I387_MXCSR_REGNUM (tdep); i++)
1568 {
1569 regcache_raw_collect (regcache, i, raw);
1570 p = FXSAVE_ADDR (tdep, regs, i);
1571 if (memcmp (raw, p, 16))
1572 {
1573 xstate_bv |= X86_XSTATE_SSE;
1574 memcpy (p, raw, 16);
1575 }
1576 }
1577
1578 /* Check if any X87 registers are changed. */
1579 if ((tdep->xcr0 & X86_XSTATE_X87))
1580 for (i = I387_ST0_REGNUM (tdep);
1581 i < I387_FCTRL_REGNUM (tdep); i++)
1582 {
1583 regcache_raw_collect (regcache, i, raw);
1584 p = FXSAVE_ADDR (tdep, regs, i);
1585 if (memcmp (raw, p, 10))
1586 {
1587 xstate_bv |= X86_XSTATE_X87;
1588 memcpy (p, raw, 10);
1589 }
1590 }
1591 }
1592 else
1593 {
1594 /* Check if REGNUM is changed. */
1595 regcache_raw_collect (regcache, regnum, raw);
1596
1597 switch (regclass)
1598 {
1599 default:
1600 internal_error (__FILE__, __LINE__,
1601 _("invalid i387 regclass"));
1602
1603 case pkeys:
1604 /* This is a PKEYS register. */
1605 p = XSAVE_PKEYS_ADDR (tdep, regs, regnum);
1606 if (memcmp (raw, p, 4) != 0)
1607 {
1608 xstate_bv |= X86_XSTATE_PKRU;
1609 memcpy (p, raw, 4);
1610 }
1611 break;
1612
1613 case avx512_zmm_h:
1614 /* This is a ZMM register. */
1615 p = XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, regnum);
1616 if (memcmp (raw, p, 32) != 0)
1617 {
1618 xstate_bv |= (X86_XSTATE_ZMM_H | X86_XSTATE_ZMM);
1619 memcpy (p, raw, 32);
1620 }
1621 break;
1622 case avx512_k:
1623 /* This is a AVX512 mask register. */
1624 p = XSAVE_AVX512_K_ADDR (tdep, regs, regnum);
1625 if (memcmp (raw, p, 8) != 0)
1626 {
1627 xstate_bv |= X86_XSTATE_K;
1628 memcpy (p, raw, 8);
1629 }
1630 break;
1631
1632 case avx512_ymmh_avx512:
1633 /* This is an upper YMM16-31 register. */
1634 p = XSAVE_YMM_AVX512_ADDR (tdep, regs, regnum);
1635 if (memcmp (raw, p, 16) != 0)
1636 {
1637 xstate_bv |= X86_XSTATE_ZMM;
1638 memcpy (p, raw, 16);
1639 }
1640 break;
1641
1642 case avx512_xmm_avx512:
1643 /* This is an upper XMM16-31 register. */
1644 p = XSAVE_XMM_AVX512_ADDR (tdep, regs, regnum);
1645 if (memcmp (raw, p, 16) != 0)
1646 {
1647 xstate_bv |= X86_XSTATE_ZMM;
1648 memcpy (p, raw, 16);
1649 }
1650 break;
1651
1652 case avxh:
1653 /* This is an upper YMM register. */
1654 p = XSAVE_AVXH_ADDR (tdep, regs, regnum);
1655 if (memcmp (raw, p, 16))
1656 {
1657 xstate_bv |= X86_XSTATE_AVX;
1658 memcpy (p, raw, 16);
1659 }
1660 break;
1661
1662 case mpx:
1663 if (regnum < I387_BNDCFGU_REGNUM (tdep))
1664 {
1665 regcache_raw_collect (regcache, regnum, raw);
1666 p = XSAVE_MPX_ADDR (tdep, regs, regnum);
1667 if (memcmp (raw, p, 16))
1668 {
1669 xstate_bv |= X86_XSTATE_BNDREGS;
1670 memcpy (p, raw, 16);
1671 }
1672 }
1673 else
1674 {
1675 p = XSAVE_MPX_ADDR (tdep, regs, regnum);
1676 xstate_bv |= X86_XSTATE_BNDCFG;
1677 memcpy (p, raw, 8);
1678 }
1679 break;
1680
1681 case sse:
1682 /* This is an SSE register. */
1683 p = FXSAVE_ADDR (tdep, regs, regnum);
1684 if (memcmp (raw, p, 16))
1685 {
1686 xstate_bv |= X86_XSTATE_SSE;
1687 memcpy (p, raw, 16);
1688 }
1689 break;
1690
1691 case x87:
1692 /* This is an x87 register. */
1693 p = FXSAVE_ADDR (tdep, regs, regnum);
1694 if (memcmp (raw, p, 10))
1695 {
1696 xstate_bv |= X86_XSTATE_X87;
1697 memcpy (p, raw, 10);
1698 }
1699 break;
1700 }
1701 }
1702
1703 /* Update the corresponding bits in `xstate_bv' if any SSE/AVX
1704 registers are changed. */
1705 if (xstate_bv)
1706 {
1707 /* The supported bits in `xstat_bv' are 8 bytes. */
1708 initial_xstate_bv |= xstate_bv;
1709 store_unsigned_integer (XSAVE_XSTATE_BV_ADDR (regs),
1710 8, byte_order,
1711 initial_xstate_bv);
1712
1713 switch (regclass)
1714 {
1715 default:
1716 internal_error (__FILE__, __LINE__,
1717 _("invalid i387 regclass"));
1718
1719 case all:
1720 break;
1721
1722 case x87:
1723 case sse:
1724 case avxh:
1725 case mpx:
1726 case avx512_k:
1727 case avx512_zmm_h:
1728 case avx512_ymmh_avx512:
1729 case avx512_xmm_avx512:
1730 case pkeys:
1731 /* Register REGNUM has been updated. Return. */
1732 return;
1733 }
1734 }
1735 else
1736 {
1737 /* Return if REGNUM isn't changed. */
1738 if (regclass != all)
1739 return;
1740 }
1741 }
1742
1743 /* Only handle x87 control registers. */
1744 for (i = I387_FCTRL_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++)
1745 if (regnum == -1 || regnum == i)
1746 {
1747 /* Most of the FPU control registers occupy only 16 bits in
1748 the xsave extended state. Give those a special treatment. */
1749 if (i != I387_FIOFF_REGNUM (tdep)
1750 && i != I387_FOOFF_REGNUM (tdep))
1751 {
1752 gdb_byte buf[4];
1753
1754 regcache_raw_collect (regcache, i, buf);
1755
1756 if (i == I387_FOP_REGNUM (tdep))
1757 {
1758 /* The opcode occupies only 11 bits. Make sure we
1759 don't touch the other bits. */
1760 buf[1] &= ((1 << 3) - 1);
1761 buf[1] |= ((FXSAVE_ADDR (tdep, regs, i))[1] & ~((1 << 3) - 1));
1762 }
1763 else if (i == I387_FTAG_REGNUM (tdep))
1764 {
1765 /* Converting back is much easier. */
1766
1767 unsigned short ftag;
1768 int fpreg;
1769
1770 ftag = (buf[1] << 8) | buf[0];
1771 buf[0] = 0;
1772 buf[1] = 0;
1773
1774 for (fpreg = 7; fpreg >= 0; fpreg--)
1775 {
1776 int tag = (ftag >> (fpreg * 2)) & 3;
1777
1778 if (tag != 3)
1779 buf[0] |= (1 << fpreg);
1780 }
1781 }
1782 memcpy (FXSAVE_ADDR (tdep, regs, i), buf, 2);
1783 }
1784 else
1785 regcache_raw_collect (regcache, i, FXSAVE_ADDR (tdep, regs, i));
1786 }
1787
1788 if (regnum == I387_MXCSR_REGNUM (tdep) || regnum == -1)
1789 regcache_raw_collect (regcache, I387_MXCSR_REGNUM (tdep),
1790 FXSAVE_MXCSR_ADDR (regs));
1791 }
1792
1793 /* Recreate the FTW (tag word) valid bits from the 80-bit FP data in
1794 *RAW. */
1795
1796 static int
1797 i387_tag (const gdb_byte *raw)
1798 {
1799 int integer;
1800 unsigned int exponent;
1801 unsigned long fraction[2];
1802
1803 integer = raw[7] & 0x80;
1804 exponent = (((raw[9] & 0x7f) << 8) | raw[8]);
1805 fraction[0] = ((raw[3] << 24) | (raw[2] << 16) | (raw[1] << 8) | raw[0]);
1806 fraction[1] = (((raw[7] & 0x7f) << 24) | (raw[6] << 16)
1807 | (raw[5] << 8) | raw[4]);
1808
1809 if (exponent == 0x7fff)
1810 {
1811 /* Special. */
1812 return (2);
1813 }
1814 else if (exponent == 0x0000)
1815 {
1816 if (fraction[0] == 0x0000 && fraction[1] == 0x0000 && !integer)
1817 {
1818 /* Zero. */
1819 return (1);
1820 }
1821 else
1822 {
1823 /* Special. */
1824 return (2);
1825 }
1826 }
1827 else
1828 {
1829 if (integer)
1830 {
1831 /* Valid. */
1832 return (0);
1833 }
1834 else
1835 {
1836 /* Special. */
1837 return (2);
1838 }
1839 }
1840 }
1841
1842 /* Prepare the FPU stack in REGCACHE for a function return. */
1843
1844 void
1845 i387_return_value (struct gdbarch *gdbarch, struct regcache *regcache)
1846 {
1847 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1848 ULONGEST fstat;
1849
1850 /* Set the top of the floating-point register stack to 7. The
1851 actual value doesn't really matter, but 7 is what a normal
1852 function return would end up with if the program started out with
1853 a freshly initialized FPU. */
1854 regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat);
1855 fstat |= (7 << 11);
1856 regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat);
1857
1858 /* Mark %st(1) through %st(7) as empty. Since we set the top of the
1859 floating-point register stack to 7, the appropriate value for the
1860 tag word is 0x3fff. */
1861 regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff);
1862
1863 }
1864
1865 /* See i387-tdep.h. */
1866
1867 void
1868 i387_reset_bnd_regs (struct gdbarch *gdbarch, struct regcache *regcache)
1869 {
1870 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1871
1872 if (I387_BND0R_REGNUM (tdep) > 0)
1873 {
1874 gdb_byte bnd_buf[16];
1875
1876 memset (bnd_buf, 0, 16);
1877 for (int i = 0; i < I387_NUM_BND_REGS; i++)
1878 regcache_raw_write (regcache, I387_BND0R_REGNUM (tdep) + i, bnd_buf);
1879 }
1880 }
GDB Binutils - Deliverables
This page took 0.068206 seconds and 4 git commands to generate.