projects / deliverable / binutils-gdb.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Include gdb_assert.h in common-defs.h
[deliverable/binutils-gdb.git] / gdb / i387-tdep.c
1 /* Intel 387 floating point stuff.
2
3 Copyright (C) 1988-2014 Free Software Foundation, Inc.
4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
19
20 #include "defs.h"
21 #include "doublest.h"
22 #include "floatformat.h"
23 #include "frame.h"
24 #include "gdbcore.h"
25 #include "inferior.h"
26 #include "language.h"
27 #include "regcache.h"
28 #include "value.h"
29
30 #include <string.h>
31
32 #include "i386-tdep.h"
33 #include "i387-tdep.h"
34 #include "i386-xstate.h"
35
36 /* Print the floating point number specified by RAW. */
37
38 static void
39 print_i387_value (struct gdbarch *gdbarch,
40 const gdb_byte *raw, struct ui_file *file)
41 {
42 DOUBLEST value;
43
44 /* Using extract_typed_floating here might affect the representation
45 of certain numbers such as NaNs, even if GDB is running natively.
46 This is fine since our caller already detects such special
47 numbers and we print the hexadecimal representation anyway. */
48 value = extract_typed_floating (raw, i387_ext_type (gdbarch));
49
50 /* We try to print 19 digits. The last digit may or may not contain
51 garbage, but we'd better print one too many. We need enough room
52 to print the value, 1 position for the sign, 1 for the decimal
53 point, 19 for the digits and 6 for the exponent adds up to 27. */
54 #ifdef PRINTF_HAS_LONG_DOUBLE
55 fprintf_filtered (file, " %-+27.19Lg", (long double) value);
56 #else
57 fprintf_filtered (file, " %-+27.19g", (double) value);
58 #endif
59 }
60
61 /* Print the classification for the register contents RAW. */
62
63 static void
64 print_i387_ext (struct gdbarch *gdbarch,
65 const gdb_byte *raw, struct ui_file *file)
66 {
67 int sign;
68 int integer;
69 unsigned int exponent;
70 unsigned long fraction[2];
71
72 sign = raw[9] & 0x80;
73 integer = raw[7] & 0x80;
74 exponent = (((raw[9] & 0x7f) << 8) | raw[8]);
75 fraction[0] = ((raw[3] << 24) | (raw[2] << 16) | (raw[1] << 8) | raw[0]);
76 fraction[1] = (((raw[7] & 0x7f) << 24) | (raw[6] << 16)
77 | (raw[5] << 8) | raw[4]);
78
79 if (exponent == 0x7fff && integer)
80 {
81 if (fraction[0] == 0x00000000 && fraction[1] == 0x00000000)
82 /* Infinity. */
83 fprintf_filtered (file, " %cInf", (sign ? '-' : '+'));
84 else if (sign && fraction[0] == 0x00000000 && fraction[1] == 0x40000000)
85 /* Real Indefinite (QNaN). */
86 fputs_unfiltered (" Real Indefinite (QNaN)", file);
87 else if (fraction[1] & 0x40000000)
88 /* QNaN. */
89 fputs_filtered (" QNaN", file);
90 else
91 /* SNaN. */
92 fputs_filtered (" SNaN", file);
93 }
94 else if (exponent < 0x7fff && exponent > 0x0000 && integer)
95 /* Normal. */
96 print_i387_value (gdbarch, raw, file);
97 else if (exponent == 0x0000)
98 {
99 /* Denormal or zero. */
100 print_i387_value (gdbarch, raw, file);
101
102 if (integer)
103 /* Pseudo-denormal. */
104 fputs_filtered (" Pseudo-denormal", file);
105 else if (fraction[0] || fraction[1])
106 /* Denormal. */
107 fputs_filtered (" Denormal", file);
108 }
109 else
110 /* Unsupported. */
111 fputs_filtered (" Unsupported", file);
112 }
113
114 /* Print the status word STATUS. If STATUS_P is false, then STATUS
115 was unavailable. */
116
117 static void
118 print_i387_status_word (int status_p,
119 unsigned int status, struct ui_file *file)
120 {
121 fprintf_filtered (file, "Status Word: ");
122 if (!status_p)
123 {
124 fprintf_filtered (file, "%s\n", _("<unavailable>"));
125 return;
126 }
127
128 fprintf_filtered (file, "%s", hex_string_custom (status, 4));
129 fputs_filtered (" ", file);
130 fprintf_filtered (file, " %s", (status & 0x0001) ? "IE" : " ");
131 fprintf_filtered (file, " %s", (status & 0x0002) ? "DE" : " ");
132 fprintf_filtered (file, " %s", (status & 0x0004) ? "ZE" : " ");
133 fprintf_filtered (file, " %s", (status & 0x0008) ? "OE" : " ");
134 fprintf_filtered (file, " %s", (status & 0x0010) ? "UE" : " ");
135 fprintf_filtered (file, " %s", (status & 0x0020) ? "PE" : " ");
136 fputs_filtered (" ", file);
137 fprintf_filtered (file, " %s", (status & 0x0080) ? "ES" : " ");
138 fputs_filtered (" ", file);
139 fprintf_filtered (file, " %s", (status & 0x0040) ? "SF" : " ");
140 fputs_filtered (" ", file);
141 fprintf_filtered (file, " %s", (status & 0x0100) ? "C0" : " ");
142 fprintf_filtered (file, " %s", (status & 0x0200) ? "C1" : " ");
143 fprintf_filtered (file, " %s", (status & 0x0400) ? "C2" : " ");
144 fprintf_filtered (file, " %s", (status & 0x4000) ? "C3" : " ");
145
146 fputs_filtered ("\n", file);
147
148 fprintf_filtered (file,
149 " TOP: %d\n", ((status >> 11) & 7));
150 }
151
152 /* Print the control word CONTROL. If CONTROL_P is false, then
153 CONTROL was unavailable. */
154
155 static void
156 print_i387_control_word (int control_p,
157 unsigned int control, struct ui_file *file)
158 {
159 fprintf_filtered (file, "Control Word: ");
160 if (!control_p)
161 {
162 fprintf_filtered (file, "%s\n", _("<unavailable>"));
163 return;
164 }
165
166 fprintf_filtered (file, "%s", hex_string_custom (control, 4));
167 fputs_filtered (" ", file);
168 fprintf_filtered (file, " %s", (control & 0x0001) ? "IM" : " ");
169 fprintf_filtered (file, " %s", (control & 0x0002) ? "DM" : " ");
170 fprintf_filtered (file, " %s", (control & 0x0004) ? "ZM" : " ");
171 fprintf_filtered (file, " %s", (control & 0x0008) ? "OM" : " ");
172 fprintf_filtered (file, " %s", (control & 0x0010) ? "UM" : " ");
173 fprintf_filtered (file, " %s", (control & 0x0020) ? "PM" : " ");
174
175 fputs_filtered ("\n", file);
176
177 fputs_filtered (" PC: ", file);
178 switch ((control >> 8) & 3)
179 {
180 case 0:
181 fputs_filtered ("Single Precision (24-bits)\n", file);
182 break;
183 case 1:
184 fputs_filtered ("Reserved\n", file);
185 break;
186 case 2:
187 fputs_filtered ("Double Precision (53-bits)\n", file);
188 break;
189 case 3:
190 fputs_filtered ("Extended Precision (64-bits)\n", file);
191 break;
192 }
193
194 fputs_filtered (" RC: ", file);
195 switch ((control >> 10) & 3)
196 {
197 case 0:
198 fputs_filtered ("Round to nearest\n", file);
199 break;
200 case 1:
201 fputs_filtered ("Round down\n", file);
202 break;
203 case 2:
204 fputs_filtered ("Round up\n", file);
205 break;
206 case 3:
207 fputs_filtered ("Round toward zero\n", file);
208 break;
209 }
210 }
211
212 /* Print out the i387 floating point state. Note that we ignore FRAME
213 in the code below. That's OK since floating-point registers are
214 never saved on the stack. */
215
216 void
217 i387_print_float_info (struct gdbarch *gdbarch, struct ui_file *file,
218 struct frame_info *frame, const char *args)
219 {
220 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (frame));
221 ULONGEST fctrl;
222 int fctrl_p;
223 ULONGEST fstat;
224 int fstat_p;
225 ULONGEST ftag;
226 int ftag_p;
227 ULONGEST fiseg;
228 int fiseg_p;
229 ULONGEST fioff;
230 int fioff_p;
231 ULONGEST foseg;
232 int foseg_p;
233 ULONGEST fooff;
234 int fooff_p;
235 ULONGEST fop;
236 int fop_p;
237 int fpreg;
238 int top;
239
240 gdb_assert (gdbarch == get_frame_arch (frame));
241
242 fctrl_p = read_frame_register_unsigned (frame,
243 I387_FCTRL_REGNUM (tdep), &fctrl);
244 fstat_p = read_frame_register_unsigned (frame,
245 I387_FSTAT_REGNUM (tdep), &fstat);
246 ftag_p = read_frame_register_unsigned (frame,
247 I387_FTAG_REGNUM (tdep), &ftag);
248 fiseg_p = read_frame_register_unsigned (frame,
249 I387_FISEG_REGNUM (tdep), &fiseg);
250 fioff_p = read_frame_register_unsigned (frame,
251 I387_FIOFF_REGNUM (tdep), &fioff);
252 foseg_p = read_frame_register_unsigned (frame,
253 I387_FOSEG_REGNUM (tdep), &foseg);
254 fooff_p = read_frame_register_unsigned (frame,
255 I387_FOOFF_REGNUM (tdep), &fooff);
256 fop_p = read_frame_register_unsigned (frame,
257 I387_FOP_REGNUM (tdep), &fop);
258
259 if (fstat_p)
260 {
261 top = ((fstat >> 11) & 7);
262
263 for (fpreg = 7; fpreg >= 0; fpreg--)
264 {
265 struct value *regval;
266 int regnum;
267 int i;
268 int tag = -1;
269
270 fprintf_filtered (file, "%sR%d: ", fpreg == top ? "=>" : " ", fpreg);
271
272 if (ftag_p)
273 {
274 tag = (ftag >> (fpreg * 2)) & 3;
275
276 switch (tag)
277 {
278 case 0:
279 fputs_filtered ("Valid ", file);
280 break;
281 case 1:
282 fputs_filtered ("Zero ", file);
283 break;
284 case 2:
285 fputs_filtered ("Special ", file);
286 break;
287 case 3:
288 fputs_filtered ("Empty ", file);
289 break;
290 }
291 }
292 else
293 fputs_filtered ("Unknown ", file);
294
295 regnum = (fpreg + 8 - top) % 8 + I387_ST0_REGNUM (tdep);
296 regval = get_frame_register_value (frame, regnum);
297
298 if (value_entirely_available (regval))
299 {
300 const gdb_byte *raw = value_contents (regval);
301
302 fputs_filtered ("0x", file);
303 for (i = 9; i >= 0; i--)
304 fprintf_filtered (file, "%02x", raw[i]);
305
306 if (tag != -1 && tag != 3)
307 print_i387_ext (gdbarch, raw, file);
308 }
309 else
310 fprintf_filtered (file, "%s", _("<unavailable>"));
311
312 fputs_filtered ("\n", file);
313 }
314 }
315
316 fputs_filtered ("\n", file);
317 print_i387_status_word (fstat_p, fstat, file);
318 print_i387_control_word (fctrl_p, fctrl, file);
319 fprintf_filtered (file, "Tag Word: %s\n",
320 ftag_p ? hex_string_custom (ftag, 4) : _("<unavailable>"));
321 fprintf_filtered (file, "Instruction Pointer: %s:",
322 fiseg_p ? hex_string_custom (fiseg, 2) : _("<unavailable>"));
323 fprintf_filtered (file, "%s\n",
324 fioff_p ? hex_string_custom (fioff, 8) : _("<unavailable>"));
325 fprintf_filtered (file, "Operand Pointer: %s:",
326 foseg_p ? hex_string_custom (foseg, 2) : _("<unavailable>"));
327 fprintf_filtered (file, "%s\n",
328 fooff_p ? hex_string_custom (fooff, 8) : _("<unavailable>"));
329 fprintf_filtered (file, "Opcode: %s\n",
330 fop_p
331 ? (hex_string_custom (fop ? (fop | 0xd800) : 0, 4))
332 : _("<unavailable>"));
333 }
334 \f
335
336 /* Return nonzero if a value of type TYPE stored in register REGNUM
337 needs any special handling. */
338
339 int
340 i387_convert_register_p (struct gdbarch *gdbarch, int regnum,
341 struct type *type)
342 {
343 if (i386_fp_regnum_p (gdbarch, regnum))
344 {
345 /* Floating point registers must be converted unless we are
346 accessing them in their hardware type. */
347 if (type == i387_ext_type (gdbarch))
348 return 0;
349 else
350 return 1;
351 }
352
353 return 0;
354 }
355
356 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
357 return its contents in TO. */
358
359 int
360 i387_register_to_value (struct frame_info *frame, int regnum,
361 struct type *type, gdb_byte *to,
362 int *optimizedp, int *unavailablep)
363 {
364 struct gdbarch *gdbarch = get_frame_arch (frame);
365 gdb_byte from[I386_MAX_REGISTER_SIZE];
366
367 gdb_assert (i386_fp_regnum_p (gdbarch, regnum));
368
369 /* We only support floating-point values. */
370 if (TYPE_CODE (type) != TYPE_CODE_FLT)
371 {
372 warning (_("Cannot convert floating-point register value "
373 "to non-floating-point type."));
374 *optimizedp = *unavailablep = 0;
375 return 0;
376 }
377
378 /* Convert to TYPE. */
379 if (!get_frame_register_bytes (frame, regnum, 0, TYPE_LENGTH (type),
380 from, optimizedp, unavailablep))
381 return 0;
382
383 convert_typed_floating (from, i387_ext_type (gdbarch), to, type);
384 *optimizedp = *unavailablep = 0;
385 return 1;
386 }
387
388 /* Write the contents FROM of a value of type TYPE into register
389 REGNUM in frame FRAME. */
390
391 void
392 i387_value_to_register (struct frame_info *frame, int regnum,
393 struct type *type, const gdb_byte *from)
394 {
395 struct gdbarch *gdbarch = get_frame_arch (frame);
396 gdb_byte to[I386_MAX_REGISTER_SIZE];
397
398 gdb_assert (i386_fp_regnum_p (gdbarch, regnum));
399
400 /* We only support floating-point values. */
401 if (TYPE_CODE (type) != TYPE_CODE_FLT)
402 {
403 warning (_("Cannot convert non-floating-point type "
404 "to floating-point register value."));
405 return;
406 }
407
408 /* Convert from TYPE. */
409 convert_typed_floating (from, type, to, i387_ext_type (gdbarch));
410 put_frame_register (frame, regnum, to);
411 }
412 \f
413
414 /* Handle FSAVE and FXSAVE formats. */
415
416 /* At fsave_offset[REGNUM] you'll find the offset to the location in
417 the data structure used by the "fsave" instruction where GDB
418 register REGNUM is stored. */
419
420 static int fsave_offset[] =
421 {
422 28 + 0 * 10, /* %st(0) ... */
423 28 + 1 * 10,
424 28 + 2 * 10,
425 28 + 3 * 10,
426 28 + 4 * 10,
427 28 + 5 * 10,
428 28 + 6 * 10,
429 28 + 7 * 10, /* ... %st(7). */
430 0, /* `fctrl' (16 bits). */
431 4, /* `fstat' (16 bits). */
432 8, /* `ftag' (16 bits). */
433 16, /* `fiseg' (16 bits). */
434 12, /* `fioff'. */
435 24, /* `foseg' (16 bits). */
436 20, /* `fooff'. */
437 18 /* `fop' (bottom 11 bits). */
438 };
439
440 #define FSAVE_ADDR(tdep, fsave, regnum) \
441 (fsave + fsave_offset[regnum - I387_ST0_REGNUM (tdep)])
442 \f
443
444 /* Fill register REGNUM in REGCACHE with the appropriate value from
445 *FSAVE. This function masks off any of the reserved bits in
446 *FSAVE. */
447
448 void
449 i387_supply_fsave (struct regcache *regcache, int regnum, const void *fsave)
450 {
451 struct gdbarch *gdbarch = get_regcache_arch (regcache);
452 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
453 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
454 const gdb_byte *regs = fsave;
455 int i;
456
457 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
458
459 for (i = I387_ST0_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++)
460 if (regnum == -1 || regnum == i)
461 {
462 if (fsave == NULL)
463 {
464 regcache_raw_supply (regcache, i, NULL);
465 continue;
466 }
467
468 /* Most of the FPU control registers occupy only 16 bits in the
469 fsave area. Give those a special treatment. */
470 if (i >= I387_FCTRL_REGNUM (tdep)
471 && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep))
472 {
473 gdb_byte val[4];
474
475 memcpy (val, FSAVE_ADDR (tdep, regs, i), 2);
476 val[2] = val[3] = 0;
477 if (i == I387_FOP_REGNUM (tdep))
478 val[1] &= ((1 << 3) - 1);
479 regcache_raw_supply (regcache, i, val);
480 }
481 else
482 regcache_raw_supply (regcache, i, FSAVE_ADDR (tdep, regs, i));
483 }
484
485 /* Provide dummy values for the SSE registers. */
486 for (i = I387_XMM0_REGNUM (tdep); i < I387_MXCSR_REGNUM (tdep); i++)
487 if (regnum == -1 || regnum == i)
488 regcache_raw_supply (regcache, i, NULL);
489 if (regnum == -1 || regnum == I387_MXCSR_REGNUM (tdep))
490 {
491 gdb_byte buf[4];
492
493 store_unsigned_integer (buf, 4, byte_order, 0x1f80);
494 regcache_raw_supply (regcache, I387_MXCSR_REGNUM (tdep), buf);
495 }
496 }
497
498 /* Fill register REGNUM (if it is a floating-point register) in *FSAVE
499 with the value from REGCACHE. If REGNUM is -1, do this for all
500 registers. This function doesn't touch any of the reserved bits in
501 *FSAVE. */
502
503 void
504 i387_collect_fsave (const struct regcache *regcache, int regnum, void *fsave)
505 {
506 struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache));
507 gdb_byte *regs = fsave;
508 int i;
509
510 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
511
512 for (i = I387_ST0_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++)
513 if (regnum == -1 || regnum == i)
514 {
515 /* Most of the FPU control registers occupy only 16 bits in
516 the fsave area. Give those a special treatment. */
517 if (i >= I387_FCTRL_REGNUM (tdep)
518 && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep))
519 {
520 gdb_byte buf[4];
521
522 regcache_raw_collect (regcache, i, buf);
523
524 if (i == I387_FOP_REGNUM (tdep))
525 {
526 /* The opcode occupies only 11 bits. Make sure we
527 don't touch the other bits. */
528 buf[1] &= ((1 << 3) - 1);
529 buf[1] |= ((FSAVE_ADDR (tdep, regs, i))[1] & ~((1 << 3) - 1));
530 }
531 memcpy (FSAVE_ADDR (tdep, regs, i), buf, 2);
532 }
533 else
534 regcache_raw_collect (regcache, i, FSAVE_ADDR (tdep, regs, i));
535 }
536 }
537 \f
538
539 /* At fxsave_offset[REGNUM] you'll find the offset to the location in
540 the data structure used by the "fxsave" instruction where GDB
541 register REGNUM is stored. */
542
543 static int fxsave_offset[] =
544 {
545 32, /* %st(0) through ... */
546 48,
547 64,
548 80,
549 96,
550 112,
551 128,
552 144, /* ... %st(7) (80 bits each). */
553 0, /* `fctrl' (16 bits). */
554 2, /* `fstat' (16 bits). */
555 4, /* `ftag' (16 bits). */
556 12, /* `fiseg' (16 bits). */
557 8, /* `fioff'. */
558 20, /* `foseg' (16 bits). */
559 16, /* `fooff'. */
560 6, /* `fop' (bottom 11 bits). */
561 160 + 0 * 16, /* %xmm0 through ... */
562 160 + 1 * 16,
563 160 + 2 * 16,
564 160 + 3 * 16,
565 160 + 4 * 16,
566 160 + 5 * 16,
567 160 + 6 * 16,
568 160 + 7 * 16,
569 160 + 8 * 16,
570 160 + 9 * 16,
571 160 + 10 * 16,
572 160 + 11 * 16,
573 160 + 12 * 16,
574 160 + 13 * 16,
575 160 + 14 * 16,
576 160 + 15 * 16, /* ... %xmm15 (128 bits each). */
577 };
578
579 #define FXSAVE_ADDR(tdep, fxsave, regnum) \
580 (fxsave + fxsave_offset[regnum - I387_ST0_REGNUM (tdep)])
581
582 /* We made an unfortunate choice in putting %mxcsr after the SSE
583 registers %xmm0-%xmm7 instead of before, since it makes supporting
584 the registers %xmm8-%xmm15 on AMD64 a bit involved. Therefore we
585 don't include the offset for %mxcsr here above. */
586
587 #define FXSAVE_MXCSR_ADDR(fxsave) (fxsave + 24)
588
589 static int i387_tag (const gdb_byte *raw);
590 \f
591
592 /* Fill register REGNUM in REGCACHE with the appropriate
593 floating-point or SSE register value from *FXSAVE. This function
594 masks off any of the reserved bits in *FXSAVE. */
595
596 void
597 i387_supply_fxsave (struct regcache *regcache, int regnum, const void *fxsave)
598 {
599 struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache));
600 const gdb_byte *regs = fxsave;
601 int i;
602
603 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
604 gdb_assert (tdep->num_xmm_regs > 0);
605
606 for (i = I387_ST0_REGNUM (tdep); i < I387_MXCSR_REGNUM (tdep); i++)
607 if (regnum == -1 || regnum == i)
608 {
609 if (regs == NULL)
610 {
611 regcache_raw_supply (regcache, i, NULL);
612 continue;
613 }
614
615 /* Most of the FPU control registers occupy only 16 bits in
616 the fxsave area. Give those a special treatment. */
617 if (i >= I387_FCTRL_REGNUM (tdep) && i < I387_XMM0_REGNUM (tdep)
618 && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep))
619 {
620 gdb_byte val[4];
621
622 memcpy (val, FXSAVE_ADDR (tdep, regs, i), 2);
623 val[2] = val[3] = 0;
624 if (i == I387_FOP_REGNUM (tdep))
625 val[1] &= ((1 << 3) - 1);
626 else if (i== I387_FTAG_REGNUM (tdep))
627 {
628 /* The fxsave area contains a simplified version of
629 the tag word. We have to look at the actual 80-bit
630 FP data to recreate the traditional i387 tag word. */
631
632 unsigned long ftag = 0;
633 int fpreg;
634 int top;
635
636 top = ((FXSAVE_ADDR (tdep, regs,
637 I387_FSTAT_REGNUM (tdep)))[1] >> 3);
638 top &= 0x7;
639
640 for (fpreg = 7; fpreg >= 0; fpreg--)
641 {
642 int tag;
643
644 if (val[0] & (1 << fpreg))
645 {
646 int thisreg = (fpreg + 8 - top) % 8
647 + I387_ST0_REGNUM (tdep);
648 tag = i387_tag (FXSAVE_ADDR (tdep, regs, thisreg));
649 }
650 else
651 tag = 3; /* Empty */
652
653 ftag |= tag << (2 * fpreg);
654 }
655 val[0] = ftag & 0xff;
656 val[1] = (ftag >> 8) & 0xff;
657 }
658 regcache_raw_supply (regcache, i, val);
659 }
660 else
661 regcache_raw_supply (regcache, i, FXSAVE_ADDR (tdep, regs, i));
662 }
663
664 if (regnum == I387_MXCSR_REGNUM (tdep) || regnum == -1)
665 {
666 if (regs == NULL)
667 regcache_raw_supply (regcache, I387_MXCSR_REGNUM (tdep), NULL);
668 else
669 regcache_raw_supply (regcache, I387_MXCSR_REGNUM (tdep),
670 FXSAVE_MXCSR_ADDR (regs));
671 }
672 }
673
674 /* Fill register REGNUM (if it is a floating-point or SSE register) in
675 *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for
676 all registers. This function doesn't touch any of the reserved
677 bits in *FXSAVE. */
678
679 void
680 i387_collect_fxsave (const struct regcache *regcache, int regnum, void *fxsave)
681 {
682 struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache));
683 gdb_byte *regs = fxsave;
684 int i;
685
686 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
687 gdb_assert (tdep->num_xmm_regs > 0);
688
689 for (i = I387_ST0_REGNUM (tdep); i < I387_MXCSR_REGNUM (tdep); i++)
690 if (regnum == -1 || regnum == i)
691 {
692 /* Most of the FPU control registers occupy only 16 bits in
693 the fxsave area. Give those a special treatment. */
694 if (i >= I387_FCTRL_REGNUM (tdep) && i < I387_XMM0_REGNUM (tdep)
695 && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep))
696 {
697 gdb_byte buf[4];
698
699 regcache_raw_collect (regcache, i, buf);
700
701 if (i == I387_FOP_REGNUM (tdep))
702 {
703 /* The opcode occupies only 11 bits. Make sure we
704 don't touch the other bits. */
705 buf[1] &= ((1 << 3) - 1);
706 buf[1] |= ((FXSAVE_ADDR (tdep, regs, i))[1] & ~((1 << 3) - 1));
707 }
708 else if (i == I387_FTAG_REGNUM (tdep))
709 {
710 /* Converting back is much easier. */
711
712 unsigned short ftag;
713 int fpreg;
714
715 ftag = (buf[1] << 8) | buf[0];
716 buf[0] = 0;
717 buf[1] = 0;
718
719 for (fpreg = 7; fpreg >= 0; fpreg--)
720 {
721 int tag = (ftag >> (fpreg * 2)) & 3;
722
723 if (tag != 3)
724 buf[0] |= (1 << fpreg);
725 }
726 }
727 memcpy (FXSAVE_ADDR (tdep, regs, i), buf, 2);
728 }
729 else
730 regcache_raw_collect (regcache, i, FXSAVE_ADDR (tdep, regs, i));
731 }
732
733 if (regnum == I387_MXCSR_REGNUM (tdep) || regnum == -1)
734 regcache_raw_collect (regcache, I387_MXCSR_REGNUM (tdep),
735 FXSAVE_MXCSR_ADDR (regs));
736 }
737
738 /* `xstate_bv' is at byte offset 512. */
739 #define XSAVE_XSTATE_BV_ADDR(xsave) (xsave + 512)
740
741 /* At xsave_avxh_offset[REGNUM] you'll find the offset to the location in
742 the upper 128bit of AVX register data structure used by the "xsave"
743 instruction where GDB register REGNUM is stored. */
744
745 static int xsave_avxh_offset[] =
746 {
747 576 + 0 * 16, /* Upper 128bit of %ymm0 through ... */
748 576 + 1 * 16,
749 576 + 2 * 16,
750 576 + 3 * 16,
751 576 + 4 * 16,
752 576 + 5 * 16,
753 576 + 6 * 16,
754 576 + 7 * 16,
755 576 + 8 * 16,
756 576 + 9 * 16,
757 576 + 10 * 16,
758 576 + 11 * 16,
759 576 + 12 * 16,
760 576 + 13 * 16,
761 576 + 14 * 16,
762 576 + 15 * 16 /* Upper 128bit of ... %ymm15 (128 bits each). */
763 };
764
765 #define XSAVE_AVXH_ADDR(tdep, xsave, regnum) \
766 (xsave + xsave_avxh_offset[regnum - I387_YMM0H_REGNUM (tdep)])
767
768 /* At xsave_ymm_avx512_offset[REGNUM] you'll find the offset to the location in
769 the upper 128bit of ZMM register data structure used by the "xsave"
770 instruction where GDB register REGNUM is stored. */
771
772 static int xsave_ymm_avx512_offset[] =
773 {
774 /* HI16_ZMM_area + 16 bytes + regnum* 64 bytes. */
775 1664 + 16 + 0 * 64, /* %ymm16 through... */
776 1664 + 16 + 1 * 64,
777 1664 + 16 + 2 * 64,
778 1664 + 16 + 3 * 64,
779 1664 + 16 + 4 * 64,
780 1664 + 16 + 5 * 64,
781 1664 + 16 + 6 * 64,
782 1664 + 16 + 7 * 64,
783 1664 + 16 + 8 * 64,
784 1664 + 16 + 9 * 64,
785 1664 + 16 + 10 * 64,
786 1664 + 16 + 11 * 64,
787 1664 + 16 + 12 * 64,
788 1664 + 16 + 13 * 64,
789 1664 + 16 + 14 * 64,
790 1664 + 16 + 15 * 64 /* ... %ymm31 (128 bits each). */
791 };
792
793 #define XSAVE_YMM_AVX512_ADDR(tdep, xsave, regnum) \
794 (xsave + xsave_ymm_avx512_offset[regnum - I387_YMM16H_REGNUM (tdep)])
795
796 static int xsave_xmm_avx512_offset[] =
797 {
798 1664 + 0 * 64, /* %ymm16 through... */
799 1664 + 1 * 64,
800 1664 + 2 * 64,
801 1664 + 3 * 64,
802 1664 + 4 * 64,
803 1664 + 5 * 64,
804 1664 + 6 * 64,
805 1664 + 7 * 64,
806 1664 + 8 * 64,
807 1664 + 9 * 64,
808 1664 + 10 * 64,
809 1664 + 11 * 64,
810 1664 + 12 * 64,
811 1664 + 13 * 64,
812 1664 + 14 * 64,
813 1664 + 15 * 64 /* ... %ymm31 (128 bits each). */
814 };
815
816 #define XSAVE_XMM_AVX512_ADDR(tdep, xsave, regnum) \
817 (xsave + xsave_xmm_avx512_offset[regnum - I387_XMM16_REGNUM (tdep)])
818
819 static int xsave_mpx_offset[] = {
820 960 + 0 * 16, /* bnd0r...bnd3r registers. */
821 960 + 1 * 16,
822 960 + 2 * 16,
823 960 + 3 * 16,
824 1024 + 0 * 8, /* bndcfg ... bndstatus. */
825 1024 + 1 * 8,
826 };
827
828 #define XSAVE_MPX_ADDR(tdep, xsave, regnum) \
829 (xsave + xsave_mpx_offset[regnum - I387_BND0R_REGNUM (tdep)])
830
831 /* At xsave_avx512__h_offset[REGNUM] you find the offset to the location
832 of the AVX512 opmask register data structure used by the "xsave"
833 instruction where GDB register REGNUM is stored. */
834
835 static int xsave_avx512_k_offset[] =
836 {
837 1088 + 0 * 8, /* %k0 through... */
838 1088 + 1 * 8,
839 1088 + 2 * 8,
840 1088 + 3 * 8,
841 1088 + 4 * 8,
842 1088 + 5 * 8,
843 1088 + 6 * 8,
844 1088 + 7 * 8 /* %k7 (64 bits each). */
845 };
846
847 #define XSAVE_AVX512_K_ADDR(tdep, xsave, regnum) \
848 (xsave + xsave_avx512_k_offset[regnum - I387_K0_REGNUM (tdep)])
849
850 /* At xsave_avx512_zmm_h_offset[REGNUM] you find the offset to the location in
851 the upper 256bit of AVX512 ZMMH register data structure used by the "xsave"
852 instruction where GDB register REGNUM is stored. */
853
854 static int xsave_avx512_zmm_h_offset[] =
855 {
856 1152 + 0 * 32,
857 1152 + 1 * 32, /* Upper 256bit of %zmmh0 through... */
858 1152 + 2 * 32,
859 1152 + 3 * 32,
860 1152 + 4 * 32,
861 1152 + 5 * 32,
862 1152 + 6 * 32,
863 1152 + 7 * 32,
864 1152 + 8 * 32,
865 1152 + 9 * 32,
866 1152 + 10 * 32,
867 1152 + 11 * 32,
868 1152 + 12 * 32,
869 1152 + 13 * 32,
870 1152 + 14 * 32,
871 1152 + 15 * 32, /* Upper 256bit of... %zmmh15 (256 bits each). */
872 1664 + 32 + 0 * 64, /* Upper 256bit of... %zmmh16 (256 bits each). */
873 1664 + 32 + 1 * 64,
874 1664 + 32 + 2 * 64,
875 1664 + 32 + 3 * 64,
876 1664 + 32 + 4 * 64,
877 1664 + 32 + 5 * 64,
878 1664 + 32 + 6 * 64,
879 1664 + 32 + 7 * 64,
880 1664 + 32 + 8 * 64,
881 1664 + 32 + 9 * 64,
882 1664 + 32 + 10 * 64,
883 1664 + 32 + 11 * 64,
884 1664 + 32 + 12 * 64,
885 1664 + 32 + 13 * 64,
886 1664 + 32 + 14 * 64,
887 1664 + 32 + 15 * 64 /* Upper 256bit of... %zmmh31 (256 bits each). */
888 };
889
890 #define XSAVE_AVX512_ZMM_H_ADDR(tdep, xsave, regnum) \
891 (xsave + xsave_avx512_zmm_h_offset[regnum - I387_ZMM0H_REGNUM (tdep)])
892
893 /* Similar to i387_supply_fxsave, but use XSAVE extended state. */
894
895 void
896 i387_supply_xsave (struct regcache *regcache, int regnum,
897 const void *xsave)
898 {
899 struct gdbarch *gdbarch = get_regcache_arch (regcache);
900 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
901 const gdb_byte *regs = xsave;
902 int i;
903 unsigned int clear_bv;
904 static const gdb_byte zero[MAX_REGISTER_SIZE] = { 0 };
905 enum
906 {
907 none = 0x0,
908 x87 = 0x1,
909 sse = 0x2,
910 avxh = 0x4,
911 mpx = 0x8,
912 avx512_k = 0x10,
913 avx512_zmm_h = 0x20,
914 avx512_ymmh_avx512 = 0x40,
915 avx512_xmm_avx512 = 0x80,
916 all = x87 | sse | avxh | mpx | avx512_k | avx512_zmm_h
917 | avx512_ymmh_avx512 | avx512_xmm_avx512
918 } regclass;
919
920 gdb_assert (regs != NULL);
921 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
922 gdb_assert (tdep->num_xmm_regs > 0);
923
924 if (regnum == -1)
925 regclass = all;
926 else if (regnum >= I387_ZMM0H_REGNUM (tdep)
927 && regnum < I387_ZMMENDH_REGNUM (tdep))
928 regclass = avx512_zmm_h;
929 else if (regnum >= I387_K0_REGNUM (tdep)
930 && regnum < I387_KEND_REGNUM (tdep))
931 regclass = avx512_k;
932 else if (regnum >= I387_YMM16H_REGNUM (tdep)
933 && regnum < I387_YMMH_AVX512_END_REGNUM (tdep))
934 regclass = avx512_ymmh_avx512;
935 else if (regnum >= I387_XMM16_REGNUM (tdep)
936 && regnum < I387_XMM_AVX512_END_REGNUM (tdep))
937 regclass = avx512_xmm_avx512;
938 else if (regnum >= I387_YMM0H_REGNUM (tdep)
939 && regnum < I387_YMMENDH_REGNUM (tdep))
940 regclass = avxh;
941 else if (regnum >= I387_BND0R_REGNUM (tdep)
942 && regnum < I387_MPXEND_REGNUM (tdep))
943 regclass = mpx;
944 else if (regnum >= I387_XMM0_REGNUM (tdep)
945 && regnum < I387_MXCSR_REGNUM (tdep))
946 regclass = sse;
947 else if (regnum >= I387_ST0_REGNUM (tdep)
948 && regnum < I387_FCTRL_REGNUM (tdep))
949 regclass = x87;
950 else
951 regclass = none;
952
953 if (regclass != none)
954 {
955 /* Get `xstat_bv'. */
956 const gdb_byte *xstate_bv_p = XSAVE_XSTATE_BV_ADDR (regs);
957
958 /* The supported bits in `xstat_bv' are 1 byte. Clear part in
959 vector registers if its bit in xstat_bv is zero. */
960 clear_bv = (~(*xstate_bv_p)) & tdep->xcr0;
961 }
962 else
963 clear_bv = I386_XSTATE_ALL_MASK;
964
965 /* With the delayed xsave mechanism, in between the program
966 starting, and the program accessing the vector registers for the
967 first time, the register's values are invalid. The kernel
968 initializes register states to zero when they are set the first
969 time in a program. This means that from the user-space programs'
970 perspective, it's the same as if the registers have always been
971 zero from the start of the program. Therefore, the debugger
972 should provide the same illusion to the user. */
973
974 switch (regclass)
975 {
976 case none:
977 break;
978
979 case avx512_zmm_h:
980 if ((clear_bv & (I386_XSTATE_ZMM_H | I386_XSTATE_ZMM)))
981 regcache_raw_supply (regcache, regnum, zero);
982 else
983 regcache_raw_supply (regcache, regnum,
984 XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, regnum));
985 return;
986
987 case avx512_k:
988 if ((clear_bv & I386_XSTATE_K))
989 regcache_raw_supply (regcache, regnum, zero);
990 else
991 regcache_raw_supply (regcache, regnum,
992 XSAVE_AVX512_K_ADDR (tdep, regs, regnum));
993 return;
994
995 case avx512_ymmh_avx512:
996 if ((clear_bv & I386_XSTATE_ZMM))
997 regcache_raw_supply (regcache, regnum, zero);
998 else
999 regcache_raw_supply (regcache, regnum,
1000 XSAVE_YMM_AVX512_ADDR (tdep, regs, regnum));
1001 return;
1002
1003 case avx512_xmm_avx512:
1004 if ((clear_bv & I386_XSTATE_ZMM))
1005 regcache_raw_supply (regcache, regnum, zero);
1006 else
1007 regcache_raw_supply (regcache, regnum,
1008 XSAVE_XMM_AVX512_ADDR (tdep, regs, regnum));
1009 return;
1010
1011 case avxh:
1012 if ((clear_bv & I386_XSTATE_AVX))
1013 regcache_raw_supply (regcache, regnum, zero);
1014 else
1015 regcache_raw_supply (regcache, regnum,
1016 XSAVE_AVXH_ADDR (tdep, regs, regnum));
1017 return;
1018
1019 case mpx:
1020 if ((clear_bv & I386_XSTATE_BNDREGS))
1021 regcache_raw_supply (regcache, regnum, zero);
1022 else
1023 regcache_raw_supply (regcache, regnum,
1024 XSAVE_MPX_ADDR (tdep, regs, regnum));
1025 return;
1026
1027 case sse:
1028 if ((clear_bv & I386_XSTATE_SSE))
1029 regcache_raw_supply (regcache, regnum, zero);
1030 else
1031 regcache_raw_supply (regcache, regnum,
1032 FXSAVE_ADDR (tdep, regs, regnum));
1033 return;
1034
1035 case x87:
1036 if ((clear_bv & I386_XSTATE_X87))
1037 regcache_raw_supply (regcache, regnum, zero);
1038 else
1039 regcache_raw_supply (regcache, regnum,
1040 FXSAVE_ADDR (tdep, regs, regnum));
1041 return;
1042
1043 case all:
1044 /* Handle the upper ZMM registers. */
1045 if ((tdep->xcr0 & (I386_XSTATE_ZMM_H | I386_XSTATE_ZMM)))
1046 {
1047 if ((clear_bv & (I386_XSTATE_ZMM_H | I386_XSTATE_ZMM)))
1048 {
1049 for (i = I387_ZMM0H_REGNUM (tdep);
1050 i < I387_ZMMENDH_REGNUM (tdep);
1051 i++)
1052 regcache_raw_supply (regcache, i, zero);
1053 }
1054 else
1055 {
1056 for (i = I387_ZMM0H_REGNUM (tdep);
1057 i < I387_ZMMENDH_REGNUM (tdep);
1058 i++)
1059 regcache_raw_supply (regcache, i,
1060 XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, i));
1061 }
1062 }
1063
1064 /* Handle AVX512 OpMask registers. */
1065 if ((tdep->xcr0 & I386_XSTATE_K))
1066 {
1067 if ((clear_bv & I386_XSTATE_K))
1068 {
1069 for (i = I387_K0_REGNUM (tdep);
1070 i < I387_KEND_REGNUM (tdep);
1071 i++)
1072 regcache_raw_supply (regcache, i, zero);
1073 }
1074 else
1075 {
1076 for (i = I387_K0_REGNUM (tdep);
1077 i < I387_KEND_REGNUM (tdep);
1078 i++)
1079 regcache_raw_supply (regcache, i,
1080 XSAVE_AVX512_K_ADDR (tdep, regs, i));
1081 }
1082 }
1083
1084 /* Handle the YMM_AVX512 registers. */
1085 if ((tdep->xcr0 & I386_XSTATE_ZMM))
1086 {
1087 if ((clear_bv & I386_XSTATE_ZMM))
1088 {
1089 for (i = I387_YMM16H_REGNUM (tdep);
1090 i < I387_YMMH_AVX512_END_REGNUM (tdep);
1091 i++)
1092 regcache_raw_supply (regcache, i, zero);
1093 for (i = I387_XMM16_REGNUM (tdep);
1094 i < I387_XMM_AVX512_END_REGNUM (tdep);
1095 i++)
1096 regcache_raw_supply (regcache, i, zero);
1097 }
1098 else
1099 {
1100 for (i = I387_YMM16H_REGNUM (tdep);
1101 i < I387_YMMH_AVX512_END_REGNUM (tdep);
1102 i++)
1103 regcache_raw_supply (regcache, i,
1104 XSAVE_YMM_AVX512_ADDR (tdep, regs, i));
1105 for (i = I387_XMM16_REGNUM (tdep);
1106 i < I387_XMM_AVX512_END_REGNUM (tdep);
1107 i++)
1108 regcache_raw_supply (regcache, i,
1109 XSAVE_XMM_AVX512_ADDR (tdep, regs, i));
1110 }
1111 }
1112 /* Handle the upper YMM registers. */
1113 if ((tdep->xcr0 & I386_XSTATE_AVX))
1114 {
1115 if ((clear_bv & I386_XSTATE_AVX))
1116 {
1117 for (i = I387_YMM0H_REGNUM (tdep);
1118 i < I387_YMMENDH_REGNUM (tdep);
1119 i++)
1120 regcache_raw_supply (regcache, i, zero);
1121 }
1122 else
1123 {
1124 for (i = I387_YMM0H_REGNUM (tdep);
1125 i < I387_YMMENDH_REGNUM (tdep);
1126 i++)
1127 regcache_raw_supply (regcache, i,
1128 XSAVE_AVXH_ADDR (tdep, regs, i));
1129 }
1130 }
1131
1132 /* Handle the MPX registers. */
1133 if ((tdep->xcr0 & I386_XSTATE_BNDREGS))
1134 {
1135 if (clear_bv & I386_XSTATE_BNDREGS)
1136 {
1137 for (i = I387_BND0R_REGNUM (tdep);
1138 i < I387_BNDCFGU_REGNUM (tdep); i++)
1139 regcache_raw_supply (regcache, i, zero);
1140 }
1141 else
1142 {
1143 for (i = I387_BND0R_REGNUM (tdep);
1144 i < I387_BNDCFGU_REGNUM (tdep); i++)
1145 regcache_raw_supply (regcache, i,
1146 XSAVE_MPX_ADDR (tdep, regs, i));
1147 }
1148 }
1149
1150 /* Handle the MPX registers. */
1151 if ((tdep->xcr0 & I386_XSTATE_BNDCFG))
1152 {
1153 if (clear_bv & I386_XSTATE_BNDCFG)
1154 {
1155 for (i = I387_BNDCFGU_REGNUM (tdep);
1156 i < I387_MPXEND_REGNUM (tdep); i++)
1157 regcache_raw_supply (regcache, i, zero);
1158 }
1159 else
1160 {
1161 for (i = I387_BNDCFGU_REGNUM (tdep);
1162 i < I387_MPXEND_REGNUM (tdep); i++)
1163 regcache_raw_supply (regcache, i,
1164 XSAVE_MPX_ADDR (tdep, regs, i));
1165 }
1166 }
1167
1168 /* Handle the XMM registers. */
1169 if ((tdep->xcr0 & I386_XSTATE_SSE))
1170 {
1171 if ((clear_bv & I386_XSTATE_SSE))
1172 {
1173 for (i = I387_XMM0_REGNUM (tdep);
1174 i < I387_MXCSR_REGNUM (tdep);
1175 i++)
1176 regcache_raw_supply (regcache, i, zero);
1177 }
1178 else
1179 {
1180 for (i = I387_XMM0_REGNUM (tdep);
1181 i < I387_MXCSR_REGNUM (tdep); i++)
1182 regcache_raw_supply (regcache, i,
1183 FXSAVE_ADDR (tdep, regs, i));
1184 }
1185 }
1186
1187 /* Handle the x87 registers. */
1188 if ((tdep->xcr0 & I386_XSTATE_X87))
1189 {
1190 if ((clear_bv & I386_XSTATE_X87))
1191 {
1192 for (i = I387_ST0_REGNUM (tdep);
1193 i < I387_FCTRL_REGNUM (tdep);
1194 i++)
1195 regcache_raw_supply (regcache, i, zero);
1196 }
1197 else
1198 {
1199 for (i = I387_ST0_REGNUM (tdep);
1200 i < I387_FCTRL_REGNUM (tdep);
1201 i++)
1202 regcache_raw_supply (regcache, i, FXSAVE_ADDR (tdep, regs, i));
1203 }
1204 }
1205 break;
1206 }
1207
1208 /* Only handle x87 control registers. */
1209 for (i = I387_FCTRL_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++)
1210 if (regnum == -1 || regnum == i)
1211 {
1212 /* Most of the FPU control registers occupy only 16 bits in
1213 the xsave extended state. Give those a special treatment. */
1214 if (i != I387_FIOFF_REGNUM (tdep)
1215 && i != I387_FOOFF_REGNUM (tdep))
1216 {
1217 gdb_byte val[4];
1218
1219 memcpy (val, FXSAVE_ADDR (tdep, regs, i), 2);
1220 val[2] = val[3] = 0;
1221 if (i == I387_FOP_REGNUM (tdep))
1222 val[1] &= ((1 << 3) - 1);
1223 else if (i== I387_FTAG_REGNUM (tdep))
1224 {
1225 /* The fxsave area contains a simplified version of
1226 the tag word. We have to look at the actual 80-bit
1227 FP data to recreate the traditional i387 tag word. */
1228
1229 unsigned long ftag = 0;
1230 int fpreg;
1231 int top;
1232
1233 top = ((FXSAVE_ADDR (tdep, regs,
1234 I387_FSTAT_REGNUM (tdep)))[1] >> 3);
1235 top &= 0x7;
1236
1237 for (fpreg = 7; fpreg >= 0; fpreg--)
1238 {
1239 int tag;
1240
1241 if (val[0] & (1 << fpreg))
1242 {
1243 int thisreg = (fpreg + 8 - top) % 8
1244 + I387_ST0_REGNUM (tdep);
1245 tag = i387_tag (FXSAVE_ADDR (tdep, regs, thisreg));
1246 }
1247 else
1248 tag = 3; /* Empty */
1249
1250 ftag |= tag << (2 * fpreg);
1251 }
1252 val[0] = ftag & 0xff;
1253 val[1] = (ftag >> 8) & 0xff;
1254 }
1255 regcache_raw_supply (regcache, i, val);
1256 }
1257 else
1258 regcache_raw_supply (regcache, i, FXSAVE_ADDR (tdep, regs, i));
1259 }
1260
1261 if (regnum == I387_MXCSR_REGNUM (tdep) || regnum == -1)
1262 regcache_raw_supply (regcache, I387_MXCSR_REGNUM (tdep),
1263 FXSAVE_MXCSR_ADDR (regs));
1264 }
1265
1266 /* Similar to i387_collect_fxsave, but use XSAVE extended state. */
1267
1268 void
1269 i387_collect_xsave (const struct regcache *regcache, int regnum,
1270 void *xsave, int gcore)
1271 {
1272 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1273 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1274 gdb_byte *regs = xsave;
1275 int i;
1276 enum
1277 {
1278 none = 0x0,
1279 check = 0x1,
1280 x87 = 0x2 | check,
1281 sse = 0x4 | check,
1282 avxh = 0x8 | check,
1283 mpx = 0x10 | check,
1284 avx512_k = 0x20 | check,
1285 avx512_zmm_h = 0x40 | check,
1286 avx512_ymmh_avx512 = 0x80 | check,
1287 avx512_xmm_avx512 = 0x100 | check,
1288 all = x87 | sse | avxh | mpx | avx512_k | avx512_zmm_h
1289 | avx512_ymmh_avx512 | avx512_xmm_avx512
1290 } regclass;
1291
1292 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
1293 gdb_assert (tdep->num_xmm_regs > 0);
1294
1295 if (regnum == -1)
1296 regclass = all;
1297 else if (regnum >= I387_ZMM0H_REGNUM (tdep)
1298 && regnum < I387_ZMMENDH_REGNUM (tdep))
1299 regclass = avx512_zmm_h;
1300 else if (regnum >= I387_K0_REGNUM (tdep)
1301 && regnum < I387_KEND_REGNUM (tdep))
1302 regclass = avx512_k;
1303 else if (regnum >= I387_YMM16H_REGNUM (tdep)
1304 && regnum < I387_YMMH_AVX512_END_REGNUM (tdep))
1305 regclass = avx512_ymmh_avx512;
1306 else if (regnum >= I387_XMM16_REGNUM (tdep)
1307 && regnum < I387_XMM_AVX512_END_REGNUM (tdep))
1308 regclass = avx512_xmm_avx512;
1309 else if (regnum >= I387_YMM0H_REGNUM (tdep)
1310 && regnum < I387_YMMENDH_REGNUM (tdep))
1311 regclass = avxh;
1312 else if (regnum >= I387_BND0R_REGNUM (tdep)
1313 && regnum < I387_MPXEND_REGNUM (tdep))
1314 regclass = mpx;
1315 else if (regnum >= I387_XMM0_REGNUM (tdep)
1316 && regnum < I387_MXCSR_REGNUM (tdep))
1317 regclass = sse;
1318 else if (regnum >= I387_ST0_REGNUM (tdep)
1319 && regnum < I387_FCTRL_REGNUM (tdep))
1320 regclass = x87;
1321 else
1322 regclass = none;
1323
1324 if (gcore)
1325 {
1326 /* Clear XSAVE extended state. */
1327 memset (regs, 0, I386_XSTATE_SIZE (tdep->xcr0));
1328
1329 /* Update XCR0 and `xstate_bv' with XCR0 for gcore. */
1330 if (tdep->xsave_xcr0_offset != -1)
1331 memcpy (regs + tdep->xsave_xcr0_offset, &tdep->xcr0, 8);
1332 memcpy (XSAVE_XSTATE_BV_ADDR (regs), &tdep->xcr0, 8);
1333 }
1334
1335 if ((regclass & check))
1336 {
1337 gdb_byte raw[I386_MAX_REGISTER_SIZE];
1338 gdb_byte *xstate_bv_p = XSAVE_XSTATE_BV_ADDR (regs);
1339 unsigned int xstate_bv = 0;
1340 /* The supported bits in `xstat_bv' are 1 byte. */
1341 unsigned int clear_bv = (~(*xstate_bv_p)) & tdep->xcr0;
1342 gdb_byte *p;
1343
1344 /* Clear register set if its bit in xstat_bv is zero. */
1345 if (clear_bv)
1346 {
1347 if ((clear_bv & I386_XSTATE_BNDREGS))
1348 for (i = I387_BND0R_REGNUM (tdep);
1349 i < I387_BNDCFGU_REGNUM (tdep); i++)
1350 memset (XSAVE_MPX_ADDR (tdep, regs, i), 0, 16);
1351
1352 if ((clear_bv & I386_XSTATE_BNDCFG))
1353 for (i = I387_BNDCFGU_REGNUM (tdep);
1354 i < I387_MPXEND_REGNUM (tdep); i++)
1355 memset (XSAVE_MPX_ADDR (tdep, regs, i), 0, 8);
1356
1357 if ((clear_bv & (I386_XSTATE_ZMM_H | I386_XSTATE_ZMM)))
1358 for (i = I387_ZMM0H_REGNUM (tdep);
1359 i < I387_ZMMENDH_REGNUM (tdep); i++)
1360 memset (XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, i), 0, 32);
1361
1362 if ((clear_bv & I386_XSTATE_K))
1363 for (i = I387_K0_REGNUM (tdep);
1364 i < I387_KEND_REGNUM (tdep); i++)
1365 memset (XSAVE_AVX512_K_ADDR (tdep, regs, i), 0, 8);
1366
1367 if ((clear_bv & I386_XSTATE_ZMM))
1368 {
1369 for (i = I387_YMM16H_REGNUM (tdep);
1370 i < I387_YMMH_AVX512_END_REGNUM (tdep); i++)
1371 memset (XSAVE_YMM_AVX512_ADDR (tdep, regs, i), 0, 16);
1372 for (i = I387_XMM16_REGNUM (tdep);
1373 i < I387_XMM_AVX512_END_REGNUM (tdep); i++)
1374 memset (XSAVE_XMM_AVX512_ADDR (tdep, regs, i), 0, 16);
1375 }
1376
1377 if ((clear_bv & I386_XSTATE_AVX))
1378 for (i = I387_YMM0H_REGNUM (tdep);
1379 i < I387_YMMENDH_REGNUM (tdep); i++)
1380 memset (XSAVE_AVXH_ADDR (tdep, regs, i), 0, 16);
1381
1382 if ((clear_bv & I386_XSTATE_SSE))
1383 for (i = I387_XMM0_REGNUM (tdep);
1384 i < I387_MXCSR_REGNUM (tdep); i++)
1385 memset (FXSAVE_ADDR (tdep, regs, i), 0, 16);
1386
1387 if ((clear_bv & I386_XSTATE_X87))
1388 for (i = I387_ST0_REGNUM (tdep);
1389 i < I387_FCTRL_REGNUM (tdep); i++)
1390 memset (FXSAVE_ADDR (tdep, regs, i), 0, 10);
1391 }
1392
1393 if (regclass == all)
1394 {
1395 /* Check if any ZMMH registers are changed. */
1396 if ((tdep->xcr0 & (I386_XSTATE_ZMM_H | I386_XSTATE_ZMM)))
1397 for (i = I387_ZMM0H_REGNUM (tdep);
1398 i < I387_ZMMENDH_REGNUM (tdep); i++)
1399 {
1400 regcache_raw_collect (regcache, i, raw);
1401 p = XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, i);
1402 if (memcmp (raw, p, 32) != 0)
1403 {
1404 xstate_bv |= (I386_XSTATE_ZMM_H | I386_XSTATE_ZMM);
1405 memcpy (p, raw, 32);
1406 }
1407 }
1408
1409 /* Check if any K registers are changed. */
1410 if ((tdep->xcr0 & I386_XSTATE_K))
1411 for (i = I387_K0_REGNUM (tdep);
1412 i < I387_KEND_REGNUM (tdep); i++)
1413 {
1414 regcache_raw_collect (regcache, i, raw);
1415 p = XSAVE_AVX512_K_ADDR (tdep, regs, i);
1416 if (memcmp (raw, p, 8) != 0)
1417 {
1418 xstate_bv |= I386_XSTATE_K;
1419 memcpy (p, raw, 8);
1420 }
1421 }
1422
1423 /* Check if any XMM or upper YMM registers are changed. */
1424 if ((tdep->xcr0 & I386_XSTATE_ZMM))
1425 {
1426 for (i = I387_YMM16H_REGNUM (tdep);
1427 i < I387_YMMH_AVX512_END_REGNUM (tdep); i++)
1428 {
1429 regcache_raw_collect (regcache, i, raw);
1430 p = XSAVE_YMM_AVX512_ADDR (tdep, regs, i);
1431 if (memcmp (raw, p, 16) != 0)
1432 {
1433 xstate_bv |= I386_XSTATE_ZMM;
1434 memcpy (p, raw, 16);
1435 }
1436 }
1437 for (i = I387_XMM16_REGNUM (tdep);
1438 i < I387_XMM_AVX512_END_REGNUM (tdep); i++)
1439 {
1440 regcache_raw_collect (regcache, i, raw);
1441 p = XSAVE_XMM_AVX512_ADDR (tdep, regs, i);
1442 if (memcmp (raw, p, 16) != 0)
1443 {
1444 xstate_bv |= I386_XSTATE_ZMM;
1445 memcpy (p, raw, 16);
1446 }
1447 }
1448 }
1449
1450 /* Check if any upper YMM registers are changed. */
1451 if ((tdep->xcr0 & I386_XSTATE_AVX))
1452 for (i = I387_YMM0H_REGNUM (tdep);
1453 i < I387_YMMENDH_REGNUM (tdep); i++)
1454 {
1455 regcache_raw_collect (regcache, i, raw);
1456 p = XSAVE_AVXH_ADDR (tdep, regs, i);
1457 if (memcmp (raw, p, 16))
1458 {
1459 xstate_bv |= I386_XSTATE_AVX;
1460 memcpy (p, raw, 16);
1461 }
1462 }
1463 /* Check if any upper MPX registers are changed. */
1464 if ((tdep->xcr0 & I386_XSTATE_BNDREGS))
1465 for (i = I387_BND0R_REGNUM (tdep);
1466 i < I387_BNDCFGU_REGNUM (tdep); i++)
1467 {
1468 regcache_raw_collect (regcache, i, raw);
1469 p = XSAVE_MPX_ADDR (tdep, regs, i);
1470 if (memcmp (raw, p, 16))
1471 {
1472 xstate_bv |= I386_XSTATE_BNDREGS;
1473 memcpy (p, raw, 16);
1474 }
1475 }
1476
1477 /* Check if any upper MPX registers are changed. */
1478 if ((tdep->xcr0 & I386_XSTATE_BNDCFG))
1479 for (i = I387_BNDCFGU_REGNUM (tdep);
1480 i < I387_MPXEND_REGNUM (tdep); i++)
1481 {
1482 regcache_raw_collect (regcache, i, raw);
1483 p = XSAVE_MPX_ADDR (tdep, regs, i);
1484 if (memcmp (raw, p, 8))
1485 {
1486 xstate_bv |= I386_XSTATE_BNDCFG;
1487 memcpy (p, raw, 8);
1488 }
1489 }
1490
1491 /* Check if any SSE registers are changed. */
1492 if ((tdep->xcr0 & I386_XSTATE_SSE))
1493 for (i = I387_XMM0_REGNUM (tdep);
1494 i < I387_MXCSR_REGNUM (tdep); i++)
1495 {
1496 regcache_raw_collect (regcache, i, raw);
1497 p = FXSAVE_ADDR (tdep, regs, i);
1498 if (memcmp (raw, p, 16))
1499 {
1500 xstate_bv |= I386_XSTATE_SSE;
1501 memcpy (p, raw, 16);
1502 }
1503 }
1504
1505 /* Check if any X87 registers are changed. */
1506 if ((tdep->xcr0 & I386_XSTATE_X87))
1507 for (i = I387_ST0_REGNUM (tdep);
1508 i < I387_FCTRL_REGNUM (tdep); i++)
1509 {
1510 regcache_raw_collect (regcache, i, raw);
1511 p = FXSAVE_ADDR (tdep, regs, i);
1512 if (memcmp (raw, p, 10))
1513 {
1514 xstate_bv |= I386_XSTATE_X87;
1515 memcpy (p, raw, 10);
1516 }
1517 }
1518 }
1519 else
1520 {
1521 /* Check if REGNUM is changed. */
1522 regcache_raw_collect (regcache, regnum, raw);
1523
1524 switch (regclass)
1525 {
1526 default:
1527 internal_error (__FILE__, __LINE__,
1528 _("invalid i387 regclass"));
1529
1530 case avx512_zmm_h:
1531 /* This is a ZMM register. */
1532 p = XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, regnum);
1533 if (memcmp (raw, p, 32) != 0)
1534 {
1535 xstate_bv |= (I386_XSTATE_ZMM_H | I386_XSTATE_ZMM);
1536 memcpy (p, raw, 32);
1537 }
1538 break;
1539 case avx512_k:
1540 /* This is a AVX512 mask register. */
1541 p = XSAVE_AVX512_K_ADDR (tdep, regs, regnum);
1542 if (memcmp (raw, p, 8) != 0)
1543 {
1544 xstate_bv |= I386_XSTATE_K;
1545 memcpy (p, raw, 8);
1546 }
1547 break;
1548
1549 case avx512_ymmh_avx512:
1550 /* This is an upper YMM16-31 register. */
1551 p = XSAVE_YMM_AVX512_ADDR (tdep, regs, regnum);
1552 if (memcmp (raw, p, 16) != 0)
1553 {
1554 xstate_bv |= I386_XSTATE_ZMM;
1555 memcpy (p, raw, 16);
1556 }
1557 break;
1558
1559 case avx512_xmm_avx512:
1560 /* This is an upper XMM16-31 register. */
1561 p = XSAVE_XMM_AVX512_ADDR (tdep, regs, regnum);
1562 if (memcmp (raw, p, 16) != 0)
1563 {
1564 xstate_bv |= I386_XSTATE_ZMM;
1565 memcpy (p, raw, 16);
1566 }
1567 break;
1568
1569 case avxh:
1570 /* This is an upper YMM register. */
1571 p = XSAVE_AVXH_ADDR (tdep, regs, regnum);
1572 if (memcmp (raw, p, 16))
1573 {
1574 xstate_bv |= I386_XSTATE_AVX;
1575 memcpy (p, raw, 16);
1576 }
1577 break;
1578
1579 case mpx:
1580 if (regnum < I387_BNDCFGU_REGNUM (tdep))
1581 {
1582 regcache_raw_collect (regcache, regnum, raw);
1583 p = XSAVE_MPX_ADDR (tdep, regs, regnum);
1584 if (memcmp (raw, p, 16))
1585 {
1586 xstate_bv |= I386_XSTATE_BNDREGS;
1587 memcpy (p, raw, 16);
1588 }
1589 }
1590 else
1591 {
1592 p = XSAVE_MPX_ADDR (tdep, regs, regnum);
1593 xstate_bv |= I386_XSTATE_BNDCFG;
1594 memcpy (p, raw, 8);
1595 }
1596 break;
1597
1598 case sse:
1599 /* This is an SSE register. */
1600 p = FXSAVE_ADDR (tdep, regs, regnum);
1601 if (memcmp (raw, p, 16))
1602 {
1603 xstate_bv |= I386_XSTATE_SSE;
1604 memcpy (p, raw, 16);
1605 }
1606 break;
1607
1608 case x87:
1609 /* This is an x87 register. */
1610 p = FXSAVE_ADDR (tdep, regs, regnum);
1611 if (memcmp (raw, p, 10))
1612 {
1613 xstate_bv |= I386_XSTATE_X87;
1614 memcpy (p, raw, 10);
1615 }
1616 break;
1617 }
1618 }
1619
1620 /* Update the corresponding bits in `xstate_bv' if any SSE/AVX
1621 registers are changed. */
1622 if (xstate_bv)
1623 {
1624 /* The supported bits in `xstat_bv' are 1 byte. */
1625 *xstate_bv_p |= (gdb_byte) xstate_bv;
1626
1627 switch (regclass)
1628 {
1629 default:
1630 internal_error (__FILE__, __LINE__,
1631 _("invalid i387 regclass"));
1632
1633 case all:
1634 break;
1635
1636 case x87:
1637 case sse:
1638 case avxh:
1639 case mpx:
1640 case avx512_k:
1641 case avx512_zmm_h:
1642 case avx512_ymmh_avx512:
1643 case avx512_xmm_avx512:
1644 /* Register REGNUM has been updated. Return. */
1645 return;
1646 }
1647 }
1648 else
1649 {
1650 /* Return if REGNUM isn't changed. */
1651 if (regclass != all)
1652 return;
1653 }
1654 }
1655
1656 /* Only handle x87 control registers. */
1657 for (i = I387_FCTRL_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++)
1658 if (regnum == -1 || regnum == i)
1659 {
1660 /* Most of the FPU control registers occupy only 16 bits in
1661 the xsave extended state. Give those a special treatment. */
1662 if (i != I387_FIOFF_REGNUM (tdep)
1663 && i != I387_FOOFF_REGNUM (tdep))
1664 {
1665 gdb_byte buf[4];
1666
1667 regcache_raw_collect (regcache, i, buf);
1668
1669 if (i == I387_FOP_REGNUM (tdep))
1670 {
1671 /* The opcode occupies only 11 bits. Make sure we
1672 don't touch the other bits. */
1673 buf[1] &= ((1 << 3) - 1);
1674 buf[1] |= ((FXSAVE_ADDR (tdep, regs, i))[1] & ~((1 << 3) - 1));
1675 }
1676 else if (i == I387_FTAG_REGNUM (tdep))
1677 {
1678 /* Converting back is much easier. */
1679
1680 unsigned short ftag;
1681 int fpreg;
1682
1683 ftag = (buf[1] << 8) | buf[0];
1684 buf[0] = 0;
1685 buf[1] = 0;
1686
1687 for (fpreg = 7; fpreg >= 0; fpreg--)
1688 {
1689 int tag = (ftag >> (fpreg * 2)) & 3;
1690
1691 if (tag != 3)
1692 buf[0] |= (1 << fpreg);
1693 }
1694 }
1695 memcpy (FXSAVE_ADDR (tdep, regs, i), buf, 2);
1696 }
1697 else
1698 regcache_raw_collect (regcache, i, FXSAVE_ADDR (tdep, regs, i));
1699 }
1700
1701 if (regnum == I387_MXCSR_REGNUM (tdep) || regnum == -1)
1702 regcache_raw_collect (regcache, I387_MXCSR_REGNUM (tdep),
1703 FXSAVE_MXCSR_ADDR (regs));
1704 }
1705
1706 /* Recreate the FTW (tag word) valid bits from the 80-bit FP data in
1707 *RAW. */
1708
1709 static int
1710 i387_tag (const gdb_byte *raw)
1711 {
1712 int integer;
1713 unsigned int exponent;
1714 unsigned long fraction[2];
1715
1716 integer = raw[7] & 0x80;
1717 exponent = (((raw[9] & 0x7f) << 8) | raw[8]);
1718 fraction[0] = ((raw[3] << 24) | (raw[2] << 16) | (raw[1] << 8) | raw[0]);
1719 fraction[1] = (((raw[7] & 0x7f) << 24) | (raw[6] << 16)
1720 | (raw[5] << 8) | raw[4]);
1721
1722 if (exponent == 0x7fff)
1723 {
1724 /* Special. */
1725 return (2);
1726 }
1727 else if (exponent == 0x0000)
1728 {
1729 if (fraction[0] == 0x0000 && fraction[1] == 0x0000 && !integer)
1730 {
1731 /* Zero. */
1732 return (1);
1733 }
1734 else
1735 {
1736 /* Special. */
1737 return (2);
1738 }
1739 }
1740 else
1741 {
1742 if (integer)
1743 {
1744 /* Valid. */
1745 return (0);
1746 }
1747 else
1748 {
1749 /* Special. */
1750 return (2);
1751 }
1752 }
1753 }
1754
1755 /* Prepare the FPU stack in REGCACHE for a function return. */
1756
1757 void
1758 i387_return_value (struct gdbarch *gdbarch, struct regcache *regcache)
1759 {
1760 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1761 ULONGEST fstat;
1762
1763 /* Set the top of the floating-point register stack to 7. The
1764 actual value doesn't really matter, but 7 is what a normal
1765 function return would end up with if the program started out with
1766 a freshly initialized FPU. */
1767 regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat);
1768 fstat |= (7 << 11);
1769 regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat);
1770
1771 /* Mark %st(1) through %st(7) as empty. Since we set the top of the
1772 floating-point register stack to 7, the appropriate value for the
1773 tag word is 0x3fff. */
1774 regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff);
1775
1776 }
GDB Binutils - Deliverables
This page took 0.084147 seconds and 5 git commands to generate.