1 /* i80960 instruction disassembler for GDB.
2 Copyright 1990, 1991, 1992 Free Software Foundation, Inc.
4 This file is part of GDB.
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
23 /* Print the instruction at address MEMADDR in debugged memory,
24 on STREAM. Returns length of the instruction, in bytes. */
27 print_insn (memaddr
, stream
)
31 disassemble_info info
;
33 GDB_INIT_DISASSEMBLE_INFO(info
, stream
);
35 return print_insn_i960 (memaddr
, &info
);
38 /****************************************/
40 /****************************************/
47 static int /* returns instruction length: 4 or 8 */
48 mem( memaddr
, word1
, word2
, noprint
)
49 unsigned long memaddr
;
50 unsigned long word1
, word2
;
51 int noprint
; /* If TRUE, return instruction length, but
52 don't output any text. */
58 const char *reg1
, *reg2
, *reg3
;
60 /* This lookup table is too sparse to make it worth typing in, but not
61 * so large as to make a sparse array necessary. We allocate the
62 * table at runtime, initialize all entries to empty, and copy the
63 * real ones in from an initialization table.
65 * NOTE: In this table, the meaning of 'numops' is:
67 * 2: 2 operands, load instruction
68 * -2: 2 operands, store instruction
70 static struct tabent
*mem_tab
= NULL
;
71 /* Opcodes of 0x8X, 9X, aX, bX, and cX must be in the table. */
74 #define MEM_SIZ ((MEM_MAX-MEM_MIN+1) * sizeof(struct tabent))
76 static struct { int opcode
; char *name
; char numops
; } mem_init
[] = {
100 if ( mem_tab
== NULL
){
101 mem_tab
= (struct tabent
*) xmalloc( MEM_SIZ
);
102 bzero( mem_tab
, MEM_SIZ
);
103 for ( i
= 0; mem_init
[i
].opcode
!= 0; i
++ ){
104 j
= mem_init
[i
].opcode
- MEM_MIN
;
105 mem_tab
[j
].name
= mem_init
[i
].name
;
106 mem_tab
[j
].numops
= mem_init
[i
].numops
;
110 i
= ((word1
>> 24) & 0xff) - MEM_MIN
;
111 mode
= (word1
>> 10) & 0xf;
113 if ( (mem_tab
[i
].name
!= NULL
) /* Valid instruction */
114 && ((mode
== 5) || (mode
>=12)) ){ /* With 32-bit displacement */
126 /* Read the i960 instruction at 'memaddr' and return the address of
127 the next instruction after that, or 0 if 'memaddr' is not the
128 address of a valid instruction. The first word of the instruction
129 is stored at 'pword1', and the second word, if any, is stored at
133 next_insn (memaddr
, pword1
, pword2
)
134 unsigned long *pword1
, *pword2
;
138 unsigned long buf
[2];
140 /* Read the two (potential) words of the instruction at once,
141 to eliminate the overhead of two calls to read_memory ().
142 TODO: read more instructions at once and cache them. */
144 read_memory (memaddr
, buf
, sizeof (buf
));
146 SWAP_TARGET_AND_HOST (pword1
, sizeof (long));
148 SWAP_TARGET_AND_HOST (pword2
, sizeof (long));
150 /* Divide instruction set into classes based on high 4 bits of opcode*/
152 switch ((*pword1
>> 28) & 0xf)
171 len
= mem (memaddr
, *pword1
, *pword2
, 1);
174 default: /* invalid instruction */
180 return memaddr
+ len
;
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