1 /* i80960 instruction disassembler for GDB.
2 Copyright (C) 1990-1991 Free Software Foundation, Inc.
4 This file is part of GDB.
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
24 extern char *reg_names
[];
26 static FILE *stream
; /* Output goes here */
27 static void print_addr();
35 static void invalid();
37 static void put_abs();
40 /* Print the i960 instruction at address 'memaddr' in debugged memory,
41 on stream 's'. Returns length of the instruction, in bytes. */
43 print_insn( memaddr
, s
)
47 unsigned int word1
, word2
;
50 word1
= read_memory_integer( memaddr
, 4 );
51 word2
= read_memory_integer( memaddr
+4, 4 );
52 return pinsn( memaddr
, word1
, word2
);
56 /* Read the i960 instruction at 'memaddr' and return the address of
57 the next instruction after that, or 0 if 'memaddr' is not the
58 address of a valid instruction. The first word of the instruction
59 is stored at 'pword1', and the second word, if any, is stored at
63 next_insn (memaddr
, pword1
, pword2
)
64 unsigned long *pword1
, *pword2
;
70 /* Read the two (potential) words of the instruction at once,
71 to eliminate the overhead of two calls to read_memory ().
72 TODO: read more instructions at once and cache them. */
74 read_memory (memaddr
, buf
, sizeof (buf
));
76 SWAP_TARGET_AND_HOST (pword1
, sizeof (long));
78 SWAP_TARGET_AND_HOST (pword2
, sizeof (long));
80 /* Divide instruction set into classes based on high 4 bits of opcode*/
82 switch ((*pword1
>> 28) & 0xf)
101 len
= mem (memaddr
, *pword1
, *pword2
, 1);
104 default: /* invalid instruction */
110 return memaddr
+ len
;
117 /*****************************************************************************
118 * All code below this point should be identical with that of
119 * the disassembler in gdmp960.
120 *****************************************************************************/
128 pinsn( memaddr
, word1
, word2
)
129 unsigned long memaddr
;
130 unsigned long word1
, word2
;
135 put_abs( word1
, word2
);
137 /* Divide instruction set into classes based on high 4 bits of opcode*/
139 switch ( (word1
>> 28) & 0xf ){
142 ctrl( memaddr
, word1
, word2
);
146 cobr( memaddr
, word1
, word2
);
158 instr_len
= mem( memaddr
, word1
, word2
, 0 );
161 /* invalid instruction, print as data word */
168 /****************************************/
170 /****************************************/
172 ctrl( memaddr
, word1
, word2
)
173 unsigned long memaddr
;
174 unsigned long word1
, word2
;
177 static struct tabent ctrl_tab
[] = {
187 "call", 1, /* 0x09 */
202 "faultno", 0, /* 0x18 */
203 "faultg", 0, /* 0x19 */
204 "faulte", 0, /* 0x1a */
205 "faultge", 0, /* 0x1b */
206 "faultl", 0, /* 0x1c */
207 "faultne", 0, /* 0x1d */
208 "faultle", 0, /* 0x1e */
209 "faulto", 0, /* 0x1f */
212 i
= (word1
>> 24) & 0xff;
213 if ( (ctrl_tab
[i
].name
== NULL
) || ((word1
& 1) != 0) ){
218 fputs( ctrl_tab
[i
].name
, stream
);
219 if ( word1
& 2 ){ /* Predicts branch not taken */
220 fputs( ".f", stream
);
223 if ( ctrl_tab
[i
].numops
== 1 ){
224 /* EXTRACT DISPLACEMENT AND CONVERT TO ADDRESS */
226 if ( word1
& 0x00800000 ){ /* Sign bit is set */
227 word1
|= (-1 & ~0xffffff); /* Sign extend */
229 putc( '\t', stream
);
230 print_addr( word1
+ memaddr
);
234 /****************************************/
236 /****************************************/
238 cobr( memaddr
, word1
, word2
)
239 unsigned long memaddr
;
240 unsigned long word1
, word2
;
246 static struct tabent cobr_tab
[] = {
247 "testno", 1, /* 0x20 */
248 "testg", 1, /* 0x21 */
249 "teste", 1, /* 0x22 */
250 "testge", 1, /* 0x23 */
251 "testl", 1, /* 0x24 */
252 "testne", 1, /* 0x25 */
253 "testle", 1, /* 0x26 */
254 "testo", 1, /* 0x27 */
264 "cmpobg", 3, /* 0x31 */
265 "cmpobe", 3, /* 0x32 */
266 "cmpobge", 3, /* 0x33 */
267 "cmpobl", 3, /* 0x34 */
268 "cmpobne", 3, /* 0x35 */
269 "cmpoble", 3, /* 0x36 */
271 "cmpibno", 3, /* 0x38 */
272 "cmpibg", 3, /* 0x39 */
273 "cmpibe", 3, /* 0x3a */
274 "cmpibge", 3, /* 0x3b */
275 "cmpibl", 3, /* 0x3c */
276 "cmpibne", 3, /* 0x3d */
277 "cmpible", 3, /* 0x3e */
278 "cmpibo", 3, /* 0x3f */
281 i
= ((word1
>> 24) & 0xff) - 0x20;
282 if ( cobr_tab
[i
].name
== NULL
){
287 fputs( cobr_tab
[i
].name
, stream
);
288 if ( word1
& 2 ){ /* Predicts branch not taken */
289 fputs( ".f", stream
);
291 putc( '\t', stream
);
293 src1
= (word1
>> 19) & 0x1f;
294 src2
= (word1
>> 14) & 0x1f;
296 if ( word1
& 0x02000 ){ /* M1 is 1 */
297 fprintf( stream
, "%d", src1
);
298 } else { /* M1 is 0 */
299 fputs( reg_names
[src1
], stream
);
302 if ( cobr_tab
[i
].numops
> 1 ){
303 if ( word1
& 1 ){ /* S2 is 1 */
304 fprintf( stream
, ",sf%d,", src2
);
305 } else { /* S1 is 0 */
306 fprintf( stream
, ",%s,", reg_names
[src2
] );
309 /* Extract displacement and convert to address
312 if ( word1
& 0x00001000 ){ /* Negative displacement */
313 word1
|= (-1 & ~0x1fff); /* Sign extend */
315 print_addr( memaddr
+ word1
);
319 /****************************************/
321 /****************************************/
322 static int /* returns instruction length: 4 or 8 */
323 mem( memaddr
, word1
, word2
, noprint
)
324 unsigned long memaddr
;
325 unsigned long word1
, word2
;
326 int noprint
; /* If TRUE, return instruction length, but
327 don't output any text. */
333 char *reg1
, *reg2
, *reg3
;
335 /* This lookup table is too sparse to make it worth typing in, but not
336 * so large as to make a sparse array necessary. We allocate the
337 * table at runtime, initialize all entries to empty, and copy the
338 * real ones in from an initialization table.
340 * NOTE: In this table, the meaning of 'numops' is:
342 * 2: 2 operands, load instruction
343 * -2: 2 operands, store instruction
345 static struct tabent
*mem_tab
= NULL
;
346 static struct { int opcode
; char *name
; char numops
; } mem_init
[] = {
369 #define MEM_SIZ ((MEM_MAX-MEM_MIN+1) * sizeof(struct tabent))
373 if ( mem_tab
== NULL
){
374 mem_tab
= (struct tabent
*) xmalloc( MEM_SIZ
);
375 bzero( mem_tab
, MEM_SIZ
);
376 for ( i
= 0; mem_init
[i
].opcode
!= 0; i
++ ){
377 j
= mem_init
[i
].opcode
- MEM_MIN
;
378 mem_tab
[j
].name
= mem_init
[i
].name
;
379 mem_tab
[j
].numops
= mem_init
[i
].numops
;
383 i
= ((word1
>> 24) & 0xff) - MEM_MIN
;
384 mode
= (word1
>> 10) & 0xf;
386 if ( (mem_tab
[i
].name
!= NULL
) /* Valid instruction */
387 && ((mode
== 5) || (mode
>=12)) ){ /* With 32-bit displacement */
397 if ( (mem_tab
[i
].name
== NULL
) || (mode
== 6) ){
402 fprintf( stream
, "%s\t", mem_tab
[i
].name
);
404 reg1
= reg_names
[ (word1
>> 19) & 0x1f ]; /* MEMB only */
405 reg2
= reg_names
[ (word1
>> 14) & 0x1f ];
406 reg3
= reg_names
[ word1
& 0x1f ]; /* MEMB only */
407 offset
= word1
& 0xfff; /* MEMA only */
409 switch ( mem_tab
[i
].numops
){
411 case 2: /* LOAD INSTRUCTION */
412 if ( mode
& 4 ){ /* MEMB FORMAT */
413 ea( memaddr
, mode
, reg2
, reg3
, word1
, word2
);
414 fprintf( stream
, ",%s", reg1
);
415 } else { /* MEMA FORMAT */
416 fprintf( stream
, "0x%x", offset
);
418 fprintf( stream
, "(%s)", reg2
);
420 fprintf( stream
, ",%s", reg1
);
424 case -2: /* STORE INSTRUCTION */
425 if ( mode
& 4 ){ /* MEMB FORMAT */
426 fprintf( stream
, "%s,", reg1
);
427 ea( memaddr
, mode
, reg2
, reg3
, word1
, word2
);
428 } else { /* MEMA FORMAT */
429 fprintf( stream
, "%s,0x%x", reg1
, offset
);
431 fprintf( stream
, "(%s)", reg2
);
436 case 1: /* BX/CALLX INSTRUCTION */
437 if ( mode
& 4 ){ /* MEMB FORMAT */
438 ea( memaddr
, mode
, reg2
, reg3
, word1
, word2
);
439 } else { /* MEMA FORMAT */
440 fprintf( stream
, "0x%x", offset
);
442 fprintf( stream
, "(%s)", reg2
);
451 /****************************************/
453 /****************************************/
466 /* This lookup table is too sparse to make it worth typing in, but not
467 * so large as to make a sparse array necessary. We allocate the
468 * table at runtime, initialize all entries to empty, and copy the
469 * real ones in from an initialization table.
471 * NOTE: In this table, the meaning of 'numops' is:
472 * 1: single operand, which is NOT a destination.
473 * -1: single operand, which IS a destination.
474 * 2: 2 operands, the 2nd of which is NOT a destination.
475 * -2: 2 operands, the 2nd of which IS a destination.
478 * If an opcode mnemonic begins with "F", it is a floating-point
479 * opcode (the "F" is not printed).
482 static struct tabent
*reg_tab
= NULL
;
483 static struct { int opcode
; char *name
; char numops
; } reg_init
[] = {
484 #define REG_MIN 0x580
499 0x58f, "alterbit", 3,
518 0x5ac, "scanbyte", 2,
535 0x613, "inspacc", -2,
541 0x640, "spanbit", -2,
542 0x641, "scanbit", -2,
547 0x646, "condrec", -2,
552 0x656, "receive", -2,
556 0x663, "sendserv", 1,
557 0x664, "resumprcs", 1,
558 0x665, "schedprcs", 1,
559 0x666, "saveprcs", 0,
560 0x668, "condwait", 1,
565 0x66d, "flushreg", 0,
571 0x675, "Fcvtilr", -2,
572 0x676, "Fscalerl", 3,
582 0x68a, "Flogbnr", -2,
583 0x68b, "Froundr", -2,
589 0x691, "Flogeprl", 3,
594 0x698, "Fsqrtrl", -2,
596 0x69a, "Flogbnrl", -2,
597 0x69b, "Froundrl", -2,
601 0x69f, "Fclassrl", 1,
603 0x6c1, "Fcvtril", -2,
604 0x6c2, "Fcvtzri", -2,
605 0x6c3, "Fcvtzril", -2,
610 0x6e3, "Fcpyrsre", 3,
626 #define REG_MAX 0x79f
627 #define REG_SIZ ((REG_MAX-REG_MIN+1) * sizeof(struct tabent))
631 if ( reg_tab
== NULL
){
632 reg_tab
= (struct tabent
*) xmalloc( REG_SIZ
);
633 bzero( reg_tab
, REG_SIZ
);
634 for ( i
= 0; reg_init
[i
].opcode
!= 0; i
++ ){
635 j
= reg_init
[i
].opcode
- REG_MIN
;
636 reg_tab
[j
].name
= reg_init
[i
].name
;
637 reg_tab
[j
].numops
= reg_init
[i
].numops
;
641 opcode
= ((word1
>> 20) & 0xff0) | ((word1
>> 7) & 0xf);
642 i
= opcode
- REG_MIN
;
644 if ( (opcode
<REG_MIN
) || (opcode
>REG_MAX
) || (reg_tab
[i
].name
==NULL
) ){
649 mnemp
= reg_tab
[i
].name
;
650 if ( *mnemp
== 'F' ){
657 fputs( mnemp
, stream
);
659 s1
= (word1
>> 5) & 1;
660 s2
= (word1
>> 6) & 1;
661 m1
= (word1
>> 11) & 1;
662 m2
= (word1
>> 12) & 1;
663 m3
= (word1
>> 13) & 1;
665 src2
= (word1
>> 14) & 0x1f;
666 dst
= (word1
>> 19) & 0x1f;
668 if ( reg_tab
[i
].numops
!= 0 ){
669 putc( '\t', stream
);
671 switch ( reg_tab
[i
].numops
){
673 regop( m1
, s1
, src
, fp
);
676 dstop( m3
, dst
, fp
);
679 regop( m1
, s1
, src
, fp
);
681 regop( m2
, s2
, src2
, fp
);
684 regop( m1
, s1
, src
, fp
);
686 dstop( m3
, dst
, fp
);
689 regop( m1
, s1
, src
, fp
);
691 regop( m2
, s2
, src2
, fp
);
693 dstop( m3
, dst
, fp
);
701 * Print out effective address for memb instructions.
704 ea( memaddr
, mode
, reg2
, reg3
, word1
, word2
)
705 unsigned long memaddr
;
711 static int scale_tab
[] = { 1, 2, 4, 8, 16 };
713 scale
= (word1
>> 7) & 0x07;
714 if ( (scale
> 4) || ((word1
>> 5) & 0x03 != 0) ){
718 scale
= scale_tab
[scale
];
722 fprintf( stream
, "(%s)", reg2
);
724 case 5: /* displ+8(ip) */
725 print_addr( word2
+8+memaddr
);
727 case 7: /* (reg)[index*scale] */
729 fprintf( stream
, "(%s)[%s]", reg2
, reg3
);
731 fprintf( stream
, "(%s)[%s*%d]",reg2
,reg3
,scale
);
734 case 12: /* displacement */
737 case 13: /* displ(reg) */
739 fprintf( stream
, "(%s)", reg2
);
741 case 14: /* displ[index*scale] */
744 fprintf( stream
, "[%s]", reg3
);
746 fprintf( stream
, "[%s*%d]", reg3
, scale
);
749 case 15: /* displ(reg)[index*scale] */
752 fprintf( stream
, "(%s)[%s]", reg2
, reg3
);
754 fprintf( stream
, "(%s)[%s*%d]",reg2
,reg3
,scale
);
764 /************************************************/
765 /* Register Instruction Operand */
766 /************************************************/
768 regop( mode
, spec
, reg
, fp
)
769 int mode
, spec
, reg
, fp
;
771 if ( fp
){ /* FLOATING POINT INSTRUCTION */
772 if ( mode
== 1 ){ /* FP operand */
774 case 0: fputs( "fp0", stream
); break;
775 case 1: fputs( "fp1", stream
); break;
776 case 2: fputs( "fp2", stream
); break;
777 case 3: fputs( "fp3", stream
); break;
778 case 16: fputs( "0f0.0", stream
); break;
779 case 22: fputs( "0f1.0", stream
); break;
780 default: putc( '?', stream
); break;
782 } else { /* Non-FP register */
783 fputs( reg_names
[reg
], stream
);
785 } else { /* NOT FLOATING POINT */
786 if ( mode
== 1 ){ /* Literal */
787 fprintf( stream
, "%d", reg
);
788 } else { /* Register */
790 fputs( reg_names
[reg
], stream
);
792 fprintf( stream
, "sf%d", reg
);
798 /************************************************/
799 /* Register Instruction Destination Operand */
800 /************************************************/
802 dstop( mode
, reg
, fp
)
805 /* 'dst' operand can't be a literal. On non-FP instructions, register
806 * mode is assumed and "m3" acts as if were "s3"; on FP-instructions,
807 * sf registers are not allowed so m3 acts normally.
810 regop( mode
, 0, reg
, fp
);
812 regop( 0, mode
, reg
, fp
);
821 fprintf( stream
, ".word\t0x%08x", word1
);
827 fprintf( stream
, "0x%x", a
);
831 put_abs( word1
, word2
)
832 unsigned long word1
, word2
;
839 switch ( (word1
>> 28) & 0xf ){
845 /* MEM format instruction */
846 len
= mem( 0, word1
, word2
, 1 );
854 fprintf( stream
, "%08x %08x\t", word1
, word2
);
856 fprintf( stream
, "%08x \t", word1
);
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