1 /* Target-machine dependent code for the Intel 960
2 Copyright 1991, 1992, 1993, 1994, 1995 Free Software Foundation, Inc.
3 Contributed by Intel Corporation.
4 examine_prologue and other parts contributed by Wind River Systems.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
26 #include "floatformat.h"
30 static CORE_ADDR next_insn
PARAMS ((CORE_ADDR memaddr
,
32 unsigned int *pword2
));
34 /* Does the specified function use the "struct returning" convention
35 or the "value returning" convention? The "value returning" convention
36 almost invariably returns the entire value in registers. The
37 "struct returning" convention often returns the entire value in
38 memory, and passes a pointer (out of or into the function) saying
39 where the value (is or should go).
41 Since this sometimes depends on whether it was compiled with GCC,
42 this is also an argument. This is used in call_function to build a
43 stack, and in value_being_returned to print return values.
45 On i960, a structure is returned in registers g0-g3, if it will fit.
46 If it's more than 16 bytes long, g13 pointed to it on entry. */
49 i960_use_struct_convention (gcc_p
, type
)
53 return (TYPE_LENGTH (type
) > 16);
56 /* gdb960 is always running on a non-960 host. Check its characteristics.
57 This routine must be called as part of gdb initialization. */
64 static struct typestruct
{
65 int hostsize
; /* Size of type on host */
66 int i960size
; /* Size of type on i960 */
67 char *typename
; /* Name of type, for error msg */
69 { sizeof(short), 2, "short" },
70 { sizeof(int), 4, "int" },
71 { sizeof(long), 4, "long" },
72 { sizeof(float), 4, "float" },
73 { sizeof(double), 8, "double" },
74 { sizeof(char *), 4, "pointer" },
76 #define TYPELEN (sizeof(types) / sizeof(struct typestruct))
78 /* Make sure that host type sizes are same as i960
80 for ( i
= 0; i
< TYPELEN
; i
++ ){
81 if ( types
[i
].hostsize
!= types
[i
].i960size
){
82 printf_unfiltered("sizeof(%s) != %d: PROCEED AT YOUR OWN RISK!\n",
83 types
[i
].typename
, types
[i
].i960size
);
89 /* Examine an i960 function prologue, recording the addresses at which
90 registers are saved explicitly by the prologue code, and returning
91 the address of the first instruction after the prologue (but not
92 after the instruction at address LIMIT, as explained below).
94 LIMIT places an upper bound on addresses of the instructions to be
95 examined. If the prologue code scan reaches LIMIT, the scan is
96 aborted and LIMIT is returned. This is used, when examining the
97 prologue for the current frame, to keep examine_prologue () from
98 claiming that a given register has been saved when in fact the
99 instruction that saves it has not yet been executed. LIMIT is used
100 at other times to stop the scan when we hit code after the true
101 function prologue (e.g. for the first source line) which might
102 otherwise be mistaken for function prologue.
104 The format of the function prologue matched by this routine is
105 derived from examination of the source to gcc960 1.21, particularly
106 the routine i960_function_prologue (). A "regular expression" for
107 the function prologue is given below:
111 (mov 0, g14) | (lda 0, g14))?
113 (mov[qtl]? g[0-15], r[4-15])*
114 ((addo [1-31], sp, sp) | (lda n(sp), sp))?
115 (st[qtl]? g[0-15], n(fp))*
128 /* Macros for extracting fields from i960 instructions. */
130 #define BITMASK(pos, width) (((0x1 << (width)) - 1) << (pos))
131 #define EXTRACT_FIELD(val, pos, width) ((val) >> (pos) & BITMASK (0, width))
133 #define REG_SRC1(insn) EXTRACT_FIELD (insn, 0, 5)
134 #define REG_SRC2(insn) EXTRACT_FIELD (insn, 14, 5)
135 #define REG_SRCDST(insn) EXTRACT_FIELD (insn, 19, 5)
136 #define MEM_SRCDST(insn) EXTRACT_FIELD (insn, 19, 5)
137 #define MEMA_OFFSET(insn) EXTRACT_FIELD (insn, 0, 12)
139 /* Fetch the instruction at ADDR, returning 0 if ADDR is beyond LIM or
140 is not the address of a valid instruction, the address of the next
141 instruction beyond ADDR otherwise. *PWORD1 receives the first word
142 of the instruction, and (for two-word instructions), *PWORD2 receives
145 #define NEXT_PROLOGUE_INSN(addr, lim, pword1, pword2) \
146 (((addr) < (lim)) ? next_insn (addr, pword1, pword2) : 0)
149 examine_prologue (ip
, limit
, frame_addr
, fsr
)
150 register CORE_ADDR ip
;
151 register CORE_ADDR limit
;
152 CORE_ADDR frame_addr
;
153 struct frame_saved_regs
*fsr
;
155 register CORE_ADDR next_ip
;
156 register int src
, dst
;
157 register unsigned int *pcode
;
158 unsigned int insn1
, insn2
;
160 int within_leaf_prologue
;
162 static unsigned int varargs_prologue_code
[] =
164 0x3507a00c, /* cmpobne 0x0, g14, LFn */
165 0x5cf01601, /* mov sp, g14 */
166 0x8c086030, /* lda 0x30(sp), sp */
167 0xb2879000, /* LFn: stq g0, (g14) */
168 0xb2a7a010, /* stq g4, 0x10(g14) */
169 0xb2c7a020 /* stq g8, 0x20(g14) */
172 /* Accept a leaf procedure prologue code fragment if present.
173 Note that ip might point to either the leaf or non-leaf
174 entry point; we look for the non-leaf entry point first: */
176 within_leaf_prologue
= 0;
177 if ((next_ip
= NEXT_PROLOGUE_INSN (ip
, limit
, &insn1
, &insn2
))
178 && ((insn1
& 0xfffff000) == 0x8cf00000 /* lda LRx, g14 (MEMA) */
179 || (insn1
& 0xfffffc60) == 0x8cf03000)) /* lda LRx, g14 (MEMB) */
181 within_leaf_prologue
= 1;
182 next_ip
= NEXT_PROLOGUE_INSN (next_ip
, limit
, &insn1
, &insn2
);
185 /* Now look for the prologue code at a leaf entry point: */
188 && (insn1
& 0xff87ffff) == 0x5c80161e /* mov g14, gx */
189 && REG_SRCDST (insn1
) <= G0_REGNUM
+ 7)
191 within_leaf_prologue
= 1;
192 if ((next_ip
= NEXT_PROLOGUE_INSN (next_ip
, limit
, &insn1
, &insn2
))
193 && (insn1
== 0x8cf00000 /* lda 0, g14 */
194 || insn1
== 0x5cf01e00)) /* mov 0, g14 */
197 next_ip
= NEXT_PROLOGUE_INSN (ip
, limit
, &insn1
, &insn2
);
198 within_leaf_prologue
= 0;
202 /* If something that looks like the beginning of a leaf prologue
203 has been seen, but the remainder of the prologue is missing, bail.
204 We don't know what we've got. */
206 if (within_leaf_prologue
)
209 /* Accept zero or more instances of "mov[qtl]? gx, ry", where y >= 4.
210 This may cause us to mistake the moving of a register
211 parameter to a local register for the saving of a callee-saved
212 register, but that can't be helped, since with the
213 "-fcall-saved" flag, any register can be made callee-saved. */
216 && (insn1
& 0xfc802fb0) == 0x5c000610
217 && (dst
= REG_SRCDST (insn1
)) >= (R0_REGNUM
+ 4))
219 src
= REG_SRC1 (insn1
);
220 size
= EXTRACT_FIELD (insn1
, 24, 2) + 1;
221 save_addr
= frame_addr
+ ((dst
- R0_REGNUM
) * 4);
224 fsr
->regs
[src
++] = save_addr
;
228 next_ip
= NEXT_PROLOGUE_INSN (ip
, limit
, &insn1
, &insn2
);
231 /* Accept an optional "addo n, sp, sp" or "lda n(sp), sp". */
234 ((insn1
& 0xffffffe0) == 0x59084800 /* addo n, sp, sp */
235 || (insn1
& 0xfffff000) == 0x8c086000 /* lda n(sp), sp (MEMA) */
236 || (insn1
& 0xfffffc60) == 0x8c087400)) /* lda n(sp), sp (MEMB) */
239 next_ip
= NEXT_PROLOGUE_INSN (ip
, limit
, &insn1
, &insn2
);
242 /* Accept zero or more instances of "st[qtl]? gx, n(fp)".
243 This may cause us to mistake the copying of a register
244 parameter to the frame for the saving of a callee-saved
245 register, but that can't be helped, since with the
246 "-fcall-saved" flag, any register can be made callee-saved.
247 We can, however, refuse to accept a save of register g14,
248 since that is matched explicitly below. */
251 ((insn1
& 0xf787f000) == 0x9287e000 /* stl? gx, n(fp) (MEMA) */
252 || (insn1
& 0xf787fc60) == 0x9287f400 /* stl? gx, n(fp) (MEMB) */
253 || (insn1
& 0xef87f000) == 0xa287e000 /* st[tq] gx, n(fp) (MEMA) */
254 || (insn1
& 0xef87fc60) == 0xa287f400) /* st[tq] gx, n(fp) (MEMB) */
255 && ((src
= MEM_SRCDST (insn1
)) != G14_REGNUM
))
257 save_addr
= frame_addr
+ ((insn1
& BITMASK (12, 1))
258 ? insn2
: MEMA_OFFSET (insn1
));
259 size
= (insn1
& BITMASK (29, 1)) ? ((insn1
& BITMASK (28, 1)) ? 4 : 3)
260 : ((insn1
& BITMASK (27, 1)) ? 2 : 1);
263 fsr
->regs
[src
++] = save_addr
;
267 next_ip
= NEXT_PROLOGUE_INSN (ip
, limit
, &insn1
, &insn2
);
270 /* Accept the varargs prologue code if present. */
272 size
= sizeof (varargs_prologue_code
) / sizeof (int);
273 pcode
= varargs_prologue_code
;
274 while (size
-- && next_ip
&& *pcode
++ == insn1
)
277 next_ip
= NEXT_PROLOGUE_INSN (ip
, limit
, &insn1
, &insn2
);
280 /* Accept an optional "st g14, n(fp)". */
283 ((insn1
& 0xfffff000) == 0x92f7e000 /* st g14, n(fp) (MEMA) */
284 || (insn1
& 0xfffffc60) == 0x92f7f400)) /* st g14, n(fp) (MEMB) */
286 fsr
->regs
[G14_REGNUM
] = frame_addr
+ ((insn1
& BITMASK (12, 1))
287 ? insn2
: MEMA_OFFSET (insn1
));
289 next_ip
= NEXT_PROLOGUE_INSN (ip
, limit
, &insn1
, &insn2
);
292 /* Accept zero or one instance of "mov g13, ry", where y >= 4.
293 This is saving the address where a struct should be returned. */
296 && (insn1
& 0xff802fbf) == 0x5c00061d
297 && (dst
= REG_SRCDST (insn1
)) >= (R0_REGNUM
+ 4))
299 save_addr
= frame_addr
+ ((dst
- R0_REGNUM
) * 4);
300 fsr
->regs
[G0_REGNUM
+13] = save_addr
;
302 #if 0 /* We'll need this once there is a subsequent instruction examined. */
303 next_ip
= NEXT_PROLOGUE_INSN (ip
, limit
, &insn1
, &insn2
);
310 /* Given an ip value corresponding to the start of a function,
311 return the ip of the first instruction after the function
318 struct frame_saved_regs saved_regs_dummy
;
319 struct symtab_and_line sal
;
322 sal
= find_pc_line (ip
, 0);
323 limit
= (sal
.end
) ? sal
.end
: 0xffffffff;
325 return (examine_prologue (ip
, limit
, (CORE_ADDR
) 0, &saved_regs_dummy
));
328 /* Put here the code to store, into a struct frame_saved_regs,
329 the addresses of the saved registers of frame described by FRAME_INFO.
330 This includes special registers such as pc and fp saved in special
331 ways in the stack frame. sp is even more special:
332 the address we return for it IS the sp for the next frame.
334 We cache the result of doing this in the frame_cache_obstack, since
335 it is fairly expensive. */
338 frame_find_saved_regs (fi
, fsr
)
339 struct frame_info
*fi
;
340 struct frame_saved_regs
*fsr
;
342 register CORE_ADDR next_addr
;
343 register CORE_ADDR
*saved_regs
;
345 register struct frame_saved_regs
*cache_fsr
;
346 extern struct obstack frame_cache_obstack
;
348 struct symtab_and_line sal
;
353 cache_fsr
= (struct frame_saved_regs
*)
354 obstack_alloc (&frame_cache_obstack
,
355 sizeof (struct frame_saved_regs
));
356 memset (cache_fsr
, '\0', sizeof (struct frame_saved_regs
));
359 /* Find the start and end of the function prologue. If the PC
360 is in the function prologue, we only consider the part that
361 has executed already. */
363 ip
= get_pc_function_start (fi
->pc
);
364 sal
= find_pc_line (ip
, 0);
365 limit
= (sal
.end
&& sal
.end
< fi
->pc
) ? sal
.end
: fi
->pc
;
367 examine_prologue (ip
, limit
, fi
->frame
, cache_fsr
);
369 /* Record the addresses at which the local registers are saved.
370 Strictly speaking, we should only do this for non-leaf procedures,
371 but no one will ever look at these values if it is a leaf procedure,
372 since local registers are always caller-saved. */
374 next_addr
= (CORE_ADDR
) fi
->frame
;
375 saved_regs
= cache_fsr
->regs
;
376 for (regnum
= R0_REGNUM
; regnum
<= R15_REGNUM
; regnum
++)
378 *saved_regs
++ = next_addr
;
382 cache_fsr
->regs
[FP_REGNUM
] = cache_fsr
->regs
[PFP_REGNUM
];
387 /* Fetch the value of the sp from memory every time, since it
388 is conceivable that it has changed since the cache was flushed.
389 This unfortunately undoes much of the savings from caching the
390 saved register values. I suggest adding an argument to
391 get_frame_saved_regs () specifying the register number we're
392 interested in (or -1 for all registers). This would be passed
393 through to FRAME_FIND_SAVED_REGS (), permitting more efficient
394 computation of saved register addresses (e.g., on the i960,
395 we don't have to examine the prologue to find local registers).
397 FIXME, we don't need to refetch this, since the cache is cleared
398 every time the child process is restarted. If GDB itself
399 modifies SP, it has to clear the cache by hand (does it?). -gnu */
401 fsr
->regs
[SP_REGNUM
] = read_memory_integer (fsr
->regs
[SP_REGNUM
], 4);
404 /* Return the address of the argument block for the frame
405 described by FI. Returns 0 if the address is unknown. */
408 frame_args_address (fi
, must_be_correct
)
409 struct frame_info
*fi
;
411 struct frame_saved_regs fsr
;
414 /* If g14 was saved in the frame by the function prologue code, return
415 the saved value. If the frame is current and we are being sloppy,
416 return the value of g14. Otherwise, return zero. */
418 get_frame_saved_regs (fi
, &fsr
);
419 if (fsr
.regs
[G14_REGNUM
])
420 ap
= read_memory_integer (fsr
.regs
[G14_REGNUM
],4);
424 return 0; /* Don't cache this result */
425 if (get_next_frame (fi
))
428 ap
= read_register (G14_REGNUM
);
432 fi
->arg_pointer
= ap
; /* Cache it for next time */
436 /* Return the address of the return struct for the frame
437 described by FI. Returns 0 if the address is unknown. */
440 frame_struct_result_address (fi
)
441 struct frame_info
*fi
;
443 struct frame_saved_regs fsr
;
446 /* If the frame is non-current, check to see if g14 was saved in the
447 frame by the function prologue code; return the saved value if so,
448 zero otherwise. If the frame is current, return the value of g14.
450 FIXME, shouldn't this use the saved value as long as we are past
451 the function prologue, and only use the current value if we have
452 no saved value and are at TOS? -- gnu@cygnus.com */
454 if (get_next_frame (fi
))
456 get_frame_saved_regs (fi
, &fsr
);
457 if (fsr
.regs
[G13_REGNUM
])
458 ap
= read_memory_integer (fsr
.regs
[G13_REGNUM
],4);
463 ap
= read_register (G13_REGNUM
);
468 /* Return address to which the currently executing leafproc will return,
469 or 0 if ip is not in a leafproc (or if we can't tell if it is).
471 Do this by finding the starting address of the routine in which ip lies.
472 If the instruction there is "mov g14, gx" (where x is in [0,7]), this
473 is a leafproc and the return address is in register gx. Well, this is
474 true unless the return address points at a RET instruction in the current
475 procedure, which indicates that we have a 'dual entry' routine that
476 has been entered through the CALL entry point. */
480 CORE_ADDR ip
; /* ip from currently executing function */
482 register struct minimal_symbol
*msymbol
;
485 unsigned int insn1
, insn2
;
486 CORE_ADDR return_addr
;
488 if ((msymbol
= lookup_minimal_symbol_by_pc (ip
)) != NULL
)
490 if ((p
= strchr(SYMBOL_NAME (msymbol
), '.')) && STREQ (p
, ".lf"))
492 if (next_insn (SYMBOL_VALUE_ADDRESS (msymbol
), &insn1
, &insn2
)
493 && (insn1
& 0xff87ffff) == 0x5c80161e /* mov g14, gx */
494 && (dst
= REG_SRCDST (insn1
)) <= G0_REGNUM
+ 7)
496 /* Get the return address. If the "mov g14, gx"
497 instruction hasn't been executed yet, read
498 the return address from g14; otherwise, read it
499 from the register into which g14 was moved. */
502 read_register ((ip
== SYMBOL_VALUE_ADDRESS (msymbol
))
505 /* We know we are in a leaf procedure, but we don't know
506 whether the caller actually did a "bal" to the ".lf"
507 entry point, or a normal "call" to the non-leaf entry
508 point one instruction before. In the latter case, the
509 return address will be the address of a "ret"
510 instruction within the procedure itself. We test for
513 if (!next_insn (return_addr
, &insn1
, &insn2
)
514 || (insn1
& 0xff000000) != 0xa000000 /* ret */
515 || lookup_minimal_symbol_by_pc (return_addr
) != msymbol
)
516 return (return_addr
);
524 /* Immediately after a function call, return the saved pc.
525 Can't go through the frames for this because on some machines
526 the new frame is not set up until the new function executes
528 On the i960, the frame *is* set up immediately after the call,
529 unless the function is a leaf procedure. */
532 saved_pc_after_call (frame
)
533 struct frame_info
*frame
;
537 saved_pc
= leafproc_return (get_frame_pc (frame
));
539 saved_pc
= FRAME_SAVED_PC (frame
);
544 /* Discard from the stack the innermost frame,
545 restoring all saved registers. */
550 register struct frame_info
*current_fi
, *prev_fi
;
553 CORE_ADDR leaf_return_addr
;
554 struct frame_saved_regs fsr
;
555 char local_regs_buf
[16 * 4];
557 current_fi
= get_current_frame ();
559 /* First, undo what the hardware does when we return.
560 If this is a non-leaf procedure, restore local registers from
561 the save area in the calling frame. Otherwise, load the return
562 address obtained from leafproc_return () into the rip. */
564 leaf_return_addr
= leafproc_return (current_fi
->pc
);
565 if (!leaf_return_addr
)
567 /* Non-leaf procedure. Restore local registers, incl IP. */
568 prev_fi
= get_prev_frame (current_fi
);
569 read_memory (prev_fi
->frame
, local_regs_buf
, sizeof (local_regs_buf
));
570 write_register_bytes (REGISTER_BYTE (R0_REGNUM
), local_regs_buf
,
571 sizeof (local_regs_buf
));
573 /* Restore frame pointer. */
574 write_register (FP_REGNUM
, prev_fi
->frame
);
578 /* Leaf procedure. Just restore the return address into the IP. */
579 write_register (RIP_REGNUM
, leaf_return_addr
);
582 /* Now restore any global regs that the current function had saved. */
583 get_frame_saved_regs (current_fi
, &fsr
);
584 for (i
= G0_REGNUM
; i
< G14_REGNUM
; i
++)
586 if (save_addr
= fsr
.regs
[i
])
587 write_register (i
, read_memory_integer (save_addr
, 4));
590 /* Flush the frame cache, create a frame for the new innermost frame,
591 and make it the current frame. */
593 flush_cached_frames ();
596 /* Given a 960 stop code (fault or trace), return the signal which
600 i960_fault_to_signal (fault
)
605 case 0: return TARGET_SIGNAL_BUS
; /* parallel fault */
606 case 1: return TARGET_SIGNAL_UNKNOWN
;
607 case 2: return TARGET_SIGNAL_ILL
; /* operation fault */
608 case 3: return TARGET_SIGNAL_FPE
; /* arithmetic fault */
609 case 4: return TARGET_SIGNAL_FPE
; /* floating point fault */
611 /* constraint fault. This appears not to distinguish between
612 a range constraint fault (which should be SIGFPE) and a privileged
613 fault (which should be SIGILL). */
614 case 5: return TARGET_SIGNAL_ILL
;
616 case 6: return TARGET_SIGNAL_SEGV
; /* virtual memory fault */
618 /* protection fault. This is for an out-of-range argument to
619 "calls". I guess it also could be SIGILL. */
620 case 7: return TARGET_SIGNAL_SEGV
;
622 case 8: return TARGET_SIGNAL_BUS
; /* machine fault */
623 case 9: return TARGET_SIGNAL_BUS
; /* structural fault */
624 case 0xa: return TARGET_SIGNAL_ILL
; /* type fault */
625 case 0xb: return TARGET_SIGNAL_UNKNOWN
; /* reserved fault */
626 case 0xc: return TARGET_SIGNAL_BUS
; /* process fault */
627 case 0xd: return TARGET_SIGNAL_SEGV
; /* descriptor fault */
628 case 0xe: return TARGET_SIGNAL_BUS
; /* event fault */
629 case 0xf: return TARGET_SIGNAL_UNKNOWN
; /* reserved fault */
630 case 0x10: return TARGET_SIGNAL_TRAP
; /* single-step trace */
631 case 0x11: return TARGET_SIGNAL_TRAP
; /* branch trace */
632 case 0x12: return TARGET_SIGNAL_TRAP
; /* call trace */
633 case 0x13: return TARGET_SIGNAL_TRAP
; /* return trace */
634 case 0x14: return TARGET_SIGNAL_TRAP
; /* pre-return trace */
635 case 0x15: return TARGET_SIGNAL_TRAP
; /* supervisor call trace */
636 case 0x16: return TARGET_SIGNAL_TRAP
; /* breakpoint trace */
637 default: return TARGET_SIGNAL_UNKNOWN
;
641 /****************************************/
643 /****************************************/
650 static int /* returns instruction length: 4 or 8 */
651 mem( memaddr
, word1
, word2
, noprint
)
652 unsigned long memaddr
;
653 unsigned long word1
, word2
;
654 int noprint
; /* If TRUE, return instruction length, but
655 don't output any text. */
661 const char *reg1
, *reg2
, *reg3
;
663 /* This lookup table is too sparse to make it worth typing in, but not
664 * so large as to make a sparse array necessary. We allocate the
665 * table at runtime, initialize all entries to empty, and copy the
666 * real ones in from an initialization table.
668 * NOTE: In this table, the meaning of 'numops' is:
670 * 2: 2 operands, load instruction
671 * -2: 2 operands, store instruction
673 static struct tabent
*mem_tab
= NULL
;
674 /* Opcodes of 0x8X, 9X, aX, bX, and cX must be in the table. */
677 #define MEM_SIZ ((MEM_MAX-MEM_MIN+1) * sizeof(struct tabent))
679 static struct { int opcode
; char *name
; char numops
; } mem_init
[] = {
703 if ( mem_tab
== NULL
){
704 mem_tab
= (struct tabent
*) xmalloc( MEM_SIZ
);
705 memset( mem_tab
, '\0', MEM_SIZ
);
706 for ( i
= 0; mem_init
[i
].opcode
!= 0; i
++ ){
707 j
= mem_init
[i
].opcode
- MEM_MIN
;
708 mem_tab
[j
].name
= mem_init
[i
].name
;
709 mem_tab
[j
].numops
= mem_init
[i
].numops
;
713 i
= ((word1
>> 24) & 0xff) - MEM_MIN
;
714 mode
= (word1
>> 10) & 0xf;
716 if ( (mem_tab
[i
].name
!= NULL
) /* Valid instruction */
717 && ((mode
== 5) || (mode
>=12)) ){ /* With 32-bit displacement */
729 /* Read the i960 instruction at 'memaddr' and return the address of
730 the next instruction after that, or 0 if 'memaddr' is not the
731 address of a valid instruction. The first word of the instruction
732 is stored at 'pword1', and the second word, if any, is stored at
736 next_insn (memaddr
, pword1
, pword2
)
737 unsigned int *pword1
, *pword2
;
743 /* Read the two (potential) words of the instruction at once,
744 to eliminate the overhead of two calls to read_memory ().
745 FIXME: Loses if the first one is readable but the second is not
746 (e.g. last word of the segment). */
748 read_memory (memaddr
, buf
, 8);
749 *pword1
= extract_unsigned_integer (buf
, 4);
750 *pword2
= extract_unsigned_integer (buf
+ 4, 4);
752 /* Divide instruction set into classes based on high 4 bits of opcode*/
754 switch ((*pword1
>> 28) & 0xf)
773 len
= mem (memaddr
, *pword1
, *pword2
, 1);
776 default: /* invalid instruction */
782 return memaddr
+ len
;
787 /* 'start_frame' is a variable in the MON960 runtime startup routine
788 that contains the frame pointer of the 'start' routine (the routine
789 that calls 'main'). By reading its contents out of remote memory,
790 we can tell where the frame chain ends: backtraces should halt before
791 they display this frame. */
794 mon960_frame_chain_valid (chain
, curframe
)
796 struct frame_info
*curframe
;
799 struct minimal_symbol
*msymbol
;
801 /* crtmon960.o is an assembler module that is assumed to be linked
802 * first in an i80960 executable. It contains the true entry point;
803 * it performs startup up initialization and then calls 'main'.
805 * 'sf' is the name of a variable in crtmon960.o that is set
806 * during startup to the address of the first frame.
808 * 'a' is the address of that variable in 80960 memory.
810 static char sf
[] = "start_frame";
814 chain
&= ~0x3f; /* Zero low 6 bits because previous frame pointers
815 contain return status info in them. */
820 sym
= lookup_symbol(sf
, 0, VAR_NAMESPACE
, (int *)NULL
,
821 (struct symtab
**)NULL
);
823 a
= SYMBOL_VALUE (sym
);
825 msymbol
= lookup_minimal_symbol (sf
, NULL
, NULL
);
828 a
= SYMBOL_VALUE_ADDRESS (msymbol
);
831 return ( chain
!= read_memory_integer(a
,4) );
835 _initialize_i960_tdep ()
839 tm_print_insn
= print_insn_i960
;