1 /* Target-machine dependent code for the Intel 960
3 Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000,
4 2001, 2002 Free Software Foundation, Inc.
6 Contributed by Intel Corporation.
7 examine_prologue and other parts contributed by Wind River Systems.
9 This file is part of GDB.
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software
23 Foundation, Inc., 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
30 #include "floatformat.h"
35 #include "gdb_string.h"
37 static CORE_ADDR
next_insn (CORE_ADDR memaddr
,
38 unsigned int *pword1
, unsigned int *pword2
);
41 i960_register_type (int regnum
)
43 if (regnum
< FP0_REGNUM
)
44 return builtin_type_int32
;
46 return builtin_type_i960_ext
;
50 /* Does the specified function use the "struct returning" convention
51 or the "value returning" convention? The "value returning" convention
52 almost invariably returns the entire value in registers. The
53 "struct returning" convention often returns the entire value in
54 memory, and passes a pointer (out of or into the function) saying
55 where the value (is or should go).
57 Since this sometimes depends on whether it was compiled with GCC,
58 this is also an argument. This is used in call_function to build a
59 stack, and in value_being_returned to print return values.
61 On i960, a structure is returned in registers g0-g3, if it will fit.
62 If it's more than 16 bytes long, g13 pointed to it on entry. */
65 i960_use_struct_convention (int gcc_p
, struct type
*type
)
67 return (TYPE_LENGTH (type
) > 16);
70 /* gdb960 is always running on a non-960 host. Check its characteristics.
71 This routine must be called as part of gdb initialization. */
78 static struct typestruct
80 int hostsize
; /* Size of type on host */
81 int i960size
; /* Size of type on i960 */
82 char *typename
; /* Name of type, for error msg */
87 sizeof (short), 2, "short"
91 sizeof (int), 4, "int"
95 sizeof (long), 4, "long"
99 sizeof (float), 4, "float"
103 sizeof (double), 8, "double"
107 sizeof (char *), 4, "pointer"
111 #define TYPELEN (sizeof(types) / sizeof(struct typestruct))
113 /* Make sure that host type sizes are same as i960
115 for (i
= 0; i
< TYPELEN
; i
++)
117 if (types
[i
].hostsize
!= types
[i
].i960size
)
119 printf_unfiltered ("sizeof(%s) != %d: PROCEED AT YOUR OWN RISK!\n",
120 types
[i
].typename
, types
[i
].i960size
);
126 /* Is this register part of the register window system? A yes answer
127 implies that 1) The name of this register will not be the same in
128 other frames, and 2) This register is automatically "saved" upon
129 subroutine calls and thus there is no need to search more than one
132 On the i960, in fact, the name of this register in another frame is
133 "mud" -- there is no overlap between the windows. Each window is
134 simply saved into the stack (true for our purposes, after having been
135 flushed; normally they reside on-chip and are restored from on-chip
136 without ever going to memory). */
139 register_in_window_p (int regnum
)
141 return regnum
<= R15_REGNUM
;
144 /* i960_find_saved_register ()
146 Return the address in which frame FRAME's value of register REGNUM
147 has been saved in memory. Or return zero if it has not been saved.
148 If REGNUM specifies the SP, the value we return is actually the SP
149 value, not an address where it was saved. */
152 i960_find_saved_register (struct frame_info
*frame
, int regnum
)
154 register struct frame_info
*frame1
= NULL
;
155 register CORE_ADDR addr
= 0;
157 if (frame
== NULL
) /* No regs saved if want current frame */
160 /* We assume that a register in a register window will only be saved
161 in one place (since the name changes and/or disappears as you go
162 towards inner frames), so we only call get_frame_saved_regs on
163 the current frame. This is directly in contradiction to the
164 usage below, which assumes that registers used in a frame must be
165 saved in a lower (more interior) frame. This change is a result
166 of working on a register window machine; get_frame_saved_regs
167 always returns the registers saved within a frame, within the
168 context (register namespace) of that frame. */
170 /* However, note that we don't want this to return anything if
171 nothing is saved (if there's a frame inside of this one). Also,
172 callers to this routine asking for the stack pointer want the
173 stack pointer saved for *this* frame; this is returned from the
176 if (register_in_window_p (regnum
))
178 frame1
= get_next_frame (frame
);
180 return 0; /* Registers of this frame are active. */
182 /* Get the SP from the next frame in; it will be this
184 if (regnum
!= SP_REGNUM
)
187 FRAME_INIT_SAVED_REGS (frame1
);
188 return frame1
->saved_regs
[regnum
]; /* ... which might be zero */
191 /* Note that this next routine assumes that registers used in
192 frame x will be saved only in the frame that x calls and
193 frames interior to it. This is not true on the sparc, but the
194 above macro takes care of it, so we should be all right. */
198 frame1
= get_next_frame (frame
);
202 FRAME_INIT_SAVED_REGS (frame1
);
203 if (frame1
->saved_regs
[regnum
])
204 addr
= frame1
->saved_regs
[regnum
];
210 /* i960_get_saved_register ()
212 Find register number REGNUM relative to FRAME and put its (raw,
213 target format) contents in *RAW_BUFFER. Set *OPTIMIZED if the
214 variable was optimized out (and thus can't be fetched). Set *LVAL
215 to lval_memory, lval_register, or not_lval, depending on whether
216 the value was fetched from memory, from a register, or in a strange
217 and non-modifiable way (e.g. a frame pointer which was calculated
218 rather than fetched). Set *ADDRP to the address, either in memory
219 on as a REGISTER_BYTE offset into the registers array.
221 Note that this implementation never sets *LVAL to not_lval. But it
222 can be replaced by defining GET_SAVED_REGISTER and supplying your
225 The argument RAW_BUFFER must point to aligned memory. */
228 i960_get_saved_register (char *raw_buffer
,
231 struct frame_info
*frame
,
233 enum lval_type
*lval
)
237 if (!target_has_registers
)
238 error ("No registers.");
240 /* Normal systems don't optimize out things with register numbers. */
241 if (optimized
!= NULL
)
243 addr
= i960_find_saved_register (frame
, regnum
);
248 if (regnum
== SP_REGNUM
)
250 if (raw_buffer
!= NULL
)
252 /* Put it back in target format. */
253 store_address (raw_buffer
, REGISTER_RAW_SIZE (regnum
),
260 if (raw_buffer
!= NULL
)
261 target_read_memory (addr
, raw_buffer
, REGISTER_RAW_SIZE (regnum
));
266 *lval
= lval_register
;
267 addr
= REGISTER_BYTE (regnum
);
268 if (raw_buffer
!= NULL
)
269 read_register_gen (regnum
, raw_buffer
);
275 /* Examine an i960 function prologue, recording the addresses at which
276 registers are saved explicitly by the prologue code, and returning
277 the address of the first instruction after the prologue (but not
278 after the instruction at address LIMIT, as explained below).
280 LIMIT places an upper bound on addresses of the instructions to be
281 examined. If the prologue code scan reaches LIMIT, the scan is
282 aborted and LIMIT is returned. This is used, when examining the
283 prologue for the current frame, to keep examine_prologue () from
284 claiming that a given register has been saved when in fact the
285 instruction that saves it has not yet been executed. LIMIT is used
286 at other times to stop the scan when we hit code after the true
287 function prologue (e.g. for the first source line) which might
288 otherwise be mistaken for function prologue.
290 The format of the function prologue matched by this routine is
291 derived from examination of the source to gcc960 1.21, particularly
292 the routine i960_function_prologue (). A "regular expression" for
293 the function prologue is given below:
297 (mov 0, g14) | (lda 0, g14))?
299 (mov[qtl]? g[0-15], r[4-15])*
300 ((addo [1-31], sp, sp) | (lda n(sp), sp))?
301 (st[qtl]? g[0-15], n(fp))*
314 /* Macros for extracting fields from i960 instructions. */
316 #define BITMASK(pos, width) (((0x1 << (width)) - 1) << (pos))
317 #define EXTRACT_FIELD(val, pos, width) ((val) >> (pos) & BITMASK (0, width))
319 #define REG_SRC1(insn) EXTRACT_FIELD (insn, 0, 5)
320 #define REG_SRC2(insn) EXTRACT_FIELD (insn, 14, 5)
321 #define REG_SRCDST(insn) EXTRACT_FIELD (insn, 19, 5)
322 #define MEM_SRCDST(insn) EXTRACT_FIELD (insn, 19, 5)
323 #define MEMA_OFFSET(insn) EXTRACT_FIELD (insn, 0, 12)
325 /* Fetch the instruction at ADDR, returning 0 if ADDR is beyond LIM or
326 is not the address of a valid instruction, the address of the next
327 instruction beyond ADDR otherwise. *PWORD1 receives the first word
328 of the instruction, and (for two-word instructions), *PWORD2 receives
331 #define NEXT_PROLOGUE_INSN(addr, lim, pword1, pword2) \
332 (((addr) < (lim)) ? next_insn (addr, pword1, pword2) : 0)
335 examine_prologue (register CORE_ADDR ip
, register CORE_ADDR limit
,
336 CORE_ADDR frame_addr
, struct frame_saved_regs
*fsr
)
338 register CORE_ADDR next_ip
;
339 register int src
, dst
;
340 register unsigned int *pcode
;
341 unsigned int insn1
, insn2
;
343 int within_leaf_prologue
;
345 static unsigned int varargs_prologue_code
[] =
347 0x3507a00c, /* cmpobne 0x0, g14, LFn */
348 0x5cf01601, /* mov sp, g14 */
349 0x8c086030, /* lda 0x30(sp), sp */
350 0xb2879000, /* LFn: stq g0, (g14) */
351 0xb2a7a010, /* stq g4, 0x10(g14) */
352 0xb2c7a020 /* stq g8, 0x20(g14) */
355 /* Accept a leaf procedure prologue code fragment if present.
356 Note that ip might point to either the leaf or non-leaf
357 entry point; we look for the non-leaf entry point first: */
359 within_leaf_prologue
= 0;
360 if ((next_ip
= NEXT_PROLOGUE_INSN (ip
, limit
, &insn1
, &insn2
))
361 && ((insn1
& 0xfffff000) == 0x8cf00000 /* lda LRx, g14 (MEMA) */
362 || (insn1
& 0xfffffc60) == 0x8cf03000)) /* lda LRx, g14 (MEMB) */
364 within_leaf_prologue
= 1;
365 next_ip
= NEXT_PROLOGUE_INSN (next_ip
, limit
, &insn1
, &insn2
);
368 /* Now look for the prologue code at a leaf entry point: */
371 && (insn1
& 0xff87ffff) == 0x5c80161e /* mov g14, gx */
372 && REG_SRCDST (insn1
) <= G0_REGNUM
+ 7)
374 within_leaf_prologue
= 1;
375 if ((next_ip
= NEXT_PROLOGUE_INSN (next_ip
, limit
, &insn1
, &insn2
))
376 && (insn1
== 0x8cf00000 /* lda 0, g14 */
377 || insn1
== 0x5cf01e00)) /* mov 0, g14 */
380 next_ip
= NEXT_PROLOGUE_INSN (ip
, limit
, &insn1
, &insn2
);
381 within_leaf_prologue
= 0;
385 /* If something that looks like the beginning of a leaf prologue
386 has been seen, but the remainder of the prologue is missing, bail.
387 We don't know what we've got. */
389 if (within_leaf_prologue
)
392 /* Accept zero or more instances of "mov[qtl]? gx, ry", where y >= 4.
393 This may cause us to mistake the moving of a register
394 parameter to a local register for the saving of a callee-saved
395 register, but that can't be helped, since with the
396 "-fcall-saved" flag, any register can be made callee-saved. */
399 && (insn1
& 0xfc802fb0) == 0x5c000610
400 && (dst
= REG_SRCDST (insn1
)) >= (R0_REGNUM
+ 4))
402 src
= REG_SRC1 (insn1
);
403 size
= EXTRACT_FIELD (insn1
, 24, 2) + 1;
404 save_addr
= frame_addr
+ ((dst
- R0_REGNUM
) * 4);
407 fsr
->regs
[src
++] = save_addr
;
411 next_ip
= NEXT_PROLOGUE_INSN (ip
, limit
, &insn1
, &insn2
);
414 /* Accept an optional "addo n, sp, sp" or "lda n(sp), sp". */
417 ((insn1
& 0xffffffe0) == 0x59084800 /* addo n, sp, sp */
418 || (insn1
& 0xfffff000) == 0x8c086000 /* lda n(sp), sp (MEMA) */
419 || (insn1
& 0xfffffc60) == 0x8c087400)) /* lda n(sp), sp (MEMB) */
422 next_ip
= NEXT_PROLOGUE_INSN (ip
, limit
, &insn1
, &insn2
);
425 /* Accept zero or more instances of "st[qtl]? gx, n(fp)".
426 This may cause us to mistake the copying of a register
427 parameter to the frame for the saving of a callee-saved
428 register, but that can't be helped, since with the
429 "-fcall-saved" flag, any register can be made callee-saved.
430 We can, however, refuse to accept a save of register g14,
431 since that is matched explicitly below. */
434 ((insn1
& 0xf787f000) == 0x9287e000 /* stl? gx, n(fp) (MEMA) */
435 || (insn1
& 0xf787fc60) == 0x9287f400 /* stl? gx, n(fp) (MEMB) */
436 || (insn1
& 0xef87f000) == 0xa287e000 /* st[tq] gx, n(fp) (MEMA) */
437 || (insn1
& 0xef87fc60) == 0xa287f400) /* st[tq] gx, n(fp) (MEMB) */
438 && ((src
= MEM_SRCDST (insn1
)) != G14_REGNUM
))
440 save_addr
= frame_addr
+ ((insn1
& BITMASK (12, 1))
441 ? insn2
: MEMA_OFFSET (insn1
));
442 size
= (insn1
& BITMASK (29, 1)) ? ((insn1
& BITMASK (28, 1)) ? 4 : 3)
443 : ((insn1
& BITMASK (27, 1)) ? 2 : 1);
446 fsr
->regs
[src
++] = save_addr
;
450 next_ip
= NEXT_PROLOGUE_INSN (ip
, limit
, &insn1
, &insn2
);
453 /* Accept the varargs prologue code if present. */
455 size
= sizeof (varargs_prologue_code
) / sizeof (int);
456 pcode
= varargs_prologue_code
;
457 while (size
-- && next_ip
&& *pcode
++ == insn1
)
460 next_ip
= NEXT_PROLOGUE_INSN (ip
, limit
, &insn1
, &insn2
);
463 /* Accept an optional "st g14, n(fp)". */
466 ((insn1
& 0xfffff000) == 0x92f7e000 /* st g14, n(fp) (MEMA) */
467 || (insn1
& 0xfffffc60) == 0x92f7f400)) /* st g14, n(fp) (MEMB) */
469 fsr
->regs
[G14_REGNUM
] = frame_addr
+ ((insn1
& BITMASK (12, 1))
470 ? insn2
: MEMA_OFFSET (insn1
));
472 next_ip
= NEXT_PROLOGUE_INSN (ip
, limit
, &insn1
, &insn2
);
475 /* Accept zero or one instance of "mov g13, ry", where y >= 4.
476 This is saving the address where a struct should be returned. */
479 && (insn1
& 0xff802fbf) == 0x5c00061d
480 && (dst
= REG_SRCDST (insn1
)) >= (R0_REGNUM
+ 4))
482 save_addr
= frame_addr
+ ((dst
- R0_REGNUM
) * 4);
483 fsr
->regs
[G0_REGNUM
+ 13] = save_addr
;
485 #if 0 /* We'll need this once there is a subsequent instruction examined. */
486 next_ip
= NEXT_PROLOGUE_INSN (ip
, limit
, &insn1
, &insn2
);
493 /* Given an ip value corresponding to the start of a function,
494 return the ip of the first instruction after the function
498 i960_skip_prologue (CORE_ADDR ip
)
500 struct frame_saved_regs saved_regs_dummy
;
501 struct symtab_and_line sal
;
504 sal
= find_pc_line (ip
, 0);
505 limit
= (sal
.end
) ? sal
.end
: 0xffffffff;
507 return (examine_prologue (ip
, limit
, (CORE_ADDR
) 0, &saved_regs_dummy
));
510 /* Put here the code to store, into a struct frame_saved_regs,
511 the addresses of the saved registers of frame described by FRAME_INFO.
512 This includes special registers such as pc and fp saved in special
513 ways in the stack frame. sp is even more special:
514 the address we return for it IS the sp for the next frame.
516 We cache the result of doing this in the frame_obstack, since it is
520 frame_find_saved_regs (struct frame_info
*fi
, struct frame_saved_regs
*fsr
)
522 register CORE_ADDR next_addr
;
523 register CORE_ADDR
*saved_regs
;
525 register struct frame_saved_regs
*cache_fsr
;
527 struct symtab_and_line sal
;
532 cache_fsr
= (struct frame_saved_regs
*)
533 frame_obstack_alloc (sizeof (struct frame_saved_regs
));
534 memset (cache_fsr
, '\0', sizeof (struct frame_saved_regs
));
537 /* Find the start and end of the function prologue. If the PC
538 is in the function prologue, we only consider the part that
539 has executed already. */
541 ip
= get_pc_function_start (fi
->pc
);
542 sal
= find_pc_line (ip
, 0);
543 limit
= (sal
.end
&& sal
.end
< fi
->pc
) ? sal
.end
: fi
->pc
;
545 examine_prologue (ip
, limit
, fi
->frame
, cache_fsr
);
547 /* Record the addresses at which the local registers are saved.
548 Strictly speaking, we should only do this for non-leaf procedures,
549 but no one will ever look at these values if it is a leaf procedure,
550 since local registers are always caller-saved. */
552 next_addr
= (CORE_ADDR
) fi
->frame
;
553 saved_regs
= cache_fsr
->regs
;
554 for (regnum
= R0_REGNUM
; regnum
<= R15_REGNUM
; regnum
++)
556 *saved_regs
++ = next_addr
;
560 cache_fsr
->regs
[FP_REGNUM
] = cache_fsr
->regs
[PFP_REGNUM
];
565 /* Fetch the value of the sp from memory every time, since it
566 is conceivable that it has changed since the cache was flushed.
567 This unfortunately undoes much of the savings from caching the
568 saved register values. I suggest adding an argument to
569 get_frame_saved_regs () specifying the register number we're
570 interested in (or -1 for all registers). This would be passed
571 through to FRAME_FIND_SAVED_REGS (), permitting more efficient
572 computation of saved register addresses (e.g., on the i960,
573 we don't have to examine the prologue to find local registers).
575 FIXME, we don't need to refetch this, since the cache is cleared
576 every time the child process is restarted. If GDB itself
577 modifies SP, it has to clear the cache by hand (does it?). -gnu */
579 fsr
->regs
[SP_REGNUM
] = read_memory_integer (fsr
->regs
[SP_REGNUM
], 4);
582 /* Return the address of the argument block for the frame
583 described by FI. Returns 0 if the address is unknown. */
586 frame_args_address (struct frame_info
*fi
, int must_be_correct
)
588 struct frame_saved_regs fsr
;
591 /* If g14 was saved in the frame by the function prologue code, return
592 the saved value. If the frame is current and we are being sloppy,
593 return the value of g14. Otherwise, return zero. */
595 get_frame_saved_regs (fi
, &fsr
);
596 if (fsr
.regs
[G14_REGNUM
])
597 ap
= read_memory_integer (fsr
.regs
[G14_REGNUM
], 4);
601 return 0; /* Don't cache this result */
602 if (get_next_frame (fi
))
605 ap
= read_register (G14_REGNUM
);
609 fi
->arg_pointer
= ap
; /* Cache it for next time */
613 /* Return the address of the return struct for the frame
614 described by FI. Returns 0 if the address is unknown. */
617 frame_struct_result_address (struct frame_info
*fi
)
619 struct frame_saved_regs fsr
;
622 /* If the frame is non-current, check to see if g14 was saved in the
623 frame by the function prologue code; return the saved value if so,
624 zero otherwise. If the frame is current, return the value of g14.
626 FIXME, shouldn't this use the saved value as long as we are past
627 the function prologue, and only use the current value if we have
628 no saved value and are at TOS? -- gnu@cygnus.com */
630 if (get_next_frame (fi
))
632 get_frame_saved_regs (fi
, &fsr
);
633 if (fsr
.regs
[G13_REGNUM
])
634 ap
= read_memory_integer (fsr
.regs
[G13_REGNUM
], 4);
639 ap
= read_register (G13_REGNUM
);
644 /* Return address to which the currently executing leafproc will return,
645 or 0 if IP, the value of the instruction pointer from the currently
646 executing function, is not in a leafproc (or if we can't tell if it
649 Do this by finding the starting address of the routine in which IP lies.
650 If the instruction there is "mov g14, gx" (where x is in [0,7]), this
651 is a leafproc and the return address is in register gx. Well, this is
652 true unless the return address points at a RET instruction in the current
653 procedure, which indicates that we have a 'dual entry' routine that
654 has been entered through the CALL entry point. */
657 leafproc_return (CORE_ADDR ip
)
659 register struct minimal_symbol
*msymbol
;
662 unsigned int insn1
, insn2
;
663 CORE_ADDR return_addr
;
665 if ((msymbol
= lookup_minimal_symbol_by_pc (ip
)) != NULL
)
667 if ((p
= strchr (SYMBOL_NAME (msymbol
), '.')) && STREQ (p
, ".lf"))
669 if (next_insn (SYMBOL_VALUE_ADDRESS (msymbol
), &insn1
, &insn2
)
670 && (insn1
& 0xff87ffff) == 0x5c80161e /* mov g14, gx */
671 && (dst
= REG_SRCDST (insn1
)) <= G0_REGNUM
+ 7)
673 /* Get the return address. If the "mov g14, gx"
674 instruction hasn't been executed yet, read
675 the return address from g14; otherwise, read it
676 from the register into which g14 was moved. */
679 read_register ((ip
== SYMBOL_VALUE_ADDRESS (msymbol
))
682 /* We know we are in a leaf procedure, but we don't know
683 whether the caller actually did a "bal" to the ".lf"
684 entry point, or a normal "call" to the non-leaf entry
685 point one instruction before. In the latter case, the
686 return address will be the address of a "ret"
687 instruction within the procedure itself. We test for
690 if (!next_insn (return_addr
, &insn1
, &insn2
)
691 || (insn1
& 0xff000000) != 0xa000000 /* ret */
692 || lookup_minimal_symbol_by_pc (return_addr
) != msymbol
)
693 return (return_addr
);
701 /* Immediately after a function call, return the saved pc.
702 Can't go through the frames for this because on some machines
703 the new frame is not set up until the new function executes
705 On the i960, the frame *is* set up immediately after the call,
706 unless the function is a leaf procedure. */
709 saved_pc_after_call (struct frame_info
*frame
)
713 saved_pc
= leafproc_return (get_frame_pc (frame
));
715 saved_pc
= FRAME_SAVED_PC (frame
);
720 /* Discard from the stack the innermost frame,
721 restoring all saved registers. */
724 i960_pop_frame (void)
726 register struct frame_info
*current_fi
, *prev_fi
;
729 CORE_ADDR leaf_return_addr
;
730 struct frame_saved_regs fsr
;
731 char local_regs_buf
[16 * 4];
733 current_fi
= get_current_frame ();
735 /* First, undo what the hardware does when we return.
736 If this is a non-leaf procedure, restore local registers from
737 the save area in the calling frame. Otherwise, load the return
738 address obtained from leafproc_return () into the rip. */
740 leaf_return_addr
= leafproc_return (current_fi
->pc
);
741 if (!leaf_return_addr
)
743 /* Non-leaf procedure. Restore local registers, incl IP. */
744 prev_fi
= get_prev_frame (current_fi
);
745 read_memory (prev_fi
->frame
, local_regs_buf
, sizeof (local_regs_buf
));
746 write_register_bytes (REGISTER_BYTE (R0_REGNUM
), local_regs_buf
,
747 sizeof (local_regs_buf
));
749 /* Restore frame pointer. */
750 write_register (FP_REGNUM
, prev_fi
->frame
);
754 /* Leaf procedure. Just restore the return address into the IP. */
755 write_register (RIP_REGNUM
, leaf_return_addr
);
758 /* Now restore any global regs that the current function had saved. */
759 get_frame_saved_regs (current_fi
, &fsr
);
760 for (i
= G0_REGNUM
; i
< G14_REGNUM
; i
++)
762 save_addr
= fsr
.regs
[i
];
764 write_register (i
, read_memory_integer (save_addr
, 4));
767 /* Flush the frame cache, create a frame for the new innermost frame,
768 and make it the current frame. */
770 flush_cached_frames ();
773 /* Given a 960 stop code (fault or trace), return the signal which
777 i960_fault_to_signal (int fault
)
782 return TARGET_SIGNAL_BUS
; /* parallel fault */
784 return TARGET_SIGNAL_UNKNOWN
;
786 return TARGET_SIGNAL_ILL
; /* operation fault */
788 return TARGET_SIGNAL_FPE
; /* arithmetic fault */
790 return TARGET_SIGNAL_FPE
; /* floating point fault */
792 /* constraint fault. This appears not to distinguish between
793 a range constraint fault (which should be SIGFPE) and a privileged
794 fault (which should be SIGILL). */
796 return TARGET_SIGNAL_ILL
;
799 return TARGET_SIGNAL_SEGV
; /* virtual memory fault */
801 /* protection fault. This is for an out-of-range argument to
802 "calls". I guess it also could be SIGILL. */
804 return TARGET_SIGNAL_SEGV
;
807 return TARGET_SIGNAL_BUS
; /* machine fault */
809 return TARGET_SIGNAL_BUS
; /* structural fault */
811 return TARGET_SIGNAL_ILL
; /* type fault */
813 return TARGET_SIGNAL_UNKNOWN
; /* reserved fault */
815 return TARGET_SIGNAL_BUS
; /* process fault */
817 return TARGET_SIGNAL_SEGV
; /* descriptor fault */
819 return TARGET_SIGNAL_BUS
; /* event fault */
821 return TARGET_SIGNAL_UNKNOWN
; /* reserved fault */
823 return TARGET_SIGNAL_TRAP
; /* single-step trace */
825 return TARGET_SIGNAL_TRAP
; /* branch trace */
827 return TARGET_SIGNAL_TRAP
; /* call trace */
829 return TARGET_SIGNAL_TRAP
; /* return trace */
831 return TARGET_SIGNAL_TRAP
; /* pre-return trace */
833 return TARGET_SIGNAL_TRAP
; /* supervisor call trace */
835 return TARGET_SIGNAL_TRAP
; /* breakpoint trace */
837 return TARGET_SIGNAL_UNKNOWN
;
841 /****************************************/
843 /****************************************/
851 /* Return instruction length, either 4 or 8. When NOPRINT is non-zero
852 (TRUE), don't output any text. (Actually, as implemented, if NOPRINT
853 is 0, abort() is called.) */
856 mem (unsigned long memaddr
, unsigned long word1
, unsigned long word2
,
863 const char *reg1
, *reg2
, *reg3
;
865 /* This lookup table is too sparse to make it worth typing in, but not
866 * so large as to make a sparse array necessary. We allocate the
867 * table at runtime, initialize all entries to empty, and copy the
868 * real ones in from an initialization table.
870 * NOTE: In this table, the meaning of 'numops' is:
872 * 2: 2 operands, load instruction
873 * -2: 2 operands, store instruction
875 static struct tabent
*mem_tab
= NULL
;
876 /* Opcodes of 0x8X, 9X, aX, bX, and cX must be in the table. */
879 #define MEM_SIZ ((MEM_MAX-MEM_MIN+1) * sizeof(struct tabent))
914 mem_tab
= (struct tabent
*) xmalloc (MEM_SIZ
);
915 memset (mem_tab
, '\0', MEM_SIZ
);
916 for (i
= 0; mem_init
[i
].opcode
!= 0; i
++)
918 j
= mem_init
[i
].opcode
- MEM_MIN
;
919 mem_tab
[j
].name
= mem_init
[i
].name
;
920 mem_tab
[j
].numops
= mem_init
[i
].numops
;
924 i
= ((word1
>> 24) & 0xff) - MEM_MIN
;
925 mode
= (word1
>> 10) & 0xf;
927 if ((mem_tab
[i
].name
!= NULL
) /* Valid instruction */
928 && ((mode
== 5) || (mode
>= 12)))
929 { /* With 32-bit displacement */
941 internal_error (__FILE__
, __LINE__
, "failed internal consistency check");
944 /* Read the i960 instruction at 'memaddr' and return the address of
945 the next instruction after that, or 0 if 'memaddr' is not the
946 address of a valid instruction. The first word of the instruction
947 is stored at 'pword1', and the second word, if any, is stored at
951 next_insn (CORE_ADDR memaddr
, unsigned int *pword1
, unsigned int *pword2
)
956 /* Read the two (potential) words of the instruction at once,
957 to eliminate the overhead of two calls to read_memory ().
958 FIXME: Loses if the first one is readable but the second is not
959 (e.g. last word of the segment). */
961 read_memory (memaddr
, buf
, 8);
962 *pword1
= extract_unsigned_integer (buf
, 4);
963 *pword2
= extract_unsigned_integer (buf
+ 4, 4);
965 /* Divide instruction set into classes based on high 4 bits of opcode */
967 switch ((*pword1
>> 28) & 0xf)
986 len
= mem (memaddr
, *pword1
, *pword2
, 1);
989 default: /* invalid instruction */
995 return memaddr
+ len
;
1000 /* 'start_frame' is a variable in the MON960 runtime startup routine
1001 that contains the frame pointer of the 'start' routine (the routine
1002 that calls 'main'). By reading its contents out of remote memory,
1003 we can tell where the frame chain ends: backtraces should halt before
1004 they display this frame. */
1007 mon960_frame_chain_valid (CORE_ADDR chain
, struct frame_info
*curframe
)
1010 struct minimal_symbol
*msymbol
;
1012 /* crtmon960.o is an assembler module that is assumed to be linked
1013 * first in an i80960 executable. It contains the true entry point;
1014 * it performs startup up initialization and then calls 'main'.
1016 * 'sf' is the name of a variable in crtmon960.o that is set
1017 * during startup to the address of the first frame.
1019 * 'a' is the address of that variable in 80960 memory.
1021 static char sf
[] = "start_frame";
1025 chain
&= ~0x3f; /* Zero low 6 bits because previous frame pointers
1026 contain return status info in them. */
1032 sym
= lookup_symbol (sf
, 0, VAR_NAMESPACE
, (int *) NULL
,
1033 (struct symtab
**) NULL
);
1036 a
= SYMBOL_VALUE (sym
);
1040 msymbol
= lookup_minimal_symbol (sf
, NULL
, NULL
);
1041 if (msymbol
== NULL
)
1043 a
= SYMBOL_VALUE_ADDRESS (msymbol
);
1046 return (chain
!= read_memory_integer (a
, 4));
1051 _initialize_i960_tdep (void)
1055 tm_print_insn
= print_insn_i960
;