1 /* Target-machine dependent code for the Intel 960
3 Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000,
4 2001, 2002 Free Software Foundation, Inc.
6 Contributed by Intel Corporation.
7 examine_prologue and other parts contributed by Wind River Systems.
9 This file is part of GDB.
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software
23 Foundation, Inc., 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
30 #include "floatformat.h"
36 static CORE_ADDR
next_insn (CORE_ADDR memaddr
,
37 unsigned int *pword1
, unsigned int *pword2
);
40 i960_register_type (int regnum
)
42 if (regnum
< FP0_REGNUM
)
43 return builtin_type_int32
;
45 return builtin_type_i960_ext
;
49 /* Does the specified function use the "struct returning" convention
50 or the "value returning" convention? The "value returning" convention
51 almost invariably returns the entire value in registers. The
52 "struct returning" convention often returns the entire value in
53 memory, and passes a pointer (out of or into the function) saying
54 where the value (is or should go).
56 Since this sometimes depends on whether it was compiled with GCC,
57 this is also an argument. This is used in call_function to build a
58 stack, and in value_being_returned to print return values.
60 On i960, a structure is returned in registers g0-g3, if it will fit.
61 If it's more than 16 bytes long, g13 pointed to it on entry. */
64 i960_use_struct_convention (int gcc_p
, struct type
*type
)
66 return (TYPE_LENGTH (type
) > 16);
69 /* gdb960 is always running on a non-960 host. Check its characteristics.
70 This routine must be called as part of gdb initialization. */
77 static struct typestruct
79 int hostsize
; /* Size of type on host */
80 int i960size
; /* Size of type on i960 */
81 char *typename
; /* Name of type, for error msg */
86 sizeof (short), 2, "short"
90 sizeof (int), 4, "int"
94 sizeof (long), 4, "long"
98 sizeof (float), 4, "float"
102 sizeof (double), 8, "double"
106 sizeof (char *), 4, "pointer"
110 #define TYPELEN (sizeof(types) / sizeof(struct typestruct))
112 /* Make sure that host type sizes are same as i960
114 for (i
= 0; i
< TYPELEN
; i
++)
116 if (types
[i
].hostsize
!= types
[i
].i960size
)
118 printf_unfiltered ("sizeof(%s) != %d: PROCEED AT YOUR OWN RISK!\n",
119 types
[i
].typename
, types
[i
].i960size
);
125 /* Is this register part of the register window system? A yes answer
126 implies that 1) The name of this register will not be the same in
127 other frames, and 2) This register is automatically "saved" upon
128 subroutine calls and thus there is no need to search more than one
131 On the i960, in fact, the name of this register in another frame is
132 "mud" -- there is no overlap between the windows. Each window is
133 simply saved into the stack (true for our purposes, after having been
134 flushed; normally they reside on-chip and are restored from on-chip
135 without ever going to memory). */
138 register_in_window_p (int regnum
)
140 return regnum
<= R15_REGNUM
;
143 /* i960_find_saved_register ()
145 Return the address in which frame FRAME's value of register REGNUM
146 has been saved in memory. Or return zero if it has not been saved.
147 If REGNUM specifies the SP, the value we return is actually the SP
148 value, not an address where it was saved. */
151 i960_find_saved_register (struct frame_info
*frame
, int regnum
)
153 register struct frame_info
*frame1
= NULL
;
154 register CORE_ADDR addr
= 0;
156 if (frame
== NULL
) /* No regs saved if want current frame */
159 /* We assume that a register in a register window will only be saved
160 in one place (since the name changes and/or disappears as you go
161 towards inner frames), so we only call get_frame_saved_regs on
162 the current frame. This is directly in contradiction to the
163 usage below, which assumes that registers used in a frame must be
164 saved in a lower (more interior) frame. This change is a result
165 of working on a register window machine; get_frame_saved_regs
166 always returns the registers saved within a frame, within the
167 context (register namespace) of that frame. */
169 /* However, note that we don't want this to return anything if
170 nothing is saved (if there's a frame inside of this one). Also,
171 callers to this routine asking for the stack pointer want the
172 stack pointer saved for *this* frame; this is returned from the
175 if (register_in_window_p (regnum
))
177 frame1
= get_next_frame (frame
);
179 return 0; /* Registers of this frame are active. */
181 /* Get the SP from the next frame in; it will be this
183 if (regnum
!= SP_REGNUM
)
186 FRAME_INIT_SAVED_REGS (frame1
);
187 return frame1
->saved_regs
[regnum
]; /* ... which might be zero */
190 /* Note that this next routine assumes that registers used in
191 frame x will be saved only in the frame that x calls and
192 frames interior to it. This is not true on the sparc, but the
193 above macro takes care of it, so we should be all right. */
197 frame1
= get_next_frame (frame
);
201 FRAME_INIT_SAVED_REGS (frame1
);
202 if (frame1
->saved_regs
[regnum
])
203 addr
= frame1
->saved_regs
[regnum
];
209 /* i960_get_saved_register ()
211 Find register number REGNUM relative to FRAME and put its (raw,
212 target format) contents in *RAW_BUFFER. Set *OPTIMIZED if the
213 variable was optimized out (and thus can't be fetched). Set *LVAL
214 to lval_memory, lval_register, or not_lval, depending on whether
215 the value was fetched from memory, from a register, or in a strange
216 and non-modifiable way (e.g. a frame pointer which was calculated
217 rather than fetched). Set *ADDRP to the address, either in memory
218 on as a REGISTER_BYTE offset into the registers array.
220 Note that this implementation never sets *LVAL to not_lval. But it
221 can be replaced by defining GET_SAVED_REGISTER and supplying your
224 The argument RAW_BUFFER must point to aligned memory. */
227 i960_get_saved_register (char *raw_buffer
,
230 struct frame_info
*frame
,
232 enum lval_type
*lval
)
236 if (!target_has_registers
)
237 error ("No registers.");
239 /* Normal systems don't optimize out things with register numbers. */
240 if (optimized
!= NULL
)
242 addr
= i960_find_saved_register (frame
, regnum
);
247 if (regnum
== SP_REGNUM
)
249 if (raw_buffer
!= NULL
)
251 /* Put it back in target format. */
252 store_address (raw_buffer
, REGISTER_RAW_SIZE (regnum
),
259 if (raw_buffer
!= NULL
)
260 target_read_memory (addr
, raw_buffer
, REGISTER_RAW_SIZE (regnum
));
265 *lval
= lval_register
;
266 addr
= REGISTER_BYTE (regnum
);
267 if (raw_buffer
!= NULL
)
268 read_register_gen (regnum
, raw_buffer
);
274 /* Examine an i960 function prologue, recording the addresses at which
275 registers are saved explicitly by the prologue code, and returning
276 the address of the first instruction after the prologue (but not
277 after the instruction at address LIMIT, as explained below).
279 LIMIT places an upper bound on addresses of the instructions to be
280 examined. If the prologue code scan reaches LIMIT, the scan is
281 aborted and LIMIT is returned. This is used, when examining the
282 prologue for the current frame, to keep examine_prologue () from
283 claiming that a given register has been saved when in fact the
284 instruction that saves it has not yet been executed. LIMIT is used
285 at other times to stop the scan when we hit code after the true
286 function prologue (e.g. for the first source line) which might
287 otherwise be mistaken for function prologue.
289 The format of the function prologue matched by this routine is
290 derived from examination of the source to gcc960 1.21, particularly
291 the routine i960_function_prologue (). A "regular expression" for
292 the function prologue is given below:
296 (mov 0, g14) | (lda 0, g14))?
298 (mov[qtl]? g[0-15], r[4-15])*
299 ((addo [1-31], sp, sp) | (lda n(sp), sp))?
300 (st[qtl]? g[0-15], n(fp))*
313 /* Macros for extracting fields from i960 instructions. */
315 #define BITMASK(pos, width) (((0x1 << (width)) - 1) << (pos))
316 #define EXTRACT_FIELD(val, pos, width) ((val) >> (pos) & BITMASK (0, width))
318 #define REG_SRC1(insn) EXTRACT_FIELD (insn, 0, 5)
319 #define REG_SRC2(insn) EXTRACT_FIELD (insn, 14, 5)
320 #define REG_SRCDST(insn) EXTRACT_FIELD (insn, 19, 5)
321 #define MEM_SRCDST(insn) EXTRACT_FIELD (insn, 19, 5)
322 #define MEMA_OFFSET(insn) EXTRACT_FIELD (insn, 0, 12)
324 /* Fetch the instruction at ADDR, returning 0 if ADDR is beyond LIM or
325 is not the address of a valid instruction, the address of the next
326 instruction beyond ADDR otherwise. *PWORD1 receives the first word
327 of the instruction, and (for two-word instructions), *PWORD2 receives
330 #define NEXT_PROLOGUE_INSN(addr, lim, pword1, pword2) \
331 (((addr) < (lim)) ? next_insn (addr, pword1, pword2) : 0)
334 examine_prologue (register CORE_ADDR ip
, register CORE_ADDR limit
,
335 CORE_ADDR frame_addr
, struct frame_saved_regs
*fsr
)
337 register CORE_ADDR next_ip
;
338 register int src
, dst
;
339 register unsigned int *pcode
;
340 unsigned int insn1
, insn2
;
342 int within_leaf_prologue
;
344 static unsigned int varargs_prologue_code
[] =
346 0x3507a00c, /* cmpobne 0x0, g14, LFn */
347 0x5cf01601, /* mov sp, g14 */
348 0x8c086030, /* lda 0x30(sp), sp */
349 0xb2879000, /* LFn: stq g0, (g14) */
350 0xb2a7a010, /* stq g4, 0x10(g14) */
351 0xb2c7a020 /* stq g8, 0x20(g14) */
354 /* Accept a leaf procedure prologue code fragment if present.
355 Note that ip might point to either the leaf or non-leaf
356 entry point; we look for the non-leaf entry point first: */
358 within_leaf_prologue
= 0;
359 if ((next_ip
= NEXT_PROLOGUE_INSN (ip
, limit
, &insn1
, &insn2
))
360 && ((insn1
& 0xfffff000) == 0x8cf00000 /* lda LRx, g14 (MEMA) */
361 || (insn1
& 0xfffffc60) == 0x8cf03000)) /* lda LRx, g14 (MEMB) */
363 within_leaf_prologue
= 1;
364 next_ip
= NEXT_PROLOGUE_INSN (next_ip
, limit
, &insn1
, &insn2
);
367 /* Now look for the prologue code at a leaf entry point: */
370 && (insn1
& 0xff87ffff) == 0x5c80161e /* mov g14, gx */
371 && REG_SRCDST (insn1
) <= G0_REGNUM
+ 7)
373 within_leaf_prologue
= 1;
374 if ((next_ip
= NEXT_PROLOGUE_INSN (next_ip
, limit
, &insn1
, &insn2
))
375 && (insn1
== 0x8cf00000 /* lda 0, g14 */
376 || insn1
== 0x5cf01e00)) /* mov 0, g14 */
379 next_ip
= NEXT_PROLOGUE_INSN (ip
, limit
, &insn1
, &insn2
);
380 within_leaf_prologue
= 0;
384 /* If something that looks like the beginning of a leaf prologue
385 has been seen, but the remainder of the prologue is missing, bail.
386 We don't know what we've got. */
388 if (within_leaf_prologue
)
391 /* Accept zero or more instances of "mov[qtl]? gx, ry", where y >= 4.
392 This may cause us to mistake the moving of a register
393 parameter to a local register for the saving of a callee-saved
394 register, but that can't be helped, since with the
395 "-fcall-saved" flag, any register can be made callee-saved. */
398 && (insn1
& 0xfc802fb0) == 0x5c000610
399 && (dst
= REG_SRCDST (insn1
)) >= (R0_REGNUM
+ 4))
401 src
= REG_SRC1 (insn1
);
402 size
= EXTRACT_FIELD (insn1
, 24, 2) + 1;
403 save_addr
= frame_addr
+ ((dst
- R0_REGNUM
) * 4);
406 fsr
->regs
[src
++] = save_addr
;
410 next_ip
= NEXT_PROLOGUE_INSN (ip
, limit
, &insn1
, &insn2
);
413 /* Accept an optional "addo n, sp, sp" or "lda n(sp), sp". */
416 ((insn1
& 0xffffffe0) == 0x59084800 /* addo n, sp, sp */
417 || (insn1
& 0xfffff000) == 0x8c086000 /* lda n(sp), sp (MEMA) */
418 || (insn1
& 0xfffffc60) == 0x8c087400)) /* lda n(sp), sp (MEMB) */
421 next_ip
= NEXT_PROLOGUE_INSN (ip
, limit
, &insn1
, &insn2
);
424 /* Accept zero or more instances of "st[qtl]? gx, n(fp)".
425 This may cause us to mistake the copying of a register
426 parameter to the frame for the saving of a callee-saved
427 register, but that can't be helped, since with the
428 "-fcall-saved" flag, any register can be made callee-saved.
429 We can, however, refuse to accept a save of register g14,
430 since that is matched explicitly below. */
433 ((insn1
& 0xf787f000) == 0x9287e000 /* stl? gx, n(fp) (MEMA) */
434 || (insn1
& 0xf787fc60) == 0x9287f400 /* stl? gx, n(fp) (MEMB) */
435 || (insn1
& 0xef87f000) == 0xa287e000 /* st[tq] gx, n(fp) (MEMA) */
436 || (insn1
& 0xef87fc60) == 0xa287f400) /* st[tq] gx, n(fp) (MEMB) */
437 && ((src
= MEM_SRCDST (insn1
)) != G14_REGNUM
))
439 save_addr
= frame_addr
+ ((insn1
& BITMASK (12, 1))
440 ? insn2
: MEMA_OFFSET (insn1
));
441 size
= (insn1
& BITMASK (29, 1)) ? ((insn1
& BITMASK (28, 1)) ? 4 : 3)
442 : ((insn1
& BITMASK (27, 1)) ? 2 : 1);
445 fsr
->regs
[src
++] = save_addr
;
449 next_ip
= NEXT_PROLOGUE_INSN (ip
, limit
, &insn1
, &insn2
);
452 /* Accept the varargs prologue code if present. */
454 size
= sizeof (varargs_prologue_code
) / sizeof (int);
455 pcode
= varargs_prologue_code
;
456 while (size
-- && next_ip
&& *pcode
++ == insn1
)
459 next_ip
= NEXT_PROLOGUE_INSN (ip
, limit
, &insn1
, &insn2
);
462 /* Accept an optional "st g14, n(fp)". */
465 ((insn1
& 0xfffff000) == 0x92f7e000 /* st g14, n(fp) (MEMA) */
466 || (insn1
& 0xfffffc60) == 0x92f7f400)) /* st g14, n(fp) (MEMB) */
468 fsr
->regs
[G14_REGNUM
] = frame_addr
+ ((insn1
& BITMASK (12, 1))
469 ? insn2
: MEMA_OFFSET (insn1
));
471 next_ip
= NEXT_PROLOGUE_INSN (ip
, limit
, &insn1
, &insn2
);
474 /* Accept zero or one instance of "mov g13, ry", where y >= 4.
475 This is saving the address where a struct should be returned. */
478 && (insn1
& 0xff802fbf) == 0x5c00061d
479 && (dst
= REG_SRCDST (insn1
)) >= (R0_REGNUM
+ 4))
481 save_addr
= frame_addr
+ ((dst
- R0_REGNUM
) * 4);
482 fsr
->regs
[G0_REGNUM
+ 13] = save_addr
;
484 #if 0 /* We'll need this once there is a subsequent instruction examined. */
485 next_ip
= NEXT_PROLOGUE_INSN (ip
, limit
, &insn1
, &insn2
);
492 /* Given an ip value corresponding to the start of a function,
493 return the ip of the first instruction after the function
497 i960_skip_prologue (CORE_ADDR ip
)
499 struct frame_saved_regs saved_regs_dummy
;
500 struct symtab_and_line sal
;
503 sal
= find_pc_line (ip
, 0);
504 limit
= (sal
.end
) ? sal
.end
: 0xffffffff;
506 return (examine_prologue (ip
, limit
, (CORE_ADDR
) 0, &saved_regs_dummy
));
509 /* Put here the code to store, into a struct frame_saved_regs,
510 the addresses of the saved registers of frame described by FRAME_INFO.
511 This includes special registers such as pc and fp saved in special
512 ways in the stack frame. sp is even more special:
513 the address we return for it IS the sp for the next frame.
515 We cache the result of doing this in the frame_obstack, since it is
519 frame_find_saved_regs (struct frame_info
*fi
, struct frame_saved_regs
*fsr
)
521 register CORE_ADDR next_addr
;
522 register CORE_ADDR
*saved_regs
;
524 register struct frame_saved_regs
*cache_fsr
;
526 struct symtab_and_line sal
;
531 cache_fsr
= (struct frame_saved_regs
*)
532 frame_obstack_alloc (sizeof (struct frame_saved_regs
));
533 memset (cache_fsr
, '\0', sizeof (struct frame_saved_regs
));
536 /* Find the start and end of the function prologue. If the PC
537 is in the function prologue, we only consider the part that
538 has executed already. */
540 ip
= get_pc_function_start (fi
->pc
);
541 sal
= find_pc_line (ip
, 0);
542 limit
= (sal
.end
&& sal
.end
< fi
->pc
) ? sal
.end
: fi
->pc
;
544 examine_prologue (ip
, limit
, fi
->frame
, cache_fsr
);
546 /* Record the addresses at which the local registers are saved.
547 Strictly speaking, we should only do this for non-leaf procedures,
548 but no one will ever look at these values if it is a leaf procedure,
549 since local registers are always caller-saved. */
551 next_addr
= (CORE_ADDR
) fi
->frame
;
552 saved_regs
= cache_fsr
->regs
;
553 for (regnum
= R0_REGNUM
; regnum
<= R15_REGNUM
; regnum
++)
555 *saved_regs
++ = next_addr
;
559 cache_fsr
->regs
[FP_REGNUM
] = cache_fsr
->regs
[PFP_REGNUM
];
564 /* Fetch the value of the sp from memory every time, since it
565 is conceivable that it has changed since the cache was flushed.
566 This unfortunately undoes much of the savings from caching the
567 saved register values. I suggest adding an argument to
568 get_frame_saved_regs () specifying the register number we're
569 interested in (or -1 for all registers). This would be passed
570 through to FRAME_FIND_SAVED_REGS (), permitting more efficient
571 computation of saved register addresses (e.g., on the i960,
572 we don't have to examine the prologue to find local registers).
574 FIXME, we don't need to refetch this, since the cache is cleared
575 every time the child process is restarted. If GDB itself
576 modifies SP, it has to clear the cache by hand (does it?). -gnu */
578 fsr
->regs
[SP_REGNUM
] = read_memory_integer (fsr
->regs
[SP_REGNUM
], 4);
581 /* Return the address of the argument block for the frame
582 described by FI. Returns 0 if the address is unknown. */
585 frame_args_address (struct frame_info
*fi
, int must_be_correct
)
587 struct frame_saved_regs fsr
;
590 /* If g14 was saved in the frame by the function prologue code, return
591 the saved value. If the frame is current and we are being sloppy,
592 return the value of g14. Otherwise, return zero. */
594 get_frame_saved_regs (fi
, &fsr
);
595 if (fsr
.regs
[G14_REGNUM
])
596 ap
= read_memory_integer (fsr
.regs
[G14_REGNUM
], 4);
600 return 0; /* Don't cache this result */
601 if (get_next_frame (fi
))
604 ap
= read_register (G14_REGNUM
);
608 fi
->arg_pointer
= ap
; /* Cache it for next time */
612 /* Return the address of the return struct for the frame
613 described by FI. Returns 0 if the address is unknown. */
616 frame_struct_result_address (struct frame_info
*fi
)
618 struct frame_saved_regs fsr
;
621 /* If the frame is non-current, check to see if g14 was saved in the
622 frame by the function prologue code; return the saved value if so,
623 zero otherwise. If the frame is current, return the value of g14.
625 FIXME, shouldn't this use the saved value as long as we are past
626 the function prologue, and only use the current value if we have
627 no saved value and are at TOS? -- gnu@cygnus.com */
629 if (get_next_frame (fi
))
631 get_frame_saved_regs (fi
, &fsr
);
632 if (fsr
.regs
[G13_REGNUM
])
633 ap
= read_memory_integer (fsr
.regs
[G13_REGNUM
], 4);
638 ap
= read_register (G13_REGNUM
);
643 /* Return address to which the currently executing leafproc will return,
644 or 0 if IP, the value of the instruction pointer from the currently
645 executing function, is not in a leafproc (or if we can't tell if it
648 Do this by finding the starting address of the routine in which IP lies.
649 If the instruction there is "mov g14, gx" (where x is in [0,7]), this
650 is a leafproc and the return address is in register gx. Well, this is
651 true unless the return address points at a RET instruction in the current
652 procedure, which indicates that we have a 'dual entry' routine that
653 has been entered through the CALL entry point. */
656 leafproc_return (CORE_ADDR ip
)
658 register struct minimal_symbol
*msymbol
;
661 unsigned int insn1
, insn2
;
662 CORE_ADDR return_addr
;
664 if ((msymbol
= lookup_minimal_symbol_by_pc (ip
)) != NULL
)
666 if ((p
= strchr (SYMBOL_NAME (msymbol
), '.')) && STREQ (p
, ".lf"))
668 if (next_insn (SYMBOL_VALUE_ADDRESS (msymbol
), &insn1
, &insn2
)
669 && (insn1
& 0xff87ffff) == 0x5c80161e /* mov g14, gx */
670 && (dst
= REG_SRCDST (insn1
)) <= G0_REGNUM
+ 7)
672 /* Get the return address. If the "mov g14, gx"
673 instruction hasn't been executed yet, read
674 the return address from g14; otherwise, read it
675 from the register into which g14 was moved. */
678 read_register ((ip
== SYMBOL_VALUE_ADDRESS (msymbol
))
681 /* We know we are in a leaf procedure, but we don't know
682 whether the caller actually did a "bal" to the ".lf"
683 entry point, or a normal "call" to the non-leaf entry
684 point one instruction before. In the latter case, the
685 return address will be the address of a "ret"
686 instruction within the procedure itself. We test for
689 if (!next_insn (return_addr
, &insn1
, &insn2
)
690 || (insn1
& 0xff000000) != 0xa000000 /* ret */
691 || lookup_minimal_symbol_by_pc (return_addr
) != msymbol
)
692 return (return_addr
);
700 /* Immediately after a function call, return the saved pc.
701 Can't go through the frames for this because on some machines
702 the new frame is not set up until the new function executes
704 On the i960, the frame *is* set up immediately after the call,
705 unless the function is a leaf procedure. */
708 saved_pc_after_call (struct frame_info
*frame
)
712 saved_pc
= leafproc_return (get_frame_pc (frame
));
714 saved_pc
= FRAME_SAVED_PC (frame
);
719 /* Discard from the stack the innermost frame,
720 restoring all saved registers. */
723 i960_pop_frame (void)
725 register struct frame_info
*current_fi
, *prev_fi
;
728 CORE_ADDR leaf_return_addr
;
729 struct frame_saved_regs fsr
;
730 char local_regs_buf
[16 * 4];
732 current_fi
= get_current_frame ();
734 /* First, undo what the hardware does when we return.
735 If this is a non-leaf procedure, restore local registers from
736 the save area in the calling frame. Otherwise, load the return
737 address obtained from leafproc_return () into the rip. */
739 leaf_return_addr
= leafproc_return (current_fi
->pc
);
740 if (!leaf_return_addr
)
742 /* Non-leaf procedure. Restore local registers, incl IP. */
743 prev_fi
= get_prev_frame (current_fi
);
744 read_memory (prev_fi
->frame
, local_regs_buf
, sizeof (local_regs_buf
));
745 write_register_bytes (REGISTER_BYTE (R0_REGNUM
), local_regs_buf
,
746 sizeof (local_regs_buf
));
748 /* Restore frame pointer. */
749 write_register (FP_REGNUM
, prev_fi
->frame
);
753 /* Leaf procedure. Just restore the return address into the IP. */
754 write_register (RIP_REGNUM
, leaf_return_addr
);
757 /* Now restore any global regs that the current function had saved. */
758 get_frame_saved_regs (current_fi
, &fsr
);
759 for (i
= G0_REGNUM
; i
< G14_REGNUM
; i
++)
761 save_addr
= fsr
.regs
[i
];
763 write_register (i
, read_memory_integer (save_addr
, 4));
766 /* Flush the frame cache, create a frame for the new innermost frame,
767 and make it the current frame. */
769 flush_cached_frames ();
772 /* Given a 960 stop code (fault or trace), return the signal which
776 i960_fault_to_signal (int fault
)
781 return TARGET_SIGNAL_BUS
; /* parallel fault */
783 return TARGET_SIGNAL_UNKNOWN
;
785 return TARGET_SIGNAL_ILL
; /* operation fault */
787 return TARGET_SIGNAL_FPE
; /* arithmetic fault */
789 return TARGET_SIGNAL_FPE
; /* floating point fault */
791 /* constraint fault. This appears not to distinguish between
792 a range constraint fault (which should be SIGFPE) and a privileged
793 fault (which should be SIGILL). */
795 return TARGET_SIGNAL_ILL
;
798 return TARGET_SIGNAL_SEGV
; /* virtual memory fault */
800 /* protection fault. This is for an out-of-range argument to
801 "calls". I guess it also could be SIGILL. */
803 return TARGET_SIGNAL_SEGV
;
806 return TARGET_SIGNAL_BUS
; /* machine fault */
808 return TARGET_SIGNAL_BUS
; /* structural fault */
810 return TARGET_SIGNAL_ILL
; /* type fault */
812 return TARGET_SIGNAL_UNKNOWN
; /* reserved fault */
814 return TARGET_SIGNAL_BUS
; /* process fault */
816 return TARGET_SIGNAL_SEGV
; /* descriptor fault */
818 return TARGET_SIGNAL_BUS
; /* event fault */
820 return TARGET_SIGNAL_UNKNOWN
; /* reserved fault */
822 return TARGET_SIGNAL_TRAP
; /* single-step trace */
824 return TARGET_SIGNAL_TRAP
; /* branch trace */
826 return TARGET_SIGNAL_TRAP
; /* call trace */
828 return TARGET_SIGNAL_TRAP
; /* return trace */
830 return TARGET_SIGNAL_TRAP
; /* pre-return trace */
832 return TARGET_SIGNAL_TRAP
; /* supervisor call trace */
834 return TARGET_SIGNAL_TRAP
; /* breakpoint trace */
836 return TARGET_SIGNAL_UNKNOWN
;
840 /****************************************/
842 /****************************************/
850 /* Return instruction length, either 4 or 8. When NOPRINT is non-zero
851 (TRUE), don't output any text. (Actually, as implemented, if NOPRINT
852 is 0, abort() is called.) */
855 mem (unsigned long memaddr
, unsigned long word1
, unsigned long word2
,
862 const char *reg1
, *reg2
, *reg3
;
864 /* This lookup table is too sparse to make it worth typing in, but not
865 * so large as to make a sparse array necessary. We allocate the
866 * table at runtime, initialize all entries to empty, and copy the
867 * real ones in from an initialization table.
869 * NOTE: In this table, the meaning of 'numops' is:
871 * 2: 2 operands, load instruction
872 * -2: 2 operands, store instruction
874 static struct tabent
*mem_tab
= NULL
;
875 /* Opcodes of 0x8X, 9X, aX, bX, and cX must be in the table. */
878 #define MEM_SIZ ((MEM_MAX-MEM_MIN+1) * sizeof(struct tabent))
913 mem_tab
= (struct tabent
*) xmalloc (MEM_SIZ
);
914 memset (mem_tab
, '\0', MEM_SIZ
);
915 for (i
= 0; mem_init
[i
].opcode
!= 0; i
++)
917 j
= mem_init
[i
].opcode
- MEM_MIN
;
918 mem_tab
[j
].name
= mem_init
[i
].name
;
919 mem_tab
[j
].numops
= mem_init
[i
].numops
;
923 i
= ((word1
>> 24) & 0xff) - MEM_MIN
;
924 mode
= (word1
>> 10) & 0xf;
926 if ((mem_tab
[i
].name
!= NULL
) /* Valid instruction */
927 && ((mode
== 5) || (mode
>= 12)))
928 { /* With 32-bit displacement */
940 internal_error (__FILE__
, __LINE__
, "failed internal consistency check");
943 /* Read the i960 instruction at 'memaddr' and return the address of
944 the next instruction after that, or 0 if 'memaddr' is not the
945 address of a valid instruction. The first word of the instruction
946 is stored at 'pword1', and the second word, if any, is stored at
950 next_insn (CORE_ADDR memaddr
, unsigned int *pword1
, unsigned int *pword2
)
955 /* Read the two (potential) words of the instruction at once,
956 to eliminate the overhead of two calls to read_memory ().
957 FIXME: Loses if the first one is readable but the second is not
958 (e.g. last word of the segment). */
960 read_memory (memaddr
, buf
, 8);
961 *pword1
= extract_unsigned_integer (buf
, 4);
962 *pword2
= extract_unsigned_integer (buf
+ 4, 4);
964 /* Divide instruction set into classes based on high 4 bits of opcode */
966 switch ((*pword1
>> 28) & 0xf)
985 len
= mem (memaddr
, *pword1
, *pword2
, 1);
988 default: /* invalid instruction */
994 return memaddr
+ len
;
999 /* 'start_frame' is a variable in the MON960 runtime startup routine
1000 that contains the frame pointer of the 'start' routine (the routine
1001 that calls 'main'). By reading its contents out of remote memory,
1002 we can tell where the frame chain ends: backtraces should halt before
1003 they display this frame. */
1006 mon960_frame_chain_valid (CORE_ADDR chain
, struct frame_info
*curframe
)
1009 struct minimal_symbol
*msymbol
;
1011 /* crtmon960.o is an assembler module that is assumed to be linked
1012 * first in an i80960 executable. It contains the true entry point;
1013 * it performs startup up initialization and then calls 'main'.
1015 * 'sf' is the name of a variable in crtmon960.o that is set
1016 * during startup to the address of the first frame.
1018 * 'a' is the address of that variable in 80960 memory.
1020 static char sf
[] = "start_frame";
1024 chain
&= ~0x3f; /* Zero low 6 bits because previous frame pointers
1025 contain return status info in them. */
1031 sym
= lookup_symbol (sf
, 0, VAR_NAMESPACE
, (int *) NULL
,
1032 (struct symtab
**) NULL
);
1035 a
= SYMBOL_VALUE (sym
);
1039 msymbol
= lookup_minimal_symbol (sf
, NULL
, NULL
);
1040 if (msymbol
== NULL
)
1042 a
= SYMBOL_VALUE_ADDRESS (msymbol
);
1045 return (chain
!= read_memory_integer (a
, 4));
1050 _initialize_i960_tdep (void)
1054 tm_print_insn
= print_insn_i960
;