1 /* Target-machine dependent code for the Intel 960
2 Copyright 1991, 1992, 1993, 1994, 1995 Free Software Foundation, Inc.
3 Contributed by Intel Corporation.
4 examine_prologue and other parts contributed by Wind River Systems.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
26 #include "floatformat.h"
30 static CORE_ADDR next_insn
PARAMS ((CORE_ADDR memaddr
,
32 unsigned int *pword2
));
34 /* Does the specified function use the "struct returning" convention
35 or the "value returning" convention? The "value returning" convention
36 almost invariably returns the entire value in registers. The
37 "struct returning" convention often returns the entire value in
38 memory, and passes a pointer (out of or into the function) saying
39 where the value (is or should go).
41 Since this sometimes depends on whether it was compiled with GCC,
42 this is also an argument. This is used in call_function to build a
43 stack, and in value_being_returned to print return values.
45 On i960, a structure is returned in registers g0-g3, if it will fit.
46 If it's more than 16 bytes long, g13 pointed to it on entry. */
49 i960_use_struct_convention (gcc_p
, type
)
53 return (TYPE_LENGTH (type
) > 16);
56 /* gdb960 is always running on a non-960 host. Check its characteristics.
57 This routine must be called as part of gdb initialization. */
64 static struct typestruct
{
65 int hostsize
; /* Size of type on host */
66 int i960size
; /* Size of type on i960 */
67 char *typename
; /* Name of type, for error msg */
69 { sizeof(short), 2, "short" },
70 { sizeof(int), 4, "int" },
71 { sizeof(long), 4, "long" },
72 { sizeof(float), 4, "float" },
73 { sizeof(double), 8, "double" },
74 { sizeof(char *), 4, "pointer" },
76 #define TYPELEN (sizeof(types) / sizeof(struct typestruct))
78 /* Make sure that host type sizes are same as i960
80 for ( i
= 0; i
< TYPELEN
; i
++ ){
81 if ( types
[i
].hostsize
!= types
[i
].i960size
){
82 printf_unfiltered("sizeof(%s) != %d: PROCEED AT YOUR OWN RISK!\n",
83 types
[i
].typename
, types
[i
].i960size
);
89 /* Examine an i960 function prologue, recording the addresses at which
90 registers are saved explicitly by the prologue code, and returning
91 the address of the first instruction after the prologue (but not
92 after the instruction at address LIMIT, as explained below).
94 LIMIT places an upper bound on addresses of the instructions to be
95 examined. If the prologue code scan reaches LIMIT, the scan is
96 aborted and LIMIT is returned. This is used, when examining the
97 prologue for the current frame, to keep examine_prologue () from
98 claiming that a given register has been saved when in fact the
99 instruction that saves it has not yet been executed. LIMIT is used
100 at other times to stop the scan when we hit code after the true
101 function prologue (e.g. for the first source line) which might
102 otherwise be mistaken for function prologue.
104 The format of the function prologue matched by this routine is
105 derived from examination of the source to gcc960 1.21, particularly
106 the routine i960_function_prologue (). A "regular expression" for
107 the function prologue is given below:
111 (mov 0, g14) | (lda 0, g14))?
113 (mov[qtl]? g[0-15], r[4-15])*
114 ((addo [1-31], sp, sp) | (lda n(sp), sp))?
115 (st[qtl]? g[0-15], n(fp))*
128 /* Macros for extracting fields from i960 instructions. */
130 #define BITMASK(pos, width) (((0x1 << (width)) - 1) << (pos))
131 #define EXTRACT_FIELD(val, pos, width) ((val) >> (pos) & BITMASK (0, width))
133 #define REG_SRC1(insn) EXTRACT_FIELD (insn, 0, 5)
134 #define REG_SRC2(insn) EXTRACT_FIELD (insn, 14, 5)
135 #define REG_SRCDST(insn) EXTRACT_FIELD (insn, 19, 5)
136 #define MEM_SRCDST(insn) EXTRACT_FIELD (insn, 19, 5)
137 #define MEMA_OFFSET(insn) EXTRACT_FIELD (insn, 0, 12)
139 /* Fetch the instruction at ADDR, returning 0 if ADDR is beyond LIM or
140 is not the address of a valid instruction, the address of the next
141 instruction beyond ADDR otherwise. *PWORD1 receives the first word
142 of the instruction, and (for two-word instructions), *PWORD2 receives
145 #define NEXT_PROLOGUE_INSN(addr, lim, pword1, pword2) \
146 (((addr) < (lim)) ? next_insn (addr, pword1, pword2) : 0)
149 examine_prologue (ip
, limit
, frame_addr
, fsr
)
150 register CORE_ADDR ip
;
151 register CORE_ADDR limit
;
152 CORE_ADDR frame_addr
;
153 struct frame_saved_regs
*fsr
;
155 register CORE_ADDR next_ip
;
156 register int src
, dst
;
157 register unsigned int *pcode
;
158 unsigned int insn1
, insn2
;
160 int within_leaf_prologue
;
162 static unsigned int varargs_prologue_code
[] =
164 0x3507a00c, /* cmpobne 0x0, g14, LFn */
165 0x5cf01601, /* mov sp, g14 */
166 0x8c086030, /* lda 0x30(sp), sp */
167 0xb2879000, /* LFn: stq g0, (g14) */
168 0xb2a7a010, /* stq g4, 0x10(g14) */
169 0xb2c7a020 /* stq g8, 0x20(g14) */
172 /* Accept a leaf procedure prologue code fragment if present.
173 Note that ip might point to either the leaf or non-leaf
174 entry point; we look for the non-leaf entry point first: */
176 within_leaf_prologue
= 0;
177 if ((next_ip
= NEXT_PROLOGUE_INSN (ip
, limit
, &insn1
, &insn2
))
178 && ((insn1
& 0xfffff000) == 0x8cf00000 /* lda LRx, g14 (MEMA) */
179 || (insn1
& 0xfffffc60) == 0x8cf03000)) /* lda LRx, g14 (MEMB) */
181 within_leaf_prologue
= 1;
182 next_ip
= NEXT_PROLOGUE_INSN (next_ip
, limit
, &insn1
, &insn2
);
185 /* Now look for the prologue code at a leaf entry point: */
188 && (insn1
& 0xff87ffff) == 0x5c80161e /* mov g14, gx */
189 && REG_SRCDST (insn1
) <= G0_REGNUM
+ 7)
191 within_leaf_prologue
= 1;
192 if ((next_ip
= NEXT_PROLOGUE_INSN (next_ip
, limit
, &insn1
, &insn2
))
193 && (insn1
== 0x8cf00000 /* lda 0, g14 */
194 || insn1
== 0x5cf01e00)) /* mov 0, g14 */
197 next_ip
= NEXT_PROLOGUE_INSN (ip
, limit
, &insn1
, &insn2
);
198 within_leaf_prologue
= 0;
202 /* If something that looks like the beginning of a leaf prologue
203 has been seen, but the remainder of the prologue is missing, bail.
204 We don't know what we've got. */
206 if (within_leaf_prologue
)
209 /* Accept zero or more instances of "mov[qtl]? gx, ry", where y >= 4.
210 This may cause us to mistake the moving of a register
211 parameter to a local register for the saving of a callee-saved
212 register, but that can't be helped, since with the
213 "-fcall-saved" flag, any register can be made callee-saved. */
216 && (insn1
& 0xfc802fb0) == 0x5c000610
217 && (dst
= REG_SRCDST (insn1
)) >= (R0_REGNUM
+ 4))
219 src
= REG_SRC1 (insn1
);
220 size
= EXTRACT_FIELD (insn1
, 24, 2) + 1;
221 save_addr
= frame_addr
+ ((dst
- R0_REGNUM
) * 4);
224 fsr
->regs
[src
++] = save_addr
;
228 next_ip
= NEXT_PROLOGUE_INSN (ip
, limit
, &insn1
, &insn2
);
231 /* Accept an optional "addo n, sp, sp" or "lda n(sp), sp". */
234 ((insn1
& 0xffffffe0) == 0x59084800 /* addo n, sp, sp */
235 || (insn1
& 0xfffff000) == 0x8c086000 /* lda n(sp), sp (MEMA) */
236 || (insn1
& 0xfffffc60) == 0x8c087400)) /* lda n(sp), sp (MEMB) */
239 next_ip
= NEXT_PROLOGUE_INSN (ip
, limit
, &insn1
, &insn2
);
242 /* Accept zero or more instances of "st[qtl]? gx, n(fp)".
243 This may cause us to mistake the copying of a register
244 parameter to the frame for the saving of a callee-saved
245 register, but that can't be helped, since with the
246 "-fcall-saved" flag, any register can be made callee-saved.
247 We can, however, refuse to accept a save of register g14,
248 since that is matched explicitly below. */
251 ((insn1
& 0xf787f000) == 0x9287e000 /* stl? gx, n(fp) (MEMA) */
252 || (insn1
& 0xf787fc60) == 0x9287f400 /* stl? gx, n(fp) (MEMB) */
253 || (insn1
& 0xef87f000) == 0xa287e000 /* st[tq] gx, n(fp) (MEMA) */
254 || (insn1
& 0xef87fc60) == 0xa287f400) /* st[tq] gx, n(fp) (MEMB) */
255 && ((src
= MEM_SRCDST (insn1
)) != G14_REGNUM
))
257 save_addr
= frame_addr
+ ((insn1
& BITMASK (12, 1))
258 ? insn2
: MEMA_OFFSET (insn1
));
259 size
= (insn1
& BITMASK (29, 1)) ? ((insn1
& BITMASK (28, 1)) ? 4 : 3)
260 : ((insn1
& BITMASK (27, 1)) ? 2 : 1);
263 fsr
->regs
[src
++] = save_addr
;
267 next_ip
= NEXT_PROLOGUE_INSN (ip
, limit
, &insn1
, &insn2
);
270 /* Accept the varargs prologue code if present. */
272 size
= sizeof (varargs_prologue_code
) / sizeof (int);
273 pcode
= varargs_prologue_code
;
274 while (size
-- && next_ip
&& *pcode
++ == insn1
)
277 next_ip
= NEXT_PROLOGUE_INSN (ip
, limit
, &insn1
, &insn2
);
280 /* Accept an optional "st g14, n(fp)". */
283 ((insn1
& 0xfffff000) == 0x92f7e000 /* st g14, n(fp) (MEMA) */
284 || (insn1
& 0xfffffc60) == 0x92f7f400)) /* st g14, n(fp) (MEMB) */
286 fsr
->regs
[G14_REGNUM
] = frame_addr
+ ((insn1
& BITMASK (12, 1))
287 ? insn2
: MEMA_OFFSET (insn1
));
289 next_ip
= NEXT_PROLOGUE_INSN (ip
, limit
, &insn1
, &insn2
);
292 /* Accept zero or one instance of "mov g13, ry", where y >= 4.
293 This is saving the address where a struct should be returned. */
296 && (insn1
& 0xff802fbf) == 0x5c00061d
297 && (dst
= REG_SRCDST (insn1
)) >= (R0_REGNUM
+ 4))
299 save_addr
= frame_addr
+ ((dst
- R0_REGNUM
) * 4);
300 fsr
->regs
[G0_REGNUM
+13] = save_addr
;
302 #if 0 /* We'll need this once there is a subsequent instruction examined. */
303 next_ip
= NEXT_PROLOGUE_INSN (ip
, limit
, &insn1
, &insn2
);
310 /* Given an ip value corresponding to the start of a function,
311 return the ip of the first instruction after the function
318 struct frame_saved_regs saved_regs_dummy
;
319 struct symtab_and_line sal
;
322 sal
= find_pc_line (ip
, 0);
323 limit
= (sal
.end
) ? sal
.end
: 0xffffffff;
325 return (examine_prologue (ip
, limit
, (CORE_ADDR
) 0, &saved_regs_dummy
));
328 /* Put here the code to store, into a struct frame_saved_regs,
329 the addresses of the saved registers of frame described by FRAME_INFO.
330 This includes special registers such as pc and fp saved in special
331 ways in the stack frame. sp is even more special:
332 the address we return for it IS the sp for the next frame.
334 We cache the result of doing this in the frame_obstack, since it is
338 frame_find_saved_regs (fi
, fsr
)
339 struct frame_info
*fi
;
340 struct frame_saved_regs
*fsr
;
342 register CORE_ADDR next_addr
;
343 register CORE_ADDR
*saved_regs
;
345 register struct frame_saved_regs
*cache_fsr
;
347 struct symtab_and_line sal
;
352 cache_fsr
= (struct frame_saved_regs
*)
353 frame_obstack_alloc (sizeof (struct frame_saved_regs
));
354 memset (cache_fsr
, '\0', sizeof (struct frame_saved_regs
));
357 /* Find the start and end of the function prologue. If the PC
358 is in the function prologue, we only consider the part that
359 has executed already. */
361 ip
= get_pc_function_start (fi
->pc
);
362 sal
= find_pc_line (ip
, 0);
363 limit
= (sal
.end
&& sal
.end
< fi
->pc
) ? sal
.end
: fi
->pc
;
365 examine_prologue (ip
, limit
, fi
->frame
, cache_fsr
);
367 /* Record the addresses at which the local registers are saved.
368 Strictly speaking, we should only do this for non-leaf procedures,
369 but no one will ever look at these values if it is a leaf procedure,
370 since local registers are always caller-saved. */
372 next_addr
= (CORE_ADDR
) fi
->frame
;
373 saved_regs
= cache_fsr
->regs
;
374 for (regnum
= R0_REGNUM
; regnum
<= R15_REGNUM
; regnum
++)
376 *saved_regs
++ = next_addr
;
380 cache_fsr
->regs
[FP_REGNUM
] = cache_fsr
->regs
[PFP_REGNUM
];
385 /* Fetch the value of the sp from memory every time, since it
386 is conceivable that it has changed since the cache was flushed.
387 This unfortunately undoes much of the savings from caching the
388 saved register values. I suggest adding an argument to
389 get_frame_saved_regs () specifying the register number we're
390 interested in (or -1 for all registers). This would be passed
391 through to FRAME_FIND_SAVED_REGS (), permitting more efficient
392 computation of saved register addresses (e.g., on the i960,
393 we don't have to examine the prologue to find local registers).
395 FIXME, we don't need to refetch this, since the cache is cleared
396 every time the child process is restarted. If GDB itself
397 modifies SP, it has to clear the cache by hand (does it?). -gnu */
399 fsr
->regs
[SP_REGNUM
] = read_memory_integer (fsr
->regs
[SP_REGNUM
], 4);
402 /* Return the address of the argument block for the frame
403 described by FI. Returns 0 if the address is unknown. */
406 frame_args_address (fi
, must_be_correct
)
407 struct frame_info
*fi
;
409 struct frame_saved_regs fsr
;
412 /* If g14 was saved in the frame by the function prologue code, return
413 the saved value. If the frame is current and we are being sloppy,
414 return the value of g14. Otherwise, return zero. */
416 get_frame_saved_regs (fi
, &fsr
);
417 if (fsr
.regs
[G14_REGNUM
])
418 ap
= read_memory_integer (fsr
.regs
[G14_REGNUM
],4);
422 return 0; /* Don't cache this result */
423 if (get_next_frame (fi
))
426 ap
= read_register (G14_REGNUM
);
430 fi
->arg_pointer
= ap
; /* Cache it for next time */
434 /* Return the address of the return struct for the frame
435 described by FI. Returns 0 if the address is unknown. */
438 frame_struct_result_address (fi
)
439 struct frame_info
*fi
;
441 struct frame_saved_regs fsr
;
444 /* If the frame is non-current, check to see if g14 was saved in the
445 frame by the function prologue code; return the saved value if so,
446 zero otherwise. If the frame is current, return the value of g14.
448 FIXME, shouldn't this use the saved value as long as we are past
449 the function prologue, and only use the current value if we have
450 no saved value and are at TOS? -- gnu@cygnus.com */
452 if (get_next_frame (fi
))
454 get_frame_saved_regs (fi
, &fsr
);
455 if (fsr
.regs
[G13_REGNUM
])
456 ap
= read_memory_integer (fsr
.regs
[G13_REGNUM
],4);
461 ap
= read_register (G13_REGNUM
);
466 /* Return address to which the currently executing leafproc will return,
467 or 0 if ip is not in a leafproc (or if we can't tell if it is).
469 Do this by finding the starting address of the routine in which ip lies.
470 If the instruction there is "mov g14, gx" (where x is in [0,7]), this
471 is a leafproc and the return address is in register gx. Well, this is
472 true unless the return address points at a RET instruction in the current
473 procedure, which indicates that we have a 'dual entry' routine that
474 has been entered through the CALL entry point. */
478 CORE_ADDR ip
; /* ip from currently executing function */
480 register struct minimal_symbol
*msymbol
;
483 unsigned int insn1
, insn2
;
484 CORE_ADDR return_addr
;
486 if ((msymbol
= lookup_minimal_symbol_by_pc (ip
)) != NULL
)
488 if ((p
= strchr(SYMBOL_NAME (msymbol
), '.')) && STREQ (p
, ".lf"))
490 if (next_insn (SYMBOL_VALUE_ADDRESS (msymbol
), &insn1
, &insn2
)
491 && (insn1
& 0xff87ffff) == 0x5c80161e /* mov g14, gx */
492 && (dst
= REG_SRCDST (insn1
)) <= G0_REGNUM
+ 7)
494 /* Get the return address. If the "mov g14, gx"
495 instruction hasn't been executed yet, read
496 the return address from g14; otherwise, read it
497 from the register into which g14 was moved. */
500 read_register ((ip
== SYMBOL_VALUE_ADDRESS (msymbol
))
503 /* We know we are in a leaf procedure, but we don't know
504 whether the caller actually did a "bal" to the ".lf"
505 entry point, or a normal "call" to the non-leaf entry
506 point one instruction before. In the latter case, the
507 return address will be the address of a "ret"
508 instruction within the procedure itself. We test for
511 if (!next_insn (return_addr
, &insn1
, &insn2
)
512 || (insn1
& 0xff000000) != 0xa000000 /* ret */
513 || lookup_minimal_symbol_by_pc (return_addr
) != msymbol
)
514 return (return_addr
);
522 /* Immediately after a function call, return the saved pc.
523 Can't go through the frames for this because on some machines
524 the new frame is not set up until the new function executes
526 On the i960, the frame *is* set up immediately after the call,
527 unless the function is a leaf procedure. */
530 saved_pc_after_call (frame
)
531 struct frame_info
*frame
;
535 saved_pc
= leafproc_return (get_frame_pc (frame
));
537 saved_pc
= FRAME_SAVED_PC (frame
);
542 /* Discard from the stack the innermost frame,
543 restoring all saved registers. */
548 register struct frame_info
*current_fi
, *prev_fi
;
551 CORE_ADDR leaf_return_addr
;
552 struct frame_saved_regs fsr
;
553 char local_regs_buf
[16 * 4];
555 current_fi
= get_current_frame ();
557 /* First, undo what the hardware does when we return.
558 If this is a non-leaf procedure, restore local registers from
559 the save area in the calling frame. Otherwise, load the return
560 address obtained from leafproc_return () into the rip. */
562 leaf_return_addr
= leafproc_return (current_fi
->pc
);
563 if (!leaf_return_addr
)
565 /* Non-leaf procedure. Restore local registers, incl IP. */
566 prev_fi
= get_prev_frame (current_fi
);
567 read_memory (prev_fi
->frame
, local_regs_buf
, sizeof (local_regs_buf
));
568 write_register_bytes (REGISTER_BYTE (R0_REGNUM
), local_regs_buf
,
569 sizeof (local_regs_buf
));
571 /* Restore frame pointer. */
572 write_register (FP_REGNUM
, prev_fi
->frame
);
576 /* Leaf procedure. Just restore the return address into the IP. */
577 write_register (RIP_REGNUM
, leaf_return_addr
);
580 /* Now restore any global regs that the current function had saved. */
581 get_frame_saved_regs (current_fi
, &fsr
);
582 for (i
= G0_REGNUM
; i
< G14_REGNUM
; i
++)
584 if (save_addr
= fsr
.regs
[i
])
585 write_register (i
, read_memory_integer (save_addr
, 4));
588 /* Flush the frame cache, create a frame for the new innermost frame,
589 and make it the current frame. */
591 flush_cached_frames ();
594 /* Given a 960 stop code (fault or trace), return the signal which
598 i960_fault_to_signal (fault
)
603 case 0: return TARGET_SIGNAL_BUS
; /* parallel fault */
604 case 1: return TARGET_SIGNAL_UNKNOWN
;
605 case 2: return TARGET_SIGNAL_ILL
; /* operation fault */
606 case 3: return TARGET_SIGNAL_FPE
; /* arithmetic fault */
607 case 4: return TARGET_SIGNAL_FPE
; /* floating point fault */
609 /* constraint fault. This appears not to distinguish between
610 a range constraint fault (which should be SIGFPE) and a privileged
611 fault (which should be SIGILL). */
612 case 5: return TARGET_SIGNAL_ILL
;
614 case 6: return TARGET_SIGNAL_SEGV
; /* virtual memory fault */
616 /* protection fault. This is for an out-of-range argument to
617 "calls". I guess it also could be SIGILL. */
618 case 7: return TARGET_SIGNAL_SEGV
;
620 case 8: return TARGET_SIGNAL_BUS
; /* machine fault */
621 case 9: return TARGET_SIGNAL_BUS
; /* structural fault */
622 case 0xa: return TARGET_SIGNAL_ILL
; /* type fault */
623 case 0xb: return TARGET_SIGNAL_UNKNOWN
; /* reserved fault */
624 case 0xc: return TARGET_SIGNAL_BUS
; /* process fault */
625 case 0xd: return TARGET_SIGNAL_SEGV
; /* descriptor fault */
626 case 0xe: return TARGET_SIGNAL_BUS
; /* event fault */
627 case 0xf: return TARGET_SIGNAL_UNKNOWN
; /* reserved fault */
628 case 0x10: return TARGET_SIGNAL_TRAP
; /* single-step trace */
629 case 0x11: return TARGET_SIGNAL_TRAP
; /* branch trace */
630 case 0x12: return TARGET_SIGNAL_TRAP
; /* call trace */
631 case 0x13: return TARGET_SIGNAL_TRAP
; /* return trace */
632 case 0x14: return TARGET_SIGNAL_TRAP
; /* pre-return trace */
633 case 0x15: return TARGET_SIGNAL_TRAP
; /* supervisor call trace */
634 case 0x16: return TARGET_SIGNAL_TRAP
; /* breakpoint trace */
635 default: return TARGET_SIGNAL_UNKNOWN
;
639 /****************************************/
641 /****************************************/
648 static int /* returns instruction length: 4 or 8 */
649 mem( memaddr
, word1
, word2
, noprint
)
650 unsigned long memaddr
;
651 unsigned long word1
, word2
;
652 int noprint
; /* If TRUE, return instruction length, but
653 don't output any text. */
659 const char *reg1
, *reg2
, *reg3
;
661 /* This lookup table is too sparse to make it worth typing in, but not
662 * so large as to make a sparse array necessary. We allocate the
663 * table at runtime, initialize all entries to empty, and copy the
664 * real ones in from an initialization table.
666 * NOTE: In this table, the meaning of 'numops' is:
668 * 2: 2 operands, load instruction
669 * -2: 2 operands, store instruction
671 static struct tabent
*mem_tab
= NULL
;
672 /* Opcodes of 0x8X, 9X, aX, bX, and cX must be in the table. */
675 #define MEM_SIZ ((MEM_MAX-MEM_MIN+1) * sizeof(struct tabent))
677 static struct { int opcode
; char *name
; char numops
; } mem_init
[] = {
701 if ( mem_tab
== NULL
){
702 mem_tab
= (struct tabent
*) xmalloc( MEM_SIZ
);
703 memset( mem_tab
, '\0', MEM_SIZ
);
704 for ( i
= 0; mem_init
[i
].opcode
!= 0; i
++ ){
705 j
= mem_init
[i
].opcode
- MEM_MIN
;
706 mem_tab
[j
].name
= mem_init
[i
].name
;
707 mem_tab
[j
].numops
= mem_init
[i
].numops
;
711 i
= ((word1
>> 24) & 0xff) - MEM_MIN
;
712 mode
= (word1
>> 10) & 0xf;
714 if ( (mem_tab
[i
].name
!= NULL
) /* Valid instruction */
715 && ((mode
== 5) || (mode
>=12)) ){ /* With 32-bit displacement */
727 /* Read the i960 instruction at 'memaddr' and return the address of
728 the next instruction after that, or 0 if 'memaddr' is not the
729 address of a valid instruction. The first word of the instruction
730 is stored at 'pword1', and the second word, if any, is stored at
734 next_insn (memaddr
, pword1
, pword2
)
735 unsigned int *pword1
, *pword2
;
741 /* Read the two (potential) words of the instruction at once,
742 to eliminate the overhead of two calls to read_memory ().
743 FIXME: Loses if the first one is readable but the second is not
744 (e.g. last word of the segment). */
746 read_memory (memaddr
, buf
, 8);
747 *pword1
= extract_unsigned_integer (buf
, 4);
748 *pword2
= extract_unsigned_integer (buf
+ 4, 4);
750 /* Divide instruction set into classes based on high 4 bits of opcode*/
752 switch ((*pword1
>> 28) & 0xf)
771 len
= mem (memaddr
, *pword1
, *pword2
, 1);
774 default: /* invalid instruction */
780 return memaddr
+ len
;
785 /* 'start_frame' is a variable in the MON960 runtime startup routine
786 that contains the frame pointer of the 'start' routine (the routine
787 that calls 'main'). By reading its contents out of remote memory,
788 we can tell where the frame chain ends: backtraces should halt before
789 they display this frame. */
792 mon960_frame_chain_valid (chain
, curframe
)
794 struct frame_info
*curframe
;
797 struct minimal_symbol
*msymbol
;
799 /* crtmon960.o is an assembler module that is assumed to be linked
800 * first in an i80960 executable. It contains the true entry point;
801 * it performs startup up initialization and then calls 'main'.
803 * 'sf' is the name of a variable in crtmon960.o that is set
804 * during startup to the address of the first frame.
806 * 'a' is the address of that variable in 80960 memory.
808 static char sf
[] = "start_frame";
812 chain
&= ~0x3f; /* Zero low 6 bits because previous frame pointers
813 contain return status info in them. */
818 sym
= lookup_symbol(sf
, 0, VAR_NAMESPACE
, (int *)NULL
,
819 (struct symtab
**)NULL
);
821 a
= SYMBOL_VALUE (sym
);
823 msymbol
= lookup_minimal_symbol (sf
, NULL
, NULL
);
826 a
= SYMBOL_VALUE_ADDRESS (msymbol
);
829 return ( chain
!= read_memory_integer(a
,4) );
833 _initialize_i960_tdep ()
837 tm_print_insn
= print_insn_i960
;