1 /* Functions specific to running gdb native on IA-64 running
4 Copyright 1999, 2000, 2001, 2002, 2003, 2004
5 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
25 #include "gdb_string.h"
32 #include <sys/ptrace.h>
37 #include <sys/syscall.h>
40 #include <asm/ptrace_offsets.h>
41 #include <sys/procfs.h>
43 /* Prototypes for supply_gregset etc. */
46 /* These must match the order of the register names.
48 Some sort of lookup table is needed because the offsets associated
49 with the registers are all over the board. */
51 static int u_offsets
[] =
53 /* general registers */
54 -1, /* gr0 not available; i.e, it's always zero */
86 /* gr32 through gr127 not directly available via the ptrace interface */
87 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
88 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
89 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
90 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
91 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
92 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
93 /* Floating point registers */
94 -1, -1, /* f0 and f1 not available (f0 is +0.0 and f1 is +1.0) */
221 /* predicate registers - we don't fetch these individually */
222 -1, -1, -1, -1, -1, -1, -1, -1,
223 -1, -1, -1, -1, -1, -1, -1, -1,
224 -1, -1, -1, -1, -1, -1, -1, -1,
225 -1, -1, -1, -1, -1, -1, -1, -1,
226 -1, -1, -1, -1, -1, -1, -1, -1,
227 -1, -1, -1, -1, -1, -1, -1, -1,
228 -1, -1, -1, -1, -1, -1, -1, -1,
229 -1, -1, -1, -1, -1, -1, -1, -1,
230 /* branch registers */
239 /* virtual frame pointer and virtual return address pointer */
241 /* other registers */
244 PT_CR_IPSR
, /* psr */
246 /* kernel registers not visible via ptrace interface (?) */
247 -1, -1, -1, -1, -1, -1, -1, -1,
249 -1, -1, -1, -1, -1, -1, -1, -1,
255 -1, /* Not available: FCR, IA32 floating control register */
257 -1, /* Not available: EFLAG */
258 -1, /* Not available: CSD */
259 -1, /* Not available: SSD */
260 -1, /* Not available: CFLG */
261 -1, /* Not available: FSR */
262 -1, /* Not available: FIR */
263 -1, /* Not available: FDR */
271 -1, /* Not available: ITC */
272 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
273 -1, -1, -1, -1, -1, -1, -1, -1, -1,
276 -1, /* Not available: EC, the Epilog Count register */
277 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
278 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
279 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
280 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
281 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
282 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
284 /* nat bits - not fetched directly; instead we obtain these bits from
285 either rnat or unat or from memory. */
286 -1, -1, -1, -1, -1, -1, -1, -1,
287 -1, -1, -1, -1, -1, -1, -1, -1,
288 -1, -1, -1, -1, -1, -1, -1, -1,
289 -1, -1, -1, -1, -1, -1, -1, -1,
290 -1, -1, -1, -1, -1, -1, -1, -1,
291 -1, -1, -1, -1, -1, -1, -1, -1,
292 -1, -1, -1, -1, -1, -1, -1, -1,
293 -1, -1, -1, -1, -1, -1, -1, -1,
294 -1, -1, -1, -1, -1, -1, -1, -1,
295 -1, -1, -1, -1, -1, -1, -1, -1,
296 -1, -1, -1, -1, -1, -1, -1, -1,
297 -1, -1, -1, -1, -1, -1, -1, -1,
298 -1, -1, -1, -1, -1, -1, -1, -1,
299 -1, -1, -1, -1, -1, -1, -1, -1,
300 -1, -1, -1, -1, -1, -1, -1, -1,
301 -1, -1, -1, -1, -1, -1, -1, -1,
305 register_addr (int regno
, CORE_ADDR blockend
)
309 if (regno
< 0 || regno
>= NUM_REGS
)
310 error ("Invalid register number %d.", regno
);
312 if (u_offsets
[regno
] == -1)
315 addr
= (CORE_ADDR
) u_offsets
[regno
];
320 int ia64_cannot_fetch_register (regno
)
323 return regno
< 0 || regno
>= NUM_REGS
|| u_offsets
[regno
] == -1;
326 int ia64_cannot_store_register (regno
)
329 /* Rationale behind not permitting stores to bspstore...
331 The IA-64 architecture provides bspstore and bsp which refer
332 memory locations in the RSE's backing store. bspstore is the
333 next location which will be written when the RSE needs to write
334 to memory. bsp is the address at which r32 in the current frame
335 would be found if it were written to the backing store.
337 The IA-64 architecture provides read-only access to bsp and
338 read/write access to bspstore (but only when the RSE is in
339 the enforced lazy mode). It should be noted that stores
340 to bspstore also affect the value of bsp. Changing bspstore
341 does not affect the number of dirty entries between bspstore
342 and bsp, so changing bspstore by N words will also cause bsp
343 to be changed by (roughly) N as well. (It could be N-1 or N+1
344 depending upon where the NaT collection bits fall.)
346 OTOH, the Linux kernel provides read/write access to bsp (and
347 currently read/write access to bspstore as well). But it
348 is definitely the case that if you change one, the other
349 will change at the same time. It is more useful to gdb to
350 be able to change bsp. So in order to prevent strange and
351 undesirable things from happening when a dummy stack frame
352 is popped (after calling an inferior function), we allow
353 bspstore to be read, but not written. (Note that popping
354 a (generic) dummy stack frame causes all registers that
355 were previously read from the inferior process to be written
358 return regno
< 0 || regno
>= NUM_REGS
|| u_offsets
[regno
] == -1
359 || regno
== IA64_BSPSTORE_REGNUM
;
363 supply_gregset (gregset_t
*gregsetp
)
366 greg_t
*regp
= (greg_t
*) gregsetp
;
368 for (regi
= IA64_GR0_REGNUM
; regi
<= IA64_GR31_REGNUM
; regi
++)
370 regcache_raw_supply (current_regcache
, regi
,
371 (char *) (regp
+ (regi
- IA64_GR0_REGNUM
)));
374 /* FIXME: NAT collection bits are at index 32; gotta deal with these
377 regcache_raw_supply (current_regcache
, IA64_PR_REGNUM
, (char *) (regp
+ 33));
379 for (regi
= IA64_BR0_REGNUM
; regi
<= IA64_BR7_REGNUM
; regi
++)
381 regcache_raw_supply (current_regcache
, regi
,
382 (char *) (regp
+ 34 + (regi
- IA64_BR0_REGNUM
)));
385 regcache_raw_supply (current_regcache
, IA64_IP_REGNUM
,
386 (char *) (regp
+ 42));
387 regcache_raw_supply (current_regcache
, IA64_CFM_REGNUM
,
388 (char *) (regp
+ 43));
389 regcache_raw_supply (current_regcache
, IA64_PSR_REGNUM
,
390 (char *) (regp
+ 44));
391 regcache_raw_supply (current_regcache
, IA64_RSC_REGNUM
,
392 (char *) (regp
+ 45));
393 regcache_raw_supply (current_regcache
, IA64_BSP_REGNUM
,
394 (char *) (regp
+ 46));
395 regcache_raw_supply (current_regcache
, IA64_BSPSTORE_REGNUM
,
396 (char *) (regp
+ 47));
397 regcache_raw_supply (current_regcache
, IA64_RNAT_REGNUM
,
398 (char *) (regp
+ 48));
399 regcache_raw_supply (current_regcache
, IA64_CCV_REGNUM
,
400 (char *) (regp
+ 49));
401 regcache_raw_supply (current_regcache
, IA64_UNAT_REGNUM
,
402 (char *) (regp
+ 50));
403 regcache_raw_supply (current_regcache
, IA64_FPSR_REGNUM
,
404 (char *) (regp
+ 51));
405 regcache_raw_supply (current_regcache
, IA64_PFS_REGNUM
,
406 (char *) (regp
+ 52));
407 regcache_raw_supply (current_regcache
, IA64_LC_REGNUM
,
408 (char *) (regp
+ 53));
409 regcache_raw_supply (current_regcache
, IA64_EC_REGNUM
,
410 (char *) (regp
+ 54));
414 fill_gregset (gregset_t
*gregsetp
, int regno
)
417 greg_t
*regp
= (greg_t
*) gregsetp
;
419 #define COPY_REG(_idx_,_regi_) \
420 if ((regno == -1) || regno == _regi_) \
421 memcpy (regp + _idx_, &deprecated_registers[DEPRECATED_REGISTER_BYTE (_regi_)], \
422 register_size (current_gdbarch, _regi_))
424 for (regi
= IA64_GR0_REGNUM
; regi
<= IA64_GR31_REGNUM
; regi
++)
426 COPY_REG (regi
- IA64_GR0_REGNUM
, regi
);
429 /* FIXME: NAT collection bits at index 32? */
431 COPY_REG (33, IA64_PR_REGNUM
);
433 for (regi
= IA64_BR0_REGNUM
; regi
<= IA64_BR7_REGNUM
; regi
++)
435 COPY_REG (34 + (regi
- IA64_BR0_REGNUM
), regi
);
438 COPY_REG (42, IA64_IP_REGNUM
);
439 COPY_REG (43, IA64_CFM_REGNUM
);
440 COPY_REG (44, IA64_PSR_REGNUM
);
441 COPY_REG (45, IA64_RSC_REGNUM
);
442 COPY_REG (46, IA64_BSP_REGNUM
);
443 COPY_REG (47, IA64_BSPSTORE_REGNUM
);
444 COPY_REG (48, IA64_RNAT_REGNUM
);
445 COPY_REG (49, IA64_CCV_REGNUM
);
446 COPY_REG (50, IA64_UNAT_REGNUM
);
447 COPY_REG (51, IA64_FPSR_REGNUM
);
448 COPY_REG (52, IA64_PFS_REGNUM
);
449 COPY_REG (53, IA64_LC_REGNUM
);
450 COPY_REG (54, IA64_EC_REGNUM
);
453 /* Given a pointer to a floating point register set in /proc format
454 (fpregset_t *), unpack the register contents and supply them as gdb's
455 idea of the current floating point register values. */
458 supply_fpregset (fpregset_t
*fpregsetp
)
463 for (regi
= IA64_FR0_REGNUM
; regi
<= IA64_FR127_REGNUM
; regi
++)
465 from
= (char *) &((*fpregsetp
)[regi
- IA64_FR0_REGNUM
]);
466 regcache_raw_supply (current_regcache
, regi
, from
);
470 /* Given a pointer to a floating point register set in /proc format
471 (fpregset_t *), update the register specified by REGNO from gdb's idea
472 of the current floating point register set. If REGNO is -1, update
476 fill_fpregset (fpregset_t
*fpregsetp
, int regno
)
482 for (regi
= IA64_FR0_REGNUM
; regi
<= IA64_FR127_REGNUM
; regi
++)
484 if ((regno
== -1) || (regno
== regi
))
486 from
= (char *) &deprecated_registers
[DEPRECATED_REGISTER_BYTE (regi
)];
487 to
= (char *) &((*fpregsetp
)[regi
- IA64_FR0_REGNUM
]);
488 memcpy (to
, from
, register_size (current_gdbarch
, regi
));
493 #define IA64_PSR_DB (1UL << 24)
494 #define IA64_PSR_DD (1UL << 39)
497 enable_watchpoints_in_psr (ptid_t ptid
)
501 psr
= read_register_pid (IA64_PSR_REGNUM
, ptid
);
502 if (!(psr
& IA64_PSR_DB
))
504 psr
|= IA64_PSR_DB
; /* Set the db bit - this enables hardware
505 watchpoints and breakpoints. */
506 write_register_pid (IA64_PSR_REGNUM
, psr
, ptid
);
511 fetch_debug_register (ptid_t ptid
, int idx
)
520 val
= ptrace (PT_READ_U
, tid
, (PTRACE_TYPE_ARG3
) (PT_DBR
+ 8 * idx
), 0);
526 store_debug_register (ptid_t ptid
, int idx
, long val
)
534 (void) ptrace (PT_WRITE_U
, tid
, (PTRACE_TYPE_ARG3
) (PT_DBR
+ 8 * idx
), val
);
538 fetch_debug_register_pair (ptid_t ptid
, int idx
, long *dbr_addr
, long *dbr_mask
)
541 *dbr_addr
= fetch_debug_register (ptid
, 2 * idx
);
543 *dbr_mask
= fetch_debug_register (ptid
, 2 * idx
+ 1);
547 store_debug_register_pair (ptid_t ptid
, int idx
, long *dbr_addr
, long *dbr_mask
)
550 store_debug_register (ptid
, 2 * idx
, *dbr_addr
);
552 store_debug_register (ptid
, 2 * idx
+ 1, *dbr_mask
);
556 is_power_of_2 (int val
)
561 for (i
= 0; i
< 8 * sizeof (val
); i
++)
565 return onecount
<= 1;
569 ia64_linux_insert_watchpoint (ptid_t ptid
, CORE_ADDR addr
, int len
, int rw
)
572 long dbr_addr
, dbr_mask
;
573 int max_watchpoints
= 4;
575 if (len
<= 0 || !is_power_of_2 (len
))
578 for (idx
= 0; idx
< max_watchpoints
; idx
++)
580 fetch_debug_register_pair (ptid
, idx
, NULL
, &dbr_mask
);
581 if ((dbr_mask
& (0x3UL
<< 62)) == 0)
583 /* Exit loop if both r and w bits clear */
588 if (idx
== max_watchpoints
)
591 dbr_addr
= (long) addr
;
592 dbr_mask
= (~(len
- 1) & 0x00ffffffffffffffL
); /* construct mask to match */
593 dbr_mask
|= 0x0800000000000000L
; /* Only match privilege level 3 */
597 dbr_mask
|= (1L << 62); /* Set w bit */
600 dbr_mask
|= (1L << 63); /* Set r bit */
603 dbr_mask
|= (3L << 62); /* Set both r and w bits */
609 store_debug_register_pair (ptid
, idx
, &dbr_addr
, &dbr_mask
);
610 enable_watchpoints_in_psr (ptid
);
616 ia64_linux_remove_watchpoint (ptid_t ptid
, CORE_ADDR addr
, int len
)
619 long dbr_addr
, dbr_mask
;
620 int max_watchpoints
= 4;
622 if (len
<= 0 || !is_power_of_2 (len
))
625 for (idx
= 0; idx
< max_watchpoints
; idx
++)
627 fetch_debug_register_pair (ptid
, idx
, &dbr_addr
, &dbr_mask
);
628 if ((dbr_mask
& (0x3UL
<< 62)) && addr
== (CORE_ADDR
) dbr_addr
)
632 store_debug_register_pair (ptid
, idx
, &dbr_addr
, &dbr_mask
);
640 ia64_linux_stopped_by_watchpoint (ptid_t ptid
)
644 struct siginfo siginfo
;
651 ptrace (PTRACE_GETSIGINFO
, tid
, (PTRACE_TYPE_ARG3
) 0, &siginfo
);
653 if (errno
!= 0 || siginfo
.si_signo
!= SIGTRAP
||
654 (siginfo
.si_code
& 0xffff) != 0x0004 /* TRAP_HWBKPT */)
657 psr
= read_register_pid (IA64_PSR_REGNUM
, ptid
);
658 psr
|= IA64_PSR_DD
; /* Set the dd bit - this will disable the watchpoint
659 for the next instruction */
660 write_register_pid (IA64_PSR_REGNUM
, psr
, ptid
);
662 return (CORE_ADDR
) siginfo
.si_addr
;
666 ia64_linux_xfer_unwind_table (struct target_ops
*ops
,
667 enum target_object object
,
669 void *readbuf
, const void *writebuf
,
670 ULONGEST offset
, LONGEST len
)
672 return syscall (__NR_getunwind
, readbuf
, len
);
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