1 /* Functions specific to running gdb native on IA-64 running
4 Copyright 1999, 2000, 2001, 2002, 2003, 2004
5 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
25 #include "gdb_string.h"
32 #include <sys/ptrace.h>
37 #include <sys/syscall.h>
40 #include <asm/ptrace_offsets.h>
41 #include <sys/procfs.h>
43 /* Prototypes for supply_gregset etc. */
46 /* These must match the order of the register names.
48 Some sort of lookup table is needed because the offsets associated
49 with the registers are all over the board. */
51 static int u_offsets
[] =
53 /* general registers */
54 -1, /* gr0 not available; i.e, it's always zero */
86 /* gr32 through gr127 not directly available via the ptrace interface */
87 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
88 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
89 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
90 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
91 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
92 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
93 /* Floating point registers */
94 -1, -1, /* f0 and f1 not available (f0 is +0.0 and f1 is +1.0) */
221 /* predicate registers - we don't fetch these individually */
222 -1, -1, -1, -1, -1, -1, -1, -1,
223 -1, -1, -1, -1, -1, -1, -1, -1,
224 -1, -1, -1, -1, -1, -1, -1, -1,
225 -1, -1, -1, -1, -1, -1, -1, -1,
226 -1, -1, -1, -1, -1, -1, -1, -1,
227 -1, -1, -1, -1, -1, -1, -1, -1,
228 -1, -1, -1, -1, -1, -1, -1, -1,
229 -1, -1, -1, -1, -1, -1, -1, -1,
230 /* branch registers */
239 /* virtual frame pointer and virtual return address pointer */
241 /* other registers */
244 PT_CR_IPSR
, /* psr */
246 /* kernel registers not visible via ptrace interface (?) */
247 -1, -1, -1, -1, -1, -1, -1, -1,
249 -1, -1, -1, -1, -1, -1, -1, -1,
255 -1, /* Not available: FCR, IA32 floating control register */
257 -1, /* Not available: EFLAG */
258 -1, /* Not available: CSD */
259 -1, /* Not available: SSD */
260 -1, /* Not available: CFLG */
261 -1, /* Not available: FSR */
262 -1, /* Not available: FIR */
263 -1, /* Not available: FDR */
271 -1, /* Not available: ITC */
272 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
273 -1, -1, -1, -1, -1, -1, -1, -1, -1,
276 -1, /* Not available: EC, the Epilog Count register */
277 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
278 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
279 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
280 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
281 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
282 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
284 /* nat bits - not fetched directly; instead we obtain these bits from
285 either rnat or unat or from memory. */
286 -1, -1, -1, -1, -1, -1, -1, -1,
287 -1, -1, -1, -1, -1, -1, -1, -1,
288 -1, -1, -1, -1, -1, -1, -1, -1,
289 -1, -1, -1, -1, -1, -1, -1, -1,
290 -1, -1, -1, -1, -1, -1, -1, -1,
291 -1, -1, -1, -1, -1, -1, -1, -1,
292 -1, -1, -1, -1, -1, -1, -1, -1,
293 -1, -1, -1, -1, -1, -1, -1, -1,
294 -1, -1, -1, -1, -1, -1, -1, -1,
295 -1, -1, -1, -1, -1, -1, -1, -1,
296 -1, -1, -1, -1, -1, -1, -1, -1,
297 -1, -1, -1, -1, -1, -1, -1, -1,
298 -1, -1, -1, -1, -1, -1, -1, -1,
299 -1, -1, -1, -1, -1, -1, -1, -1,
300 -1, -1, -1, -1, -1, -1, -1, -1,
301 -1, -1, -1, -1, -1, -1, -1, -1,
305 register_addr (int regno
, CORE_ADDR blockend
)
309 if (regno
< 0 || regno
>= NUM_REGS
)
310 error ("Invalid register number %d.", regno
);
312 if (u_offsets
[regno
] == -1)
315 addr
= (CORE_ADDR
) u_offsets
[regno
];
320 int ia64_cannot_fetch_register (regno
)
323 return regno
< 0 || regno
>= NUM_REGS
|| u_offsets
[regno
] == -1;
326 int ia64_cannot_store_register (regno
)
329 /* Rationale behind not permitting stores to bspstore...
331 The IA-64 architecture provides bspstore and bsp which refer
332 memory locations in the RSE's backing store. bspstore is the
333 next location which will be written when the RSE needs to write
334 to memory. bsp is the address at which r32 in the current frame
335 would be found if it were written to the backing store.
337 The IA-64 architecture provides read-only access to bsp and
338 read/write access to bspstore (but only when the RSE is in
339 the enforced lazy mode). It should be noted that stores
340 to bspstore also affect the value of bsp. Changing bspstore
341 does not affect the number of dirty entries between bspstore
342 and bsp, so changing bspstore by N words will also cause bsp
343 to be changed by (roughly) N as well. (It could be N-1 or N+1
344 depending upon where the NaT collection bits fall.)
346 OTOH, the Linux kernel provides read/write access to bsp (and
347 currently read/write access to bspstore as well). But it
348 is definitely the case that if you change one, the other
349 will change at the same time. It is more useful to gdb to
350 be able to change bsp. So in order to prevent strange and
351 undesirable things from happening when a dummy stack frame
352 is popped (after calling an inferior function), we allow
353 bspstore to be read, but not written. (Note that popping
354 a (generic) dummy stack frame causes all registers that
355 were previously read from the inferior process to be written
358 return regno
< 0 || regno
>= NUM_REGS
|| u_offsets
[regno
] == -1
359 || regno
== IA64_BSPSTORE_REGNUM
;
363 supply_gregset (gregset_t
*gregsetp
)
366 greg_t
*regp
= (greg_t
*) gregsetp
;
368 for (regi
= IA64_GR0_REGNUM
; regi
<= IA64_GR31_REGNUM
; regi
++)
370 regcache_raw_supply (current_regcache
, regi
,
371 (char *) (regp
+ (regi
- IA64_GR0_REGNUM
)));
374 /* FIXME: NAT collection bits are at index 32; gotta deal with these
377 regcache_raw_supply (current_regcache
, IA64_PR_REGNUM
, (char *) (regp
+ 33));
379 for (regi
= IA64_BR0_REGNUM
; regi
<= IA64_BR7_REGNUM
; regi
++)
381 regcache_raw_supply (current_regcache
, regi
,
382 (char *) (regp
+ 34 + (regi
- IA64_BR0_REGNUM
)));
385 regcache_raw_supply (current_regcache
, IA64_IP_REGNUM
,
386 (char *) (regp
+ 42));
387 regcache_raw_supply (current_regcache
, IA64_CFM_REGNUM
,
388 (char *) (regp
+ 43));
389 regcache_raw_supply (current_regcache
, IA64_PSR_REGNUM
,
390 (char *) (regp
+ 44));
391 regcache_raw_supply (current_regcache
, IA64_RSC_REGNUM
,
392 (char *) (regp
+ 45));
393 regcache_raw_supply (current_regcache
, IA64_BSP_REGNUM
,
394 (char *) (regp
+ 46));
395 regcache_raw_supply (current_regcache
, IA64_BSPSTORE_REGNUM
,
396 (char *) (regp
+ 47));
397 regcache_raw_supply (current_regcache
, IA64_RNAT_REGNUM
,
398 (char *) (regp
+ 48));
399 regcache_raw_supply (current_regcache
, IA64_CCV_REGNUM
,
400 (char *) (regp
+ 49));
401 regcache_raw_supply (current_regcache
, IA64_UNAT_REGNUM
,
402 (char *) (regp
+ 50));
403 regcache_raw_supply (current_regcache
, IA64_FPSR_REGNUM
,
404 (char *) (regp
+ 51));
405 regcache_raw_supply (current_regcache
, IA64_PFS_REGNUM
,
406 (char *) (regp
+ 52));
407 regcache_raw_supply (current_regcache
, IA64_LC_REGNUM
,
408 (char *) (regp
+ 53));
409 regcache_raw_supply (current_regcache
, IA64_EC_REGNUM
,
410 (char *) (regp
+ 54));
414 fill_gregset (gregset_t
*gregsetp
, int regno
)
417 greg_t
*regp
= (greg_t
*) gregsetp
;
419 #define COPY_REG(_idx_,_regi_) \
420 if ((regno == -1) || regno == _regi_) \
421 regcache_raw_collect (current_regcache, _regi_, regp + _idx_)
423 for (regi
= IA64_GR0_REGNUM
; regi
<= IA64_GR31_REGNUM
; regi
++)
425 COPY_REG (regi
- IA64_GR0_REGNUM
, regi
);
428 /* FIXME: NAT collection bits at index 32? */
430 COPY_REG (33, IA64_PR_REGNUM
);
432 for (regi
= IA64_BR0_REGNUM
; regi
<= IA64_BR7_REGNUM
; regi
++)
434 COPY_REG (34 + (regi
- IA64_BR0_REGNUM
), regi
);
437 COPY_REG (42, IA64_IP_REGNUM
);
438 COPY_REG (43, IA64_CFM_REGNUM
);
439 COPY_REG (44, IA64_PSR_REGNUM
);
440 COPY_REG (45, IA64_RSC_REGNUM
);
441 COPY_REG (46, IA64_BSP_REGNUM
);
442 COPY_REG (47, IA64_BSPSTORE_REGNUM
);
443 COPY_REG (48, IA64_RNAT_REGNUM
);
444 COPY_REG (49, IA64_CCV_REGNUM
);
445 COPY_REG (50, IA64_UNAT_REGNUM
);
446 COPY_REG (51, IA64_FPSR_REGNUM
);
447 COPY_REG (52, IA64_PFS_REGNUM
);
448 COPY_REG (53, IA64_LC_REGNUM
);
449 COPY_REG (54, IA64_EC_REGNUM
);
452 /* Given a pointer to a floating point register set in /proc format
453 (fpregset_t *), unpack the register contents and supply them as gdb's
454 idea of the current floating point register values. */
457 supply_fpregset (fpregset_t
*fpregsetp
)
462 for (regi
= IA64_FR0_REGNUM
; regi
<= IA64_FR127_REGNUM
; regi
++)
464 from
= (char *) &((*fpregsetp
)[regi
- IA64_FR0_REGNUM
]);
465 regcache_raw_supply (current_regcache
, regi
, from
);
469 /* Given a pointer to a floating point register set in /proc format
470 (fpregset_t *), update the register specified by REGNO from gdb's idea
471 of the current floating point register set. If REGNO is -1, update
475 fill_fpregset (fpregset_t
*fpregsetp
, int regno
)
479 for (regi
= IA64_FR0_REGNUM
; regi
<= IA64_FR127_REGNUM
; regi
++)
481 if ((regno
== -1) || (regno
== regi
))
482 regcache_raw_collect (current_regcache
, regi
,
483 &((*fpregsetp
)[regi
- IA64_FR0_REGNUM
]));
487 #define IA64_PSR_DB (1UL << 24)
488 #define IA64_PSR_DD (1UL << 39)
491 enable_watchpoints_in_psr (ptid_t ptid
)
495 psr
= read_register_pid (IA64_PSR_REGNUM
, ptid
);
496 if (!(psr
& IA64_PSR_DB
))
498 psr
|= IA64_PSR_DB
; /* Set the db bit - this enables hardware
499 watchpoints and breakpoints. */
500 write_register_pid (IA64_PSR_REGNUM
, psr
, ptid
);
505 fetch_debug_register (ptid_t ptid
, int idx
)
514 val
= ptrace (PT_READ_U
, tid
, (PTRACE_TYPE_ARG3
) (PT_DBR
+ 8 * idx
), 0);
520 store_debug_register (ptid_t ptid
, int idx
, long val
)
528 (void) ptrace (PT_WRITE_U
, tid
, (PTRACE_TYPE_ARG3
) (PT_DBR
+ 8 * idx
), val
);
532 fetch_debug_register_pair (ptid_t ptid
, int idx
, long *dbr_addr
, long *dbr_mask
)
535 *dbr_addr
= fetch_debug_register (ptid
, 2 * idx
);
537 *dbr_mask
= fetch_debug_register (ptid
, 2 * idx
+ 1);
541 store_debug_register_pair (ptid_t ptid
, int idx
, long *dbr_addr
, long *dbr_mask
)
544 store_debug_register (ptid
, 2 * idx
, *dbr_addr
);
546 store_debug_register (ptid
, 2 * idx
+ 1, *dbr_mask
);
550 is_power_of_2 (int val
)
555 for (i
= 0; i
< 8 * sizeof (val
); i
++)
559 return onecount
<= 1;
563 ia64_linux_insert_watchpoint (ptid_t ptid
, CORE_ADDR addr
, int len
, int rw
)
566 long dbr_addr
, dbr_mask
;
567 int max_watchpoints
= 4;
569 if (len
<= 0 || !is_power_of_2 (len
))
572 for (idx
= 0; idx
< max_watchpoints
; idx
++)
574 fetch_debug_register_pair (ptid
, idx
, NULL
, &dbr_mask
);
575 if ((dbr_mask
& (0x3UL
<< 62)) == 0)
577 /* Exit loop if both r and w bits clear */
582 if (idx
== max_watchpoints
)
585 dbr_addr
= (long) addr
;
586 dbr_mask
= (~(len
- 1) & 0x00ffffffffffffffL
); /* construct mask to match */
587 dbr_mask
|= 0x0800000000000000L
; /* Only match privilege level 3 */
591 dbr_mask
|= (1L << 62); /* Set w bit */
594 dbr_mask
|= (1L << 63); /* Set r bit */
597 dbr_mask
|= (3L << 62); /* Set both r and w bits */
603 store_debug_register_pair (ptid
, idx
, &dbr_addr
, &dbr_mask
);
604 enable_watchpoints_in_psr (ptid
);
610 ia64_linux_remove_watchpoint (ptid_t ptid
, CORE_ADDR addr
, int len
)
613 long dbr_addr
, dbr_mask
;
614 int max_watchpoints
= 4;
616 if (len
<= 0 || !is_power_of_2 (len
))
619 for (idx
= 0; idx
< max_watchpoints
; idx
++)
621 fetch_debug_register_pair (ptid
, idx
, &dbr_addr
, &dbr_mask
);
622 if ((dbr_mask
& (0x3UL
<< 62)) && addr
== (CORE_ADDR
) dbr_addr
)
626 store_debug_register_pair (ptid
, idx
, &dbr_addr
, &dbr_mask
);
634 ia64_linux_stopped_data_address (CORE_ADDR
*addr_p
)
638 struct siginfo siginfo
;
639 ptid_t ptid
= inferior_ptid
;
646 ptrace (PTRACE_GETSIGINFO
, tid
, (PTRACE_TYPE_ARG3
) 0, &siginfo
);
648 if (errno
!= 0 || siginfo
.si_signo
!= SIGTRAP
||
649 (siginfo
.si_code
& 0xffff) != 0x0004 /* TRAP_HWBKPT */)
652 psr
= read_register_pid (IA64_PSR_REGNUM
, ptid
);
653 psr
|= IA64_PSR_DD
; /* Set the dd bit - this will disable the watchpoint
654 for the next instruction */
655 write_register_pid (IA64_PSR_REGNUM
, psr
, ptid
);
657 *addr_p
= (CORE_ADDR
)siginfo
.si_addr
;
662 ia64_linux_stopped_by_watchpoint (void)
665 return ia64_linux_stopped_data_address (&addr
);
669 ia64_linux_xfer_unwind_table (struct target_ops
*ops
,
670 enum target_object object
,
672 void *readbuf
, const void *writebuf
,
673 ULONGEST offset
, LONGEST len
)
675 return syscall (__NR_getunwind
, readbuf
, len
);
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