1 /* Functions specific to running gdb native on IA-64 running Linux.
2 Copyright 1999, 2000, 2001 Free Software Foundation, Inc.
4 This file is part of GDB.
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
28 #include <sys/ptrace.h>
35 #include <asm/ptrace_offsets.h>
36 #include <sys/procfs.h>
38 /* Prototypes for supply_gregset etc. */
41 /* These must match the order of the register names.
43 Some sort of lookup table is needed because the offsets associated
44 with the registers are all over the board. */
46 static int u_offsets
[] =
48 /* general registers */
49 -1, /* gr0 not available; i.e, it's always zero */
81 /* gr32 through gr127 not directly available via the ptrace interface */
82 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
83 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
84 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
85 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
86 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
87 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
88 /* Floating point registers */
89 -1, -1, /* f0 and f1 not available (f0 is +0.0 and f1 is +1.0) */
216 /* predicate registers - we don't fetch these individually */
217 -1, -1, -1, -1, -1, -1, -1, -1,
218 -1, -1, -1, -1, -1, -1, -1, -1,
219 -1, -1, -1, -1, -1, -1, -1, -1,
220 -1, -1, -1, -1, -1, -1, -1, -1,
221 -1, -1, -1, -1, -1, -1, -1, -1,
222 -1, -1, -1, -1, -1, -1, -1, -1,
223 -1, -1, -1, -1, -1, -1, -1, -1,
224 -1, -1, -1, -1, -1, -1, -1, -1,
225 /* branch registers */
234 /* virtual frame pointer and virtual return address pointer */
236 /* other registers */
239 PT_CR_IPSR
, /* psr */
241 /* kernel registers not visible via ptrace interface (?) */
242 -1, -1, -1, -1, -1, -1, -1, -1,
244 -1, -1, -1, -1, -1, -1, -1, -1,
250 -1, /* Not available: FCR, IA32 floating control register */
252 -1, /* Not available: EFLAG */
253 -1, /* Not available: CSD */
254 -1, /* Not available: SSD */
255 -1, /* Not available: CFLG */
256 -1, /* Not available: FSR */
257 -1, /* Not available: FIR */
258 -1, /* Not available: FDR */
266 -1, /* Not available: ITC */
267 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
268 -1, -1, -1, -1, -1, -1, -1, -1, -1,
271 -1, /* Not available: EC, the Epilog Count register */
272 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
273 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
274 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
275 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
276 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
277 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
279 /* nat bits - not fetched directly; instead we obtain these bits from
280 either rnat or unat or from memory. */
281 -1, -1, -1, -1, -1, -1, -1, -1,
282 -1, -1, -1, -1, -1, -1, -1, -1,
283 -1, -1, -1, -1, -1, -1, -1, -1,
284 -1, -1, -1, -1, -1, -1, -1, -1,
285 -1, -1, -1, -1, -1, -1, -1, -1,
286 -1, -1, -1, -1, -1, -1, -1, -1,
287 -1, -1, -1, -1, -1, -1, -1, -1,
288 -1, -1, -1, -1, -1, -1, -1, -1,
289 -1, -1, -1, -1, -1, -1, -1, -1,
290 -1, -1, -1, -1, -1, -1, -1, -1,
291 -1, -1, -1, -1, -1, -1, -1, -1,
292 -1, -1, -1, -1, -1, -1, -1, -1,
293 -1, -1, -1, -1, -1, -1, -1, -1,
294 -1, -1, -1, -1, -1, -1, -1, -1,
295 -1, -1, -1, -1, -1, -1, -1, -1,
296 -1, -1, -1, -1, -1, -1, -1, -1,
300 register_addr (int regno
, CORE_ADDR blockend
)
304 if (regno
< 0 || regno
>= NUM_REGS
)
305 error ("Invalid register number %d.", regno
);
307 if (u_offsets
[regno
] == -1)
310 addr
= (CORE_ADDR
) u_offsets
[regno
];
315 int ia64_cannot_fetch_register (regno
)
318 return regno
< 0 || regno
>= NUM_REGS
|| u_offsets
[regno
] == -1;
321 int ia64_cannot_store_register (regno
)
324 /* Rationale behind not permitting stores to bspstore...
326 The IA-64 architecture provides bspstore and bsp which refer
327 memory locations in the RSE's backing store. bspstore is the
328 next location which will be written when the RSE needs to write
329 to memory. bsp is the address at which r32 in the current frame
330 would be found if it were written to the backing store.
332 The IA-64 architecture provides read-only access to bsp and
333 read/write access to bspstore (but only when the RSE is in
334 the enforced lazy mode). It should be noted that stores
335 to bspstore also affect the value of bsp. Changing bspstore
336 does not affect the number of dirty entries between bspstore
337 and bsp, so changing bspstore by N words will also cause bsp
338 to be changed by (roughly) N as well. (It could be N-1 or N+1
339 depending upon where the NaT collection bits fall.)
341 OTOH, the linux kernel provides read/write access to bsp (and
342 currently read/write access to bspstore as well). But it
343 is definitely the case that if you change one, the other
344 will change at the same time. It is more useful to gdb to
345 be able to change bsp. So in order to prevent strange and
346 undesirable things from happening when a dummy stack frame
347 is popped (after calling an inferior function), we allow
348 bspstore to be read, but not written. (Note that popping
349 a (generic) dummy stack frame causes all registers that
350 were previously read from the inferior process to be written
353 return regno
< 0 || regno
>= NUM_REGS
|| u_offsets
[regno
] == -1
354 || regno
== IA64_BSPSTORE_REGNUM
;
358 supply_gregset (gregset_t
*gregsetp
)
361 greg_t
*regp
= (greg_t
*) gregsetp
;
363 for (regi
= IA64_GR0_REGNUM
; regi
<= IA64_GR31_REGNUM
; regi
++)
365 supply_register (regi
, (char *) (regp
+ (regi
- IA64_GR0_REGNUM
)));
368 /* FIXME: NAT collection bits are at index 32; gotta deal with these
371 supply_register (IA64_PR_REGNUM
, (char *) (regp
+ 33));
373 for (regi
= IA64_BR0_REGNUM
; regi
<= IA64_BR7_REGNUM
; regi
++)
375 supply_register (regi
, (char *) (regp
+ 34 + (regi
- IA64_BR0_REGNUM
)));
378 supply_register (IA64_IP_REGNUM
, (char *) (regp
+ 42));
379 supply_register (IA64_CFM_REGNUM
, (char *) (regp
+ 43));
380 supply_register (IA64_PSR_REGNUM
, (char *) (regp
+ 44));
381 supply_register (IA64_RSC_REGNUM
, (char *) (regp
+ 45));
382 supply_register (IA64_BSP_REGNUM
, (char *) (regp
+ 46));
383 supply_register (IA64_BSPSTORE_REGNUM
, (char *) (regp
+ 47));
384 supply_register (IA64_RNAT_REGNUM
, (char *) (regp
+ 48));
385 supply_register (IA64_CCV_REGNUM
, (char *) (regp
+ 49));
386 supply_register (IA64_UNAT_REGNUM
, (char *) (regp
+ 50));
387 supply_register (IA64_FPSR_REGNUM
, (char *) (regp
+ 51));
388 supply_register (IA64_PFS_REGNUM
, (char *) (regp
+ 52));
389 supply_register (IA64_LC_REGNUM
, (char *) (regp
+ 53));
390 supply_register (IA64_EC_REGNUM
, (char *) (regp
+ 54));
394 fill_gregset (gregset_t
*gregsetp
, int regno
)
397 greg_t
*regp
= (greg_t
*) gregsetp
;
399 #define COPY_REG(_idx_,_regi_) \
400 if ((regno == -1) || regno == _regi_) \
401 memcpy (regp + _idx_, ®isters[REGISTER_BYTE (_regi_)], \
402 REGISTER_RAW_SIZE (_regi_))
404 for (regi
= IA64_GR0_REGNUM
; regi
<= IA64_GR31_REGNUM
; regi
++)
406 COPY_REG (regi
- IA64_GR0_REGNUM
, regi
);
409 /* FIXME: NAT collection bits at index 32? */
411 COPY_REG (33, IA64_PR_REGNUM
);
413 for (regi
= IA64_BR0_REGNUM
; regi
<= IA64_BR7_REGNUM
; regi
++)
415 COPY_REG (34 + (regi
- IA64_BR0_REGNUM
), regi
);
418 COPY_REG (42, IA64_IP_REGNUM
);
419 COPY_REG (43, IA64_CFM_REGNUM
);
420 COPY_REG (44, IA64_PSR_REGNUM
);
421 COPY_REG (45, IA64_RSC_REGNUM
);
422 COPY_REG (46, IA64_BSP_REGNUM
);
423 COPY_REG (47, IA64_BSPSTORE_REGNUM
);
424 COPY_REG (48, IA64_RNAT_REGNUM
);
425 COPY_REG (49, IA64_CCV_REGNUM
);
426 COPY_REG (50, IA64_UNAT_REGNUM
);
427 COPY_REG (51, IA64_FPSR_REGNUM
);
428 COPY_REG (52, IA64_PFS_REGNUM
);
429 COPY_REG (53, IA64_LC_REGNUM
);
430 COPY_REG (54, IA64_EC_REGNUM
);
433 /* Given a pointer to a floating point register set in /proc format
434 (fpregset_t *), unpack the register contents and supply them as gdb's
435 idea of the current floating point register values. */
438 supply_fpregset (fpregset_t
*fpregsetp
)
443 for (regi
= IA64_FR0_REGNUM
; regi
<= IA64_FR127_REGNUM
; regi
++)
445 from
= (char *) &((*fpregsetp
)[regi
- IA64_FR0_REGNUM
]);
446 supply_register (regi
, from
);
450 /* Given a pointer to a floating point register set in /proc format
451 (fpregset_t *), update the register specified by REGNO from gdb's idea
452 of the current floating point register set. If REGNO is -1, update
456 fill_fpregset (fpregset_t
*fpregsetp
, int regno
)
462 for (regi
= IA64_FR0_REGNUM
; regi
<= IA64_FR127_REGNUM
; regi
++)
464 if ((regno
== -1) || (regno
== regi
))
466 from
= (char *) ®isters
[REGISTER_BYTE (regi
)];
467 to
= (char *) &((*fpregsetp
)[regi
- IA64_FR0_REGNUM
]);
468 memcpy (to
, from
, REGISTER_RAW_SIZE (regi
));
473 #define IA64_PSR_DB (1UL << 24)
474 #define IA64_PSR_DD (1UL << 39)
477 enable_watchpoints_in_psr (ptid_t ptid
)
481 psr
= read_register_pid (IA64_PSR_REGNUM
, ptid
);
482 if (!(psr
& IA64_PSR_DB
))
484 psr
|= IA64_PSR_DB
; /* Set the db bit - this enables hardware
485 watchpoints and breakpoints. */
486 write_register_pid (IA64_PSR_REGNUM
, psr
, ptid
);
491 fetch_debug_register (ptid_t ptid
, int idx
)
500 val
= ptrace (PT_READ_U
, tid
, (PTRACE_ARG3_TYPE
) (PT_DBR
+ 8 * idx
), 0);
506 store_debug_register (ptid_t ptid
, int idx
, long val
)
514 (void) ptrace (PT_WRITE_U
, tid
, (PTRACE_ARG3_TYPE
) (PT_DBR
+ 8 * idx
), val
);
518 fetch_debug_register_pair (ptid_t ptid
, int idx
, long *dbr_addr
, long *dbr_mask
)
521 *dbr_addr
= fetch_debug_register (ptid
, 2 * idx
);
523 *dbr_mask
= fetch_debug_register (ptid
, 2 * idx
+ 1);
527 store_debug_register_pair (ptid_t ptid
, int idx
, long *dbr_addr
, long *dbr_mask
)
530 store_debug_register (ptid
, 2 * idx
, *dbr_addr
);
532 store_debug_register (ptid
, 2 * idx
+ 1, *dbr_mask
);
536 is_power_of_2 (int val
)
541 for (i
= 0; i
< 8 * sizeof (val
); i
++)
545 return onecount
<= 1;
549 ia64_linux_insert_watchpoint (ptid_t ptid
, CORE_ADDR addr
, int len
, int rw
)
552 long dbr_addr
, dbr_mask
;
553 int max_watchpoints
= 4;
555 if (len
<= 0 || !is_power_of_2 (len
))
558 for (idx
= 0; idx
< max_watchpoints
; idx
++)
560 fetch_debug_register_pair (ptid
, idx
, NULL
, &dbr_mask
);
561 if ((dbr_mask
& (0x3UL
<< 62)) == 0)
563 /* Exit loop if both r and w bits clear */
568 if (idx
== max_watchpoints
)
571 dbr_addr
= (long) addr
;
572 dbr_mask
= (~(len
- 1) & 0x00ffffffffffffffL
); /* construct mask to match */
573 dbr_mask
|= 0x0800000000000000L
; /* Only match privilege level 3 */
577 dbr_mask
|= (1L << 62); /* Set w bit */
580 dbr_mask
|= (1L << 63); /* Set r bit */
583 dbr_mask
|= (3L << 62); /* Set both r and w bits */
589 store_debug_register_pair (ptid
, idx
, &dbr_addr
, &dbr_mask
);
590 enable_watchpoints_in_psr (ptid
);
596 ia64_linux_remove_watchpoint (ptid_t ptid
, CORE_ADDR addr
, int len
)
599 long dbr_addr
, dbr_mask
;
600 int max_watchpoints
= 4;
602 if (len
<= 0 || !is_power_of_2 (len
))
605 for (idx
= 0; idx
< max_watchpoints
; idx
++)
607 fetch_debug_register_pair (ptid
, idx
, &dbr_addr
, &dbr_mask
);
608 if ((dbr_mask
& (0x3UL
<< 62)) && addr
== (CORE_ADDR
) dbr_addr
)
612 store_debug_register_pair (ptid
, idx
, &dbr_addr
, &dbr_mask
);
620 ia64_linux_stopped_by_watchpoint (ptid_t ptid
)
624 struct siginfo siginfo
;
631 ptrace (PTRACE_GETSIGINFO
, tid
, (PTRACE_ARG3_TYPE
) 0, &siginfo
);
633 if (errno
!= 0 || (siginfo
.si_code
& 0xffff) != 0x0004 /* TRAP_HWBKPT */)
636 psr
= read_register_pid (IA64_PSR_REGNUM
, ptid
);
637 psr
|= IA64_PSR_DD
; /* Set the dd bit - this will disable the watchpoint
638 for the next instruction */
639 write_register_pid (IA64_PSR_REGNUM
, psr
, ptid
);
641 return (CORE_ADDR
) siginfo
.si_addr
;
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