1 /* Functions specific to running gdb native on IA-64 running
4 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
5 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 51 Franklin Street, Fifth Floor,
22 Boston, MA 02110-1301, USA. */
25 #include "gdb_string.h"
30 #include "ia64-tdep.h"
31 #include "linux-nat.h"
34 #include <sys/ptrace.h>
39 #include <sys/syscall.h>
42 #include <asm/ptrace_offsets.h>
43 #include <sys/procfs.h>
45 /* Prototypes for supply_gregset etc. */
48 /* These must match the order of the register names.
50 Some sort of lookup table is needed because the offsets associated
51 with the registers are all over the board. */
53 static int u_offsets
[] =
55 /* general registers */
56 -1, /* gr0 not available; i.e, it's always zero */
88 /* gr32 through gr127 not directly available via the ptrace interface */
89 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
90 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
91 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
92 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
93 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
94 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
95 /* Floating point registers */
96 -1, -1, /* f0 and f1 not available (f0 is +0.0 and f1 is +1.0) */
223 /* predicate registers - we don't fetch these individually */
224 -1, -1, -1, -1, -1, -1, -1, -1,
225 -1, -1, -1, -1, -1, -1, -1, -1,
226 -1, -1, -1, -1, -1, -1, -1, -1,
227 -1, -1, -1, -1, -1, -1, -1, -1,
228 -1, -1, -1, -1, -1, -1, -1, -1,
229 -1, -1, -1, -1, -1, -1, -1, -1,
230 -1, -1, -1, -1, -1, -1, -1, -1,
231 -1, -1, -1, -1, -1, -1, -1, -1,
232 /* branch registers */
241 /* virtual frame pointer and virtual return address pointer */
243 /* other registers */
246 PT_CR_IPSR
, /* psr */
248 /* kernel registers not visible via ptrace interface (?) */
249 -1, -1, -1, -1, -1, -1, -1, -1,
251 -1, -1, -1, -1, -1, -1, -1, -1,
257 -1, /* Not available: FCR, IA32 floating control register */
259 -1, /* Not available: EFLAG */
260 -1, /* Not available: CSD */
261 -1, /* Not available: SSD */
262 -1, /* Not available: CFLG */
263 -1, /* Not available: FSR */
264 -1, /* Not available: FIR */
265 -1, /* Not available: FDR */
273 -1, /* Not available: ITC */
274 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
275 -1, -1, -1, -1, -1, -1, -1, -1, -1,
278 -1, /* Not available: EC, the Epilog Count register */
279 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
280 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
281 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
282 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
283 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
284 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
286 /* nat bits - not fetched directly; instead we obtain these bits from
287 either rnat or unat or from memory. */
288 -1, -1, -1, -1, -1, -1, -1, -1,
289 -1, -1, -1, -1, -1, -1, -1, -1,
290 -1, -1, -1, -1, -1, -1, -1, -1,
291 -1, -1, -1, -1, -1, -1, -1, -1,
292 -1, -1, -1, -1, -1, -1, -1, -1,
293 -1, -1, -1, -1, -1, -1, -1, -1,
294 -1, -1, -1, -1, -1, -1, -1, -1,
295 -1, -1, -1, -1, -1, -1, -1, -1,
296 -1, -1, -1, -1, -1, -1, -1, -1,
297 -1, -1, -1, -1, -1, -1, -1, -1,
298 -1, -1, -1, -1, -1, -1, -1, -1,
299 -1, -1, -1, -1, -1, -1, -1, -1,
300 -1, -1, -1, -1, -1, -1, -1, -1,
301 -1, -1, -1, -1, -1, -1, -1, -1,
302 -1, -1, -1, -1, -1, -1, -1, -1,
303 -1, -1, -1, -1, -1, -1, -1, -1,
307 ia64_register_addr (int regno
)
311 if (regno
< 0 || regno
>= gdbarch_num_regs (current_gdbarch
))
312 error (_("Invalid register number %d."), regno
);
314 if (u_offsets
[regno
] == -1)
317 addr
= (CORE_ADDR
) u_offsets
[regno
];
323 ia64_cannot_fetch_register (int regno
)
326 || regno
>= gdbarch_num_regs (current_gdbarch
)
327 || u_offsets
[regno
] == -1;
331 ia64_cannot_store_register (int regno
)
333 /* Rationale behind not permitting stores to bspstore...
335 The IA-64 architecture provides bspstore and bsp which refer
336 memory locations in the RSE's backing store. bspstore is the
337 next location which will be written when the RSE needs to write
338 to memory. bsp is the address at which r32 in the current frame
339 would be found if it were written to the backing store.
341 The IA-64 architecture provides read-only access to bsp and
342 read/write access to bspstore (but only when the RSE is in
343 the enforced lazy mode). It should be noted that stores
344 to bspstore also affect the value of bsp. Changing bspstore
345 does not affect the number of dirty entries between bspstore
346 and bsp, so changing bspstore by N words will also cause bsp
347 to be changed by (roughly) N as well. (It could be N-1 or N+1
348 depending upon where the NaT collection bits fall.)
350 OTOH, the Linux kernel provides read/write access to bsp (and
351 currently read/write access to bspstore as well). But it
352 is definitely the case that if you change one, the other
353 will change at the same time. It is more useful to gdb to
354 be able to change bsp. So in order to prevent strange and
355 undesirable things from happening when a dummy stack frame
356 is popped (after calling an inferior function), we allow
357 bspstore to be read, but not written. (Note that popping
358 a (generic) dummy stack frame causes all registers that
359 were previously read from the inferior process to be written
363 || regno
>= gdbarch_num_regs (current_gdbarch
)
364 || u_offsets
[regno
] == -1
365 || regno
== IA64_BSPSTORE_REGNUM
;
369 supply_gregset (struct regcache
*regcache
, const gregset_t
*gregsetp
)
372 const greg_t
*regp
= (const greg_t
*) gregsetp
;
374 for (regi
= IA64_GR0_REGNUM
; regi
<= IA64_GR31_REGNUM
; regi
++)
376 regcache_raw_supply (regcache
, regi
, regp
+ (regi
- IA64_GR0_REGNUM
));
379 /* FIXME: NAT collection bits are at index 32; gotta deal with these
382 regcache_raw_supply (regcache
, IA64_PR_REGNUM
, regp
+ 33);
384 for (regi
= IA64_BR0_REGNUM
; regi
<= IA64_BR7_REGNUM
; regi
++)
386 regcache_raw_supply (regcache
, regi
,
387 regp
+ 34 + (regi
- IA64_BR0_REGNUM
));
390 regcache_raw_supply (regcache
, IA64_IP_REGNUM
, regp
+ 42);
391 regcache_raw_supply (regcache
, IA64_CFM_REGNUM
, regp
+ 43);
392 regcache_raw_supply (regcache
, IA64_PSR_REGNUM
, regp
+ 44);
393 regcache_raw_supply (regcache
, IA64_RSC_REGNUM
, regp
+ 45);
394 regcache_raw_supply (regcache
, IA64_BSP_REGNUM
, regp
+ 46);
395 regcache_raw_supply (regcache
, IA64_BSPSTORE_REGNUM
, regp
+ 47);
396 regcache_raw_supply (regcache
, IA64_RNAT_REGNUM
, regp
+ 48);
397 regcache_raw_supply (regcache
, IA64_CCV_REGNUM
, regp
+ 49);
398 regcache_raw_supply (regcache
, IA64_UNAT_REGNUM
, regp
+ 50);
399 regcache_raw_supply (regcache
, IA64_FPSR_REGNUM
, regp
+ 51);
400 regcache_raw_supply (regcache
, IA64_PFS_REGNUM
, regp
+ 52);
401 regcache_raw_supply (regcache
, IA64_LC_REGNUM
, regp
+ 53);
402 regcache_raw_supply (regcache
, IA64_EC_REGNUM
, regp
+ 54);
406 fill_gregset (const struct regcache
*regcache
, gregset_t
*gregsetp
, int regno
)
409 greg_t
*regp
= (greg_t
*) gregsetp
;
411 #define COPY_REG(_idx_,_regi_) \
412 if ((regno == -1) || regno == _regi_) \
413 regcache_raw_collect (regcache, _regi_, regp + _idx_)
415 for (regi
= IA64_GR0_REGNUM
; regi
<= IA64_GR31_REGNUM
; regi
++)
417 COPY_REG (regi
- IA64_GR0_REGNUM
, regi
);
420 /* FIXME: NAT collection bits at index 32? */
422 COPY_REG (33, IA64_PR_REGNUM
);
424 for (regi
= IA64_BR0_REGNUM
; regi
<= IA64_BR7_REGNUM
; regi
++)
426 COPY_REG (34 + (regi
- IA64_BR0_REGNUM
), regi
);
429 COPY_REG (42, IA64_IP_REGNUM
);
430 COPY_REG (43, IA64_CFM_REGNUM
);
431 COPY_REG (44, IA64_PSR_REGNUM
);
432 COPY_REG (45, IA64_RSC_REGNUM
);
433 COPY_REG (46, IA64_BSP_REGNUM
);
434 COPY_REG (47, IA64_BSPSTORE_REGNUM
);
435 COPY_REG (48, IA64_RNAT_REGNUM
);
436 COPY_REG (49, IA64_CCV_REGNUM
);
437 COPY_REG (50, IA64_UNAT_REGNUM
);
438 COPY_REG (51, IA64_FPSR_REGNUM
);
439 COPY_REG (52, IA64_PFS_REGNUM
);
440 COPY_REG (53, IA64_LC_REGNUM
);
441 COPY_REG (54, IA64_EC_REGNUM
);
444 /* Given a pointer to a floating point register set in /proc format
445 (fpregset_t *), unpack the register contents and supply them as gdb's
446 idea of the current floating point register values. */
449 supply_fpregset (struct regcache
*regcache
, const fpregset_t
*fpregsetp
)
454 for (regi
= IA64_FR0_REGNUM
; regi
<= IA64_FR127_REGNUM
; regi
++)
456 from
= (const char *) &((*fpregsetp
)[regi
- IA64_FR0_REGNUM
]);
457 regcache_raw_supply (regcache
, regi
, from
);
461 /* Given a pointer to a floating point register set in /proc format
462 (fpregset_t *), update the register specified by REGNO from gdb's idea
463 of the current floating point register set. If REGNO is -1, update
467 fill_fpregset (const struct regcache
*regcache
,
468 fpregset_t
*fpregsetp
, int regno
)
472 for (regi
= IA64_FR0_REGNUM
; regi
<= IA64_FR127_REGNUM
; regi
++)
474 if ((regno
== -1) || (regno
== regi
))
475 regcache_raw_collect (regcache
, regi
,
476 &((*fpregsetp
)[regi
- IA64_FR0_REGNUM
]));
480 #define IA64_PSR_DB (1UL << 24)
481 #define IA64_PSR_DD (1UL << 39)
484 enable_watchpoints_in_psr (struct regcache
*regcache
)
488 regcache_cooked_read_unsigned (regcache
, IA64_PSR_REGNUM
, &psr
);
489 if (!(psr
& IA64_PSR_DB
))
491 psr
|= IA64_PSR_DB
; /* Set the db bit - this enables hardware
492 watchpoints and breakpoints. */
493 regcache_cooked_write_unsigned (regcache
, IA64_PSR_REGNUM
, psr
);
498 fetch_debug_register (ptid_t ptid
, int idx
)
507 val
= ptrace (PT_READ_U
, tid
, (PTRACE_TYPE_ARG3
) (PT_DBR
+ 8 * idx
), 0);
513 store_debug_register (ptid_t ptid
, int idx
, long val
)
521 (void) ptrace (PT_WRITE_U
, tid
, (PTRACE_TYPE_ARG3
) (PT_DBR
+ 8 * idx
), val
);
525 fetch_debug_register_pair (ptid_t ptid
, int idx
, long *dbr_addr
, long *dbr_mask
)
528 *dbr_addr
= fetch_debug_register (ptid
, 2 * idx
);
530 *dbr_mask
= fetch_debug_register (ptid
, 2 * idx
+ 1);
534 store_debug_register_pair (ptid_t ptid
, int idx
, long *dbr_addr
, long *dbr_mask
)
537 store_debug_register (ptid
, 2 * idx
, *dbr_addr
);
539 store_debug_register (ptid
, 2 * idx
+ 1, *dbr_mask
);
543 is_power_of_2 (int val
)
548 for (i
= 0; i
< 8 * sizeof (val
); i
++)
552 return onecount
<= 1;
556 ia64_linux_insert_watchpoint (CORE_ADDR addr
, int len
, int rw
)
558 ptid_t ptid
= inferior_ptid
;
560 long dbr_addr
, dbr_mask
;
561 int max_watchpoints
= 4;
563 if (len
<= 0 || !is_power_of_2 (len
))
566 for (idx
= 0; idx
< max_watchpoints
; idx
++)
568 fetch_debug_register_pair (ptid
, idx
, NULL
, &dbr_mask
);
569 if ((dbr_mask
& (0x3UL
<< 62)) == 0)
571 /* Exit loop if both r and w bits clear */
576 if (idx
== max_watchpoints
)
579 dbr_addr
= (long) addr
;
580 dbr_mask
= (~(len
- 1) & 0x00ffffffffffffffL
); /* construct mask to match */
581 dbr_mask
|= 0x0800000000000000L
; /* Only match privilege level 3 */
585 dbr_mask
|= (1L << 62); /* Set w bit */
588 dbr_mask
|= (1L << 63); /* Set r bit */
591 dbr_mask
|= (3L << 62); /* Set both r and w bits */
597 store_debug_register_pair (ptid
, idx
, &dbr_addr
, &dbr_mask
);
598 enable_watchpoints_in_psr (current_regcache
);
604 ia64_linux_remove_watchpoint (CORE_ADDR addr
, int len
, int type
)
606 ptid_t ptid
= inferior_ptid
;
608 long dbr_addr
, dbr_mask
;
609 int max_watchpoints
= 4;
611 if (len
<= 0 || !is_power_of_2 (len
))
614 for (idx
= 0; idx
< max_watchpoints
; idx
++)
616 fetch_debug_register_pair (ptid
, idx
, &dbr_addr
, &dbr_mask
);
617 if ((dbr_mask
& (0x3UL
<< 62)) && addr
== (CORE_ADDR
) dbr_addr
)
621 store_debug_register_pair (ptid
, idx
, &dbr_addr
, &dbr_mask
);
629 ia64_linux_stopped_data_address (struct target_ops
*ops
, CORE_ADDR
*addr_p
)
633 struct siginfo siginfo
;
634 ptid_t ptid
= inferior_ptid
;
635 struct regcache
*regcache
= current_regcache
;
642 ptrace (PTRACE_GETSIGINFO
, tid
, (PTRACE_TYPE_ARG3
) 0, &siginfo
);
644 if (errno
!= 0 || siginfo
.si_signo
!= SIGTRAP
||
645 (siginfo
.si_code
& 0xffff) != 0x0004 /* TRAP_HWBKPT */)
648 regcache_cooked_read_unsigned (regcache
, IA64_PSR_REGNUM
, &psr
);
649 psr
|= IA64_PSR_DD
; /* Set the dd bit - this will disable the watchpoint
650 for the next instruction */
651 regcache_cooked_write_unsigned (regcache
, IA64_PSR_REGNUM
, psr
);
653 *addr_p
= (CORE_ADDR
)siginfo
.si_addr
;
658 ia64_linux_stopped_by_watchpoint (void)
661 return ia64_linux_stopped_data_address (¤t_target
, &addr
);
665 ia64_linux_can_use_hw_breakpoint (int type
, int cnt
, int othertype
)
671 /* Fetch register REGNUM from the inferior. */
674 ia64_linux_fetch_register (struct regcache
*regcache
, int regnum
)
678 PTRACE_TYPE_RET
*buf
;
681 if (ia64_cannot_fetch_register (regnum
))
683 regcache_raw_supply (regcache
, regnum
, NULL
);
687 /* Cater for systems like GNU/Linux, that implement threads as
688 separate processes. */
689 pid
= ptid_get_lwp (inferior_ptid
);
691 pid
= ptid_get_pid (inferior_ptid
);
693 /* This isn't really an address, but ptrace thinks of it as one. */
694 addr
= ia64_register_addr (regnum
);
695 size
= register_size (current_gdbarch
, regnum
);
697 gdb_assert ((size
% sizeof (PTRACE_TYPE_RET
)) == 0);
700 /* Read the register contents from the inferior a chunk at a time. */
701 for (i
= 0; i
< size
/ sizeof (PTRACE_TYPE_RET
); i
++)
704 buf
[i
] = ptrace (PT_READ_U
, pid
, (PTRACE_TYPE_ARG3
)addr
, 0);
706 error (_("Couldn't read register %s (#%d): %s."),
707 REGISTER_NAME (regnum
), regnum
, safe_strerror (errno
));
709 addr
+= sizeof (PTRACE_TYPE_RET
);
711 regcache_raw_supply (regcache
, regnum
, buf
);
714 /* Fetch register REGNUM from the inferior. If REGNUM is -1, do this
715 for all registers. */
718 ia64_linux_fetch_registers (struct regcache
*regcache
, int regnum
)
721 for (regnum
= 0; regnum
< gdbarch_num_regs (current_gdbarch
); regnum
++)
722 ia64_linux_fetch_register (regcache
, regnum
);
724 ia64_linux_fetch_register (regcache
, regnum
);
727 /* Store register REGNUM into the inferior. */
730 ia64_linux_store_register (const struct regcache
*regcache
, int regnum
)
734 PTRACE_TYPE_RET
*buf
;
737 if (ia64_cannot_store_register (regnum
))
740 /* Cater for systems like GNU/Linux, that implement threads as
741 separate processes. */
742 pid
= ptid_get_lwp (inferior_ptid
);
744 pid
= ptid_get_pid (inferior_ptid
);
746 /* This isn't really an address, but ptrace thinks of it as one. */
747 addr
= ia64_register_addr (regnum
);
748 size
= register_size (current_gdbarch
, regnum
);
750 gdb_assert ((size
% sizeof (PTRACE_TYPE_RET
)) == 0);
753 /* Write the register contents into the inferior a chunk at a time. */
754 regcache_raw_collect (regcache
, regnum
, buf
);
755 for (i
= 0; i
< size
/ sizeof (PTRACE_TYPE_RET
); i
++)
758 ptrace (PT_WRITE_U
, pid
, (PTRACE_TYPE_ARG3
)addr
, buf
[i
]);
760 error (_("Couldn't write register %s (#%d): %s."),
761 REGISTER_NAME (regnum
), regnum
, safe_strerror (errno
));
763 addr
+= sizeof (PTRACE_TYPE_RET
);
767 /* Store register REGNUM back into the inferior. If REGNUM is -1, do
768 this for all registers. */
771 ia64_linux_store_registers (struct regcache
*regcache
, int regnum
)
774 for (regnum
= 0; regnum
< gdbarch_num_regs (current_gdbarch
); regnum
++)
775 ia64_linux_store_register (regcache
, regnum
);
777 ia64_linux_store_register (regcache
, regnum
);
781 static LONGEST (*super_xfer_partial
) (struct target_ops
*, enum target_object
,
782 const char *, gdb_byte
*, const gdb_byte
*,
786 ia64_linux_xfer_partial (struct target_ops
*ops
,
787 enum target_object object
,
789 gdb_byte
*readbuf
, const gdb_byte
*writebuf
,
790 ULONGEST offset
, LONGEST len
)
792 if (object
== TARGET_OBJECT_UNWIND_TABLE
&& writebuf
== NULL
&& offset
== 0)
793 return syscall (__NR_getunwind
, readbuf
, len
);
795 return super_xfer_partial (ops
, object
, annex
, readbuf
, writebuf
,
799 void _initialize_ia64_linux_nat (void);
802 _initialize_ia64_linux_nat (void)
804 struct target_ops
*t
= linux_target ();
806 /* Fill in the generic GNU/Linux methods. */
809 /* Override the default fetch/store register routines. */
810 t
->to_fetch_registers
= ia64_linux_fetch_registers
;
811 t
->to_store_registers
= ia64_linux_store_registers
;
813 /* Override the default to_xfer_partial. */
814 super_xfer_partial
= t
->to_xfer_partial
;
815 t
->to_xfer_partial
= ia64_linux_xfer_partial
;
817 /* Override watchpoint routines. */
819 /* The IA-64 architecture can step over a watch point (without triggering
820 it again) if the "dd" (data debug fault disable) bit in the processor
823 This PSR bit is set in ia64_linux_stopped_by_watchpoint when the
824 code there has determined that a hardware watchpoint has indeed
825 been hit. The CPU will then be able to execute one instruction
826 without triggering a watchpoint. */
828 t
->to_have_steppable_watchpoint
= 1;
829 t
->to_can_use_hw_breakpoint
= ia64_linux_can_use_hw_breakpoint
;
830 t
->to_stopped_by_watchpoint
= ia64_linux_stopped_by_watchpoint
;
831 t
->to_stopped_data_address
= ia64_linux_stopped_data_address
;
832 t
->to_insert_watchpoint
= ia64_linux_insert_watchpoint
;
833 t
->to_remove_watchpoint
= ia64_linux_remove_watchpoint
;
835 /* Register the target. */
836 linux_nat_add_target (t
);