1 /* Functions specific to running gdb native on IA-64 running
4 Copyright 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
30 #include <sys/ptrace.h>
37 #include <asm/ptrace_offsets.h>
38 #include <sys/procfs.h>
40 /* Prototypes for supply_gregset etc. */
43 /* These must match the order of the register names.
45 Some sort of lookup table is needed because the offsets associated
46 with the registers are all over the board. */
48 static int u_offsets
[] =
50 /* general registers */
51 -1, /* gr0 not available; i.e, it's always zero */
83 /* gr32 through gr127 not directly available via the ptrace interface */
84 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
85 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
86 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
87 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
88 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
89 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
90 /* Floating point registers */
91 -1, -1, /* f0 and f1 not available (f0 is +0.0 and f1 is +1.0) */
218 /* predicate registers - we don't fetch these individually */
219 -1, -1, -1, -1, -1, -1, -1, -1,
220 -1, -1, -1, -1, -1, -1, -1, -1,
221 -1, -1, -1, -1, -1, -1, -1, -1,
222 -1, -1, -1, -1, -1, -1, -1, -1,
223 -1, -1, -1, -1, -1, -1, -1, -1,
224 -1, -1, -1, -1, -1, -1, -1, -1,
225 -1, -1, -1, -1, -1, -1, -1, -1,
226 -1, -1, -1, -1, -1, -1, -1, -1,
227 /* branch registers */
236 /* virtual frame pointer and virtual return address pointer */
238 /* other registers */
241 PT_CR_IPSR
, /* psr */
243 /* kernel registers not visible via ptrace interface (?) */
244 -1, -1, -1, -1, -1, -1, -1, -1,
246 -1, -1, -1, -1, -1, -1, -1, -1,
252 -1, /* Not available: FCR, IA32 floating control register */
254 -1, /* Not available: EFLAG */
255 -1, /* Not available: CSD */
256 -1, /* Not available: SSD */
257 -1, /* Not available: CFLG */
258 -1, /* Not available: FSR */
259 -1, /* Not available: FIR */
260 -1, /* Not available: FDR */
268 -1, /* Not available: ITC */
269 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
270 -1, -1, -1, -1, -1, -1, -1, -1, -1,
273 -1, /* Not available: EC, the Epilog Count register */
274 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
275 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
276 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
277 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
278 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
279 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
281 /* nat bits - not fetched directly; instead we obtain these bits from
282 either rnat or unat or from memory. */
283 -1, -1, -1, -1, -1, -1, -1, -1,
284 -1, -1, -1, -1, -1, -1, -1, -1,
285 -1, -1, -1, -1, -1, -1, -1, -1,
286 -1, -1, -1, -1, -1, -1, -1, -1,
287 -1, -1, -1, -1, -1, -1, -1, -1,
288 -1, -1, -1, -1, -1, -1, -1, -1,
289 -1, -1, -1, -1, -1, -1, -1, -1,
290 -1, -1, -1, -1, -1, -1, -1, -1,
291 -1, -1, -1, -1, -1, -1, -1, -1,
292 -1, -1, -1, -1, -1, -1, -1, -1,
293 -1, -1, -1, -1, -1, -1, -1, -1,
294 -1, -1, -1, -1, -1, -1, -1, -1,
295 -1, -1, -1, -1, -1, -1, -1, -1,
296 -1, -1, -1, -1, -1, -1, -1, -1,
297 -1, -1, -1, -1, -1, -1, -1, -1,
298 -1, -1, -1, -1, -1, -1, -1, -1,
302 register_addr (int regno
, CORE_ADDR blockend
)
306 if (regno
< 0 || regno
>= NUM_REGS
)
307 error ("Invalid register number %d.", regno
);
309 if (u_offsets
[regno
] == -1)
312 addr
= (CORE_ADDR
) u_offsets
[regno
];
317 int ia64_cannot_fetch_register (regno
)
320 return regno
< 0 || regno
>= NUM_REGS
|| u_offsets
[regno
] == -1;
323 int ia64_cannot_store_register (regno
)
326 /* Rationale behind not permitting stores to bspstore...
328 The IA-64 architecture provides bspstore and bsp which refer
329 memory locations in the RSE's backing store. bspstore is the
330 next location which will be written when the RSE needs to write
331 to memory. bsp is the address at which r32 in the current frame
332 would be found if it were written to the backing store.
334 The IA-64 architecture provides read-only access to bsp and
335 read/write access to bspstore (but only when the RSE is in
336 the enforced lazy mode). It should be noted that stores
337 to bspstore also affect the value of bsp. Changing bspstore
338 does not affect the number of dirty entries between bspstore
339 and bsp, so changing bspstore by N words will also cause bsp
340 to be changed by (roughly) N as well. (It could be N-1 or N+1
341 depending upon where the NaT collection bits fall.)
343 OTOH, the Linux kernel provides read/write access to bsp (and
344 currently read/write access to bspstore as well). But it
345 is definitely the case that if you change one, the other
346 will change at the same time. It is more useful to gdb to
347 be able to change bsp. So in order to prevent strange and
348 undesirable things from happening when a dummy stack frame
349 is popped (after calling an inferior function), we allow
350 bspstore to be read, but not written. (Note that popping
351 a (generic) dummy stack frame causes all registers that
352 were previously read from the inferior process to be written
355 return regno
< 0 || regno
>= NUM_REGS
|| u_offsets
[regno
] == -1
356 || regno
== IA64_BSPSTORE_REGNUM
;
360 supply_gregset (gregset_t
*gregsetp
)
363 greg_t
*regp
= (greg_t
*) gregsetp
;
365 for (regi
= IA64_GR0_REGNUM
; regi
<= IA64_GR31_REGNUM
; regi
++)
367 supply_register (regi
, (char *) (regp
+ (regi
- IA64_GR0_REGNUM
)));
370 /* FIXME: NAT collection bits are at index 32; gotta deal with these
373 supply_register (IA64_PR_REGNUM
, (char *) (regp
+ 33));
375 for (regi
= IA64_BR0_REGNUM
; regi
<= IA64_BR7_REGNUM
; regi
++)
377 supply_register (regi
, (char *) (regp
+ 34 + (regi
- IA64_BR0_REGNUM
)));
380 supply_register (IA64_IP_REGNUM
, (char *) (regp
+ 42));
381 supply_register (IA64_CFM_REGNUM
, (char *) (regp
+ 43));
382 supply_register (IA64_PSR_REGNUM
, (char *) (regp
+ 44));
383 supply_register (IA64_RSC_REGNUM
, (char *) (regp
+ 45));
384 supply_register (IA64_BSP_REGNUM
, (char *) (regp
+ 46));
385 supply_register (IA64_BSPSTORE_REGNUM
, (char *) (regp
+ 47));
386 supply_register (IA64_RNAT_REGNUM
, (char *) (regp
+ 48));
387 supply_register (IA64_CCV_REGNUM
, (char *) (regp
+ 49));
388 supply_register (IA64_UNAT_REGNUM
, (char *) (regp
+ 50));
389 supply_register (IA64_FPSR_REGNUM
, (char *) (regp
+ 51));
390 supply_register (IA64_PFS_REGNUM
, (char *) (regp
+ 52));
391 supply_register (IA64_LC_REGNUM
, (char *) (regp
+ 53));
392 supply_register (IA64_EC_REGNUM
, (char *) (regp
+ 54));
396 fill_gregset (gregset_t
*gregsetp
, int regno
)
399 greg_t
*regp
= (greg_t
*) gregsetp
;
401 #define COPY_REG(_idx_,_regi_) \
402 if ((regno == -1) || regno == _regi_) \
403 memcpy (regp + _idx_, ®isters[REGISTER_BYTE (_regi_)], \
404 REGISTER_RAW_SIZE (_regi_))
406 for (regi
= IA64_GR0_REGNUM
; regi
<= IA64_GR31_REGNUM
; regi
++)
408 COPY_REG (regi
- IA64_GR0_REGNUM
, regi
);
411 /* FIXME: NAT collection bits at index 32? */
413 COPY_REG (33, IA64_PR_REGNUM
);
415 for (regi
= IA64_BR0_REGNUM
; regi
<= IA64_BR7_REGNUM
; regi
++)
417 COPY_REG (34 + (regi
- IA64_BR0_REGNUM
), regi
);
420 COPY_REG (42, IA64_IP_REGNUM
);
421 COPY_REG (43, IA64_CFM_REGNUM
);
422 COPY_REG (44, IA64_PSR_REGNUM
);
423 COPY_REG (45, IA64_RSC_REGNUM
);
424 COPY_REG (46, IA64_BSP_REGNUM
);
425 COPY_REG (47, IA64_BSPSTORE_REGNUM
);
426 COPY_REG (48, IA64_RNAT_REGNUM
);
427 COPY_REG (49, IA64_CCV_REGNUM
);
428 COPY_REG (50, IA64_UNAT_REGNUM
);
429 COPY_REG (51, IA64_FPSR_REGNUM
);
430 COPY_REG (52, IA64_PFS_REGNUM
);
431 COPY_REG (53, IA64_LC_REGNUM
);
432 COPY_REG (54, IA64_EC_REGNUM
);
435 /* Given a pointer to a floating point register set in /proc format
436 (fpregset_t *), unpack the register contents and supply them as gdb's
437 idea of the current floating point register values. */
440 supply_fpregset (fpregset_t
*fpregsetp
)
445 for (regi
= IA64_FR0_REGNUM
; regi
<= IA64_FR127_REGNUM
; regi
++)
447 from
= (char *) &((*fpregsetp
)[regi
- IA64_FR0_REGNUM
]);
448 supply_register (regi
, from
);
452 /* Given a pointer to a floating point register set in /proc format
453 (fpregset_t *), update the register specified by REGNO from gdb's idea
454 of the current floating point register set. If REGNO is -1, update
458 fill_fpregset (fpregset_t
*fpregsetp
, int regno
)
464 for (regi
= IA64_FR0_REGNUM
; regi
<= IA64_FR127_REGNUM
; regi
++)
466 if ((regno
== -1) || (regno
== regi
))
468 from
= (char *) ®isters
[REGISTER_BYTE (regi
)];
469 to
= (char *) &((*fpregsetp
)[regi
- IA64_FR0_REGNUM
]);
470 memcpy (to
, from
, REGISTER_RAW_SIZE (regi
));
475 #define IA64_PSR_DB (1UL << 24)
476 #define IA64_PSR_DD (1UL << 39)
479 enable_watchpoints_in_psr (ptid_t ptid
)
483 psr
= read_register_pid (IA64_PSR_REGNUM
, ptid
);
484 if (!(psr
& IA64_PSR_DB
))
486 psr
|= IA64_PSR_DB
; /* Set the db bit - this enables hardware
487 watchpoints and breakpoints. */
488 write_register_pid (IA64_PSR_REGNUM
, psr
, ptid
);
493 fetch_debug_register (ptid_t ptid
, int idx
)
502 val
= ptrace (PT_READ_U
, tid
, (PTRACE_ARG3_TYPE
) (PT_DBR
+ 8 * idx
), 0);
508 store_debug_register (ptid_t ptid
, int idx
, long val
)
516 (void) ptrace (PT_WRITE_U
, tid
, (PTRACE_ARG3_TYPE
) (PT_DBR
+ 8 * idx
), val
);
520 fetch_debug_register_pair (ptid_t ptid
, int idx
, long *dbr_addr
, long *dbr_mask
)
523 *dbr_addr
= fetch_debug_register (ptid
, 2 * idx
);
525 *dbr_mask
= fetch_debug_register (ptid
, 2 * idx
+ 1);
529 store_debug_register_pair (ptid_t ptid
, int idx
, long *dbr_addr
, long *dbr_mask
)
532 store_debug_register (ptid
, 2 * idx
, *dbr_addr
);
534 store_debug_register (ptid
, 2 * idx
+ 1, *dbr_mask
);
538 is_power_of_2 (int val
)
543 for (i
= 0; i
< 8 * sizeof (val
); i
++)
547 return onecount
<= 1;
551 ia64_linux_insert_watchpoint (ptid_t ptid
, CORE_ADDR addr
, int len
, int rw
)
554 long dbr_addr
, dbr_mask
;
555 int max_watchpoints
= 4;
557 if (len
<= 0 || !is_power_of_2 (len
))
560 for (idx
= 0; idx
< max_watchpoints
; idx
++)
562 fetch_debug_register_pair (ptid
, idx
, NULL
, &dbr_mask
);
563 if ((dbr_mask
& (0x3UL
<< 62)) == 0)
565 /* Exit loop if both r and w bits clear */
570 if (idx
== max_watchpoints
)
573 dbr_addr
= (long) addr
;
574 dbr_mask
= (~(len
- 1) & 0x00ffffffffffffffL
); /* construct mask to match */
575 dbr_mask
|= 0x0800000000000000L
; /* Only match privilege level 3 */
579 dbr_mask
|= (1L << 62); /* Set w bit */
582 dbr_mask
|= (1L << 63); /* Set r bit */
585 dbr_mask
|= (3L << 62); /* Set both r and w bits */
591 store_debug_register_pair (ptid
, idx
, &dbr_addr
, &dbr_mask
);
592 enable_watchpoints_in_psr (ptid
);
598 ia64_linux_remove_watchpoint (ptid_t ptid
, CORE_ADDR addr
, int len
)
601 long dbr_addr
, dbr_mask
;
602 int max_watchpoints
= 4;
604 if (len
<= 0 || !is_power_of_2 (len
))
607 for (idx
= 0; idx
< max_watchpoints
; idx
++)
609 fetch_debug_register_pair (ptid
, idx
, &dbr_addr
, &dbr_mask
);
610 if ((dbr_mask
& (0x3UL
<< 62)) && addr
== (CORE_ADDR
) dbr_addr
)
614 store_debug_register_pair (ptid
, idx
, &dbr_addr
, &dbr_mask
);
622 ia64_linux_stopped_by_watchpoint (ptid_t ptid
)
626 struct siginfo siginfo
;
633 ptrace (PTRACE_GETSIGINFO
, tid
, (PTRACE_ARG3_TYPE
) 0, &siginfo
);
635 if (errno
!= 0 || (siginfo
.si_code
& 0xffff) != 0x0004 /* TRAP_HWBKPT */)
638 psr
= read_register_pid (IA64_PSR_REGNUM
, ptid
);
639 psr
|= IA64_PSR_DD
; /* Set the dd bit - this will disable the watchpoint
640 for the next instruction */
641 write_register_pid (IA64_PSR_REGNUM
, psr
, ptid
);
643 return (CORE_ADDR
) siginfo
.si_addr
;
This page took 0.041904 seconds and 4 git commands to generate.