1 /* Functions specific to running gdb native on IA-64 running Linux.
2 Copyright 1999, 2000 Free Software Foundation, Inc.
4 This file is part of GDB.
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
27 #include <sys/ptrace.h>
34 #include <asm/ptrace_offsets.h>
35 #include <sys/procfs.h>
37 /* Prototypes for supply_gregset etc. */
40 /* These must match the order of the register names.
42 Some sort of lookup table is needed because the offsets associated
43 with the registers are all over the board. */
45 static int u_offsets
[] =
47 /* general registers */
48 -1, /* gr0 not available; i.e, it's always zero */
80 /* gr32 through gr127 not directly available via the ptrace interface */
81 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
82 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
83 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
84 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
85 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
86 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
87 /* Floating point registers */
88 -1, -1, /* f0 and f1 not available (f0 is +0.0 and f1 is +1.0) */
215 /* predicate registers - we don't fetch these individually */
216 -1, -1, -1, -1, -1, -1, -1, -1,
217 -1, -1, -1, -1, -1, -1, -1, -1,
218 -1, -1, -1, -1, -1, -1, -1, -1,
219 -1, -1, -1, -1, -1, -1, -1, -1,
220 -1, -1, -1, -1, -1, -1, -1, -1,
221 -1, -1, -1, -1, -1, -1, -1, -1,
222 -1, -1, -1, -1, -1, -1, -1, -1,
223 -1, -1, -1, -1, -1, -1, -1, -1,
224 /* branch registers */
233 /* virtual frame pointer and virtual return address pointer */
235 /* other registers */
238 PT_CR_IPSR
, /* psr */
240 /* kernel registers not visible via ptrace interface (?) */
241 -1, -1, -1, -1, -1, -1, -1, -1,
243 -1, -1, -1, -1, -1, -1, -1, -1,
249 -1, /* Not available: FCR, IA32 floating control register */
251 -1, /* Not available: EFLAG */
252 -1, /* Not available: CSD */
253 -1, /* Not available: SSD */
254 -1, /* Not available: CFLG */
255 -1, /* Not available: FSR */
256 -1, /* Not available: FIR */
257 -1, /* Not available: FDR */
265 -1, /* Not available: ITC */
266 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
267 -1, -1, -1, -1, -1, -1, -1, -1, -1,
270 -1, /* Not available: EC, the Epilog Count register */
271 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
272 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
273 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
274 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
275 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
276 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
278 /* nat bits - not fetched directly; instead we obtain these bits from
279 either rnat or unat or from memory. */
280 -1, -1, -1, -1, -1, -1, -1, -1,
281 -1, -1, -1, -1, -1, -1, -1, -1,
282 -1, -1, -1, -1, -1, -1, -1, -1,
283 -1, -1, -1, -1, -1, -1, -1, -1,
284 -1, -1, -1, -1, -1, -1, -1, -1,
285 -1, -1, -1, -1, -1, -1, -1, -1,
286 -1, -1, -1, -1, -1, -1, -1, -1,
287 -1, -1, -1, -1, -1, -1, -1, -1,
288 -1, -1, -1, -1, -1, -1, -1, -1,
289 -1, -1, -1, -1, -1, -1, -1, -1,
290 -1, -1, -1, -1, -1, -1, -1, -1,
291 -1, -1, -1, -1, -1, -1, -1, -1,
292 -1, -1, -1, -1, -1, -1, -1, -1,
293 -1, -1, -1, -1, -1, -1, -1, -1,
294 -1, -1, -1, -1, -1, -1, -1, -1,
295 -1, -1, -1, -1, -1, -1, -1, -1,
299 register_addr (int regno
, CORE_ADDR blockend
)
303 if (regno
< 0 || regno
>= NUM_REGS
)
304 error ("Invalid register number %d.", regno
);
306 if (u_offsets
[regno
] == -1)
309 addr
= (CORE_ADDR
) u_offsets
[regno
];
314 int ia64_cannot_fetch_register (regno
)
317 return regno
< 0 || regno
>= NUM_REGS
|| u_offsets
[regno
] == -1;
320 int ia64_cannot_store_register (regno
)
323 /* Rationale behind not permitting stores to bspstore...
325 The IA-64 architecture provides bspstore and bsp which refer
326 memory locations in the RSE's backing store. bspstore is the
327 next location which will be written when the RSE needs to write
328 to memory. bsp is the address at which r32 in the current frame
329 would be found if it were written to the backing store.
331 The IA-64 architecture provides read-only access to bsp and
332 read/write access to bspstore (but only when the RSE is in
333 the enforced lazy mode). It should be noted that stores
334 to bspstore also affect the value of bsp. Changing bspstore
335 does not affect the number of dirty entries between bspstore
336 and bsp, so changing bspstore by N words will also cause bsp
337 to be changed by (roughly) N as well. (It could be N-1 or N+1
338 depending upon where the NaT collection bits fall.)
340 OTOH, the linux kernel provides read/write access to bsp (and
341 currently read/write access to bspstore as well). But it
342 is definitely the case that if you change one, the other
343 will change at the same time. It is more useful to gdb to
344 be able to change bsp. So in order to prevent strange and
345 undesirable things from happening when a dummy stack frame
346 is popped (after calling an inferior function), we allow
347 bspstore to be read, but not written. (Note that popping
348 a (generic) dummy stack frame causes all registers that
349 were previously read from the inferior process to be written
352 return regno
< 0 || regno
>= NUM_REGS
|| u_offsets
[regno
] == -1
353 || regno
== IA64_BSPSTORE_REGNUM
;
357 supply_gregset (gregset_t
*gregsetp
)
360 greg_t
*regp
= (greg_t
*) gregsetp
;
362 for (regi
= IA64_GR0_REGNUM
; regi
<= IA64_GR31_REGNUM
; regi
++)
364 supply_register (regi
, (char *) (regp
+ (regi
- IA64_GR0_REGNUM
)));
367 /* FIXME: NAT collection bits are at index 32; gotta deal with these
370 supply_register (IA64_PR_REGNUM
, (char *) (regp
+ 33));
372 for (regi
= IA64_BR0_REGNUM
; regi
<= IA64_BR7_REGNUM
; regi
++)
374 supply_register (regi
, (char *) (regp
+ 34 + (regi
- IA64_BR0_REGNUM
)));
377 supply_register (IA64_IP_REGNUM
, (char *) (regp
+ 42));
378 supply_register (IA64_CFM_REGNUM
, (char *) (regp
+ 43));
379 supply_register (IA64_PSR_REGNUM
, (char *) (regp
+ 44));
380 supply_register (IA64_RSC_REGNUM
, (char *) (regp
+ 45));
381 supply_register (IA64_BSP_REGNUM
, (char *) (regp
+ 46));
382 supply_register (IA64_BSPSTORE_REGNUM
, (char *) (regp
+ 47));
383 supply_register (IA64_RNAT_REGNUM
, (char *) (regp
+ 48));
384 supply_register (IA64_CCV_REGNUM
, (char *) (regp
+ 49));
385 supply_register (IA64_UNAT_REGNUM
, (char *) (regp
+ 50));
386 supply_register (IA64_FPSR_REGNUM
, (char *) (regp
+ 51));
387 supply_register (IA64_PFS_REGNUM
, (char *) (regp
+ 52));
388 supply_register (IA64_LC_REGNUM
, (char *) (regp
+ 53));
389 supply_register (IA64_EC_REGNUM
, (char *) (regp
+ 54));
393 fill_gregset (gregset_t
*gregsetp
, int regno
)
396 greg_t
*regp
= (greg_t
*) gregsetp
;
398 #define COPY_REG(_idx_,_regi_) \
399 if ((regno == -1) || regno == _regi_) \
400 memcpy (regp + _idx_, ®isters[REGISTER_BYTE (_regi_)], \
401 REGISTER_RAW_SIZE (_regi_))
403 for (regi
= IA64_GR0_REGNUM
; regi
<= IA64_GR31_REGNUM
; regi
++)
405 COPY_REG (regi
- IA64_GR0_REGNUM
, regi
);
408 /* FIXME: NAT collection bits at index 32? */
410 COPY_REG (33, IA64_PR_REGNUM
);
412 for (regi
= IA64_BR0_REGNUM
; regi
<= IA64_BR7_REGNUM
; regi
++)
414 COPY_REG (34 + (regi
- IA64_BR0_REGNUM
), regi
);
417 COPY_REG (42, IA64_IP_REGNUM
);
418 COPY_REG (43, IA64_CFM_REGNUM
);
419 COPY_REG (44, IA64_PSR_REGNUM
);
420 COPY_REG (45, IA64_RSC_REGNUM
);
421 COPY_REG (46, IA64_BSP_REGNUM
);
422 COPY_REG (47, IA64_BSPSTORE_REGNUM
);
423 COPY_REG (48, IA64_RNAT_REGNUM
);
424 COPY_REG (49, IA64_CCV_REGNUM
);
425 COPY_REG (50, IA64_UNAT_REGNUM
);
426 COPY_REG (51, IA64_FPSR_REGNUM
);
427 COPY_REG (52, IA64_PFS_REGNUM
);
428 COPY_REG (53, IA64_LC_REGNUM
);
429 COPY_REG (54, IA64_EC_REGNUM
);
432 /* Given a pointer to a floating point register set in /proc format
433 (fpregset_t *), unpack the register contents and supply them as gdb's
434 idea of the current floating point register values. */
437 supply_fpregset (fpregset_t
*fpregsetp
)
442 for (regi
= IA64_FR0_REGNUM
; regi
<= IA64_FR127_REGNUM
; regi
++)
444 from
= (char *) &((*fpregsetp
)[regi
- IA64_FR0_REGNUM
]);
445 supply_register (regi
, from
);
449 /* Given a pointer to a floating point register set in /proc format
450 (fpregset_t *), update the register specified by REGNO from gdb's idea
451 of the current floating point register set. If REGNO is -1, update
455 fill_fpregset (fpregset_t
*fpregsetp
, int regno
)
461 for (regi
= IA64_FR0_REGNUM
; regi
<= IA64_FR127_REGNUM
; regi
++)
463 if ((regno
== -1) || (regno
== regi
))
465 from
= (char *) ®isters
[REGISTER_BYTE (regi
)];
466 to
= (char *) &((*fpregsetp
)[regi
- IA64_FR0_REGNUM
]);
467 memcpy (to
, from
, REGISTER_RAW_SIZE (regi
));
472 #define IA64_PSR_DB (1UL << 24)
473 #define IA64_PSR_DD (1UL << 39)
476 enable_watchpoints_in_psr (int pid
)
480 psr
= read_register_pid (IA64_PSR_REGNUM
, pid
);
481 if (!(psr
& IA64_PSR_DB
))
483 psr
|= IA64_PSR_DB
; /* Set the db bit - this enables hardware
484 watchpoints and breakpoints. */
485 write_register_pid (IA64_PSR_REGNUM
, psr
, pid
);
490 fetch_debug_register (int pid
, int idx
)
499 val
= ptrace (PT_READ_U
, tid
, (PTRACE_ARG3_TYPE
) (PT_DBR
+ 8 * idx
), 0);
505 store_debug_register (int pid
, int idx
, long val
)
513 (void) ptrace (PT_WRITE_U
, tid
, (PTRACE_ARG3_TYPE
) (PT_DBR
+ 8 * idx
), val
);
517 fetch_debug_register_pair (int pid
, int idx
, long *dbr_addr
, long *dbr_mask
)
520 *dbr_addr
= fetch_debug_register (pid
, 2 * idx
);
522 *dbr_mask
= fetch_debug_register (pid
, 2 * idx
+ 1);
526 store_debug_register_pair (int pid
, int idx
, long *dbr_addr
, long *dbr_mask
)
529 store_debug_register (pid
, 2 * idx
, *dbr_addr
);
531 store_debug_register (pid
, 2 * idx
+ 1, *dbr_mask
);
535 is_power_of_2 (int val
)
540 for (i
= 0; i
< 8 * sizeof (val
); i
++)
544 return onecount
<= 1;
548 ia64_linux_insert_watchpoint (int pid
, CORE_ADDR addr
, int len
, int rw
)
551 long dbr_addr
, dbr_mask
;
552 int max_watchpoints
= 4;
554 if (len
<= 0 || !is_power_of_2 (len
))
557 for (idx
= 0; idx
< max_watchpoints
; idx
++)
559 fetch_debug_register_pair (pid
, idx
, NULL
, &dbr_mask
);
560 if ((dbr_mask
& (0x3UL
<< 62)) == 0)
562 /* Exit loop if both r and w bits clear */
567 if (idx
== max_watchpoints
)
570 dbr_addr
= (long) addr
;
571 dbr_mask
= (~(len
- 1) & 0x00ffffffffffffffL
); /* construct mask to match */
572 dbr_mask
|= 0x0800000000000000L
; /* Only match privilege level 3 */
576 dbr_mask
|= (1L << 62); /* Set w bit */
579 dbr_mask
|= (1L << 63); /* Set r bit */
582 dbr_mask
|= (3L << 62); /* Set both r and w bits */
588 store_debug_register_pair (pid
, idx
, &dbr_addr
, &dbr_mask
);
589 enable_watchpoints_in_psr (pid
);
595 ia64_linux_remove_watchpoint (int pid
, CORE_ADDR addr
, int len
)
598 long dbr_addr
, dbr_mask
;
599 int max_watchpoints
= 4;
601 if (len
<= 0 || !is_power_of_2 (len
))
604 for (idx
= 0; idx
< max_watchpoints
; idx
++)
606 fetch_debug_register_pair (pid
, idx
, &dbr_addr
, &dbr_mask
);
607 if ((dbr_mask
& (0x3UL
<< 62)) && addr
== (CORE_ADDR
) dbr_addr
)
611 store_debug_register_pair (pid
, idx
, &dbr_addr
, &dbr_mask
);
619 ia64_linux_stopped_by_watchpoint (int pid
)
623 struct siginfo siginfo
;
630 ptrace (PTRACE_GETSIGINFO
, tid
, (PTRACE_ARG3_TYPE
) 0, &siginfo
);
632 if (errno
!= 0 || siginfo
.si_code
!= 4 /* TRAP_HWBKPT */)
635 psr
= read_register_pid (IA64_PSR_REGNUM
, pid
);
636 psr
|= IA64_PSR_DD
; /* Set the dd bit - this will disable the watchpoint
637 for the next instruction */
638 write_register_pid (IA64_PSR_REGNUM
, psr
, pid
);
640 return (CORE_ADDR
) siginfo
.si_addr
;
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