1 /* Functions specific to running gdb native on IA-64 running
4 Copyright (C) 1999-2018 Free Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
26 #include "ia64-tdep.h"
27 #include "linux-nat.h"
30 #include "nat/gdb_ptrace.h"
35 #include <sys/syscall.h>
38 #include <asm/ptrace_offsets.h>
39 #include <sys/procfs.h>
41 /* Prototypes for supply_gregset etc. */
44 #include "inf-ptrace.h"
46 class ia64_linux_nat_target final
: public linux_nat_target
49 /* Add our register access methods. */
50 void fetch_registers (struct regcache
*, int) override
;
51 void store_registers (struct regcache
*, int) override
;
53 enum target_xfer_status
xfer_partial (enum target_object object
,
56 const gdb_byte
*writebuf
,
57 ULONGEST offset
, ULONGEST len
,
58 ULONGEST
*xfered_len
) override
;
60 const struct target_desc
*read_description () override
;
62 /* Override watchpoint routines. */
64 /* The IA-64 architecture can step over a watch point (without
65 triggering it again) if the "dd" (data debug fault disable) bit
66 in the processor status word is set.
68 This PSR bit is set in
69 ia64_linux_nat_target::stopped_by_watchpoint when the code there
70 has determined that a hardware watchpoint has indeed been hit.
71 The CPU will then be able to execute one instruction without
72 triggering a watchpoint. */
73 bool have_steppable_watchpoint () { return 1; }
75 int can_use_hw_breakpoint (enum bptype
, int, int) override
;
76 bool stopped_by_watchpoint () override
;
77 bool stopped_data_address (CORE_ADDR
*) override
;
78 int insert_watchpoint (CORE_ADDR
, int, enum target_hw_bp_type
,
79 struct expression
*) override
;
80 int remove_watchpoint (CORE_ADDR
, int, enum target_hw_bp_type
,
81 struct expression
*) override
;
82 /* Override linux_nat_target low methods. */
83 void low_new_thread (struct lwp_info
*lp
) override
;
84 bool low_status_is_event (int status
) override
;
87 static ia64_linux_nat_target the_ia64_linux_nat_target
;
89 /* These must match the order of the register names.
91 Some sort of lookup table is needed because the offsets associated
92 with the registers are all over the board. */
94 static int u_offsets
[] =
96 /* general registers */
97 -1, /* gr0 not available; i.e, it's always zero. */
129 /* gr32 through gr127 not directly available via the ptrace interface. */
130 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
131 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
132 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
133 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
134 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
135 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
136 /* Floating point registers */
137 -1, -1, /* f0 and f1 not available (f0 is +0.0 and f1 is +1.0). */
264 /* Predicate registers - we don't fetch these individually. */
265 -1, -1, -1, -1, -1, -1, -1, -1,
266 -1, -1, -1, -1, -1, -1, -1, -1,
267 -1, -1, -1, -1, -1, -1, -1, -1,
268 -1, -1, -1, -1, -1, -1, -1, -1,
269 -1, -1, -1, -1, -1, -1, -1, -1,
270 -1, -1, -1, -1, -1, -1, -1, -1,
271 -1, -1, -1, -1, -1, -1, -1, -1,
272 -1, -1, -1, -1, -1, -1, -1, -1,
273 /* branch registers */
282 /* Virtual frame pointer and virtual return address pointer. */
284 /* other registers */
287 PT_CR_IPSR
, /* psr */
289 /* kernel registers not visible via ptrace interface (?) */
290 -1, -1, -1, -1, -1, -1, -1, -1,
292 -1, -1, -1, -1, -1, -1, -1, -1,
298 -1, /* Not available: FCR, IA32 floating control register. */
300 -1, /* Not available: EFLAG */
301 -1, /* Not available: CSD */
302 -1, /* Not available: SSD */
303 -1, /* Not available: CFLG */
304 -1, /* Not available: FSR */
305 -1, /* Not available: FIR */
306 -1, /* Not available: FDR */
314 -1, /* Not available: ITC */
315 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
316 -1, -1, -1, -1, -1, -1, -1, -1, -1,
320 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
321 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
322 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
323 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
324 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
325 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
327 /* nat bits - not fetched directly; instead we obtain these bits from
328 either rnat or unat or from memory. */
329 -1, -1, -1, -1, -1, -1, -1, -1,
330 -1, -1, -1, -1, -1, -1, -1, -1,
331 -1, -1, -1, -1, -1, -1, -1, -1,
332 -1, -1, -1, -1, -1, -1, -1, -1,
333 -1, -1, -1, -1, -1, -1, -1, -1,
334 -1, -1, -1, -1, -1, -1, -1, -1,
335 -1, -1, -1, -1, -1, -1, -1, -1,
336 -1, -1, -1, -1, -1, -1, -1, -1,
337 -1, -1, -1, -1, -1, -1, -1, -1,
338 -1, -1, -1, -1, -1, -1, -1, -1,
339 -1, -1, -1, -1, -1, -1, -1, -1,
340 -1, -1, -1, -1, -1, -1, -1, -1,
341 -1, -1, -1, -1, -1, -1, -1, -1,
342 -1, -1, -1, -1, -1, -1, -1, -1,
343 -1, -1, -1, -1, -1, -1, -1, -1,
344 -1, -1, -1, -1, -1, -1, -1, -1,
348 ia64_register_addr (struct gdbarch
*gdbarch
, int regno
)
352 if (regno
< 0 || regno
>= gdbarch_num_regs (gdbarch
))
353 error (_("Invalid register number %d."), regno
);
355 if (u_offsets
[regno
] == -1)
358 addr
= (CORE_ADDR
) u_offsets
[regno
];
364 ia64_cannot_fetch_register (struct gdbarch
*gdbarch
, int regno
)
367 || regno
>= gdbarch_num_regs (gdbarch
)
368 || u_offsets
[regno
] == -1;
372 ia64_cannot_store_register (struct gdbarch
*gdbarch
, int regno
)
374 /* Rationale behind not permitting stores to bspstore...
376 The IA-64 architecture provides bspstore and bsp which refer
377 memory locations in the RSE's backing store. bspstore is the
378 next location which will be written when the RSE needs to write
379 to memory. bsp is the address at which r32 in the current frame
380 would be found if it were written to the backing store.
382 The IA-64 architecture provides read-only access to bsp and
383 read/write access to bspstore (but only when the RSE is in
384 the enforced lazy mode). It should be noted that stores
385 to bspstore also affect the value of bsp. Changing bspstore
386 does not affect the number of dirty entries between bspstore
387 and bsp, so changing bspstore by N words will also cause bsp
388 to be changed by (roughly) N as well. (It could be N-1 or N+1
389 depending upon where the NaT collection bits fall.)
391 OTOH, the Linux kernel provides read/write access to bsp (and
392 currently read/write access to bspstore as well). But it
393 is definitely the case that if you change one, the other
394 will change at the same time. It is more useful to gdb to
395 be able to change bsp. So in order to prevent strange and
396 undesirable things from happening when a dummy stack frame
397 is popped (after calling an inferior function), we allow
398 bspstore to be read, but not written. (Note that popping
399 a (generic) dummy stack frame causes all registers that
400 were previously read from the inferior process to be written
404 || regno
>= gdbarch_num_regs (gdbarch
)
405 || u_offsets
[regno
] == -1
406 || regno
== IA64_BSPSTORE_REGNUM
;
410 supply_gregset (struct regcache
*regcache
, const gregset_t
*gregsetp
)
413 const greg_t
*regp
= (const greg_t
*) gregsetp
;
415 for (regi
= IA64_GR0_REGNUM
; regi
<= IA64_GR31_REGNUM
; regi
++)
417 regcache_raw_supply (regcache
, regi
, regp
+ (regi
- IA64_GR0_REGNUM
));
420 /* FIXME: NAT collection bits are at index 32; gotta deal with these
423 regcache_raw_supply (regcache
, IA64_PR_REGNUM
, regp
+ 33);
425 for (regi
= IA64_BR0_REGNUM
; regi
<= IA64_BR7_REGNUM
; regi
++)
427 regcache_raw_supply (regcache
, regi
,
428 regp
+ 34 + (regi
- IA64_BR0_REGNUM
));
431 regcache_raw_supply (regcache
, IA64_IP_REGNUM
, regp
+ 42);
432 regcache_raw_supply (regcache
, IA64_CFM_REGNUM
, regp
+ 43);
433 regcache_raw_supply (regcache
, IA64_PSR_REGNUM
, regp
+ 44);
434 regcache_raw_supply (regcache
, IA64_RSC_REGNUM
, regp
+ 45);
435 regcache_raw_supply (regcache
, IA64_BSP_REGNUM
, regp
+ 46);
436 regcache_raw_supply (regcache
, IA64_BSPSTORE_REGNUM
, regp
+ 47);
437 regcache_raw_supply (regcache
, IA64_RNAT_REGNUM
, regp
+ 48);
438 regcache_raw_supply (regcache
, IA64_CCV_REGNUM
, regp
+ 49);
439 regcache_raw_supply (regcache
, IA64_UNAT_REGNUM
, regp
+ 50);
440 regcache_raw_supply (regcache
, IA64_FPSR_REGNUM
, regp
+ 51);
441 regcache_raw_supply (regcache
, IA64_PFS_REGNUM
, regp
+ 52);
442 regcache_raw_supply (regcache
, IA64_LC_REGNUM
, regp
+ 53);
443 regcache_raw_supply (regcache
, IA64_EC_REGNUM
, regp
+ 54);
447 fill_gregset (const struct regcache
*regcache
, gregset_t
*gregsetp
, int regno
)
450 greg_t
*regp
= (greg_t
*) gregsetp
;
452 #define COPY_REG(_idx_,_regi_) \
453 if ((regno == -1) || regno == _regi_) \
454 regcache_raw_collect (regcache, _regi_, regp + _idx_)
456 for (regi
= IA64_GR0_REGNUM
; regi
<= IA64_GR31_REGNUM
; regi
++)
458 COPY_REG (regi
- IA64_GR0_REGNUM
, regi
);
461 /* FIXME: NAT collection bits at index 32? */
463 COPY_REG (33, IA64_PR_REGNUM
);
465 for (regi
= IA64_BR0_REGNUM
; regi
<= IA64_BR7_REGNUM
; regi
++)
467 COPY_REG (34 + (regi
- IA64_BR0_REGNUM
), regi
);
470 COPY_REG (42, IA64_IP_REGNUM
);
471 COPY_REG (43, IA64_CFM_REGNUM
);
472 COPY_REG (44, IA64_PSR_REGNUM
);
473 COPY_REG (45, IA64_RSC_REGNUM
);
474 COPY_REG (46, IA64_BSP_REGNUM
);
475 COPY_REG (47, IA64_BSPSTORE_REGNUM
);
476 COPY_REG (48, IA64_RNAT_REGNUM
);
477 COPY_REG (49, IA64_CCV_REGNUM
);
478 COPY_REG (50, IA64_UNAT_REGNUM
);
479 COPY_REG (51, IA64_FPSR_REGNUM
);
480 COPY_REG (52, IA64_PFS_REGNUM
);
481 COPY_REG (53, IA64_LC_REGNUM
);
482 COPY_REG (54, IA64_EC_REGNUM
);
485 /* Given a pointer to a floating point register set in /proc format
486 (fpregset_t *), unpack the register contents and supply them as gdb's
487 idea of the current floating point register values. */
490 supply_fpregset (struct regcache
*regcache
, const fpregset_t
*fpregsetp
)
494 const gdb_byte f_zero
[16] = { 0 };
495 const gdb_byte f_one
[16] =
496 { 0, 0, 0, 0, 0, 0, 0, 0x80, 0xff, 0xff, 0, 0, 0, 0, 0, 0 };
498 /* Kernel generated cores have fr1==0 instead of 1.0. Older GDBs
499 did the same. So ignore whatever might be recorded in fpregset_t
500 for fr0/fr1 and always supply their expected values. */
502 /* fr0 is always read as zero. */
503 regcache_raw_supply (regcache
, IA64_FR0_REGNUM
, f_zero
);
504 /* fr1 is always read as one (1.0). */
505 regcache_raw_supply (regcache
, IA64_FR1_REGNUM
, f_one
);
507 for (regi
= IA64_FR2_REGNUM
; regi
<= IA64_FR127_REGNUM
; regi
++)
509 from
= (const char *) &((*fpregsetp
)[regi
- IA64_FR0_REGNUM
]);
510 regcache_raw_supply (regcache
, regi
, from
);
514 /* Given a pointer to a floating point register set in /proc format
515 (fpregset_t *), update the register specified by REGNO from gdb's idea
516 of the current floating point register set. If REGNO is -1, update
520 fill_fpregset (const struct regcache
*regcache
,
521 fpregset_t
*fpregsetp
, int regno
)
525 for (regi
= IA64_FR0_REGNUM
; regi
<= IA64_FR127_REGNUM
; regi
++)
527 if ((regno
== -1) || (regno
== regi
))
528 regcache_raw_collect (regcache
, regi
,
529 &((*fpregsetp
)[regi
- IA64_FR0_REGNUM
]));
533 #define IA64_PSR_DB (1UL << 24)
534 #define IA64_PSR_DD (1UL << 39)
537 enable_watchpoints_in_psr (ptid_t ptid
)
539 struct regcache
*regcache
= get_thread_regcache (ptid
);
542 regcache_cooked_read_unsigned (regcache
, IA64_PSR_REGNUM
, &psr
);
543 if (!(psr
& IA64_PSR_DB
))
545 psr
|= IA64_PSR_DB
; /* Set the db bit - this enables hardware
546 watchpoints and breakpoints. */
547 regcache_cooked_write_unsigned (regcache
, IA64_PSR_REGNUM
, psr
);
551 static long debug_registers
[8];
554 store_debug_register (ptid_t ptid
, int idx
, long val
)
558 tid
= ptid_get_lwp (ptid
);
560 tid
= ptid_get_pid (ptid
);
562 (void) ptrace (PT_WRITE_U
, tid
, (PTRACE_TYPE_ARG3
) (PT_DBR
+ 8 * idx
), val
);
566 store_debug_register_pair (ptid_t ptid
, int idx
, long *dbr_addr
,
570 store_debug_register (ptid
, 2 * idx
, *dbr_addr
);
572 store_debug_register (ptid
, 2 * idx
+ 1, *dbr_mask
);
576 is_power_of_2 (int val
)
581 for (i
= 0; i
< 8 * sizeof (val
); i
++)
585 return onecount
<= 1;
589 ia64_linux_nat_target::insert_watchpoint (CORE_ADDR addr
, int len
,
590 enum target_hw_bp_type type
,
591 struct expression
*cond
)
595 long dbr_addr
, dbr_mask
;
596 int max_watchpoints
= 4;
598 if (len
<= 0 || !is_power_of_2 (len
))
601 for (idx
= 0; idx
< max_watchpoints
; idx
++)
603 dbr_mask
= debug_registers
[idx
* 2 + 1];
604 if ((dbr_mask
& (0x3UL
<< 62)) == 0)
606 /* Exit loop if both r and w bits clear. */
611 if (idx
== max_watchpoints
)
614 dbr_addr
= (long) addr
;
615 dbr_mask
= (~(len
- 1) & 0x00ffffffffffffffL
); /* construct mask to match */
616 dbr_mask
|= 0x0800000000000000L
; /* Only match privilege level 3 */
620 dbr_mask
|= (1L << 62); /* Set w bit */
623 dbr_mask
|= (1L << 63); /* Set r bit */
626 dbr_mask
|= (3L << 62); /* Set both r and w bits */
632 debug_registers
[2 * idx
] = dbr_addr
;
633 debug_registers
[2 * idx
+ 1] = dbr_mask
;
636 store_debug_register_pair (lp
->ptid
, idx
, &dbr_addr
, &dbr_mask
);
637 enable_watchpoints_in_psr (lp
->ptid
);
644 ia64_linux_nat_target::remove_watchpoint (CORE_ADDR addr
, int len
,
645 enum target_hw_bp_type type
,
646 struct expression
*cond
)
649 long dbr_addr
, dbr_mask
;
650 int max_watchpoints
= 4;
652 if (len
<= 0 || !is_power_of_2 (len
))
655 for (idx
= 0; idx
< max_watchpoints
; idx
++)
657 dbr_addr
= debug_registers
[2 * idx
];
658 dbr_mask
= debug_registers
[2 * idx
+ 1];
659 if ((dbr_mask
& (0x3UL
<< 62)) && addr
== (CORE_ADDR
) dbr_addr
)
663 debug_registers
[2 * idx
] = 0;
664 debug_registers
[2 * idx
+ 1] = 0;
669 store_debug_register_pair (lp
->ptid
, idx
, &dbr_addr
, &dbr_mask
);
678 ia64_linux_new_thread (struct lwp_info
*lp
)
683 for (i
= 0; i
< 8; i
++)
685 if (debug_registers
[i
] != 0)
687 store_debug_register (lp
->ptid
, i
, debug_registers
[i
]);
691 enable_watchpoints_in_psr (lp
->ptid
);
695 ia64_linux_nat_target::stopped_data_address (CORE_ADDR
*addr_p
)
699 struct regcache
*regcache
= get_current_regcache ();
701 if (!linux_nat_get_siginfo (inferior_ptid
, &siginfo
))
704 if (siginfo
.si_signo
!= SIGTRAP
705 || (siginfo
.si_code
& 0xffff) != 0x0004 /* TRAP_HWBKPT */)
708 regcache_cooked_read_unsigned (regcache
, IA64_PSR_REGNUM
, &psr
);
709 psr
|= IA64_PSR_DD
; /* Set the dd bit - this will disable the watchpoint
710 for the next instruction. */
711 regcache_cooked_write_unsigned (regcache
, IA64_PSR_REGNUM
, psr
);
713 *addr_p
= (CORE_ADDR
) siginfo
.si_addr
;
718 ia64_linux_nat_target::stopped_by_watchpoint ()
721 return stopped_data_address (&addr
);
725 ia64_linux_can_use_hw_breakpoint (struct target_ops
*self
,
727 int cnt
, int othertype
)
733 /* Fetch register REGNUM from the inferior. */
736 ia64_linux_fetch_register (struct regcache
*regcache
, int regnum
)
738 struct gdbarch
*gdbarch
= regcache
->arch ();
741 PTRACE_TYPE_RET
*buf
;
745 /* r0 cannot be fetched but is always zero. */
746 if (regnum
== IA64_GR0_REGNUM
)
748 const gdb_byte zero
[8] = { 0 };
750 gdb_assert (sizeof (zero
) == register_size (gdbarch
, regnum
));
751 regcache_raw_supply (regcache
, regnum
, zero
);
755 /* fr0 cannot be fetched but is always zero. */
756 if (regnum
== IA64_FR0_REGNUM
)
758 const gdb_byte f_zero
[16] = { 0 };
760 gdb_assert (sizeof (f_zero
) == register_size (gdbarch
, regnum
));
761 regcache_raw_supply (regcache
, regnum
, f_zero
);
765 /* fr1 cannot be fetched but is always one (1.0). */
766 if (regnum
== IA64_FR1_REGNUM
)
768 const gdb_byte f_one
[16] =
769 { 0, 0, 0, 0, 0, 0, 0, 0x80, 0xff, 0xff, 0, 0, 0, 0, 0, 0 };
771 gdb_assert (sizeof (f_one
) == register_size (gdbarch
, regnum
));
772 regcache_raw_supply (regcache
, regnum
, f_one
);
776 if (ia64_cannot_fetch_register (gdbarch
, regnum
))
778 regcache_raw_supply (regcache
, regnum
, NULL
);
782 pid
= get_ptrace_pid (regcache_get_ptid (regcache
));
784 /* This isn't really an address, but ptrace thinks of it as one. */
785 addr
= ia64_register_addr (gdbarch
, regnum
);
786 size
= register_size (gdbarch
, regnum
);
788 gdb_assert ((size
% sizeof (PTRACE_TYPE_RET
)) == 0);
789 buf
= (PTRACE_TYPE_RET
*) alloca (size
);
791 /* Read the register contents from the inferior a chunk at a time. */
792 for (i
= 0; i
< size
/ sizeof (PTRACE_TYPE_RET
); i
++)
795 buf
[i
] = ptrace (PT_READ_U
, pid
, (PTRACE_TYPE_ARG3
)addr
, 0);
797 error (_("Couldn't read register %s (#%d): %s."),
798 gdbarch_register_name (gdbarch
, regnum
),
799 regnum
, safe_strerror (errno
));
801 addr
+= sizeof (PTRACE_TYPE_RET
);
803 regcache_raw_supply (regcache
, regnum
, buf
);
806 /* Fetch register REGNUM from the inferior. If REGNUM is -1, do this
807 for all registers. */
810 ia64_linux_nat_target::fetch_registers (struct regcache
*regcache
, int regnum
)
814 regnum
< gdbarch_num_regs (regcache
->arch ());
816 ia64_linux_fetch_register (regcache
, regnum
);
818 ia64_linux_fetch_register (regcache
, regnum
);
821 /* Store register REGNUM into the inferior. */
824 ia64_linux_store_register (const struct regcache
*regcache
, int regnum
)
826 struct gdbarch
*gdbarch
= regcache
->arch ();
829 PTRACE_TYPE_RET
*buf
;
833 if (ia64_cannot_store_register (gdbarch
, regnum
))
836 pid
= get_ptrace_pid (regcache_get_ptid (regcache
));
838 /* This isn't really an address, but ptrace thinks of it as one. */
839 addr
= ia64_register_addr (gdbarch
, regnum
);
840 size
= register_size (gdbarch
, regnum
);
842 gdb_assert ((size
% sizeof (PTRACE_TYPE_RET
)) == 0);
843 buf
= (PTRACE_TYPE_RET
*) alloca (size
);
845 /* Write the register contents into the inferior a chunk at a time. */
846 regcache_raw_collect (regcache
, regnum
, buf
);
847 for (i
= 0; i
< size
/ sizeof (PTRACE_TYPE_RET
); i
++)
850 ptrace (PT_WRITE_U
, pid
, (PTRACE_TYPE_ARG3
)addr
, buf
[i
]);
852 error (_("Couldn't write register %s (#%d): %s."),
853 gdbarch_register_name (gdbarch
, regnum
),
854 regnum
, safe_strerror (errno
));
856 addr
+= sizeof (PTRACE_TYPE_RET
);
860 /* Store register REGNUM back into the inferior. If REGNUM is -1, do
861 this for all registers. */
864 ia64_linux_nat_target::store_registers (struct regcache
*regcache
, int regnum
)
868 regnum
< gdbarch_num_regs (regcache
->arch ());
870 ia64_linux_store_register (regcache
, regnum
);
872 ia64_linux_store_register (regcache
, regnum
);
875 /* Implement the xfer_partial target_ops method. */
877 enum target_xfer_status
878 ia64_linux_nat_target::xfer_partial (enum target_object object
,
880 gdb_byte
*readbuf
, const gdb_byte
*writebuf
,
881 ULONGEST offset
, ULONGEST len
,
882 ULONGEST
*xfered_len
)
884 if (object
== TARGET_OBJECT_UNWIND_TABLE
&& readbuf
!= NULL
)
886 static long gate_table_size
;
890 /* Probe for the table size once. */
891 if (gate_table_size
== 0)
892 gate_table_size
= syscall (__NR_getunwind
, NULL
, 0);
893 if (gate_table_size
< 0)
894 return TARGET_XFER_E_IO
;
896 if (offset
>= gate_table_size
)
897 return TARGET_XFER_EOF
;
899 tmp_buf
= (gdb_byte
*) alloca (gate_table_size
);
900 res
= syscall (__NR_getunwind
, tmp_buf
, gate_table_size
);
902 return TARGET_XFER_E_IO
;
903 gdb_assert (res
== gate_table_size
);
905 if (offset
+ len
> gate_table_size
)
906 len
= gate_table_size
- offset
;
908 memcpy (readbuf
, tmp_buf
+ offset
, len
);
910 return TARGET_XFER_OK
;
913 return linux_nat_target::xfer_partial (object
, annex
, readbuf
, writebuf
,
914 offset
, len
, xfered_len
);
917 /* For break.b instruction ia64 CPU forgets the immediate value and generates
918 SIGILL with ILL_ILLOPC instead of more common SIGTRAP with TRAP_BRKPT.
919 ia64 does not use gdbarch_decr_pc_after_break so we do not have to make any
920 difference for the signals here. */
923 ia64_linux_nat_target::low_status_is_event (int status
)
925 return WIFSTOPPED (status
) && (WSTOPSIG (status
) == SIGTRAP
926 || WSTOPSIG (status
) == SIGILL
);
930 _initialize_ia64_linux_nat (void)
932 /* Register the target. */
933 linux_target
= &the_ia64_linux_nat_target
;
934 add_inf_child_target (&the_ia64_linux_nat_target
);