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* regcache.c (register_buffer): Consitify first argument.
[deliverable/binutils-gdb.git] / gdb / ia64-tdep.c
1 /* Target-dependent code for the IA-64 for GDB, the GNU debugger.
2
3 Copyright 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
21
22 #include "defs.h"
23 #include "inferior.h"
24 #include "symfile.h" /* for entry_point_address */
25 #include "gdbcore.h"
26 #include "arch-utils.h"
27 #include "floatformat.h"
28 #include "regcache.h"
29 #include "reggroups.h"
30 #include "frame.h"
31 #include "frame-base.h"
32 #include "frame-unwind.h"
33 #include "doublest.h"
34 #include "value.h"
35 #include "gdb_assert.h"
36 #include "objfiles.h"
37 #include "elf/common.h" /* for DT_PLTGOT value */
38 #include "elf-bfd.h"
39
40 /* Hook for determining the global pointer when calling functions in
41 the inferior under AIX. The initialization code in ia64-aix-nat.c
42 sets this hook to the address of a function which will find the
43 global pointer for a given address.
44
45 The generic code which uses the dynamic section in the inferior for
46 finding the global pointer is not of much use on AIX since the
47 values obtained from the inferior have not been relocated. */
48
49 CORE_ADDR (*native_find_global_pointer) (CORE_ADDR) = 0;
50
51 /* An enumeration of the different IA-64 instruction types. */
52
53 typedef enum instruction_type
54 {
55 A, /* Integer ALU ; I-unit or M-unit */
56 I, /* Non-ALU integer; I-unit */
57 M, /* Memory ; M-unit */
58 F, /* Floating-point ; F-unit */
59 B, /* Branch ; B-unit */
60 L, /* Extended (L+X) ; I-unit */
61 X, /* Extended (L+X) ; I-unit */
62 undefined /* undefined or reserved */
63 } instruction_type;
64
65 /* We represent IA-64 PC addresses as the value of the instruction
66 pointer or'd with some bit combination in the low nibble which
67 represents the slot number in the bundle addressed by the
68 instruction pointer. The problem is that the Linux kernel
69 multiplies its slot numbers (for exceptions) by one while the
70 disassembler multiplies its slot numbers by 6. In addition, I've
71 heard it said that the simulator uses 1 as the multiplier.
72
73 I've fixed the disassembler so that the bytes_per_line field will
74 be the slot multiplier. If bytes_per_line comes in as zero, it
75 is set to six (which is how it was set up initially). -- objdump
76 displays pretty disassembly dumps with this value. For our purposes,
77 we'll set bytes_per_line to SLOT_MULTIPLIER. This is okay since we
78 never want to also display the raw bytes the way objdump does. */
79
80 #define SLOT_MULTIPLIER 1
81
82 /* Length in bytes of an instruction bundle */
83
84 #define BUNDLE_LEN 16
85
86 /* FIXME: These extern declarations should go in ia64-tdep.h. */
87 extern CORE_ADDR ia64_linux_sigcontext_register_address (CORE_ADDR, int);
88 extern CORE_ADDR ia64_aix_sigcontext_register_address (CORE_ADDR, int);
89
90 static gdbarch_init_ftype ia64_gdbarch_init;
91
92 static gdbarch_register_name_ftype ia64_register_name;
93 static gdbarch_register_type_ftype ia64_register_type;
94 static gdbarch_breakpoint_from_pc_ftype ia64_breakpoint_from_pc;
95 static gdbarch_skip_prologue_ftype ia64_skip_prologue;
96 static gdbarch_extract_return_value_ftype ia64_extract_return_value;
97 static gdbarch_extract_struct_value_address_ftype ia64_extract_struct_value_address;
98 static gdbarch_use_struct_convention_ftype ia64_use_struct_convention;
99 static struct type *is_float_or_hfa_type (struct type *t);
100
101 static struct type *builtin_type_ia64_ext;
102
103 #define NUM_IA64_RAW_REGS 462
104
105 static int sp_regnum = IA64_GR12_REGNUM;
106 static int fp_regnum = IA64_VFP_REGNUM;
107 static int lr_regnum = IA64_VRAP_REGNUM;
108
109 /* NOTE: we treat the register stack registers r32-r127 as pseudo-registers because
110 they are in memory and must be calculated via the bsp register. */
111 enum pseudo_regs { FIRST_PSEUDO_REGNUM = NUM_IA64_RAW_REGS, VBOF_REGNUM = IA64_NAT127_REGNUM + 1, V32_REGNUM,
112 V127_REGNUM = V32_REGNUM + 95,
113 VP0_REGNUM, VP16_REGNUM = VP0_REGNUM + 16, VP63_REGNUM = VP0_REGNUM + 63, LAST_PSEUDO_REGNUM };
114
115 /* Array of register names; There should be ia64_num_regs strings in
116 the initializer. */
117
118 static char *ia64_register_names[] =
119 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
120 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
121 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
122 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
123 "", "", "", "", "", "", "", "",
124 "", "", "", "", "", "", "", "",
125 "", "", "", "", "", "", "", "",
126 "", "", "", "", "", "", "", "",
127 "", "", "", "", "", "", "", "",
128 "", "", "", "", "", "", "", "",
129 "", "", "", "", "", "", "", "",
130 "", "", "", "", "", "", "", "",
131 "", "", "", "", "", "", "", "",
132 "", "", "", "", "", "", "", "",
133 "", "", "", "", "", "", "", "",
134 "", "", "", "", "", "", "", "",
135
136 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
137 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
138 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
139 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
140 "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
141 "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47",
142 "f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55",
143 "f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63",
144 "f64", "f65", "f66", "f67", "f68", "f69", "f70", "f71",
145 "f72", "f73", "f74", "f75", "f76", "f77", "f78", "f79",
146 "f80", "f81", "f82", "f83", "f84", "f85", "f86", "f87",
147 "f88", "f89", "f90", "f91", "f92", "f93", "f94", "f95",
148 "f96", "f97", "f98", "f99", "f100", "f101", "f102", "f103",
149 "f104", "f105", "f106", "f107", "f108", "f109", "f110", "f111",
150 "f112", "f113", "f114", "f115", "f116", "f117", "f118", "f119",
151 "f120", "f121", "f122", "f123", "f124", "f125", "f126", "f127",
152
153 "", "", "", "", "", "", "", "",
154 "", "", "", "", "", "", "", "",
155 "", "", "", "", "", "", "", "",
156 "", "", "", "", "", "", "", "",
157 "", "", "", "", "", "", "", "",
158 "", "", "", "", "", "", "", "",
159 "", "", "", "", "", "", "", "",
160 "", "", "", "", "", "", "", "",
161
162 "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7",
163
164 "vfp", "vrap",
165
166 "pr", "ip", "psr", "cfm",
167
168 "kr0", "kr1", "kr2", "kr3", "kr4", "kr5", "kr6", "kr7",
169 "", "", "", "", "", "", "", "",
170 "rsc", "bsp", "bspstore", "rnat",
171 "", "fcr", "", "",
172 "eflag", "csd", "ssd", "cflg", "fsr", "fir", "fdr", "",
173 "ccv", "", "", "", "unat", "", "", "",
174 "fpsr", "", "", "", "itc",
175 "", "", "", "", "", "", "", "", "", "",
176 "", "", "", "", "", "", "", "", "",
177 "pfs", "lc", "ec",
178 "", "", "", "", "", "", "", "", "", "",
179 "", "", "", "", "", "", "", "", "", "",
180 "", "", "", "", "", "", "", "", "", "",
181 "", "", "", "", "", "", "", "", "", "",
182 "", "", "", "", "", "", "", "", "", "",
183 "", "", "", "", "", "", "", "", "", "",
184 "",
185 "nat0", "nat1", "nat2", "nat3", "nat4", "nat5", "nat6", "nat7",
186 "nat8", "nat9", "nat10", "nat11", "nat12", "nat13", "nat14", "nat15",
187 "nat16", "nat17", "nat18", "nat19", "nat20", "nat21", "nat22", "nat23",
188 "nat24", "nat25", "nat26", "nat27", "nat28", "nat29", "nat30", "nat31",
189 "nat32", "nat33", "nat34", "nat35", "nat36", "nat37", "nat38", "nat39",
190 "nat40", "nat41", "nat42", "nat43", "nat44", "nat45", "nat46", "nat47",
191 "nat48", "nat49", "nat50", "nat51", "nat52", "nat53", "nat54", "nat55",
192 "nat56", "nat57", "nat58", "nat59", "nat60", "nat61", "nat62", "nat63",
193 "nat64", "nat65", "nat66", "nat67", "nat68", "nat69", "nat70", "nat71",
194 "nat72", "nat73", "nat74", "nat75", "nat76", "nat77", "nat78", "nat79",
195 "nat80", "nat81", "nat82", "nat83", "nat84", "nat85", "nat86", "nat87",
196 "nat88", "nat89", "nat90", "nat91", "nat92", "nat93", "nat94", "nat95",
197 "nat96", "nat97", "nat98", "nat99", "nat100","nat101","nat102","nat103",
198 "nat104","nat105","nat106","nat107","nat108","nat109","nat110","nat111",
199 "nat112","nat113","nat114","nat115","nat116","nat117","nat118","nat119",
200 "nat120","nat121","nat122","nat123","nat124","nat125","nat126","nat127",
201
202 "bof",
203
204 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
205 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
206 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
207 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
208 "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71",
209 "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
210 "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87",
211 "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95",
212 "r96", "r97", "r98", "r99", "r100", "r101", "r102", "r103",
213 "r104", "r105", "r106", "r107", "r108", "r109", "r110", "r111",
214 "r112", "r113", "r114", "r115", "r116", "r117", "r118", "r119",
215 "r120", "r121", "r122", "r123", "r124", "r125", "r126", "r127",
216
217 "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7",
218 "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15",
219 "p16", "p17", "p18", "p19", "p20", "p21", "p22", "p23",
220 "p24", "p25", "p26", "p27", "p28", "p29", "p30", "p31",
221 "p32", "p33", "p34", "p35", "p36", "p37", "p38", "p39",
222 "p40", "p41", "p42", "p43", "p44", "p45", "p46", "p47",
223 "p48", "p49", "p50", "p51", "p52", "p53", "p54", "p55",
224 "p56", "p57", "p58", "p59", "p60", "p61", "p62", "p63",
225 };
226
227 struct ia64_frame_cache
228 {
229 CORE_ADDR base; /* frame pointer base for frame */
230 CORE_ADDR pc; /* function start pc for frame */
231 CORE_ADDR saved_sp; /* stack pointer for frame */
232 CORE_ADDR bsp; /* points at r32 for the current frame */
233 CORE_ADDR cfm; /* cfm value for current frame */
234 int frameless;
235 int sof; /* Size of frame (decoded from cfm value) */
236 int sol; /* Size of locals (decoded from cfm value) */
237 int sor; /* Number of rotating registers. (decoded from cfm value) */
238 CORE_ADDR after_prologue;
239 /* Address of first instruction after the last
240 prologue instruction; Note that there may
241 be instructions from the function's body
242 intermingled with the prologue. */
243 int mem_stack_frame_size;
244 /* Size of the memory stack frame (may be zero),
245 or -1 if it has not been determined yet. */
246 int fp_reg; /* Register number (if any) used a frame pointer
247 for this frame. 0 if no register is being used
248 as the frame pointer. */
249
250 /* Saved registers. */
251 CORE_ADDR saved_regs[NUM_IA64_RAW_REGS];
252
253 };
254
255 struct gdbarch_tdep
256 {
257 int os_ident; /* From the ELF header, one of the ELFOSABI_
258 constants: ELFOSABI_LINUX, ELFOSABI_AIX,
259 etc. */
260 CORE_ADDR (*sigcontext_register_address) (CORE_ADDR, int);
261 /* OS specific function which, given a frame address
262 and register number, returns the offset to the
263 given register from the start of the frame. */
264 CORE_ADDR (*find_global_pointer) (CORE_ADDR);
265 };
266
267 #define SIGCONTEXT_REGISTER_ADDRESS \
268 (gdbarch_tdep (current_gdbarch)->sigcontext_register_address)
269 #define FIND_GLOBAL_POINTER \
270 (gdbarch_tdep (current_gdbarch)->find_global_pointer)
271
272 int
273 ia64_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
274 struct reggroup *group)
275 {
276 int vector_p;
277 int float_p;
278 int raw_p;
279 if (group == all_reggroup)
280 return 1;
281 vector_p = TYPE_VECTOR (register_type (gdbarch, regnum));
282 float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT;
283 raw_p = regnum < NUM_IA64_RAW_REGS;
284 if (group == float_reggroup)
285 return float_p;
286 if (group == vector_reggroup)
287 return vector_p;
288 if (group == general_reggroup)
289 return (!vector_p && !float_p);
290 if (group == save_reggroup || group == restore_reggroup)
291 return raw_p;
292 return 0;
293 }
294
295 static const char *
296 ia64_register_name (int reg)
297 {
298 return ia64_register_names[reg];
299 }
300
301 struct type *
302 ia64_register_type (struct gdbarch *arch, int reg)
303 {
304 if (reg >= IA64_FR0_REGNUM && reg <= IA64_FR127_REGNUM)
305 return builtin_type_ia64_ext;
306 else
307 return builtin_type_long;
308 }
309
310 static int
311 ia64_dwarf_reg_to_regnum (int reg)
312 {
313 if (reg >= IA64_GR32_REGNUM && reg <= IA64_GR127_REGNUM)
314 return V32_REGNUM + (reg - IA64_GR32_REGNUM);
315 return reg;
316 }
317
318 const struct floatformat floatformat_ia64_ext =
319 {
320 floatformat_little, 82, 0, 1, 17, 65535, 0x1ffff, 18, 64,
321 floatformat_intbit_yes
322 };
323
324
325 /* Read the given register from a sigcontext structure in the
326 specified frame. */
327
328 static CORE_ADDR
329 read_sigcontext_register (struct frame_info *frame, int regnum)
330 {
331 CORE_ADDR regaddr;
332
333 if (frame == NULL)
334 internal_error (__FILE__, __LINE__,
335 "read_sigcontext_register: NULL frame");
336 if (!(get_frame_type (frame) == SIGTRAMP_FRAME))
337 internal_error (__FILE__, __LINE__,
338 "read_sigcontext_register: frame not a signal trampoline");
339 if (SIGCONTEXT_REGISTER_ADDRESS == 0)
340 internal_error (__FILE__, __LINE__,
341 "read_sigcontext_register: SIGCONTEXT_REGISTER_ADDRESS is 0");
342
343 regaddr = SIGCONTEXT_REGISTER_ADDRESS (get_frame_base (frame), regnum);
344 if (regaddr)
345 return read_memory_integer (regaddr, REGISTER_RAW_SIZE (regnum));
346 else
347 internal_error (__FILE__, __LINE__,
348 "read_sigcontext_register: Register %d not in struct sigcontext", regnum);
349 }
350
351 /* Extract ``len'' bits from an instruction bundle starting at
352 bit ``from''. */
353
354 static long long
355 extract_bit_field (char *bundle, int from, int len)
356 {
357 long long result = 0LL;
358 int to = from + len;
359 int from_byte = from / 8;
360 int to_byte = to / 8;
361 unsigned char *b = (unsigned char *) bundle;
362 unsigned char c;
363 int lshift;
364 int i;
365
366 c = b[from_byte];
367 if (from_byte == to_byte)
368 c = ((unsigned char) (c << (8 - to % 8))) >> (8 - to % 8);
369 result = c >> (from % 8);
370 lshift = 8 - (from % 8);
371
372 for (i = from_byte+1; i < to_byte; i++)
373 {
374 result |= ((long long) b[i]) << lshift;
375 lshift += 8;
376 }
377
378 if (from_byte < to_byte && (to % 8 != 0))
379 {
380 c = b[to_byte];
381 c = ((unsigned char) (c << (8 - to % 8))) >> (8 - to % 8);
382 result |= ((long long) c) << lshift;
383 }
384
385 return result;
386 }
387
388 /* Replace the specified bits in an instruction bundle */
389
390 static void
391 replace_bit_field (char *bundle, long long val, int from, int len)
392 {
393 int to = from + len;
394 int from_byte = from / 8;
395 int to_byte = to / 8;
396 unsigned char *b = (unsigned char *) bundle;
397 unsigned char c;
398
399 if (from_byte == to_byte)
400 {
401 unsigned char left, right;
402 c = b[from_byte];
403 left = (c >> (to % 8)) << (to % 8);
404 right = ((unsigned char) (c << (8 - from % 8))) >> (8 - from % 8);
405 c = (unsigned char) (val & 0xff);
406 c = (unsigned char) (c << (from % 8 + 8 - to % 8)) >> (8 - to % 8);
407 c |= right | left;
408 b[from_byte] = c;
409 }
410 else
411 {
412 int i;
413 c = b[from_byte];
414 c = ((unsigned char) (c << (8 - from % 8))) >> (8 - from % 8);
415 c = c | (val << (from % 8));
416 b[from_byte] = c;
417 val >>= 8 - from % 8;
418
419 for (i = from_byte+1; i < to_byte; i++)
420 {
421 c = val & 0xff;
422 val >>= 8;
423 b[i] = c;
424 }
425
426 if (to % 8 != 0)
427 {
428 unsigned char cv = (unsigned char) val;
429 c = b[to_byte];
430 c = c >> (to % 8) << (to % 8);
431 c |= ((unsigned char) (cv << (8 - to % 8))) >> (8 - to % 8);
432 b[to_byte] = c;
433 }
434 }
435 }
436
437 /* Return the contents of slot N (for N = 0, 1, or 2) in
438 and instruction bundle */
439
440 static long long
441 slotN_contents (char *bundle, int slotnum)
442 {
443 return extract_bit_field (bundle, 5+41*slotnum, 41);
444 }
445
446 /* Store an instruction in an instruction bundle */
447
448 static void
449 replace_slotN_contents (char *bundle, long long instr, int slotnum)
450 {
451 replace_bit_field (bundle, instr, 5+41*slotnum, 41);
452 }
453
454 static enum instruction_type template_encoding_table[32][3] =
455 {
456 { M, I, I }, /* 00 */
457 { M, I, I }, /* 01 */
458 { M, I, I }, /* 02 */
459 { M, I, I }, /* 03 */
460 { M, L, X }, /* 04 */
461 { M, L, X }, /* 05 */
462 { undefined, undefined, undefined }, /* 06 */
463 { undefined, undefined, undefined }, /* 07 */
464 { M, M, I }, /* 08 */
465 { M, M, I }, /* 09 */
466 { M, M, I }, /* 0A */
467 { M, M, I }, /* 0B */
468 { M, F, I }, /* 0C */
469 { M, F, I }, /* 0D */
470 { M, M, F }, /* 0E */
471 { M, M, F }, /* 0F */
472 { M, I, B }, /* 10 */
473 { M, I, B }, /* 11 */
474 { M, B, B }, /* 12 */
475 { M, B, B }, /* 13 */
476 { undefined, undefined, undefined }, /* 14 */
477 { undefined, undefined, undefined }, /* 15 */
478 { B, B, B }, /* 16 */
479 { B, B, B }, /* 17 */
480 { M, M, B }, /* 18 */
481 { M, M, B }, /* 19 */
482 { undefined, undefined, undefined }, /* 1A */
483 { undefined, undefined, undefined }, /* 1B */
484 { M, F, B }, /* 1C */
485 { M, F, B }, /* 1D */
486 { undefined, undefined, undefined }, /* 1E */
487 { undefined, undefined, undefined }, /* 1F */
488 };
489
490 /* Fetch and (partially) decode an instruction at ADDR and return the
491 address of the next instruction to fetch. */
492
493 static CORE_ADDR
494 fetch_instruction (CORE_ADDR addr, instruction_type *it, long long *instr)
495 {
496 char bundle[BUNDLE_LEN];
497 int slotnum = (int) (addr & 0x0f) / SLOT_MULTIPLIER;
498 long long template;
499 int val;
500
501 /* Warn about slot numbers greater than 2. We used to generate
502 an error here on the assumption that the user entered an invalid
503 address. But, sometimes GDB itself requests an invalid address.
504 This can (easily) happen when execution stops in a function for
505 which there are no symbols. The prologue scanner will attempt to
506 find the beginning of the function - if the nearest symbol
507 happens to not be aligned on a bundle boundary (16 bytes), the
508 resulting starting address will cause GDB to think that the slot
509 number is too large.
510
511 So we warn about it and set the slot number to zero. It is
512 not necessarily a fatal condition, particularly if debugging
513 at the assembly language level. */
514 if (slotnum > 2)
515 {
516 warning ("Can't fetch instructions for slot numbers greater than 2.\n"
517 "Using slot 0 instead");
518 slotnum = 0;
519 }
520
521 addr &= ~0x0f;
522
523 val = target_read_memory (addr, bundle, BUNDLE_LEN);
524
525 if (val != 0)
526 return 0;
527
528 *instr = slotN_contents (bundle, slotnum);
529 template = extract_bit_field (bundle, 0, 5);
530 *it = template_encoding_table[(int)template][slotnum];
531
532 if (slotnum == 2 || (slotnum == 1 && *it == L))
533 addr += 16;
534 else
535 addr += (slotnum + 1) * SLOT_MULTIPLIER;
536
537 return addr;
538 }
539
540 /* There are 5 different break instructions (break.i, break.b,
541 break.m, break.f, and break.x), but they all have the same
542 encoding. (The five bit template in the low five bits of the
543 instruction bundle distinguishes one from another.)
544
545 The runtime architecture manual specifies that break instructions
546 used for debugging purposes must have the upper two bits of the 21
547 bit immediate set to a 0 and a 1 respectively. A breakpoint
548 instruction encodes the most significant bit of its 21 bit
549 immediate at bit 36 of the 41 bit instruction. The penultimate msb
550 is at bit 25 which leads to the pattern below.
551
552 Originally, I had this set up to do, e.g, a "break.i 0x80000" But
553 it turns out that 0x80000 was used as the syscall break in the early
554 simulators. So I changed the pattern slightly to do "break.i 0x080001"
555 instead. But that didn't work either (I later found out that this
556 pattern was used by the simulator that I was using.) So I ended up
557 using the pattern seen below. */
558
559 #if 0
560 #define IA64_BREAKPOINT 0x00002000040LL
561 #endif
562 #define IA64_BREAKPOINT 0x00003333300LL
563
564 static int
565 ia64_memory_insert_breakpoint (CORE_ADDR addr, char *contents_cache)
566 {
567 char bundle[BUNDLE_LEN];
568 int slotnum = (int) (addr & 0x0f) / SLOT_MULTIPLIER;
569 long long instr;
570 int val;
571 int template;
572
573 if (slotnum > 2)
574 error("Can't insert breakpoint for slot numbers greater than 2.");
575
576 addr &= ~0x0f;
577
578 val = target_read_memory (addr, bundle, BUNDLE_LEN);
579
580 /* Check for L type instruction in 2nd slot, if present then
581 bump up the slot number to the 3rd slot */
582 template = extract_bit_field (bundle, 0, 5);
583 if (slotnum == 1 && template_encoding_table[template][1] == L)
584 {
585 slotnum = 2;
586 }
587
588 instr = slotN_contents (bundle, slotnum);
589 memcpy(contents_cache, &instr, sizeof(instr));
590 replace_slotN_contents (bundle, IA64_BREAKPOINT, slotnum);
591 if (val == 0)
592 target_write_memory (addr, bundle, BUNDLE_LEN);
593
594 return val;
595 }
596
597 static int
598 ia64_memory_remove_breakpoint (CORE_ADDR addr, char *contents_cache)
599 {
600 char bundle[BUNDLE_LEN];
601 int slotnum = (addr & 0x0f) / SLOT_MULTIPLIER;
602 long long instr;
603 int val;
604 int template;
605
606 addr &= ~0x0f;
607
608 val = target_read_memory (addr, bundle, BUNDLE_LEN);
609
610 /* Check for L type instruction in 2nd slot, if present then
611 bump up the slot number to the 3rd slot */
612 template = extract_bit_field (bundle, 0, 5);
613 if (slotnum == 1 && template_encoding_table[template][1] == L)
614 {
615 slotnum = 2;
616 }
617
618 memcpy (&instr, contents_cache, sizeof instr);
619 replace_slotN_contents (bundle, instr, slotnum);
620 if (val == 0)
621 target_write_memory (addr, bundle, BUNDLE_LEN);
622
623 return val;
624 }
625
626 /* We don't really want to use this, but remote.c needs to call it in order
627 to figure out if Z-packets are supported or not. Oh, well. */
628 const unsigned char *
629 ia64_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
630 {
631 static unsigned char breakpoint[] =
632 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
633 *lenptr = sizeof (breakpoint);
634 #if 0
635 *pcptr &= ~0x0f;
636 #endif
637 return breakpoint;
638 }
639
640 static CORE_ADDR
641 ia64_read_fp (void)
642 {
643 /* We won't necessarily have a frame pointer and even if we do, it
644 winds up being extraordinarly messy when attempting to find the
645 frame chain. So for the purposes of creating frames (which is
646 all deprecated_read_fp() is used for), simply use the stack
647 pointer value instead. */
648 gdb_assert (SP_REGNUM >= 0);
649 return read_register (SP_REGNUM);
650 }
651
652 static CORE_ADDR
653 ia64_read_pc (ptid_t ptid)
654 {
655 CORE_ADDR psr_value = read_register_pid (IA64_PSR_REGNUM, ptid);
656 CORE_ADDR pc_value = read_register_pid (IA64_IP_REGNUM, ptid);
657 int slot_num = (psr_value >> 41) & 3;
658
659 return pc_value | (slot_num * SLOT_MULTIPLIER);
660 }
661
662 static void
663 ia64_write_pc (CORE_ADDR new_pc, ptid_t ptid)
664 {
665 int slot_num = (int) (new_pc & 0xf) / SLOT_MULTIPLIER;
666 CORE_ADDR psr_value = read_register_pid (IA64_PSR_REGNUM, ptid);
667 psr_value &= ~(3LL << 41);
668 psr_value |= (CORE_ADDR)(slot_num & 0x3) << 41;
669
670 new_pc &= ~0xfLL;
671
672 write_register_pid (IA64_PSR_REGNUM, psr_value, ptid);
673 write_register_pid (IA64_IP_REGNUM, new_pc, ptid);
674 }
675
676 #define IS_NaT_COLLECTION_ADDR(addr) ((((addr) >> 3) & 0x3f) == 0x3f)
677
678 /* Returns the address of the slot that's NSLOTS slots away from
679 the address ADDR. NSLOTS may be positive or negative. */
680 static CORE_ADDR
681 rse_address_add(CORE_ADDR addr, int nslots)
682 {
683 CORE_ADDR new_addr;
684 int mandatory_nat_slots = nslots / 63;
685 int direction = nslots < 0 ? -1 : 1;
686
687 new_addr = addr + 8 * (nslots + mandatory_nat_slots);
688
689 if ((new_addr >> 9) != ((addr + 8 * 64 * mandatory_nat_slots) >> 9))
690 new_addr += 8 * direction;
691
692 if (IS_NaT_COLLECTION_ADDR(new_addr))
693 new_addr += 8 * direction;
694
695 return new_addr;
696 }
697
698 static void
699 ia64_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
700 int regnum, void *buf)
701 {
702 if (regnum >= V32_REGNUM && regnum <= V127_REGNUM)
703 {
704 ULONGEST bsp;
705 ULONGEST cfm;
706 CORE_ADDR reg;
707 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
708 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
709
710 /* The bsp points at the end of the register frame so we
711 subtract the size of frame from it to get start of register frame. */
712 bsp = rse_address_add (bsp, -(cfm & 0x7f));
713
714 if ((cfm & 0x7f) > regnum - V32_REGNUM)
715 {
716 ULONGEST reg_addr = rse_address_add (bsp, (regnum - V32_REGNUM));
717 reg = read_memory_integer ((CORE_ADDR)reg_addr, 8);
718 store_unsigned_integer (buf, REGISTER_RAW_SIZE (regnum), reg);
719 }
720 else
721 store_unsigned_integer (buf, REGISTER_RAW_SIZE (regnum), 0);
722 }
723 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT31_REGNUM)
724 {
725 ULONGEST unatN_val;
726 ULONGEST unat;
727 regcache_cooked_read_unsigned (regcache, IA64_UNAT_REGNUM, &unat);
728 unatN_val = (unat & (1LL << (regnum - IA64_NAT0_REGNUM))) != 0;
729 store_unsigned_integer (buf, REGISTER_RAW_SIZE (regnum), unatN_val);
730 }
731 else if (IA64_NAT32_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
732 {
733 ULONGEST natN_val = 0;
734 ULONGEST bsp;
735 ULONGEST cfm;
736 CORE_ADDR gr_addr = 0;
737 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
738 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
739
740 /* The bsp points at the end of the register frame so we
741 subtract the size of frame from it to get start of register frame. */
742 bsp = rse_address_add (bsp, -(cfm & 0x7f));
743
744 if ((cfm & 0x7f) > regnum - V32_REGNUM)
745 gr_addr = rse_address_add (bsp, (regnum - V32_REGNUM));
746
747 if (gr_addr != 0)
748 {
749 /* Compute address of nat collection bits. */
750 CORE_ADDR nat_addr = gr_addr | 0x1f8;
751 CORE_ADDR nat_collection;
752 int nat_bit;
753 /* If our nat collection address is bigger than bsp, we have to get
754 the nat collection from rnat. Otherwise, we fetch the nat
755 collection from the computed address. */
756 if (nat_addr >= bsp)
757 regcache_cooked_read_unsigned (regcache, IA64_RNAT_REGNUM, &nat_collection);
758 else
759 nat_collection = read_memory_integer (nat_addr, 8);
760 nat_bit = (gr_addr >> 3) & 0x3f;
761 natN_val = (nat_collection >> nat_bit) & 1;
762 }
763
764 store_unsigned_integer (buf, REGISTER_RAW_SIZE (regnum), natN_val);
765 }
766 else if (regnum == VBOF_REGNUM)
767 {
768 /* A virtual register frame start is provided for user convenience.
769 It can be calculated as the bsp - sof (sizeof frame). */
770 ULONGEST bsp, vbsp;
771 ULONGEST cfm;
772 CORE_ADDR reg;
773 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
774 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
775
776 /* The bsp points at the end of the register frame so we
777 subtract the size of frame from it to get beginning of frame. */
778 vbsp = rse_address_add (bsp, -(cfm & 0x7f));
779 store_unsigned_integer (buf, REGISTER_RAW_SIZE (regnum), vbsp);
780 }
781 else if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
782 {
783 ULONGEST pr;
784 ULONGEST cfm;
785 ULONGEST prN_val;
786 CORE_ADDR reg;
787 regcache_cooked_read_unsigned (regcache, IA64_PR_REGNUM, &pr);
788 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
789
790 if (VP16_REGNUM <= regnum && regnum <= VP63_REGNUM)
791 {
792 /* Fetch predicate register rename base from current frame
793 marker for this frame. */
794 int rrb_pr = (cfm >> 32) & 0x3f;
795
796 /* Adjust the register number to account for register rotation. */
797 regnum = VP16_REGNUM
798 + ((regnum - VP16_REGNUM) + rrb_pr) % 48;
799 }
800 prN_val = (pr & (1LL << (regnum - VP0_REGNUM))) != 0;
801 store_unsigned_integer (buf, REGISTER_RAW_SIZE (regnum), prN_val);
802 }
803 else
804 memset (buf, 0, REGISTER_RAW_SIZE (regnum));
805 }
806
807 static void
808 ia64_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
809 int regnum, const void *buf)
810 {
811 if (regnum >= V32_REGNUM && regnum <= V127_REGNUM)
812 {
813 ULONGEST bsp;
814 ULONGEST cfm;
815 CORE_ADDR reg;
816 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
817 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
818
819 bsp = rse_address_add (bsp, -(cfm & 0x7f));
820
821 if ((cfm & 0x7f) > regnum - V32_REGNUM)
822 {
823 ULONGEST reg_addr = rse_address_add (bsp, (regnum - V32_REGNUM));
824 write_memory (reg_addr, (void *)buf, 8);
825 }
826 }
827 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT31_REGNUM)
828 {
829 ULONGEST unatN_val, unat, unatN_mask;
830 regcache_cooked_read_unsigned (regcache, IA64_UNAT_REGNUM, &unat);
831 unatN_val = extract_unsigned_integer (buf, REGISTER_RAW_SIZE (regnum));
832 unatN_mask = (1LL << (regnum - IA64_NAT0_REGNUM));
833 if (unatN_val == 0)
834 unat &= ~unatN_mask;
835 else if (unatN_val == 1)
836 unat |= unatN_mask;
837 regcache_cooked_write_unsigned (regcache, IA64_UNAT_REGNUM, unat);
838 }
839 else if (IA64_NAT32_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
840 {
841 ULONGEST natN_val;
842 ULONGEST bsp;
843 ULONGEST cfm;
844 CORE_ADDR gr_addr = 0;
845 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
846 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
847
848 /* The bsp points at the end of the register frame so we
849 subtract the size of frame from it to get start of register frame. */
850 bsp = rse_address_add (bsp, -(cfm & 0x7f));
851
852 if ((cfm & 0x7f) > regnum - V32_REGNUM)
853 gr_addr = rse_address_add (bsp, (regnum - V32_REGNUM));
854
855 natN_val = extract_unsigned_integer (buf, REGISTER_RAW_SIZE (regnum));
856
857 if (gr_addr != 0 && (natN_val == 0 || natN_val == 1))
858 {
859 /* Compute address of nat collection bits. */
860 CORE_ADDR nat_addr = gr_addr | 0x1f8;
861 CORE_ADDR nat_collection;
862 int natN_bit = (gr_addr >> 3) & 0x3f;
863 ULONGEST natN_mask = (1LL << natN_bit);
864 /* If our nat collection address is bigger than bsp, we have to get
865 the nat collection from rnat. Otherwise, we fetch the nat
866 collection from the computed address. */
867 if (nat_addr >= bsp)
868 {
869 regcache_cooked_read_unsigned (regcache, IA64_RNAT_REGNUM, &nat_collection);
870 if (natN_val)
871 nat_collection |= natN_mask;
872 else
873 nat_collection &= ~natN_mask;
874 regcache_cooked_write_unsigned (regcache, IA64_RNAT_REGNUM, nat_collection);
875 }
876 else
877 {
878 char nat_buf[8];
879 nat_collection = read_memory_integer (nat_addr, 8);
880 if (natN_val)
881 nat_collection |= natN_mask;
882 else
883 nat_collection &= ~natN_mask;
884 store_unsigned_integer (nat_buf, REGISTER_RAW_SIZE (regnum), nat_collection);
885 write_memory (nat_addr, nat_buf, 8);
886 }
887 }
888 }
889 else if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
890 {
891 ULONGEST pr;
892 ULONGEST cfm;
893 ULONGEST prN_val;
894 ULONGEST prN_mask;
895
896 regcache_cooked_read_unsigned (regcache, IA64_PR_REGNUM, &pr);
897 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
898
899 if (VP16_REGNUM <= regnum && regnum <= VP63_REGNUM)
900 {
901 /* Fetch predicate register rename base from current frame
902 marker for this frame. */
903 int rrb_pr = (cfm >> 32) & 0x3f;
904
905 /* Adjust the register number to account for register rotation. */
906 regnum = VP16_REGNUM
907 + ((regnum - VP16_REGNUM) + rrb_pr) % 48;
908 }
909 prN_val = extract_unsigned_integer (buf, REGISTER_RAW_SIZE (regnum));
910 prN_mask = (1LL << (regnum - VP0_REGNUM));
911 if (prN_val == 0)
912 pr &= ~prN_mask;
913 else if (prN_val == 1)
914 pr |= prN_mask;
915 regcache_cooked_write_unsigned (regcache, IA64_PR_REGNUM, pr);
916 }
917 }
918
919 /* The ia64 needs to convert between various ieee floating-point formats
920 and the special ia64 floating point register format. */
921
922 static int
923 ia64_convert_register_p (int regno, struct type *type)
924 {
925 return (regno >= IA64_FR0_REGNUM && regno <= IA64_FR127_REGNUM);
926 }
927
928 static void
929 ia64_register_to_value (struct frame_info *frame, int regnum,
930 struct type *valtype, void *out)
931 {
932 char in[MAX_REGISTER_SIZE];
933 frame_register_read (frame, regnum, in);
934 convert_typed_floating (in, builtin_type_ia64_ext, out, valtype);
935 }
936
937 static void
938 ia64_value_to_register (struct frame_info *frame, int regnum,
939 struct type *valtype, const void *in)
940 {
941 char out[MAX_REGISTER_SIZE];
942 convert_typed_floating (in, valtype, out, builtin_type_ia64_ext);
943 put_frame_register (frame, regnum, out);
944 }
945
946
947 /* Limit the number of skipped non-prologue instructions since examining
948 of the prologue is expensive. */
949 static int max_skip_non_prologue_insns = 40;
950
951 /* Given PC representing the starting address of a function, and
952 LIM_PC which is the (sloppy) limit to which to scan when looking
953 for a prologue, attempt to further refine this limit by using
954 the line data in the symbol table. If successful, a better guess
955 on where the prologue ends is returned, otherwise the previous
956 value of lim_pc is returned. TRUST_LIMIT is a pointer to a flag
957 which will be set to indicate whether the returned limit may be
958 used with no further scanning in the event that the function is
959 frameless. */
960
961 static CORE_ADDR
962 refine_prologue_limit (CORE_ADDR pc, CORE_ADDR lim_pc, int *trust_limit)
963 {
964 struct symtab_and_line prologue_sal;
965 CORE_ADDR start_pc = pc;
966
967 /* Start off not trusting the limit. */
968 *trust_limit = 0;
969
970 prologue_sal = find_pc_line (pc, 0);
971 if (prologue_sal.line != 0)
972 {
973 int i;
974 CORE_ADDR addr = prologue_sal.end;
975
976 /* Handle the case in which compiler's optimizer/scheduler
977 has moved instructions into the prologue. We scan ahead
978 in the function looking for address ranges whose corresponding
979 line number is less than or equal to the first one that we
980 found for the function. (It can be less than when the
981 scheduler puts a body instruction before the first prologue
982 instruction.) */
983 for (i = 2 * max_skip_non_prologue_insns;
984 i > 0 && (lim_pc == 0 || addr < lim_pc);
985 i--)
986 {
987 struct symtab_and_line sal;
988
989 sal = find_pc_line (addr, 0);
990 if (sal.line == 0)
991 break;
992 if (sal.line <= prologue_sal.line
993 && sal.symtab == prologue_sal.symtab)
994 {
995 prologue_sal = sal;
996 }
997 addr = sal.end;
998 }
999
1000 if (lim_pc == 0 || prologue_sal.end < lim_pc)
1001 {
1002 lim_pc = prologue_sal.end;
1003 if (start_pc == get_pc_function_start (lim_pc))
1004 *trust_limit = 1;
1005 }
1006 }
1007 return lim_pc;
1008 }
1009
1010 #define isScratch(_regnum_) ((_regnum_) == 2 || (_regnum_) == 3 \
1011 || (8 <= (_regnum_) && (_regnum_) <= 11) \
1012 || (14 <= (_regnum_) && (_regnum_) <= 31))
1013 #define imm9(_instr_) \
1014 ( ((((_instr_) & 0x01000000000LL) ? -1 : 0) << 8) \
1015 | (((_instr_) & 0x00008000000LL) >> 20) \
1016 | (((_instr_) & 0x00000001fc0LL) >> 6))
1017
1018 /* Allocate and initialize a frame cache. */
1019
1020 static struct ia64_frame_cache *
1021 ia64_alloc_frame_cache (void)
1022 {
1023 struct ia64_frame_cache *cache;
1024 int i;
1025
1026 cache = FRAME_OBSTACK_ZALLOC (struct ia64_frame_cache);
1027
1028 /* Base address. */
1029 cache->base = 0;
1030 cache->pc = 0;
1031 cache->cfm = 0;
1032 cache->sof = 0;
1033 cache->sol = 0;
1034 cache->sor = 0;
1035 cache->bsp = 0;
1036 cache->fp_reg = 0;
1037 cache->frameless = 1;
1038
1039 for (i = 0; i < NUM_IA64_RAW_REGS; i++)
1040 cache->saved_regs[i] = 0;
1041
1042 return cache;
1043 }
1044
1045 static CORE_ADDR
1046 examine_prologue (CORE_ADDR pc, CORE_ADDR lim_pc, struct frame_info *next_frame, struct ia64_frame_cache *cache)
1047 {
1048 CORE_ADDR next_pc;
1049 CORE_ADDR last_prologue_pc = pc;
1050 instruction_type it;
1051 long long instr;
1052 int cfm_reg = 0;
1053 int ret_reg = 0;
1054 int fp_reg = 0;
1055 int unat_save_reg = 0;
1056 int pr_save_reg = 0;
1057 int mem_stack_frame_size = 0;
1058 int spill_reg = 0;
1059 CORE_ADDR spill_addr = 0;
1060 char instores[8];
1061 char infpstores[8];
1062 char reg_contents[256];
1063 int trust_limit;
1064 int frameless = 1;
1065 int i;
1066 CORE_ADDR addr;
1067 char buf[8];
1068 CORE_ADDR bof, sor, sol, sof, cfm, rrb_gr;
1069
1070 memset (instores, 0, sizeof instores);
1071 memset (infpstores, 0, sizeof infpstores);
1072 memset (reg_contents, 0, sizeof reg_contents);
1073
1074 if (cache->after_prologue != 0
1075 && cache->after_prologue <= lim_pc)
1076 return cache->after_prologue;
1077
1078 lim_pc = refine_prologue_limit (pc, lim_pc, &trust_limit);
1079 next_pc = fetch_instruction (pc, &it, &instr);
1080
1081 /* We want to check if we have a recognizable function start before we
1082 look ahead for a prologue. */
1083 if (pc < lim_pc && next_pc
1084 && it == M && ((instr & 0x1ee0000003fLL) == 0x02c00000000LL))
1085 {
1086 /* alloc - start of a regular function. */
1087 int sor = (int) ((instr & 0x00078000000LL) >> 27);
1088 int sol = (int) ((instr & 0x00007f00000LL) >> 20);
1089 int sof = (int) ((instr & 0x000000fe000LL) >> 13);
1090 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1091
1092 /* Verify that the current cfm matches what we think is the
1093 function start. If we have somehow jumped within a function,
1094 we do not want to interpret the prologue and calculate the
1095 addresses of various registers such as the return address.
1096 We will instead treat the frame as frameless. */
1097 if (!next_frame ||
1098 (sof == (cache->cfm & 0x7f) &&
1099 sol == ((cache->cfm >> 7) & 0x7f)))
1100 frameless = 0;
1101
1102 cfm_reg = rN;
1103 last_prologue_pc = next_pc;
1104 pc = next_pc;
1105 }
1106 else
1107 {
1108 /* Look for a leaf routine. */
1109 if (pc < lim_pc && next_pc
1110 && (it == I || it == M)
1111 && ((instr & 0x1ee00000000LL) == 0x10800000000LL))
1112 {
1113 /* adds rN = imm14, rM (or mov rN, rM when imm14 is 0) */
1114 int imm = (int) ((((instr & 0x01000000000LL) ? -1 : 0) << 13)
1115 | ((instr & 0x001f8000000LL) >> 20)
1116 | ((instr & 0x000000fe000LL) >> 13));
1117 int rM = (int) ((instr & 0x00007f00000LL) >> 20);
1118 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1119 int qp = (int) (instr & 0x0000000003fLL);
1120 if (qp == 0 && rN == 2 && imm == 0 && rM == 12 && fp_reg == 0)
1121 {
1122 /* mov r2, r12 - beginning of leaf routine */
1123 fp_reg = rN;
1124 last_prologue_pc = next_pc;
1125 }
1126 }
1127
1128 /* If we don't recognize a regular function or leaf routine, we are
1129 done. */
1130 if (!fp_reg)
1131 {
1132 pc = lim_pc;
1133 if (trust_limit)
1134 last_prologue_pc = lim_pc;
1135 }
1136 }
1137
1138 /* Loop, looking for prologue instructions, keeping track of
1139 where preserved registers were spilled. */
1140 while (pc < lim_pc)
1141 {
1142 next_pc = fetch_instruction (pc, &it, &instr);
1143 if (next_pc == 0)
1144 break;
1145
1146 if (it == B && ((instr & 0x1e1f800003f) != 0x04000000000))
1147 {
1148 /* Exit loop upon hitting a non-nop branch instruction. */
1149 if (trust_limit)
1150 lim_pc = pc;
1151 break;
1152 }
1153 else if (((instr & 0x3fLL) != 0LL) &&
1154 (frameless || ret_reg != 0))
1155 {
1156 /* Exit loop upon hitting a predicated instruction if
1157 we already have the return register or if we are frameless. */
1158 if (trust_limit)
1159 lim_pc = pc;
1160 break;
1161 }
1162 else if (it == I && ((instr & 0x1eff8000000LL) == 0x00188000000LL))
1163 {
1164 /* Move from BR */
1165 int b2 = (int) ((instr & 0x0000000e000LL) >> 13);
1166 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1167 int qp = (int) (instr & 0x0000000003f);
1168
1169 if (qp == 0 && b2 == 0 && rN >= 32 && ret_reg == 0)
1170 {
1171 ret_reg = rN;
1172 last_prologue_pc = next_pc;
1173 }
1174 }
1175 else if ((it == I || it == M)
1176 && ((instr & 0x1ee00000000LL) == 0x10800000000LL))
1177 {
1178 /* adds rN = imm14, rM (or mov rN, rM when imm14 is 0) */
1179 int imm = (int) ((((instr & 0x01000000000LL) ? -1 : 0) << 13)
1180 | ((instr & 0x001f8000000LL) >> 20)
1181 | ((instr & 0x000000fe000LL) >> 13));
1182 int rM = (int) ((instr & 0x00007f00000LL) >> 20);
1183 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1184 int qp = (int) (instr & 0x0000000003fLL);
1185
1186 if (qp == 0 && rN >= 32 && imm == 0 && rM == 12 && fp_reg == 0)
1187 {
1188 /* mov rN, r12 */
1189 fp_reg = rN;
1190 last_prologue_pc = next_pc;
1191 }
1192 else if (qp == 0 && rN == 12 && rM == 12)
1193 {
1194 /* adds r12, -mem_stack_frame_size, r12 */
1195 mem_stack_frame_size -= imm;
1196 last_prologue_pc = next_pc;
1197 }
1198 else if (qp == 0 && rN == 2
1199 && ((rM == fp_reg && fp_reg != 0) || rM == 12))
1200 {
1201 char buf[MAX_REGISTER_SIZE];
1202 CORE_ADDR saved_sp = 0;
1203 /* adds r2, spilloffset, rFramePointer
1204 or
1205 adds r2, spilloffset, r12
1206
1207 Get ready for stf.spill or st8.spill instructions.
1208 The address to start spilling at is loaded into r2.
1209 FIXME: Why r2? That's what gcc currently uses; it
1210 could well be different for other compilers. */
1211
1212 /* Hmm... whether or not this will work will depend on
1213 where the pc is. If it's still early in the prologue
1214 this'll be wrong. FIXME */
1215 if (next_frame)
1216 {
1217 frame_unwind_register (next_frame, sp_regnum, buf);
1218 saved_sp = extract_unsigned_integer (buf, 8);
1219 }
1220 spill_addr = saved_sp
1221 + (rM == 12 ? 0 : mem_stack_frame_size)
1222 + imm;
1223 spill_reg = rN;
1224 last_prologue_pc = next_pc;
1225 }
1226 else if (qp == 0 && rM >= 32 && rM < 40 && !instores[rM] &&
1227 rN < 256 && imm == 0)
1228 {
1229 /* mov rN, rM where rM is an input register */
1230 reg_contents[rN] = rM;
1231 last_prologue_pc = next_pc;
1232 }
1233 else if (frameless && qp == 0 && rN == fp_reg && imm == 0 &&
1234 rM == 2)
1235 {
1236 /* mov r12, r2 */
1237 last_prologue_pc = next_pc;
1238 break;
1239 }
1240 }
1241 else if (it == M
1242 && ( ((instr & 0x1efc0000000LL) == 0x0eec0000000LL)
1243 || ((instr & 0x1ffc8000000LL) == 0x0cec0000000LL) ))
1244 {
1245 /* stf.spill [rN] = fM, imm9
1246 or
1247 stf.spill [rN] = fM */
1248
1249 int imm = imm9(instr);
1250 int rN = (int) ((instr & 0x00007f00000LL) >> 20);
1251 int fM = (int) ((instr & 0x000000fe000LL) >> 13);
1252 int qp = (int) (instr & 0x0000000003fLL);
1253 if (qp == 0 && rN == spill_reg && spill_addr != 0
1254 && ((2 <= fM && fM <= 5) || (16 <= fM && fM <= 31)))
1255 {
1256 cache->saved_regs[IA64_FR0_REGNUM + fM] = spill_addr;
1257
1258 if ((instr & 0x1efc0000000) == 0x0eec0000000)
1259 spill_addr += imm;
1260 else
1261 spill_addr = 0; /* last one; must be done */
1262 last_prologue_pc = next_pc;
1263 }
1264 }
1265 else if ((it == M && ((instr & 0x1eff8000000LL) == 0x02110000000LL))
1266 || (it == I && ((instr & 0x1eff8000000LL) == 0x00050000000LL)) )
1267 {
1268 /* mov.m rN = arM
1269 or
1270 mov.i rN = arM */
1271
1272 int arM = (int) ((instr & 0x00007f00000LL) >> 20);
1273 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1274 int qp = (int) (instr & 0x0000000003fLL);
1275 if (qp == 0 && isScratch (rN) && arM == 36 /* ar.unat */)
1276 {
1277 /* We have something like "mov.m r3 = ar.unat". Remember the
1278 r3 (or whatever) and watch for a store of this register... */
1279 unat_save_reg = rN;
1280 last_prologue_pc = next_pc;
1281 }
1282 }
1283 else if (it == I && ((instr & 0x1eff8000000LL) == 0x00198000000LL))
1284 {
1285 /* mov rN = pr */
1286 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1287 int qp = (int) (instr & 0x0000000003fLL);
1288 if (qp == 0 && isScratch (rN))
1289 {
1290 pr_save_reg = rN;
1291 last_prologue_pc = next_pc;
1292 }
1293 }
1294 else if (it == M
1295 && ( ((instr & 0x1ffc8000000LL) == 0x08cc0000000LL)
1296 || ((instr & 0x1efc0000000LL) == 0x0acc0000000LL)))
1297 {
1298 /* st8 [rN] = rM
1299 or
1300 st8 [rN] = rM, imm9 */
1301 int rN = (int) ((instr & 0x00007f00000LL) >> 20);
1302 int rM = (int) ((instr & 0x000000fe000LL) >> 13);
1303 int qp = (int) (instr & 0x0000000003fLL);
1304 int indirect = rM < 256 ? reg_contents[rM] : 0;
1305 if (qp == 0 && rN == spill_reg && spill_addr != 0
1306 && (rM == unat_save_reg || rM == pr_save_reg))
1307 {
1308 /* We've found a spill of either the UNAT register or the PR
1309 register. (Well, not exactly; what we've actually found is
1310 a spill of the register that UNAT or PR was moved to).
1311 Record that fact and move on... */
1312 if (rM == unat_save_reg)
1313 {
1314 /* Track UNAT register */
1315 cache->saved_regs[IA64_UNAT_REGNUM] = spill_addr;
1316 unat_save_reg = 0;
1317 }
1318 else
1319 {
1320 /* Track PR register */
1321 cache->saved_regs[IA64_PR_REGNUM] = spill_addr;
1322 pr_save_reg = 0;
1323 }
1324 if ((instr & 0x1efc0000000LL) == 0x0acc0000000LL)
1325 /* st8 [rN] = rM, imm9 */
1326 spill_addr += imm9(instr);
1327 else
1328 spill_addr = 0; /* must be done spilling */
1329 last_prologue_pc = next_pc;
1330 }
1331 else if (qp == 0 && 32 <= rM && rM < 40 && !instores[rM-32])
1332 {
1333 /* Allow up to one store of each input register. */
1334 instores[rM-32] = 1;
1335 last_prologue_pc = next_pc;
1336 }
1337 else if (qp == 0 && 32 <= indirect && indirect < 40 &&
1338 !instores[indirect-32])
1339 {
1340 /* Allow an indirect store of an input register. */
1341 instores[indirect-32] = 1;
1342 last_prologue_pc = next_pc;
1343 }
1344 }
1345 else if (it == M && ((instr & 0x1ff08000000LL) == 0x08c00000000LL))
1346 {
1347 /* One of
1348 st1 [rN] = rM
1349 st2 [rN] = rM
1350 st4 [rN] = rM
1351 st8 [rN] = rM
1352 Note that the st8 case is handled in the clause above.
1353
1354 Advance over stores of input registers. One store per input
1355 register is permitted. */
1356 int rM = (int) ((instr & 0x000000fe000LL) >> 13);
1357 int qp = (int) (instr & 0x0000000003fLL);
1358 int indirect = rM < 256 ? reg_contents[rM] : 0;
1359 if (qp == 0 && 32 <= rM && rM < 40 && !instores[rM-32])
1360 {
1361 instores[rM-32] = 1;
1362 last_prologue_pc = next_pc;
1363 }
1364 else if (qp == 0 && 32 <= indirect && indirect < 40 &&
1365 !instores[indirect-32])
1366 {
1367 /* Allow an indirect store of an input register. */
1368 instores[indirect-32] = 1;
1369 last_prologue_pc = next_pc;
1370 }
1371 }
1372 else if (it == M && ((instr & 0x1ff88000000LL) == 0x0cc80000000LL))
1373 {
1374 /* Either
1375 stfs [rN] = fM
1376 or
1377 stfd [rN] = fM
1378
1379 Advance over stores of floating point input registers. Again
1380 one store per register is permitted */
1381 int fM = (int) ((instr & 0x000000fe000LL) >> 13);
1382 int qp = (int) (instr & 0x0000000003fLL);
1383 if (qp == 0 && 8 <= fM && fM < 16 && !infpstores[fM - 8])
1384 {
1385 infpstores[fM-8] = 1;
1386 last_prologue_pc = next_pc;
1387 }
1388 }
1389 else if (it == M
1390 && ( ((instr & 0x1ffc8000000LL) == 0x08ec0000000LL)
1391 || ((instr & 0x1efc0000000LL) == 0x0aec0000000LL)))
1392 {
1393 /* st8.spill [rN] = rM
1394 or
1395 st8.spill [rN] = rM, imm9 */
1396 int rN = (int) ((instr & 0x00007f00000LL) >> 20);
1397 int rM = (int) ((instr & 0x000000fe000LL) >> 13);
1398 int qp = (int) (instr & 0x0000000003fLL);
1399 if (qp == 0 && rN == spill_reg && 4 <= rM && rM <= 7)
1400 {
1401 /* We've found a spill of one of the preserved general purpose
1402 regs. Record the spill address and advance the spill
1403 register if appropriate. */
1404 cache->saved_regs[IA64_GR0_REGNUM + rM] = spill_addr;
1405 if ((instr & 0x1efc0000000LL) == 0x0aec0000000LL)
1406 /* st8.spill [rN] = rM, imm9 */
1407 spill_addr += imm9(instr);
1408 else
1409 spill_addr = 0; /* Done spilling */
1410 last_prologue_pc = next_pc;
1411 }
1412 }
1413
1414 pc = next_pc;
1415 }
1416
1417 /* If not frameless and we aren't called by skip_prologue, then we need to calculate
1418 registers for the previous frame which will be needed later. */
1419
1420 if (!frameless && next_frame)
1421 {
1422 /* Extract the size of the rotating portion of the stack
1423 frame and the register rename base from the current
1424 frame marker. */
1425 cfm = cache->cfm;
1426 sor = cache->sor;
1427 sof = cache->sof;
1428 sol = cache->sol;
1429 rrb_gr = (cfm >> 18) & 0x7f;
1430
1431 /* Find the bof (beginning of frame). */
1432 bof = rse_address_add (cache->bsp, -sof);
1433
1434 for (i = 0, addr = bof;
1435 i < sof;
1436 i++, addr += 8)
1437 {
1438 if (IS_NaT_COLLECTION_ADDR (addr))
1439 {
1440 addr += 8;
1441 }
1442 if (i+32 == cfm_reg)
1443 cache->saved_regs[IA64_CFM_REGNUM] = addr;
1444 if (i+32 == ret_reg)
1445 cache->saved_regs[IA64_VRAP_REGNUM] = addr;
1446 if (i+32 == fp_reg)
1447 cache->saved_regs[IA64_VFP_REGNUM] = addr;
1448 }
1449
1450 /* For the previous argument registers we require the previous bof.
1451 If we can't find the previous cfm, then we can do nothing. */
1452 if (cache->saved_regs[IA64_CFM_REGNUM] != 0)
1453 {
1454 cfm = read_memory_integer (cache->saved_regs[IA64_CFM_REGNUM], 8);
1455 sor = ((cfm >> 14) & 0xf) * 8;
1456 sof = (cfm & 0x7f);
1457 sol = (cfm >> 7) & 0x7f;
1458 rrb_gr = (cfm >> 18) & 0x7f;
1459
1460 /* The previous bof only requires subtraction of the sol (size of locals)
1461 due to the overlap between output and input of subsequent frames. */
1462 bof = rse_address_add (bof, -sol);
1463
1464 for (i = 0, addr = bof;
1465 i < sof;
1466 i++, addr += 8)
1467 {
1468 if (IS_NaT_COLLECTION_ADDR (addr))
1469 {
1470 addr += 8;
1471 }
1472 if (i < sor)
1473 cache->saved_regs[IA64_GR32_REGNUM + ((i + (sor - rrb_gr)) % sor)]
1474 = addr;
1475 else
1476 cache->saved_regs[IA64_GR32_REGNUM + i] = addr;
1477 }
1478
1479 }
1480 }
1481
1482 /* Try and trust the lim_pc value whenever possible. */
1483 if (trust_limit && lim_pc >= last_prologue_pc)
1484 last_prologue_pc = lim_pc;
1485
1486 cache->frameless = frameless;
1487 cache->after_prologue = last_prologue_pc;
1488 cache->mem_stack_frame_size = mem_stack_frame_size;
1489 cache->fp_reg = fp_reg;
1490
1491 return last_prologue_pc;
1492 }
1493
1494 CORE_ADDR
1495 ia64_skip_prologue (CORE_ADDR pc)
1496 {
1497 struct ia64_frame_cache cache;
1498 cache.base = 0;
1499 cache.after_prologue = 0;
1500 cache.cfm = 0;
1501 cache.bsp = 0;
1502
1503 /* Call examine_prologue with - as third argument since we don't have a next frame pointer to send. */
1504 return examine_prologue (pc, pc+1024, 0, &cache);
1505 }
1506
1507
1508 /* Normal frames. */
1509
1510 static struct ia64_frame_cache *
1511 ia64_frame_cache (struct frame_info *next_frame, void **this_cache)
1512 {
1513 struct ia64_frame_cache *cache;
1514 char buf[8];
1515 CORE_ADDR cfm, sof, sol, bsp, psr;
1516 int i;
1517
1518 if (*this_cache)
1519 return *this_cache;
1520
1521 cache = ia64_alloc_frame_cache ();
1522 *this_cache = cache;
1523
1524 frame_unwind_register (next_frame, sp_regnum, buf);
1525 cache->saved_sp = extract_unsigned_integer (buf, 8);
1526
1527 /* We always want the bsp to point to the end of frame.
1528 This way, we can always get the beginning of frame (bof)
1529 by subtracting frame size. */
1530 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
1531 cache->bsp = extract_unsigned_integer (buf, 8);
1532
1533 frame_unwind_register (next_frame, IA64_PSR_REGNUM, buf);
1534 psr = extract_unsigned_integer (buf, 8);
1535
1536 frame_unwind_register (next_frame, IA64_CFM_REGNUM, buf);
1537 cfm = extract_unsigned_integer (buf, 8);
1538
1539 cache->sof = (cfm & 0x7f);
1540 cache->sol = (cfm >> 7) & 0x7f;
1541 cache->sor = ((cfm >> 14) & 0xf) * 8;
1542
1543 cache->cfm = cfm;
1544
1545 cache->pc = frame_func_unwind (next_frame);
1546
1547 if (cache->pc != 0)
1548 examine_prologue (cache->pc, frame_pc_unwind (next_frame), next_frame, cache);
1549
1550 cache->base = cache->saved_sp + cache->mem_stack_frame_size;
1551
1552 return cache;
1553 }
1554
1555 static void
1556 ia64_frame_this_id (struct frame_info *next_frame, void **this_cache,
1557 struct frame_id *this_id)
1558 {
1559 struct ia64_frame_cache *cache =
1560 ia64_frame_cache (next_frame, this_cache);
1561
1562 /* This marks the outermost frame. */
1563 if (cache->base == 0)
1564 return;
1565
1566 (*this_id) = frame_id_build (cache->base, cache->pc);
1567 }
1568
1569 static void
1570 ia64_frame_prev_register (struct frame_info *next_frame, void **this_cache,
1571 int regnum, int *optimizedp,
1572 enum lval_type *lvalp, CORE_ADDR *addrp,
1573 int *realnump, void *valuep)
1574 {
1575 struct ia64_frame_cache *cache =
1576 ia64_frame_cache (next_frame, this_cache);
1577 char dummy_valp[MAX_REGISTER_SIZE];
1578 char buf[8];
1579
1580 gdb_assert (regnum >= 0);
1581
1582 if (!target_has_registers)
1583 error ("No registers.");
1584
1585 *optimizedp = 0;
1586 *addrp = 0;
1587 *lvalp = not_lval;
1588 *realnump = -1;
1589
1590 /* Rather than check each time if valuep is non-null, supply a dummy buffer
1591 when valuep is not supplied. */
1592 if (!valuep)
1593 valuep = dummy_valp;
1594
1595 memset (valuep, 0, REGISTER_RAW_SIZE (regnum));
1596
1597 if (regnum == SP_REGNUM)
1598 {
1599 /* Handle SP values for all frames but the topmost. */
1600 store_unsigned_integer (valuep, REGISTER_RAW_SIZE (regnum),
1601 cache->base);
1602 }
1603 else if (regnum == IA64_BSP_REGNUM)
1604 {
1605 char cfm_valuep[MAX_REGISTER_SIZE];
1606 int cfm_optim;
1607 int cfm_realnum;
1608 enum lval_type cfm_lval;
1609 CORE_ADDR cfm_addr;
1610 CORE_ADDR bsp, prev_cfm, prev_bsp;
1611
1612 /* We want to calculate the previous bsp as the end of the previous register stack frame.
1613 This corresponds to what the hardware bsp register will be if we pop the frame
1614 back which is why we might have been called. We know the beginning of the current
1615 frame is cache->bsp - cache->sof. This value in the previous frame points to
1616 the start of the output registers. We can calculate the end of that frame by adding
1617 the size of output (sof (size of frame) - sol (size of locals)). */
1618 ia64_frame_prev_register (next_frame, this_cache, IA64_CFM_REGNUM,
1619 &cfm_optim, &cfm_lval, &cfm_addr, &cfm_realnum, cfm_valuep);
1620 prev_cfm = extract_unsigned_integer (cfm_valuep, 8);
1621
1622 bsp = rse_address_add (cache->bsp, -(cache->sof));
1623 prev_bsp = rse_address_add (bsp, (prev_cfm & 0x7f) - ((prev_cfm >> 7) & 0x7f));
1624
1625 store_unsigned_integer (valuep, REGISTER_RAW_SIZE (regnum),
1626 prev_bsp);
1627 }
1628 else if (regnum == IA64_CFM_REGNUM)
1629 {
1630 CORE_ADDR addr = 0;
1631
1632 if (cache->frameless)
1633 {
1634 CORE_ADDR cfm = 0;
1635 frame_unwind_register (next_frame, IA64_PFS_REGNUM, valuep);
1636 }
1637 else
1638 {
1639 addr = cache->saved_regs[IA64_CFM_REGNUM];
1640 if (addr != 0)
1641 read_memory (addr, valuep, REGISTER_RAW_SIZE (regnum));
1642 }
1643 }
1644 else if (regnum == IA64_VFP_REGNUM)
1645 {
1646 /* If the function in question uses an automatic register (r32-r127)
1647 for the frame pointer, it'll be found by ia64_find_saved_register()
1648 above. If the function lacks one of these frame pointers, we can
1649 still provide a value since we know the size of the frame. */
1650 CORE_ADDR vfp = cache->base;
1651 store_unsigned_integer (valuep, REGISTER_RAW_SIZE (IA64_VFP_REGNUM), vfp);
1652 }
1653 else if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
1654 {
1655 char pr_valuep[MAX_REGISTER_SIZE];
1656 int pr_optim;
1657 int pr_realnum;
1658 enum lval_type pr_lval;
1659 CORE_ADDR pr_addr;
1660 ULONGEST prN_val;
1661 ia64_frame_prev_register (next_frame, this_cache, IA64_PR_REGNUM,
1662 &pr_optim, &pr_lval, &pr_addr, &pr_realnum, pr_valuep);
1663 if (VP16_REGNUM <= regnum && regnum <= VP63_REGNUM)
1664 {
1665 /* Fetch predicate register rename base from current frame
1666 marker for this frame. */
1667 int rrb_pr = (cache->cfm >> 32) & 0x3f;
1668
1669 /* Adjust the register number to account for register rotation. */
1670 regnum = VP16_REGNUM
1671 + ((regnum - VP16_REGNUM) + rrb_pr) % 48;
1672 }
1673 prN_val = extract_bit_field ((unsigned char *) pr_valuep,
1674 regnum - VP0_REGNUM, 1);
1675 store_unsigned_integer (valuep, REGISTER_RAW_SIZE (regnum), prN_val);
1676 }
1677 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT31_REGNUM)
1678 {
1679 char unat_valuep[MAX_REGISTER_SIZE];
1680 int unat_optim;
1681 int unat_realnum;
1682 enum lval_type unat_lval;
1683 CORE_ADDR unat_addr;
1684 ULONGEST unatN_val;
1685 ia64_frame_prev_register (next_frame, this_cache, IA64_UNAT_REGNUM,
1686 &unat_optim, &unat_lval, &unat_addr, &unat_realnum, unat_valuep);
1687 unatN_val = extract_bit_field ((unsigned char *) unat_valuep,
1688 regnum - IA64_NAT0_REGNUM, 1);
1689 store_unsigned_integer (valuep, REGISTER_RAW_SIZE (regnum),
1690 unatN_val);
1691 }
1692 else if (IA64_NAT32_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
1693 {
1694 int natval = 0;
1695 /* Find address of general register corresponding to nat bit we're
1696 interested in. */
1697 CORE_ADDR gr_addr;
1698
1699 gr_addr = cache->saved_regs[regnum - IA64_NAT0_REGNUM
1700 + IA64_GR0_REGNUM];
1701 if (gr_addr != 0)
1702 {
1703 /* Compute address of nat collection bits. */
1704 CORE_ADDR nat_addr = gr_addr | 0x1f8;
1705 CORE_ADDR bsp;
1706 CORE_ADDR nat_collection;
1707 int nat_bit;
1708 /* If our nat collection address is bigger than bsp, we have to get
1709 the nat collection from rnat. Otherwise, we fetch the nat
1710 collection from the computed address. */
1711 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
1712 bsp = extract_unsigned_integer (buf, 8);
1713 if (nat_addr >= bsp)
1714 {
1715 frame_unwind_register (next_frame, IA64_RNAT_REGNUM, buf);
1716 nat_collection = extract_unsigned_integer (buf, 8);
1717 }
1718 else
1719 nat_collection = read_memory_integer (nat_addr, 8);
1720 nat_bit = (gr_addr >> 3) & 0x3f;
1721 natval = (nat_collection >> nat_bit) & 1;
1722 }
1723
1724 store_unsigned_integer (valuep, REGISTER_RAW_SIZE (regnum), natval);
1725 }
1726 else if (regnum == IA64_IP_REGNUM)
1727 {
1728 CORE_ADDR pc = 0;
1729
1730 if (cache->frameless)
1731 {
1732 frame_unwind_register (next_frame, IA64_BR0_REGNUM, buf);
1733 pc = extract_unsigned_integer (buf, 8);
1734 }
1735 else
1736 {
1737 CORE_ADDR addr = cache->saved_regs[IA64_VRAP_REGNUM];
1738 if (addr != 0)
1739 {
1740 read_memory (addr, buf, REGISTER_RAW_SIZE (IA64_IP_REGNUM));
1741 pc = extract_unsigned_integer (buf, 8);
1742 }
1743 }
1744 pc &= ~0xf;
1745 store_unsigned_integer (valuep, 8, pc);
1746 }
1747 else if (regnum == IA64_PSR_REGNUM)
1748 {
1749 ULONGEST slot_num = 0;
1750 CORE_ADDR pc= 0;
1751 CORE_ADDR psr = 0;
1752
1753 frame_unwind_register (next_frame, IA64_PSR_REGNUM, buf);
1754 psr = extract_unsigned_integer (buf, 8);
1755
1756 if (cache->frameless)
1757 {
1758 CORE_ADDR pc;
1759 frame_unwind_register (next_frame, IA64_BR0_REGNUM, buf);
1760 pc = extract_unsigned_integer (buf, 8);
1761 }
1762 else
1763 {
1764 CORE_ADDR addr = cache->saved_regs[IA64_VRAP_REGNUM];
1765 if (addr != 0)
1766 {
1767 read_memory (addr, buf, REGISTER_RAW_SIZE (IA64_IP_REGNUM));
1768 pc = extract_unsigned_integer (buf, 8);
1769 }
1770 }
1771 psr &= ~(3LL << 41);
1772 slot_num = pc & 0x3LL;
1773 psr |= (CORE_ADDR)slot_num << 41;
1774 store_unsigned_integer (valuep, 8, psr);
1775 }
1776 else if ((regnum >= IA64_GR32_REGNUM && regnum <= IA64_GR127_REGNUM) ||
1777 (regnum >= V32_REGNUM && regnum <= V127_REGNUM))
1778 {
1779 CORE_ADDR addr = 0;
1780 if (regnum >= V32_REGNUM)
1781 regnum = IA64_GR32_REGNUM + (regnum - V32_REGNUM);
1782 addr = cache->saved_regs[regnum];
1783 if (addr != 0)
1784 {
1785 *lvalp = lval_memory;
1786 *addrp = addr;
1787 read_memory (addr, valuep, REGISTER_RAW_SIZE (regnum));
1788 }
1789 else if (cache->frameless)
1790 {
1791 char r_valuep[MAX_REGISTER_SIZE];
1792 int r_optim;
1793 int r_realnum;
1794 enum lval_type r_lval;
1795 CORE_ADDR r_addr;
1796 CORE_ADDR prev_cfm, prev_bsp, prev_bof;
1797 CORE_ADDR addr = 0;
1798 if (regnum >= V32_REGNUM)
1799 regnum = IA64_GR32_REGNUM + (regnum - V32_REGNUM);
1800 ia64_frame_prev_register (next_frame, this_cache, IA64_CFM_REGNUM,
1801 &r_optim, &r_lval, &r_addr, &r_realnum, r_valuep);
1802 prev_cfm = extract_unsigned_integer (r_valuep, 8);
1803 ia64_frame_prev_register (next_frame, this_cache, IA64_BSP_REGNUM,
1804 &r_optim, &r_lval, &r_addr, &r_realnum, r_valuep);
1805 prev_bsp = extract_unsigned_integer (r_valuep, 8);
1806 prev_bof = rse_address_add (prev_bsp, -(prev_cfm & 0x7f));
1807
1808 addr = rse_address_add (prev_bof, (regnum - IA64_GR32_REGNUM));
1809 *lvalp = lval_memory;
1810 *addrp = addr;
1811 read_memory (addr, valuep, REGISTER_RAW_SIZE (regnum));
1812 }
1813 }
1814 else
1815 {
1816 CORE_ADDR addr = 0;
1817 if (IA64_FR32_REGNUM <= regnum && regnum <= IA64_FR127_REGNUM)
1818 {
1819 /* Fetch floating point register rename base from current
1820 frame marker for this frame. */
1821 int rrb_fr = (cache->cfm >> 25) & 0x7f;
1822
1823 /* Adjust the floating point register number to account for
1824 register rotation. */
1825 regnum = IA64_FR32_REGNUM
1826 + ((regnum - IA64_FR32_REGNUM) + rrb_fr) % 96;
1827 }
1828
1829 /* If we have stored a memory address, access the register. */
1830 addr = cache->saved_regs[regnum];
1831 if (addr != 0)
1832 {
1833 *lvalp = lval_memory;
1834 *addrp = addr;
1835 read_memory (addr, valuep, REGISTER_RAW_SIZE (regnum));
1836 }
1837 /* Otherwise, punt and get the current value of the register. */
1838 else
1839 frame_unwind_register (next_frame, regnum, valuep);
1840 }
1841 }
1842
1843 static const struct frame_unwind ia64_frame_unwind =
1844 {
1845 NORMAL_FRAME,
1846 &ia64_frame_this_id,
1847 &ia64_frame_prev_register
1848 };
1849
1850 static const struct frame_unwind *
1851 ia64_frame_sniffer (struct frame_info *next_frame)
1852 {
1853 return &ia64_frame_unwind;
1854 }
1855
1856 /* Signal trampolines. */
1857
1858 static void
1859 ia64_sigtramp_frame_init_saved_regs (struct ia64_frame_cache *cache)
1860 {
1861 if (SIGCONTEXT_REGISTER_ADDRESS)
1862 {
1863 int regno;
1864
1865 cache->saved_regs[IA64_VRAP_REGNUM] =
1866 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_IP_REGNUM);
1867 cache->saved_regs[IA64_CFM_REGNUM] =
1868 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_CFM_REGNUM);
1869 cache->saved_regs[IA64_PSR_REGNUM] =
1870 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_PSR_REGNUM);
1871 #if 0
1872 cache->saved_regs[IA64_BSP_REGNUM] =
1873 SIGCONTEXT_REGISTER_ADDRESS (frame->frame, IA64_BSP_REGNUM);
1874 #endif
1875 cache->saved_regs[IA64_RNAT_REGNUM] =
1876 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_RNAT_REGNUM);
1877 cache->saved_regs[IA64_CCV_REGNUM] =
1878 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_CCV_REGNUM);
1879 cache->saved_regs[IA64_UNAT_REGNUM] =
1880 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_UNAT_REGNUM);
1881 cache->saved_regs[IA64_FPSR_REGNUM] =
1882 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_FPSR_REGNUM);
1883 cache->saved_regs[IA64_PFS_REGNUM] =
1884 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_PFS_REGNUM);
1885 cache->saved_regs[IA64_LC_REGNUM] =
1886 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_LC_REGNUM);
1887 for (regno = IA64_GR1_REGNUM; regno <= IA64_GR31_REGNUM; regno++)
1888 if (regno != sp_regnum)
1889 cache->saved_regs[regno] =
1890 SIGCONTEXT_REGISTER_ADDRESS (cache->base, regno);
1891 for (regno = IA64_BR0_REGNUM; regno <= IA64_BR7_REGNUM; regno++)
1892 cache->saved_regs[regno] =
1893 SIGCONTEXT_REGISTER_ADDRESS (cache->base, regno);
1894 for (regno = IA64_FR2_REGNUM; regno <= IA64_BR7_REGNUM; regno++)
1895 cache->saved_regs[regno] =
1896 SIGCONTEXT_REGISTER_ADDRESS (cache->base, regno);
1897 }
1898 }
1899
1900 static struct ia64_frame_cache *
1901 ia64_sigtramp_frame_cache (struct frame_info *next_frame, void **this_cache)
1902 {
1903 struct ia64_frame_cache *cache;
1904 CORE_ADDR addr;
1905 char buf[8];
1906 int i;
1907
1908 if (*this_cache)
1909 return *this_cache;
1910
1911 cache = ia64_alloc_frame_cache ();
1912
1913 frame_unwind_register (next_frame, sp_regnum, buf);
1914 cache->base = extract_unsigned_integer (buf, 8) + cache->mem_stack_frame_size;
1915
1916 ia64_sigtramp_frame_init_saved_regs (cache);
1917
1918 *this_cache = cache;
1919 return cache;
1920 }
1921
1922 static void
1923 ia64_sigtramp_frame_this_id (struct frame_info *next_frame,
1924 void **this_cache, struct frame_id *this_id)
1925 {
1926 struct ia64_frame_cache *cache =
1927 ia64_sigtramp_frame_cache (next_frame, this_cache);
1928
1929 (*this_id) = frame_id_build (cache->base, frame_pc_unwind (next_frame));
1930 }
1931
1932 static void
1933 ia64_sigtramp_frame_prev_register (struct frame_info *next_frame,
1934 void **this_cache,
1935 int regnum, int *optimizedp,
1936 enum lval_type *lvalp, CORE_ADDR *addrp,
1937 int *realnump, void *valuep)
1938 {
1939 /* Make sure we've initialized the cache. */
1940 ia64_sigtramp_frame_cache (next_frame, this_cache);
1941
1942 ia64_frame_prev_register (next_frame, this_cache, regnum,
1943 optimizedp, lvalp, addrp, realnump, valuep);
1944 }
1945
1946 static const struct frame_unwind ia64_sigtramp_frame_unwind =
1947 {
1948 SIGTRAMP_FRAME,
1949 ia64_sigtramp_frame_this_id,
1950 ia64_sigtramp_frame_prev_register
1951 };
1952
1953 static const struct frame_unwind *
1954 ia64_sigtramp_frame_sniffer (struct frame_info *next_frame)
1955 {
1956 char *name;
1957 CORE_ADDR pc = frame_pc_unwind (next_frame);
1958
1959 find_pc_partial_function (pc, &name, NULL, NULL);
1960 if (PC_IN_SIGTRAMP (pc, name))
1961 return &ia64_sigtramp_frame_unwind;
1962
1963 return NULL;
1964 }
1965 \f
1966
1967 static CORE_ADDR
1968 ia64_frame_base_address (struct frame_info *next_frame, void **this_cache)
1969 {
1970 struct ia64_frame_cache *cache =
1971 ia64_frame_cache (next_frame, this_cache);
1972
1973 return cache->base;
1974 }
1975
1976 static const struct frame_base ia64_frame_base =
1977 {
1978 &ia64_frame_unwind,
1979 ia64_frame_base_address,
1980 ia64_frame_base_address,
1981 ia64_frame_base_address
1982 };
1983
1984 /* Should we use EXTRACT_STRUCT_VALUE_ADDRESS instead of
1985 EXTRACT_RETURN_VALUE? GCC_P is true if compiled with gcc
1986 and TYPE is the type (which is known to be struct, union or array). */
1987 int
1988 ia64_use_struct_convention (int gcc_p, struct type *type)
1989 {
1990 struct type *float_elt_type;
1991
1992 /* HFAs are structures (or arrays) consisting entirely of floating
1993 point values of the same length. Up to 8 of these are returned
1994 in registers. Don't use the struct convention when this is the
1995 case. */
1996 float_elt_type = is_float_or_hfa_type (type);
1997 if (float_elt_type != NULL
1998 && TYPE_LENGTH (type) / TYPE_LENGTH (float_elt_type) <= 8)
1999 return 0;
2000
2001 /* Other structs of length 32 or less are returned in r8-r11.
2002 Don't use the struct convention for those either. */
2003 return TYPE_LENGTH (type) > 32;
2004 }
2005
2006 void
2007 ia64_extract_return_value (struct type *type, struct regcache *regcache, void *valbuf)
2008 {
2009 struct type *float_elt_type;
2010
2011 float_elt_type = is_float_or_hfa_type (type);
2012 if (float_elt_type != NULL)
2013 {
2014 char from[MAX_REGISTER_SIZE];
2015 int offset = 0;
2016 int regnum = IA64_FR8_REGNUM;
2017 int n = TYPE_LENGTH (type) / TYPE_LENGTH (float_elt_type);
2018
2019 while (n-- > 0)
2020 {
2021 regcache_cooked_read (regcache, regnum, from);
2022 convert_typed_floating (from, builtin_type_ia64_ext,
2023 (char *)valbuf + offset, float_elt_type);
2024 offset += TYPE_LENGTH (float_elt_type);
2025 regnum++;
2026 }
2027 }
2028 else
2029 {
2030 ULONGEST val;
2031 int offset = 0;
2032 int regnum = IA64_GR8_REGNUM;
2033 int reglen = TYPE_LENGTH (ia64_register_type (NULL, IA64_GR8_REGNUM));
2034 int n = TYPE_LENGTH (type) / reglen;
2035 int m = TYPE_LENGTH (type) % reglen;
2036
2037 while (n-- > 0)
2038 {
2039 ULONGEST val;
2040 regcache_cooked_read_unsigned (regcache, regnum, &val);
2041 memcpy ((char *)valbuf + offset, &val, reglen);
2042 offset += reglen;
2043 regnum++;
2044 }
2045
2046 if (m)
2047 {
2048 regcache_cooked_read_unsigned (regcache, regnum, &val);
2049 memcpy ((char *)valbuf + offset, &val, m);
2050 }
2051 }
2052 }
2053
2054 CORE_ADDR
2055 ia64_extract_struct_value_address (struct regcache *regcache)
2056 {
2057 error ("ia64_extract_struct_value_address called and cannot get struct value address");
2058 return 0;
2059 }
2060
2061
2062 static int
2063 is_float_or_hfa_type_recurse (struct type *t, struct type **etp)
2064 {
2065 switch (TYPE_CODE (t))
2066 {
2067 case TYPE_CODE_FLT:
2068 if (*etp)
2069 return TYPE_LENGTH (*etp) == TYPE_LENGTH (t);
2070 else
2071 {
2072 *etp = t;
2073 return 1;
2074 }
2075 break;
2076 case TYPE_CODE_ARRAY:
2077 return
2078 is_float_or_hfa_type_recurse (check_typedef (TYPE_TARGET_TYPE (t)),
2079 etp);
2080 break;
2081 case TYPE_CODE_STRUCT:
2082 {
2083 int i;
2084
2085 for (i = 0; i < TYPE_NFIELDS (t); i++)
2086 if (!is_float_or_hfa_type_recurse
2087 (check_typedef (TYPE_FIELD_TYPE (t, i)), etp))
2088 return 0;
2089 return 1;
2090 }
2091 break;
2092 default:
2093 return 0;
2094 break;
2095 }
2096 }
2097
2098 /* Determine if the given type is one of the floating point types or
2099 and HFA (which is a struct, array, or combination thereof whose
2100 bottom-most elements are all of the same floating point type). */
2101
2102 static struct type *
2103 is_float_or_hfa_type (struct type *t)
2104 {
2105 struct type *et = 0;
2106
2107 return is_float_or_hfa_type_recurse (t, &et) ? et : 0;
2108 }
2109
2110
2111 /* Return 1 if the alignment of T is such that the next even slot
2112 should be used. Return 0, if the next available slot should
2113 be used. (See section 8.5.1 of the IA-64 Software Conventions
2114 and Runtime manual). */
2115
2116 static int
2117 slot_alignment_is_next_even (struct type *t)
2118 {
2119 switch (TYPE_CODE (t))
2120 {
2121 case TYPE_CODE_INT:
2122 case TYPE_CODE_FLT:
2123 if (TYPE_LENGTH (t) > 8)
2124 return 1;
2125 else
2126 return 0;
2127 case TYPE_CODE_ARRAY:
2128 return
2129 slot_alignment_is_next_even (check_typedef (TYPE_TARGET_TYPE (t)));
2130 case TYPE_CODE_STRUCT:
2131 {
2132 int i;
2133
2134 for (i = 0; i < TYPE_NFIELDS (t); i++)
2135 if (slot_alignment_is_next_even
2136 (check_typedef (TYPE_FIELD_TYPE (t, i))))
2137 return 1;
2138 return 0;
2139 }
2140 default:
2141 return 0;
2142 }
2143 }
2144
2145 /* Attempt to find (and return) the global pointer for the given
2146 function.
2147
2148 This is a rather nasty bit of code searchs for the .dynamic section
2149 in the objfile corresponding to the pc of the function we're trying
2150 to call. Once it finds the addresses at which the .dynamic section
2151 lives in the child process, it scans the Elf64_Dyn entries for a
2152 DT_PLTGOT tag. If it finds one of these, the corresponding
2153 d_un.d_ptr value is the global pointer. */
2154
2155 static CORE_ADDR
2156 generic_elf_find_global_pointer (CORE_ADDR faddr)
2157 {
2158 struct obj_section *faddr_sect;
2159
2160 faddr_sect = find_pc_section (faddr);
2161 if (faddr_sect != NULL)
2162 {
2163 struct obj_section *osect;
2164
2165 ALL_OBJFILE_OSECTIONS (faddr_sect->objfile, osect)
2166 {
2167 if (strcmp (osect->the_bfd_section->name, ".dynamic") == 0)
2168 break;
2169 }
2170
2171 if (osect < faddr_sect->objfile->sections_end)
2172 {
2173 CORE_ADDR addr;
2174
2175 addr = osect->addr;
2176 while (addr < osect->endaddr)
2177 {
2178 int status;
2179 LONGEST tag;
2180 char buf[8];
2181
2182 status = target_read_memory (addr, buf, sizeof (buf));
2183 if (status != 0)
2184 break;
2185 tag = extract_signed_integer (buf, sizeof (buf));
2186
2187 if (tag == DT_PLTGOT)
2188 {
2189 CORE_ADDR global_pointer;
2190
2191 status = target_read_memory (addr + 8, buf, sizeof (buf));
2192 if (status != 0)
2193 break;
2194 global_pointer = extract_unsigned_integer (buf, sizeof (buf));
2195
2196 /* The payoff... */
2197 return global_pointer;
2198 }
2199
2200 if (tag == DT_NULL)
2201 break;
2202
2203 addr += 16;
2204 }
2205 }
2206 }
2207 return 0;
2208 }
2209
2210 /* Given a function's address, attempt to find (and return) the
2211 corresponding (canonical) function descriptor. Return 0 if
2212 not found. */
2213 static CORE_ADDR
2214 find_extant_func_descr (CORE_ADDR faddr)
2215 {
2216 struct obj_section *faddr_sect;
2217
2218 /* Return early if faddr is already a function descriptor. */
2219 faddr_sect = find_pc_section (faddr);
2220 if (faddr_sect && strcmp (faddr_sect->the_bfd_section->name, ".opd") == 0)
2221 return faddr;
2222
2223 if (faddr_sect != NULL)
2224 {
2225 struct obj_section *osect;
2226 ALL_OBJFILE_OSECTIONS (faddr_sect->objfile, osect)
2227 {
2228 if (strcmp (osect->the_bfd_section->name, ".opd") == 0)
2229 break;
2230 }
2231
2232 if (osect < faddr_sect->objfile->sections_end)
2233 {
2234 CORE_ADDR addr;
2235
2236 addr = osect->addr;
2237 while (addr < osect->endaddr)
2238 {
2239 int status;
2240 LONGEST faddr2;
2241 char buf[8];
2242
2243 status = target_read_memory (addr, buf, sizeof (buf));
2244 if (status != 0)
2245 break;
2246 faddr2 = extract_signed_integer (buf, sizeof (buf));
2247
2248 if (faddr == faddr2)
2249 return addr;
2250
2251 addr += 16;
2252 }
2253 }
2254 }
2255 return 0;
2256 }
2257
2258 /* Attempt to find a function descriptor corresponding to the
2259 given address. If none is found, construct one on the
2260 stack using the address at fdaptr. */
2261
2262 static CORE_ADDR
2263 find_func_descr (CORE_ADDR faddr, CORE_ADDR *fdaptr)
2264 {
2265 CORE_ADDR fdesc;
2266
2267 fdesc = find_extant_func_descr (faddr);
2268
2269 if (fdesc == 0)
2270 {
2271 CORE_ADDR global_pointer;
2272 char buf[16];
2273
2274 fdesc = *fdaptr;
2275 *fdaptr += 16;
2276
2277 global_pointer = FIND_GLOBAL_POINTER (faddr);
2278
2279 if (global_pointer == 0)
2280 global_pointer = read_register (IA64_GR1_REGNUM);
2281
2282 store_unsigned_integer (buf, 8, faddr);
2283 store_unsigned_integer (buf + 8, 8, global_pointer);
2284
2285 write_memory (fdesc, buf, 16);
2286 }
2287
2288 return fdesc;
2289 }
2290
2291 /* Use the following routine when printing out function pointers
2292 so the user can see the function address rather than just the
2293 function descriptor. */
2294 static CORE_ADDR
2295 ia64_convert_from_func_ptr_addr (CORE_ADDR addr)
2296 {
2297 struct obj_section *s;
2298
2299 s = find_pc_section (addr);
2300
2301 /* check if ADDR points to a function descriptor. */
2302 if (s && strcmp (s->the_bfd_section->name, ".opd") == 0)
2303 return read_memory_unsigned_integer (addr, 8);
2304
2305 return addr;
2306 }
2307
2308 static CORE_ADDR
2309 ia64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
2310 {
2311 return sp & ~0xfLL;
2312 }
2313
2314 static CORE_ADDR
2315 ia64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
2316 struct regcache *regcache, CORE_ADDR bp_addr,
2317 int nargs, struct value **args, CORE_ADDR sp,
2318 int struct_return, CORE_ADDR struct_addr)
2319 {
2320 int argno;
2321 struct value *arg;
2322 struct type *type;
2323 int len, argoffset;
2324 int nslots, rseslots, memslots, slotnum, nfuncargs;
2325 int floatreg;
2326 CORE_ADDR bsp, cfm, pfs, new_bsp, funcdescaddr, pc, global_pointer;
2327
2328 nslots = 0;
2329 nfuncargs = 0;
2330 /* Count the number of slots needed for the arguments. */
2331 for (argno = 0; argno < nargs; argno++)
2332 {
2333 arg = args[argno];
2334 type = check_typedef (VALUE_TYPE (arg));
2335 len = TYPE_LENGTH (type);
2336
2337 if ((nslots & 1) && slot_alignment_is_next_even (type))
2338 nslots++;
2339
2340 if (TYPE_CODE (type) == TYPE_CODE_FUNC)
2341 nfuncargs++;
2342
2343 nslots += (len + 7) / 8;
2344 }
2345
2346 /* Divvy up the slots between the RSE and the memory stack. */
2347 rseslots = (nslots > 8) ? 8 : nslots;
2348 memslots = nslots - rseslots;
2349
2350 /* Allocate a new RSE frame. */
2351 cfm = read_register (IA64_CFM_REGNUM);
2352
2353 bsp = read_register (IA64_BSP_REGNUM);
2354 new_bsp = rse_address_add (bsp, rseslots);
2355 write_register (IA64_BSP_REGNUM, new_bsp);
2356
2357 pfs = read_register (IA64_PFS_REGNUM);
2358 pfs &= 0xc000000000000000LL;
2359 pfs |= (cfm & 0xffffffffffffLL);
2360 write_register (IA64_PFS_REGNUM, pfs);
2361
2362 cfm &= 0xc000000000000000LL;
2363 cfm |= rseslots;
2364 write_register (IA64_CFM_REGNUM, cfm);
2365
2366 /* We will attempt to find function descriptors in the .opd segment,
2367 but if we can't we'll construct them ourselves. That being the
2368 case, we'll need to reserve space on the stack for them. */
2369 funcdescaddr = sp - nfuncargs * 16;
2370 funcdescaddr &= ~0xfLL;
2371
2372 /* Adjust the stack pointer to it's new value. The calling conventions
2373 require us to have 16 bytes of scratch, plus whatever space is
2374 necessary for the memory slots and our function descriptors. */
2375 sp = sp - 16 - (memslots + nfuncargs) * 8;
2376 sp &= ~0xfLL; /* Maintain 16 byte alignment. */
2377
2378 /* Place the arguments where they belong. The arguments will be
2379 either placed in the RSE backing store or on the memory stack.
2380 In addition, floating point arguments or HFAs are placed in
2381 floating point registers. */
2382 slotnum = 0;
2383 floatreg = IA64_FR8_REGNUM;
2384 for (argno = 0; argno < nargs; argno++)
2385 {
2386 struct type *float_elt_type;
2387
2388 arg = args[argno];
2389 type = check_typedef (VALUE_TYPE (arg));
2390 len = TYPE_LENGTH (type);
2391
2392 /* Special handling for function parameters. */
2393 if (len == 8
2394 && TYPE_CODE (type) == TYPE_CODE_PTR
2395 && TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC)
2396 {
2397 char val_buf[8];
2398
2399 store_unsigned_integer (val_buf, 8,
2400 find_func_descr (extract_unsigned_integer (VALUE_CONTENTS (arg), 8),
2401 &funcdescaddr));
2402 if (slotnum < rseslots)
2403 write_memory (rse_address_add (bsp, slotnum), val_buf, 8);
2404 else
2405 write_memory (sp + 16 + 8 * (slotnum - rseslots), val_buf, 8);
2406 slotnum++;
2407 continue;
2408 }
2409
2410 /* Normal slots. */
2411
2412 /* Skip odd slot if necessary... */
2413 if ((slotnum & 1) && slot_alignment_is_next_even (type))
2414 slotnum++;
2415
2416 argoffset = 0;
2417 while (len > 0)
2418 {
2419 char val_buf[8];
2420
2421 memset (val_buf, 0, 8);
2422 memcpy (val_buf, VALUE_CONTENTS (arg) + argoffset, (len > 8) ? 8 : len);
2423
2424 if (slotnum < rseslots)
2425 write_memory (rse_address_add (bsp, slotnum), val_buf, 8);
2426 else
2427 write_memory (sp + 16 + 8 * (slotnum - rseslots), val_buf, 8);
2428
2429 argoffset += 8;
2430 len -= 8;
2431 slotnum++;
2432 }
2433
2434 /* Handle floating point types (including HFAs). */
2435 float_elt_type = is_float_or_hfa_type (type);
2436 if (float_elt_type != NULL)
2437 {
2438 argoffset = 0;
2439 len = TYPE_LENGTH (type);
2440 while (len > 0 && floatreg < IA64_FR16_REGNUM)
2441 {
2442 char to[MAX_REGISTER_SIZE];
2443 convert_typed_floating (VALUE_CONTENTS (arg) + argoffset, float_elt_type,
2444 to, builtin_type_ia64_ext);
2445 regcache_cooked_write (regcache, floatreg, (void *)to);
2446 floatreg++;
2447 argoffset += TYPE_LENGTH (float_elt_type);
2448 len -= TYPE_LENGTH (float_elt_type);
2449 }
2450 }
2451 }
2452
2453 /* Store the struct return value in r8 if necessary. */
2454 if (struct_return)
2455 {
2456 regcache_cooked_write_unsigned (regcache, IA64_GR8_REGNUM, (ULONGEST)struct_addr);
2457 }
2458
2459 global_pointer = FIND_GLOBAL_POINTER (func_addr);
2460
2461 if (global_pointer != 0)
2462 write_register (IA64_GR1_REGNUM, global_pointer);
2463
2464 write_register (IA64_BR0_REGNUM, bp_addr);
2465
2466 write_register (sp_regnum, sp);
2467
2468 return sp;
2469 }
2470
2471 static struct frame_id
2472 ia64_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
2473 {
2474 char buf[8];
2475 CORE_ADDR sp;
2476
2477 frame_unwind_register (next_frame, sp_regnum, buf);
2478 sp = extract_unsigned_integer (buf, 8);
2479
2480 return frame_id_build (sp, frame_pc_unwind (next_frame));
2481 }
2482
2483 static CORE_ADDR
2484 ia64_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
2485 {
2486 char buf[8];
2487 CORE_ADDR ip, psr, pc;
2488
2489 frame_unwind_register (next_frame, IA64_IP_REGNUM, buf);
2490 ip = extract_unsigned_integer (buf, 8);
2491 frame_unwind_register (next_frame, IA64_PSR_REGNUM, buf);
2492 psr = extract_unsigned_integer (buf, 8);
2493
2494 pc = (ip & ~0xf) | ((psr >> 41) & 3);
2495 return pc;
2496 }
2497
2498 static void
2499 ia64_store_return_value (struct type *type, struct regcache *regcache, const void *valbuf)
2500 {
2501 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2502 {
2503 char to[MAX_REGISTER_SIZE];
2504 convert_typed_floating (valbuf, type, to, builtin_type_ia64_ext);
2505 regcache_cooked_write (regcache, IA64_FR8_REGNUM, (void *)to);
2506 target_store_registers (IA64_FR8_REGNUM);
2507 }
2508 else
2509 regcache_cooked_write (regcache, IA64_GR8_REGNUM, valbuf);
2510 }
2511
2512 static void
2513 ia64_remote_translate_xfer_address (struct gdbarch *gdbarch,
2514 struct regcache *regcache,
2515 CORE_ADDR memaddr, int nr_bytes,
2516 CORE_ADDR *targ_addr, int *targ_len)
2517 {
2518 *targ_addr = memaddr;
2519 *targ_len = nr_bytes;
2520 }
2521
2522 static void
2523 process_note_abi_tag_sections (bfd *abfd, asection *sect, void *obj)
2524 {
2525 int *os_ident_ptr = obj;
2526 const char *name;
2527 unsigned int sectsize;
2528
2529 name = bfd_get_section_name (abfd, sect);
2530 sectsize = bfd_section_size (abfd, sect);
2531 if (strcmp (name, ".note.ABI-tag") == 0 && sectsize > 0)
2532 {
2533 unsigned int name_length, data_length, note_type;
2534 char *note = alloca (sectsize);
2535
2536 bfd_get_section_contents (abfd, sect, note,
2537 (file_ptr) 0, (bfd_size_type) sectsize);
2538
2539 name_length = bfd_h_get_32 (abfd, note);
2540 data_length = bfd_h_get_32 (abfd, note + 4);
2541 note_type = bfd_h_get_32 (abfd, note + 8);
2542
2543 if (name_length == 4 && data_length == 16 && note_type == 1
2544 && strcmp (note + 12, "GNU") == 0)
2545 {
2546 int os_number = bfd_h_get_32 (abfd, note + 16);
2547
2548 /* The case numbers are from abi-tags in glibc. */
2549 switch (os_number)
2550 {
2551 case 0 :
2552 *os_ident_ptr = ELFOSABI_LINUX;
2553 break;
2554 case 1 :
2555 *os_ident_ptr = ELFOSABI_HURD;
2556 break;
2557 case 2 :
2558 *os_ident_ptr = ELFOSABI_SOLARIS;
2559 break;
2560 default :
2561 internal_error (__FILE__, __LINE__,
2562 "process_note_abi_sections: unknown OS number %d", os_number);
2563 break;
2564 }
2565 }
2566 }
2567 }
2568
2569 static int
2570 ia64_print_insn (bfd_vma memaddr, struct disassemble_info *info)
2571 {
2572 info->bytes_per_line = SLOT_MULTIPLIER;
2573 return print_insn_ia64 (memaddr, info);
2574 }
2575
2576 static struct gdbarch *
2577 ia64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2578 {
2579 struct gdbarch *gdbarch;
2580 struct gdbarch_tdep *tdep;
2581 int os_ident;
2582
2583 if (info.abfd != NULL
2584 && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
2585 {
2586 os_ident = elf_elfheader (info.abfd)->e_ident[EI_OSABI];
2587
2588 /* If os_ident is 0, it is not necessarily the case that we're
2589 on a SYSV system. (ELFOSABI_NONE is defined to be 0.)
2590 GNU/Linux uses a note section to record OS/ABI info, but
2591 leaves e_ident[EI_OSABI] zero. So we have to check for note
2592 sections too. */
2593 if (os_ident == 0)
2594 {
2595 bfd_map_over_sections (info.abfd,
2596 process_note_abi_tag_sections,
2597 &os_ident);
2598 }
2599 }
2600 else
2601 os_ident = -1;
2602
2603 for (arches = gdbarch_list_lookup_by_info (arches, &info);
2604 arches != NULL;
2605 arches = gdbarch_list_lookup_by_info (arches->next, &info))
2606 {
2607 tdep = gdbarch_tdep (arches->gdbarch);
2608 if (tdep &&tdep->os_ident == os_ident)
2609 return arches->gdbarch;
2610 }
2611
2612 tdep = xmalloc (sizeof (struct gdbarch_tdep));
2613 gdbarch = gdbarch_alloc (&info, tdep);
2614 tdep->os_ident = os_ident;
2615
2616 /* Set the method of obtaining the sigcontext addresses at which
2617 registers are saved. The method of checking to see if
2618 native_find_global_pointer is nonzero to indicate that we're
2619 on AIX is kind of hokey, but I can't think of a better way
2620 to do it. */
2621 if (os_ident == ELFOSABI_LINUX)
2622 tdep->sigcontext_register_address = ia64_linux_sigcontext_register_address;
2623 else if (native_find_global_pointer != 0)
2624 tdep->sigcontext_register_address = ia64_aix_sigcontext_register_address;
2625 else
2626 tdep->sigcontext_register_address = 0;
2627
2628 /* We know that GNU/Linux won't have to resort to the
2629 native_find_global_pointer hackery. But that's the only one we
2630 know about so far, so if native_find_global_pointer is set to
2631 something non-zero, then use it. Otherwise fall back to using
2632 generic_elf_find_global_pointer. This arrangement should (in
2633 theory) allow us to cross debug GNU/Linux binaries from an AIX
2634 machine. */
2635 if (os_ident == ELFOSABI_LINUX)
2636 tdep->find_global_pointer = generic_elf_find_global_pointer;
2637 else if (native_find_global_pointer != 0)
2638 tdep->find_global_pointer = native_find_global_pointer;
2639 else
2640 tdep->find_global_pointer = generic_elf_find_global_pointer;
2641
2642 /* Define the ia64 floating-point format to gdb. */
2643 builtin_type_ia64_ext =
2644 init_type (TYPE_CODE_FLT, 128 / 8,
2645 0, "builtin_type_ia64_ext", NULL);
2646 TYPE_FLOATFORMAT (builtin_type_ia64_ext) = &floatformat_ia64_ext;
2647
2648 set_gdbarch_short_bit (gdbarch, 16);
2649 set_gdbarch_int_bit (gdbarch, 32);
2650 set_gdbarch_long_bit (gdbarch, 64);
2651 set_gdbarch_long_long_bit (gdbarch, 64);
2652 set_gdbarch_float_bit (gdbarch, 32);
2653 set_gdbarch_double_bit (gdbarch, 64);
2654 set_gdbarch_long_double_bit (gdbarch, 128);
2655 set_gdbarch_ptr_bit (gdbarch, 64);
2656
2657 set_gdbarch_num_regs (gdbarch, NUM_IA64_RAW_REGS);
2658 set_gdbarch_num_pseudo_regs (gdbarch, LAST_PSEUDO_REGNUM - FIRST_PSEUDO_REGNUM);
2659 set_gdbarch_sp_regnum (gdbarch, sp_regnum);
2660 set_gdbarch_fp0_regnum (gdbarch, IA64_FR0_REGNUM);
2661
2662 set_gdbarch_register_name (gdbarch, ia64_register_name);
2663 /* FIXME: Following interface should not be needed, however, without it recurse.exp
2664 gets a number of extra failures. */
2665 set_gdbarch_deprecated_register_size (gdbarch, 8);
2666 set_gdbarch_register_type (gdbarch, ia64_register_type);
2667
2668 set_gdbarch_pseudo_register_read (gdbarch, ia64_pseudo_register_read);
2669 set_gdbarch_pseudo_register_write (gdbarch, ia64_pseudo_register_write);
2670 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, ia64_dwarf_reg_to_regnum);
2671 set_gdbarch_register_reggroup_p (gdbarch, ia64_register_reggroup_p);
2672 set_gdbarch_convert_register_p (gdbarch, ia64_convert_register_p);
2673 set_gdbarch_register_to_value (gdbarch, ia64_register_to_value);
2674 set_gdbarch_value_to_register (gdbarch, ia64_value_to_register);
2675
2676 set_gdbarch_skip_prologue (gdbarch, ia64_skip_prologue);
2677
2678 set_gdbarch_use_struct_convention (gdbarch, ia64_use_struct_convention);
2679 set_gdbarch_extract_return_value (gdbarch, ia64_extract_return_value);
2680
2681 set_gdbarch_store_return_value (gdbarch, ia64_store_return_value);
2682 set_gdbarch_extract_struct_value_address (gdbarch, ia64_extract_struct_value_address);
2683
2684 set_gdbarch_memory_insert_breakpoint (gdbarch, ia64_memory_insert_breakpoint);
2685 set_gdbarch_memory_remove_breakpoint (gdbarch, ia64_memory_remove_breakpoint);
2686 set_gdbarch_breakpoint_from_pc (gdbarch, ia64_breakpoint_from_pc);
2687 set_gdbarch_read_pc (gdbarch, ia64_read_pc);
2688 set_gdbarch_write_pc (gdbarch, ia64_write_pc);
2689
2690 /* Settings for calling functions in the inferior. */
2691 set_gdbarch_push_dummy_call (gdbarch, ia64_push_dummy_call);
2692 set_gdbarch_frame_align (gdbarch, ia64_frame_align);
2693 set_gdbarch_unwind_dummy_id (gdbarch, ia64_unwind_dummy_id);
2694
2695 set_gdbarch_unwind_pc (gdbarch, ia64_unwind_pc);
2696 frame_unwind_append_sniffer (gdbarch, ia64_sigtramp_frame_sniffer);
2697 frame_unwind_append_sniffer (gdbarch, ia64_frame_sniffer);
2698 frame_base_set_default (gdbarch, &ia64_frame_base);
2699
2700 /* Settings that should be unnecessary. */
2701 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2702
2703 set_gdbarch_decr_pc_after_break (gdbarch, 0);
2704 set_gdbarch_function_start_offset (gdbarch, 0);
2705 set_gdbarch_frame_args_skip (gdbarch, 0);
2706
2707 set_gdbarch_remote_translate_xfer_address (
2708 gdbarch, ia64_remote_translate_xfer_address);
2709
2710 set_gdbarch_print_insn (gdbarch, ia64_print_insn);
2711 set_gdbarch_convert_from_func_ptr_addr (gdbarch, ia64_convert_from_func_ptr_addr);
2712
2713 return gdbarch;
2714 }
2715
2716 extern initialize_file_ftype _initialize_ia64_tdep; /* -Wmissing-prototypes */
2717
2718 void
2719 _initialize_ia64_tdep (void)
2720 {
2721 register_gdbarch_init (bfd_arch_ia64, ia64_gdbarch_init);
2722 }
GDB Binutils - Deliverables
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