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[deliverable/binutils-gdb.git] / gdb / ia64-tdep.c
1 /* Target-dependent code for the IA-64 for GDB, the GNU debugger.
2
3 Copyright 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
21
22 #include "defs.h"
23 #include "inferior.h"
24 #include "symfile.h" /* for entry_point_address */
25 #include "gdbcore.h"
26 #include "arch-utils.h"
27 #include "floatformat.h"
28 #include "regcache.h"
29 #include "reggroups.h"
30 #include "frame.h"
31 #include "frame-base.h"
32 #include "frame-unwind.h"
33 #include "doublest.h"
34 #include "value.h"
35 #include "gdb_assert.h"
36 #include "objfiles.h"
37 #include "elf/common.h" /* for DT_PLTGOT value */
38 #include "elf-bfd.h"
39 #include "dis-asm.h"
40
41 /* Hook for determining the global pointer when calling functions in
42 the inferior under AIX. The initialization code in ia64-aix-nat.c
43 sets this hook to the address of a function which will find the
44 global pointer for a given address.
45
46 The generic code which uses the dynamic section in the inferior for
47 finding the global pointer is not of much use on AIX since the
48 values obtained from the inferior have not been relocated. */
49
50 CORE_ADDR (*native_find_global_pointer) (CORE_ADDR) = 0;
51
52 /* An enumeration of the different IA-64 instruction types. */
53
54 typedef enum instruction_type
55 {
56 A, /* Integer ALU ; I-unit or M-unit */
57 I, /* Non-ALU integer; I-unit */
58 M, /* Memory ; M-unit */
59 F, /* Floating-point ; F-unit */
60 B, /* Branch ; B-unit */
61 L, /* Extended (L+X) ; I-unit */
62 X, /* Extended (L+X) ; I-unit */
63 undefined /* undefined or reserved */
64 } instruction_type;
65
66 /* We represent IA-64 PC addresses as the value of the instruction
67 pointer or'd with some bit combination in the low nibble which
68 represents the slot number in the bundle addressed by the
69 instruction pointer. The problem is that the Linux kernel
70 multiplies its slot numbers (for exceptions) by one while the
71 disassembler multiplies its slot numbers by 6. In addition, I've
72 heard it said that the simulator uses 1 as the multiplier.
73
74 I've fixed the disassembler so that the bytes_per_line field will
75 be the slot multiplier. If bytes_per_line comes in as zero, it
76 is set to six (which is how it was set up initially). -- objdump
77 displays pretty disassembly dumps with this value. For our purposes,
78 we'll set bytes_per_line to SLOT_MULTIPLIER. This is okay since we
79 never want to also display the raw bytes the way objdump does. */
80
81 #define SLOT_MULTIPLIER 1
82
83 /* Length in bytes of an instruction bundle */
84
85 #define BUNDLE_LEN 16
86
87 /* FIXME: These extern declarations should go in ia64-tdep.h. */
88 extern CORE_ADDR ia64_linux_sigcontext_register_address (CORE_ADDR, int);
89 extern CORE_ADDR ia64_aix_sigcontext_register_address (CORE_ADDR, int);
90
91 static gdbarch_init_ftype ia64_gdbarch_init;
92
93 static gdbarch_register_name_ftype ia64_register_name;
94 static gdbarch_register_type_ftype ia64_register_type;
95 static gdbarch_breakpoint_from_pc_ftype ia64_breakpoint_from_pc;
96 static gdbarch_skip_prologue_ftype ia64_skip_prologue;
97 static gdbarch_extract_return_value_ftype ia64_extract_return_value;
98 static gdbarch_extract_struct_value_address_ftype ia64_extract_struct_value_address;
99 static gdbarch_use_struct_convention_ftype ia64_use_struct_convention;
100 static struct type *is_float_or_hfa_type (struct type *t);
101
102 static struct type *builtin_type_ia64_ext;
103
104 #define NUM_IA64_RAW_REGS 462
105
106 static int sp_regnum = IA64_GR12_REGNUM;
107 static int fp_regnum = IA64_VFP_REGNUM;
108 static int lr_regnum = IA64_VRAP_REGNUM;
109
110 /* NOTE: we treat the register stack registers r32-r127 as pseudo-registers because
111 they may not be accessible via the ptrace register get/set interfaces. */
112 enum pseudo_regs { FIRST_PSEUDO_REGNUM = NUM_IA64_RAW_REGS, VBOF_REGNUM = IA64_NAT127_REGNUM + 1, V32_REGNUM,
113 V127_REGNUM = V32_REGNUM + 95,
114 VP0_REGNUM, VP16_REGNUM = VP0_REGNUM + 16, VP63_REGNUM = VP0_REGNUM + 63, LAST_PSEUDO_REGNUM };
115
116 /* Array of register names; There should be ia64_num_regs strings in
117 the initializer. */
118
119 static char *ia64_register_names[] =
120 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
121 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
122 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
123 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
124 "", "", "", "", "", "", "", "",
125 "", "", "", "", "", "", "", "",
126 "", "", "", "", "", "", "", "",
127 "", "", "", "", "", "", "", "",
128 "", "", "", "", "", "", "", "",
129 "", "", "", "", "", "", "", "",
130 "", "", "", "", "", "", "", "",
131 "", "", "", "", "", "", "", "",
132 "", "", "", "", "", "", "", "",
133 "", "", "", "", "", "", "", "",
134 "", "", "", "", "", "", "", "",
135 "", "", "", "", "", "", "", "",
136
137 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
138 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
139 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
140 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
141 "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
142 "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47",
143 "f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55",
144 "f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63",
145 "f64", "f65", "f66", "f67", "f68", "f69", "f70", "f71",
146 "f72", "f73", "f74", "f75", "f76", "f77", "f78", "f79",
147 "f80", "f81", "f82", "f83", "f84", "f85", "f86", "f87",
148 "f88", "f89", "f90", "f91", "f92", "f93", "f94", "f95",
149 "f96", "f97", "f98", "f99", "f100", "f101", "f102", "f103",
150 "f104", "f105", "f106", "f107", "f108", "f109", "f110", "f111",
151 "f112", "f113", "f114", "f115", "f116", "f117", "f118", "f119",
152 "f120", "f121", "f122", "f123", "f124", "f125", "f126", "f127",
153
154 "", "", "", "", "", "", "", "",
155 "", "", "", "", "", "", "", "",
156 "", "", "", "", "", "", "", "",
157 "", "", "", "", "", "", "", "",
158 "", "", "", "", "", "", "", "",
159 "", "", "", "", "", "", "", "",
160 "", "", "", "", "", "", "", "",
161 "", "", "", "", "", "", "", "",
162
163 "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7",
164
165 "vfp", "vrap",
166
167 "pr", "ip", "psr", "cfm",
168
169 "kr0", "kr1", "kr2", "kr3", "kr4", "kr5", "kr6", "kr7",
170 "", "", "", "", "", "", "", "",
171 "rsc", "bsp", "bspstore", "rnat",
172 "", "fcr", "", "",
173 "eflag", "csd", "ssd", "cflg", "fsr", "fir", "fdr", "",
174 "ccv", "", "", "", "unat", "", "", "",
175 "fpsr", "", "", "", "itc",
176 "", "", "", "", "", "", "", "", "", "",
177 "", "", "", "", "", "", "", "", "",
178 "pfs", "lc", "ec",
179 "", "", "", "", "", "", "", "", "", "",
180 "", "", "", "", "", "", "", "", "", "",
181 "", "", "", "", "", "", "", "", "", "",
182 "", "", "", "", "", "", "", "", "", "",
183 "", "", "", "", "", "", "", "", "", "",
184 "", "", "", "", "", "", "", "", "", "",
185 "",
186 "nat0", "nat1", "nat2", "nat3", "nat4", "nat5", "nat6", "nat7",
187 "nat8", "nat9", "nat10", "nat11", "nat12", "nat13", "nat14", "nat15",
188 "nat16", "nat17", "nat18", "nat19", "nat20", "nat21", "nat22", "nat23",
189 "nat24", "nat25", "nat26", "nat27", "nat28", "nat29", "nat30", "nat31",
190 "nat32", "nat33", "nat34", "nat35", "nat36", "nat37", "nat38", "nat39",
191 "nat40", "nat41", "nat42", "nat43", "nat44", "nat45", "nat46", "nat47",
192 "nat48", "nat49", "nat50", "nat51", "nat52", "nat53", "nat54", "nat55",
193 "nat56", "nat57", "nat58", "nat59", "nat60", "nat61", "nat62", "nat63",
194 "nat64", "nat65", "nat66", "nat67", "nat68", "nat69", "nat70", "nat71",
195 "nat72", "nat73", "nat74", "nat75", "nat76", "nat77", "nat78", "nat79",
196 "nat80", "nat81", "nat82", "nat83", "nat84", "nat85", "nat86", "nat87",
197 "nat88", "nat89", "nat90", "nat91", "nat92", "nat93", "nat94", "nat95",
198 "nat96", "nat97", "nat98", "nat99", "nat100","nat101","nat102","nat103",
199 "nat104","nat105","nat106","nat107","nat108","nat109","nat110","nat111",
200 "nat112","nat113","nat114","nat115","nat116","nat117","nat118","nat119",
201 "nat120","nat121","nat122","nat123","nat124","nat125","nat126","nat127",
202
203 "bof",
204
205 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
206 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
207 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
208 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
209 "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71",
210 "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
211 "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87",
212 "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95",
213 "r96", "r97", "r98", "r99", "r100", "r101", "r102", "r103",
214 "r104", "r105", "r106", "r107", "r108", "r109", "r110", "r111",
215 "r112", "r113", "r114", "r115", "r116", "r117", "r118", "r119",
216 "r120", "r121", "r122", "r123", "r124", "r125", "r126", "r127",
217
218 "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7",
219 "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15",
220 "p16", "p17", "p18", "p19", "p20", "p21", "p22", "p23",
221 "p24", "p25", "p26", "p27", "p28", "p29", "p30", "p31",
222 "p32", "p33", "p34", "p35", "p36", "p37", "p38", "p39",
223 "p40", "p41", "p42", "p43", "p44", "p45", "p46", "p47",
224 "p48", "p49", "p50", "p51", "p52", "p53", "p54", "p55",
225 "p56", "p57", "p58", "p59", "p60", "p61", "p62", "p63",
226 };
227
228 struct ia64_frame_cache
229 {
230 CORE_ADDR base; /* frame pointer base for frame */
231 CORE_ADDR pc; /* function start pc for frame */
232 CORE_ADDR saved_sp; /* stack pointer for frame */
233 CORE_ADDR bsp; /* points at r32 for the current frame */
234 CORE_ADDR cfm; /* cfm value for current frame */
235 CORE_ADDR prev_cfm; /* cfm value for previous frame */
236 int frameless;
237 int sof; /* Size of frame (decoded from cfm value) */
238 int sol; /* Size of locals (decoded from cfm value) */
239 int sor; /* Number of rotating registers. (decoded from cfm value) */
240 CORE_ADDR after_prologue;
241 /* Address of first instruction after the last
242 prologue instruction; Note that there may
243 be instructions from the function's body
244 intermingled with the prologue. */
245 int mem_stack_frame_size;
246 /* Size of the memory stack frame (may be zero),
247 or -1 if it has not been determined yet. */
248 int fp_reg; /* Register number (if any) used a frame pointer
249 for this frame. 0 if no register is being used
250 as the frame pointer. */
251
252 /* Saved registers. */
253 CORE_ADDR saved_regs[NUM_IA64_RAW_REGS];
254
255 };
256
257 struct gdbarch_tdep
258 {
259 CORE_ADDR (*sigcontext_register_address) (CORE_ADDR, int);
260 /* OS specific function which, given a frame address
261 and register number, returns the offset to the
262 given register from the start of the frame. */
263 CORE_ADDR (*find_global_pointer) (CORE_ADDR);
264 };
265
266 #define SIGCONTEXT_REGISTER_ADDRESS \
267 (gdbarch_tdep (current_gdbarch)->sigcontext_register_address)
268 #define FIND_GLOBAL_POINTER \
269 (gdbarch_tdep (current_gdbarch)->find_global_pointer)
270
271 int
272 ia64_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
273 struct reggroup *group)
274 {
275 int vector_p;
276 int float_p;
277 int raw_p;
278 if (group == all_reggroup)
279 return 1;
280 vector_p = TYPE_VECTOR (register_type (gdbarch, regnum));
281 float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT;
282 raw_p = regnum < NUM_IA64_RAW_REGS;
283 if (group == float_reggroup)
284 return float_p;
285 if (group == vector_reggroup)
286 return vector_p;
287 if (group == general_reggroup)
288 return (!vector_p && !float_p);
289 if (group == save_reggroup || group == restore_reggroup)
290 return raw_p;
291 return 0;
292 }
293
294 static const char *
295 ia64_register_name (int reg)
296 {
297 return ia64_register_names[reg];
298 }
299
300 struct type *
301 ia64_register_type (struct gdbarch *arch, int reg)
302 {
303 if (reg >= IA64_FR0_REGNUM && reg <= IA64_FR127_REGNUM)
304 return builtin_type_ia64_ext;
305 else
306 return builtin_type_long;
307 }
308
309 static int
310 ia64_dwarf_reg_to_regnum (int reg)
311 {
312 if (reg >= IA64_GR32_REGNUM && reg <= IA64_GR127_REGNUM)
313 return V32_REGNUM + (reg - IA64_GR32_REGNUM);
314 return reg;
315 }
316
317 static int
318 floatformat_valid (const struct floatformat *fmt, const char *from)
319 {
320 return 1;
321 }
322
323 const struct floatformat floatformat_ia64_ext =
324 {
325 floatformat_little, 82, 0, 1, 17, 65535, 0x1ffff, 18, 64,
326 floatformat_intbit_yes, "floatformat_ia64_ext", floatformat_valid
327 };
328
329
330 /* Read the given register from a sigcontext structure in the
331 specified frame. */
332
333 static CORE_ADDR
334 read_sigcontext_register (struct frame_info *frame, int regnum)
335 {
336 CORE_ADDR regaddr;
337
338 if (frame == NULL)
339 internal_error (__FILE__, __LINE__,
340 "read_sigcontext_register: NULL frame");
341 if (!(get_frame_type (frame) == SIGTRAMP_FRAME))
342 internal_error (__FILE__, __LINE__,
343 "read_sigcontext_register: frame not a signal trampoline");
344 if (SIGCONTEXT_REGISTER_ADDRESS == 0)
345 internal_error (__FILE__, __LINE__,
346 "read_sigcontext_register: SIGCONTEXT_REGISTER_ADDRESS is 0");
347
348 regaddr = SIGCONTEXT_REGISTER_ADDRESS (get_frame_base (frame), regnum);
349 if (regaddr)
350 return read_memory_integer (regaddr, register_size (current_gdbarch, regnum));
351 else
352 internal_error (__FILE__, __LINE__,
353 "read_sigcontext_register: Register %d not in struct sigcontext", regnum);
354 }
355
356 /* Extract ``len'' bits from an instruction bundle starting at
357 bit ``from''. */
358
359 static long long
360 extract_bit_field (char *bundle, int from, int len)
361 {
362 long long result = 0LL;
363 int to = from + len;
364 int from_byte = from / 8;
365 int to_byte = to / 8;
366 unsigned char *b = (unsigned char *) bundle;
367 unsigned char c;
368 int lshift;
369 int i;
370
371 c = b[from_byte];
372 if (from_byte == to_byte)
373 c = ((unsigned char) (c << (8 - to % 8))) >> (8 - to % 8);
374 result = c >> (from % 8);
375 lshift = 8 - (from % 8);
376
377 for (i = from_byte+1; i < to_byte; i++)
378 {
379 result |= ((long long) b[i]) << lshift;
380 lshift += 8;
381 }
382
383 if (from_byte < to_byte && (to % 8 != 0))
384 {
385 c = b[to_byte];
386 c = ((unsigned char) (c << (8 - to % 8))) >> (8 - to % 8);
387 result |= ((long long) c) << lshift;
388 }
389
390 return result;
391 }
392
393 /* Replace the specified bits in an instruction bundle */
394
395 static void
396 replace_bit_field (char *bundle, long long val, int from, int len)
397 {
398 int to = from + len;
399 int from_byte = from / 8;
400 int to_byte = to / 8;
401 unsigned char *b = (unsigned char *) bundle;
402 unsigned char c;
403
404 if (from_byte == to_byte)
405 {
406 unsigned char left, right;
407 c = b[from_byte];
408 left = (c >> (to % 8)) << (to % 8);
409 right = ((unsigned char) (c << (8 - from % 8))) >> (8 - from % 8);
410 c = (unsigned char) (val & 0xff);
411 c = (unsigned char) (c << (from % 8 + 8 - to % 8)) >> (8 - to % 8);
412 c |= right | left;
413 b[from_byte] = c;
414 }
415 else
416 {
417 int i;
418 c = b[from_byte];
419 c = ((unsigned char) (c << (8 - from % 8))) >> (8 - from % 8);
420 c = c | (val << (from % 8));
421 b[from_byte] = c;
422 val >>= 8 - from % 8;
423
424 for (i = from_byte+1; i < to_byte; i++)
425 {
426 c = val & 0xff;
427 val >>= 8;
428 b[i] = c;
429 }
430
431 if (to % 8 != 0)
432 {
433 unsigned char cv = (unsigned char) val;
434 c = b[to_byte];
435 c = c >> (to % 8) << (to % 8);
436 c |= ((unsigned char) (cv << (8 - to % 8))) >> (8 - to % 8);
437 b[to_byte] = c;
438 }
439 }
440 }
441
442 /* Return the contents of slot N (for N = 0, 1, or 2) in
443 and instruction bundle */
444
445 static long long
446 slotN_contents (char *bundle, int slotnum)
447 {
448 return extract_bit_field (bundle, 5+41*slotnum, 41);
449 }
450
451 /* Store an instruction in an instruction bundle */
452
453 static void
454 replace_slotN_contents (char *bundle, long long instr, int slotnum)
455 {
456 replace_bit_field (bundle, instr, 5+41*slotnum, 41);
457 }
458
459 static enum instruction_type template_encoding_table[32][3] =
460 {
461 { M, I, I }, /* 00 */
462 { M, I, I }, /* 01 */
463 { M, I, I }, /* 02 */
464 { M, I, I }, /* 03 */
465 { M, L, X }, /* 04 */
466 { M, L, X }, /* 05 */
467 { undefined, undefined, undefined }, /* 06 */
468 { undefined, undefined, undefined }, /* 07 */
469 { M, M, I }, /* 08 */
470 { M, M, I }, /* 09 */
471 { M, M, I }, /* 0A */
472 { M, M, I }, /* 0B */
473 { M, F, I }, /* 0C */
474 { M, F, I }, /* 0D */
475 { M, M, F }, /* 0E */
476 { M, M, F }, /* 0F */
477 { M, I, B }, /* 10 */
478 { M, I, B }, /* 11 */
479 { M, B, B }, /* 12 */
480 { M, B, B }, /* 13 */
481 { undefined, undefined, undefined }, /* 14 */
482 { undefined, undefined, undefined }, /* 15 */
483 { B, B, B }, /* 16 */
484 { B, B, B }, /* 17 */
485 { M, M, B }, /* 18 */
486 { M, M, B }, /* 19 */
487 { undefined, undefined, undefined }, /* 1A */
488 { undefined, undefined, undefined }, /* 1B */
489 { M, F, B }, /* 1C */
490 { M, F, B }, /* 1D */
491 { undefined, undefined, undefined }, /* 1E */
492 { undefined, undefined, undefined }, /* 1F */
493 };
494
495 /* Fetch and (partially) decode an instruction at ADDR and return the
496 address of the next instruction to fetch. */
497
498 static CORE_ADDR
499 fetch_instruction (CORE_ADDR addr, instruction_type *it, long long *instr)
500 {
501 char bundle[BUNDLE_LEN];
502 int slotnum = (int) (addr & 0x0f) / SLOT_MULTIPLIER;
503 long long template;
504 int val;
505
506 /* Warn about slot numbers greater than 2. We used to generate
507 an error here on the assumption that the user entered an invalid
508 address. But, sometimes GDB itself requests an invalid address.
509 This can (easily) happen when execution stops in a function for
510 which there are no symbols. The prologue scanner will attempt to
511 find the beginning of the function - if the nearest symbol
512 happens to not be aligned on a bundle boundary (16 bytes), the
513 resulting starting address will cause GDB to think that the slot
514 number is too large.
515
516 So we warn about it and set the slot number to zero. It is
517 not necessarily a fatal condition, particularly if debugging
518 at the assembly language level. */
519 if (slotnum > 2)
520 {
521 warning ("Can't fetch instructions for slot numbers greater than 2.\n"
522 "Using slot 0 instead");
523 slotnum = 0;
524 }
525
526 addr &= ~0x0f;
527
528 val = target_read_memory (addr, bundle, BUNDLE_LEN);
529
530 if (val != 0)
531 return 0;
532
533 *instr = slotN_contents (bundle, slotnum);
534 template = extract_bit_field (bundle, 0, 5);
535 *it = template_encoding_table[(int)template][slotnum];
536
537 if (slotnum == 2 || (slotnum == 1 && *it == L))
538 addr += 16;
539 else
540 addr += (slotnum + 1) * SLOT_MULTIPLIER;
541
542 return addr;
543 }
544
545 /* There are 5 different break instructions (break.i, break.b,
546 break.m, break.f, and break.x), but they all have the same
547 encoding. (The five bit template in the low five bits of the
548 instruction bundle distinguishes one from another.)
549
550 The runtime architecture manual specifies that break instructions
551 used for debugging purposes must have the upper two bits of the 21
552 bit immediate set to a 0 and a 1 respectively. A breakpoint
553 instruction encodes the most significant bit of its 21 bit
554 immediate at bit 36 of the 41 bit instruction. The penultimate msb
555 is at bit 25 which leads to the pattern below.
556
557 Originally, I had this set up to do, e.g, a "break.i 0x80000" But
558 it turns out that 0x80000 was used as the syscall break in the early
559 simulators. So I changed the pattern slightly to do "break.i 0x080001"
560 instead. But that didn't work either (I later found out that this
561 pattern was used by the simulator that I was using.) So I ended up
562 using the pattern seen below. */
563
564 #if 0
565 #define IA64_BREAKPOINT 0x00002000040LL
566 #endif
567 #define IA64_BREAKPOINT 0x00003333300LL
568
569 static int
570 ia64_memory_insert_breakpoint (CORE_ADDR addr, char *contents_cache)
571 {
572 char bundle[BUNDLE_LEN];
573 int slotnum = (int) (addr & 0x0f) / SLOT_MULTIPLIER;
574 long long instr;
575 int val;
576 int template;
577
578 if (slotnum > 2)
579 error("Can't insert breakpoint for slot numbers greater than 2.");
580
581 addr &= ~0x0f;
582
583 val = target_read_memory (addr, bundle, BUNDLE_LEN);
584
585 /* Check for L type instruction in 2nd slot, if present then
586 bump up the slot number to the 3rd slot */
587 template = extract_bit_field (bundle, 0, 5);
588 if (slotnum == 1 && template_encoding_table[template][1] == L)
589 {
590 slotnum = 2;
591 }
592
593 instr = slotN_contents (bundle, slotnum);
594 memcpy(contents_cache, &instr, sizeof(instr));
595 replace_slotN_contents (bundle, IA64_BREAKPOINT, slotnum);
596 if (val == 0)
597 target_write_memory (addr, bundle, BUNDLE_LEN);
598
599 return val;
600 }
601
602 static int
603 ia64_memory_remove_breakpoint (CORE_ADDR addr, char *contents_cache)
604 {
605 char bundle[BUNDLE_LEN];
606 int slotnum = (addr & 0x0f) / SLOT_MULTIPLIER;
607 long long instr;
608 int val;
609 int template;
610
611 addr &= ~0x0f;
612
613 val = target_read_memory (addr, bundle, BUNDLE_LEN);
614
615 /* Check for L type instruction in 2nd slot, if present then
616 bump up the slot number to the 3rd slot */
617 template = extract_bit_field (bundle, 0, 5);
618 if (slotnum == 1 && template_encoding_table[template][1] == L)
619 {
620 slotnum = 2;
621 }
622
623 memcpy (&instr, contents_cache, sizeof instr);
624 replace_slotN_contents (bundle, instr, slotnum);
625 if (val == 0)
626 target_write_memory (addr, bundle, BUNDLE_LEN);
627
628 return val;
629 }
630
631 /* We don't really want to use this, but remote.c needs to call it in order
632 to figure out if Z-packets are supported or not. Oh, well. */
633 const unsigned char *
634 ia64_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
635 {
636 static unsigned char breakpoint[] =
637 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
638 *lenptr = sizeof (breakpoint);
639 #if 0
640 *pcptr &= ~0x0f;
641 #endif
642 return breakpoint;
643 }
644
645 static CORE_ADDR
646 ia64_read_fp (void)
647 {
648 /* We won't necessarily have a frame pointer and even if we do, it
649 winds up being extraordinarly messy when attempting to find the
650 frame chain. So for the purposes of creating frames (which is
651 all deprecated_read_fp() is used for), simply use the stack
652 pointer value instead. */
653 gdb_assert (SP_REGNUM >= 0);
654 return read_register (SP_REGNUM);
655 }
656
657 static CORE_ADDR
658 ia64_read_pc (ptid_t ptid)
659 {
660 CORE_ADDR psr_value = read_register_pid (IA64_PSR_REGNUM, ptid);
661 CORE_ADDR pc_value = read_register_pid (IA64_IP_REGNUM, ptid);
662 int slot_num = (psr_value >> 41) & 3;
663
664 return pc_value | (slot_num * SLOT_MULTIPLIER);
665 }
666
667 static void
668 ia64_write_pc (CORE_ADDR new_pc, ptid_t ptid)
669 {
670 int slot_num = (int) (new_pc & 0xf) / SLOT_MULTIPLIER;
671 CORE_ADDR psr_value = read_register_pid (IA64_PSR_REGNUM, ptid);
672 psr_value &= ~(3LL << 41);
673 psr_value |= (CORE_ADDR)(slot_num & 0x3) << 41;
674
675 new_pc &= ~0xfLL;
676
677 write_register_pid (IA64_PSR_REGNUM, psr_value, ptid);
678 write_register_pid (IA64_IP_REGNUM, new_pc, ptid);
679 }
680
681 #define IS_NaT_COLLECTION_ADDR(addr) ((((addr) >> 3) & 0x3f) == 0x3f)
682
683 /* Returns the address of the slot that's NSLOTS slots away from
684 the address ADDR. NSLOTS may be positive or negative. */
685 static CORE_ADDR
686 rse_address_add(CORE_ADDR addr, int nslots)
687 {
688 CORE_ADDR new_addr;
689 int mandatory_nat_slots = nslots / 63;
690 int direction = nslots < 0 ? -1 : 1;
691
692 new_addr = addr + 8 * (nslots + mandatory_nat_slots);
693
694 if ((new_addr >> 9) != ((addr + 8 * 64 * mandatory_nat_slots) >> 9))
695 new_addr += 8 * direction;
696
697 if (IS_NaT_COLLECTION_ADDR(new_addr))
698 new_addr += 8 * direction;
699
700 return new_addr;
701 }
702
703 static void
704 ia64_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
705 int regnum, void *buf)
706 {
707 if (regnum >= V32_REGNUM && regnum <= V127_REGNUM)
708 {
709 ULONGEST bsp;
710 ULONGEST cfm;
711 CORE_ADDR reg;
712 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
713 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
714
715 /* The bsp points at the end of the register frame so we
716 subtract the size of frame from it to get start of register frame. */
717 bsp = rse_address_add (bsp, -(cfm & 0x7f));
718
719 if ((cfm & 0x7f) > regnum - V32_REGNUM)
720 {
721 ULONGEST reg_addr = rse_address_add (bsp, (regnum - V32_REGNUM));
722 reg = read_memory_integer ((CORE_ADDR)reg_addr, 8);
723 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), reg);
724 }
725 else
726 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), 0);
727 }
728 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT31_REGNUM)
729 {
730 ULONGEST unatN_val;
731 ULONGEST unat;
732 regcache_cooked_read_unsigned (regcache, IA64_UNAT_REGNUM, &unat);
733 unatN_val = (unat & (1LL << (regnum - IA64_NAT0_REGNUM))) != 0;
734 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), unatN_val);
735 }
736 else if (IA64_NAT32_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
737 {
738 ULONGEST natN_val = 0;
739 ULONGEST bsp;
740 ULONGEST cfm;
741 CORE_ADDR gr_addr = 0;
742 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
743 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
744
745 /* The bsp points at the end of the register frame so we
746 subtract the size of frame from it to get start of register frame. */
747 bsp = rse_address_add (bsp, -(cfm & 0x7f));
748
749 if ((cfm & 0x7f) > regnum - V32_REGNUM)
750 gr_addr = rse_address_add (bsp, (regnum - V32_REGNUM));
751
752 if (gr_addr != 0)
753 {
754 /* Compute address of nat collection bits. */
755 CORE_ADDR nat_addr = gr_addr | 0x1f8;
756 CORE_ADDR nat_collection;
757 int nat_bit;
758 /* If our nat collection address is bigger than bsp, we have to get
759 the nat collection from rnat. Otherwise, we fetch the nat
760 collection from the computed address. */
761 if (nat_addr >= bsp)
762 regcache_cooked_read_unsigned (regcache, IA64_RNAT_REGNUM, &nat_collection);
763 else
764 nat_collection = read_memory_integer (nat_addr, 8);
765 nat_bit = (gr_addr >> 3) & 0x3f;
766 natN_val = (nat_collection >> nat_bit) & 1;
767 }
768
769 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), natN_val);
770 }
771 else if (regnum == VBOF_REGNUM)
772 {
773 /* A virtual register frame start is provided for user convenience.
774 It can be calculated as the bsp - sof (sizeof frame). */
775 ULONGEST bsp, vbsp;
776 ULONGEST cfm;
777 CORE_ADDR reg;
778 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
779 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
780
781 /* The bsp points at the end of the register frame so we
782 subtract the size of frame from it to get beginning of frame. */
783 vbsp = rse_address_add (bsp, -(cfm & 0x7f));
784 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), vbsp);
785 }
786 else if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
787 {
788 ULONGEST pr;
789 ULONGEST cfm;
790 ULONGEST prN_val;
791 CORE_ADDR reg;
792 regcache_cooked_read_unsigned (regcache, IA64_PR_REGNUM, &pr);
793 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
794
795 if (VP16_REGNUM <= regnum && regnum <= VP63_REGNUM)
796 {
797 /* Fetch predicate register rename base from current frame
798 marker for this frame. */
799 int rrb_pr = (cfm >> 32) & 0x3f;
800
801 /* Adjust the register number to account for register rotation. */
802 regnum = VP16_REGNUM
803 + ((regnum - VP16_REGNUM) + rrb_pr) % 48;
804 }
805 prN_val = (pr & (1LL << (regnum - VP0_REGNUM))) != 0;
806 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), prN_val);
807 }
808 else
809 memset (buf, 0, register_size (current_gdbarch, regnum));
810 }
811
812 static void
813 ia64_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
814 int regnum, const void *buf)
815 {
816 if (regnum >= V32_REGNUM && regnum <= V127_REGNUM)
817 {
818 ULONGEST bsp;
819 ULONGEST cfm;
820 CORE_ADDR reg;
821 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
822 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
823
824 bsp = rse_address_add (bsp, -(cfm & 0x7f));
825
826 if ((cfm & 0x7f) > regnum - V32_REGNUM)
827 {
828 ULONGEST reg_addr = rse_address_add (bsp, (regnum - V32_REGNUM));
829 write_memory (reg_addr, (void *)buf, 8);
830 }
831 }
832 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT31_REGNUM)
833 {
834 ULONGEST unatN_val, unat, unatN_mask;
835 regcache_cooked_read_unsigned (regcache, IA64_UNAT_REGNUM, &unat);
836 unatN_val = extract_unsigned_integer (buf, register_size (current_gdbarch, regnum));
837 unatN_mask = (1LL << (regnum - IA64_NAT0_REGNUM));
838 if (unatN_val == 0)
839 unat &= ~unatN_mask;
840 else if (unatN_val == 1)
841 unat |= unatN_mask;
842 regcache_cooked_write_unsigned (regcache, IA64_UNAT_REGNUM, unat);
843 }
844 else if (IA64_NAT32_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
845 {
846 ULONGEST natN_val;
847 ULONGEST bsp;
848 ULONGEST cfm;
849 CORE_ADDR gr_addr = 0;
850 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
851 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
852
853 /* The bsp points at the end of the register frame so we
854 subtract the size of frame from it to get start of register frame. */
855 bsp = rse_address_add (bsp, -(cfm & 0x7f));
856
857 if ((cfm & 0x7f) > regnum - V32_REGNUM)
858 gr_addr = rse_address_add (bsp, (regnum - V32_REGNUM));
859
860 natN_val = extract_unsigned_integer (buf, register_size (current_gdbarch, regnum));
861
862 if (gr_addr != 0 && (natN_val == 0 || natN_val == 1))
863 {
864 /* Compute address of nat collection bits. */
865 CORE_ADDR nat_addr = gr_addr | 0x1f8;
866 CORE_ADDR nat_collection;
867 int natN_bit = (gr_addr >> 3) & 0x3f;
868 ULONGEST natN_mask = (1LL << natN_bit);
869 /* If our nat collection address is bigger than bsp, we have to get
870 the nat collection from rnat. Otherwise, we fetch the nat
871 collection from the computed address. */
872 if (nat_addr >= bsp)
873 {
874 regcache_cooked_read_unsigned (regcache, IA64_RNAT_REGNUM, &nat_collection);
875 if (natN_val)
876 nat_collection |= natN_mask;
877 else
878 nat_collection &= ~natN_mask;
879 regcache_cooked_write_unsigned (regcache, IA64_RNAT_REGNUM, nat_collection);
880 }
881 else
882 {
883 char nat_buf[8];
884 nat_collection = read_memory_integer (nat_addr, 8);
885 if (natN_val)
886 nat_collection |= natN_mask;
887 else
888 nat_collection &= ~natN_mask;
889 store_unsigned_integer (nat_buf, register_size (current_gdbarch, regnum), nat_collection);
890 write_memory (nat_addr, nat_buf, 8);
891 }
892 }
893 }
894 else if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
895 {
896 ULONGEST pr;
897 ULONGEST cfm;
898 ULONGEST prN_val;
899 ULONGEST prN_mask;
900
901 regcache_cooked_read_unsigned (regcache, IA64_PR_REGNUM, &pr);
902 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
903
904 if (VP16_REGNUM <= regnum && regnum <= VP63_REGNUM)
905 {
906 /* Fetch predicate register rename base from current frame
907 marker for this frame. */
908 int rrb_pr = (cfm >> 32) & 0x3f;
909
910 /* Adjust the register number to account for register rotation. */
911 regnum = VP16_REGNUM
912 + ((regnum - VP16_REGNUM) + rrb_pr) % 48;
913 }
914 prN_val = extract_unsigned_integer (buf, register_size (current_gdbarch, regnum));
915 prN_mask = (1LL << (regnum - VP0_REGNUM));
916 if (prN_val == 0)
917 pr &= ~prN_mask;
918 else if (prN_val == 1)
919 pr |= prN_mask;
920 regcache_cooked_write_unsigned (regcache, IA64_PR_REGNUM, pr);
921 }
922 }
923
924 /* The ia64 needs to convert between various ieee floating-point formats
925 and the special ia64 floating point register format. */
926
927 static int
928 ia64_convert_register_p (int regno, struct type *type)
929 {
930 return (regno >= IA64_FR0_REGNUM && regno <= IA64_FR127_REGNUM);
931 }
932
933 static void
934 ia64_register_to_value (struct frame_info *frame, int regnum,
935 struct type *valtype, void *out)
936 {
937 char in[MAX_REGISTER_SIZE];
938 frame_register_read (frame, regnum, in);
939 convert_typed_floating (in, builtin_type_ia64_ext, out, valtype);
940 }
941
942 static void
943 ia64_value_to_register (struct frame_info *frame, int regnum,
944 struct type *valtype, const void *in)
945 {
946 char out[MAX_REGISTER_SIZE];
947 convert_typed_floating (in, valtype, out, builtin_type_ia64_ext);
948 put_frame_register (frame, regnum, out);
949 }
950
951
952 /* Limit the number of skipped non-prologue instructions since examining
953 of the prologue is expensive. */
954 static int max_skip_non_prologue_insns = 40;
955
956 /* Given PC representing the starting address of a function, and
957 LIM_PC which is the (sloppy) limit to which to scan when looking
958 for a prologue, attempt to further refine this limit by using
959 the line data in the symbol table. If successful, a better guess
960 on where the prologue ends is returned, otherwise the previous
961 value of lim_pc is returned. TRUST_LIMIT is a pointer to a flag
962 which will be set to indicate whether the returned limit may be
963 used with no further scanning in the event that the function is
964 frameless. */
965
966 static CORE_ADDR
967 refine_prologue_limit (CORE_ADDR pc, CORE_ADDR lim_pc, int *trust_limit)
968 {
969 struct symtab_and_line prologue_sal;
970 CORE_ADDR start_pc = pc;
971
972 /* Start off not trusting the limit. */
973 *trust_limit = 0;
974
975 prologue_sal = find_pc_line (pc, 0);
976 if (prologue_sal.line != 0)
977 {
978 int i;
979 CORE_ADDR addr = prologue_sal.end;
980
981 /* Handle the case in which compiler's optimizer/scheduler
982 has moved instructions into the prologue. We scan ahead
983 in the function looking for address ranges whose corresponding
984 line number is less than or equal to the first one that we
985 found for the function. (It can be less than when the
986 scheduler puts a body instruction before the first prologue
987 instruction.) */
988 for (i = 2 * max_skip_non_prologue_insns;
989 i > 0 && (lim_pc == 0 || addr < lim_pc);
990 i--)
991 {
992 struct symtab_and_line sal;
993
994 sal = find_pc_line (addr, 0);
995 if (sal.line == 0)
996 break;
997 if (sal.line <= prologue_sal.line
998 && sal.symtab == prologue_sal.symtab)
999 {
1000 prologue_sal = sal;
1001 }
1002 addr = sal.end;
1003 }
1004
1005 if (lim_pc == 0 || prologue_sal.end < lim_pc)
1006 {
1007 lim_pc = prologue_sal.end;
1008 if (start_pc == get_pc_function_start (lim_pc))
1009 *trust_limit = 1;
1010 }
1011 }
1012 return lim_pc;
1013 }
1014
1015 #define isScratch(_regnum_) ((_regnum_) == 2 || (_regnum_) == 3 \
1016 || (8 <= (_regnum_) && (_regnum_) <= 11) \
1017 || (14 <= (_regnum_) && (_regnum_) <= 31))
1018 #define imm9(_instr_) \
1019 ( ((((_instr_) & 0x01000000000LL) ? -1 : 0) << 8) \
1020 | (((_instr_) & 0x00008000000LL) >> 20) \
1021 | (((_instr_) & 0x00000001fc0LL) >> 6))
1022
1023 /* Allocate and initialize a frame cache. */
1024
1025 static struct ia64_frame_cache *
1026 ia64_alloc_frame_cache (void)
1027 {
1028 struct ia64_frame_cache *cache;
1029 int i;
1030
1031 cache = FRAME_OBSTACK_ZALLOC (struct ia64_frame_cache);
1032
1033 /* Base address. */
1034 cache->base = 0;
1035 cache->pc = 0;
1036 cache->cfm = 0;
1037 cache->prev_cfm = 0;
1038 cache->sof = 0;
1039 cache->sol = 0;
1040 cache->sor = 0;
1041 cache->bsp = 0;
1042 cache->fp_reg = 0;
1043 cache->frameless = 1;
1044
1045 for (i = 0; i < NUM_IA64_RAW_REGS; i++)
1046 cache->saved_regs[i] = 0;
1047
1048 return cache;
1049 }
1050
1051 static CORE_ADDR
1052 examine_prologue (CORE_ADDR pc, CORE_ADDR lim_pc, struct frame_info *next_frame, struct ia64_frame_cache *cache)
1053 {
1054 CORE_ADDR next_pc;
1055 CORE_ADDR last_prologue_pc = pc;
1056 instruction_type it;
1057 long long instr;
1058 int cfm_reg = 0;
1059 int ret_reg = 0;
1060 int fp_reg = 0;
1061 int unat_save_reg = 0;
1062 int pr_save_reg = 0;
1063 int mem_stack_frame_size = 0;
1064 int spill_reg = 0;
1065 CORE_ADDR spill_addr = 0;
1066 char instores[8];
1067 char infpstores[8];
1068 char reg_contents[256];
1069 int trust_limit;
1070 int frameless = 1;
1071 int i;
1072 CORE_ADDR addr;
1073 char buf[8];
1074 CORE_ADDR bof, sor, sol, sof, cfm, rrb_gr;
1075
1076 memset (instores, 0, sizeof instores);
1077 memset (infpstores, 0, sizeof infpstores);
1078 memset (reg_contents, 0, sizeof reg_contents);
1079
1080 if (cache->after_prologue != 0
1081 && cache->after_prologue <= lim_pc)
1082 return cache->after_prologue;
1083
1084 lim_pc = refine_prologue_limit (pc, lim_pc, &trust_limit);
1085 next_pc = fetch_instruction (pc, &it, &instr);
1086
1087 /* We want to check if we have a recognizable function start before we
1088 look ahead for a prologue. */
1089 if (pc < lim_pc && next_pc
1090 && it == M && ((instr & 0x1ee0000003fLL) == 0x02c00000000LL))
1091 {
1092 /* alloc - start of a regular function. */
1093 int sor = (int) ((instr & 0x00078000000LL) >> 27);
1094 int sol = (int) ((instr & 0x00007f00000LL) >> 20);
1095 int sof = (int) ((instr & 0x000000fe000LL) >> 13);
1096 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1097
1098 /* Verify that the current cfm matches what we think is the
1099 function start. If we have somehow jumped within a function,
1100 we do not want to interpret the prologue and calculate the
1101 addresses of various registers such as the return address.
1102 We will instead treat the frame as frameless. */
1103 if (!next_frame ||
1104 (sof == (cache->cfm & 0x7f) &&
1105 sol == ((cache->cfm >> 7) & 0x7f)))
1106 frameless = 0;
1107
1108 cfm_reg = rN;
1109 last_prologue_pc = next_pc;
1110 pc = next_pc;
1111 }
1112 else
1113 {
1114 /* Look for a leaf routine. */
1115 if (pc < lim_pc && next_pc
1116 && (it == I || it == M)
1117 && ((instr & 0x1ee00000000LL) == 0x10800000000LL))
1118 {
1119 /* adds rN = imm14, rM (or mov rN, rM when imm14 is 0) */
1120 int imm = (int) ((((instr & 0x01000000000LL) ? -1 : 0) << 13)
1121 | ((instr & 0x001f8000000LL) >> 20)
1122 | ((instr & 0x000000fe000LL) >> 13));
1123 int rM = (int) ((instr & 0x00007f00000LL) >> 20);
1124 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1125 int qp = (int) (instr & 0x0000000003fLL);
1126 if (qp == 0 && rN == 2 && imm == 0 && rM == 12 && fp_reg == 0)
1127 {
1128 /* mov r2, r12 - beginning of leaf routine */
1129 fp_reg = rN;
1130 last_prologue_pc = next_pc;
1131 }
1132 }
1133
1134 /* If we don't recognize a regular function or leaf routine, we are
1135 done. */
1136 if (!fp_reg)
1137 {
1138 pc = lim_pc;
1139 if (trust_limit)
1140 last_prologue_pc = lim_pc;
1141 }
1142 }
1143
1144 /* Loop, looking for prologue instructions, keeping track of
1145 where preserved registers were spilled. */
1146 while (pc < lim_pc)
1147 {
1148 next_pc = fetch_instruction (pc, &it, &instr);
1149 if (next_pc == 0)
1150 break;
1151
1152 if (it == B && ((instr & 0x1e1f800003f) != 0x04000000000))
1153 {
1154 /* Exit loop upon hitting a non-nop branch instruction. */
1155 if (trust_limit)
1156 lim_pc = pc;
1157 break;
1158 }
1159 else if (((instr & 0x3fLL) != 0LL) &&
1160 (frameless || ret_reg != 0))
1161 {
1162 /* Exit loop upon hitting a predicated instruction if
1163 we already have the return register or if we are frameless. */
1164 if (trust_limit)
1165 lim_pc = pc;
1166 break;
1167 }
1168 else if (it == I && ((instr & 0x1eff8000000LL) == 0x00188000000LL))
1169 {
1170 /* Move from BR */
1171 int b2 = (int) ((instr & 0x0000000e000LL) >> 13);
1172 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1173 int qp = (int) (instr & 0x0000000003f);
1174
1175 if (qp == 0 && b2 == 0 && rN >= 32 && ret_reg == 0)
1176 {
1177 ret_reg = rN;
1178 last_prologue_pc = next_pc;
1179 }
1180 }
1181 else if ((it == I || it == M)
1182 && ((instr & 0x1ee00000000LL) == 0x10800000000LL))
1183 {
1184 /* adds rN = imm14, rM (or mov rN, rM when imm14 is 0) */
1185 int imm = (int) ((((instr & 0x01000000000LL) ? -1 : 0) << 13)
1186 | ((instr & 0x001f8000000LL) >> 20)
1187 | ((instr & 0x000000fe000LL) >> 13));
1188 int rM = (int) ((instr & 0x00007f00000LL) >> 20);
1189 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1190 int qp = (int) (instr & 0x0000000003fLL);
1191
1192 if (qp == 0 && rN >= 32 && imm == 0 && rM == 12 && fp_reg == 0)
1193 {
1194 /* mov rN, r12 */
1195 fp_reg = rN;
1196 last_prologue_pc = next_pc;
1197 }
1198 else if (qp == 0 && rN == 12 && rM == 12)
1199 {
1200 /* adds r12, -mem_stack_frame_size, r12 */
1201 mem_stack_frame_size -= imm;
1202 last_prologue_pc = next_pc;
1203 }
1204 else if (qp == 0 && rN == 2
1205 && ((rM == fp_reg && fp_reg != 0) || rM == 12))
1206 {
1207 char buf[MAX_REGISTER_SIZE];
1208 CORE_ADDR saved_sp = 0;
1209 /* adds r2, spilloffset, rFramePointer
1210 or
1211 adds r2, spilloffset, r12
1212
1213 Get ready for stf.spill or st8.spill instructions.
1214 The address to start spilling at is loaded into r2.
1215 FIXME: Why r2? That's what gcc currently uses; it
1216 could well be different for other compilers. */
1217
1218 /* Hmm... whether or not this will work will depend on
1219 where the pc is. If it's still early in the prologue
1220 this'll be wrong. FIXME */
1221 if (next_frame)
1222 {
1223 frame_unwind_register (next_frame, sp_regnum, buf);
1224 saved_sp = extract_unsigned_integer (buf, 8);
1225 }
1226 spill_addr = saved_sp
1227 + (rM == 12 ? 0 : mem_stack_frame_size)
1228 + imm;
1229 spill_reg = rN;
1230 last_prologue_pc = next_pc;
1231 }
1232 else if (qp == 0 && rM >= 32 && rM < 40 && !instores[rM] &&
1233 rN < 256 && imm == 0)
1234 {
1235 /* mov rN, rM where rM is an input register */
1236 reg_contents[rN] = rM;
1237 last_prologue_pc = next_pc;
1238 }
1239 else if (frameless && qp == 0 && rN == fp_reg && imm == 0 &&
1240 rM == 2)
1241 {
1242 /* mov r12, r2 */
1243 last_prologue_pc = next_pc;
1244 break;
1245 }
1246 }
1247 else if (it == M
1248 && ( ((instr & 0x1efc0000000LL) == 0x0eec0000000LL)
1249 || ((instr & 0x1ffc8000000LL) == 0x0cec0000000LL) ))
1250 {
1251 /* stf.spill [rN] = fM, imm9
1252 or
1253 stf.spill [rN] = fM */
1254
1255 int imm = imm9(instr);
1256 int rN = (int) ((instr & 0x00007f00000LL) >> 20);
1257 int fM = (int) ((instr & 0x000000fe000LL) >> 13);
1258 int qp = (int) (instr & 0x0000000003fLL);
1259 if (qp == 0 && rN == spill_reg && spill_addr != 0
1260 && ((2 <= fM && fM <= 5) || (16 <= fM && fM <= 31)))
1261 {
1262 cache->saved_regs[IA64_FR0_REGNUM + fM] = spill_addr;
1263
1264 if ((instr & 0x1efc0000000) == 0x0eec0000000)
1265 spill_addr += imm;
1266 else
1267 spill_addr = 0; /* last one; must be done */
1268 last_prologue_pc = next_pc;
1269 }
1270 }
1271 else if ((it == M && ((instr & 0x1eff8000000LL) == 0x02110000000LL))
1272 || (it == I && ((instr & 0x1eff8000000LL) == 0x00050000000LL)) )
1273 {
1274 /* mov.m rN = arM
1275 or
1276 mov.i rN = arM */
1277
1278 int arM = (int) ((instr & 0x00007f00000LL) >> 20);
1279 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1280 int qp = (int) (instr & 0x0000000003fLL);
1281 if (qp == 0 && isScratch (rN) && arM == 36 /* ar.unat */)
1282 {
1283 /* We have something like "mov.m r3 = ar.unat". Remember the
1284 r3 (or whatever) and watch for a store of this register... */
1285 unat_save_reg = rN;
1286 last_prologue_pc = next_pc;
1287 }
1288 }
1289 else if (it == I && ((instr & 0x1eff8000000LL) == 0x00198000000LL))
1290 {
1291 /* mov rN = pr */
1292 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1293 int qp = (int) (instr & 0x0000000003fLL);
1294 if (qp == 0 && isScratch (rN))
1295 {
1296 pr_save_reg = rN;
1297 last_prologue_pc = next_pc;
1298 }
1299 }
1300 else if (it == M
1301 && ( ((instr & 0x1ffc8000000LL) == 0x08cc0000000LL)
1302 || ((instr & 0x1efc0000000LL) == 0x0acc0000000LL)))
1303 {
1304 /* st8 [rN] = rM
1305 or
1306 st8 [rN] = rM, imm9 */
1307 int rN = (int) ((instr & 0x00007f00000LL) >> 20);
1308 int rM = (int) ((instr & 0x000000fe000LL) >> 13);
1309 int qp = (int) (instr & 0x0000000003fLL);
1310 int indirect = rM < 256 ? reg_contents[rM] : 0;
1311 if (qp == 0 && rN == spill_reg && spill_addr != 0
1312 && (rM == unat_save_reg || rM == pr_save_reg))
1313 {
1314 /* We've found a spill of either the UNAT register or the PR
1315 register. (Well, not exactly; what we've actually found is
1316 a spill of the register that UNAT or PR was moved to).
1317 Record that fact and move on... */
1318 if (rM == unat_save_reg)
1319 {
1320 /* Track UNAT register */
1321 cache->saved_regs[IA64_UNAT_REGNUM] = spill_addr;
1322 unat_save_reg = 0;
1323 }
1324 else
1325 {
1326 /* Track PR register */
1327 cache->saved_regs[IA64_PR_REGNUM] = spill_addr;
1328 pr_save_reg = 0;
1329 }
1330 if ((instr & 0x1efc0000000LL) == 0x0acc0000000LL)
1331 /* st8 [rN] = rM, imm9 */
1332 spill_addr += imm9(instr);
1333 else
1334 spill_addr = 0; /* must be done spilling */
1335 last_prologue_pc = next_pc;
1336 }
1337 else if (qp == 0 && 32 <= rM && rM < 40 && !instores[rM-32])
1338 {
1339 /* Allow up to one store of each input register. */
1340 instores[rM-32] = 1;
1341 last_prologue_pc = next_pc;
1342 }
1343 else if (qp == 0 && 32 <= indirect && indirect < 40 &&
1344 !instores[indirect-32])
1345 {
1346 /* Allow an indirect store of an input register. */
1347 instores[indirect-32] = 1;
1348 last_prologue_pc = next_pc;
1349 }
1350 }
1351 else if (it == M && ((instr & 0x1ff08000000LL) == 0x08c00000000LL))
1352 {
1353 /* One of
1354 st1 [rN] = rM
1355 st2 [rN] = rM
1356 st4 [rN] = rM
1357 st8 [rN] = rM
1358 Note that the st8 case is handled in the clause above.
1359
1360 Advance over stores of input registers. One store per input
1361 register is permitted. */
1362 int rM = (int) ((instr & 0x000000fe000LL) >> 13);
1363 int qp = (int) (instr & 0x0000000003fLL);
1364 int indirect = rM < 256 ? reg_contents[rM] : 0;
1365 if (qp == 0 && 32 <= rM && rM < 40 && !instores[rM-32])
1366 {
1367 instores[rM-32] = 1;
1368 last_prologue_pc = next_pc;
1369 }
1370 else if (qp == 0 && 32 <= indirect && indirect < 40 &&
1371 !instores[indirect-32])
1372 {
1373 /* Allow an indirect store of an input register. */
1374 instores[indirect-32] = 1;
1375 last_prologue_pc = next_pc;
1376 }
1377 }
1378 else if (it == M && ((instr & 0x1ff88000000LL) == 0x0cc80000000LL))
1379 {
1380 /* Either
1381 stfs [rN] = fM
1382 or
1383 stfd [rN] = fM
1384
1385 Advance over stores of floating point input registers. Again
1386 one store per register is permitted */
1387 int fM = (int) ((instr & 0x000000fe000LL) >> 13);
1388 int qp = (int) (instr & 0x0000000003fLL);
1389 if (qp == 0 && 8 <= fM && fM < 16 && !infpstores[fM - 8])
1390 {
1391 infpstores[fM-8] = 1;
1392 last_prologue_pc = next_pc;
1393 }
1394 }
1395 else if (it == M
1396 && ( ((instr & 0x1ffc8000000LL) == 0x08ec0000000LL)
1397 || ((instr & 0x1efc0000000LL) == 0x0aec0000000LL)))
1398 {
1399 /* st8.spill [rN] = rM
1400 or
1401 st8.spill [rN] = rM, imm9 */
1402 int rN = (int) ((instr & 0x00007f00000LL) >> 20);
1403 int rM = (int) ((instr & 0x000000fe000LL) >> 13);
1404 int qp = (int) (instr & 0x0000000003fLL);
1405 if (qp == 0 && rN == spill_reg && 4 <= rM && rM <= 7)
1406 {
1407 /* We've found a spill of one of the preserved general purpose
1408 regs. Record the spill address and advance the spill
1409 register if appropriate. */
1410 cache->saved_regs[IA64_GR0_REGNUM + rM] = spill_addr;
1411 if ((instr & 0x1efc0000000LL) == 0x0aec0000000LL)
1412 /* st8.spill [rN] = rM, imm9 */
1413 spill_addr += imm9(instr);
1414 else
1415 spill_addr = 0; /* Done spilling */
1416 last_prologue_pc = next_pc;
1417 }
1418 }
1419
1420 pc = next_pc;
1421 }
1422
1423 /* If not frameless and we aren't called by skip_prologue, then we need to calculate
1424 registers for the previous frame which will be needed later. */
1425
1426 if (!frameless && next_frame)
1427 {
1428 /* Extract the size of the rotating portion of the stack
1429 frame and the register rename base from the current
1430 frame marker. */
1431 cfm = cache->cfm;
1432 sor = cache->sor;
1433 sof = cache->sof;
1434 sol = cache->sol;
1435 rrb_gr = (cfm >> 18) & 0x7f;
1436
1437 /* Find the bof (beginning of frame). */
1438 bof = rse_address_add (cache->bsp, -sof);
1439
1440 for (i = 0, addr = bof;
1441 i < sof;
1442 i++, addr += 8)
1443 {
1444 if (IS_NaT_COLLECTION_ADDR (addr))
1445 {
1446 addr += 8;
1447 }
1448 if (i+32 == cfm_reg)
1449 cache->saved_regs[IA64_CFM_REGNUM] = addr;
1450 if (i+32 == ret_reg)
1451 cache->saved_regs[IA64_VRAP_REGNUM] = addr;
1452 if (i+32 == fp_reg)
1453 cache->saved_regs[IA64_VFP_REGNUM] = addr;
1454 }
1455
1456 /* For the previous argument registers we require the previous bof.
1457 If we can't find the previous cfm, then we can do nothing. */
1458 cfm = 0;
1459 if (cache->saved_regs[IA64_CFM_REGNUM] != 0)
1460 {
1461 cfm = read_memory_integer (cache->saved_regs[IA64_CFM_REGNUM], 8);
1462 }
1463 else if (cfm_reg != 0)
1464 {
1465 frame_unwind_register (next_frame, cfm_reg, buf);
1466 cfm = extract_unsigned_integer (buf, 8);
1467 }
1468 cache->prev_cfm = cfm;
1469
1470 if (cfm != 0)
1471 {
1472 sor = ((cfm >> 14) & 0xf) * 8;
1473 sof = (cfm & 0x7f);
1474 sol = (cfm >> 7) & 0x7f;
1475 rrb_gr = (cfm >> 18) & 0x7f;
1476
1477 /* The previous bof only requires subtraction of the sol (size of locals)
1478 due to the overlap between output and input of subsequent frames. */
1479 bof = rse_address_add (bof, -sol);
1480
1481 for (i = 0, addr = bof;
1482 i < sof;
1483 i++, addr += 8)
1484 {
1485 if (IS_NaT_COLLECTION_ADDR (addr))
1486 {
1487 addr += 8;
1488 }
1489 if (i < sor)
1490 cache->saved_regs[IA64_GR32_REGNUM + ((i + (sor - rrb_gr)) % sor)]
1491 = addr;
1492 else
1493 cache->saved_regs[IA64_GR32_REGNUM + i] = addr;
1494 }
1495
1496 }
1497 }
1498
1499 /* Try and trust the lim_pc value whenever possible. */
1500 if (trust_limit && lim_pc >= last_prologue_pc)
1501 last_prologue_pc = lim_pc;
1502
1503 cache->frameless = frameless;
1504 cache->after_prologue = last_prologue_pc;
1505 cache->mem_stack_frame_size = mem_stack_frame_size;
1506 cache->fp_reg = fp_reg;
1507
1508 return last_prologue_pc;
1509 }
1510
1511 CORE_ADDR
1512 ia64_skip_prologue (CORE_ADDR pc)
1513 {
1514 struct ia64_frame_cache cache;
1515 cache.base = 0;
1516 cache.after_prologue = 0;
1517 cache.cfm = 0;
1518 cache.bsp = 0;
1519
1520 /* Call examine_prologue with - as third argument since we don't have a next frame pointer to send. */
1521 return examine_prologue (pc, pc+1024, 0, &cache);
1522 }
1523
1524
1525 /* Normal frames. */
1526
1527 static struct ia64_frame_cache *
1528 ia64_frame_cache (struct frame_info *next_frame, void **this_cache)
1529 {
1530 struct ia64_frame_cache *cache;
1531 char buf[8];
1532 CORE_ADDR cfm, sof, sol, bsp, psr;
1533 int i;
1534
1535 if (*this_cache)
1536 return *this_cache;
1537
1538 cache = ia64_alloc_frame_cache ();
1539 *this_cache = cache;
1540
1541 frame_unwind_register (next_frame, sp_regnum, buf);
1542 cache->saved_sp = extract_unsigned_integer (buf, 8);
1543
1544 /* We always want the bsp to point to the end of frame.
1545 This way, we can always get the beginning of frame (bof)
1546 by subtracting frame size. */
1547 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
1548 cache->bsp = extract_unsigned_integer (buf, 8);
1549
1550 frame_unwind_register (next_frame, IA64_PSR_REGNUM, buf);
1551 psr = extract_unsigned_integer (buf, 8);
1552
1553 frame_unwind_register (next_frame, IA64_CFM_REGNUM, buf);
1554 cfm = extract_unsigned_integer (buf, 8);
1555
1556 cache->sof = (cfm & 0x7f);
1557 cache->sol = (cfm >> 7) & 0x7f;
1558 cache->sor = ((cfm >> 14) & 0xf) * 8;
1559
1560 cache->cfm = cfm;
1561
1562 cache->pc = frame_func_unwind (next_frame);
1563
1564 if (cache->pc != 0)
1565 examine_prologue (cache->pc, frame_pc_unwind (next_frame), next_frame, cache);
1566
1567 cache->base = cache->saved_sp + cache->mem_stack_frame_size;
1568
1569 return cache;
1570 }
1571
1572 static void
1573 ia64_frame_this_id (struct frame_info *next_frame, void **this_cache,
1574 struct frame_id *this_id)
1575 {
1576 struct ia64_frame_cache *cache =
1577 ia64_frame_cache (next_frame, this_cache);
1578
1579 /* This marks the outermost frame. */
1580 if (cache->base == 0)
1581 return;
1582
1583 (*this_id) = frame_id_build_special (cache->base, cache->pc, cache->bsp);
1584 if (gdbarch_debug >= 1)
1585 fprintf_unfiltered (gdb_stdlog,
1586 "regular frame id: code %lx, stack %lx, special %lx, next_frame %p\n",
1587 this_id->code_addr, this_id->stack_addr, cache->bsp, next_frame);
1588 }
1589
1590 static void
1591 ia64_frame_prev_register (struct frame_info *next_frame, void **this_cache,
1592 int regnum, int *optimizedp,
1593 enum lval_type *lvalp, CORE_ADDR *addrp,
1594 int *realnump, void *valuep)
1595 {
1596 struct ia64_frame_cache *cache =
1597 ia64_frame_cache (next_frame, this_cache);
1598 char dummy_valp[MAX_REGISTER_SIZE];
1599 char buf[8];
1600
1601 gdb_assert (regnum >= 0);
1602
1603 if (!target_has_registers)
1604 error ("No registers.");
1605
1606 *optimizedp = 0;
1607 *addrp = 0;
1608 *lvalp = not_lval;
1609 *realnump = -1;
1610
1611 /* Rather than check each time if valuep is non-null, supply a dummy buffer
1612 when valuep is not supplied. */
1613 if (!valuep)
1614 valuep = dummy_valp;
1615
1616 memset (valuep, 0, register_size (current_gdbarch, regnum));
1617
1618 if (regnum == SP_REGNUM)
1619 {
1620 /* Handle SP values for all frames but the topmost. */
1621 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum),
1622 cache->base);
1623 }
1624 else if (regnum == IA64_BSP_REGNUM)
1625 {
1626 char cfm_valuep[MAX_REGISTER_SIZE];
1627 int cfm_optim;
1628 int cfm_realnum;
1629 enum lval_type cfm_lval;
1630 CORE_ADDR cfm_addr;
1631 CORE_ADDR bsp, prev_cfm, prev_bsp;
1632
1633 /* We want to calculate the previous bsp as the end of the previous register stack frame.
1634 This corresponds to what the hardware bsp register will be if we pop the frame
1635 back which is why we might have been called. We know the beginning of the current
1636 frame is cache->bsp - cache->sof. This value in the previous frame points to
1637 the start of the output registers. We can calculate the end of that frame by adding
1638 the size of output (sof (size of frame) - sol (size of locals)). */
1639 ia64_frame_prev_register (next_frame, this_cache, IA64_CFM_REGNUM,
1640 &cfm_optim, &cfm_lval, &cfm_addr, &cfm_realnum, cfm_valuep);
1641 prev_cfm = extract_unsigned_integer (cfm_valuep, 8);
1642
1643 bsp = rse_address_add (cache->bsp, -(cache->sof));
1644 prev_bsp = rse_address_add (bsp, (prev_cfm & 0x7f) - ((prev_cfm >> 7) & 0x7f));
1645
1646 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum),
1647 prev_bsp);
1648 }
1649 else if (regnum == IA64_CFM_REGNUM)
1650 {
1651 CORE_ADDR addr = cache->saved_regs[IA64_CFM_REGNUM];
1652
1653 if (addr != 0)
1654 {
1655 *lvalp = lval_memory;
1656 *addrp = addr;
1657 read_memory (addr, valuep, register_size (current_gdbarch, regnum));
1658 }
1659 else if (cache->prev_cfm)
1660 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum), cache->prev_cfm);
1661 else if (cache->frameless)
1662 {
1663 CORE_ADDR cfm = 0;
1664 frame_unwind_register (next_frame, IA64_PFS_REGNUM, valuep);
1665 }
1666 }
1667 else if (regnum == IA64_VFP_REGNUM)
1668 {
1669 /* If the function in question uses an automatic register (r32-r127)
1670 for the frame pointer, it'll be found by ia64_find_saved_register()
1671 above. If the function lacks one of these frame pointers, we can
1672 still provide a value since we know the size of the frame. */
1673 CORE_ADDR vfp = cache->base;
1674 store_unsigned_integer (valuep, register_size (current_gdbarch, IA64_VFP_REGNUM), vfp);
1675 }
1676 else if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
1677 {
1678 char pr_valuep[MAX_REGISTER_SIZE];
1679 int pr_optim;
1680 int pr_realnum;
1681 enum lval_type pr_lval;
1682 CORE_ADDR pr_addr;
1683 ULONGEST prN_val;
1684 ia64_frame_prev_register (next_frame, this_cache, IA64_PR_REGNUM,
1685 &pr_optim, &pr_lval, &pr_addr, &pr_realnum, pr_valuep);
1686 if (VP16_REGNUM <= regnum && regnum <= VP63_REGNUM)
1687 {
1688 /* Fetch predicate register rename base from current frame
1689 marker for this frame. */
1690 int rrb_pr = (cache->cfm >> 32) & 0x3f;
1691
1692 /* Adjust the register number to account for register rotation. */
1693 regnum = VP16_REGNUM
1694 + ((regnum - VP16_REGNUM) + rrb_pr) % 48;
1695 }
1696 prN_val = extract_bit_field ((unsigned char *) pr_valuep,
1697 regnum - VP0_REGNUM, 1);
1698 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum), prN_val);
1699 }
1700 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT31_REGNUM)
1701 {
1702 char unat_valuep[MAX_REGISTER_SIZE];
1703 int unat_optim;
1704 int unat_realnum;
1705 enum lval_type unat_lval;
1706 CORE_ADDR unat_addr;
1707 ULONGEST unatN_val;
1708 ia64_frame_prev_register (next_frame, this_cache, IA64_UNAT_REGNUM,
1709 &unat_optim, &unat_lval, &unat_addr, &unat_realnum, unat_valuep);
1710 unatN_val = extract_bit_field ((unsigned char *) unat_valuep,
1711 regnum - IA64_NAT0_REGNUM, 1);
1712 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum),
1713 unatN_val);
1714 }
1715 else if (IA64_NAT32_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
1716 {
1717 int natval = 0;
1718 /* Find address of general register corresponding to nat bit we're
1719 interested in. */
1720 CORE_ADDR gr_addr;
1721
1722 gr_addr = cache->saved_regs[regnum - IA64_NAT0_REGNUM
1723 + IA64_GR0_REGNUM];
1724 if (gr_addr != 0)
1725 {
1726 /* Compute address of nat collection bits. */
1727 CORE_ADDR nat_addr = gr_addr | 0x1f8;
1728 CORE_ADDR bsp;
1729 CORE_ADDR nat_collection;
1730 int nat_bit;
1731 /* If our nat collection address is bigger than bsp, we have to get
1732 the nat collection from rnat. Otherwise, we fetch the nat
1733 collection from the computed address. */
1734 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
1735 bsp = extract_unsigned_integer (buf, 8);
1736 if (nat_addr >= bsp)
1737 {
1738 frame_unwind_register (next_frame, IA64_RNAT_REGNUM, buf);
1739 nat_collection = extract_unsigned_integer (buf, 8);
1740 }
1741 else
1742 nat_collection = read_memory_integer (nat_addr, 8);
1743 nat_bit = (gr_addr >> 3) & 0x3f;
1744 natval = (nat_collection >> nat_bit) & 1;
1745 }
1746
1747 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum), natval);
1748 }
1749 else if (regnum == IA64_IP_REGNUM)
1750 {
1751 CORE_ADDR pc = 0;
1752 CORE_ADDR addr = cache->saved_regs[IA64_VRAP_REGNUM];
1753
1754 if (addr != 0)
1755 {
1756 *lvalp = lval_memory;
1757 *addrp = addr;
1758 read_memory (addr, buf, register_size (current_gdbarch, IA64_IP_REGNUM));
1759 pc = extract_unsigned_integer (buf, 8);
1760 }
1761 else if (cache->frameless)
1762 {
1763 frame_unwind_register (next_frame, IA64_BR0_REGNUM, buf);
1764 pc = extract_unsigned_integer (buf, 8);
1765 }
1766 pc &= ~0xf;
1767 store_unsigned_integer (valuep, 8, pc);
1768 }
1769 else if (regnum == IA64_PSR_REGNUM)
1770 {
1771 /* We don't know how to get the complete previous PSR, but we need it for
1772 the slot information when we unwind the pc (pc is formed of IP register
1773 plus slot information from PSR). To get the previous slot information,
1774 we mask it off the return address. */
1775 ULONGEST slot_num = 0;
1776 CORE_ADDR pc= 0;
1777 CORE_ADDR psr = 0;
1778 CORE_ADDR addr = cache->saved_regs[IA64_VRAP_REGNUM];
1779
1780 frame_unwind_register (next_frame, IA64_PSR_REGNUM, buf);
1781 psr = extract_unsigned_integer (buf, 8);
1782
1783 if (addr != 0)
1784 {
1785 *lvalp = lval_memory;
1786 *addrp = addr;
1787 read_memory (addr, buf, register_size (current_gdbarch, IA64_IP_REGNUM));
1788 pc = extract_unsigned_integer (buf, 8);
1789 }
1790 else if (cache->frameless)
1791 {
1792 CORE_ADDR pc;
1793 frame_unwind_register (next_frame, IA64_BR0_REGNUM, buf);
1794 pc = extract_unsigned_integer (buf, 8);
1795 }
1796 psr &= ~(3LL << 41);
1797 slot_num = pc & 0x3LL;
1798 psr |= (CORE_ADDR)slot_num << 41;
1799 store_unsigned_integer (valuep, 8, psr);
1800 }
1801 else if (regnum == IA64_BR0_REGNUM)
1802 {
1803 CORE_ADDR br0 = 0;
1804 CORE_ADDR addr = cache->saved_regs[IA64_BR0_REGNUM];
1805 if (addr != 0)
1806 {
1807 *lvalp = lval_memory;
1808 *addrp = addr;
1809 read_memory (addr, buf, register_size (current_gdbarch, IA64_BR0_REGNUM));
1810 br0 = extract_unsigned_integer (buf, 8);
1811 }
1812 store_unsigned_integer (valuep, 8, br0);
1813 }
1814 else if ((regnum >= IA64_GR32_REGNUM && regnum <= IA64_GR127_REGNUM) ||
1815 (regnum >= V32_REGNUM && regnum <= V127_REGNUM))
1816 {
1817 CORE_ADDR addr = 0;
1818 if (regnum >= V32_REGNUM)
1819 regnum = IA64_GR32_REGNUM + (regnum - V32_REGNUM);
1820 addr = cache->saved_regs[regnum];
1821 if (addr != 0)
1822 {
1823 *lvalp = lval_memory;
1824 *addrp = addr;
1825 read_memory (addr, valuep, register_size (current_gdbarch, regnum));
1826 }
1827 else if (cache->frameless)
1828 {
1829 char r_valuep[MAX_REGISTER_SIZE];
1830 int r_optim;
1831 int r_realnum;
1832 enum lval_type r_lval;
1833 CORE_ADDR r_addr;
1834 CORE_ADDR prev_cfm, prev_bsp, prev_bof;
1835 CORE_ADDR addr = 0;
1836 if (regnum >= V32_REGNUM)
1837 regnum = IA64_GR32_REGNUM + (regnum - V32_REGNUM);
1838 ia64_frame_prev_register (next_frame, this_cache, IA64_CFM_REGNUM,
1839 &r_optim, &r_lval, &r_addr, &r_realnum, r_valuep);
1840 prev_cfm = extract_unsigned_integer (r_valuep, 8);
1841 ia64_frame_prev_register (next_frame, this_cache, IA64_BSP_REGNUM,
1842 &r_optim, &r_lval, &r_addr, &r_realnum, r_valuep);
1843 prev_bsp = extract_unsigned_integer (r_valuep, 8);
1844 prev_bof = rse_address_add (prev_bsp, -(prev_cfm & 0x7f));
1845
1846 addr = rse_address_add (prev_bof, (regnum - IA64_GR32_REGNUM));
1847 *lvalp = lval_memory;
1848 *addrp = addr;
1849 read_memory (addr, valuep, register_size (current_gdbarch, regnum));
1850 }
1851 }
1852 else
1853 {
1854 CORE_ADDR addr = 0;
1855 if (IA64_FR32_REGNUM <= regnum && regnum <= IA64_FR127_REGNUM)
1856 {
1857 /* Fetch floating point register rename base from current
1858 frame marker for this frame. */
1859 int rrb_fr = (cache->cfm >> 25) & 0x7f;
1860
1861 /* Adjust the floating point register number to account for
1862 register rotation. */
1863 regnum = IA64_FR32_REGNUM
1864 + ((regnum - IA64_FR32_REGNUM) + rrb_fr) % 96;
1865 }
1866
1867 /* If we have stored a memory address, access the register. */
1868 addr = cache->saved_regs[regnum];
1869 if (addr != 0)
1870 {
1871 *lvalp = lval_memory;
1872 *addrp = addr;
1873 read_memory (addr, valuep, register_size (current_gdbarch, regnum));
1874 }
1875 /* Otherwise, punt and get the current value of the register. */
1876 else
1877 frame_unwind_register (next_frame, regnum, valuep);
1878 }
1879
1880 if (gdbarch_debug >= 1)
1881 fprintf_unfiltered (gdb_stdlog,
1882 "regular prev register <%d> <%s> is %lx\n", regnum,
1883 (((unsigned) regnum <= IA64_NAT127_REGNUM)
1884 ? ia64_register_names[regnum] : "r??"), extract_unsigned_integer (valuep, 8));
1885 }
1886
1887 static const struct frame_unwind ia64_frame_unwind =
1888 {
1889 NORMAL_FRAME,
1890 &ia64_frame_this_id,
1891 &ia64_frame_prev_register
1892 };
1893
1894 static const struct frame_unwind *
1895 ia64_frame_sniffer (struct frame_info *next_frame)
1896 {
1897 return &ia64_frame_unwind;
1898 }
1899
1900 /* Signal trampolines. */
1901
1902 static void
1903 ia64_sigtramp_frame_init_saved_regs (struct ia64_frame_cache *cache)
1904 {
1905 if (SIGCONTEXT_REGISTER_ADDRESS)
1906 {
1907 int regno;
1908
1909 cache->saved_regs[IA64_VRAP_REGNUM] =
1910 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_IP_REGNUM);
1911 cache->saved_regs[IA64_CFM_REGNUM] =
1912 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_CFM_REGNUM);
1913 cache->saved_regs[IA64_PSR_REGNUM] =
1914 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_PSR_REGNUM);
1915 cache->saved_regs[IA64_BSP_REGNUM] =
1916 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_BSP_REGNUM);
1917 cache->saved_regs[IA64_RNAT_REGNUM] =
1918 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_RNAT_REGNUM);
1919 cache->saved_regs[IA64_CCV_REGNUM] =
1920 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_CCV_REGNUM);
1921 cache->saved_regs[IA64_UNAT_REGNUM] =
1922 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_UNAT_REGNUM);
1923 cache->saved_regs[IA64_FPSR_REGNUM] =
1924 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_FPSR_REGNUM);
1925 cache->saved_regs[IA64_PFS_REGNUM] =
1926 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_PFS_REGNUM);
1927 cache->saved_regs[IA64_LC_REGNUM] =
1928 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_LC_REGNUM);
1929 for (regno = IA64_GR1_REGNUM; regno <= IA64_GR31_REGNUM; regno++)
1930 cache->saved_regs[regno] =
1931 SIGCONTEXT_REGISTER_ADDRESS (cache->base, regno);
1932 for (regno = IA64_BR0_REGNUM; regno <= IA64_BR7_REGNUM; regno++)
1933 cache->saved_regs[regno] =
1934 SIGCONTEXT_REGISTER_ADDRESS (cache->base, regno);
1935 for (regno = IA64_FR2_REGNUM; regno <= IA64_FR31_REGNUM; regno++)
1936 cache->saved_regs[regno] =
1937 SIGCONTEXT_REGISTER_ADDRESS (cache->base, regno);
1938 }
1939 }
1940
1941 static struct ia64_frame_cache *
1942 ia64_sigtramp_frame_cache (struct frame_info *next_frame, void **this_cache)
1943 {
1944 struct ia64_frame_cache *cache;
1945 CORE_ADDR addr;
1946 char buf[8];
1947 int i;
1948
1949 if (*this_cache)
1950 return *this_cache;
1951
1952 cache = ia64_alloc_frame_cache ();
1953
1954 frame_unwind_register (next_frame, sp_regnum, buf);
1955 /* Note that frame size is hard-coded below. We cannot calculate it
1956 via prologue examination. */
1957 cache->base = extract_unsigned_integer (buf, 8) + 16;
1958
1959 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
1960 cache->bsp = extract_unsigned_integer (buf, 8);
1961
1962 frame_unwind_register (next_frame, IA64_CFM_REGNUM, buf);
1963 cache->cfm = extract_unsigned_integer (buf, 8);
1964 cache->sof = cache->cfm & 0x7f;
1965
1966 ia64_sigtramp_frame_init_saved_regs (cache);
1967
1968 *this_cache = cache;
1969 return cache;
1970 }
1971
1972 static void
1973 ia64_sigtramp_frame_this_id (struct frame_info *next_frame,
1974 void **this_cache, struct frame_id *this_id)
1975 {
1976 struct ia64_frame_cache *cache =
1977 ia64_sigtramp_frame_cache (next_frame, this_cache);
1978
1979 (*this_id) = frame_id_build_special (cache->base, frame_pc_unwind (next_frame), cache->bsp);
1980 if (gdbarch_debug >= 1)
1981 fprintf_unfiltered (gdb_stdlog,
1982 "sigtramp frame id: code %lx, stack %lx, special %lx, next_frame %p\n",
1983 this_id->code_addr, this_id->stack_addr, cache->bsp, next_frame);
1984 }
1985
1986 static void
1987 ia64_sigtramp_frame_prev_register (struct frame_info *next_frame,
1988 void **this_cache,
1989 int regnum, int *optimizedp,
1990 enum lval_type *lvalp, CORE_ADDR *addrp,
1991 int *realnump, void *valuep)
1992 {
1993 char dummy_valp[MAX_REGISTER_SIZE];
1994 char buf[MAX_REGISTER_SIZE];
1995
1996 struct ia64_frame_cache *cache =
1997 ia64_sigtramp_frame_cache (next_frame, this_cache);
1998
1999 gdb_assert (regnum >= 0);
2000
2001 if (!target_has_registers)
2002 error ("No registers.");
2003
2004 *optimizedp = 0;
2005 *addrp = 0;
2006 *lvalp = not_lval;
2007 *realnump = -1;
2008
2009 /* Rather than check each time if valuep is non-null, supply a dummy buffer
2010 when valuep is not supplied. */
2011 if (!valuep)
2012 valuep = dummy_valp;
2013
2014 memset (valuep, 0, register_size (current_gdbarch, regnum));
2015
2016 if (regnum == IA64_IP_REGNUM)
2017 {
2018 CORE_ADDR pc = 0;
2019 CORE_ADDR addr = cache->saved_regs[IA64_VRAP_REGNUM];
2020
2021 if (addr != 0)
2022 {
2023 *lvalp = lval_memory;
2024 *addrp = addr;
2025 read_memory (addr, buf, register_size (current_gdbarch, IA64_IP_REGNUM));
2026 pc = extract_unsigned_integer (buf, 8);
2027 }
2028 pc &= ~0xf;
2029 store_unsigned_integer (valuep, 8, pc);
2030 }
2031 else if ((regnum >= IA64_GR32_REGNUM && regnum <= IA64_GR127_REGNUM) ||
2032 (regnum >= V32_REGNUM && regnum <= V127_REGNUM))
2033 {
2034 CORE_ADDR addr = 0;
2035 if (regnum >= V32_REGNUM)
2036 regnum = IA64_GR32_REGNUM + (regnum - V32_REGNUM);
2037 addr = cache->saved_regs[regnum];
2038 if (addr != 0)
2039 {
2040 *lvalp = lval_memory;
2041 *addrp = addr;
2042 read_memory (addr, valuep, register_size (current_gdbarch, regnum));
2043 }
2044 }
2045 else
2046 {
2047 /* All other registers not listed above. */
2048 CORE_ADDR addr = cache->saved_regs[regnum];
2049 if (addr != 0)
2050 {
2051 *lvalp = lval_memory;
2052 *addrp = addr;
2053 read_memory (addr, valuep, register_size (current_gdbarch, regnum));
2054 }
2055 }
2056
2057 if (gdbarch_debug >= 1)
2058 fprintf_unfiltered (gdb_stdlog,
2059 "sigtramp prev register <%s> is %lx\n",
2060 (((unsigned) regnum <= IA64_NAT127_REGNUM)
2061 ? ia64_register_names[regnum] : "r??"), extract_unsigned_integer (valuep, 8));
2062 }
2063
2064 static const struct frame_unwind ia64_sigtramp_frame_unwind =
2065 {
2066 SIGTRAMP_FRAME,
2067 ia64_sigtramp_frame_this_id,
2068 ia64_sigtramp_frame_prev_register
2069 };
2070
2071 static const struct frame_unwind *
2072 ia64_sigtramp_frame_sniffer (struct frame_info *next_frame)
2073 {
2074 char *name;
2075 CORE_ADDR pc = frame_pc_unwind (next_frame);
2076
2077 find_pc_partial_function (pc, &name, NULL, NULL);
2078 if (PC_IN_SIGTRAMP (pc, name))
2079 return &ia64_sigtramp_frame_unwind;
2080
2081 return NULL;
2082 }
2083 \f
2084
2085 static CORE_ADDR
2086 ia64_frame_base_address (struct frame_info *next_frame, void **this_cache)
2087 {
2088 struct ia64_frame_cache *cache =
2089 ia64_frame_cache (next_frame, this_cache);
2090
2091 return cache->base;
2092 }
2093
2094 static const struct frame_base ia64_frame_base =
2095 {
2096 &ia64_frame_unwind,
2097 ia64_frame_base_address,
2098 ia64_frame_base_address,
2099 ia64_frame_base_address
2100 };
2101
2102 /* Should we use EXTRACT_STRUCT_VALUE_ADDRESS instead of
2103 EXTRACT_RETURN_VALUE? GCC_P is true if compiled with gcc
2104 and TYPE is the type (which is known to be struct, union or array). */
2105 int
2106 ia64_use_struct_convention (int gcc_p, struct type *type)
2107 {
2108 struct type *float_elt_type;
2109
2110 /* HFAs are structures (or arrays) consisting entirely of floating
2111 point values of the same length. Up to 8 of these are returned
2112 in registers. Don't use the struct convention when this is the
2113 case. */
2114 float_elt_type = is_float_or_hfa_type (type);
2115 if (float_elt_type != NULL
2116 && TYPE_LENGTH (type) / TYPE_LENGTH (float_elt_type) <= 8)
2117 return 0;
2118
2119 /* Other structs of length 32 or less are returned in r8-r11.
2120 Don't use the struct convention for those either. */
2121 return TYPE_LENGTH (type) > 32;
2122 }
2123
2124 void
2125 ia64_extract_return_value (struct type *type, struct regcache *regcache, void *valbuf)
2126 {
2127 struct type *float_elt_type;
2128
2129 float_elt_type = is_float_or_hfa_type (type);
2130 if (float_elt_type != NULL)
2131 {
2132 char from[MAX_REGISTER_SIZE];
2133 int offset = 0;
2134 int regnum = IA64_FR8_REGNUM;
2135 int n = TYPE_LENGTH (type) / TYPE_LENGTH (float_elt_type);
2136
2137 while (n-- > 0)
2138 {
2139 regcache_cooked_read (regcache, regnum, from);
2140 convert_typed_floating (from, builtin_type_ia64_ext,
2141 (char *)valbuf + offset, float_elt_type);
2142 offset += TYPE_LENGTH (float_elt_type);
2143 regnum++;
2144 }
2145 }
2146 else
2147 {
2148 ULONGEST val;
2149 int offset = 0;
2150 int regnum = IA64_GR8_REGNUM;
2151 int reglen = TYPE_LENGTH (ia64_register_type (NULL, IA64_GR8_REGNUM));
2152 int n = TYPE_LENGTH (type) / reglen;
2153 int m = TYPE_LENGTH (type) % reglen;
2154
2155 while (n-- > 0)
2156 {
2157 ULONGEST val;
2158 regcache_cooked_read_unsigned (regcache, regnum, &val);
2159 memcpy ((char *)valbuf + offset, &val, reglen);
2160 offset += reglen;
2161 regnum++;
2162 }
2163
2164 if (m)
2165 {
2166 regcache_cooked_read_unsigned (regcache, regnum, &val);
2167 memcpy ((char *)valbuf + offset, &val, m);
2168 }
2169 }
2170 }
2171
2172 CORE_ADDR
2173 ia64_extract_struct_value_address (struct regcache *regcache)
2174 {
2175 error ("ia64_extract_struct_value_address called and cannot get struct value address");
2176 return 0;
2177 }
2178
2179
2180 static int
2181 is_float_or_hfa_type_recurse (struct type *t, struct type **etp)
2182 {
2183 switch (TYPE_CODE (t))
2184 {
2185 case TYPE_CODE_FLT:
2186 if (*etp)
2187 return TYPE_LENGTH (*etp) == TYPE_LENGTH (t);
2188 else
2189 {
2190 *etp = t;
2191 return 1;
2192 }
2193 break;
2194 case TYPE_CODE_ARRAY:
2195 return
2196 is_float_or_hfa_type_recurse (check_typedef (TYPE_TARGET_TYPE (t)),
2197 etp);
2198 break;
2199 case TYPE_CODE_STRUCT:
2200 {
2201 int i;
2202
2203 for (i = 0; i < TYPE_NFIELDS (t); i++)
2204 if (!is_float_or_hfa_type_recurse
2205 (check_typedef (TYPE_FIELD_TYPE (t, i)), etp))
2206 return 0;
2207 return 1;
2208 }
2209 break;
2210 default:
2211 return 0;
2212 break;
2213 }
2214 }
2215
2216 /* Determine if the given type is one of the floating point types or
2217 and HFA (which is a struct, array, or combination thereof whose
2218 bottom-most elements are all of the same floating point type). */
2219
2220 static struct type *
2221 is_float_or_hfa_type (struct type *t)
2222 {
2223 struct type *et = 0;
2224
2225 return is_float_or_hfa_type_recurse (t, &et) ? et : 0;
2226 }
2227
2228
2229 /* Return 1 if the alignment of T is such that the next even slot
2230 should be used. Return 0, if the next available slot should
2231 be used. (See section 8.5.1 of the IA-64 Software Conventions
2232 and Runtime manual). */
2233
2234 static int
2235 slot_alignment_is_next_even (struct type *t)
2236 {
2237 switch (TYPE_CODE (t))
2238 {
2239 case TYPE_CODE_INT:
2240 case TYPE_CODE_FLT:
2241 if (TYPE_LENGTH (t) > 8)
2242 return 1;
2243 else
2244 return 0;
2245 case TYPE_CODE_ARRAY:
2246 return
2247 slot_alignment_is_next_even (check_typedef (TYPE_TARGET_TYPE (t)));
2248 case TYPE_CODE_STRUCT:
2249 {
2250 int i;
2251
2252 for (i = 0; i < TYPE_NFIELDS (t); i++)
2253 if (slot_alignment_is_next_even
2254 (check_typedef (TYPE_FIELD_TYPE (t, i))))
2255 return 1;
2256 return 0;
2257 }
2258 default:
2259 return 0;
2260 }
2261 }
2262
2263 /* Attempt to find (and return) the global pointer for the given
2264 function.
2265
2266 This is a rather nasty bit of code searchs for the .dynamic section
2267 in the objfile corresponding to the pc of the function we're trying
2268 to call. Once it finds the addresses at which the .dynamic section
2269 lives in the child process, it scans the Elf64_Dyn entries for a
2270 DT_PLTGOT tag. If it finds one of these, the corresponding
2271 d_un.d_ptr value is the global pointer. */
2272
2273 static CORE_ADDR
2274 generic_elf_find_global_pointer (CORE_ADDR faddr)
2275 {
2276 struct obj_section *faddr_sect;
2277
2278 faddr_sect = find_pc_section (faddr);
2279 if (faddr_sect != NULL)
2280 {
2281 struct obj_section *osect;
2282
2283 ALL_OBJFILE_OSECTIONS (faddr_sect->objfile, osect)
2284 {
2285 if (strcmp (osect->the_bfd_section->name, ".dynamic") == 0)
2286 break;
2287 }
2288
2289 if (osect < faddr_sect->objfile->sections_end)
2290 {
2291 CORE_ADDR addr;
2292
2293 addr = osect->addr;
2294 while (addr < osect->endaddr)
2295 {
2296 int status;
2297 LONGEST tag;
2298 char buf[8];
2299
2300 status = target_read_memory (addr, buf, sizeof (buf));
2301 if (status != 0)
2302 break;
2303 tag = extract_signed_integer (buf, sizeof (buf));
2304
2305 if (tag == DT_PLTGOT)
2306 {
2307 CORE_ADDR global_pointer;
2308
2309 status = target_read_memory (addr + 8, buf, sizeof (buf));
2310 if (status != 0)
2311 break;
2312 global_pointer = extract_unsigned_integer (buf, sizeof (buf));
2313
2314 /* The payoff... */
2315 return global_pointer;
2316 }
2317
2318 if (tag == DT_NULL)
2319 break;
2320
2321 addr += 16;
2322 }
2323 }
2324 }
2325 return 0;
2326 }
2327
2328 /* Given a function's address, attempt to find (and return) the
2329 corresponding (canonical) function descriptor. Return 0 if
2330 not found. */
2331 static CORE_ADDR
2332 find_extant_func_descr (CORE_ADDR faddr)
2333 {
2334 struct obj_section *faddr_sect;
2335
2336 /* Return early if faddr is already a function descriptor. */
2337 faddr_sect = find_pc_section (faddr);
2338 if (faddr_sect && strcmp (faddr_sect->the_bfd_section->name, ".opd") == 0)
2339 return faddr;
2340
2341 if (faddr_sect != NULL)
2342 {
2343 struct obj_section *osect;
2344 ALL_OBJFILE_OSECTIONS (faddr_sect->objfile, osect)
2345 {
2346 if (strcmp (osect->the_bfd_section->name, ".opd") == 0)
2347 break;
2348 }
2349
2350 if (osect < faddr_sect->objfile->sections_end)
2351 {
2352 CORE_ADDR addr;
2353
2354 addr = osect->addr;
2355 while (addr < osect->endaddr)
2356 {
2357 int status;
2358 LONGEST faddr2;
2359 char buf[8];
2360
2361 status = target_read_memory (addr, buf, sizeof (buf));
2362 if (status != 0)
2363 break;
2364 faddr2 = extract_signed_integer (buf, sizeof (buf));
2365
2366 if (faddr == faddr2)
2367 return addr;
2368
2369 addr += 16;
2370 }
2371 }
2372 }
2373 return 0;
2374 }
2375
2376 /* Attempt to find a function descriptor corresponding to the
2377 given address. If none is found, construct one on the
2378 stack using the address at fdaptr. */
2379
2380 static CORE_ADDR
2381 find_func_descr (CORE_ADDR faddr, CORE_ADDR *fdaptr)
2382 {
2383 CORE_ADDR fdesc;
2384
2385 fdesc = find_extant_func_descr (faddr);
2386
2387 if (fdesc == 0)
2388 {
2389 CORE_ADDR global_pointer;
2390 char buf[16];
2391
2392 fdesc = *fdaptr;
2393 *fdaptr += 16;
2394
2395 global_pointer = FIND_GLOBAL_POINTER (faddr);
2396
2397 if (global_pointer == 0)
2398 global_pointer = read_register (IA64_GR1_REGNUM);
2399
2400 store_unsigned_integer (buf, 8, faddr);
2401 store_unsigned_integer (buf + 8, 8, global_pointer);
2402
2403 write_memory (fdesc, buf, 16);
2404 }
2405
2406 return fdesc;
2407 }
2408
2409 /* Use the following routine when printing out function pointers
2410 so the user can see the function address rather than just the
2411 function descriptor. */
2412 static CORE_ADDR
2413 ia64_convert_from_func_ptr_addr (struct gdbarch *gdbarch, CORE_ADDR addr,
2414 struct target_ops *targ)
2415 {
2416 struct obj_section *s;
2417
2418 s = find_pc_section (addr);
2419
2420 /* check if ADDR points to a function descriptor. */
2421 if (s && strcmp (s->the_bfd_section->name, ".opd") == 0)
2422 return read_memory_unsigned_integer (addr, 8);
2423
2424 return addr;
2425 }
2426
2427 static CORE_ADDR
2428 ia64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
2429 {
2430 return sp & ~0xfLL;
2431 }
2432
2433 static CORE_ADDR
2434 ia64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
2435 struct regcache *regcache, CORE_ADDR bp_addr,
2436 int nargs, struct value **args, CORE_ADDR sp,
2437 int struct_return, CORE_ADDR struct_addr)
2438 {
2439 int argno;
2440 struct value *arg;
2441 struct type *type;
2442 int len, argoffset;
2443 int nslots, rseslots, memslots, slotnum, nfuncargs;
2444 int floatreg;
2445 CORE_ADDR bsp, cfm, pfs, new_bsp, funcdescaddr, pc, global_pointer;
2446
2447 nslots = 0;
2448 nfuncargs = 0;
2449 /* Count the number of slots needed for the arguments. */
2450 for (argno = 0; argno < nargs; argno++)
2451 {
2452 arg = args[argno];
2453 type = check_typedef (VALUE_TYPE (arg));
2454 len = TYPE_LENGTH (type);
2455
2456 if ((nslots & 1) && slot_alignment_is_next_even (type))
2457 nslots++;
2458
2459 if (TYPE_CODE (type) == TYPE_CODE_FUNC)
2460 nfuncargs++;
2461
2462 nslots += (len + 7) / 8;
2463 }
2464
2465 /* Divvy up the slots between the RSE and the memory stack. */
2466 rseslots = (nslots > 8) ? 8 : nslots;
2467 memslots = nslots - rseslots;
2468
2469 /* Allocate a new RSE frame. */
2470 cfm = read_register (IA64_CFM_REGNUM);
2471
2472 bsp = read_register (IA64_BSP_REGNUM);
2473 new_bsp = rse_address_add (bsp, rseslots);
2474 write_register (IA64_BSP_REGNUM, new_bsp);
2475
2476 pfs = read_register (IA64_PFS_REGNUM);
2477 pfs &= 0xc000000000000000LL;
2478 pfs |= (cfm & 0xffffffffffffLL);
2479 write_register (IA64_PFS_REGNUM, pfs);
2480
2481 cfm &= 0xc000000000000000LL;
2482 cfm |= rseslots;
2483 write_register (IA64_CFM_REGNUM, cfm);
2484
2485 /* We will attempt to find function descriptors in the .opd segment,
2486 but if we can't we'll construct them ourselves. That being the
2487 case, we'll need to reserve space on the stack for them. */
2488 funcdescaddr = sp - nfuncargs * 16;
2489 funcdescaddr &= ~0xfLL;
2490
2491 /* Adjust the stack pointer to it's new value. The calling conventions
2492 require us to have 16 bytes of scratch, plus whatever space is
2493 necessary for the memory slots and our function descriptors. */
2494 sp = sp - 16 - (memslots + nfuncargs) * 8;
2495 sp &= ~0xfLL; /* Maintain 16 byte alignment. */
2496
2497 /* Place the arguments where they belong. The arguments will be
2498 either placed in the RSE backing store or on the memory stack.
2499 In addition, floating point arguments or HFAs are placed in
2500 floating point registers. */
2501 slotnum = 0;
2502 floatreg = IA64_FR8_REGNUM;
2503 for (argno = 0; argno < nargs; argno++)
2504 {
2505 struct type *float_elt_type;
2506
2507 arg = args[argno];
2508 type = check_typedef (VALUE_TYPE (arg));
2509 len = TYPE_LENGTH (type);
2510
2511 /* Special handling for function parameters. */
2512 if (len == 8
2513 && TYPE_CODE (type) == TYPE_CODE_PTR
2514 && TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC)
2515 {
2516 char val_buf[8];
2517
2518 store_unsigned_integer (val_buf, 8,
2519 find_func_descr (extract_unsigned_integer (VALUE_CONTENTS (arg), 8),
2520 &funcdescaddr));
2521 if (slotnum < rseslots)
2522 write_memory (rse_address_add (bsp, slotnum), val_buf, 8);
2523 else
2524 write_memory (sp + 16 + 8 * (slotnum - rseslots), val_buf, 8);
2525 slotnum++;
2526 continue;
2527 }
2528
2529 /* Normal slots. */
2530
2531 /* Skip odd slot if necessary... */
2532 if ((slotnum & 1) && slot_alignment_is_next_even (type))
2533 slotnum++;
2534
2535 argoffset = 0;
2536 while (len > 0)
2537 {
2538 char val_buf[8];
2539
2540 memset (val_buf, 0, 8);
2541 memcpy (val_buf, VALUE_CONTENTS (arg) + argoffset, (len > 8) ? 8 : len);
2542
2543 if (slotnum < rseslots)
2544 write_memory (rse_address_add (bsp, slotnum), val_buf, 8);
2545 else
2546 write_memory (sp + 16 + 8 * (slotnum - rseslots), val_buf, 8);
2547
2548 argoffset += 8;
2549 len -= 8;
2550 slotnum++;
2551 }
2552
2553 /* Handle floating point types (including HFAs). */
2554 float_elt_type = is_float_or_hfa_type (type);
2555 if (float_elt_type != NULL)
2556 {
2557 argoffset = 0;
2558 len = TYPE_LENGTH (type);
2559 while (len > 0 && floatreg < IA64_FR16_REGNUM)
2560 {
2561 char to[MAX_REGISTER_SIZE];
2562 convert_typed_floating (VALUE_CONTENTS (arg) + argoffset, float_elt_type,
2563 to, builtin_type_ia64_ext);
2564 regcache_cooked_write (regcache, floatreg, (void *)to);
2565 floatreg++;
2566 argoffset += TYPE_LENGTH (float_elt_type);
2567 len -= TYPE_LENGTH (float_elt_type);
2568 }
2569 }
2570 }
2571
2572 /* Store the struct return value in r8 if necessary. */
2573 if (struct_return)
2574 {
2575 regcache_cooked_write_unsigned (regcache, IA64_GR8_REGNUM, (ULONGEST)struct_addr);
2576 }
2577
2578 global_pointer = FIND_GLOBAL_POINTER (func_addr);
2579
2580 if (global_pointer != 0)
2581 write_register (IA64_GR1_REGNUM, global_pointer);
2582
2583 write_register (IA64_BR0_REGNUM, bp_addr);
2584
2585 write_register (sp_regnum, sp);
2586
2587 return sp;
2588 }
2589
2590 static struct frame_id
2591 ia64_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
2592 {
2593 char buf[8];
2594 CORE_ADDR sp, bsp;
2595
2596 frame_unwind_register (next_frame, sp_regnum, buf);
2597 sp = extract_unsigned_integer (buf, 8);
2598
2599 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
2600 bsp = extract_unsigned_integer (buf, 8);
2601
2602 if (gdbarch_debug >= 1)
2603 fprintf_unfiltered (gdb_stdlog,
2604 "dummy frame id: code %lx, stack %lx, special %lx\n",
2605 frame_pc_unwind (next_frame), sp, bsp);
2606
2607 return frame_id_build_special (sp, frame_pc_unwind (next_frame), bsp);
2608 }
2609
2610 static CORE_ADDR
2611 ia64_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
2612 {
2613 char buf[8];
2614 CORE_ADDR ip, psr, pc;
2615
2616 frame_unwind_register (next_frame, IA64_IP_REGNUM, buf);
2617 ip = extract_unsigned_integer (buf, 8);
2618 frame_unwind_register (next_frame, IA64_PSR_REGNUM, buf);
2619 psr = extract_unsigned_integer (buf, 8);
2620
2621 pc = (ip & ~0xf) | ((psr >> 41) & 3);
2622 return pc;
2623 }
2624
2625 static void
2626 ia64_store_return_value (struct type *type, struct regcache *regcache, const void *valbuf)
2627 {
2628 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2629 {
2630 char to[MAX_REGISTER_SIZE];
2631 convert_typed_floating (valbuf, type, to, builtin_type_ia64_ext);
2632 regcache_cooked_write (regcache, IA64_FR8_REGNUM, (void *)to);
2633 target_store_registers (IA64_FR8_REGNUM);
2634 }
2635 else
2636 regcache_cooked_write (regcache, IA64_GR8_REGNUM, valbuf);
2637 }
2638
2639 static void
2640 ia64_remote_translate_xfer_address (struct gdbarch *gdbarch,
2641 struct regcache *regcache,
2642 CORE_ADDR memaddr, int nr_bytes,
2643 CORE_ADDR *targ_addr, int *targ_len)
2644 {
2645 *targ_addr = memaddr;
2646 *targ_len = nr_bytes;
2647 }
2648
2649 static void
2650 process_note_abi_tag_sections (bfd *abfd, asection *sect, void *obj)
2651 {
2652 int *os_ident_ptr = obj;
2653 const char *name;
2654 unsigned int sectsize;
2655
2656 name = bfd_get_section_name (abfd, sect);
2657 sectsize = bfd_section_size (abfd, sect);
2658 if (strcmp (name, ".note.ABI-tag") == 0 && sectsize > 0)
2659 {
2660 unsigned int name_length, data_length, note_type;
2661 char *note = alloca (sectsize);
2662
2663 bfd_get_section_contents (abfd, sect, note,
2664 (file_ptr) 0, (bfd_size_type) sectsize);
2665
2666 name_length = bfd_h_get_32 (abfd, note);
2667 data_length = bfd_h_get_32 (abfd, note + 4);
2668 note_type = bfd_h_get_32 (abfd, note + 8);
2669
2670 if (name_length == 4 && data_length == 16 && note_type == 1
2671 && strcmp (note + 12, "GNU") == 0)
2672 {
2673 int os_number = bfd_h_get_32 (abfd, note + 16);
2674
2675 /* The case numbers are from abi-tags in glibc. */
2676 switch (os_number)
2677 {
2678 case 0 :
2679 *os_ident_ptr = ELFOSABI_LINUX;
2680 break;
2681 case 1 :
2682 *os_ident_ptr = ELFOSABI_HURD;
2683 break;
2684 case 2 :
2685 *os_ident_ptr = ELFOSABI_SOLARIS;
2686 break;
2687 default :
2688 internal_error (__FILE__, __LINE__,
2689 "process_note_abi_sections: unknown OS number %d", os_number);
2690 break;
2691 }
2692 }
2693 }
2694 }
2695
2696 static int
2697 ia64_print_insn (bfd_vma memaddr, struct disassemble_info *info)
2698 {
2699 info->bytes_per_line = SLOT_MULTIPLIER;
2700 return print_insn_ia64 (memaddr, info);
2701 }
2702
2703 static struct gdbarch *
2704 ia64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2705 {
2706 struct gdbarch *gdbarch;
2707 struct gdbarch_tdep *tdep;
2708
2709 /* If there is already a candidate, use it. */
2710 arches = gdbarch_list_lookup_by_info (arches, &info);
2711 if (arches != NULL)
2712 return arches->gdbarch;
2713
2714 tdep = xmalloc (sizeof (struct gdbarch_tdep));
2715 gdbarch = gdbarch_alloc (&info, tdep);
2716
2717 /* Set the method of obtaining the sigcontext addresses at which
2718 registers are saved. The method of checking to see if
2719 native_find_global_pointer is nonzero to indicate that we're
2720 on AIX is kind of hokey, but I can't think of a better way
2721 to do it. */
2722 if (info.osabi == GDB_OSABI_LINUX)
2723 tdep->sigcontext_register_address = ia64_linux_sigcontext_register_address;
2724 else if (native_find_global_pointer != 0)
2725 tdep->sigcontext_register_address = ia64_aix_sigcontext_register_address;
2726 else
2727 tdep->sigcontext_register_address = 0;
2728
2729 /* We know that GNU/Linux won't have to resort to the
2730 native_find_global_pointer hackery. But that's the only one we
2731 know about so far, so if native_find_global_pointer is set to
2732 something non-zero, then use it. Otherwise fall back to using
2733 generic_elf_find_global_pointer. This arrangement should (in
2734 theory) allow us to cross debug GNU/Linux binaries from an AIX
2735 machine. */
2736 if (info.osabi == GDB_OSABI_LINUX)
2737 tdep->find_global_pointer = generic_elf_find_global_pointer;
2738 else if (native_find_global_pointer != 0)
2739 tdep->find_global_pointer = native_find_global_pointer;
2740 else
2741 tdep->find_global_pointer = generic_elf_find_global_pointer;
2742
2743 /* Define the ia64 floating-point format to gdb. */
2744 builtin_type_ia64_ext =
2745 init_type (TYPE_CODE_FLT, 128 / 8,
2746 0, "builtin_type_ia64_ext", NULL);
2747 TYPE_FLOATFORMAT (builtin_type_ia64_ext) = &floatformat_ia64_ext;
2748
2749 set_gdbarch_short_bit (gdbarch, 16);
2750 set_gdbarch_int_bit (gdbarch, 32);
2751 set_gdbarch_long_bit (gdbarch, 64);
2752 set_gdbarch_long_long_bit (gdbarch, 64);
2753 set_gdbarch_float_bit (gdbarch, 32);
2754 set_gdbarch_double_bit (gdbarch, 64);
2755 set_gdbarch_long_double_bit (gdbarch, 128);
2756 set_gdbarch_ptr_bit (gdbarch, 64);
2757
2758 set_gdbarch_num_regs (gdbarch, NUM_IA64_RAW_REGS);
2759 set_gdbarch_num_pseudo_regs (gdbarch, LAST_PSEUDO_REGNUM - FIRST_PSEUDO_REGNUM);
2760 set_gdbarch_sp_regnum (gdbarch, sp_regnum);
2761 set_gdbarch_fp0_regnum (gdbarch, IA64_FR0_REGNUM);
2762
2763 set_gdbarch_register_name (gdbarch, ia64_register_name);
2764 /* FIXME: Following interface should not be needed, however, without it recurse.exp
2765 gets a number of extra failures. */
2766 set_gdbarch_deprecated_register_size (gdbarch, 8);
2767 set_gdbarch_register_type (gdbarch, ia64_register_type);
2768
2769 set_gdbarch_pseudo_register_read (gdbarch, ia64_pseudo_register_read);
2770 set_gdbarch_pseudo_register_write (gdbarch, ia64_pseudo_register_write);
2771 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, ia64_dwarf_reg_to_regnum);
2772 set_gdbarch_register_reggroup_p (gdbarch, ia64_register_reggroup_p);
2773 set_gdbarch_convert_register_p (gdbarch, ia64_convert_register_p);
2774 set_gdbarch_register_to_value (gdbarch, ia64_register_to_value);
2775 set_gdbarch_value_to_register (gdbarch, ia64_value_to_register);
2776
2777 set_gdbarch_skip_prologue (gdbarch, ia64_skip_prologue);
2778
2779 set_gdbarch_use_struct_convention (gdbarch, ia64_use_struct_convention);
2780 set_gdbarch_extract_return_value (gdbarch, ia64_extract_return_value);
2781
2782 set_gdbarch_store_return_value (gdbarch, ia64_store_return_value);
2783 set_gdbarch_extract_struct_value_address (gdbarch, ia64_extract_struct_value_address);
2784
2785 set_gdbarch_memory_insert_breakpoint (gdbarch, ia64_memory_insert_breakpoint);
2786 set_gdbarch_memory_remove_breakpoint (gdbarch, ia64_memory_remove_breakpoint);
2787 set_gdbarch_breakpoint_from_pc (gdbarch, ia64_breakpoint_from_pc);
2788 set_gdbarch_read_pc (gdbarch, ia64_read_pc);
2789 set_gdbarch_write_pc (gdbarch, ia64_write_pc);
2790
2791 /* Settings for calling functions in the inferior. */
2792 set_gdbarch_push_dummy_call (gdbarch, ia64_push_dummy_call);
2793 set_gdbarch_frame_align (gdbarch, ia64_frame_align);
2794 set_gdbarch_unwind_dummy_id (gdbarch, ia64_unwind_dummy_id);
2795
2796 set_gdbarch_unwind_pc (gdbarch, ia64_unwind_pc);
2797 frame_unwind_append_sniffer (gdbarch, ia64_sigtramp_frame_sniffer);
2798 frame_unwind_append_sniffer (gdbarch, ia64_frame_sniffer);
2799 frame_base_set_default (gdbarch, &ia64_frame_base);
2800
2801 /* Settings that should be unnecessary. */
2802 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2803
2804 set_gdbarch_decr_pc_after_break (gdbarch, 0);
2805 set_gdbarch_function_start_offset (gdbarch, 0);
2806 set_gdbarch_frame_args_skip (gdbarch, 0);
2807
2808 set_gdbarch_remote_translate_xfer_address (
2809 gdbarch, ia64_remote_translate_xfer_address);
2810
2811 set_gdbarch_print_insn (gdbarch, ia64_print_insn);
2812 set_gdbarch_convert_from_func_ptr_addr (gdbarch, ia64_convert_from_func_ptr_addr);
2813
2814 return gdbarch;
2815 }
2816
2817 extern initialize_file_ftype _initialize_ia64_tdep; /* -Wmissing-prototypes */
2818
2819 void
2820 _initialize_ia64_tdep (void)
2821 {
2822 register_gdbarch_init (bfd_arch_ia64, ia64_gdbarch_init);
2823 }
GDB Binutils - Deliverables
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