1 /* Target-dependent code for the IA-64 for GDB, the GNU debugger.
3 Copyright 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
24 #include "symfile.h" /* for entry_point_address */
26 #include "arch-utils.h"
27 #include "floatformat.h"
29 #include "reggroups.h"
31 #include "frame-base.h"
32 #include "frame-unwind.h"
35 #include "gdb_assert.h"
37 #include "elf/common.h" /* for DT_PLTGOT value */
41 /* Hook for determining the global pointer when calling functions in
42 the inferior under AIX. The initialization code in ia64-aix-nat.c
43 sets this hook to the address of a function which will find the
44 global pointer for a given address.
46 The generic code which uses the dynamic section in the inferior for
47 finding the global pointer is not of much use on AIX since the
48 values obtained from the inferior have not been relocated. */
50 CORE_ADDR (*native_find_global_pointer
) (CORE_ADDR
) = 0;
52 /* An enumeration of the different IA-64 instruction types. */
54 typedef enum instruction_type
56 A
, /* Integer ALU ; I-unit or M-unit */
57 I
, /* Non-ALU integer; I-unit */
58 M
, /* Memory ; M-unit */
59 F
, /* Floating-point ; F-unit */
60 B
, /* Branch ; B-unit */
61 L
, /* Extended (L+X) ; I-unit */
62 X
, /* Extended (L+X) ; I-unit */
63 undefined
/* undefined or reserved */
66 /* We represent IA-64 PC addresses as the value of the instruction
67 pointer or'd with some bit combination in the low nibble which
68 represents the slot number in the bundle addressed by the
69 instruction pointer. The problem is that the Linux kernel
70 multiplies its slot numbers (for exceptions) by one while the
71 disassembler multiplies its slot numbers by 6. In addition, I've
72 heard it said that the simulator uses 1 as the multiplier.
74 I've fixed the disassembler so that the bytes_per_line field will
75 be the slot multiplier. If bytes_per_line comes in as zero, it
76 is set to six (which is how it was set up initially). -- objdump
77 displays pretty disassembly dumps with this value. For our purposes,
78 we'll set bytes_per_line to SLOT_MULTIPLIER. This is okay since we
79 never want to also display the raw bytes the way objdump does. */
81 #define SLOT_MULTIPLIER 1
83 /* Length in bytes of an instruction bundle */
87 /* FIXME: These extern declarations should go in ia64-tdep.h. */
88 extern CORE_ADDR
ia64_linux_sigcontext_register_address (CORE_ADDR
, int);
89 extern CORE_ADDR
ia64_aix_sigcontext_register_address (CORE_ADDR
, int);
91 static gdbarch_init_ftype ia64_gdbarch_init
;
93 static gdbarch_register_name_ftype ia64_register_name
;
94 static gdbarch_register_type_ftype ia64_register_type
;
95 static gdbarch_breakpoint_from_pc_ftype ia64_breakpoint_from_pc
;
96 static gdbarch_skip_prologue_ftype ia64_skip_prologue
;
97 static gdbarch_extract_return_value_ftype ia64_extract_return_value
;
98 static gdbarch_extract_struct_value_address_ftype ia64_extract_struct_value_address
;
99 static gdbarch_use_struct_convention_ftype ia64_use_struct_convention
;
100 static struct type
*is_float_or_hfa_type (struct type
*t
);
102 static struct type
*builtin_type_ia64_ext
;
104 #define NUM_IA64_RAW_REGS 462
106 static int sp_regnum
= IA64_GR12_REGNUM
;
107 static int fp_regnum
= IA64_VFP_REGNUM
;
108 static int lr_regnum
= IA64_VRAP_REGNUM
;
110 /* NOTE: we treat the register stack registers r32-r127 as pseudo-registers because
111 they are in memory and must be calculated via the bsp register. */
112 enum pseudo_regs
{ FIRST_PSEUDO_REGNUM
= NUM_IA64_RAW_REGS
, VBOF_REGNUM
= IA64_NAT127_REGNUM
+ 1, V32_REGNUM
,
113 V127_REGNUM
= V32_REGNUM
+ 95,
114 VP0_REGNUM
, VP16_REGNUM
= VP0_REGNUM
+ 16, VP63_REGNUM
= VP0_REGNUM
+ 63, LAST_PSEUDO_REGNUM
};
116 /* Array of register names; There should be ia64_num_regs strings in
119 static char *ia64_register_names
[] =
120 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
121 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
122 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
123 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
124 "", "", "", "", "", "", "", "",
125 "", "", "", "", "", "", "", "",
126 "", "", "", "", "", "", "", "",
127 "", "", "", "", "", "", "", "",
128 "", "", "", "", "", "", "", "",
129 "", "", "", "", "", "", "", "",
130 "", "", "", "", "", "", "", "",
131 "", "", "", "", "", "", "", "",
132 "", "", "", "", "", "", "", "",
133 "", "", "", "", "", "", "", "",
134 "", "", "", "", "", "", "", "",
135 "", "", "", "", "", "", "", "",
137 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
138 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
139 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
140 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
141 "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
142 "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47",
143 "f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55",
144 "f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63",
145 "f64", "f65", "f66", "f67", "f68", "f69", "f70", "f71",
146 "f72", "f73", "f74", "f75", "f76", "f77", "f78", "f79",
147 "f80", "f81", "f82", "f83", "f84", "f85", "f86", "f87",
148 "f88", "f89", "f90", "f91", "f92", "f93", "f94", "f95",
149 "f96", "f97", "f98", "f99", "f100", "f101", "f102", "f103",
150 "f104", "f105", "f106", "f107", "f108", "f109", "f110", "f111",
151 "f112", "f113", "f114", "f115", "f116", "f117", "f118", "f119",
152 "f120", "f121", "f122", "f123", "f124", "f125", "f126", "f127",
154 "", "", "", "", "", "", "", "",
155 "", "", "", "", "", "", "", "",
156 "", "", "", "", "", "", "", "",
157 "", "", "", "", "", "", "", "",
158 "", "", "", "", "", "", "", "",
159 "", "", "", "", "", "", "", "",
160 "", "", "", "", "", "", "", "",
161 "", "", "", "", "", "", "", "",
163 "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7",
167 "pr", "ip", "psr", "cfm",
169 "kr0", "kr1", "kr2", "kr3", "kr4", "kr5", "kr6", "kr7",
170 "", "", "", "", "", "", "", "",
171 "rsc", "bsp", "bspstore", "rnat",
173 "eflag", "csd", "ssd", "cflg", "fsr", "fir", "fdr", "",
174 "ccv", "", "", "", "unat", "", "", "",
175 "fpsr", "", "", "", "itc",
176 "", "", "", "", "", "", "", "", "", "",
177 "", "", "", "", "", "", "", "", "",
179 "", "", "", "", "", "", "", "", "", "",
180 "", "", "", "", "", "", "", "", "", "",
181 "", "", "", "", "", "", "", "", "", "",
182 "", "", "", "", "", "", "", "", "", "",
183 "", "", "", "", "", "", "", "", "", "",
184 "", "", "", "", "", "", "", "", "", "",
186 "nat0", "nat1", "nat2", "nat3", "nat4", "nat5", "nat6", "nat7",
187 "nat8", "nat9", "nat10", "nat11", "nat12", "nat13", "nat14", "nat15",
188 "nat16", "nat17", "nat18", "nat19", "nat20", "nat21", "nat22", "nat23",
189 "nat24", "nat25", "nat26", "nat27", "nat28", "nat29", "nat30", "nat31",
190 "nat32", "nat33", "nat34", "nat35", "nat36", "nat37", "nat38", "nat39",
191 "nat40", "nat41", "nat42", "nat43", "nat44", "nat45", "nat46", "nat47",
192 "nat48", "nat49", "nat50", "nat51", "nat52", "nat53", "nat54", "nat55",
193 "nat56", "nat57", "nat58", "nat59", "nat60", "nat61", "nat62", "nat63",
194 "nat64", "nat65", "nat66", "nat67", "nat68", "nat69", "nat70", "nat71",
195 "nat72", "nat73", "nat74", "nat75", "nat76", "nat77", "nat78", "nat79",
196 "nat80", "nat81", "nat82", "nat83", "nat84", "nat85", "nat86", "nat87",
197 "nat88", "nat89", "nat90", "nat91", "nat92", "nat93", "nat94", "nat95",
198 "nat96", "nat97", "nat98", "nat99", "nat100","nat101","nat102","nat103",
199 "nat104","nat105","nat106","nat107","nat108","nat109","nat110","nat111",
200 "nat112","nat113","nat114","nat115","nat116","nat117","nat118","nat119",
201 "nat120","nat121","nat122","nat123","nat124","nat125","nat126","nat127",
205 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
206 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
207 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
208 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
209 "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71",
210 "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
211 "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87",
212 "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95",
213 "r96", "r97", "r98", "r99", "r100", "r101", "r102", "r103",
214 "r104", "r105", "r106", "r107", "r108", "r109", "r110", "r111",
215 "r112", "r113", "r114", "r115", "r116", "r117", "r118", "r119",
216 "r120", "r121", "r122", "r123", "r124", "r125", "r126", "r127",
218 "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7",
219 "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15",
220 "p16", "p17", "p18", "p19", "p20", "p21", "p22", "p23",
221 "p24", "p25", "p26", "p27", "p28", "p29", "p30", "p31",
222 "p32", "p33", "p34", "p35", "p36", "p37", "p38", "p39",
223 "p40", "p41", "p42", "p43", "p44", "p45", "p46", "p47",
224 "p48", "p49", "p50", "p51", "p52", "p53", "p54", "p55",
225 "p56", "p57", "p58", "p59", "p60", "p61", "p62", "p63",
228 struct ia64_frame_cache
230 CORE_ADDR base
; /* frame pointer base for frame */
231 CORE_ADDR pc
; /* function start pc for frame */
232 CORE_ADDR saved_sp
; /* stack pointer for frame */
233 CORE_ADDR bsp
; /* points at r32 for the current frame */
234 CORE_ADDR cfm
; /* cfm value for current frame */
236 int sof
; /* Size of frame (decoded from cfm value) */
237 int sol
; /* Size of locals (decoded from cfm value) */
238 int sor
; /* Number of rotating registers. (decoded from cfm value) */
239 CORE_ADDR after_prologue
;
240 /* Address of first instruction after the last
241 prologue instruction; Note that there may
242 be instructions from the function's body
243 intermingled with the prologue. */
244 int mem_stack_frame_size
;
245 /* Size of the memory stack frame (may be zero),
246 or -1 if it has not been determined yet. */
247 int fp_reg
; /* Register number (if any) used a frame pointer
248 for this frame. 0 if no register is being used
249 as the frame pointer. */
251 /* Saved registers. */
252 CORE_ADDR saved_regs
[NUM_IA64_RAW_REGS
];
258 int os_ident
; /* From the ELF header, one of the ELFOSABI_
259 constants: ELFOSABI_LINUX, ELFOSABI_AIX,
261 CORE_ADDR (*sigcontext_register_address
) (CORE_ADDR
, int);
262 /* OS specific function which, given a frame address
263 and register number, returns the offset to the
264 given register from the start of the frame. */
265 CORE_ADDR (*find_global_pointer
) (CORE_ADDR
);
268 #define SIGCONTEXT_REGISTER_ADDRESS \
269 (gdbarch_tdep (current_gdbarch)->sigcontext_register_address)
270 #define FIND_GLOBAL_POINTER \
271 (gdbarch_tdep (current_gdbarch)->find_global_pointer)
274 ia64_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
275 struct reggroup
*group
)
280 if (group
== all_reggroup
)
282 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
283 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
284 raw_p
= regnum
< NUM_IA64_RAW_REGS
;
285 if (group
== float_reggroup
)
287 if (group
== vector_reggroup
)
289 if (group
== general_reggroup
)
290 return (!vector_p
&& !float_p
);
291 if (group
== save_reggroup
|| group
== restore_reggroup
)
297 ia64_register_name (int reg
)
299 return ia64_register_names
[reg
];
303 ia64_register_type (struct gdbarch
*arch
, int reg
)
305 if (reg
>= IA64_FR0_REGNUM
&& reg
<= IA64_FR127_REGNUM
)
306 return builtin_type_ia64_ext
;
308 return builtin_type_long
;
312 ia64_dwarf_reg_to_regnum (int reg
)
314 if (reg
>= IA64_GR32_REGNUM
&& reg
<= IA64_GR127_REGNUM
)
315 return V32_REGNUM
+ (reg
- IA64_GR32_REGNUM
);
319 const struct floatformat floatformat_ia64_ext
=
321 floatformat_little
, 82, 0, 1, 17, 65535, 0x1ffff, 18, 64,
322 floatformat_intbit_yes
326 /* Read the given register from a sigcontext structure in the
330 read_sigcontext_register (struct frame_info
*frame
, int regnum
)
335 internal_error (__FILE__
, __LINE__
,
336 "read_sigcontext_register: NULL frame");
337 if (!(get_frame_type (frame
) == SIGTRAMP_FRAME
))
338 internal_error (__FILE__
, __LINE__
,
339 "read_sigcontext_register: frame not a signal trampoline");
340 if (SIGCONTEXT_REGISTER_ADDRESS
== 0)
341 internal_error (__FILE__
, __LINE__
,
342 "read_sigcontext_register: SIGCONTEXT_REGISTER_ADDRESS is 0");
344 regaddr
= SIGCONTEXT_REGISTER_ADDRESS (get_frame_base (frame
), regnum
);
346 return read_memory_integer (regaddr
, REGISTER_RAW_SIZE (regnum
));
348 internal_error (__FILE__
, __LINE__
,
349 "read_sigcontext_register: Register %d not in struct sigcontext", regnum
);
352 /* Extract ``len'' bits from an instruction bundle starting at
356 extract_bit_field (char *bundle
, int from
, int len
)
358 long long result
= 0LL;
360 int from_byte
= from
/ 8;
361 int to_byte
= to
/ 8;
362 unsigned char *b
= (unsigned char *) bundle
;
368 if (from_byte
== to_byte
)
369 c
= ((unsigned char) (c
<< (8 - to
% 8))) >> (8 - to
% 8);
370 result
= c
>> (from
% 8);
371 lshift
= 8 - (from
% 8);
373 for (i
= from_byte
+1; i
< to_byte
; i
++)
375 result
|= ((long long) b
[i
]) << lshift
;
379 if (from_byte
< to_byte
&& (to
% 8 != 0))
382 c
= ((unsigned char) (c
<< (8 - to
% 8))) >> (8 - to
% 8);
383 result
|= ((long long) c
) << lshift
;
389 /* Replace the specified bits in an instruction bundle */
392 replace_bit_field (char *bundle
, long long val
, int from
, int len
)
395 int from_byte
= from
/ 8;
396 int to_byte
= to
/ 8;
397 unsigned char *b
= (unsigned char *) bundle
;
400 if (from_byte
== to_byte
)
402 unsigned char left
, right
;
404 left
= (c
>> (to
% 8)) << (to
% 8);
405 right
= ((unsigned char) (c
<< (8 - from
% 8))) >> (8 - from
% 8);
406 c
= (unsigned char) (val
& 0xff);
407 c
= (unsigned char) (c
<< (from
% 8 + 8 - to
% 8)) >> (8 - to
% 8);
415 c
= ((unsigned char) (c
<< (8 - from
% 8))) >> (8 - from
% 8);
416 c
= c
| (val
<< (from
% 8));
418 val
>>= 8 - from
% 8;
420 for (i
= from_byte
+1; i
< to_byte
; i
++)
429 unsigned char cv
= (unsigned char) val
;
431 c
= c
>> (to
% 8) << (to
% 8);
432 c
|= ((unsigned char) (cv
<< (8 - to
% 8))) >> (8 - to
% 8);
438 /* Return the contents of slot N (for N = 0, 1, or 2) in
439 and instruction bundle */
442 slotN_contents (char *bundle
, int slotnum
)
444 return extract_bit_field (bundle
, 5+41*slotnum
, 41);
447 /* Store an instruction in an instruction bundle */
450 replace_slotN_contents (char *bundle
, long long instr
, int slotnum
)
452 replace_bit_field (bundle
, instr
, 5+41*slotnum
, 41);
455 static enum instruction_type template_encoding_table
[32][3] =
457 { M
, I
, I
}, /* 00 */
458 { M
, I
, I
}, /* 01 */
459 { M
, I
, I
}, /* 02 */
460 { M
, I
, I
}, /* 03 */
461 { M
, L
, X
}, /* 04 */
462 { M
, L
, X
}, /* 05 */
463 { undefined
, undefined
, undefined
}, /* 06 */
464 { undefined
, undefined
, undefined
}, /* 07 */
465 { M
, M
, I
}, /* 08 */
466 { M
, M
, I
}, /* 09 */
467 { M
, M
, I
}, /* 0A */
468 { M
, M
, I
}, /* 0B */
469 { M
, F
, I
}, /* 0C */
470 { M
, F
, I
}, /* 0D */
471 { M
, M
, F
}, /* 0E */
472 { M
, M
, F
}, /* 0F */
473 { M
, I
, B
}, /* 10 */
474 { M
, I
, B
}, /* 11 */
475 { M
, B
, B
}, /* 12 */
476 { M
, B
, B
}, /* 13 */
477 { undefined
, undefined
, undefined
}, /* 14 */
478 { undefined
, undefined
, undefined
}, /* 15 */
479 { B
, B
, B
}, /* 16 */
480 { B
, B
, B
}, /* 17 */
481 { M
, M
, B
}, /* 18 */
482 { M
, M
, B
}, /* 19 */
483 { undefined
, undefined
, undefined
}, /* 1A */
484 { undefined
, undefined
, undefined
}, /* 1B */
485 { M
, F
, B
}, /* 1C */
486 { M
, F
, B
}, /* 1D */
487 { undefined
, undefined
, undefined
}, /* 1E */
488 { undefined
, undefined
, undefined
}, /* 1F */
491 /* Fetch and (partially) decode an instruction at ADDR and return the
492 address of the next instruction to fetch. */
495 fetch_instruction (CORE_ADDR addr
, instruction_type
*it
, long long *instr
)
497 char bundle
[BUNDLE_LEN
];
498 int slotnum
= (int) (addr
& 0x0f) / SLOT_MULTIPLIER
;
502 /* Warn about slot numbers greater than 2. We used to generate
503 an error here on the assumption that the user entered an invalid
504 address. But, sometimes GDB itself requests an invalid address.
505 This can (easily) happen when execution stops in a function for
506 which there are no symbols. The prologue scanner will attempt to
507 find the beginning of the function - if the nearest symbol
508 happens to not be aligned on a bundle boundary (16 bytes), the
509 resulting starting address will cause GDB to think that the slot
512 So we warn about it and set the slot number to zero. It is
513 not necessarily a fatal condition, particularly if debugging
514 at the assembly language level. */
517 warning ("Can't fetch instructions for slot numbers greater than 2.\n"
518 "Using slot 0 instead");
524 val
= target_read_memory (addr
, bundle
, BUNDLE_LEN
);
529 *instr
= slotN_contents (bundle
, slotnum
);
530 template = extract_bit_field (bundle
, 0, 5);
531 *it
= template_encoding_table
[(int)template][slotnum
];
533 if (slotnum
== 2 || (slotnum
== 1 && *it
== L
))
536 addr
+= (slotnum
+ 1) * SLOT_MULTIPLIER
;
541 /* There are 5 different break instructions (break.i, break.b,
542 break.m, break.f, and break.x), but they all have the same
543 encoding. (The five bit template in the low five bits of the
544 instruction bundle distinguishes one from another.)
546 The runtime architecture manual specifies that break instructions
547 used for debugging purposes must have the upper two bits of the 21
548 bit immediate set to a 0 and a 1 respectively. A breakpoint
549 instruction encodes the most significant bit of its 21 bit
550 immediate at bit 36 of the 41 bit instruction. The penultimate msb
551 is at bit 25 which leads to the pattern below.
553 Originally, I had this set up to do, e.g, a "break.i 0x80000" But
554 it turns out that 0x80000 was used as the syscall break in the early
555 simulators. So I changed the pattern slightly to do "break.i 0x080001"
556 instead. But that didn't work either (I later found out that this
557 pattern was used by the simulator that I was using.) So I ended up
558 using the pattern seen below. */
561 #define IA64_BREAKPOINT 0x00002000040LL
563 #define IA64_BREAKPOINT 0x00003333300LL
566 ia64_memory_insert_breakpoint (CORE_ADDR addr
, char *contents_cache
)
568 char bundle
[BUNDLE_LEN
];
569 int slotnum
= (int) (addr
& 0x0f) / SLOT_MULTIPLIER
;
575 error("Can't insert breakpoint for slot numbers greater than 2.");
579 val
= target_read_memory (addr
, bundle
, BUNDLE_LEN
);
581 /* Check for L type instruction in 2nd slot, if present then
582 bump up the slot number to the 3rd slot */
583 template = extract_bit_field (bundle
, 0, 5);
584 if (slotnum
== 1 && template_encoding_table
[template][1] == L
)
589 instr
= slotN_contents (bundle
, slotnum
);
590 memcpy(contents_cache
, &instr
, sizeof(instr
));
591 replace_slotN_contents (bundle
, IA64_BREAKPOINT
, slotnum
);
593 target_write_memory (addr
, bundle
, BUNDLE_LEN
);
599 ia64_memory_remove_breakpoint (CORE_ADDR addr
, char *contents_cache
)
601 char bundle
[BUNDLE_LEN
];
602 int slotnum
= (addr
& 0x0f) / SLOT_MULTIPLIER
;
609 val
= target_read_memory (addr
, bundle
, BUNDLE_LEN
);
611 /* Check for L type instruction in 2nd slot, if present then
612 bump up the slot number to the 3rd slot */
613 template = extract_bit_field (bundle
, 0, 5);
614 if (slotnum
== 1 && template_encoding_table
[template][1] == L
)
619 memcpy (&instr
, contents_cache
, sizeof instr
);
620 replace_slotN_contents (bundle
, instr
, slotnum
);
622 target_write_memory (addr
, bundle
, BUNDLE_LEN
);
627 /* We don't really want to use this, but remote.c needs to call it in order
628 to figure out if Z-packets are supported or not. Oh, well. */
629 const unsigned char *
630 ia64_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
632 static unsigned char breakpoint
[] =
633 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
634 *lenptr
= sizeof (breakpoint
);
644 /* We won't necessarily have a frame pointer and even if we do, it
645 winds up being extraordinarly messy when attempting to find the
646 frame chain. So for the purposes of creating frames (which is
647 all deprecated_read_fp() is used for), simply use the stack
648 pointer value instead. */
649 gdb_assert (SP_REGNUM
>= 0);
650 return read_register (SP_REGNUM
);
654 ia64_read_pc (ptid_t ptid
)
656 CORE_ADDR psr_value
= read_register_pid (IA64_PSR_REGNUM
, ptid
);
657 CORE_ADDR pc_value
= read_register_pid (IA64_IP_REGNUM
, ptid
);
658 int slot_num
= (psr_value
>> 41) & 3;
660 return pc_value
| (slot_num
* SLOT_MULTIPLIER
);
664 ia64_write_pc (CORE_ADDR new_pc
, ptid_t ptid
)
666 int slot_num
= (int) (new_pc
& 0xf) / SLOT_MULTIPLIER
;
667 CORE_ADDR psr_value
= read_register_pid (IA64_PSR_REGNUM
, ptid
);
668 psr_value
&= ~(3LL << 41);
669 psr_value
|= (CORE_ADDR
)(slot_num
& 0x3) << 41;
673 write_register_pid (IA64_PSR_REGNUM
, psr_value
, ptid
);
674 write_register_pid (IA64_IP_REGNUM
, new_pc
, ptid
);
677 #define IS_NaT_COLLECTION_ADDR(addr) ((((addr) >> 3) & 0x3f) == 0x3f)
679 /* Returns the address of the slot that's NSLOTS slots away from
680 the address ADDR. NSLOTS may be positive or negative. */
682 rse_address_add(CORE_ADDR addr
, int nslots
)
685 int mandatory_nat_slots
= nslots
/ 63;
686 int direction
= nslots
< 0 ? -1 : 1;
688 new_addr
= addr
+ 8 * (nslots
+ mandatory_nat_slots
);
690 if ((new_addr
>> 9) != ((addr
+ 8 * 64 * mandatory_nat_slots
) >> 9))
691 new_addr
+= 8 * direction
;
693 if (IS_NaT_COLLECTION_ADDR(new_addr
))
694 new_addr
+= 8 * direction
;
700 ia64_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
701 int regnum
, void *buf
)
703 if (regnum
>= V32_REGNUM
&& regnum
<= V127_REGNUM
)
708 regcache_cooked_read_unsigned (regcache
, IA64_BSP_REGNUM
, &bsp
);
709 regcache_cooked_read_unsigned (regcache
, IA64_CFM_REGNUM
, &cfm
);
711 /* The bsp points at the end of the register frame so we
712 subtract the size of frame from it to get start of register frame. */
713 bsp
= rse_address_add (bsp
, -(cfm
& 0x7f));
715 if ((cfm
& 0x7f) > regnum
- V32_REGNUM
)
717 ULONGEST reg_addr
= rse_address_add (bsp
, (regnum
- V32_REGNUM
));
718 reg
= read_memory_integer ((CORE_ADDR
)reg_addr
, 8);
719 store_unsigned_integer (buf
, REGISTER_RAW_SIZE (regnum
), reg
);
722 store_unsigned_integer (buf
, REGISTER_RAW_SIZE (regnum
), 0);
724 else if (IA64_NAT0_REGNUM
<= regnum
&& regnum
<= IA64_NAT31_REGNUM
)
728 regcache_cooked_read_unsigned (regcache
, IA64_UNAT_REGNUM
, &unat
);
729 unatN_val
= (unat
& (1LL << (regnum
- IA64_NAT0_REGNUM
))) != 0;
730 store_unsigned_integer (buf
, REGISTER_RAW_SIZE (regnum
), unatN_val
);
732 else if (IA64_NAT32_REGNUM
<= regnum
&& regnum
<= IA64_NAT127_REGNUM
)
734 ULONGEST natN_val
= 0;
737 CORE_ADDR gr_addr
= 0;
738 regcache_cooked_read_unsigned (regcache
, IA64_BSP_REGNUM
, &bsp
);
739 regcache_cooked_read_unsigned (regcache
, IA64_CFM_REGNUM
, &cfm
);
741 /* The bsp points at the end of the register frame so we
742 subtract the size of frame from it to get start of register frame. */
743 bsp
= rse_address_add (bsp
, -(cfm
& 0x7f));
745 if ((cfm
& 0x7f) > regnum
- V32_REGNUM
)
746 gr_addr
= rse_address_add (bsp
, (regnum
- V32_REGNUM
));
750 /* Compute address of nat collection bits. */
751 CORE_ADDR nat_addr
= gr_addr
| 0x1f8;
752 CORE_ADDR nat_collection
;
754 /* If our nat collection address is bigger than bsp, we have to get
755 the nat collection from rnat. Otherwise, we fetch the nat
756 collection from the computed address. */
758 regcache_cooked_read_unsigned (regcache
, IA64_RNAT_REGNUM
, &nat_collection
);
760 nat_collection
= read_memory_integer (nat_addr
, 8);
761 nat_bit
= (gr_addr
>> 3) & 0x3f;
762 natN_val
= (nat_collection
>> nat_bit
) & 1;
765 store_unsigned_integer (buf
, REGISTER_RAW_SIZE (regnum
), natN_val
);
767 else if (regnum
== VBOF_REGNUM
)
769 /* A virtual register frame start is provided for user convenience.
770 It can be calculated as the bsp - sof (sizeof frame). */
774 regcache_cooked_read_unsigned (regcache
, IA64_BSP_REGNUM
, &bsp
);
775 regcache_cooked_read_unsigned (regcache
, IA64_CFM_REGNUM
, &cfm
);
777 /* The bsp points at the end of the register frame so we
778 subtract the size of frame from it to get beginning of frame. */
779 vbsp
= rse_address_add (bsp
, -(cfm
& 0x7f));
780 store_unsigned_integer (buf
, REGISTER_RAW_SIZE (regnum
), vbsp
);
782 else if (VP0_REGNUM
<= regnum
&& regnum
<= VP63_REGNUM
)
788 regcache_cooked_read_unsigned (regcache
, IA64_PR_REGNUM
, &pr
);
789 regcache_cooked_read_unsigned (regcache
, IA64_CFM_REGNUM
, &cfm
);
791 if (VP16_REGNUM
<= regnum
&& regnum
<= VP63_REGNUM
)
793 /* Fetch predicate register rename base from current frame
794 marker for this frame. */
795 int rrb_pr
= (cfm
>> 32) & 0x3f;
797 /* Adjust the register number to account for register rotation. */
799 + ((regnum
- VP16_REGNUM
) + rrb_pr
) % 48;
801 prN_val
= (pr
& (1LL << (regnum
- VP0_REGNUM
))) != 0;
802 store_unsigned_integer (buf
, REGISTER_RAW_SIZE (regnum
), prN_val
);
805 memset (buf
, 0, REGISTER_RAW_SIZE (regnum
));
809 ia64_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
810 int regnum
, const void *buf
)
812 if (regnum
>= V32_REGNUM
&& regnum
<= V127_REGNUM
)
817 regcache_cooked_read_unsigned (regcache
, IA64_BSP_REGNUM
, &bsp
);
818 regcache_cooked_read_unsigned (regcache
, IA64_CFM_REGNUM
, &cfm
);
820 bsp
= rse_address_add (bsp
, -(cfm
& 0x7f));
822 if ((cfm
& 0x7f) > regnum
- V32_REGNUM
)
824 ULONGEST reg_addr
= rse_address_add (bsp
, (regnum
- V32_REGNUM
));
825 write_memory (reg_addr
, (void *)buf
, 8);
828 else if (IA64_NAT0_REGNUM
<= regnum
&& regnum
<= IA64_NAT31_REGNUM
)
830 ULONGEST unatN_val
, unat
, unatN_mask
;
831 regcache_cooked_read_unsigned (regcache
, IA64_UNAT_REGNUM
, &unat
);
832 unatN_val
= extract_unsigned_integer (buf
, REGISTER_RAW_SIZE (regnum
));
833 unatN_mask
= (1LL << (regnum
- IA64_NAT0_REGNUM
));
836 else if (unatN_val
== 1)
838 regcache_cooked_write_unsigned (regcache
, IA64_UNAT_REGNUM
, unat
);
840 else if (IA64_NAT32_REGNUM
<= regnum
&& regnum
<= IA64_NAT127_REGNUM
)
845 CORE_ADDR gr_addr
= 0;
846 regcache_cooked_read_unsigned (regcache
, IA64_BSP_REGNUM
, &bsp
);
847 regcache_cooked_read_unsigned (regcache
, IA64_CFM_REGNUM
, &cfm
);
849 /* The bsp points at the end of the register frame so we
850 subtract the size of frame from it to get start of register frame. */
851 bsp
= rse_address_add (bsp
, -(cfm
& 0x7f));
853 if ((cfm
& 0x7f) > regnum
- V32_REGNUM
)
854 gr_addr
= rse_address_add (bsp
, (regnum
- V32_REGNUM
));
856 natN_val
= extract_unsigned_integer (buf
, REGISTER_RAW_SIZE (regnum
));
858 if (gr_addr
!= 0 && (natN_val
== 0 || natN_val
== 1))
860 /* Compute address of nat collection bits. */
861 CORE_ADDR nat_addr
= gr_addr
| 0x1f8;
862 CORE_ADDR nat_collection
;
863 int natN_bit
= (gr_addr
>> 3) & 0x3f;
864 ULONGEST natN_mask
= (1LL << natN_bit
);
865 /* If our nat collection address is bigger than bsp, we have to get
866 the nat collection from rnat. Otherwise, we fetch the nat
867 collection from the computed address. */
870 regcache_cooked_read_unsigned (regcache
, IA64_RNAT_REGNUM
, &nat_collection
);
872 nat_collection
|= natN_mask
;
874 nat_collection
&= ~natN_mask
;
875 regcache_cooked_write_unsigned (regcache
, IA64_RNAT_REGNUM
, nat_collection
);
880 nat_collection
= read_memory_integer (nat_addr
, 8);
882 nat_collection
|= natN_mask
;
884 nat_collection
&= ~natN_mask
;
885 store_unsigned_integer (nat_buf
, REGISTER_RAW_SIZE (regnum
), nat_collection
);
886 write_memory (nat_addr
, nat_buf
, 8);
890 else if (VP0_REGNUM
<= regnum
&& regnum
<= VP63_REGNUM
)
897 regcache_cooked_read_unsigned (regcache
, IA64_PR_REGNUM
, &pr
);
898 regcache_cooked_read_unsigned (regcache
, IA64_CFM_REGNUM
, &cfm
);
900 if (VP16_REGNUM
<= regnum
&& regnum
<= VP63_REGNUM
)
902 /* Fetch predicate register rename base from current frame
903 marker for this frame. */
904 int rrb_pr
= (cfm
>> 32) & 0x3f;
906 /* Adjust the register number to account for register rotation. */
908 + ((regnum
- VP16_REGNUM
) + rrb_pr
) % 48;
910 prN_val
= extract_unsigned_integer (buf
, REGISTER_RAW_SIZE (regnum
));
911 prN_mask
= (1LL << (regnum
- VP0_REGNUM
));
914 else if (prN_val
== 1)
916 regcache_cooked_write_unsigned (regcache
, IA64_PR_REGNUM
, pr
);
920 /* The ia64 needs to convert between various ieee floating-point formats
921 and the special ia64 floating point register format. */
924 ia64_convert_register_p (int regno
, struct type
*type
)
926 return (regno
>= IA64_FR0_REGNUM
&& regno
<= IA64_FR127_REGNUM
);
930 ia64_register_to_value (struct frame_info
*frame
, int regnum
,
931 struct type
*valtype
, void *out
)
933 char in
[MAX_REGISTER_SIZE
];
934 frame_register_read (frame
, regnum
, in
);
935 convert_typed_floating (in
, builtin_type_ia64_ext
, out
, valtype
);
939 ia64_value_to_register (struct frame_info
*frame
, int regnum
,
940 struct type
*valtype
, const void *in
)
942 char out
[MAX_REGISTER_SIZE
];
943 convert_typed_floating (in
, valtype
, out
, builtin_type_ia64_ext
);
944 put_frame_register (frame
, regnum
, out
);
948 /* Limit the number of skipped non-prologue instructions since examining
949 of the prologue is expensive. */
950 static int max_skip_non_prologue_insns
= 40;
952 /* Given PC representing the starting address of a function, and
953 LIM_PC which is the (sloppy) limit to which to scan when looking
954 for a prologue, attempt to further refine this limit by using
955 the line data in the symbol table. If successful, a better guess
956 on where the prologue ends is returned, otherwise the previous
957 value of lim_pc is returned. TRUST_LIMIT is a pointer to a flag
958 which will be set to indicate whether the returned limit may be
959 used with no further scanning in the event that the function is
963 refine_prologue_limit (CORE_ADDR pc
, CORE_ADDR lim_pc
, int *trust_limit
)
965 struct symtab_and_line prologue_sal
;
966 CORE_ADDR start_pc
= pc
;
968 /* Start off not trusting the limit. */
971 prologue_sal
= find_pc_line (pc
, 0);
972 if (prologue_sal
.line
!= 0)
975 CORE_ADDR addr
= prologue_sal
.end
;
977 /* Handle the case in which compiler's optimizer/scheduler
978 has moved instructions into the prologue. We scan ahead
979 in the function looking for address ranges whose corresponding
980 line number is less than or equal to the first one that we
981 found for the function. (It can be less than when the
982 scheduler puts a body instruction before the first prologue
984 for (i
= 2 * max_skip_non_prologue_insns
;
985 i
> 0 && (lim_pc
== 0 || addr
< lim_pc
);
988 struct symtab_and_line sal
;
990 sal
= find_pc_line (addr
, 0);
993 if (sal
.line
<= prologue_sal
.line
994 && sal
.symtab
== prologue_sal
.symtab
)
1001 if (lim_pc
== 0 || prologue_sal
.end
< lim_pc
)
1003 lim_pc
= prologue_sal
.end
;
1004 if (start_pc
== get_pc_function_start (lim_pc
))
1011 #define isScratch(_regnum_) ((_regnum_) == 2 || (_regnum_) == 3 \
1012 || (8 <= (_regnum_) && (_regnum_) <= 11) \
1013 || (14 <= (_regnum_) && (_regnum_) <= 31))
1014 #define imm9(_instr_) \
1015 ( ((((_instr_) & 0x01000000000LL) ? -1 : 0) << 8) \
1016 | (((_instr_) & 0x00008000000LL) >> 20) \
1017 | (((_instr_) & 0x00000001fc0LL) >> 6))
1019 /* Allocate and initialize a frame cache. */
1021 static struct ia64_frame_cache
*
1022 ia64_alloc_frame_cache (void)
1024 struct ia64_frame_cache
*cache
;
1027 cache
= FRAME_OBSTACK_ZALLOC (struct ia64_frame_cache
);
1038 cache
->frameless
= 1;
1040 for (i
= 0; i
< NUM_IA64_RAW_REGS
; i
++)
1041 cache
->saved_regs
[i
] = 0;
1047 examine_prologue (CORE_ADDR pc
, CORE_ADDR lim_pc
, struct frame_info
*next_frame
, struct ia64_frame_cache
*cache
)
1050 CORE_ADDR last_prologue_pc
= pc
;
1051 instruction_type it
;
1056 int unat_save_reg
= 0;
1057 int pr_save_reg
= 0;
1058 int mem_stack_frame_size
= 0;
1060 CORE_ADDR spill_addr
= 0;
1063 char reg_contents
[256];
1069 CORE_ADDR bof
, sor
, sol
, sof
, cfm
, rrb_gr
;
1071 memset (instores
, 0, sizeof instores
);
1072 memset (infpstores
, 0, sizeof infpstores
);
1073 memset (reg_contents
, 0, sizeof reg_contents
);
1075 if (cache
->after_prologue
!= 0
1076 && cache
->after_prologue
<= lim_pc
)
1077 return cache
->after_prologue
;
1079 lim_pc
= refine_prologue_limit (pc
, lim_pc
, &trust_limit
);
1080 next_pc
= fetch_instruction (pc
, &it
, &instr
);
1082 /* We want to check if we have a recognizable function start before we
1083 look ahead for a prologue. */
1084 if (pc
< lim_pc
&& next_pc
1085 && it
== M
&& ((instr
& 0x1ee0000003fLL
) == 0x02c00000000LL
))
1087 /* alloc - start of a regular function. */
1088 int sor
= (int) ((instr
& 0x00078000000LL
) >> 27);
1089 int sol
= (int) ((instr
& 0x00007f00000LL
) >> 20);
1090 int sof
= (int) ((instr
& 0x000000fe000LL
) >> 13);
1091 int rN
= (int) ((instr
& 0x00000001fc0LL
) >> 6);
1093 /* Verify that the current cfm matches what we think is the
1094 function start. If we have somehow jumped within a function,
1095 we do not want to interpret the prologue and calculate the
1096 addresses of various registers such as the return address.
1097 We will instead treat the frame as frameless. */
1099 (sof
== (cache
->cfm
& 0x7f) &&
1100 sol
== ((cache
->cfm
>> 7) & 0x7f)))
1104 last_prologue_pc
= next_pc
;
1109 /* Look for a leaf routine. */
1110 if (pc
< lim_pc
&& next_pc
1111 && (it
== I
|| it
== M
)
1112 && ((instr
& 0x1ee00000000LL
) == 0x10800000000LL
))
1114 /* adds rN = imm14, rM (or mov rN, rM when imm14 is 0) */
1115 int imm
= (int) ((((instr
& 0x01000000000LL
) ? -1 : 0) << 13)
1116 | ((instr
& 0x001f8000000LL
) >> 20)
1117 | ((instr
& 0x000000fe000LL
) >> 13));
1118 int rM
= (int) ((instr
& 0x00007f00000LL
) >> 20);
1119 int rN
= (int) ((instr
& 0x00000001fc0LL
) >> 6);
1120 int qp
= (int) (instr
& 0x0000000003fLL
);
1121 if (qp
== 0 && rN
== 2 && imm
== 0 && rM
== 12 && fp_reg
== 0)
1123 /* mov r2, r12 - beginning of leaf routine */
1125 last_prologue_pc
= next_pc
;
1129 /* If we don't recognize a regular function or leaf routine, we are
1135 last_prologue_pc
= lim_pc
;
1139 /* Loop, looking for prologue instructions, keeping track of
1140 where preserved registers were spilled. */
1143 next_pc
= fetch_instruction (pc
, &it
, &instr
);
1147 if (it
== B
&& ((instr
& 0x1e1f800003f) != 0x04000000000))
1149 /* Exit loop upon hitting a non-nop branch instruction. */
1154 else if (((instr
& 0x3fLL
) != 0LL) &&
1155 (frameless
|| ret_reg
!= 0))
1157 /* Exit loop upon hitting a predicated instruction if
1158 we already have the return register or if we are frameless. */
1163 else if (it
== I
&& ((instr
& 0x1eff8000000LL
) == 0x00188000000LL
))
1166 int b2
= (int) ((instr
& 0x0000000e000LL
) >> 13);
1167 int rN
= (int) ((instr
& 0x00000001fc0LL
) >> 6);
1168 int qp
= (int) (instr
& 0x0000000003f);
1170 if (qp
== 0 && b2
== 0 && rN
>= 32 && ret_reg
== 0)
1173 last_prologue_pc
= next_pc
;
1176 else if ((it
== I
|| it
== M
)
1177 && ((instr
& 0x1ee00000000LL
) == 0x10800000000LL
))
1179 /* adds rN = imm14, rM (or mov rN, rM when imm14 is 0) */
1180 int imm
= (int) ((((instr
& 0x01000000000LL
) ? -1 : 0) << 13)
1181 | ((instr
& 0x001f8000000LL
) >> 20)
1182 | ((instr
& 0x000000fe000LL
) >> 13));
1183 int rM
= (int) ((instr
& 0x00007f00000LL
) >> 20);
1184 int rN
= (int) ((instr
& 0x00000001fc0LL
) >> 6);
1185 int qp
= (int) (instr
& 0x0000000003fLL
);
1187 if (qp
== 0 && rN
>= 32 && imm
== 0 && rM
== 12 && fp_reg
== 0)
1191 last_prologue_pc
= next_pc
;
1193 else if (qp
== 0 && rN
== 12 && rM
== 12)
1195 /* adds r12, -mem_stack_frame_size, r12 */
1196 mem_stack_frame_size
-= imm
;
1197 last_prologue_pc
= next_pc
;
1199 else if (qp
== 0 && rN
== 2
1200 && ((rM
== fp_reg
&& fp_reg
!= 0) || rM
== 12))
1202 char buf
[MAX_REGISTER_SIZE
];
1203 CORE_ADDR saved_sp
= 0;
1204 /* adds r2, spilloffset, rFramePointer
1206 adds r2, spilloffset, r12
1208 Get ready for stf.spill or st8.spill instructions.
1209 The address to start spilling at is loaded into r2.
1210 FIXME: Why r2? That's what gcc currently uses; it
1211 could well be different for other compilers. */
1213 /* Hmm... whether or not this will work will depend on
1214 where the pc is. If it's still early in the prologue
1215 this'll be wrong. FIXME */
1218 frame_unwind_register (next_frame
, sp_regnum
, buf
);
1219 saved_sp
= extract_unsigned_integer (buf
, 8);
1221 spill_addr
= saved_sp
1222 + (rM
== 12 ? 0 : mem_stack_frame_size
)
1225 last_prologue_pc
= next_pc
;
1227 else if (qp
== 0 && rM
>= 32 && rM
< 40 && !instores
[rM
] &&
1228 rN
< 256 && imm
== 0)
1230 /* mov rN, rM where rM is an input register */
1231 reg_contents
[rN
] = rM
;
1232 last_prologue_pc
= next_pc
;
1234 else if (frameless
&& qp
== 0 && rN
== fp_reg
&& imm
== 0 &&
1238 last_prologue_pc
= next_pc
;
1243 && ( ((instr
& 0x1efc0000000LL
) == 0x0eec0000000LL
)
1244 || ((instr
& 0x1ffc8000000LL
) == 0x0cec0000000LL
) ))
1246 /* stf.spill [rN] = fM, imm9
1248 stf.spill [rN] = fM */
1250 int imm
= imm9(instr
);
1251 int rN
= (int) ((instr
& 0x00007f00000LL
) >> 20);
1252 int fM
= (int) ((instr
& 0x000000fe000LL
) >> 13);
1253 int qp
= (int) (instr
& 0x0000000003fLL
);
1254 if (qp
== 0 && rN
== spill_reg
&& spill_addr
!= 0
1255 && ((2 <= fM
&& fM
<= 5) || (16 <= fM
&& fM
<= 31)))
1257 cache
->saved_regs
[IA64_FR0_REGNUM
+ fM
] = spill_addr
;
1259 if ((instr
& 0x1efc0000000) == 0x0eec0000000)
1262 spill_addr
= 0; /* last one; must be done */
1263 last_prologue_pc
= next_pc
;
1266 else if ((it
== M
&& ((instr
& 0x1eff8000000LL
) == 0x02110000000LL
))
1267 || (it
== I
&& ((instr
& 0x1eff8000000LL
) == 0x00050000000LL
)) )
1273 int arM
= (int) ((instr
& 0x00007f00000LL
) >> 20);
1274 int rN
= (int) ((instr
& 0x00000001fc0LL
) >> 6);
1275 int qp
= (int) (instr
& 0x0000000003fLL
);
1276 if (qp
== 0 && isScratch (rN
) && arM
== 36 /* ar.unat */)
1278 /* We have something like "mov.m r3 = ar.unat". Remember the
1279 r3 (or whatever) and watch for a store of this register... */
1281 last_prologue_pc
= next_pc
;
1284 else if (it
== I
&& ((instr
& 0x1eff8000000LL
) == 0x00198000000LL
))
1287 int rN
= (int) ((instr
& 0x00000001fc0LL
) >> 6);
1288 int qp
= (int) (instr
& 0x0000000003fLL
);
1289 if (qp
== 0 && isScratch (rN
))
1292 last_prologue_pc
= next_pc
;
1296 && ( ((instr
& 0x1ffc8000000LL
) == 0x08cc0000000LL
)
1297 || ((instr
& 0x1efc0000000LL
) == 0x0acc0000000LL
)))
1301 st8 [rN] = rM, imm9 */
1302 int rN
= (int) ((instr
& 0x00007f00000LL
) >> 20);
1303 int rM
= (int) ((instr
& 0x000000fe000LL
) >> 13);
1304 int qp
= (int) (instr
& 0x0000000003fLL
);
1305 int indirect
= rM
< 256 ? reg_contents
[rM
] : 0;
1306 if (qp
== 0 && rN
== spill_reg
&& spill_addr
!= 0
1307 && (rM
== unat_save_reg
|| rM
== pr_save_reg
))
1309 /* We've found a spill of either the UNAT register or the PR
1310 register. (Well, not exactly; what we've actually found is
1311 a spill of the register that UNAT or PR was moved to).
1312 Record that fact and move on... */
1313 if (rM
== unat_save_reg
)
1315 /* Track UNAT register */
1316 cache
->saved_regs
[IA64_UNAT_REGNUM
] = spill_addr
;
1321 /* Track PR register */
1322 cache
->saved_regs
[IA64_PR_REGNUM
] = spill_addr
;
1325 if ((instr
& 0x1efc0000000LL
) == 0x0acc0000000LL
)
1326 /* st8 [rN] = rM, imm9 */
1327 spill_addr
+= imm9(instr
);
1329 spill_addr
= 0; /* must be done spilling */
1330 last_prologue_pc
= next_pc
;
1332 else if (qp
== 0 && 32 <= rM
&& rM
< 40 && !instores
[rM
-32])
1334 /* Allow up to one store of each input register. */
1335 instores
[rM
-32] = 1;
1336 last_prologue_pc
= next_pc
;
1338 else if (qp
== 0 && 32 <= indirect
&& indirect
< 40 &&
1339 !instores
[indirect
-32])
1341 /* Allow an indirect store of an input register. */
1342 instores
[indirect
-32] = 1;
1343 last_prologue_pc
= next_pc
;
1346 else if (it
== M
&& ((instr
& 0x1ff08000000LL
) == 0x08c00000000LL
))
1353 Note that the st8 case is handled in the clause above.
1355 Advance over stores of input registers. One store per input
1356 register is permitted. */
1357 int rM
= (int) ((instr
& 0x000000fe000LL
) >> 13);
1358 int qp
= (int) (instr
& 0x0000000003fLL
);
1359 int indirect
= rM
< 256 ? reg_contents
[rM
] : 0;
1360 if (qp
== 0 && 32 <= rM
&& rM
< 40 && !instores
[rM
-32])
1362 instores
[rM
-32] = 1;
1363 last_prologue_pc
= next_pc
;
1365 else if (qp
== 0 && 32 <= indirect
&& indirect
< 40 &&
1366 !instores
[indirect
-32])
1368 /* Allow an indirect store of an input register. */
1369 instores
[indirect
-32] = 1;
1370 last_prologue_pc
= next_pc
;
1373 else if (it
== M
&& ((instr
& 0x1ff88000000LL
) == 0x0cc80000000LL
))
1380 Advance over stores of floating point input registers. Again
1381 one store per register is permitted */
1382 int fM
= (int) ((instr
& 0x000000fe000LL
) >> 13);
1383 int qp
= (int) (instr
& 0x0000000003fLL
);
1384 if (qp
== 0 && 8 <= fM
&& fM
< 16 && !infpstores
[fM
- 8])
1386 infpstores
[fM
-8] = 1;
1387 last_prologue_pc
= next_pc
;
1391 && ( ((instr
& 0x1ffc8000000LL
) == 0x08ec0000000LL
)
1392 || ((instr
& 0x1efc0000000LL
) == 0x0aec0000000LL
)))
1394 /* st8.spill [rN] = rM
1396 st8.spill [rN] = rM, imm9 */
1397 int rN
= (int) ((instr
& 0x00007f00000LL
) >> 20);
1398 int rM
= (int) ((instr
& 0x000000fe000LL
) >> 13);
1399 int qp
= (int) (instr
& 0x0000000003fLL
);
1400 if (qp
== 0 && rN
== spill_reg
&& 4 <= rM
&& rM
<= 7)
1402 /* We've found a spill of one of the preserved general purpose
1403 regs. Record the spill address and advance the spill
1404 register if appropriate. */
1405 cache
->saved_regs
[IA64_GR0_REGNUM
+ rM
] = spill_addr
;
1406 if ((instr
& 0x1efc0000000LL
) == 0x0aec0000000LL
)
1407 /* st8.spill [rN] = rM, imm9 */
1408 spill_addr
+= imm9(instr
);
1410 spill_addr
= 0; /* Done spilling */
1411 last_prologue_pc
= next_pc
;
1418 /* If not frameless and we aren't called by skip_prologue, then we need to calculate
1419 registers for the previous frame which will be needed later. */
1421 if (!frameless
&& next_frame
)
1423 /* Extract the size of the rotating portion of the stack
1424 frame and the register rename base from the current
1430 rrb_gr
= (cfm
>> 18) & 0x7f;
1432 /* Find the bof (beginning of frame). */
1433 bof
= rse_address_add (cache
->bsp
, -sof
);
1435 for (i
= 0, addr
= bof
;
1439 if (IS_NaT_COLLECTION_ADDR (addr
))
1443 if (i
+32 == cfm_reg
)
1444 cache
->saved_regs
[IA64_CFM_REGNUM
] = addr
;
1445 if (i
+32 == ret_reg
)
1446 cache
->saved_regs
[IA64_VRAP_REGNUM
] = addr
;
1448 cache
->saved_regs
[IA64_VFP_REGNUM
] = addr
;
1451 /* For the previous argument registers we require the previous bof.
1452 If we can't find the previous cfm, then we can do nothing. */
1453 if (cache
->saved_regs
[IA64_CFM_REGNUM
] != 0)
1455 cfm
= read_memory_integer (cache
->saved_regs
[IA64_CFM_REGNUM
], 8);
1456 sor
= ((cfm
>> 14) & 0xf) * 8;
1458 sol
= (cfm
>> 7) & 0x7f;
1459 rrb_gr
= (cfm
>> 18) & 0x7f;
1461 /* The previous bof only requires subtraction of the sol (size of locals)
1462 due to the overlap between output and input of subsequent frames. */
1463 bof
= rse_address_add (bof
, -sol
);
1465 for (i
= 0, addr
= bof
;
1469 if (IS_NaT_COLLECTION_ADDR (addr
))
1474 cache
->saved_regs
[IA64_GR32_REGNUM
+ ((i
+ (sor
- rrb_gr
)) % sor
)]
1477 cache
->saved_regs
[IA64_GR32_REGNUM
+ i
] = addr
;
1483 /* Try and trust the lim_pc value whenever possible. */
1484 if (trust_limit
&& lim_pc
>= last_prologue_pc
)
1485 last_prologue_pc
= lim_pc
;
1487 cache
->frameless
= frameless
;
1488 cache
->after_prologue
= last_prologue_pc
;
1489 cache
->mem_stack_frame_size
= mem_stack_frame_size
;
1490 cache
->fp_reg
= fp_reg
;
1492 return last_prologue_pc
;
1496 ia64_skip_prologue (CORE_ADDR pc
)
1498 struct ia64_frame_cache cache
;
1500 cache
.after_prologue
= 0;
1504 /* Call examine_prologue with - as third argument since we don't have a next frame pointer to send. */
1505 return examine_prologue (pc
, pc
+1024, 0, &cache
);
1509 /* Normal frames. */
1511 static struct ia64_frame_cache
*
1512 ia64_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1514 struct ia64_frame_cache
*cache
;
1516 CORE_ADDR cfm
, sof
, sol
, bsp
, psr
;
1522 cache
= ia64_alloc_frame_cache ();
1523 *this_cache
= cache
;
1525 frame_unwind_register (next_frame
, sp_regnum
, buf
);
1526 cache
->saved_sp
= extract_unsigned_integer (buf
, 8);
1528 /* We always want the bsp to point to the end of frame.
1529 This way, we can always get the beginning of frame (bof)
1530 by subtracting frame size. */
1531 frame_unwind_register (next_frame
, IA64_BSP_REGNUM
, buf
);
1532 cache
->bsp
= extract_unsigned_integer (buf
, 8);
1534 frame_unwind_register (next_frame
, IA64_PSR_REGNUM
, buf
);
1535 psr
= extract_unsigned_integer (buf
, 8);
1537 frame_unwind_register (next_frame
, IA64_CFM_REGNUM
, buf
);
1538 cfm
= extract_unsigned_integer (buf
, 8);
1540 cache
->sof
= (cfm
& 0x7f);
1541 cache
->sol
= (cfm
>> 7) & 0x7f;
1542 cache
->sor
= ((cfm
>> 14) & 0xf) * 8;
1546 cache
->pc
= frame_func_unwind (next_frame
);
1549 examine_prologue (cache
->pc
, frame_pc_unwind (next_frame
), next_frame
, cache
);
1551 cache
->base
= cache
->saved_sp
+ cache
->mem_stack_frame_size
;
1557 ia64_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
1558 struct frame_id
*this_id
)
1560 struct ia64_frame_cache
*cache
=
1561 ia64_frame_cache (next_frame
, this_cache
);
1563 /* This marks the outermost frame. */
1564 if (cache
->base
== 0)
1567 (*this_id
) = frame_id_build (cache
->base
, cache
->pc
);
1571 ia64_frame_prev_register (struct frame_info
*next_frame
, void **this_cache
,
1572 int regnum
, int *optimizedp
,
1573 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1574 int *realnump
, void *valuep
)
1576 struct ia64_frame_cache
*cache
=
1577 ia64_frame_cache (next_frame
, this_cache
);
1578 char dummy_valp
[MAX_REGISTER_SIZE
];
1581 gdb_assert (regnum
>= 0);
1583 if (!target_has_registers
)
1584 error ("No registers.");
1591 /* Rather than check each time if valuep is non-null, supply a dummy buffer
1592 when valuep is not supplied. */
1594 valuep
= dummy_valp
;
1596 memset (valuep
, 0, REGISTER_RAW_SIZE (regnum
));
1598 if (regnum
== SP_REGNUM
)
1600 /* Handle SP values for all frames but the topmost. */
1601 store_unsigned_integer (valuep
, REGISTER_RAW_SIZE (regnum
),
1604 else if (regnum
== IA64_BSP_REGNUM
)
1606 char cfm_valuep
[MAX_REGISTER_SIZE
];
1609 enum lval_type cfm_lval
;
1611 CORE_ADDR bsp
, prev_cfm
, prev_bsp
;
1613 /* We want to calculate the previous bsp as the end of the previous register stack frame.
1614 This corresponds to what the hardware bsp register will be if we pop the frame
1615 back which is why we might have been called. We know the beginning of the current
1616 frame is cache->bsp - cache->sof. This value in the previous frame points to
1617 the start of the output registers. We can calculate the end of that frame by adding
1618 the size of output (sof (size of frame) - sol (size of locals)). */
1619 ia64_frame_prev_register (next_frame
, this_cache
, IA64_CFM_REGNUM
,
1620 &cfm_optim
, &cfm_lval
, &cfm_addr
, &cfm_realnum
, cfm_valuep
);
1621 prev_cfm
= extract_unsigned_integer (cfm_valuep
, 8);
1623 bsp
= rse_address_add (cache
->bsp
, -(cache
->sof
));
1624 prev_bsp
= rse_address_add (bsp
, (prev_cfm
& 0x7f) - ((prev_cfm
>> 7) & 0x7f));
1626 store_unsigned_integer (valuep
, REGISTER_RAW_SIZE (regnum
),
1629 else if (regnum
== IA64_CFM_REGNUM
)
1633 if (cache
->frameless
)
1636 frame_unwind_register (next_frame
, IA64_PFS_REGNUM
, valuep
);
1640 addr
= cache
->saved_regs
[IA64_CFM_REGNUM
];
1642 read_memory (addr
, valuep
, REGISTER_RAW_SIZE (regnum
));
1645 else if (regnum
== IA64_VFP_REGNUM
)
1647 /* If the function in question uses an automatic register (r32-r127)
1648 for the frame pointer, it'll be found by ia64_find_saved_register()
1649 above. If the function lacks one of these frame pointers, we can
1650 still provide a value since we know the size of the frame. */
1651 CORE_ADDR vfp
= cache
->base
;
1652 store_unsigned_integer (valuep
, REGISTER_RAW_SIZE (IA64_VFP_REGNUM
), vfp
);
1654 else if (VP0_REGNUM
<= regnum
&& regnum
<= VP63_REGNUM
)
1656 char pr_valuep
[MAX_REGISTER_SIZE
];
1659 enum lval_type pr_lval
;
1662 ia64_frame_prev_register (next_frame
, this_cache
, IA64_PR_REGNUM
,
1663 &pr_optim
, &pr_lval
, &pr_addr
, &pr_realnum
, pr_valuep
);
1664 if (VP16_REGNUM
<= regnum
&& regnum
<= VP63_REGNUM
)
1666 /* Fetch predicate register rename base from current frame
1667 marker for this frame. */
1668 int rrb_pr
= (cache
->cfm
>> 32) & 0x3f;
1670 /* Adjust the register number to account for register rotation. */
1671 regnum
= VP16_REGNUM
1672 + ((regnum
- VP16_REGNUM
) + rrb_pr
) % 48;
1674 prN_val
= extract_bit_field ((unsigned char *) pr_valuep
,
1675 regnum
- VP0_REGNUM
, 1);
1676 store_unsigned_integer (valuep
, REGISTER_RAW_SIZE (regnum
), prN_val
);
1678 else if (IA64_NAT0_REGNUM
<= regnum
&& regnum
<= IA64_NAT31_REGNUM
)
1680 char unat_valuep
[MAX_REGISTER_SIZE
];
1683 enum lval_type unat_lval
;
1684 CORE_ADDR unat_addr
;
1686 ia64_frame_prev_register (next_frame
, this_cache
, IA64_UNAT_REGNUM
,
1687 &unat_optim
, &unat_lval
, &unat_addr
, &unat_realnum
, unat_valuep
);
1688 unatN_val
= extract_bit_field ((unsigned char *) unat_valuep
,
1689 regnum
- IA64_NAT0_REGNUM
, 1);
1690 store_unsigned_integer (valuep
, REGISTER_RAW_SIZE (regnum
),
1693 else if (IA64_NAT32_REGNUM
<= regnum
&& regnum
<= IA64_NAT127_REGNUM
)
1696 /* Find address of general register corresponding to nat bit we're
1700 gr_addr
= cache
->saved_regs
[regnum
- IA64_NAT0_REGNUM
1704 /* Compute address of nat collection bits. */
1705 CORE_ADDR nat_addr
= gr_addr
| 0x1f8;
1707 CORE_ADDR nat_collection
;
1709 /* If our nat collection address is bigger than bsp, we have to get
1710 the nat collection from rnat. Otherwise, we fetch the nat
1711 collection from the computed address. */
1712 frame_unwind_register (next_frame
, IA64_BSP_REGNUM
, buf
);
1713 bsp
= extract_unsigned_integer (buf
, 8);
1714 if (nat_addr
>= bsp
)
1716 frame_unwind_register (next_frame
, IA64_RNAT_REGNUM
, buf
);
1717 nat_collection
= extract_unsigned_integer (buf
, 8);
1720 nat_collection
= read_memory_integer (nat_addr
, 8);
1721 nat_bit
= (gr_addr
>> 3) & 0x3f;
1722 natval
= (nat_collection
>> nat_bit
) & 1;
1725 store_unsigned_integer (valuep
, REGISTER_RAW_SIZE (regnum
), natval
);
1727 else if (regnum
== IA64_IP_REGNUM
)
1731 if (cache
->frameless
)
1733 frame_unwind_register (next_frame
, IA64_BR0_REGNUM
, buf
);
1734 pc
= extract_unsigned_integer (buf
, 8);
1738 CORE_ADDR addr
= cache
->saved_regs
[IA64_VRAP_REGNUM
];
1741 read_memory (addr
, buf
, REGISTER_RAW_SIZE (IA64_IP_REGNUM
));
1742 pc
= extract_unsigned_integer (buf
, 8);
1746 store_unsigned_integer (valuep
, 8, pc
);
1748 else if (regnum
== IA64_PSR_REGNUM
)
1750 ULONGEST slot_num
= 0;
1754 frame_unwind_register (next_frame
, IA64_PSR_REGNUM
, buf
);
1755 psr
= extract_unsigned_integer (buf
, 8);
1757 if (cache
->frameless
)
1760 frame_unwind_register (next_frame
, IA64_BR0_REGNUM
, buf
);
1761 pc
= extract_unsigned_integer (buf
, 8);
1765 CORE_ADDR addr
= cache
->saved_regs
[IA64_VRAP_REGNUM
];
1768 read_memory (addr
, buf
, REGISTER_RAW_SIZE (IA64_IP_REGNUM
));
1769 pc
= extract_unsigned_integer (buf
, 8);
1772 psr
&= ~(3LL << 41);
1773 slot_num
= pc
& 0x3LL
;
1774 psr
|= (CORE_ADDR
)slot_num
<< 41;
1775 store_unsigned_integer (valuep
, 8, psr
);
1777 else if ((regnum
>= IA64_GR32_REGNUM
&& regnum
<= IA64_GR127_REGNUM
) ||
1778 (regnum
>= V32_REGNUM
&& regnum
<= V127_REGNUM
))
1781 if (regnum
>= V32_REGNUM
)
1782 regnum
= IA64_GR32_REGNUM
+ (regnum
- V32_REGNUM
);
1783 addr
= cache
->saved_regs
[regnum
];
1786 *lvalp
= lval_memory
;
1788 read_memory (addr
, valuep
, REGISTER_RAW_SIZE (regnum
));
1790 else if (cache
->frameless
)
1792 char r_valuep
[MAX_REGISTER_SIZE
];
1795 enum lval_type r_lval
;
1797 CORE_ADDR prev_cfm
, prev_bsp
, prev_bof
;
1799 if (regnum
>= V32_REGNUM
)
1800 regnum
= IA64_GR32_REGNUM
+ (regnum
- V32_REGNUM
);
1801 ia64_frame_prev_register (next_frame
, this_cache
, IA64_CFM_REGNUM
,
1802 &r_optim
, &r_lval
, &r_addr
, &r_realnum
, r_valuep
);
1803 prev_cfm
= extract_unsigned_integer (r_valuep
, 8);
1804 ia64_frame_prev_register (next_frame
, this_cache
, IA64_BSP_REGNUM
,
1805 &r_optim
, &r_lval
, &r_addr
, &r_realnum
, r_valuep
);
1806 prev_bsp
= extract_unsigned_integer (r_valuep
, 8);
1807 prev_bof
= rse_address_add (prev_bsp
, -(prev_cfm
& 0x7f));
1809 addr
= rse_address_add (prev_bof
, (regnum
- IA64_GR32_REGNUM
));
1810 *lvalp
= lval_memory
;
1812 read_memory (addr
, valuep
, REGISTER_RAW_SIZE (regnum
));
1818 if (IA64_FR32_REGNUM
<= regnum
&& regnum
<= IA64_FR127_REGNUM
)
1820 /* Fetch floating point register rename base from current
1821 frame marker for this frame. */
1822 int rrb_fr
= (cache
->cfm
>> 25) & 0x7f;
1824 /* Adjust the floating point register number to account for
1825 register rotation. */
1826 regnum
= IA64_FR32_REGNUM
1827 + ((regnum
- IA64_FR32_REGNUM
) + rrb_fr
) % 96;
1830 /* If we have stored a memory address, access the register. */
1831 addr
= cache
->saved_regs
[regnum
];
1834 *lvalp
= lval_memory
;
1836 read_memory (addr
, valuep
, REGISTER_RAW_SIZE (regnum
));
1838 /* Otherwise, punt and get the current value of the register. */
1840 frame_unwind_register (next_frame
, regnum
, valuep
);
1844 static const struct frame_unwind ia64_frame_unwind
=
1847 &ia64_frame_this_id
,
1848 &ia64_frame_prev_register
1851 static const struct frame_unwind
*
1852 ia64_frame_sniffer (struct frame_info
*next_frame
)
1854 return &ia64_frame_unwind
;
1857 /* Signal trampolines. */
1860 ia64_sigtramp_frame_init_saved_regs (struct ia64_frame_cache
*cache
)
1862 if (SIGCONTEXT_REGISTER_ADDRESS
)
1866 cache
->saved_regs
[IA64_VRAP_REGNUM
] =
1867 SIGCONTEXT_REGISTER_ADDRESS (cache
->base
, IA64_IP_REGNUM
);
1868 cache
->saved_regs
[IA64_CFM_REGNUM
] =
1869 SIGCONTEXT_REGISTER_ADDRESS (cache
->base
, IA64_CFM_REGNUM
);
1870 cache
->saved_regs
[IA64_PSR_REGNUM
] =
1871 SIGCONTEXT_REGISTER_ADDRESS (cache
->base
, IA64_PSR_REGNUM
);
1873 cache
->saved_regs
[IA64_BSP_REGNUM
] =
1874 SIGCONTEXT_REGISTER_ADDRESS (frame
->frame
, IA64_BSP_REGNUM
);
1876 cache
->saved_regs
[IA64_RNAT_REGNUM
] =
1877 SIGCONTEXT_REGISTER_ADDRESS (cache
->base
, IA64_RNAT_REGNUM
);
1878 cache
->saved_regs
[IA64_CCV_REGNUM
] =
1879 SIGCONTEXT_REGISTER_ADDRESS (cache
->base
, IA64_CCV_REGNUM
);
1880 cache
->saved_regs
[IA64_UNAT_REGNUM
] =
1881 SIGCONTEXT_REGISTER_ADDRESS (cache
->base
, IA64_UNAT_REGNUM
);
1882 cache
->saved_regs
[IA64_FPSR_REGNUM
] =
1883 SIGCONTEXT_REGISTER_ADDRESS (cache
->base
, IA64_FPSR_REGNUM
);
1884 cache
->saved_regs
[IA64_PFS_REGNUM
] =
1885 SIGCONTEXT_REGISTER_ADDRESS (cache
->base
, IA64_PFS_REGNUM
);
1886 cache
->saved_regs
[IA64_LC_REGNUM
] =
1887 SIGCONTEXT_REGISTER_ADDRESS (cache
->base
, IA64_LC_REGNUM
);
1888 for (regno
= IA64_GR1_REGNUM
; regno
<= IA64_GR31_REGNUM
; regno
++)
1889 if (regno
!= sp_regnum
)
1890 cache
->saved_regs
[regno
] =
1891 SIGCONTEXT_REGISTER_ADDRESS (cache
->base
, regno
);
1892 for (regno
= IA64_BR0_REGNUM
; regno
<= IA64_BR7_REGNUM
; regno
++)
1893 cache
->saved_regs
[regno
] =
1894 SIGCONTEXT_REGISTER_ADDRESS (cache
->base
, regno
);
1895 for (regno
= IA64_FR2_REGNUM
; regno
<= IA64_FR31_REGNUM
; regno
++)
1896 cache
->saved_regs
[regno
] =
1897 SIGCONTEXT_REGISTER_ADDRESS (cache
->base
, regno
);
1901 static struct ia64_frame_cache
*
1902 ia64_sigtramp_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1904 struct ia64_frame_cache
*cache
;
1912 cache
= ia64_alloc_frame_cache ();
1914 frame_unwind_register (next_frame
, sp_regnum
, buf
);
1915 cache
->base
= extract_unsigned_integer (buf
, 8) + cache
->mem_stack_frame_size
;
1917 ia64_sigtramp_frame_init_saved_regs (cache
);
1919 *this_cache
= cache
;
1924 ia64_sigtramp_frame_this_id (struct frame_info
*next_frame
,
1925 void **this_cache
, struct frame_id
*this_id
)
1927 struct ia64_frame_cache
*cache
=
1928 ia64_sigtramp_frame_cache (next_frame
, this_cache
);
1930 (*this_id
) = frame_id_build (cache
->base
, frame_pc_unwind (next_frame
));
1934 ia64_sigtramp_frame_prev_register (struct frame_info
*next_frame
,
1936 int regnum
, int *optimizedp
,
1937 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1938 int *realnump
, void *valuep
)
1940 /* Make sure we've initialized the cache. */
1941 ia64_sigtramp_frame_cache (next_frame
, this_cache
);
1943 ia64_frame_prev_register (next_frame
, this_cache
, regnum
,
1944 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
1947 static const struct frame_unwind ia64_sigtramp_frame_unwind
=
1950 ia64_sigtramp_frame_this_id
,
1951 ia64_sigtramp_frame_prev_register
1954 static const struct frame_unwind
*
1955 ia64_sigtramp_frame_sniffer (struct frame_info
*next_frame
)
1958 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1960 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
1961 if (PC_IN_SIGTRAMP (pc
, name
))
1962 return &ia64_sigtramp_frame_unwind
;
1969 ia64_frame_base_address (struct frame_info
*next_frame
, void **this_cache
)
1971 struct ia64_frame_cache
*cache
=
1972 ia64_frame_cache (next_frame
, this_cache
);
1977 static const struct frame_base ia64_frame_base
=
1980 ia64_frame_base_address
,
1981 ia64_frame_base_address
,
1982 ia64_frame_base_address
1985 /* Should we use EXTRACT_STRUCT_VALUE_ADDRESS instead of
1986 EXTRACT_RETURN_VALUE? GCC_P is true if compiled with gcc
1987 and TYPE is the type (which is known to be struct, union or array). */
1989 ia64_use_struct_convention (int gcc_p
, struct type
*type
)
1991 struct type
*float_elt_type
;
1993 /* HFAs are structures (or arrays) consisting entirely of floating
1994 point values of the same length. Up to 8 of these are returned
1995 in registers. Don't use the struct convention when this is the
1997 float_elt_type
= is_float_or_hfa_type (type
);
1998 if (float_elt_type
!= NULL
1999 && TYPE_LENGTH (type
) / TYPE_LENGTH (float_elt_type
) <= 8)
2002 /* Other structs of length 32 or less are returned in r8-r11.
2003 Don't use the struct convention for those either. */
2004 return TYPE_LENGTH (type
) > 32;
2008 ia64_extract_return_value (struct type
*type
, struct regcache
*regcache
, void *valbuf
)
2010 struct type
*float_elt_type
;
2012 float_elt_type
= is_float_or_hfa_type (type
);
2013 if (float_elt_type
!= NULL
)
2015 char from
[MAX_REGISTER_SIZE
];
2017 int regnum
= IA64_FR8_REGNUM
;
2018 int n
= TYPE_LENGTH (type
) / TYPE_LENGTH (float_elt_type
);
2022 regcache_cooked_read (regcache
, regnum
, from
);
2023 convert_typed_floating (from
, builtin_type_ia64_ext
,
2024 (char *)valbuf
+ offset
, float_elt_type
);
2025 offset
+= TYPE_LENGTH (float_elt_type
);
2033 int regnum
= IA64_GR8_REGNUM
;
2034 int reglen
= TYPE_LENGTH (ia64_register_type (NULL
, IA64_GR8_REGNUM
));
2035 int n
= TYPE_LENGTH (type
) / reglen
;
2036 int m
= TYPE_LENGTH (type
) % reglen
;
2041 regcache_cooked_read_unsigned (regcache
, regnum
, &val
);
2042 memcpy ((char *)valbuf
+ offset
, &val
, reglen
);
2049 regcache_cooked_read_unsigned (regcache
, regnum
, &val
);
2050 memcpy ((char *)valbuf
+ offset
, &val
, m
);
2056 ia64_extract_struct_value_address (struct regcache
*regcache
)
2058 error ("ia64_extract_struct_value_address called and cannot get struct value address");
2064 is_float_or_hfa_type_recurse (struct type
*t
, struct type
**etp
)
2066 switch (TYPE_CODE (t
))
2070 return TYPE_LENGTH (*etp
) == TYPE_LENGTH (t
);
2077 case TYPE_CODE_ARRAY
:
2079 is_float_or_hfa_type_recurse (check_typedef (TYPE_TARGET_TYPE (t
)),
2082 case TYPE_CODE_STRUCT
:
2086 for (i
= 0; i
< TYPE_NFIELDS (t
); i
++)
2087 if (!is_float_or_hfa_type_recurse
2088 (check_typedef (TYPE_FIELD_TYPE (t
, i
)), etp
))
2099 /* Determine if the given type is one of the floating point types or
2100 and HFA (which is a struct, array, or combination thereof whose
2101 bottom-most elements are all of the same floating point type). */
2103 static struct type
*
2104 is_float_or_hfa_type (struct type
*t
)
2106 struct type
*et
= 0;
2108 return is_float_or_hfa_type_recurse (t
, &et
) ? et
: 0;
2112 /* Return 1 if the alignment of T is such that the next even slot
2113 should be used. Return 0, if the next available slot should
2114 be used. (See section 8.5.1 of the IA-64 Software Conventions
2115 and Runtime manual). */
2118 slot_alignment_is_next_even (struct type
*t
)
2120 switch (TYPE_CODE (t
))
2124 if (TYPE_LENGTH (t
) > 8)
2128 case TYPE_CODE_ARRAY
:
2130 slot_alignment_is_next_even (check_typedef (TYPE_TARGET_TYPE (t
)));
2131 case TYPE_CODE_STRUCT
:
2135 for (i
= 0; i
< TYPE_NFIELDS (t
); i
++)
2136 if (slot_alignment_is_next_even
2137 (check_typedef (TYPE_FIELD_TYPE (t
, i
))))
2146 /* Attempt to find (and return) the global pointer for the given
2149 This is a rather nasty bit of code searchs for the .dynamic section
2150 in the objfile corresponding to the pc of the function we're trying
2151 to call. Once it finds the addresses at which the .dynamic section
2152 lives in the child process, it scans the Elf64_Dyn entries for a
2153 DT_PLTGOT tag. If it finds one of these, the corresponding
2154 d_un.d_ptr value is the global pointer. */
2157 generic_elf_find_global_pointer (CORE_ADDR faddr
)
2159 struct obj_section
*faddr_sect
;
2161 faddr_sect
= find_pc_section (faddr
);
2162 if (faddr_sect
!= NULL
)
2164 struct obj_section
*osect
;
2166 ALL_OBJFILE_OSECTIONS (faddr_sect
->objfile
, osect
)
2168 if (strcmp (osect
->the_bfd_section
->name
, ".dynamic") == 0)
2172 if (osect
< faddr_sect
->objfile
->sections_end
)
2177 while (addr
< osect
->endaddr
)
2183 status
= target_read_memory (addr
, buf
, sizeof (buf
));
2186 tag
= extract_signed_integer (buf
, sizeof (buf
));
2188 if (tag
== DT_PLTGOT
)
2190 CORE_ADDR global_pointer
;
2192 status
= target_read_memory (addr
+ 8, buf
, sizeof (buf
));
2195 global_pointer
= extract_unsigned_integer (buf
, sizeof (buf
));
2198 return global_pointer
;
2211 /* Given a function's address, attempt to find (and return) the
2212 corresponding (canonical) function descriptor. Return 0 if
2215 find_extant_func_descr (CORE_ADDR faddr
)
2217 struct obj_section
*faddr_sect
;
2219 /* Return early if faddr is already a function descriptor. */
2220 faddr_sect
= find_pc_section (faddr
);
2221 if (faddr_sect
&& strcmp (faddr_sect
->the_bfd_section
->name
, ".opd") == 0)
2224 if (faddr_sect
!= NULL
)
2226 struct obj_section
*osect
;
2227 ALL_OBJFILE_OSECTIONS (faddr_sect
->objfile
, osect
)
2229 if (strcmp (osect
->the_bfd_section
->name
, ".opd") == 0)
2233 if (osect
< faddr_sect
->objfile
->sections_end
)
2238 while (addr
< osect
->endaddr
)
2244 status
= target_read_memory (addr
, buf
, sizeof (buf
));
2247 faddr2
= extract_signed_integer (buf
, sizeof (buf
));
2249 if (faddr
== faddr2
)
2259 /* Attempt to find a function descriptor corresponding to the
2260 given address. If none is found, construct one on the
2261 stack using the address at fdaptr. */
2264 find_func_descr (CORE_ADDR faddr
, CORE_ADDR
*fdaptr
)
2268 fdesc
= find_extant_func_descr (faddr
);
2272 CORE_ADDR global_pointer
;
2278 global_pointer
= FIND_GLOBAL_POINTER (faddr
);
2280 if (global_pointer
== 0)
2281 global_pointer
= read_register (IA64_GR1_REGNUM
);
2283 store_unsigned_integer (buf
, 8, faddr
);
2284 store_unsigned_integer (buf
+ 8, 8, global_pointer
);
2286 write_memory (fdesc
, buf
, 16);
2292 /* Use the following routine when printing out function pointers
2293 so the user can see the function address rather than just the
2294 function descriptor. */
2296 ia64_convert_from_func_ptr_addr (CORE_ADDR addr
)
2298 struct obj_section
*s
;
2300 s
= find_pc_section (addr
);
2302 /* check if ADDR points to a function descriptor. */
2303 if (s
&& strcmp (s
->the_bfd_section
->name
, ".opd") == 0)
2304 return read_memory_unsigned_integer (addr
, 8);
2310 ia64_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
2316 ia64_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
2317 struct regcache
*regcache
, CORE_ADDR bp_addr
,
2318 int nargs
, struct value
**args
, CORE_ADDR sp
,
2319 int struct_return
, CORE_ADDR struct_addr
)
2325 int nslots
, rseslots
, memslots
, slotnum
, nfuncargs
;
2327 CORE_ADDR bsp
, cfm
, pfs
, new_bsp
, funcdescaddr
, pc
, global_pointer
;
2331 /* Count the number of slots needed for the arguments. */
2332 for (argno
= 0; argno
< nargs
; argno
++)
2335 type
= check_typedef (VALUE_TYPE (arg
));
2336 len
= TYPE_LENGTH (type
);
2338 if ((nslots
& 1) && slot_alignment_is_next_even (type
))
2341 if (TYPE_CODE (type
) == TYPE_CODE_FUNC
)
2344 nslots
+= (len
+ 7) / 8;
2347 /* Divvy up the slots between the RSE and the memory stack. */
2348 rseslots
= (nslots
> 8) ? 8 : nslots
;
2349 memslots
= nslots
- rseslots
;
2351 /* Allocate a new RSE frame. */
2352 cfm
= read_register (IA64_CFM_REGNUM
);
2354 bsp
= read_register (IA64_BSP_REGNUM
);
2355 new_bsp
= rse_address_add (bsp
, rseslots
);
2356 write_register (IA64_BSP_REGNUM
, new_bsp
);
2358 pfs
= read_register (IA64_PFS_REGNUM
);
2359 pfs
&= 0xc000000000000000LL
;
2360 pfs
|= (cfm
& 0xffffffffffffLL
);
2361 write_register (IA64_PFS_REGNUM
, pfs
);
2363 cfm
&= 0xc000000000000000LL
;
2365 write_register (IA64_CFM_REGNUM
, cfm
);
2367 /* We will attempt to find function descriptors in the .opd segment,
2368 but if we can't we'll construct them ourselves. That being the
2369 case, we'll need to reserve space on the stack for them. */
2370 funcdescaddr
= sp
- nfuncargs
* 16;
2371 funcdescaddr
&= ~0xfLL
;
2373 /* Adjust the stack pointer to it's new value. The calling conventions
2374 require us to have 16 bytes of scratch, plus whatever space is
2375 necessary for the memory slots and our function descriptors. */
2376 sp
= sp
- 16 - (memslots
+ nfuncargs
) * 8;
2377 sp
&= ~0xfLL
; /* Maintain 16 byte alignment. */
2379 /* Place the arguments where they belong. The arguments will be
2380 either placed in the RSE backing store or on the memory stack.
2381 In addition, floating point arguments or HFAs are placed in
2382 floating point registers. */
2384 floatreg
= IA64_FR8_REGNUM
;
2385 for (argno
= 0; argno
< nargs
; argno
++)
2387 struct type
*float_elt_type
;
2390 type
= check_typedef (VALUE_TYPE (arg
));
2391 len
= TYPE_LENGTH (type
);
2393 /* Special handling for function parameters. */
2395 && TYPE_CODE (type
) == TYPE_CODE_PTR
2396 && TYPE_CODE (TYPE_TARGET_TYPE (type
)) == TYPE_CODE_FUNC
)
2400 store_unsigned_integer (val_buf
, 8,
2401 find_func_descr (extract_unsigned_integer (VALUE_CONTENTS (arg
), 8),
2403 if (slotnum
< rseslots
)
2404 write_memory (rse_address_add (bsp
, slotnum
), val_buf
, 8);
2406 write_memory (sp
+ 16 + 8 * (slotnum
- rseslots
), val_buf
, 8);
2413 /* Skip odd slot if necessary... */
2414 if ((slotnum
& 1) && slot_alignment_is_next_even (type
))
2422 memset (val_buf
, 0, 8);
2423 memcpy (val_buf
, VALUE_CONTENTS (arg
) + argoffset
, (len
> 8) ? 8 : len
);
2425 if (slotnum
< rseslots
)
2426 write_memory (rse_address_add (bsp
, slotnum
), val_buf
, 8);
2428 write_memory (sp
+ 16 + 8 * (slotnum
- rseslots
), val_buf
, 8);
2435 /* Handle floating point types (including HFAs). */
2436 float_elt_type
= is_float_or_hfa_type (type
);
2437 if (float_elt_type
!= NULL
)
2440 len
= TYPE_LENGTH (type
);
2441 while (len
> 0 && floatreg
< IA64_FR16_REGNUM
)
2443 char to
[MAX_REGISTER_SIZE
];
2444 convert_typed_floating (VALUE_CONTENTS (arg
) + argoffset
, float_elt_type
,
2445 to
, builtin_type_ia64_ext
);
2446 regcache_cooked_write (regcache
, floatreg
, (void *)to
);
2448 argoffset
+= TYPE_LENGTH (float_elt_type
);
2449 len
-= TYPE_LENGTH (float_elt_type
);
2454 /* Store the struct return value in r8 if necessary. */
2457 regcache_cooked_write_unsigned (regcache
, IA64_GR8_REGNUM
, (ULONGEST
)struct_addr
);
2460 global_pointer
= FIND_GLOBAL_POINTER (func_addr
);
2462 if (global_pointer
!= 0)
2463 write_register (IA64_GR1_REGNUM
, global_pointer
);
2465 write_register (IA64_BR0_REGNUM
, bp_addr
);
2467 write_register (sp_regnum
, sp
);
2472 static struct frame_id
2473 ia64_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
2478 frame_unwind_register (next_frame
, sp_regnum
, buf
);
2479 sp
= extract_unsigned_integer (buf
, 8);
2481 return frame_id_build (sp
, frame_pc_unwind (next_frame
));
2485 ia64_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
2488 CORE_ADDR ip
, psr
, pc
;
2490 frame_unwind_register (next_frame
, IA64_IP_REGNUM
, buf
);
2491 ip
= extract_unsigned_integer (buf
, 8);
2492 frame_unwind_register (next_frame
, IA64_PSR_REGNUM
, buf
);
2493 psr
= extract_unsigned_integer (buf
, 8);
2495 pc
= (ip
& ~0xf) | ((psr
>> 41) & 3);
2500 ia64_store_return_value (struct type
*type
, struct regcache
*regcache
, const void *valbuf
)
2502 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2504 char to
[MAX_REGISTER_SIZE
];
2505 convert_typed_floating (valbuf
, type
, to
, builtin_type_ia64_ext
);
2506 regcache_cooked_write (regcache
, IA64_FR8_REGNUM
, (void *)to
);
2507 target_store_registers (IA64_FR8_REGNUM
);
2510 regcache_cooked_write (regcache
, IA64_GR8_REGNUM
, valbuf
);
2514 ia64_remote_translate_xfer_address (struct gdbarch
*gdbarch
,
2515 struct regcache
*regcache
,
2516 CORE_ADDR memaddr
, int nr_bytes
,
2517 CORE_ADDR
*targ_addr
, int *targ_len
)
2519 *targ_addr
= memaddr
;
2520 *targ_len
= nr_bytes
;
2524 process_note_abi_tag_sections (bfd
*abfd
, asection
*sect
, void *obj
)
2526 int *os_ident_ptr
= obj
;
2528 unsigned int sectsize
;
2530 name
= bfd_get_section_name (abfd
, sect
);
2531 sectsize
= bfd_section_size (abfd
, sect
);
2532 if (strcmp (name
, ".note.ABI-tag") == 0 && sectsize
> 0)
2534 unsigned int name_length
, data_length
, note_type
;
2535 char *note
= alloca (sectsize
);
2537 bfd_get_section_contents (abfd
, sect
, note
,
2538 (file_ptr
) 0, (bfd_size_type
) sectsize
);
2540 name_length
= bfd_h_get_32 (abfd
, note
);
2541 data_length
= bfd_h_get_32 (abfd
, note
+ 4);
2542 note_type
= bfd_h_get_32 (abfd
, note
+ 8);
2544 if (name_length
== 4 && data_length
== 16 && note_type
== 1
2545 && strcmp (note
+ 12, "GNU") == 0)
2547 int os_number
= bfd_h_get_32 (abfd
, note
+ 16);
2549 /* The case numbers are from abi-tags in glibc. */
2553 *os_ident_ptr
= ELFOSABI_LINUX
;
2556 *os_ident_ptr
= ELFOSABI_HURD
;
2559 *os_ident_ptr
= ELFOSABI_SOLARIS
;
2562 internal_error (__FILE__
, __LINE__
,
2563 "process_note_abi_sections: unknown OS number %d", os_number
);
2571 ia64_print_insn (bfd_vma memaddr
, struct disassemble_info
*info
)
2573 info
->bytes_per_line
= SLOT_MULTIPLIER
;
2574 return print_insn_ia64 (memaddr
, info
);
2577 static struct gdbarch
*
2578 ia64_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
2580 struct gdbarch
*gdbarch
;
2581 struct gdbarch_tdep
*tdep
;
2584 if (info
.abfd
!= NULL
2585 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
2587 os_ident
= elf_elfheader (info
.abfd
)->e_ident
[EI_OSABI
];
2589 /* If os_ident is 0, it is not necessarily the case that we're
2590 on a SYSV system. (ELFOSABI_NONE is defined to be 0.)
2591 GNU/Linux uses a note section to record OS/ABI info, but
2592 leaves e_ident[EI_OSABI] zero. So we have to check for note
2596 bfd_map_over_sections (info
.abfd
,
2597 process_note_abi_tag_sections
,
2604 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
2606 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
2608 tdep
= gdbarch_tdep (arches
->gdbarch
);
2609 if (tdep
&&tdep
->os_ident
== os_ident
)
2610 return arches
->gdbarch
;
2613 tdep
= xmalloc (sizeof (struct gdbarch_tdep
));
2614 gdbarch
= gdbarch_alloc (&info
, tdep
);
2615 tdep
->os_ident
= os_ident
;
2617 /* Set the method of obtaining the sigcontext addresses at which
2618 registers are saved. The method of checking to see if
2619 native_find_global_pointer is nonzero to indicate that we're
2620 on AIX is kind of hokey, but I can't think of a better way
2622 if (os_ident
== ELFOSABI_LINUX
)
2623 tdep
->sigcontext_register_address
= ia64_linux_sigcontext_register_address
;
2624 else if (native_find_global_pointer
!= 0)
2625 tdep
->sigcontext_register_address
= ia64_aix_sigcontext_register_address
;
2627 tdep
->sigcontext_register_address
= 0;
2629 /* We know that GNU/Linux won't have to resort to the
2630 native_find_global_pointer hackery. But that's the only one we
2631 know about so far, so if native_find_global_pointer is set to
2632 something non-zero, then use it. Otherwise fall back to using
2633 generic_elf_find_global_pointer. This arrangement should (in
2634 theory) allow us to cross debug GNU/Linux binaries from an AIX
2636 if (os_ident
== ELFOSABI_LINUX
)
2637 tdep
->find_global_pointer
= generic_elf_find_global_pointer
;
2638 else if (native_find_global_pointer
!= 0)
2639 tdep
->find_global_pointer
= native_find_global_pointer
;
2641 tdep
->find_global_pointer
= generic_elf_find_global_pointer
;
2643 /* Define the ia64 floating-point format to gdb. */
2644 builtin_type_ia64_ext
=
2645 init_type (TYPE_CODE_FLT
, 128 / 8,
2646 0, "builtin_type_ia64_ext", NULL
);
2647 TYPE_FLOATFORMAT (builtin_type_ia64_ext
) = &floatformat_ia64_ext
;
2649 set_gdbarch_short_bit (gdbarch
, 16);
2650 set_gdbarch_int_bit (gdbarch
, 32);
2651 set_gdbarch_long_bit (gdbarch
, 64);
2652 set_gdbarch_long_long_bit (gdbarch
, 64);
2653 set_gdbarch_float_bit (gdbarch
, 32);
2654 set_gdbarch_double_bit (gdbarch
, 64);
2655 set_gdbarch_long_double_bit (gdbarch
, 128);
2656 set_gdbarch_ptr_bit (gdbarch
, 64);
2658 set_gdbarch_num_regs (gdbarch
, NUM_IA64_RAW_REGS
);
2659 set_gdbarch_num_pseudo_regs (gdbarch
, LAST_PSEUDO_REGNUM
- FIRST_PSEUDO_REGNUM
);
2660 set_gdbarch_sp_regnum (gdbarch
, sp_regnum
);
2661 set_gdbarch_fp0_regnum (gdbarch
, IA64_FR0_REGNUM
);
2663 set_gdbarch_register_name (gdbarch
, ia64_register_name
);
2664 /* FIXME: Following interface should not be needed, however, without it recurse.exp
2665 gets a number of extra failures. */
2666 set_gdbarch_deprecated_register_size (gdbarch
, 8);
2667 set_gdbarch_register_type (gdbarch
, ia64_register_type
);
2669 set_gdbarch_pseudo_register_read (gdbarch
, ia64_pseudo_register_read
);
2670 set_gdbarch_pseudo_register_write (gdbarch
, ia64_pseudo_register_write
);
2671 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, ia64_dwarf_reg_to_regnum
);
2672 set_gdbarch_register_reggroup_p (gdbarch
, ia64_register_reggroup_p
);
2673 set_gdbarch_convert_register_p (gdbarch
, ia64_convert_register_p
);
2674 set_gdbarch_register_to_value (gdbarch
, ia64_register_to_value
);
2675 set_gdbarch_value_to_register (gdbarch
, ia64_value_to_register
);
2677 set_gdbarch_skip_prologue (gdbarch
, ia64_skip_prologue
);
2679 set_gdbarch_use_struct_convention (gdbarch
, ia64_use_struct_convention
);
2680 set_gdbarch_extract_return_value (gdbarch
, ia64_extract_return_value
);
2682 set_gdbarch_store_return_value (gdbarch
, ia64_store_return_value
);
2683 set_gdbarch_extract_struct_value_address (gdbarch
, ia64_extract_struct_value_address
);
2685 set_gdbarch_memory_insert_breakpoint (gdbarch
, ia64_memory_insert_breakpoint
);
2686 set_gdbarch_memory_remove_breakpoint (gdbarch
, ia64_memory_remove_breakpoint
);
2687 set_gdbarch_breakpoint_from_pc (gdbarch
, ia64_breakpoint_from_pc
);
2688 set_gdbarch_read_pc (gdbarch
, ia64_read_pc
);
2689 set_gdbarch_write_pc (gdbarch
, ia64_write_pc
);
2691 /* Settings for calling functions in the inferior. */
2692 set_gdbarch_push_dummy_call (gdbarch
, ia64_push_dummy_call
);
2693 set_gdbarch_frame_align (gdbarch
, ia64_frame_align
);
2694 set_gdbarch_unwind_dummy_id (gdbarch
, ia64_unwind_dummy_id
);
2696 set_gdbarch_unwind_pc (gdbarch
, ia64_unwind_pc
);
2697 frame_unwind_append_sniffer (gdbarch
, ia64_sigtramp_frame_sniffer
);
2698 frame_unwind_append_sniffer (gdbarch
, ia64_frame_sniffer
);
2699 frame_base_set_default (gdbarch
, &ia64_frame_base
);
2701 /* Settings that should be unnecessary. */
2702 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
2704 set_gdbarch_decr_pc_after_break (gdbarch
, 0);
2705 set_gdbarch_function_start_offset (gdbarch
, 0);
2706 set_gdbarch_frame_args_skip (gdbarch
, 0);
2708 set_gdbarch_remote_translate_xfer_address (
2709 gdbarch
, ia64_remote_translate_xfer_address
);
2711 set_gdbarch_print_insn (gdbarch
, ia64_print_insn
);
2712 set_gdbarch_convert_from_func_ptr_addr (gdbarch
, ia64_convert_from_func_ptr_addr
);
2717 extern initialize_file_ftype _initialize_ia64_tdep
; /* -Wmissing-prototypes */
2720 _initialize_ia64_tdep (void)
2722 register_gdbarch_init (bfd_arch_ia64
, ia64_gdbarch_init
);