gdb/lm32-tdep.c

   1 /* Target-dependent code for Lattice Mico32 processor, for GDB.
   2    Contributed by Jon Beniston <jon@beniston.com>
   3
   4    Copyright (C) 2009-2021 Free Software Foundation, Inc.
   5
   6    This file is part of GDB.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the License, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  20
  21 #include "defs.h"
  22 #include "frame.h"
  23 #include "frame-unwind.h"
  24 #include "frame-base.h"
  25 #include "inferior.h"
  26 #include "dis-asm.h"
  27 #include "symfile.h"
  28 #include "remote.h"
  29 #include "gdbcore.h"
  30 #include "gdb/sim-lm32.h"
  31 #include "gdb/callback.h"
  32 #include "gdb/remote-sim.h"
  33 #include "sim-regno.h"
  34 #include "arch-utils.h"
  35 #include "regcache.h"
  36 #include "trad-frame.h"
  37 #include "reggroups.h"
  38 #include "opcodes/lm32-desc.h"
  39 #include <algorithm>
  40
  41 /* Macros to extract fields from an instruction.  */
  42 #define LM32_OPCODE(insn)       ((insn >> 26) & 0x3f)
  43 #define LM32_REG0(insn)         ((insn >> 21) & 0x1f)
  44 #define LM32_REG1(insn)         ((insn >> 16) & 0x1f)
  45 #define LM32_REG2(insn)         ((insn >> 11) & 0x1f)
  46 #define LM32_IMM16(insn)        ((((long)insn & 0xffff) << 16) >> 16)
  47
  48 struct gdbarch_tdep
  49 {
  50   /* gdbarch target dependent data here.  Currently unused for LM32.  */
  51 };
  52
  53 struct lm32_frame_cache
  54 {
  55   /* The frame's base.  Used when constructing a frame ID.  */
  56   CORE_ADDR base;
  57   CORE_ADDR pc;
  58   /* Size of frame.  */
  59   int size;
  60   /* Table indicating the location of each and every register.  */
  61   trad_frame_saved_reg *saved_regs;
  62 };
  63
  64 /* Add the available register groups.  */
  65
  66 static void
  67 lm32_add_reggroups (struct gdbarch *gdbarch)
  68 {
  69   reggroup_add (gdbarch, general_reggroup);
  70   reggroup_add (gdbarch, all_reggroup);
  71   reggroup_add (gdbarch, system_reggroup);
  72 }
  73
  74 /* Return whether a given register is in a given group.  */
  75
  76 static int
  77 lm32_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
  78                           struct reggroup *group)
  79 {
  80   if (group == general_reggroup)
  81     return ((regnum >= SIM_LM32_R0_REGNUM) && (regnum <= SIM_LM32_RA_REGNUM))
  82       || (regnum == SIM_LM32_PC_REGNUM);
  83   else if (group == system_reggroup)
  84     return ((regnum >= SIM_LM32_BA_REGNUM) && (regnum <= SIM_LM32_EA_REGNUM))
  85       || ((regnum >= SIM_LM32_EID_REGNUM) && (regnum <= SIM_LM32_IP_REGNUM));
  86   return default_register_reggroup_p (gdbarch, regnum, group);
  87 }
  88
  89 /* Return a name that corresponds to the given register number.  */
  90
  91 static const char *
  92 lm32_register_name (struct gdbarch *gdbarch, int reg_nr)
  93 {
  94   static const char *register_names[] = {
  95     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
  96     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
  97     "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
  98     "r24", "r25", "gp", "fp", "sp", "ra", "ea", "ba",
  99     "PC", "EID", "EBA", "DEBA", "IE", "IM", "IP"
 100   };
 101
 102   if ((reg_nr < 0) || (reg_nr >= ARRAY_SIZE (register_names)))
 103     return NULL;
 104   else
 105     return register_names[reg_nr];
 106 }
 107
 108 /* Return type of register.  */
 109
 110 static struct type *
 111 lm32_register_type (struct gdbarch *gdbarch, int reg_nr)
 112 {
 113   return builtin_type (gdbarch)->builtin_int32;
 114 }
 115
 116 /* Return non-zero if a register can't be written.  */
 117
 118 static int
 119 lm32_cannot_store_register (struct gdbarch *gdbarch, int regno)
 120 {
 121   return (regno == SIM_LM32_R0_REGNUM) || (regno == SIM_LM32_EID_REGNUM);
 122 }
 123
 124 /* Analyze a function's prologue.  */
 125
 126 static CORE_ADDR
 127 lm32_analyze_prologue (struct gdbarch *gdbarch,
 128                        CORE_ADDR pc, CORE_ADDR limit,
 129                        struct lm32_frame_cache *info)
 130 {
 131   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
 132   unsigned long instruction;
 133
 134   /* Keep reading though instructions, until we come across an instruction
 135      that isn't likely to be part of the prologue.  */
 136   info->size = 0;
 137   for (; pc < limit; pc += 4)
 138     {
 139
 140       /* Read an instruction.  */
 141       instruction = read_memory_integer (pc, 4, byte_order);
 142
 143       if ((LM32_OPCODE (instruction) == OP_SW)
 144           && (LM32_REG0 (instruction) == SIM_LM32_SP_REGNUM))
 145         {
 146           /* Any stack displaced store is likely part of the prologue.
 147              Record that the register is being saved, and the offset
 148              into the stack.  */
 149           info->saved_regs[LM32_REG1 (instruction)].set_addr (LM32_IMM16 (instruction));
 150         }
 151       else if ((LM32_OPCODE (instruction) == OP_ADDI)
 152                && (LM32_REG1 (instruction) == SIM_LM32_SP_REGNUM))
 153         {
 154           /* An add to the SP is likely to be part of the prologue.
 155              Adjust stack size by whatever the instruction adds to the sp.  */
 156           info->size -= LM32_IMM16 (instruction);
 157         }
 158       else if (                 /* add fp,fp,sp */
 159                 ((LM32_OPCODE (instruction) == OP_ADD)
 160                  && (LM32_REG2 (instruction) == SIM_LM32_FP_REGNUM)
 161                  && (LM32_REG0 (instruction) == SIM_LM32_FP_REGNUM)
 162                  && (LM32_REG1 (instruction) == SIM_LM32_SP_REGNUM))
 163                 /* mv fp,imm */
 164                 || ((LM32_OPCODE (instruction) == OP_ADDI)
 165                     && (LM32_REG1 (instruction) == SIM_LM32_FP_REGNUM)
 166                     && (LM32_REG0 (instruction) == SIM_LM32_R0_REGNUM)))
 167         {
 168           /* Likely to be in the prologue for functions that require
 169              a frame pointer.  */
 170         }
 171       else
 172         {
 173           /* Any other instruction is likely not to be part of the
 174              prologue.  */
 175           break;
 176         }
 177     }
 178
 179   return pc;
 180 }
 181
 182 /* Return PC of first non prologue instruction, for the function at the
 183    specified address.  */
 184
 185 static CORE_ADDR
 186 lm32_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
 187 {
 188   CORE_ADDR func_addr, limit_pc;
 189   struct lm32_frame_cache frame_info;
 190   trad_frame_saved_reg saved_regs[SIM_LM32_NUM_REGS];
 191
 192   /* See if we can determine the end of the prologue via the symbol table.
 193      If so, then return either PC, or the PC after the prologue, whichever
 194      is greater.  */
 195   if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
 196     {
 197       CORE_ADDR post_prologue_pc
 198         = skip_prologue_using_sal (gdbarch, func_addr);
 199       if (post_prologue_pc != 0)
 200         return std::max (pc, post_prologue_pc);
 201     }
 202
 203   /* Can't determine prologue from the symbol table, need to examine
 204      instructions.  */
 205
 206   /* Find an upper limit on the function prologue using the debug
 207      information.  If the debug information could not be used to provide
 208      that bound, then use an arbitrary large number as the upper bound.  */
 209   limit_pc = skip_prologue_using_sal (gdbarch, pc);
 210   if (limit_pc == 0)
 211     limit_pc = pc + 100;        /* Magic.  */
 212
 213   frame_info.saved_regs = saved_regs;
 214   return lm32_analyze_prologue (gdbarch, pc, limit_pc, &frame_info);
 215 }
 216
 217 /* Create a breakpoint instruction.  */
 218 constexpr gdb_byte lm32_break_insn[4] = { OP_RAISE << 2, 0, 0, 2 };
 219
 220 typedef BP_MANIPULATION (lm32_break_insn) lm32_breakpoint;
 221
 222
 223 /* Setup registers and stack for faking a call to a function in the
 224    inferior.  */
 225
 226 static CORE_ADDR
 227 lm32_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
 228                       struct regcache *regcache, CORE_ADDR bp_addr,
 229                       int nargs, struct value **args, CORE_ADDR sp,
 230                       function_call_return_method return_method,
 231                       CORE_ADDR struct_addr)
 232 {
 233   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
 234   int first_arg_reg = SIM_LM32_R1_REGNUM;
 235   int num_arg_regs = 8;
 236   int i;
 237
 238   /* Set the return address.  */
 239   regcache_cooked_write_signed (regcache, SIM_LM32_RA_REGNUM, bp_addr);
 240
 241   /* If we're returning a large struct, a pointer to the address to
 242      store it at is passed as a first hidden parameter.  */
 243   if (return_method == return_method_struct)
 244     {
 245       regcache_cooked_write_unsigned (regcache, first_arg_reg, struct_addr);
 246       first_arg_reg++;
 247       num_arg_regs--;
 248       sp -= 4;
 249     }
 250
 251   /* Setup parameters.  */
 252   for (i = 0; i < nargs; i++)
 253     {
 254       struct value *arg = args[i];
 255       struct type *arg_type = check_typedef (value_type (arg));
 256       gdb_byte *contents;
 257       ULONGEST val;
 258
 259       /* Promote small integer types to int.  */
 260       switch (arg_type->code ())
 261         {
 262         case TYPE_CODE_INT:
 263         case TYPE_CODE_BOOL:
 264         case TYPE_CODE_CHAR:
 265         case TYPE_CODE_RANGE:
 266         case TYPE_CODE_ENUM:
 267           if (TYPE_LENGTH (arg_type) < 4)
 268             {
 269               arg_type = builtin_type (gdbarch)->builtin_int32;
 270               arg = value_cast (arg_type, arg);
 271             }
 272           break;
 273         }
 274
 275       /* FIXME: Handle structures.  */
 276
 277       contents = (gdb_byte *) value_contents (arg);
 278       val = extract_unsigned_integer (contents, TYPE_LENGTH (arg_type),
 279                                       byte_order);
 280
 281       /* First num_arg_regs parameters are passed by registers,
 282          and the rest are passed on the stack.  */
 283       if (i < num_arg_regs)
 284         regcache_cooked_write_unsigned (regcache, first_arg_reg + i, val);
 285       else
 286         {
 287           write_memory_unsigned_integer (sp, TYPE_LENGTH (arg_type), byte_order,
 288                                          val);
 289           sp -= 4;
 290         }
 291     }
 292
 293   /* Update stack pointer.  */
 294   regcache_cooked_write_signed (regcache, SIM_LM32_SP_REGNUM, sp);
 295
 296   /* Return adjusted stack pointer.  */
 297   return sp;
 298 }
 299
 300 /* Extract return value after calling a function in the inferior.  */
 301
 302 static void
 303 lm32_extract_return_value (struct type *type, struct regcache *regcache,
 304                            gdb_byte *valbuf)
 305 {
 306   struct gdbarch *gdbarch = regcache->arch ();
 307   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
 308   ULONGEST l;
 309   CORE_ADDR return_buffer;
 310
 311   if (type->code () != TYPE_CODE_STRUCT
 312       && type->code () != TYPE_CODE_UNION
 313       && type->code () != TYPE_CODE_ARRAY && TYPE_LENGTH (type) <= 4)
 314     {
 315       /* Return value is returned in a single register.  */
 316       regcache_cooked_read_unsigned (regcache, SIM_LM32_R1_REGNUM, &l);
 317       store_unsigned_integer (valbuf, TYPE_LENGTH (type), byte_order, l);
 318     }
 319   else if ((type->code () == TYPE_CODE_INT) && (TYPE_LENGTH (type) == 8))
 320     {
 321       /* 64-bit values are returned in a register pair.  */
 322       regcache_cooked_read_unsigned (regcache, SIM_LM32_R1_REGNUM, &l);
 323       memcpy (valbuf, &l, 4);
 324       regcache_cooked_read_unsigned (regcache, SIM_LM32_R2_REGNUM, &l);
 325       memcpy (valbuf + 4, &l, 4);
 326     }
 327   else
 328     {
 329       /* Aggregate types greater than a single register are returned
 330          in memory.  FIXME: Unless they are only 2 regs?.  */
 331       regcache_cooked_read_unsigned (regcache, SIM_LM32_R1_REGNUM, &l);
 332       return_buffer = l;
 333       read_memory (return_buffer, valbuf, TYPE_LENGTH (type));
 334     }
 335 }
 336
 337 /* Write into appropriate registers a function return value of type
 338    TYPE, given in virtual format.  */
 339 static void
 340 lm32_store_return_value (struct type *type, struct regcache *regcache,
 341                          const gdb_byte *valbuf)
 342 {
 343   struct gdbarch *gdbarch = regcache->arch ();
 344   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
 345   ULONGEST val;
 346   int len = TYPE_LENGTH (type);
 347
 348   if (len <= 4)
 349     {
 350       val = extract_unsigned_integer (valbuf, len, byte_order);
 351       regcache_cooked_write_unsigned (regcache, SIM_LM32_R1_REGNUM, val);
 352     }
 353   else if (len <= 8)
 354     {
 355       val = extract_unsigned_integer (valbuf, 4, byte_order);
 356       regcache_cooked_write_unsigned (regcache, SIM_LM32_R1_REGNUM, val);
 357       val = extract_unsigned_integer (valbuf + 4, len - 4, byte_order);
 358       regcache_cooked_write_unsigned (regcache, SIM_LM32_R2_REGNUM, val);
 359     }
 360   else
 361     error (_("lm32_store_return_value: type length too large."));
 362 }
 363
 364 /* Determine whether a functions return value is in a register or memory.  */
 365 static enum return_value_convention
 366 lm32_return_value (struct gdbarch *gdbarch, struct value *function,
 367                    struct type *valtype, struct regcache *regcache,
 368                    gdb_byte *readbuf, const gdb_byte *writebuf)
 369 {
 370   enum type_code code = valtype->code ();
 371
 372   if (code == TYPE_CODE_STRUCT
 373       || code == TYPE_CODE_UNION
 374       || code == TYPE_CODE_ARRAY || TYPE_LENGTH (valtype) > 8)
 375     return RETURN_VALUE_STRUCT_CONVENTION;
 376
 377   if (readbuf)
 378     lm32_extract_return_value (valtype, regcache, readbuf);
 379   if (writebuf)
 380     lm32_store_return_value (valtype, regcache, writebuf);
 381
 382   return RETURN_VALUE_REGISTER_CONVENTION;
 383 }
 384
 385 /* Put here the code to store, into fi->saved_regs, the addresses of
 386    the saved registers of frame described by FRAME_INFO.  This
 387    includes special registers such as pc and fp saved in special ways
 388    in the stack frame.  sp is even more special: the address we return
 389    for it IS the sp for the next frame.  */
 390
 391 static struct lm32_frame_cache *
 392 lm32_frame_cache (struct frame_info *this_frame, void **this_prologue_cache)
 393 {
 394   CORE_ADDR current_pc;
 395   ULONGEST prev_sp;
 396   ULONGEST this_base;
 397   struct lm32_frame_cache *info;
 398   int i;
 399
 400   if ((*this_prologue_cache))
 401     return (struct lm32_frame_cache *) (*this_prologue_cache);
 402
 403   info = FRAME_OBSTACK_ZALLOC (struct lm32_frame_cache);
 404   (*this_prologue_cache) = info;
 405   info->saved_regs = trad_frame_alloc_saved_regs (this_frame);
 406
 407   info->pc = get_frame_func (this_frame);
 408   current_pc = get_frame_pc (this_frame);
 409   lm32_analyze_prologue (get_frame_arch (this_frame),
 410                          info->pc, current_pc, info);
 411
 412   /* Compute the frame's base, and the previous frame's SP.  */
 413   this_base = get_frame_register_unsigned (this_frame, SIM_LM32_SP_REGNUM);
 414   prev_sp = this_base + info->size;
 415   info->base = this_base;
 416
 417   /* Convert callee save offsets into addresses.  */
 418   for (i = 0; i < gdbarch_num_regs (get_frame_arch (this_frame)) - 1; i++)
 419     {
 420       if (info->saved_regs[i].is_addr ())
 421         info->saved_regs[i].set_addr (this_base + info->saved_regs[i].addr ());
 422     }
 423
 424   /* The call instruction moves the caller's PC in the callee's RA register.
 425      Since this is an unwind, do the reverse.  Copy the location of RA register
 426      into PC (the address / regnum) so that a request for PC will be
 427      converted into a request for the RA register.  */
 428   info->saved_regs[SIM_LM32_PC_REGNUM] = info->saved_regs[SIM_LM32_RA_REGNUM];
 429
 430   /* The previous frame's SP needed to be computed.  Save the computed
 431      value.  */
 432   info->saved_regs[SIM_LM32_SP_REGNUM].set_value (prev_sp);
 433
 434   return info;
 435 }
 436
 437 static void
 438 lm32_frame_this_id (struct frame_info *this_frame, void **this_cache,
 439                     struct frame_id *this_id)
 440 {
 441   struct lm32_frame_cache *cache = lm32_frame_cache (this_frame, this_cache);
 442
 443   /* This marks the outermost frame.  */
 444   if (cache->base == 0)
 445     return;
 446
 447   (*this_id) = frame_id_build (cache->base, cache->pc);
 448 }
 449
 450 static struct value *
 451 lm32_frame_prev_register (struct frame_info *this_frame,
 452                           void **this_prologue_cache, int regnum)
 453 {
 454   struct lm32_frame_cache *info;
 455
 456   info = lm32_frame_cache (this_frame, this_prologue_cache);
 457   return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
 458 }
 459
 460 static const struct frame_unwind lm32_frame_unwind = {
 461   NORMAL_FRAME,
 462   default_frame_unwind_stop_reason,
 463   lm32_frame_this_id,
 464   lm32_frame_prev_register,
 465   NULL,
 466   default_frame_sniffer
 467 };
 468
 469 static CORE_ADDR
 470 lm32_frame_base_address (struct frame_info *this_frame, void **this_cache)
 471 {
 472   struct lm32_frame_cache *info = lm32_frame_cache (this_frame, this_cache);
 473
 474   return info->base;
 475 }
 476
 477 static const struct frame_base lm32_frame_base = {
 478   &lm32_frame_unwind,
 479   lm32_frame_base_address,
 480   lm32_frame_base_address,
 481   lm32_frame_base_address
 482 };
 483
 484 static CORE_ADDR
 485 lm32_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
 486 {
 487   /* Align to the size of an instruction (so that they can safely be
 488      pushed onto the stack.  */
 489   return sp & ~3;
 490 }
 491
 492 static struct gdbarch *
 493 lm32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
 494 {
 495   struct gdbarch *gdbarch;
 496   struct gdbarch_tdep *tdep;
 497
 498   /* If there is already a candidate, use it.  */
 499   arches = gdbarch_list_lookup_by_info (arches, &info);
 500   if (arches != NULL)
 501     return arches->gdbarch;
 502
 503   /* None found, create a new architecture from the information provided.  */
 504   tdep = XCNEW (struct gdbarch_tdep);
 505   gdbarch = gdbarch_alloc (&info, tdep);
 506
 507   /* Type sizes.  */
 508   set_gdbarch_short_bit (gdbarch, 16);
 509   set_gdbarch_int_bit (gdbarch, 32);
 510   set_gdbarch_long_bit (gdbarch, 32);
 511   set_gdbarch_long_long_bit (gdbarch, 64);
 512   set_gdbarch_float_bit (gdbarch, 32);
 513   set_gdbarch_double_bit (gdbarch, 64);
 514   set_gdbarch_long_double_bit (gdbarch, 64);
 515   set_gdbarch_ptr_bit (gdbarch, 32);
 516
 517   /* Register info.  */
 518   set_gdbarch_num_regs (gdbarch, SIM_LM32_NUM_REGS);
 519   set_gdbarch_sp_regnum (gdbarch, SIM_LM32_SP_REGNUM);
 520   set_gdbarch_pc_regnum (gdbarch, SIM_LM32_PC_REGNUM);
 521   set_gdbarch_register_name (gdbarch, lm32_register_name);
 522   set_gdbarch_register_type (gdbarch, lm32_register_type);
 523   set_gdbarch_cannot_store_register (gdbarch, lm32_cannot_store_register);
 524
 525   /* Frame info.  */
 526   set_gdbarch_skip_prologue (gdbarch, lm32_skip_prologue);
 527   set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
 528   set_gdbarch_decr_pc_after_break (gdbarch, 0);
 529   set_gdbarch_frame_args_skip (gdbarch, 0);
 530
 531   /* Frame unwinding.  */
 532   set_gdbarch_frame_align (gdbarch, lm32_frame_align);
 533   frame_base_set_default (gdbarch, &lm32_frame_base);
 534   frame_unwind_append_unwinder (gdbarch, &lm32_frame_unwind);
 535
 536   /* Breakpoints.  */
 537   set_gdbarch_breakpoint_kind_from_pc (gdbarch, lm32_breakpoint::kind_from_pc);
 538   set_gdbarch_sw_breakpoint_from_kind (gdbarch, lm32_breakpoint::bp_from_kind);
 539   set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
 540
 541   /* Calling functions in the inferior.  */
 542   set_gdbarch_push_dummy_call (gdbarch, lm32_push_dummy_call);
 543   set_gdbarch_return_value (gdbarch, lm32_return_value);
 544
 545   lm32_add_reggroups (gdbarch);
 546   set_gdbarch_register_reggroup_p (gdbarch, lm32_register_reggroup_p);
 547
 548   return gdbarch;
 549 }
 550
 551 void _initialize_lm32_tdep ();
 552 void
 553 _initialize_lm32_tdep ()
 554 {
 555   register_gdbarch_init (bfd_arch_lm32, lm32_gdbarch_init);
 556 }