1 /* Target-dependent code for Lattice Mico32 processor, for GDB.
2 Contributed by Jon Beniston <jon@beniston.com>
4 Copyright (C) 2009-2016 Free Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "frame-unwind.h"
24 #include "frame-base.h"
30 #include "gdb/sim-lm32.h"
31 #include "gdb/callback.h"
32 #include "gdb/remote-sim.h"
33 #include "sim-regno.h"
34 #include "arch-utils.h"
36 #include "trad-frame.h"
37 #include "reggroups.h"
38 #include "opcodes/lm32-desc.h"
41 /* Macros to extract fields from an instruction. */
42 #define LM32_OPCODE(insn) ((insn >> 26) & 0x3f)
43 #define LM32_REG0(insn) ((insn >> 21) & 0x1f)
44 #define LM32_REG1(insn) ((insn >> 16) & 0x1f)
45 #define LM32_REG2(insn) ((insn >> 11) & 0x1f)
46 #define LM32_IMM16(insn) ((((long)insn & 0xffff) << 16) >> 16)
50 /* gdbarch target dependent data here. Currently unused for LM32. */
53 struct lm32_frame_cache
55 /* The frame's base. Used when constructing a frame ID. */
60 /* Table indicating the location of each and every register. */
61 struct trad_frame_saved_reg
*saved_regs
;
64 /* Add the available register groups. */
67 lm32_add_reggroups (struct gdbarch
*gdbarch
)
69 reggroup_add (gdbarch
, general_reggroup
);
70 reggroup_add (gdbarch
, all_reggroup
);
71 reggroup_add (gdbarch
, system_reggroup
);
74 /* Return whether a given register is in a given group. */
77 lm32_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
78 struct reggroup
*group
)
80 if (group
== general_reggroup
)
81 return ((regnum
>= SIM_LM32_R0_REGNUM
) && (regnum
<= SIM_LM32_RA_REGNUM
))
82 || (regnum
== SIM_LM32_PC_REGNUM
);
83 else if (group
== system_reggroup
)
84 return ((regnum
>= SIM_LM32_EA_REGNUM
) && (regnum
<= SIM_LM32_BA_REGNUM
))
85 || ((regnum
>= SIM_LM32_EID_REGNUM
) && (regnum
<= SIM_LM32_IP_REGNUM
));
86 return default_register_reggroup_p (gdbarch
, regnum
, group
);
89 /* Return a name that corresponds to the given register number. */
92 lm32_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
94 static char *register_names
[] = {
95 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
96 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
97 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
98 "r24", "r25", "gp", "fp", "sp", "ra", "ea", "ba",
99 "PC", "EID", "EBA", "DEBA", "IE", "IM", "IP"
102 if ((reg_nr
< 0) || (reg_nr
>= ARRAY_SIZE (register_names
)))
105 return register_names
[reg_nr
];
108 /* Return type of register. */
111 lm32_register_type (struct gdbarch
*gdbarch
, int reg_nr
)
113 return builtin_type (gdbarch
)->builtin_int32
;
116 /* Return non-zero if a register can't be written. */
119 lm32_cannot_store_register (struct gdbarch
*gdbarch
, int regno
)
121 return (regno
== SIM_LM32_R0_REGNUM
) || (regno
== SIM_LM32_EID_REGNUM
);
124 /* Analyze a function's prologue. */
127 lm32_analyze_prologue (struct gdbarch
*gdbarch
,
128 CORE_ADDR pc
, CORE_ADDR limit
,
129 struct lm32_frame_cache
*info
)
131 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
132 unsigned long instruction
;
134 /* Keep reading though instructions, until we come across an instruction
135 that isn't likely to be part of the prologue. */
137 for (; pc
< limit
; pc
+= 4)
140 /* Read an instruction. */
141 instruction
= read_memory_integer (pc
, 4, byte_order
);
143 if ((LM32_OPCODE (instruction
) == OP_SW
)
144 && (LM32_REG0 (instruction
) == SIM_LM32_SP_REGNUM
))
146 /* Any stack displaced store is likely part of the prologue.
147 Record that the register is being saved, and the offset
149 info
->saved_regs
[LM32_REG1 (instruction
)].addr
=
150 LM32_IMM16 (instruction
);
152 else if ((LM32_OPCODE (instruction
) == OP_ADDI
)
153 && (LM32_REG1 (instruction
) == SIM_LM32_SP_REGNUM
))
155 /* An add to the SP is likely to be part of the prologue.
156 Adjust stack size by whatever the instruction adds to the sp. */
157 info
->size
-= LM32_IMM16 (instruction
);
159 else if ( /* add fp,fp,sp */
160 ((LM32_OPCODE (instruction
) == OP_ADD
)
161 && (LM32_REG2 (instruction
) == SIM_LM32_FP_REGNUM
)
162 && (LM32_REG0 (instruction
) == SIM_LM32_FP_REGNUM
)
163 && (LM32_REG1 (instruction
) == SIM_LM32_SP_REGNUM
))
165 || ((LM32_OPCODE (instruction
) == OP_ADDI
)
166 && (LM32_REG1 (instruction
) == SIM_LM32_FP_REGNUM
)
167 && (LM32_REG0 (instruction
) == SIM_LM32_R0_REGNUM
)))
169 /* Likely to be in the prologue for functions that require
174 /* Any other instruction is likely not to be part of the
183 /* Return PC of first non prologue instruction, for the function at the
184 specified address. */
187 lm32_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
189 CORE_ADDR func_addr
, limit_pc
;
190 struct lm32_frame_cache frame_info
;
191 struct trad_frame_saved_reg saved_regs
[SIM_LM32_NUM_REGS
];
193 /* See if we can determine the end of the prologue via the symbol table.
194 If so, then return either PC, or the PC after the prologue, whichever
196 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
198 CORE_ADDR post_prologue_pc
199 = skip_prologue_using_sal (gdbarch
, func_addr
);
200 if (post_prologue_pc
!= 0)
201 return std::max (pc
, post_prologue_pc
);
204 /* Can't determine prologue from the symbol table, need to examine
207 /* Find an upper limit on the function prologue using the debug
208 information. If the debug information could not be used to provide
209 that bound, then use an arbitrary large number as the upper bound. */
210 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
212 limit_pc
= pc
+ 100; /* Magic. */
214 frame_info
.saved_regs
= saved_regs
;
215 return lm32_analyze_prologue (gdbarch
, pc
, limit_pc
, &frame_info
);
218 /* Create a breakpoint instruction. */
220 static const gdb_byte
*
221 lm32_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
,
224 static const gdb_byte breakpoint
[4] = { OP_RAISE
<< 2, 0, 0, 2 };
226 *lenptr
= sizeof (breakpoint
);
230 /* Setup registers and stack for faking a call to a function in the
234 lm32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
235 struct regcache
*regcache
, CORE_ADDR bp_addr
,
236 int nargs
, struct value
**args
, CORE_ADDR sp
,
237 int struct_return
, CORE_ADDR struct_addr
)
239 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
240 int first_arg_reg
= SIM_LM32_R1_REGNUM
;
241 int num_arg_regs
= 8;
244 /* Set the return address. */
245 regcache_cooked_write_signed (regcache
, SIM_LM32_RA_REGNUM
, bp_addr
);
247 /* If we're returning a large struct, a pointer to the address to
248 store it at is passed as a first hidden parameter. */
251 regcache_cooked_write_unsigned (regcache
, first_arg_reg
, struct_addr
);
257 /* Setup parameters. */
258 for (i
= 0; i
< nargs
; i
++)
260 struct value
*arg
= args
[i
];
261 struct type
*arg_type
= check_typedef (value_type (arg
));
265 /* Promote small integer types to int. */
266 switch (TYPE_CODE (arg_type
))
271 case TYPE_CODE_RANGE
:
273 if (TYPE_LENGTH (arg_type
) < 4)
275 arg_type
= builtin_type (gdbarch
)->builtin_int32
;
276 arg
= value_cast (arg_type
, arg
);
281 /* FIXME: Handle structures. */
283 contents
= (gdb_byte
*) value_contents (arg
);
284 val
= extract_unsigned_integer (contents
, TYPE_LENGTH (arg_type
),
287 /* First num_arg_regs parameters are passed by registers,
288 and the rest are passed on the stack. */
289 if (i
< num_arg_regs
)
290 regcache_cooked_write_unsigned (regcache
, first_arg_reg
+ i
, val
);
293 write_memory_unsigned_integer (sp
, TYPE_LENGTH (arg_type
), byte_order
,
299 /* Update stack pointer. */
300 regcache_cooked_write_signed (regcache
, SIM_LM32_SP_REGNUM
, sp
);
302 /* Return adjusted stack pointer. */
306 /* Extract return value after calling a function in the inferior. */
309 lm32_extract_return_value (struct type
*type
, struct regcache
*regcache
,
312 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
313 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
315 CORE_ADDR return_buffer
;
317 if (TYPE_CODE (type
) != TYPE_CODE_STRUCT
318 && TYPE_CODE (type
) != TYPE_CODE_UNION
319 && TYPE_CODE (type
) != TYPE_CODE_ARRAY
&& TYPE_LENGTH (type
) <= 4)
321 /* Return value is returned in a single register. */
322 regcache_cooked_read_unsigned (regcache
, SIM_LM32_R1_REGNUM
, &l
);
323 store_unsigned_integer (valbuf
, TYPE_LENGTH (type
), byte_order
, l
);
325 else if ((TYPE_CODE (type
) == TYPE_CODE_INT
) && (TYPE_LENGTH (type
) == 8))
327 /* 64-bit values are returned in a register pair. */
328 regcache_cooked_read_unsigned (regcache
, SIM_LM32_R1_REGNUM
, &l
);
329 memcpy (valbuf
, &l
, 4);
330 regcache_cooked_read_unsigned (regcache
, SIM_LM32_R2_REGNUM
, &l
);
331 memcpy (valbuf
+ 4, &l
, 4);
335 /* Aggregate types greater than a single register are returned
336 in memory. FIXME: Unless they are only 2 regs?. */
337 regcache_cooked_read_unsigned (regcache
, SIM_LM32_R1_REGNUM
, &l
);
339 read_memory (return_buffer
, valbuf
, TYPE_LENGTH (type
));
343 /* Write into appropriate registers a function return value of type
344 TYPE, given in virtual format. */
346 lm32_store_return_value (struct type
*type
, struct regcache
*regcache
,
347 const gdb_byte
*valbuf
)
349 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
350 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
352 int len
= TYPE_LENGTH (type
);
356 val
= extract_unsigned_integer (valbuf
, len
, byte_order
);
357 regcache_cooked_write_unsigned (regcache
, SIM_LM32_R1_REGNUM
, val
);
361 val
= extract_unsigned_integer (valbuf
, 4, byte_order
);
362 regcache_cooked_write_unsigned (regcache
, SIM_LM32_R1_REGNUM
, val
);
363 val
= extract_unsigned_integer (valbuf
+ 4, len
- 4, byte_order
);
364 regcache_cooked_write_unsigned (regcache
, SIM_LM32_R2_REGNUM
, val
);
367 error (_("lm32_store_return_value: type length too large."));
370 /* Determine whether a functions return value is in a register or memory. */
371 static enum return_value_convention
372 lm32_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
373 struct type
*valtype
, struct regcache
*regcache
,
374 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
376 enum type_code code
= TYPE_CODE (valtype
);
378 if (code
== TYPE_CODE_STRUCT
379 || code
== TYPE_CODE_UNION
380 || code
== TYPE_CODE_ARRAY
|| TYPE_LENGTH (valtype
) > 8)
381 return RETURN_VALUE_STRUCT_CONVENTION
;
384 lm32_extract_return_value (valtype
, regcache
, readbuf
);
386 lm32_store_return_value (valtype
, regcache
, writebuf
);
388 return RETURN_VALUE_REGISTER_CONVENTION
;
392 lm32_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
394 return frame_unwind_register_unsigned (next_frame
, SIM_LM32_PC_REGNUM
);
398 lm32_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
400 return frame_unwind_register_unsigned (next_frame
, SIM_LM32_SP_REGNUM
);
403 static struct frame_id
404 lm32_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
406 CORE_ADDR sp
= get_frame_register_unsigned (this_frame
, SIM_LM32_SP_REGNUM
);
408 return frame_id_build (sp
, get_frame_pc (this_frame
));
411 /* Put here the code to store, into fi->saved_regs, the addresses of
412 the saved registers of frame described by FRAME_INFO. This
413 includes special registers such as pc and fp saved in special ways
414 in the stack frame. sp is even more special: the address we return
415 for it IS the sp for the next frame. */
417 static struct lm32_frame_cache
*
418 lm32_frame_cache (struct frame_info
*this_frame
, void **this_prologue_cache
)
420 CORE_ADDR current_pc
;
423 struct lm32_frame_cache
*info
;
426 if ((*this_prologue_cache
))
427 return (struct lm32_frame_cache
*) (*this_prologue_cache
);
429 info
= FRAME_OBSTACK_ZALLOC (struct lm32_frame_cache
);
430 (*this_prologue_cache
) = info
;
431 info
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
433 info
->pc
= get_frame_func (this_frame
);
434 current_pc
= get_frame_pc (this_frame
);
435 lm32_analyze_prologue (get_frame_arch (this_frame
),
436 info
->pc
, current_pc
, info
);
438 /* Compute the frame's base, and the previous frame's SP. */
439 this_base
= get_frame_register_unsigned (this_frame
, SIM_LM32_SP_REGNUM
);
440 prev_sp
= this_base
+ info
->size
;
441 info
->base
= this_base
;
443 /* Convert callee save offsets into addresses. */
444 for (i
= 0; i
< gdbarch_num_regs (get_frame_arch (this_frame
)) - 1; i
++)
446 if (trad_frame_addr_p (info
->saved_regs
, i
))
447 info
->saved_regs
[i
].addr
= this_base
+ info
->saved_regs
[i
].addr
;
450 /* The call instruction moves the caller's PC in the callee's RA register.
451 Since this is an unwind, do the reverse. Copy the location of RA register
452 into PC (the address / regnum) so that a request for PC will be
453 converted into a request for the RA register. */
454 info
->saved_regs
[SIM_LM32_PC_REGNUM
] = info
->saved_regs
[SIM_LM32_RA_REGNUM
];
456 /* The previous frame's SP needed to be computed. Save the computed
458 trad_frame_set_value (info
->saved_regs
, SIM_LM32_SP_REGNUM
, prev_sp
);
464 lm32_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
465 struct frame_id
*this_id
)
467 struct lm32_frame_cache
*cache
= lm32_frame_cache (this_frame
, this_cache
);
469 /* This marks the outermost frame. */
470 if (cache
->base
== 0)
473 (*this_id
) = frame_id_build (cache
->base
, cache
->pc
);
476 static struct value
*
477 lm32_frame_prev_register (struct frame_info
*this_frame
,
478 void **this_prologue_cache
, int regnum
)
480 struct lm32_frame_cache
*info
;
482 info
= lm32_frame_cache (this_frame
, this_prologue_cache
);
483 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
486 static const struct frame_unwind lm32_frame_unwind
= {
488 default_frame_unwind_stop_reason
,
490 lm32_frame_prev_register
,
492 default_frame_sniffer
496 lm32_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
498 struct lm32_frame_cache
*info
= lm32_frame_cache (this_frame
, this_cache
);
503 static const struct frame_base lm32_frame_base
= {
505 lm32_frame_base_address
,
506 lm32_frame_base_address
,
507 lm32_frame_base_address
511 lm32_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
513 /* Align to the size of an instruction (so that they can safely be
514 pushed onto the stack. */
518 static struct gdbarch
*
519 lm32_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
521 struct gdbarch
*gdbarch
;
522 struct gdbarch_tdep
*tdep
;
524 /* If there is already a candidate, use it. */
525 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
527 return arches
->gdbarch
;
529 /* None found, create a new architecture from the information provided. */
530 tdep
= XNEW (struct gdbarch_tdep
);
531 gdbarch
= gdbarch_alloc (&info
, tdep
);
534 set_gdbarch_short_bit (gdbarch
, 16);
535 set_gdbarch_int_bit (gdbarch
, 32);
536 set_gdbarch_long_bit (gdbarch
, 32);
537 set_gdbarch_long_long_bit (gdbarch
, 64);
538 set_gdbarch_float_bit (gdbarch
, 32);
539 set_gdbarch_double_bit (gdbarch
, 64);
540 set_gdbarch_long_double_bit (gdbarch
, 64);
541 set_gdbarch_ptr_bit (gdbarch
, 32);
544 set_gdbarch_num_regs (gdbarch
, SIM_LM32_NUM_REGS
);
545 set_gdbarch_sp_regnum (gdbarch
, SIM_LM32_SP_REGNUM
);
546 set_gdbarch_pc_regnum (gdbarch
, SIM_LM32_PC_REGNUM
);
547 set_gdbarch_register_name (gdbarch
, lm32_register_name
);
548 set_gdbarch_register_type (gdbarch
, lm32_register_type
);
549 set_gdbarch_cannot_store_register (gdbarch
, lm32_cannot_store_register
);
552 set_gdbarch_skip_prologue (gdbarch
, lm32_skip_prologue
);
553 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
554 set_gdbarch_decr_pc_after_break (gdbarch
, 0);
555 set_gdbarch_frame_args_skip (gdbarch
, 0);
557 /* Frame unwinding. */
558 set_gdbarch_frame_align (gdbarch
, lm32_frame_align
);
559 frame_base_set_default (gdbarch
, &lm32_frame_base
);
560 set_gdbarch_unwind_pc (gdbarch
, lm32_unwind_pc
);
561 set_gdbarch_unwind_sp (gdbarch
, lm32_unwind_sp
);
562 set_gdbarch_dummy_id (gdbarch
, lm32_dummy_id
);
563 frame_unwind_append_unwinder (gdbarch
, &lm32_frame_unwind
);
566 set_gdbarch_breakpoint_from_pc (gdbarch
, lm32_breakpoint_from_pc
);
567 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
569 /* Calling functions in the inferior. */
570 set_gdbarch_push_dummy_call (gdbarch
, lm32_push_dummy_call
);
571 set_gdbarch_return_value (gdbarch
, lm32_return_value
);
573 /* Instruction disassembler. */
574 set_gdbarch_print_insn (gdbarch
, print_insn_lm32
);
576 lm32_add_reggroups (gdbarch
);
577 set_gdbarch_register_reggroup_p (gdbarch
, lm32_register_reggroup_p
);
582 /* -Wmissing-prototypes */
583 extern initialize_file_ftype _initialize_lm32_tdep
;
586 _initialize_lm32_tdep (void)
588 register_gdbarch_init (bfd_arch_lm32
, lm32_gdbarch_init
);