1 /* Native-dependent code for GNU/Linux on MIPS processors.
3 Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
24 #include "gdb_assert.h"
26 #include "mips-tdep.h"
29 #include "linux-nat.h"
30 #include "mips-linux-tdep.h"
31 #include "target-descriptions.h"
33 #include "gdb_proc_service.h"
37 #include <sys/ptrace.h>
39 #include "features/mips-linux.c"
40 #include "features/mips64-linux.c"
42 #ifndef PTRACE_GET_THREAD_AREA
43 #define PTRACE_GET_THREAD_AREA 25
46 /* Assume that we have PTRACE_GETREGS et al. support. If we do not,
47 we'll clear this and use PTRACE_PEEKUSER instead. */
48 static int have_ptrace_regsets
= 1;
50 /* Whether or not to print the mirrored debug registers. */
52 static int maint_show_dr
;
54 /* Saved function pointers to fetch and store a single register using
55 PTRACE_PEEKUSER and PTRACE_POKEUSER. */
57 static void (*super_fetch_registers
) (struct target_ops
*,
58 struct regcache
*, int);
59 static void (*super_store_registers
) (struct target_ops
*,
60 struct regcache
*, int);
62 static void (*super_close
) (int);
64 /* Map gdb internal register number to ptrace ``address''.
65 These ``addresses'' are normally defined in <asm/ptrace.h>.
67 ptrace does not provide a way to read (or set) MIPS_PS_REGNUM,
68 and there's no point in reading or setting MIPS_ZERO_REGNUM.
69 We also can not set BADVADDR, CAUSE, or FCRIR via ptrace(). */
72 mips_linux_register_addr (struct gdbarch
*gdbarch
, int regno
, int store
)
76 if (regno
< 0 || regno
>= gdbarch_num_regs (gdbarch
))
77 error (_("Bogon register number %d."), regno
);
79 if (regno
> MIPS_ZERO_REGNUM
&& regno
< MIPS_ZERO_REGNUM
+ 32)
81 else if ((regno
>= mips_regnum (gdbarch
)->fp0
)
82 && (regno
< mips_regnum (gdbarch
)->fp0
+ 32))
83 regaddr
= FPR_BASE
+ (regno
- mips_regnum (gdbarch
)->fp0
);
84 else if (regno
== mips_regnum (gdbarch
)->pc
)
86 else if (regno
== mips_regnum (gdbarch
)->cause
)
87 regaddr
= store
? (CORE_ADDR
) -1 : CAUSE
;
88 else if (regno
== mips_regnum (gdbarch
)->badvaddr
)
89 regaddr
= store
? (CORE_ADDR
) -1 : BADVADDR
;
90 else if (regno
== mips_regnum (gdbarch
)->lo
)
92 else if (regno
== mips_regnum (gdbarch
)->hi
)
94 else if (regno
== mips_regnum (gdbarch
)->fp_control_status
)
96 else if (regno
== mips_regnum (gdbarch
)->fp_implementation_revision
)
97 regaddr
= store
? (CORE_ADDR
) -1 : FPC_EIR
;
98 else if (mips_linux_restart_reg_p (gdbarch
) && regno
== MIPS_RESTART_REGNUM
)
101 regaddr
= (CORE_ADDR
) -1;
107 mips64_linux_register_addr (struct gdbarch
*gdbarch
, int regno
, int store
)
111 if (regno
< 0 || regno
>= gdbarch_num_regs (gdbarch
))
112 error (_("Bogon register number %d."), regno
);
114 if (regno
> MIPS_ZERO_REGNUM
&& regno
< MIPS_ZERO_REGNUM
+ 32)
116 else if ((regno
>= mips_regnum (gdbarch
)->fp0
)
117 && (regno
< mips_regnum (gdbarch
)->fp0
+ 32))
118 regaddr
= MIPS64_FPR_BASE
+ (regno
- gdbarch_fp0_regnum (gdbarch
));
119 else if (regno
== mips_regnum (gdbarch
)->pc
)
121 else if (regno
== mips_regnum (gdbarch
)->cause
)
122 regaddr
= store
? (CORE_ADDR
) -1 : MIPS64_CAUSE
;
123 else if (regno
== mips_regnum (gdbarch
)->badvaddr
)
124 regaddr
= store
? (CORE_ADDR
) -1 : MIPS64_BADVADDR
;
125 else if (regno
== mips_regnum (gdbarch
)->lo
)
126 regaddr
= MIPS64_MMLO
;
127 else if (regno
== mips_regnum (gdbarch
)->hi
)
128 regaddr
= MIPS64_MMHI
;
129 else if (regno
== mips_regnum (gdbarch
)->fp_control_status
)
130 regaddr
= MIPS64_FPC_CSR
;
131 else if (regno
== mips_regnum (gdbarch
)->fp_implementation_revision
)
132 regaddr
= store
? (CORE_ADDR
) -1 : MIPS64_FPC_EIR
;
133 else if (mips_linux_restart_reg_p (gdbarch
) && regno
== MIPS_RESTART_REGNUM
)
136 regaddr
= (CORE_ADDR
) -1;
141 /* Fetch the thread-local storage pointer for libthread_db. */
144 ps_get_thread_area (const struct ps_prochandle
*ph
,
145 lwpid_t lwpid
, int idx
, void **base
)
147 if (ptrace (PTRACE_GET_THREAD_AREA
, lwpid
, NULL
, base
) != 0)
150 /* IDX is the bias from the thread pointer to the beginning of the
151 thread descriptor. It has to be subtracted due to implementation
152 quirks in libthread_db. */
153 *base
= (void *) ((char *)*base
- idx
);
158 /* Wrapper functions. These are only used by libthread_db. */
161 supply_gregset (struct regcache
*regcache
, const gdb_gregset_t
*gregsetp
)
163 if (mips_isa_regsize (get_regcache_arch (regcache
)) == 4)
164 mips_supply_gregset (regcache
, (const mips_elf_gregset_t
*) gregsetp
);
166 mips64_supply_gregset (regcache
, (const mips64_elf_gregset_t
*) gregsetp
);
170 fill_gregset (const struct regcache
*regcache
,
171 gdb_gregset_t
*gregsetp
, int regno
)
173 if (mips_isa_regsize (get_regcache_arch (regcache
)) == 4)
174 mips_fill_gregset (regcache
, (mips_elf_gregset_t
*) gregsetp
, regno
);
176 mips64_fill_gregset (regcache
, (mips64_elf_gregset_t
*) gregsetp
, regno
);
180 supply_fpregset (struct regcache
*regcache
, const gdb_fpregset_t
*fpregsetp
)
182 if (mips_isa_regsize (get_regcache_arch (regcache
)) == 4)
183 mips_supply_fpregset (regcache
, (const mips_elf_fpregset_t
*) fpregsetp
);
185 mips64_supply_fpregset (regcache
, (const mips64_elf_fpregset_t
*) fpregsetp
);
189 fill_fpregset (const struct regcache
*regcache
,
190 gdb_fpregset_t
*fpregsetp
, int regno
)
192 if (mips_isa_regsize (get_regcache_arch (regcache
)) == 4)
193 mips_fill_fpregset (regcache
, (mips_elf_fpregset_t
*) fpregsetp
, regno
);
195 mips64_fill_fpregset (regcache
, (mips64_elf_fpregset_t
*) fpregsetp
, regno
);
199 /* Fetch REGNO (or all registers if REGNO == -1) from the target
200 using PTRACE_GETREGS et al. */
203 mips64_linux_regsets_fetch_registers (struct regcache
*regcache
, int regno
)
205 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
209 if (regno
>= mips_regnum (gdbarch
)->fp0
210 && regno
<= mips_regnum (gdbarch
)->fp0
+ 32)
212 else if (regno
== mips_regnum (gdbarch
)->fp_control_status
)
214 else if (regno
== mips_regnum (gdbarch
)->fp_implementation_revision
)
219 tid
= ptid_get_lwp (inferior_ptid
);
221 tid
= ptid_get_pid (inferior_ptid
);
223 if (regno
== -1 || !is_fp
)
225 mips64_elf_gregset_t regs
;
227 if (ptrace (PTRACE_GETREGS
, tid
, 0L, (PTRACE_TYPE_ARG3
) ®s
) == -1)
231 have_ptrace_regsets
= 0;
234 perror_with_name (_("Couldn't get registers"));
237 mips64_supply_gregset (regcache
,
238 (const mips64_elf_gregset_t
*) ®s
);
241 if (regno
== -1 || is_fp
)
243 mips64_elf_fpregset_t fp_regs
;
245 if (ptrace (PTRACE_GETFPREGS
, tid
, 0L,
246 (PTRACE_TYPE_ARG3
) &fp_regs
) == -1)
250 have_ptrace_regsets
= 0;
253 perror_with_name (_("Couldn't get FP registers"));
256 mips64_supply_fpregset (regcache
,
257 (const mips64_elf_fpregset_t
*) &fp_regs
);
261 /* Store REGNO (or all registers if REGNO == -1) to the target
262 using PTRACE_SETREGS et al. */
265 mips64_linux_regsets_store_registers (const struct regcache
*regcache
, int regno
)
267 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
271 if (regno
>= mips_regnum (gdbarch
)->fp0
272 && regno
<= mips_regnum (gdbarch
)->fp0
+ 32)
274 else if (regno
== mips_regnum (gdbarch
)->fp_control_status
)
276 else if (regno
== mips_regnum (gdbarch
)->fp_implementation_revision
)
281 tid
= ptid_get_lwp (inferior_ptid
);
283 tid
= ptid_get_pid (inferior_ptid
);
285 if (regno
== -1 || !is_fp
)
287 mips64_elf_gregset_t regs
;
289 if (ptrace (PTRACE_GETREGS
, tid
, 0L, (PTRACE_TYPE_ARG3
) ®s
) == -1)
290 perror_with_name (_("Couldn't get registers"));
292 mips64_fill_gregset (regcache
, ®s
, regno
);
294 if (ptrace (PTRACE_SETREGS
, tid
, 0L, (PTRACE_TYPE_ARG3
) ®s
) == -1)
295 perror_with_name (_("Couldn't set registers"));
298 if (regno
== -1 || is_fp
)
300 mips64_elf_fpregset_t fp_regs
;
302 if (ptrace (PTRACE_GETFPREGS
, tid
, 0L,
303 (PTRACE_TYPE_ARG3
) &fp_regs
) == -1)
304 perror_with_name (_("Couldn't get FP registers"));
306 mips64_fill_fpregset (regcache
, &fp_regs
, regno
);
308 if (ptrace (PTRACE_SETFPREGS
, tid
, 0L,
309 (PTRACE_TYPE_ARG3
) &fp_regs
) == -1)
310 perror_with_name (_("Couldn't set FP registers"));
314 /* Fetch REGNO (or all registers if REGNO == -1) from the target
315 using any working method. */
318 mips64_linux_fetch_registers (struct target_ops
*ops
,
319 struct regcache
*regcache
, int regnum
)
321 /* Unless we already know that PTRACE_GETREGS does not work, try it. */
322 if (have_ptrace_regsets
)
323 mips64_linux_regsets_fetch_registers (regcache
, regnum
);
325 /* If we know, or just found out, that PTRACE_GETREGS does not work, fall
326 back to PTRACE_PEEKUSER. */
327 if (!have_ptrace_regsets
)
328 super_fetch_registers (ops
, regcache
, regnum
);
331 /* Store REGNO (or all registers if REGNO == -1) to the target
332 using any working method. */
335 mips64_linux_store_registers (struct target_ops
*ops
,
336 struct regcache
*regcache
, int regnum
)
338 /* Unless we already know that PTRACE_GETREGS does not work, try it. */
339 if (have_ptrace_regsets
)
340 mips64_linux_regsets_store_registers (regcache
, regnum
);
342 /* If we know, or just found out, that PTRACE_GETREGS does not work, fall
343 back to PTRACE_PEEKUSER. */
344 if (!have_ptrace_regsets
)
345 super_store_registers (ops
, regcache
, regnum
);
348 /* Return the address in the core dump or inferior of register
352 mips_linux_register_u_offset (struct gdbarch
*gdbarch
, int regno
, int store_p
)
354 if (mips_abi_regsize (gdbarch
) == 8)
355 return mips64_linux_register_addr (gdbarch
, regno
, store_p
);
357 return mips_linux_register_addr (gdbarch
, regno
, store_p
);
360 static const struct target_desc
*
361 mips_linux_read_description (struct target_ops
*ops
)
363 /* Report that target registers are a size we know for sure
364 that we can get from ptrace. */
365 if (_MIPS_SIM
== _ABIO32
)
366 return tdesc_mips_linux
;
368 return tdesc_mips64_linux
;
371 #ifndef PTRACE_GET_WATCH_REGS
372 # define PTRACE_GET_WATCH_REGS 0xd0
375 #ifndef PTRACE_SET_WATCH_REGS
376 # define PTRACE_SET_WATCH_REGS 0xd1
383 #define W_MASK (1 << W_BIT)
384 #define R_MASK (1 << R_BIT)
385 #define I_MASK (1 << I_BIT)
387 #define IRW_MASK (I_MASK | R_MASK | W_MASK)
389 enum pt_watch_style
{
390 pt_watch_style_mips32
,
391 pt_watch_style_mips64
394 #define MAX_DEBUG_REGISTER 8
396 /* A value of zero in a watchlo indicates that it is available. */
398 struct mips32_watch_regs
400 uint32_t watchlo
[MAX_DEBUG_REGISTER
];
401 /* Lower 16 bits of watchhi. */
402 uint16_t watchhi
[MAX_DEBUG_REGISTER
];
403 /* Valid mask and I R W bits.
404 * bit 0 -- 1 if W bit is usable.
405 * bit 1 -- 1 if R bit is usable.
406 * bit 2 -- 1 if I bit is usable.
407 * bits 3 - 11 -- Valid watchhi mask bits.
409 uint16_t watch_masks
[MAX_DEBUG_REGISTER
];
410 /* The number of valid watch register pairs. */
412 /* There is confusion across gcc versions about structure alignment,
413 so we force 8 byte alignment for these structures so they match
414 the kernel even if it was build with a different gcc version. */
415 } __attribute__ ((aligned (8)));
417 struct mips64_watch_regs
419 uint64_t watchlo
[MAX_DEBUG_REGISTER
];
420 uint16_t watchhi
[MAX_DEBUG_REGISTER
];
421 uint16_t watch_masks
[MAX_DEBUG_REGISTER
];
423 } __attribute__ ((aligned (8)));
427 enum pt_watch_style style
;
430 struct mips32_watch_regs mips32
;
431 struct mips64_watch_regs mips64
;
435 /* -1 if the kernel and/or CPU do not support watch registers.
436 1 if watch_readback is valid and we can read style, num_valid
438 0 if we need to read the watch_readback. */
440 static int watch_readback_valid
;
442 /* Cached watch register read values. */
444 static struct pt_watch_regs watch_readback
;
446 /* We keep list of all watchpoints we should install and calculate the
447 watch register values each time the list changes. This allows for
448 easy sharing of watch registers for more than one watchpoint. */
450 struct mips_watchpoint
455 struct mips_watchpoint
*next
;
458 static struct mips_watchpoint
*current_watches
;
460 /* The current set of watch register values for writing the
463 static struct pt_watch_regs watch_mirror
;
465 /* Assuming usable watch registers, return the irw_mask. */
468 get_irw_mask (struct pt_watch_regs
*regs
, int set
)
472 case pt_watch_style_mips32
:
473 return regs
->mips32
.watch_masks
[set
] & IRW_MASK
;
474 case pt_watch_style_mips64
:
475 return regs
->mips64
.watch_masks
[set
] & IRW_MASK
;
477 internal_error (__FILE__
, __LINE__
,
478 _("Unrecognized watch register style"));
482 /* Assuming usable watch registers, return the reg_mask. */
485 get_reg_mask (struct pt_watch_regs
*regs
, int set
)
489 case pt_watch_style_mips32
:
490 return regs
->mips32
.watch_masks
[set
] & ~IRW_MASK
;
491 case pt_watch_style_mips64
:
492 return regs
->mips64
.watch_masks
[set
] & ~IRW_MASK
;
494 internal_error (__FILE__
, __LINE__
,
495 _("Unrecognized watch register style"));
499 /* Assuming usable watch registers, return the num_valid. */
502 get_num_valid (struct pt_watch_regs
*regs
)
506 case pt_watch_style_mips32
:
507 return regs
->mips32
.num_valid
;
508 case pt_watch_style_mips64
:
509 return regs
->mips64
.num_valid
;
511 internal_error (__FILE__
, __LINE__
,
512 _("Unrecognized watch register style"));
516 /* Assuming usable watch registers, return the watchlo. */
519 get_watchlo (struct pt_watch_regs
*regs
, int set
)
523 case pt_watch_style_mips32
:
524 return regs
->mips32
.watchlo
[set
];
525 case pt_watch_style_mips64
:
526 return regs
->mips64
.watchlo
[set
];
528 internal_error (__FILE__
, __LINE__
,
529 _("Unrecognized watch register style"));
533 /* Assuming usable watch registers, set a watchlo value. */
536 set_watchlo (struct pt_watch_regs
*regs
, int set
, CORE_ADDR value
)
540 case pt_watch_style_mips32
:
541 /* The cast will never throw away bits as 64 bit addresses can
542 never be used on a 32 bit kernel. */
543 regs
->mips32
.watchlo
[set
] = (uint32_t)value
;
545 case pt_watch_style_mips64
:
546 regs
->mips64
.watchlo
[set
] = value
;
549 internal_error (__FILE__
, __LINE__
,
550 _("Unrecognized watch register style"));
554 /* Assuming usable watch registers, return the watchhi. */
557 get_watchhi (struct pt_watch_regs
*regs
, int n
)
561 case pt_watch_style_mips32
:
562 return regs
->mips32
.watchhi
[n
];
563 case pt_watch_style_mips64
:
564 return regs
->mips64
.watchhi
[n
];
566 internal_error (__FILE__
, __LINE__
,
567 _("Unrecognized watch register style"));
571 /* Assuming usable watch registers, set a watchhi value. */
574 set_watchhi (struct pt_watch_regs
*regs
, int n
, uint16_t value
)
578 case pt_watch_style_mips32
:
579 regs
->mips32
.watchhi
[n
] = value
;
581 case pt_watch_style_mips64
:
582 regs
->mips64
.watchhi
[n
] = value
;
585 internal_error (__FILE__
, __LINE__
,
586 _("Unrecognized watch register style"));
591 mips_show_dr (const char *func
, CORE_ADDR addr
,
592 int len
, enum target_hw_bp_type type
)
596 puts_unfiltered (func
);
598 printf_unfiltered (" (addr=0x%s, len=%d, type=%s)", paddr (addr
), len
,
599 type
== hw_write
? "data-write"
600 : (type
== hw_read
? "data-read"
601 : (type
== hw_access
? "data-read/write"
602 : (type
== hw_execute
? "instruction-execute"
604 puts_unfiltered (":\n");
606 for (i
= 0; i
< MAX_DEBUG_REGISTER
; i
++)
607 printf_unfiltered ("\tDR%d: lo=0x%s, hi=0x%s\n",
608 i
, paddr (get_watchlo (&watch_mirror
, i
)),
609 paddr (get_watchhi (&watch_mirror
, i
)));
612 /* Return 1 if watch registers are usable. Cached information is used
613 unless force is true. */
616 mips_linux_read_watch_registers (int force
)
620 if (force
|| watch_readback_valid
== 0)
622 tid
= ptid_get_lwp (inferior_ptid
);
623 if (ptrace (PTRACE_GET_WATCH_REGS
, tid
, &watch_readback
) == -1)
625 watch_readback_valid
= -1;
628 switch (watch_readback
.style
)
630 case pt_watch_style_mips32
:
631 if (watch_readback
.mips32
.num_valid
== 0)
633 watch_readback_valid
= -1;
637 case pt_watch_style_mips64
:
638 if (watch_readback
.mips64
.num_valid
== 0)
640 watch_readback_valid
= -1;
645 watch_readback_valid
= -1;
648 /* Watch registers appear to be usable. */
649 watch_readback_valid
= 1;
651 return (watch_readback_valid
== 1) ? 1 : 0;
654 /* Convert GDB's type to an IRW mask. */
657 type_to_irw (int type
)
666 return (W_MASK
| R_MASK
);
672 /* Target to_can_use_hw_breakpoint implementation. Return 1 if we can
673 handle the specified watch type. */
676 mips_linux_can_use_hw_breakpoint (int type
, int cnt
, int ot
)
679 uint32_t wanted_mask
, irw_mask
;
681 if (!mips_linux_read_watch_registers (0))
686 case bp_hardware_watchpoint
:
687 wanted_mask
= W_MASK
;
689 case bp_read_watchpoint
:
690 wanted_mask
= R_MASK
;
692 case bp_access_watchpoint
:
693 wanted_mask
= R_MASK
| W_MASK
;
699 for (i
= 0; i
< get_num_valid (&watch_readback
) && cnt
; i
++)
701 irw_mask
= get_irw_mask (&watch_readback
, i
);
702 if ((irw_mask
& wanted_mask
) == wanted_mask
)
705 return (cnt
== 0) ? 1 : 0;
708 /* Target to_stopped_by_watchpoint implementation. Return 1 if
709 stopped by watchpoint. The watchhi R and W bits indicate the watch
710 register triggered. */
713 mips_linux_stopped_by_watchpoint (void)
718 if (!mips_linux_read_watch_registers (1))
721 num_valid
= get_num_valid (&watch_readback
);
723 for (n
= 0; n
< MAX_DEBUG_REGISTER
&& n
< num_valid
; n
++)
724 if (get_watchhi (&watch_readback
, n
) & (R_MASK
| W_MASK
))
730 /* Target to_stopped_data_address implementation. Set the address
731 where the watch triggered (if known). Return 1 if the address was
735 mips_linux_stopped_data_address (struct target_ops
*t
, CORE_ADDR
*paddr
)
737 /* On mips we don't know the low order 3 bits of the data address,
738 so we must return false. */
742 /* Set any low order bits in mask that are not set. */
745 fill_mask (CORE_ADDR mask
)
748 while (f
&& f
< mask
)
756 /* Try to add a single watch to the specified registers. Return 1 on
757 success, 0 on failure. */
760 try_one_watch (struct pt_watch_regs
*regs
, CORE_ADDR addr
,
761 int len
, unsigned irw
)
763 CORE_ADDR base_addr
, last_byte
, break_addr
, segment_len
;
764 CORE_ADDR mask_bits
, t_low
, t_low_end
;
767 struct pt_watch_regs regs_copy
;
772 last_byte
= addr
+ len
- 1;
773 mask_bits
= fill_mask (addr
^ last_byte
) | IRW_MASK
;
774 base_addr
= addr
& ~mask_bits
;
776 /* Check to see if it is covered by current registers. */
777 for (i
= 0; i
< get_num_valid (regs
); i
++)
779 t_low
= get_watchlo (regs
, i
);
780 if (t_low
!= 0 && irw
== ((unsigned)t_low
& irw
))
782 t_hi
= get_watchhi (regs
, i
) | IRW_MASK
;
783 t_low
&= ~(CORE_ADDR
)t_hi
;
784 if (addr
>= t_low
&& last_byte
<= (t_low
+ t_hi
))
788 /* Try to find an empty register. */
790 for (i
= 0; i
< get_num_valid (regs
); i
++)
792 t_low
= get_watchlo (regs
, i
);
793 if (t_low
== 0 && irw
== (get_irw_mask (regs
, i
) & irw
))
795 if (mask_bits
<= (get_reg_mask (regs
, i
) | IRW_MASK
))
797 /* It fits, we'll take it. */
798 set_watchlo (regs
, i
, base_addr
| irw
);
799 set_watchhi (regs
, i
, mask_bits
& ~IRW_MASK
);
804 /* It doesn't fit, but has the proper IRW capabilities. */
809 if (free_watches
> 1)
811 /* Try to split it across several registers. */
813 for (i
= 0; i
< get_num_valid (®s_copy
); i
++)
815 t_low
= get_watchlo (®s_copy
, i
);
816 t_hi
= get_reg_mask (®s_copy
, i
) | IRW_MASK
;
817 if (t_low
== 0 && irw
== (t_hi
& irw
))
819 t_low
= addr
& ~(CORE_ADDR
)t_hi
;
820 break_addr
= t_low
+ t_hi
+ 1;
821 if (break_addr
>= addr
+ len
)
824 segment_len
= break_addr
- addr
;
825 mask_bits
= fill_mask (addr
^ (addr
+ segment_len
- 1));
826 set_watchlo (®s_copy
, i
, (addr
& ~mask_bits
) | irw
);
827 set_watchhi (®s_copy
, i
, mask_bits
& ~IRW_MASK
);
828 if (break_addr
>= addr
+ len
)
833 len
= addr
+ len
- break_addr
;
838 /* It didn't fit anywhere, we failed. */
842 /* Target to_region_ok_for_hw_watchpoint implementation. Return 1 if
843 the specified region can be covered by the watch registers. */
846 mips_linux_region_ok_for_hw_watchpoint (CORE_ADDR addr
, int len
)
848 struct pt_watch_regs dummy_regs
;
851 if (!mips_linux_read_watch_registers (0))
854 dummy_regs
= watch_readback
;
855 /* Clear them out. */
856 for (i
= 0; i
< get_num_valid (&dummy_regs
); i
++)
857 set_watchlo (&dummy_regs
, i
, 0);
858 return try_one_watch (&dummy_regs
, addr
, len
, 0);
862 /* Write the mirrored watch register values for each thread. */
865 write_watchpoint_regs (void)
873 tid
= ptid_get_lwp (ptid
);
874 if (ptrace (PTRACE_SET_WATCH_REGS
, tid
, &watch_mirror
) == -1)
875 perror_with_name (_("Couldn't write debug register"));
880 /* linux_nat new_thread implementation. Write the mirrored watch
881 register values for the new thread. */
884 mips_linux_new_thread (ptid_t ptid
)
888 if (!mips_linux_read_watch_registers (0))
891 tid
= ptid_get_lwp (ptid
);
892 if (ptrace (PTRACE_SET_WATCH_REGS
, tid
, &watch_mirror
) == -1)
893 perror_with_name (_("Couldn't write debug register"));
896 /* Fill in the watch registers with the currently cached watches. */
899 populate_regs_from_watches (struct pt_watch_regs
*regs
)
901 struct mips_watchpoint
*w
;
904 /* Clear them out. */
905 for (i
= 0; i
< get_num_valid (regs
); i
++)
907 set_watchlo (regs
, i
, 0);
908 set_watchhi (regs
, i
, 0);
914 i
= try_one_watch (regs
, w
->addr
, w
->len
, type_to_irw (w
->type
));
915 /* They must all fit, because we previously calculated that they
922 /* Target to_insert_watchpoint implementation. Try to insert a new
923 watch. Return zero on success. */
926 mips_linux_insert_watchpoint (CORE_ADDR addr
, int len
, int type
)
928 struct pt_watch_regs regs
;
929 struct mips_watchpoint
*new_watch
;
930 struct mips_watchpoint
**pw
;
935 if (!mips_linux_read_watch_registers (0))
941 regs
= watch_readback
;
942 /* Add the current watches. */
943 populate_regs_from_watches (®s
);
945 /* Now try to add the new watch. */
946 if (!try_one_watch (®s
, addr
, len
, type_to_irw (type
)))
949 /* It fit. Stick it on the end of the list. */
950 new_watch
= (struct mips_watchpoint
*)
951 xmalloc (sizeof (struct mips_watchpoint
));
952 new_watch
->addr
= addr
;
953 new_watch
->len
= len
;
954 new_watch
->type
= type
;
955 new_watch
->next
= NULL
;
957 pw
= ¤t_watches
;
963 retval
= write_watchpoint_regs ();
966 mips_show_dr ("insert_watchpoint", addr
, len
, type
);
971 /* Target to_remove_watchpoint implementation. Try to remove a watch.
972 Return zero on success. */
975 mips_linux_remove_watchpoint (CORE_ADDR addr
, int len
, int type
)
980 struct mips_watchpoint
**pw
;
981 struct mips_watchpoint
*w
;
983 /* Search for a known watch that matches. Then unlink and free
986 pw
= ¤t_watches
;
989 if (w
->addr
== addr
&& w
->len
== len
&& w
->type
== type
)
1000 return -1; /* We don't know about it, fail doing nothing. */
1002 /* At this point watch_readback is known to be valid because we
1003 could not have added the watch without reading it. */
1004 gdb_assert (watch_readback_valid
== 1);
1006 watch_mirror
= watch_readback
;
1007 populate_regs_from_watches (&watch_mirror
);
1009 retval
= write_watchpoint_regs ();
1012 mips_show_dr ("remove_watchpoint", addr
, len
, type
);
1017 /* Target to_close implementation. Free any watches and call the
1018 super implementation. */
1021 mips_linux_close (int quitting
)
1023 struct mips_watchpoint
*w
;
1024 struct mips_watchpoint
*nw
;
1026 /* Clean out the current_watches list. */
1027 w
= current_watches
;
1034 current_watches
= NULL
;
1037 super_close (quitting
);
1040 void _initialize_mips_linux_nat (void);
1043 _initialize_mips_linux_nat (void)
1045 struct target_ops
*t
;
1047 add_setshow_boolean_cmd ("show-debug-regs", class_maintenance
,
1048 &maint_show_dr
, _("\
1049 Set whether to show variables that mirror the mips debug registers."), _("\
1050 Show whether to show variables that mirror the mips debug registers."), _("\
1051 Use \"on\" to enable, \"off\" to disable.\n\
1052 If enabled, the debug registers values are shown when GDB inserts\n\
1053 or removes a hardware breakpoint or watchpoint, and when the inferior\n\
1054 triggers a breakpoint or watchpoint."),
1057 &maintenance_set_cmdlist
,
1058 &maintenance_show_cmdlist
);
1060 t
= linux_trad_target (mips_linux_register_u_offset
);
1062 super_close
= t
->to_close
;
1063 t
->to_close
= mips_linux_close
;
1065 super_fetch_registers
= t
->to_fetch_registers
;
1066 super_store_registers
= t
->to_store_registers
;
1068 t
->to_fetch_registers
= mips64_linux_fetch_registers
;
1069 t
->to_store_registers
= mips64_linux_store_registers
;
1071 t
->to_can_use_hw_breakpoint
= mips_linux_can_use_hw_breakpoint
;
1072 t
->to_remove_watchpoint
= mips_linux_remove_watchpoint
;
1073 t
->to_insert_watchpoint
= mips_linux_insert_watchpoint
;
1074 t
->to_stopped_by_watchpoint
= mips_linux_stopped_by_watchpoint
;
1075 t
->to_stopped_data_address
= mips_linux_stopped_data_address
;
1076 t
->to_region_ok_for_hw_watchpoint
= mips_linux_region_ok_for_hw_watchpoint
;
1078 t
->to_read_description
= mips_linux_read_description
;
1080 linux_nat_add_target (t
);
1081 linux_nat_set_new_thread (t
, mips_linux_new_thread
);
1083 /* Initialize the standard target descriptions. */
1084 initialize_tdesc_mips_linux ();
1085 initialize_tdesc_mips64_linux ();