1 /* Target-dependent code for GNU/Linux on MIPS processors.
3 Copyright (C) 2001, 2002, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street, Fifth Floor,
21 Boston, MA 02110-1301, USA. */
26 #include "solib-svr4.h"
28 #include "mips-tdep.h"
29 #include "gdb_string.h"
30 #include "gdb_assert.h"
33 #include "trad-frame.h"
34 #include "tramp-frame.h"
37 #include "solib-svr4.h"
40 #include "mips-linux-tdep.h"
42 static struct target_so_ops mips_svr4_so_ops
;
44 /* Figure out where the longjmp will land.
45 We expect the first arg to be a pointer to the jmp_buf structure
46 from which we extract the pc (MIPS_LINUX_JB_PC) that we will land
47 at. The pc is copied into PC. This routine returns 1 on
50 #define MIPS_LINUX_JB_ELEMENT_SIZE 4
51 #define MIPS_LINUX_JB_PC 0
54 mips_linux_get_longjmp_target (CORE_ADDR
*pc
)
57 char buf
[TARGET_PTR_BIT
/ TARGET_CHAR_BIT
];
59 jb_addr
= read_register (MIPS_A0_REGNUM
);
61 if (target_read_memory (jb_addr
62 + MIPS_LINUX_JB_PC
* MIPS_LINUX_JB_ELEMENT_SIZE
,
63 buf
, TARGET_PTR_BIT
/ TARGET_CHAR_BIT
))
66 *pc
= extract_unsigned_integer (buf
, TARGET_PTR_BIT
/ TARGET_CHAR_BIT
);
71 /* Transform the bits comprising a 32-bit register to the right size
72 for regcache_raw_supply(). This is needed when mips_isa_regsize()
76 supply_32bit_reg (struct regcache
*regcache
, int regnum
, const void *addr
)
78 gdb_byte buf
[MAX_REGISTER_SIZE
];
79 store_signed_integer (buf
, register_size (current_gdbarch
, regnum
),
80 extract_signed_integer (addr
, 4));
81 regcache_raw_supply (regcache
, regnum
, buf
);
84 /* Unpack an elf_gregset_t into GDB's register cache. */
87 mips_supply_gregset (struct regcache
*regcache
,
88 const mips_elf_gregset_t
*gregsetp
)
91 const mips_elf_greg_t
*regp
= *gregsetp
;
92 char zerobuf
[MAX_REGISTER_SIZE
];
94 memset (zerobuf
, 0, MAX_REGISTER_SIZE
);
96 for (regi
= EF_REG0
; regi
<= EF_REG31
; regi
++)
97 supply_32bit_reg (regcache
, regi
- EF_REG0
, regp
+ regi
);
99 supply_32bit_reg (regcache
, mips_regnum (current_gdbarch
)->lo
,
101 supply_32bit_reg (regcache
, mips_regnum (current_gdbarch
)->hi
,
104 supply_32bit_reg (regcache
, mips_regnum (current_gdbarch
)->pc
,
106 supply_32bit_reg (regcache
, mips_regnum (current_gdbarch
)->badvaddr
,
107 regp
+ EF_CP0_BADVADDR
);
108 supply_32bit_reg (regcache
, MIPS_PS_REGNUM
, regp
+ EF_CP0_STATUS
);
109 supply_32bit_reg (regcache
, mips_regnum (current_gdbarch
)->cause
,
110 regp
+ EF_CP0_CAUSE
);
112 /* Fill inaccessible registers with zero. */
113 regcache_raw_supply (regcache
, MIPS_UNUSED_REGNUM
, zerobuf
);
114 for (regi
= MIPS_FIRST_EMBED_REGNUM
;
115 regi
< MIPS_LAST_EMBED_REGNUM
;
117 regcache_raw_supply (regcache
, regi
, zerobuf
);
120 /* Pack our registers (or one register) into an elf_gregset_t. */
123 mips_fill_gregset (const struct regcache
*regcache
,
124 mips_elf_gregset_t
*gregsetp
, int regno
)
127 mips_elf_greg_t
*regp
= *gregsetp
;
132 memset (regp
, 0, sizeof (mips_elf_gregset_t
));
133 for (regi
= 0; regi
< 32; regi
++)
134 mips_fill_gregset (regcache
, gregsetp
, regi
);
135 mips_fill_gregset (regcache
, gregsetp
,
136 mips_regnum (current_gdbarch
)->lo
);
137 mips_fill_gregset (regcache
, gregsetp
,
138 mips_regnum (current_gdbarch
)->hi
);
139 mips_fill_gregset (regcache
, gregsetp
,
140 mips_regnum (current_gdbarch
)->pc
);
141 mips_fill_gregset (regcache
, gregsetp
,
142 mips_regnum (current_gdbarch
)->badvaddr
);
143 mips_fill_gregset (regcache
, gregsetp
, MIPS_PS_REGNUM
);
144 mips_fill_gregset (regcache
, gregsetp
,
145 mips_regnum (current_gdbarch
)->cause
);
151 dst
= regp
+ regno
+ EF_REG0
;
152 regcache_raw_collect (regcache
, regno
, dst
);
156 if (regno
== mips_regnum (current_gdbarch
)->lo
)
158 else if (regno
== mips_regnum (current_gdbarch
)->hi
)
160 else if (regno
== mips_regnum (current_gdbarch
)->pc
)
161 regaddr
= EF_CP0_EPC
;
162 else if (regno
== mips_regnum (current_gdbarch
)->badvaddr
)
163 regaddr
= EF_CP0_BADVADDR
;
164 else if (regno
== MIPS_PS_REGNUM
)
165 regaddr
= EF_CP0_STATUS
;
166 else if (regno
== mips_regnum (current_gdbarch
)->cause
)
167 regaddr
= EF_CP0_CAUSE
;
173 dst
= regp
+ regaddr
;
174 regcache_raw_collect (regcache
, regno
, dst
);
178 /* Likewise, unpack an elf_fpregset_t. */
181 mips_supply_fpregset (struct regcache
*regcache
,
182 const mips_elf_fpregset_t
*fpregsetp
)
185 char zerobuf
[MAX_REGISTER_SIZE
];
187 memset (zerobuf
, 0, MAX_REGISTER_SIZE
);
189 for (regi
= 0; regi
< 32; regi
++)
190 regcache_raw_supply (regcache
, FP0_REGNUM
+ regi
, *fpregsetp
+ regi
);
192 regcache_raw_supply (regcache
,
193 mips_regnum (current_gdbarch
)->fp_control_status
,
196 /* FIXME: how can we supply FCRIR? The ABI doesn't tell us. */
197 regcache_raw_supply (regcache
,
198 mips_regnum (current_gdbarch
)->fp_implementation_revision
,
202 /* Likewise, pack one or all floating point registers into an
206 mips_fill_fpregset (const struct regcache
*regcache
,
207 mips_elf_fpregset_t
*fpregsetp
, int regno
)
211 if ((regno
>= FP0_REGNUM
) && (regno
< FP0_REGNUM
+ 32))
213 to
= (char *) (*fpregsetp
+ regno
- FP0_REGNUM
);
214 regcache_raw_collect (regcache
, regno
, to
);
216 else if (regno
== mips_regnum (current_gdbarch
)->fp_control_status
)
218 to
= (char *) (*fpregsetp
+ 32);
219 regcache_raw_collect (regcache
, regno
, to
);
221 else if (regno
== -1)
225 for (regi
= 0; regi
< 32; regi
++)
226 mips_fill_fpregset (regcache
, fpregsetp
, FP0_REGNUM
+ regi
);
227 mips_fill_fpregset (regcache
, fpregsetp
,
228 mips_regnum (current_gdbarch
)->fp_control_status
);
232 /* Support for 64-bit ABIs. */
234 /* Figure out where the longjmp will land.
235 We expect the first arg to be a pointer to the jmp_buf structure
236 from which we extract the pc (MIPS_LINUX_JB_PC) that we will land
237 at. The pc is copied into PC. This routine returns 1 on
240 /* Details about jmp_buf. */
242 #define MIPS64_LINUX_JB_PC 0
245 mips64_linux_get_longjmp_target (CORE_ADDR
*pc
)
248 void *buf
= alloca (TARGET_PTR_BIT
/ TARGET_CHAR_BIT
);
249 int element_size
= TARGET_PTR_BIT
== 32 ? 4 : 8;
251 jb_addr
= read_register (MIPS_A0_REGNUM
);
253 if (target_read_memory (jb_addr
+ MIPS64_LINUX_JB_PC
* element_size
,
254 buf
, TARGET_PTR_BIT
/ TARGET_CHAR_BIT
))
257 *pc
= extract_unsigned_integer (buf
, TARGET_PTR_BIT
/ TARGET_CHAR_BIT
);
262 /* Register set support functions. These operate on standard 64-bit
263 regsets, but work whether the target is 32-bit or 64-bit. A 32-bit
264 target will still use the 64-bit format for PTRACE_GETREGS. */
266 /* Supply a 64-bit register. */
269 supply_64bit_reg (struct regcache
*regcache
, int regnum
,
272 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
273 && register_size (current_gdbarch
, regnum
) == 4)
274 regcache_raw_supply (regcache
, regnum
, buf
+ 4);
276 regcache_raw_supply (regcache
, regnum
, buf
);
279 /* Unpack a 64-bit elf_gregset_t into GDB's register cache. */
282 mips64_supply_gregset (struct regcache
*regcache
,
283 const mips64_elf_gregset_t
*gregsetp
)
286 const mips64_elf_greg_t
*regp
= *gregsetp
;
287 gdb_byte zerobuf
[MAX_REGISTER_SIZE
];
289 memset (zerobuf
, 0, MAX_REGISTER_SIZE
);
291 for (regi
= MIPS64_EF_REG0
; regi
<= MIPS64_EF_REG31
; regi
++)
292 supply_64bit_reg (regcache
, regi
- MIPS64_EF_REG0
,
293 (const gdb_byte
*)(regp
+ regi
));
295 supply_64bit_reg (regcache
, mips_regnum (current_gdbarch
)->lo
,
296 (const gdb_byte
*) (regp
+ MIPS64_EF_LO
));
297 supply_64bit_reg (regcache
, mips_regnum (current_gdbarch
)->hi
,
298 (const gdb_byte
*) (regp
+ MIPS64_EF_HI
));
300 supply_64bit_reg (regcache
, mips_regnum (current_gdbarch
)->pc
,
301 (const gdb_byte
*) (regp
+ MIPS64_EF_CP0_EPC
));
302 supply_64bit_reg (regcache
, mips_regnum (current_gdbarch
)->badvaddr
,
303 (const gdb_byte
*) (regp
+ MIPS64_EF_CP0_BADVADDR
));
304 supply_64bit_reg (regcache
, MIPS_PS_REGNUM
,
305 (const gdb_byte
*) (regp
+ MIPS64_EF_CP0_STATUS
));
306 supply_64bit_reg (regcache
, mips_regnum (current_gdbarch
)->cause
,
307 (const gdb_byte
*) (regp
+ MIPS64_EF_CP0_CAUSE
));
309 /* Fill inaccessible registers with zero. */
310 regcache_raw_supply (regcache
, MIPS_UNUSED_REGNUM
, zerobuf
);
311 for (regi
= MIPS_FIRST_EMBED_REGNUM
;
312 regi
< MIPS_LAST_EMBED_REGNUM
;
314 regcache_raw_supply (regcache
, regi
, zerobuf
);
317 /* Pack our registers (or one register) into a 64-bit elf_gregset_t. */
320 mips64_fill_gregset (const struct regcache
*regcache
,
321 mips64_elf_gregset_t
*gregsetp
, int regno
)
324 mips64_elf_greg_t
*regp
= *gregsetp
;
329 memset (regp
, 0, sizeof (mips64_elf_gregset_t
));
330 for (regi
= 0; regi
< 32; regi
++)
331 mips64_fill_gregset (regcache
, gregsetp
, regi
);
332 mips64_fill_gregset (regcache
, gregsetp
,
333 mips_regnum (current_gdbarch
)->lo
);
334 mips64_fill_gregset (regcache
, gregsetp
,
335 mips_regnum (current_gdbarch
)->hi
);
336 mips64_fill_gregset (regcache
, gregsetp
,
337 mips_regnum (current_gdbarch
)->pc
);
338 mips64_fill_gregset (regcache
, gregsetp
,
339 mips_regnum (current_gdbarch
)->badvaddr
);
340 mips64_fill_gregset (regcache
, gregsetp
, MIPS_PS_REGNUM
);
341 mips64_fill_gregset (regcache
, gregsetp
,
342 mips_regnum (current_gdbarch
)->cause
);
347 regaddr
= regno
+ MIPS64_EF_REG0
;
348 else if (regno
== mips_regnum (current_gdbarch
)->lo
)
349 regaddr
= MIPS64_EF_LO
;
350 else if (regno
== mips_regnum (current_gdbarch
)->hi
)
351 regaddr
= MIPS64_EF_HI
;
352 else if (regno
== mips_regnum (current_gdbarch
)->pc
)
353 regaddr
= MIPS64_EF_CP0_EPC
;
354 else if (regno
== mips_regnum (current_gdbarch
)->badvaddr
)
355 regaddr
= MIPS64_EF_CP0_BADVADDR
;
356 else if (regno
== MIPS_PS_REGNUM
)
357 regaddr
= MIPS64_EF_CP0_STATUS
;
358 else if (regno
== mips_regnum (current_gdbarch
)->cause
)
359 regaddr
= MIPS64_EF_CP0_CAUSE
;
365 gdb_byte buf
[MAX_REGISTER_SIZE
];
368 regcache_raw_collect (regcache
, regno
, buf
);
369 val
= extract_signed_integer (buf
,
370 register_size (current_gdbarch
, regno
));
371 dst
= regp
+ regaddr
;
372 store_signed_integer (dst
, 8, val
);
376 /* Likewise, unpack an elf_fpregset_t. */
379 mips64_supply_fpregset (struct regcache
*regcache
,
380 const mips64_elf_fpregset_t
*fpregsetp
)
384 /* See mips_linux_o32_sigframe_init for a description of the
385 peculiar FP register layout. */
386 if (register_size (current_gdbarch
, FP0_REGNUM
) == 4)
387 for (regi
= 0; regi
< 32; regi
++)
389 const gdb_byte
*reg_ptr
= (const gdb_byte
*)(*fpregsetp
+ (regi
& ~1));
390 if ((gdbarch_byte_order (current_gdbarch
)
391 == BFD_ENDIAN_BIG
) != (regi
& 1))
393 regcache_raw_supply (regcache
, FP0_REGNUM
+ regi
, reg_ptr
);
396 for (regi
= 0; regi
< 32; regi
++)
397 regcache_raw_supply (regcache
, FP0_REGNUM
+ regi
,
398 (const char *)(*fpregsetp
+ regi
));
400 supply_32bit_reg (regcache
, mips_regnum (current_gdbarch
)->fp_control_status
,
401 (const gdb_byte
*)(*fpregsetp
+ 32));
403 /* The ABI doesn't tell us how to supply FCRIR, and core dumps don't
404 include it - but the result of PTRACE_GETFPREGS does. The best we
405 can do is to assume that its value is present. */
406 supply_32bit_reg (regcache
,
407 mips_regnum (current_gdbarch
)->fp_implementation_revision
,
408 (const gdb_byte
*)(*fpregsetp
+ 32) + 4);
411 /* Likewise, pack one or all floating point registers into an
415 mips64_fill_fpregset (const struct regcache
*regcache
,
416 mips64_elf_fpregset_t
*fpregsetp
, int regno
)
420 if ((regno
>= FP0_REGNUM
) && (regno
< FP0_REGNUM
+ 32))
422 /* See mips_linux_o32_sigframe_init for a description of the
423 peculiar FP register layout. */
424 if (register_size (current_gdbarch
, regno
) == 4)
426 int regi
= regno
- FP0_REGNUM
;
428 to
= (gdb_byte
*) (*fpregsetp
+ (regi
& ~1));
429 if ((gdbarch_byte_order (current_gdbarch
)
430 == BFD_ENDIAN_BIG
) != (regi
& 1))
432 regcache_raw_collect (regcache
, regno
, to
);
436 to
= (gdb_byte
*) (*fpregsetp
+ regno
- FP0_REGNUM
);
437 regcache_raw_collect (regcache
, regno
, to
);
440 else if (regno
== mips_regnum (current_gdbarch
)->fp_control_status
)
442 gdb_byte buf
[MAX_REGISTER_SIZE
];
445 regcache_raw_collect (regcache
, regno
, buf
);
446 val
= extract_signed_integer (buf
,
447 register_size (current_gdbarch
, regno
));
448 to
= (gdb_byte
*) (*fpregsetp
+ 32);
449 store_signed_integer (to
, 4, val
);
451 else if (regno
== mips_regnum (current_gdbarch
)->fp_implementation_revision
)
453 gdb_byte buf
[MAX_REGISTER_SIZE
];
456 regcache_raw_collect (regcache
, regno
, buf
);
457 val
= extract_signed_integer (buf
,
458 register_size (current_gdbarch
, regno
));
459 to
= (gdb_byte
*) (*fpregsetp
+ 32) + 4;
460 store_signed_integer (to
, 4, val
);
462 else if (regno
== -1)
466 for (regi
= 0; regi
< 32; regi
++)
467 mips64_fill_fpregset (regcache
, fpregsetp
, FP0_REGNUM
+ regi
);
468 mips64_fill_fpregset (regcache
, fpregsetp
,
469 mips_regnum (current_gdbarch
)->fp_control_status
);
470 mips64_fill_fpregset (regcache
, fpregsetp
,
471 (mips_regnum (current_gdbarch
)
472 ->fp_implementation_revision
));
477 /* Use a local version of this function to get the correct types for
478 regsets, until multi-arch core support is ready. */
481 fetch_core_registers (struct regcache
*regcache
,
482 char *core_reg_sect
, unsigned core_reg_size
,
483 int which
, CORE_ADDR reg_addr
)
485 mips_elf_gregset_t gregset
;
486 mips_elf_fpregset_t fpregset
;
487 mips64_elf_gregset_t gregset64
;
488 mips64_elf_fpregset_t fpregset64
;
492 if (core_reg_size
== sizeof (gregset
))
494 memcpy ((char *) &gregset
, core_reg_sect
, sizeof (gregset
));
495 mips_supply_gregset (regcache
,
496 (const mips_elf_gregset_t
*) &gregset
);
498 else if (core_reg_size
== sizeof (gregset64
))
500 memcpy ((char *) &gregset64
, core_reg_sect
, sizeof (gregset64
));
501 mips64_supply_gregset (regcache
,
502 (const mips64_elf_gregset_t
*) &gregset64
);
506 warning (_("wrong size gregset struct in core file"));
511 if (core_reg_size
== sizeof (fpregset
))
513 memcpy ((char *) &fpregset
, core_reg_sect
, sizeof (fpregset
));
514 mips_supply_fpregset (regcache
,
515 (const mips_elf_fpregset_t
*) &fpregset
);
517 else if (core_reg_size
== sizeof (fpregset64
))
519 memcpy ((char *) &fpregset64
, core_reg_sect
,
520 sizeof (fpregset64
));
521 mips64_supply_fpregset (regcache
,
522 (const mips64_elf_fpregset_t
*) &fpregset64
);
526 warning (_("wrong size fpregset struct in core file"));
531 /* Register that we are able to handle ELF file formats using standard
532 procfs "regset" structures. */
534 static struct core_fns regset_core_fns
=
536 bfd_target_elf_flavour
, /* core_flavour */
537 default_check_format
, /* check_format */
538 default_core_sniffer
, /* core_sniffer */
539 fetch_core_registers
, /* core_read_registers */
544 /* Check the code at PC for a dynamic linker lazy resolution stub.
545 Because they aren't in the .plt section, we pattern-match on the
546 code generated by GNU ld. They look like this:
553 (with the appropriate doubleword instructions for N64). Also
554 return the dynamic symbol index used in the last instruction. */
557 mips_linux_in_dynsym_stub (CORE_ADDR pc
, char *name
)
559 unsigned char buf
[28], *p
;
560 ULONGEST insn
, insn1
;
561 int n64
= (mips_abi (current_gdbarch
) == MIPS_ABI_N64
);
563 read_memory (pc
- 12, buf
, 28);
567 /* ld t9,0x8010(gp) */
572 /* lw t9,0x8010(gp) */
579 insn
= extract_unsigned_integer (p
, 4);
587 insn
= extract_unsigned_integer (p
+ 4, 4);
591 if (insn
!= 0x03e0782d)
597 if (insn
!= 0x03e07821)
601 insn
= extract_unsigned_integer (p
+ 8, 4);
603 if (insn
!= 0x0320f809)
606 insn
= extract_unsigned_integer (p
+ 12, 4);
609 /* daddiu t8,zero,0 */
610 if ((insn
& 0xffff0000) != 0x64180000)
615 /* addiu t8,zero,0 */
616 if ((insn
& 0xffff0000) != 0x24180000)
620 return (insn
& 0xffff);
623 /* Return non-zero iff PC belongs to the dynamic linker resolution
624 code or to a stub. */
627 mips_linux_in_dynsym_resolve_code (CORE_ADDR pc
)
629 /* Check whether PC is in the dynamic linker. This also checks
630 whether it is in the .plt section, which MIPS does not use. */
631 if (svr4_in_dynsym_resolve_code (pc
))
634 /* Pattern match for the stub. It would be nice if there were a
635 more efficient way to avoid this check. */
636 if (mips_linux_in_dynsym_stub (pc
, NULL
))
642 /* See the comments for SKIP_SOLIB_RESOLVER at the top of infrun.c,
643 and glibc_skip_solib_resolver in glibc-tdep.c. The normal glibc
644 implementation of this triggers at "fixup" from the same objfile as
645 "_dl_runtime_resolve"; MIPS GNU/Linux can trigger at
646 "__dl_runtime_resolve" directly. An unresolved PLT entry will
647 point to _dl_runtime_resolve, which will first call
648 __dl_runtime_resolve, and then pass control to the resolved
652 mips_linux_skip_resolver (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
654 struct minimal_symbol
*resolver
;
656 resolver
= lookup_minimal_symbol ("__dl_runtime_resolve", NULL
, NULL
);
658 if (resolver
&& SYMBOL_VALUE_ADDRESS (resolver
) == pc
)
659 return frame_pc_unwind (get_current_frame ());
664 /* Signal trampoline support. There are four supported layouts for a
665 signal frame: o32 sigframe, o32 rt_sigframe, n32 rt_sigframe, and
666 n64 rt_sigframe. We handle them all independently; not the most
667 efficient way, but simplest. First, declare all the unwinders. */
669 static void mips_linux_o32_sigframe_init (const struct tramp_frame
*self
,
670 struct frame_info
*next_frame
,
671 struct trad_frame_cache
*this_cache
,
674 static void mips_linux_n32n64_sigframe_init (const struct tramp_frame
*self
,
675 struct frame_info
*next_frame
,
676 struct trad_frame_cache
*this_cache
,
679 #define MIPS_NR_LINUX 4000
680 #define MIPS_NR_N64_LINUX 5000
681 #define MIPS_NR_N32_LINUX 6000
683 #define MIPS_NR_sigreturn MIPS_NR_LINUX + 119
684 #define MIPS_NR_rt_sigreturn MIPS_NR_LINUX + 193
685 #define MIPS_NR_N64_rt_sigreturn MIPS_NR_N64_LINUX + 211
686 #define MIPS_NR_N32_rt_sigreturn MIPS_NR_N32_LINUX + 211
688 #define MIPS_INST_LI_V0_SIGRETURN 0x24020000 + MIPS_NR_sigreturn
689 #define MIPS_INST_LI_V0_RT_SIGRETURN 0x24020000 + MIPS_NR_rt_sigreturn
690 #define MIPS_INST_LI_V0_N64_RT_SIGRETURN 0x24020000 + MIPS_NR_N64_rt_sigreturn
691 #define MIPS_INST_LI_V0_N32_RT_SIGRETURN 0x24020000 + MIPS_NR_N32_rt_sigreturn
692 #define MIPS_INST_SYSCALL 0x0000000c
694 static const struct tramp_frame mips_linux_o32_sigframe
= {
698 { MIPS_INST_LI_V0_SIGRETURN
, -1 },
699 { MIPS_INST_SYSCALL
, -1 },
700 { TRAMP_SENTINEL_INSN
, -1 }
702 mips_linux_o32_sigframe_init
705 static const struct tramp_frame mips_linux_o32_rt_sigframe
= {
709 { MIPS_INST_LI_V0_RT_SIGRETURN
, -1 },
710 { MIPS_INST_SYSCALL
, -1 },
711 { TRAMP_SENTINEL_INSN
, -1 } },
712 mips_linux_o32_sigframe_init
715 static const struct tramp_frame mips_linux_n32_rt_sigframe
= {
719 { MIPS_INST_LI_V0_N32_RT_SIGRETURN
, -1 },
720 { MIPS_INST_SYSCALL
, -1 },
721 { TRAMP_SENTINEL_INSN
, -1 }
723 mips_linux_n32n64_sigframe_init
726 static const struct tramp_frame mips_linux_n64_rt_sigframe
= {
730 { MIPS_INST_LI_V0_N64_RT_SIGRETURN
, -1 },
731 { MIPS_INST_SYSCALL
, -1 },
732 { TRAMP_SENTINEL_INSN
, -1 }
734 mips_linux_n32n64_sigframe_init
738 /* The unwinder for o32 signal frames. The legacy structures look
742 u32 sf_ass[4]; [argument save space for o32]
743 u32 sf_code[2]; [signal trampoline]
744 struct sigcontext sf_sc;
749 unsigned int sc_regmask; [Unused]
750 unsigned int sc_status;
751 unsigned long long sc_pc;
752 unsigned long long sc_regs[32];
753 unsigned long long sc_fpregs[32];
754 unsigned int sc_ownedfp;
755 unsigned int sc_fpc_csr;
756 unsigned int sc_fpc_eir; [Unused]
757 unsigned int sc_used_math;
758 unsigned int sc_ssflags; [Unused]
759 [Alignment hole of four bytes]
760 unsigned long long sc_mdhi;
761 unsigned long long sc_mdlo;
763 unsigned int sc_cause; [Unused]
764 unsigned int sc_badvaddr; [Unused]
766 unsigned long sc_sigset[4]; [kernel's sigset_t]
769 The RT signal frames look like this:
772 u32 rs_ass[4]; [argument save space for o32]
773 u32 rs_code[2] [signal trampoline]
774 struct siginfo rs_info;
775 struct ucontext rs_uc;
779 unsigned long uc_flags;
780 struct ucontext *uc_link;
782 [Alignment hole of four bytes]
783 struct sigcontext uc_mcontext;
788 #define SIGFRAME_CODE_OFFSET (4 * 4)
789 #define SIGFRAME_SIGCONTEXT_OFFSET (6 * 4)
791 #define RTSIGFRAME_SIGINFO_SIZE 128
792 #define STACK_T_SIZE (3 * 4)
793 #define UCONTEXT_SIGCONTEXT_OFFSET (2 * 4 + STACK_T_SIZE + 4)
794 #define RTSIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \
795 + RTSIGFRAME_SIGINFO_SIZE \
796 + UCONTEXT_SIGCONTEXT_OFFSET)
798 #define SIGCONTEXT_PC (1 * 8)
799 #define SIGCONTEXT_REGS (2 * 8)
800 #define SIGCONTEXT_FPREGS (34 * 8)
801 #define SIGCONTEXT_FPCSR (66 * 8 + 4)
802 #define SIGCONTEXT_HI (69 * 8)
803 #define SIGCONTEXT_LO (70 * 8)
804 #define SIGCONTEXT_CAUSE (71 * 8 + 0)
805 #define SIGCONTEXT_BADVADDR (71 * 8 + 4)
807 #define SIGCONTEXT_REG_SIZE 8
810 mips_linux_o32_sigframe_init (const struct tramp_frame
*self
,
811 struct frame_info
*next_frame
,
812 struct trad_frame_cache
*this_cache
,
815 int ireg
, reg_position
;
816 CORE_ADDR sigcontext_base
= func
- SIGFRAME_CODE_OFFSET
;
817 const struct mips_regnum
*regs
= mips_regnum (current_gdbarch
);
820 if (self
== &mips_linux_o32_sigframe
)
821 sigcontext_base
+= SIGFRAME_SIGCONTEXT_OFFSET
;
823 sigcontext_base
+= RTSIGFRAME_SIGCONTEXT_OFFSET
;
825 /* I'm not proud of this hack. Eventually we will have the
826 infrastructure to indicate the size of saved registers on a
827 per-frame basis, but right now we don't; the kernel saves eight
828 bytes but we only want four. Use regs_base to access any
830 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
831 regs_base
= sigcontext_base
+ 4;
833 regs_base
= sigcontext_base
;
836 trad_frame_set_reg_addr (this_cache
, ORIG_ZERO_REGNUM
837 + gdbarch_num_regs (current_gdbarch
),
838 regs_base
+ SIGCONTEXT_REGS
);
841 for (ireg
= 1; ireg
< 32; ireg
++)
842 trad_frame_set_reg_addr (this_cache
,
843 ireg
+ MIPS_ZERO_REGNUM
844 + gdbarch_num_regs (current_gdbarch
),
845 regs_base
+ SIGCONTEXT_REGS
846 + ireg
* SIGCONTEXT_REG_SIZE
);
848 /* The way that floating point registers are saved, unfortunately,
849 depends on the architecture the kernel is built for. For the r3000 and
850 tx39, four bytes of each register are at the beginning of each of the
851 32 eight byte slots. For everything else, the registers are saved
852 using double precision; only the even-numbered slots are initialized,
853 and the high bits are the odd-numbered register. Assume the latter
854 layout, since we can't tell, and it's much more common. Which bits are
855 the "high" bits depends on endianness. */
856 for (ireg
= 0; ireg
< 32; ireg
++)
857 if ((gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
) != (ireg
& 1))
858 trad_frame_set_reg_addr (this_cache
,
860 gdbarch_num_regs (current_gdbarch
),
861 sigcontext_base
+ SIGCONTEXT_FPREGS
+ 4
862 + (ireg
& ~1) * SIGCONTEXT_REG_SIZE
);
864 trad_frame_set_reg_addr (this_cache
,
866 + gdbarch_num_regs (current_gdbarch
),
867 sigcontext_base
+ SIGCONTEXT_FPREGS
868 + (ireg
& ~1) * SIGCONTEXT_REG_SIZE
);
870 trad_frame_set_reg_addr (this_cache
,
871 regs
->pc
+ gdbarch_num_regs (current_gdbarch
),
872 regs_base
+ SIGCONTEXT_PC
);
874 trad_frame_set_reg_addr (this_cache
,
875 regs
->fp_control_status
876 + gdbarch_num_regs (current_gdbarch
),
877 sigcontext_base
+ SIGCONTEXT_FPCSR
);
878 trad_frame_set_reg_addr (this_cache
,
879 regs
->hi
+ gdbarch_num_regs (current_gdbarch
),
880 regs_base
+ SIGCONTEXT_HI
);
881 trad_frame_set_reg_addr (this_cache
,
882 regs
->lo
+ gdbarch_num_regs (current_gdbarch
),
883 regs_base
+ SIGCONTEXT_LO
);
884 trad_frame_set_reg_addr (this_cache
,
885 regs
->cause
+ gdbarch_num_regs (current_gdbarch
),
886 sigcontext_base
+ SIGCONTEXT_CAUSE
);
887 trad_frame_set_reg_addr (this_cache
,
888 regs
->badvaddr
+ gdbarch_num_regs (current_gdbarch
),
889 sigcontext_base
+ SIGCONTEXT_BADVADDR
);
891 /* Choice of the bottom of the sigframe is somewhat arbitrary. */
892 trad_frame_set_id (this_cache
,
893 frame_id_build (func
- SIGFRAME_CODE_OFFSET
,
898 /* For N32/N64 things look different. There is no non-rt signal frame.
900 struct rt_sigframe_n32 {
901 u32 rs_ass[4]; [ argument save space for o32 ]
902 u32 rs_code[2]; [ signal trampoline ]
903 struct siginfo rs_info;
904 struct ucontextn32 rs_uc;
911 struct sigcontext uc_mcontext;
912 sigset_t uc_sigmask; [ mask last for extensibility ]
915 struct rt_sigframe_n32 {
916 u32 rs_ass[4]; [ argument save space for o32 ]
917 u32 rs_code[2]; [ signal trampoline ]
918 struct siginfo rs_info;
919 struct ucontext rs_uc;
923 unsigned long uc_flags;
924 struct ucontext *uc_link;
926 struct sigcontext uc_mcontext;
927 sigset_t uc_sigmask; [ mask last for extensibility ]
930 And the sigcontext is different (this is for both n32 and n64):
933 unsigned long long sc_regs[32];
934 unsigned long long sc_fpregs[32];
935 unsigned long long sc_mdhi;
936 unsigned long long sc_mdlo;
937 unsigned long long sc_pc;
938 unsigned int sc_status;
939 unsigned int sc_fpc_csr;
940 unsigned int sc_fpc_eir;
941 unsigned int sc_used_math;
942 unsigned int sc_cause;
943 unsigned int sc_badvaddr;
947 #define N32_STACK_T_SIZE STACK_T_SIZE
948 #define N64_STACK_T_SIZE (2 * 8 + 4)
949 #define N32_UCONTEXT_SIGCONTEXT_OFFSET (2 * 4 + N32_STACK_T_SIZE + 4)
950 #define N64_UCONTEXT_SIGCONTEXT_OFFSET (2 * 8 + N64_STACK_T_SIZE + 4)
951 #define N32_SIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \
952 + RTSIGFRAME_SIGINFO_SIZE \
953 + N32_UCONTEXT_SIGCONTEXT_OFFSET)
954 #define N64_SIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \
955 + RTSIGFRAME_SIGINFO_SIZE \
956 + N64_UCONTEXT_SIGCONTEXT_OFFSET)
958 #define N64_SIGCONTEXT_REGS (0 * 8)
959 #define N64_SIGCONTEXT_FPREGS (32 * 8)
960 #define N64_SIGCONTEXT_HI (64 * 8)
961 #define N64_SIGCONTEXT_LO (65 * 8)
962 #define N64_SIGCONTEXT_PC (66 * 8)
963 #define N64_SIGCONTEXT_FPCSR (67 * 8 + 1 * 4)
964 #define N64_SIGCONTEXT_FIR (67 * 8 + 2 * 4)
965 #define N64_SIGCONTEXT_CAUSE (67 * 8 + 4 * 4)
966 #define N64_SIGCONTEXT_BADVADDR (67 * 8 + 5 * 4)
968 #define N64_SIGCONTEXT_REG_SIZE 8
971 mips_linux_n32n64_sigframe_init (const struct tramp_frame
*self
,
972 struct frame_info
*next_frame
,
973 struct trad_frame_cache
*this_cache
,
976 int ireg
, reg_position
;
977 CORE_ADDR sigcontext_base
= func
- SIGFRAME_CODE_OFFSET
;
978 const struct mips_regnum
*regs
= mips_regnum (current_gdbarch
);
980 if (self
== &mips_linux_n32_rt_sigframe
)
981 sigcontext_base
+= N32_SIGFRAME_SIGCONTEXT_OFFSET
;
983 sigcontext_base
+= N64_SIGFRAME_SIGCONTEXT_OFFSET
;
986 trad_frame_set_reg_addr (this_cache
,
988 + gdbarch_num_regs (current_gdbarch
),
989 sigcontext_base
+ N64_SIGCONTEXT_REGS
);
992 for (ireg
= 1; ireg
< 32; ireg
++)
993 trad_frame_set_reg_addr (this_cache
,
994 ireg
+ MIPS_ZERO_REGNUM
995 + gdbarch_num_regs (current_gdbarch
),
996 sigcontext_base
+ N64_SIGCONTEXT_REGS
997 + ireg
* N64_SIGCONTEXT_REG_SIZE
);
999 for (ireg
= 0; ireg
< 32; ireg
++)
1000 trad_frame_set_reg_addr (this_cache
,
1002 + gdbarch_num_regs (current_gdbarch
),
1003 sigcontext_base
+ N64_SIGCONTEXT_FPREGS
1004 + ireg
* N64_SIGCONTEXT_REG_SIZE
);
1006 trad_frame_set_reg_addr (this_cache
,
1007 regs
->pc
+ gdbarch_num_regs (current_gdbarch
),
1008 sigcontext_base
+ N64_SIGCONTEXT_PC
);
1010 trad_frame_set_reg_addr (this_cache
,
1011 regs
->fp_control_status
1012 + gdbarch_num_regs (current_gdbarch
),
1013 sigcontext_base
+ N64_SIGCONTEXT_FPCSR
);
1014 trad_frame_set_reg_addr (this_cache
,
1015 regs
->hi
+ gdbarch_num_regs (current_gdbarch
),
1016 sigcontext_base
+ N64_SIGCONTEXT_HI
);
1017 trad_frame_set_reg_addr (this_cache
,
1018 regs
->lo
+ gdbarch_num_regs (current_gdbarch
),
1019 sigcontext_base
+ N64_SIGCONTEXT_LO
);
1020 trad_frame_set_reg_addr (this_cache
,
1021 regs
->cause
+ gdbarch_num_regs (current_gdbarch
),
1022 sigcontext_base
+ N64_SIGCONTEXT_CAUSE
);
1023 trad_frame_set_reg_addr (this_cache
,
1024 regs
->badvaddr
+ gdbarch_num_regs (current_gdbarch
),
1025 sigcontext_base
+ N64_SIGCONTEXT_BADVADDR
);
1027 /* Choice of the bottom of the sigframe is somewhat arbitrary. */
1028 trad_frame_set_id (this_cache
,
1029 frame_id_build (func
- SIGFRAME_CODE_OFFSET
,
1034 /* Initialize one of the GNU/Linux OS ABIs. */
1037 mips_linux_init_abi (struct gdbarch_info info
,
1038 struct gdbarch
*gdbarch
)
1040 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1041 enum mips_abi abi
= mips_abi (gdbarch
);
1046 set_gdbarch_get_longjmp_target (gdbarch
,
1047 mips_linux_get_longjmp_target
);
1048 set_solib_svr4_fetch_link_map_offsets
1049 (gdbarch
, svr4_ilp32_fetch_link_map_offsets
);
1050 tramp_frame_prepend_unwinder (gdbarch
, &mips_linux_o32_sigframe
);
1051 tramp_frame_prepend_unwinder (gdbarch
, &mips_linux_o32_rt_sigframe
);
1054 set_gdbarch_get_longjmp_target (gdbarch
,
1055 mips_linux_get_longjmp_target
);
1056 set_solib_svr4_fetch_link_map_offsets
1057 (gdbarch
, svr4_ilp32_fetch_link_map_offsets
);
1058 set_gdbarch_long_double_bit (gdbarch
, 128);
1059 /* These floatformats should probably be renamed. MIPS uses
1060 the same 128-bit IEEE floating point format that IA-64 uses,
1061 except that the quiet/signalling NaN bit is reversed (GDB
1062 does not distinguish between quiet and signalling NaNs). */
1063 set_gdbarch_long_double_format (gdbarch
, floatformats_ia64_quad
);
1064 tramp_frame_prepend_unwinder (gdbarch
, &mips_linux_n32_rt_sigframe
);
1067 set_gdbarch_get_longjmp_target (gdbarch
,
1068 mips64_linux_get_longjmp_target
);
1069 set_solib_svr4_fetch_link_map_offsets
1070 (gdbarch
, svr4_lp64_fetch_link_map_offsets
);
1071 set_gdbarch_long_double_bit (gdbarch
, 128);
1072 /* These floatformats should probably be renamed. MIPS uses
1073 the same 128-bit IEEE floating point format that IA-64 uses,
1074 except that the quiet/signalling NaN bit is reversed (GDB
1075 does not distinguish between quiet and signalling NaNs). */
1076 set_gdbarch_long_double_format (gdbarch
, floatformats_ia64_quad
);
1077 tramp_frame_prepend_unwinder (gdbarch
, &mips_linux_n64_rt_sigframe
);
1080 internal_error (__FILE__
, __LINE__
, _("can't handle ABI"));
1084 set_gdbarch_skip_trampoline_code (gdbarch
, find_solib_trampoline_target
);
1085 set_gdbarch_skip_solib_resolver (gdbarch
, mips_linux_skip_resolver
);
1087 set_gdbarch_software_single_step (gdbarch
, mips_software_single_step
);
1089 /* Enable TLS support. */
1090 set_gdbarch_fetch_tls_load_module_address (gdbarch
,
1091 svr4_fetch_objfile_link_map
);
1093 /* Initialize this lazily, to avoid an initialization order
1094 dependency on solib-svr4.c's _initialize routine. */
1095 if (mips_svr4_so_ops
.in_dynsym_resolve_code
== NULL
)
1097 mips_svr4_so_ops
= svr4_so_ops
;
1098 mips_svr4_so_ops
.in_dynsym_resolve_code
1099 = mips_linux_in_dynsym_resolve_code
;
1101 set_solib_ops (gdbarch
, &mips_svr4_so_ops
);
1105 _initialize_mips_linux_tdep (void)
1107 const struct bfd_arch_info
*arch_info
;
1109 for (arch_info
= bfd_lookup_arch (bfd_arch_mips
, 0);
1111 arch_info
= arch_info
->next
)
1113 gdbarch_register_osabi (bfd_arch_mips
, arch_info
->mach
,
1115 mips_linux_init_abi
);
1118 deprecated_add_core_fns (®set_core_fns
);