1 /* Target-dependent code for GNU/Linux on MIPS processors.
3 Copyright (C) 2001, 2002, 2004, 2005, 2006
4 Free Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street, Fifth Floor,
21 Boston, MA 02110-1301, USA. */
26 #include "solib-svr4.h"
28 #include "mips-tdep.h"
29 #include "gdb_string.h"
30 #include "gdb_assert.h"
33 #include "trad-frame.h"
34 #include "tramp-frame.h"
35 #include "floatformat.h"
38 #include "mips-linux-tdep.h"
40 /* Figure out where the longjmp will land.
41 We expect the first arg to be a pointer to the jmp_buf structure
42 from which we extract the pc (MIPS_LINUX_JB_PC) that we will land
43 at. The pc is copied into PC. This routine returns 1 on
46 #define MIPS_LINUX_JB_ELEMENT_SIZE 4
47 #define MIPS_LINUX_JB_PC 0
50 mips_linux_get_longjmp_target (CORE_ADDR
*pc
)
53 char buf
[TARGET_PTR_BIT
/ TARGET_CHAR_BIT
];
55 jb_addr
= read_register (MIPS_A0_REGNUM
);
57 if (target_read_memory (jb_addr
58 + MIPS_LINUX_JB_PC
* MIPS_LINUX_JB_ELEMENT_SIZE
,
59 buf
, TARGET_PTR_BIT
/ TARGET_CHAR_BIT
))
62 *pc
= extract_unsigned_integer (buf
, TARGET_PTR_BIT
/ TARGET_CHAR_BIT
);
67 /* Transform the bits comprising a 32-bit register to the right size
68 for regcache_raw_supply(). This is needed when mips_isa_regsize()
72 supply_32bit_reg (int regnum
, const void *addr
)
74 gdb_byte buf
[MAX_REGISTER_SIZE
];
75 store_signed_integer (buf
, register_size (current_gdbarch
, regnum
),
76 extract_signed_integer (addr
, 4));
77 regcache_raw_supply (current_regcache
, regnum
, buf
);
80 /* Unpack an elf_gregset_t into GDB's register cache. */
83 mips_supply_gregset (mips_elf_gregset_t
*gregsetp
)
86 mips_elf_greg_t
*regp
= *gregsetp
;
87 char zerobuf
[MAX_REGISTER_SIZE
];
89 memset (zerobuf
, 0, MAX_REGISTER_SIZE
);
91 for (regi
= EF_REG0
; regi
<= EF_REG31
; regi
++)
92 supply_32bit_reg ((regi
- EF_REG0
), (char *)(regp
+ regi
));
94 supply_32bit_reg (mips_regnum (current_gdbarch
)->lo
,
95 (char *)(regp
+ EF_LO
));
96 supply_32bit_reg (mips_regnum (current_gdbarch
)->hi
,
97 (char *)(regp
+ EF_HI
));
99 supply_32bit_reg (mips_regnum (current_gdbarch
)->pc
,
100 (char *)(regp
+ EF_CP0_EPC
));
101 supply_32bit_reg (mips_regnum (current_gdbarch
)->badvaddr
,
102 (char *)(regp
+ EF_CP0_BADVADDR
));
103 supply_32bit_reg (MIPS_PS_REGNUM
, (char *)(regp
+ EF_CP0_STATUS
));
104 supply_32bit_reg (mips_regnum (current_gdbarch
)->cause
,
105 (char *)(regp
+ EF_CP0_CAUSE
));
107 /* Fill inaccessible registers with zero. */
108 regcache_raw_supply (current_regcache
, MIPS_UNUSED_REGNUM
, zerobuf
);
109 for (regi
= MIPS_FIRST_EMBED_REGNUM
;
110 regi
< MIPS_LAST_EMBED_REGNUM
;
112 regcache_raw_supply (current_regcache
, regi
, zerobuf
);
115 /* Pack our registers (or one register) into an elf_gregset_t. */
118 mips_fill_gregset (mips_elf_gregset_t
*gregsetp
, int regno
)
121 mips_elf_greg_t
*regp
= *gregsetp
;
126 memset (regp
, 0, sizeof (mips_elf_gregset_t
));
127 for (regi
= 0; regi
< 32; regi
++)
128 mips_fill_gregset (gregsetp
, regi
);
129 mips_fill_gregset (gregsetp
, mips_regnum (current_gdbarch
)->lo
);
130 mips_fill_gregset (gregsetp
, mips_regnum (current_gdbarch
)->hi
);
131 mips_fill_gregset (gregsetp
, mips_regnum (current_gdbarch
)->pc
);
132 mips_fill_gregset (gregsetp
, mips_regnum (current_gdbarch
)->badvaddr
);
133 mips_fill_gregset (gregsetp
, MIPS_PS_REGNUM
);
134 mips_fill_gregset (gregsetp
, mips_regnum (current_gdbarch
)->cause
);
141 dst
= regp
+ regno
+ EF_REG0
;
142 regcache_raw_collect (current_regcache
, regno
, dst
);
146 if (regno
== mips_regnum (current_gdbarch
)->lo
)
148 else if (regno
== mips_regnum (current_gdbarch
)->hi
)
150 else if (regno
== mips_regnum (current_gdbarch
)->pc
)
151 regaddr
= EF_CP0_EPC
;
152 else if (regno
== mips_regnum (current_gdbarch
)->badvaddr
)
153 regaddr
= EF_CP0_BADVADDR
;
154 else if (regno
== MIPS_PS_REGNUM
)
155 regaddr
= EF_CP0_STATUS
;
156 else if (regno
== mips_regnum (current_gdbarch
)->cause
)
157 regaddr
= EF_CP0_CAUSE
;
163 dst
= regp
+ regaddr
;
164 regcache_raw_collect (current_regcache
, regno
, dst
);
168 /* Likewise, unpack an elf_fpregset_t. */
171 mips_supply_fpregset (mips_elf_fpregset_t
*fpregsetp
)
174 char zerobuf
[MAX_REGISTER_SIZE
];
176 memset (zerobuf
, 0, MAX_REGISTER_SIZE
);
178 for (regi
= 0; regi
< 32; regi
++)
179 regcache_raw_supply (current_regcache
, FP0_REGNUM
+ regi
,
180 (char *)(*fpregsetp
+ regi
));
182 regcache_raw_supply (current_regcache
,
183 mips_regnum (current_gdbarch
)->fp_control_status
,
184 (char *)(*fpregsetp
+ 32));
186 /* FIXME: how can we supply FCRIR? The ABI doesn't tell us. */
187 regcache_raw_supply (current_regcache
,
188 mips_regnum (current_gdbarch
)->fp_implementation_revision
,
192 /* Likewise, pack one or all floating point registers into an
196 mips_fill_fpregset (mips_elf_fpregset_t
*fpregsetp
, int regno
)
200 if ((regno
>= FP0_REGNUM
) && (regno
< FP0_REGNUM
+ 32))
202 to
= (char *) (*fpregsetp
+ regno
- FP0_REGNUM
);
203 regcache_raw_collect (current_regcache
, regno
, to
);
205 else if (regno
== mips_regnum (current_gdbarch
)->fp_control_status
)
207 to
= (char *) (*fpregsetp
+ 32);
208 regcache_raw_collect (current_regcache
, regno
, to
);
210 else if (regno
== -1)
214 for (regi
= 0; regi
< 32; regi
++)
215 mips_fill_fpregset (fpregsetp
, FP0_REGNUM
+ regi
);
216 mips_fill_fpregset (fpregsetp
,
217 mips_regnum (current_gdbarch
)->fp_control_status
);
221 /* Map gdb internal register number to ptrace ``address''.
222 These ``addresses'' are normally defined in <asm/ptrace.h>. */
225 mips_linux_register_addr (int regno
, CORE_ADDR blockend
)
229 if (regno
< 0 || regno
>= NUM_REGS
)
230 error (_("Bogon register number %d."), regno
);
234 else if ((regno
>= mips_regnum (current_gdbarch
)->fp0
)
235 && (regno
< mips_regnum (current_gdbarch
)->fp0
+ 32))
236 regaddr
= FPR_BASE
+ (regno
- mips_regnum (current_gdbarch
)->fp0
);
237 else if (regno
== mips_regnum (current_gdbarch
)->pc
)
239 else if (regno
== mips_regnum (current_gdbarch
)->cause
)
241 else if (regno
== mips_regnum (current_gdbarch
)->badvaddr
)
243 else if (regno
== mips_regnum (current_gdbarch
)->lo
)
245 else if (regno
== mips_regnum (current_gdbarch
)->hi
)
247 else if (regno
== mips_regnum (current_gdbarch
)->fp_control_status
)
249 else if (regno
== mips_regnum (current_gdbarch
)->fp_implementation_revision
)
252 error (_("Unknowable register number %d."), regno
);
257 /* Support for 64-bit ABIs. */
259 /* Figure out where the longjmp will land.
260 We expect the first arg to be a pointer to the jmp_buf structure
261 from which we extract the pc (MIPS_LINUX_JB_PC) that we will land
262 at. The pc is copied into PC. This routine returns 1 on
265 /* Details about jmp_buf. */
267 #define MIPS64_LINUX_JB_PC 0
270 mips64_linux_get_longjmp_target (CORE_ADDR
*pc
)
273 void *buf
= alloca (TARGET_PTR_BIT
/ TARGET_CHAR_BIT
);
274 int element_size
= TARGET_PTR_BIT
== 32 ? 4 : 8;
276 jb_addr
= read_register (MIPS_A0_REGNUM
);
278 if (target_read_memory (jb_addr
+ MIPS64_LINUX_JB_PC
* element_size
,
279 buf
, TARGET_PTR_BIT
/ TARGET_CHAR_BIT
))
282 *pc
= extract_unsigned_integer (buf
, TARGET_PTR_BIT
/ TARGET_CHAR_BIT
);
287 /* Register set support functions. These operate on standard 64-bit
288 regsets, but work whether the target is 32-bit or 64-bit. A 32-bit
289 target will still use the 64-bit format for PTRACE_GETREGS. */
291 /* Supply a 64-bit register. */
294 supply_64bit_reg (int regnum
, const gdb_byte
*buf
)
296 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
297 && register_size (current_gdbarch
, regnum
) == 4)
298 regcache_raw_supply (current_regcache
, regnum
, buf
+ 4);
300 regcache_raw_supply (current_regcache
, regnum
, buf
);
303 /* Unpack a 64-bit elf_gregset_t into GDB's register cache. */
306 mips64_supply_gregset (mips64_elf_gregset_t
*gregsetp
)
309 mips64_elf_greg_t
*regp
= *gregsetp
;
310 gdb_byte zerobuf
[MAX_REGISTER_SIZE
];
312 memset (zerobuf
, 0, MAX_REGISTER_SIZE
);
314 for (regi
= MIPS64_EF_REG0
; regi
<= MIPS64_EF_REG31
; regi
++)
315 supply_64bit_reg (regi
- MIPS64_EF_REG0
, (gdb_byte
*)(regp
+ regi
));
317 supply_64bit_reg (mips_regnum (current_gdbarch
)->lo
,
318 (gdb_byte
*) (regp
+ MIPS64_EF_LO
));
319 supply_64bit_reg (mips_regnum (current_gdbarch
)->hi
,
320 (gdb_byte
*) (regp
+ MIPS64_EF_HI
));
322 supply_64bit_reg (mips_regnum (current_gdbarch
)->pc
,
323 (gdb_byte
*) (regp
+ MIPS64_EF_CP0_EPC
));
324 supply_64bit_reg (mips_regnum (current_gdbarch
)->badvaddr
,
325 (gdb_byte
*) (regp
+ MIPS64_EF_CP0_BADVADDR
));
326 supply_64bit_reg (MIPS_PS_REGNUM
,
327 (gdb_byte
*) (regp
+ MIPS64_EF_CP0_STATUS
));
328 supply_64bit_reg (mips_regnum (current_gdbarch
)->cause
,
329 (gdb_byte
*) (regp
+ MIPS64_EF_CP0_CAUSE
));
331 /* Fill inaccessible registers with zero. */
332 regcache_raw_supply (current_regcache
, MIPS_UNUSED_REGNUM
, zerobuf
);
333 for (regi
= MIPS_FIRST_EMBED_REGNUM
;
334 regi
< MIPS_LAST_EMBED_REGNUM
;
336 regcache_raw_supply (current_regcache
, regi
, zerobuf
);
339 /* Pack our registers (or one register) into a 64-bit elf_gregset_t. */
342 mips64_fill_gregset (mips64_elf_gregset_t
*gregsetp
, int regno
)
345 mips64_elf_greg_t
*regp
= *gregsetp
;
350 memset (regp
, 0, sizeof (mips64_elf_gregset_t
));
351 for (regi
= 0; regi
< 32; regi
++)
352 mips64_fill_gregset (gregsetp
, regi
);
353 mips64_fill_gregset (gregsetp
, mips_regnum (current_gdbarch
)->lo
);
354 mips64_fill_gregset (gregsetp
, mips_regnum (current_gdbarch
)->hi
);
355 mips64_fill_gregset (gregsetp
, mips_regnum (current_gdbarch
)->pc
);
356 mips64_fill_gregset (gregsetp
,
357 mips_regnum (current_gdbarch
)->badvaddr
);
358 mips64_fill_gregset (gregsetp
, MIPS_PS_REGNUM
);
359 mips64_fill_gregset (gregsetp
,
360 mips_regnum (current_gdbarch
)->cause
);
366 regaddr
= regno
+ MIPS64_EF_REG0
;
367 else if (regno
== mips_regnum (current_gdbarch
)->lo
)
368 regaddr
= MIPS64_EF_LO
;
369 else if (regno
== mips_regnum (current_gdbarch
)->hi
)
370 regaddr
= MIPS64_EF_HI
;
371 else if (regno
== mips_regnum (current_gdbarch
)->pc
)
372 regaddr
= MIPS64_EF_CP0_EPC
;
373 else if (regno
== mips_regnum (current_gdbarch
)->badvaddr
)
374 regaddr
= MIPS64_EF_CP0_BADVADDR
;
375 else if (regno
== MIPS_PS_REGNUM
)
376 regaddr
= MIPS64_EF_CP0_STATUS
;
377 else if (regno
== mips_regnum (current_gdbarch
)->cause
)
378 regaddr
= MIPS64_EF_CP0_CAUSE
;
384 gdb_byte buf
[MAX_REGISTER_SIZE
];
387 regcache_raw_collect (current_regcache
, regno
, buf
);
388 val
= extract_signed_integer (buf
,
389 register_size (current_gdbarch
, regno
));
390 dst
= regp
+ regaddr
;
391 store_signed_integer (dst
, 8, val
);
395 /* Likewise, unpack an elf_fpregset_t. */
398 mips64_supply_fpregset (mips64_elf_fpregset_t
*fpregsetp
)
402 /* See mips_linux_o32_sigframe_init for a description of the
403 peculiar FP register layout. */
404 if (register_size (current_gdbarch
, FP0_REGNUM
) == 4)
405 for (regi
= 0; regi
< 32; regi
++)
407 gdb_byte
*reg_ptr
= (gdb_byte
*) (*fpregsetp
+ (regi
& ~1));
408 if ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
) != (regi
& 1))
410 regcache_raw_supply (current_regcache
, FP0_REGNUM
+ regi
, reg_ptr
);
413 for (regi
= 0; regi
< 32; regi
++)
414 regcache_raw_supply (current_regcache
, FP0_REGNUM
+ regi
,
415 (char *)(*fpregsetp
+ regi
));
417 supply_32bit_reg (mips_regnum (current_gdbarch
)->fp_control_status
,
418 (gdb_byte
*)(*fpregsetp
+ 32));
420 /* The ABI doesn't tell us how to supply FCRIR, and core dumps don't
421 include it - but the result of PTRACE_GETFPREGS does. The best we
422 can do is to assume that its value is present. */
423 supply_32bit_reg (mips_regnum (current_gdbarch
)->fp_implementation_revision
,
424 (gdb_byte
*)(*fpregsetp
+ 32) + 4);
427 /* Likewise, pack one or all floating point registers into an
431 mips64_fill_fpregset (mips64_elf_fpregset_t
*fpregsetp
, int regno
)
435 if ((regno
>= FP0_REGNUM
) && (regno
< FP0_REGNUM
+ 32))
437 /* See mips_linux_o32_sigframe_init for a description of the
438 peculiar FP register layout. */
439 if (register_size (current_gdbarch
, regno
) == 4)
441 int regi
= regno
- FP0_REGNUM
;
443 to
= (gdb_byte
*) (*fpregsetp
+ (regi
& ~1));
444 if ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
) != (regi
& 1))
446 regcache_raw_collect (current_regcache
, regno
, to
);
450 to
= (gdb_byte
*) (*fpregsetp
+ regno
- FP0_REGNUM
);
451 regcache_raw_collect (current_regcache
, regno
, to
);
454 else if (regno
== mips_regnum (current_gdbarch
)->fp_control_status
)
456 gdb_byte buf
[MAX_REGISTER_SIZE
];
459 regcache_raw_collect (current_regcache
, regno
, buf
);
460 val
= extract_signed_integer (buf
,
461 register_size (current_gdbarch
, regno
));
462 to
= (gdb_byte
*) (*fpregsetp
+ 32);
463 store_signed_integer (to
, 4, val
);
465 else if (regno
== mips_regnum (current_gdbarch
)->fp_implementation_revision
)
467 gdb_byte buf
[MAX_REGISTER_SIZE
];
470 regcache_raw_collect (current_regcache
, regno
, buf
);
471 val
= extract_signed_integer (buf
,
472 register_size (current_gdbarch
, regno
));
473 to
= (gdb_byte
*) (*fpregsetp
+ 32) + 4;
474 store_signed_integer (to
, 4, val
);
476 else if (regno
== -1)
480 for (regi
= 0; regi
< 32; regi
++)
481 mips64_fill_fpregset (fpregsetp
, FP0_REGNUM
+ regi
);
482 mips64_fill_fpregset (fpregsetp
,
483 mips_regnum (current_gdbarch
)->fp_control_status
);
484 mips64_fill_fpregset (fpregsetp
, (mips_regnum (current_gdbarch
)
485 ->fp_implementation_revision
));
490 /* Map gdb internal register number to ptrace ``address''.
491 These ``addresses'' are normally defined in <asm/ptrace.h>. */
494 mips64_linux_register_addr (int regno
, CORE_ADDR blockend
)
498 if (regno
< 0 || regno
>= NUM_REGS
)
499 error (_("Bogon register number %d."), regno
);
503 else if ((regno
>= mips_regnum (current_gdbarch
)->fp0
)
504 && (regno
< mips_regnum (current_gdbarch
)->fp0
+ 32))
505 regaddr
= MIPS64_FPR_BASE
+ (regno
- FP0_REGNUM
);
506 else if (regno
== mips_regnum (current_gdbarch
)->pc
)
508 else if (regno
== mips_regnum (current_gdbarch
)->cause
)
509 regaddr
= MIPS64_CAUSE
;
510 else if (regno
== mips_regnum (current_gdbarch
)->badvaddr
)
511 regaddr
= MIPS64_BADVADDR
;
512 else if (regno
== mips_regnum (current_gdbarch
)->lo
)
513 regaddr
= MIPS64_MMLO
;
514 else if (regno
== mips_regnum (current_gdbarch
)->hi
)
515 regaddr
= MIPS64_MMHI
;
516 else if (regno
== mips_regnum (current_gdbarch
)->fp_control_status
)
517 regaddr
= MIPS64_FPC_CSR
;
518 else if (regno
== mips_regnum (current_gdbarch
)->fp_implementation_revision
)
519 regaddr
= MIPS64_FPC_EIR
;
521 error (_("Unknowable register number %d."), regno
);
526 /* Use a local version of this function to get the correct types for
527 regsets, until multi-arch core support is ready. */
530 fetch_core_registers (char *core_reg_sect
, unsigned core_reg_size
,
531 int which
, CORE_ADDR reg_addr
)
533 mips_elf_gregset_t gregset
;
534 mips_elf_fpregset_t fpregset
;
535 mips64_elf_gregset_t gregset64
;
536 mips64_elf_fpregset_t fpregset64
;
540 if (core_reg_size
== sizeof (gregset
))
542 memcpy ((char *) &gregset
, core_reg_sect
, sizeof (gregset
));
543 mips_supply_gregset (&gregset
);
545 else if (core_reg_size
== sizeof (gregset64
))
547 memcpy ((char *) &gregset64
, core_reg_sect
, sizeof (gregset64
));
548 mips64_supply_gregset (&gregset64
);
552 warning (_("wrong size gregset struct in core file"));
557 if (core_reg_size
== sizeof (fpregset
))
559 memcpy ((char *) &fpregset
, core_reg_sect
, sizeof (fpregset
));
560 mips_supply_fpregset (&fpregset
);
562 else if (core_reg_size
== sizeof (fpregset64
))
564 memcpy ((char *) &fpregset64
, core_reg_sect
,
565 sizeof (fpregset64
));
566 mips64_supply_fpregset (&fpregset64
);
570 warning (_("wrong size fpregset struct in core file"));
575 /* Register that we are able to handle ELF file formats using standard
576 procfs "regset" structures. */
578 static struct core_fns regset_core_fns
=
580 bfd_target_elf_flavour
, /* core_flavour */
581 default_check_format
, /* check_format */
582 default_core_sniffer
, /* core_sniffer */
583 fetch_core_registers
, /* core_read_registers */
587 /* Handle for obtaining pointer to the current register_addr()
588 function for a given architecture. */
589 static struct gdbarch_data
*register_addr_data
;
592 register_addr (int regno
, CORE_ADDR blockend
)
594 CORE_ADDR (*register_addr_ptr
) (int, CORE_ADDR
) =
595 gdbarch_data (current_gdbarch
, register_addr_data
);
597 gdb_assert (register_addr_ptr
!= 0);
599 return register_addr_ptr (regno
, blockend
);
603 set_mips_linux_register_addr (struct gdbarch
*gdbarch
,
604 CORE_ADDR (*register_addr_ptr
) (int,
607 deprecated_set_gdbarch_data (gdbarch
, register_addr_data
,
612 init_register_addr_data (struct gdbarch
*gdbarch
)
617 /* Check the code at PC for a dynamic linker lazy resolution stub.
618 Because they aren't in the .plt section, we pattern-match on the
619 code generated by GNU ld. They look like this:
626 (with the appropriate doubleword instructions for N64). Also
627 return the dynamic symbol index used in the last instruction. */
630 mips_linux_in_dynsym_stub (CORE_ADDR pc
, char *name
)
632 unsigned char buf
[28], *p
;
633 ULONGEST insn
, insn1
;
634 int n64
= (mips_abi (current_gdbarch
) == MIPS_ABI_N64
);
636 read_memory (pc
- 12, buf
, 28);
640 /* ld t9,0x8010(gp) */
645 /* lw t9,0x8010(gp) */
652 insn
= extract_unsigned_integer (p
, 4);
660 insn
= extract_unsigned_integer (p
+ 4, 4);
664 if (insn
!= 0x03e0782d)
670 if (insn
!= 0x03e07821)
674 insn
= extract_unsigned_integer (p
+ 8, 4);
676 if (insn
!= 0x0320f809)
679 insn
= extract_unsigned_integer (p
+ 12, 4);
682 /* daddiu t8,zero,0 */
683 if ((insn
& 0xffff0000) != 0x64180000)
688 /* addiu t8,zero,0 */
689 if ((insn
& 0xffff0000) != 0x24180000)
693 return (insn
& 0xffff);
696 /* Return non-zero iff PC belongs to the dynamic linker resolution
697 code or to a stub. */
700 mips_linux_in_dynsym_resolve_code (CORE_ADDR pc
)
702 /* Check whether PC is in the dynamic linker. This also checks
703 whether it is in the .plt section, which MIPS does not use. */
704 if (in_solib_dynsym_resolve_code (pc
))
707 /* Pattern match for the stub. It would be nice if there were a
708 more efficient way to avoid this check. */
709 if (mips_linux_in_dynsym_stub (pc
, NULL
))
715 /* See the comments for SKIP_SOLIB_RESOLVER at the top of infrun.c,
716 and glibc_skip_solib_resolver in glibc-tdep.c. The normal glibc
717 implementation of this triggers at "fixup" from the same objfile as
718 "_dl_runtime_resolve"; MIPS GNU/Linux can trigger at
719 "__dl_runtime_resolve" directly. An unresolved PLT entry will
720 point to _dl_runtime_resolve, which will first call
721 __dl_runtime_resolve, and then pass control to the resolved
725 mips_linux_skip_resolver (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
727 struct minimal_symbol
*resolver
;
729 resolver
= lookup_minimal_symbol ("__dl_runtime_resolve", NULL
, NULL
);
731 if (resolver
&& SYMBOL_VALUE_ADDRESS (resolver
) == pc
)
732 return frame_pc_unwind (get_current_frame ());
737 /* Signal trampoline support. There are four supported layouts for a
738 signal frame: o32 sigframe, o32 rt_sigframe, n32 rt_sigframe, and
739 n64 rt_sigframe. We handle them all independently; not the most
740 efficient way, but simplest. First, declare all the unwinders. */
742 static void mips_linux_o32_sigframe_init (const struct tramp_frame
*self
,
743 struct frame_info
*next_frame
,
744 struct trad_frame_cache
*this_cache
,
747 static void mips_linux_n32n64_sigframe_init (const struct tramp_frame
*self
,
748 struct frame_info
*next_frame
,
749 struct trad_frame_cache
*this_cache
,
752 #define MIPS_NR_LINUX 4000
753 #define MIPS_NR_N64_LINUX 5000
754 #define MIPS_NR_N32_LINUX 6000
756 #define MIPS_NR_sigreturn MIPS_NR_LINUX + 119
757 #define MIPS_NR_rt_sigreturn MIPS_NR_LINUX + 193
758 #define MIPS_NR_N64_rt_sigreturn MIPS_NR_N64_LINUX + 211
759 #define MIPS_NR_N32_rt_sigreturn MIPS_NR_N32_LINUX + 211
761 #define MIPS_INST_LI_V0_SIGRETURN 0x24020000 + MIPS_NR_sigreturn
762 #define MIPS_INST_LI_V0_RT_SIGRETURN 0x24020000 + MIPS_NR_rt_sigreturn
763 #define MIPS_INST_LI_V0_N64_RT_SIGRETURN 0x24020000 + MIPS_NR_N64_rt_sigreturn
764 #define MIPS_INST_LI_V0_N32_RT_SIGRETURN 0x24020000 + MIPS_NR_N32_rt_sigreturn
765 #define MIPS_INST_SYSCALL 0x0000000c
767 static const struct tramp_frame mips_linux_o32_sigframe
= {
771 { MIPS_INST_LI_V0_SIGRETURN
, -1 },
772 { MIPS_INST_SYSCALL
, -1 },
773 { TRAMP_SENTINEL_INSN
, -1 }
775 mips_linux_o32_sigframe_init
778 static const struct tramp_frame mips_linux_o32_rt_sigframe
= {
782 { MIPS_INST_LI_V0_RT_SIGRETURN
, -1 },
783 { MIPS_INST_SYSCALL
, -1 },
784 { TRAMP_SENTINEL_INSN
, -1 } },
785 mips_linux_o32_sigframe_init
788 static const struct tramp_frame mips_linux_n32_rt_sigframe
= {
792 { MIPS_INST_LI_V0_N32_RT_SIGRETURN
, -1 },
793 { MIPS_INST_SYSCALL
, -1 },
794 { TRAMP_SENTINEL_INSN
, -1 }
796 mips_linux_n32n64_sigframe_init
799 static const struct tramp_frame mips_linux_n64_rt_sigframe
= {
802 { MIPS_INST_LI_V0_N64_RT_SIGRETURN
,
804 TRAMP_SENTINEL_INSN
},
805 mips_linux_n32n64_sigframe_init
809 /* The unwinder for o32 signal frames. The legacy structures look
813 u32 sf_ass[4]; [argument save space for o32]
814 u32 sf_code[2]; [signal trampoline]
815 struct sigcontext sf_sc;
820 unsigned int sc_regmask; [Unused]
821 unsigned int sc_status;
822 unsigned long long sc_pc;
823 unsigned long long sc_regs[32];
824 unsigned long long sc_fpregs[32];
825 unsigned int sc_ownedfp;
826 unsigned int sc_fpc_csr;
827 unsigned int sc_fpc_eir; [Unused]
828 unsigned int sc_used_math;
829 unsigned int sc_ssflags; [Unused]
830 [Alignment hole of four bytes]
831 unsigned long long sc_mdhi;
832 unsigned long long sc_mdlo;
834 unsigned int sc_cause; [Unused]
835 unsigned int sc_badvaddr; [Unused]
837 unsigned long sc_sigset[4]; [kernel's sigset_t]
840 The RT signal frames look like this:
843 u32 rs_ass[4]; [argument save space for o32]
844 u32 rs_code[2] [signal trampoline]
845 struct siginfo rs_info;
846 struct ucontext rs_uc;
850 unsigned long uc_flags;
851 struct ucontext *uc_link;
853 [Alignment hole of four bytes]
854 struct sigcontext uc_mcontext;
859 #define SIGFRAME_CODE_OFFSET (4 * 4)
860 #define SIGFRAME_SIGCONTEXT_OFFSET (6 * 4)
862 #define RTSIGFRAME_SIGINFO_SIZE 128
863 #define STACK_T_SIZE (3 * 4)
864 #define UCONTEXT_SIGCONTEXT_OFFSET (2 * 4 + STACK_T_SIZE + 4)
865 #define RTSIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \
866 + RTSIGFRAME_SIGINFO_SIZE \
867 + UCONTEXT_SIGCONTEXT_OFFSET)
869 #define SIGCONTEXT_PC (1 * 8)
870 #define SIGCONTEXT_REGS (2 * 8)
871 #define SIGCONTEXT_FPREGS (34 * 8)
872 #define SIGCONTEXT_FPCSR (66 * 8 + 4)
873 #define SIGCONTEXT_HI (69 * 8)
874 #define SIGCONTEXT_LO (70 * 8)
875 #define SIGCONTEXT_CAUSE (71 * 8 + 0)
876 #define SIGCONTEXT_BADVADDR (71 * 8 + 4)
878 #define SIGCONTEXT_REG_SIZE 8
881 mips_linux_o32_sigframe_init (const struct tramp_frame
*self
,
882 struct frame_info
*next_frame
,
883 struct trad_frame_cache
*this_cache
,
886 int ireg
, reg_position
;
887 CORE_ADDR sigcontext_base
= func
- SIGFRAME_CODE_OFFSET
;
888 const struct mips_regnum
*regs
= mips_regnum (current_gdbarch
);
891 if (self
== &mips_linux_o32_sigframe
)
892 sigcontext_base
+= SIGFRAME_SIGCONTEXT_OFFSET
;
894 sigcontext_base
+= RTSIGFRAME_SIGCONTEXT_OFFSET
;
896 /* I'm not proud of this hack. Eventually we will have the
897 infrastructure to indicate the size of saved registers on a
898 per-frame basis, but right now we don't; the kernel saves eight
899 bytes but we only want four. Use regs_base to access any
901 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
902 regs_base
= sigcontext_base
+ 4;
904 regs_base
= sigcontext_base
;
907 trad_frame_set_reg_addr (this_cache
, ORIG_ZERO_REGNUM
+ NUM_REGS
,
908 regs_base
+ SIGCONTEXT_REGS
);
911 for (ireg
= 1; ireg
< 32; ireg
++)
912 trad_frame_set_reg_addr (this_cache
,
913 ireg
+ MIPS_ZERO_REGNUM
+ NUM_REGS
,
914 regs_base
+ SIGCONTEXT_REGS
915 + ireg
* SIGCONTEXT_REG_SIZE
);
917 /* The way that floating point registers are saved, unfortunately,
918 depends on the architecture the kernel is built for. For the r3000 and
919 tx39, four bytes of each register are at the beginning of each of the
920 32 eight byte slots. For everything else, the registers are saved
921 using double precision; only the even-numbered slots are initialized,
922 and the high bits are the odd-numbered register. Assume the latter
923 layout, since we can't tell, and it's much more common. Which bits are
924 the "high" bits depends on endianness. */
925 for (ireg
= 0; ireg
< 32; ireg
++)
926 if ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
) != (ireg
& 1))
927 trad_frame_set_reg_addr (this_cache
, ireg
+ regs
->fp0
+ NUM_REGS
,
928 sigcontext_base
+ SIGCONTEXT_FPREGS
+ 4
929 + (ireg
& ~1) * SIGCONTEXT_REG_SIZE
);
931 trad_frame_set_reg_addr (this_cache
, ireg
+ regs
->fp0
+ NUM_REGS
,
932 sigcontext_base
+ SIGCONTEXT_FPREGS
933 + (ireg
& ~1) * SIGCONTEXT_REG_SIZE
);
935 trad_frame_set_reg_addr (this_cache
, regs
->pc
+ NUM_REGS
,
936 regs_base
+ SIGCONTEXT_PC
);
938 trad_frame_set_reg_addr (this_cache
,
939 regs
->fp_control_status
+ NUM_REGS
,
940 sigcontext_base
+ SIGCONTEXT_FPCSR
);
941 trad_frame_set_reg_addr (this_cache
, regs
->hi
+ NUM_REGS
,
942 regs_base
+ SIGCONTEXT_HI
);
943 trad_frame_set_reg_addr (this_cache
, regs
->lo
+ NUM_REGS
,
944 regs_base
+ SIGCONTEXT_LO
);
945 trad_frame_set_reg_addr (this_cache
, regs
->cause
+ NUM_REGS
,
946 sigcontext_base
+ SIGCONTEXT_CAUSE
);
947 trad_frame_set_reg_addr (this_cache
, regs
->badvaddr
+ NUM_REGS
,
948 sigcontext_base
+ SIGCONTEXT_BADVADDR
);
950 /* Choice of the bottom of the sigframe is somewhat arbitrary. */
951 trad_frame_set_id (this_cache
,
952 frame_id_build (func
- SIGFRAME_CODE_OFFSET
,
957 /* For N32/N64 things look different. There is no non-rt signal frame.
959 struct rt_sigframe_n32 {
960 u32 rs_ass[4]; [ argument save space for o32 ]
961 u32 rs_code[2]; [ signal trampoline ]
962 struct siginfo rs_info;
963 struct ucontextn32 rs_uc;
970 struct sigcontext uc_mcontext;
971 sigset_t uc_sigmask; [ mask last for extensibility ]
974 struct rt_sigframe_n32 {
975 u32 rs_ass[4]; [ argument save space for o32 ]
976 u32 rs_code[2]; [ signal trampoline ]
977 struct siginfo rs_info;
978 struct ucontext rs_uc;
982 unsigned long uc_flags;
983 struct ucontext *uc_link;
985 struct sigcontext uc_mcontext;
986 sigset_t uc_sigmask; [ mask last for extensibility ]
989 And the sigcontext is different (this is for both n32 and n64):
992 unsigned long long sc_regs[32];
993 unsigned long long sc_fpregs[32];
994 unsigned long long sc_mdhi;
995 unsigned long long sc_mdlo;
996 unsigned long long sc_pc;
997 unsigned int sc_status;
998 unsigned int sc_fpc_csr;
999 unsigned int sc_fpc_eir;
1000 unsigned int sc_used_math;
1001 unsigned int sc_cause;
1002 unsigned int sc_badvaddr;
1006 #define N32_STACK_T_SIZE STACK_T_SIZE
1007 #define N64_STACK_T_SIZE (2 * 8 + 4)
1008 #define N32_UCONTEXT_SIGCONTEXT_OFFSET (2 * 4 + N32_STACK_T_SIZE + 4)
1009 #define N64_UCONTEXT_SIGCONTEXT_OFFSET (2 * 8 + N64_STACK_T_SIZE + 4)
1010 #define N32_SIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \
1011 + RTSIGFRAME_SIGINFO_SIZE \
1012 + N32_UCONTEXT_SIGCONTEXT_OFFSET)
1013 #define N64_SIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \
1014 + RTSIGFRAME_SIGINFO_SIZE \
1015 + N64_UCONTEXT_SIGCONTEXT_OFFSET)
1017 #define N64_SIGCONTEXT_REGS (0 * 8)
1018 #define N64_SIGCONTEXT_FPREGS (32 * 8)
1019 #define N64_SIGCONTEXT_HI (64 * 8)
1020 #define N64_SIGCONTEXT_LO (65 * 8)
1021 #define N64_SIGCONTEXT_PC (66 * 8)
1022 #define N64_SIGCONTEXT_FPCSR (67 * 8 + 1 * 4)
1023 #define N64_SIGCONTEXT_FIR (67 * 8 + 2 * 4)
1024 #define N64_SIGCONTEXT_CAUSE (67 * 8 + 4 * 4)
1025 #define N64_SIGCONTEXT_BADVADDR (67 * 8 + 5 * 4)
1027 #define N64_SIGCONTEXT_REG_SIZE 8
1030 mips_linux_n32n64_sigframe_init (const struct tramp_frame
*self
,
1031 struct frame_info
*next_frame
,
1032 struct trad_frame_cache
*this_cache
,
1035 int ireg
, reg_position
;
1036 CORE_ADDR sigcontext_base
= func
- SIGFRAME_CODE_OFFSET
;
1037 const struct mips_regnum
*regs
= mips_regnum (current_gdbarch
);
1039 if (self
== &mips_linux_n32_rt_sigframe
)
1040 sigcontext_base
+= N32_SIGFRAME_SIGCONTEXT_OFFSET
;
1042 sigcontext_base
+= N64_SIGFRAME_SIGCONTEXT_OFFSET
;
1045 trad_frame_set_reg_addr (this_cache
, ORIG_ZERO_REGNUM
+ NUM_REGS
,
1046 sigcontext_base
+ N64_SIGCONTEXT_REGS
);
1049 for (ireg
= 1; ireg
< 32; ireg
++)
1050 trad_frame_set_reg_addr (this_cache
,
1051 ireg
+ MIPS_ZERO_REGNUM
+ NUM_REGS
,
1052 sigcontext_base
+ N64_SIGCONTEXT_REGS
1053 + ireg
* N64_SIGCONTEXT_REG_SIZE
);
1055 for (ireg
= 0; ireg
< 32; ireg
++)
1056 trad_frame_set_reg_addr (this_cache
, ireg
+ regs
->fp0
+ NUM_REGS
,
1057 sigcontext_base
+ N64_SIGCONTEXT_FPREGS
1058 + ireg
* N64_SIGCONTEXT_REG_SIZE
);
1060 trad_frame_set_reg_addr (this_cache
, regs
->pc
+ NUM_REGS
,
1061 sigcontext_base
+ N64_SIGCONTEXT_PC
);
1063 trad_frame_set_reg_addr (this_cache
,
1064 regs
->fp_control_status
+ NUM_REGS
,
1065 sigcontext_base
+ N64_SIGCONTEXT_FPCSR
);
1066 trad_frame_set_reg_addr (this_cache
, regs
->hi
+ NUM_REGS
,
1067 sigcontext_base
+ N64_SIGCONTEXT_HI
);
1068 trad_frame_set_reg_addr (this_cache
, regs
->lo
+ NUM_REGS
,
1069 sigcontext_base
+ N64_SIGCONTEXT_LO
);
1070 trad_frame_set_reg_addr (this_cache
, regs
->cause
+ NUM_REGS
,
1071 sigcontext_base
+ N64_SIGCONTEXT_CAUSE
);
1072 trad_frame_set_reg_addr (this_cache
, regs
->badvaddr
+ NUM_REGS
,
1073 sigcontext_base
+ N64_SIGCONTEXT_BADVADDR
);
1075 /* Choice of the bottom of the sigframe is somewhat arbitrary. */
1076 trad_frame_set_id (this_cache
,
1077 frame_id_build (func
- SIGFRAME_CODE_OFFSET
,
1081 /* Wrapper functions. These are only used by libthread_db. */
1084 supply_gregset (mips_elf_gregset_t
*gregsetp
)
1086 if (mips_isa_regsize (current_gdbarch
) == 4)
1087 mips_supply_gregset (gregsetp
);
1089 mips64_supply_gregset ((void *) gregsetp
);
1093 fill_gregset (mips_elf_gregset_t
*gregsetp
, int regno
)
1095 if (mips_isa_regsize (current_gdbarch
) == 4)
1096 mips_fill_gregset (gregsetp
, regno
);
1098 mips64_fill_gregset ((void *) gregsetp
, regno
);
1101 /* Likewise, unpack an elf_fpregset_t. */
1104 supply_fpregset (mips_elf_fpregset_t
*fpregsetp
)
1106 if (mips_isa_regsize (current_gdbarch
) == 4)
1107 mips_supply_fpregset (fpregsetp
);
1109 mips64_supply_fpregset ((void *) fpregsetp
);
1112 /* Likewise, pack one or all floating point registers into an
1116 fill_fpregset (mips_elf_fpregset_t
*fpregsetp
, int regno
)
1118 if (mips_isa_regsize (current_gdbarch
) == 4)
1119 mips_fill_fpregset (fpregsetp
, regno
);
1121 mips64_fill_fpregset ((void *) fpregsetp
, regno
);
1124 /* Initialize one of the GNU/Linux OS ABIs. */
1127 mips_linux_init_abi (struct gdbarch_info info
,
1128 struct gdbarch
*gdbarch
)
1130 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1131 enum mips_abi abi
= mips_abi (gdbarch
);
1136 set_gdbarch_get_longjmp_target (gdbarch
,
1137 mips_linux_get_longjmp_target
);
1138 set_solib_svr4_fetch_link_map_offsets
1139 (gdbarch
, svr4_ilp32_fetch_link_map_offsets
);
1140 set_mips_linux_register_addr (gdbarch
, mips_linux_register_addr
);
1141 tramp_frame_prepend_unwinder (gdbarch
, &mips_linux_o32_sigframe
);
1142 tramp_frame_prepend_unwinder (gdbarch
, &mips_linux_o32_rt_sigframe
);
1145 set_gdbarch_get_longjmp_target (gdbarch
,
1146 mips_linux_get_longjmp_target
);
1147 set_solib_svr4_fetch_link_map_offsets
1148 (gdbarch
, svr4_ilp32_fetch_link_map_offsets
);
1149 set_mips_linux_register_addr (gdbarch
, mips64_linux_register_addr
);
1150 set_gdbarch_long_double_bit (gdbarch
, 128);
1151 /* These floatformats should probably be renamed. MIPS uses
1152 the same 128-bit IEEE floating point format that IA-64 uses,
1153 except that the quiet/signalling NaN bit is reversed (GDB
1154 does not distinguish between quiet and signalling NaNs). */
1155 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1156 set_gdbarch_long_double_format (gdbarch
, &floatformat_ia64_quad_big
);
1158 set_gdbarch_long_double_format (gdbarch
, &floatformat_ia64_quad_little
);
1159 tramp_frame_prepend_unwinder (gdbarch
, &mips_linux_n32_rt_sigframe
);
1162 set_gdbarch_get_longjmp_target (gdbarch
,
1163 mips64_linux_get_longjmp_target
);
1164 set_solib_svr4_fetch_link_map_offsets
1165 (gdbarch
, svr4_lp64_fetch_link_map_offsets
);
1166 set_mips_linux_register_addr (gdbarch
, mips64_linux_register_addr
);
1167 set_gdbarch_long_double_bit (gdbarch
, 128);
1168 /* These floatformats should probably be renamed. MIPS uses
1169 the same 128-bit IEEE floating point format that IA-64 uses,
1170 except that the quiet/signalling NaN bit is reversed (GDB
1171 does not distinguish between quiet and signalling NaNs). */
1172 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1173 set_gdbarch_long_double_format (gdbarch
, &floatformat_ia64_quad_big
);
1175 set_gdbarch_long_double_format (gdbarch
, &floatformat_ia64_quad_little
);
1176 tramp_frame_prepend_unwinder (gdbarch
, &mips_linux_n64_rt_sigframe
);
1179 internal_error (__FILE__
, __LINE__
, _("can't handle ABI"));
1183 set_gdbarch_skip_trampoline_code (gdbarch
, find_solib_trampoline_target
);
1184 set_gdbarch_skip_solib_resolver (gdbarch
, mips_linux_skip_resolver
);
1186 set_gdbarch_software_single_step (gdbarch
, mips_software_single_step
);
1188 /* Enable TLS support. */
1189 set_gdbarch_fetch_tls_load_module_address (gdbarch
,
1190 svr4_fetch_objfile_link_map
);
1194 _initialize_mips_linux_tdep (void)
1196 const struct bfd_arch_info
*arch_info
;
1198 register_addr_data
=
1199 gdbarch_data_register_post_init (init_register_addr_data
);
1201 for (arch_info
= bfd_lookup_arch (bfd_arch_mips
, 0);
1203 arch_info
= arch_info
->next
)
1205 gdbarch_register_osabi (bfd_arch_mips
, arch_info
->mach
,
1207 mips_linux_init_abi
);
1210 deprecated_add_core_fns (®set_core_fns
);