1 /* Target-dependent code for GNU/Linux on MIPS processors.
3 Copyright (C) 2001, 2002, 2004, 2005, 2006
4 Free Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street, Fifth Floor,
21 Boston, MA 02110-1301, USA. */
26 #include "solib-svr4.h"
28 #include "mips-tdep.h"
29 #include "gdb_string.h"
30 #include "gdb_assert.h"
33 #include "trad-frame.h"
34 #include "tramp-frame.h"
35 #include "floatformat.h"
37 #include "mips-linux-tdep.h"
39 /* Figure out where the longjmp will land.
40 We expect the first arg to be a pointer to the jmp_buf structure
41 from which we extract the pc (MIPS_LINUX_JB_PC) that we will land
42 at. The pc is copied into PC. This routine returns 1 on
45 #define MIPS_LINUX_JB_ELEMENT_SIZE 4
46 #define MIPS_LINUX_JB_PC 0
49 mips_linux_get_longjmp_target (CORE_ADDR
*pc
)
52 char buf
[TARGET_PTR_BIT
/ TARGET_CHAR_BIT
];
54 jb_addr
= read_register (MIPS_A0_REGNUM
);
56 if (target_read_memory (jb_addr
57 + MIPS_LINUX_JB_PC
* MIPS_LINUX_JB_ELEMENT_SIZE
,
58 buf
, TARGET_PTR_BIT
/ TARGET_CHAR_BIT
))
61 *pc
= extract_unsigned_integer (buf
, TARGET_PTR_BIT
/ TARGET_CHAR_BIT
);
66 /* Transform the bits comprising a 32-bit register to the right size
67 for regcache_raw_supply(). This is needed when mips_isa_regsize()
71 supply_32bit_reg (int regnum
, const void *addr
)
73 gdb_byte buf
[MAX_REGISTER_SIZE
];
74 store_signed_integer (buf
, register_size (current_gdbarch
, regnum
),
75 extract_signed_integer (addr
, 4));
76 regcache_raw_supply (current_regcache
, regnum
, buf
);
79 /* Unpack an elf_gregset_t into GDB's register cache. */
82 mips_supply_gregset (mips_elf_gregset_t
*gregsetp
)
85 mips_elf_greg_t
*regp
= *gregsetp
;
86 char zerobuf
[MAX_REGISTER_SIZE
];
88 memset (zerobuf
, 0, MAX_REGISTER_SIZE
);
90 for (regi
= EF_REG0
; regi
<= EF_REG31
; regi
++)
91 supply_32bit_reg ((regi
- EF_REG0
), (char *)(regp
+ regi
));
93 supply_32bit_reg (mips_regnum (current_gdbarch
)->lo
,
94 (char *)(regp
+ EF_LO
));
95 supply_32bit_reg (mips_regnum (current_gdbarch
)->hi
,
96 (char *)(regp
+ EF_HI
));
98 supply_32bit_reg (mips_regnum (current_gdbarch
)->pc
,
99 (char *)(regp
+ EF_CP0_EPC
));
100 supply_32bit_reg (mips_regnum (current_gdbarch
)->badvaddr
,
101 (char *)(regp
+ EF_CP0_BADVADDR
));
102 supply_32bit_reg (MIPS_PS_REGNUM
, (char *)(regp
+ EF_CP0_STATUS
));
103 supply_32bit_reg (mips_regnum (current_gdbarch
)->cause
,
104 (char *)(regp
+ EF_CP0_CAUSE
));
106 /* Fill inaccessible registers with zero. */
107 regcache_raw_supply (current_regcache
, MIPS_UNUSED_REGNUM
, zerobuf
);
108 for (regi
= MIPS_FIRST_EMBED_REGNUM
;
109 regi
< MIPS_LAST_EMBED_REGNUM
;
111 regcache_raw_supply (current_regcache
, regi
, zerobuf
);
114 /* Pack our registers (or one register) into an elf_gregset_t. */
117 mips_fill_gregset (mips_elf_gregset_t
*gregsetp
, int regno
)
120 mips_elf_greg_t
*regp
= *gregsetp
;
125 memset (regp
, 0, sizeof (mips_elf_gregset_t
));
126 for (regi
= 0; regi
< 32; regi
++)
127 mips_fill_gregset (gregsetp
, regi
);
128 mips_fill_gregset (gregsetp
, mips_regnum (current_gdbarch
)->lo
);
129 mips_fill_gregset (gregsetp
, mips_regnum (current_gdbarch
)->hi
);
130 mips_fill_gregset (gregsetp
, mips_regnum (current_gdbarch
)->pc
);
131 mips_fill_gregset (gregsetp
, mips_regnum (current_gdbarch
)->badvaddr
);
132 mips_fill_gregset (gregsetp
, MIPS_PS_REGNUM
);
133 mips_fill_gregset (gregsetp
, mips_regnum (current_gdbarch
)->cause
);
140 dst
= regp
+ regno
+ EF_REG0
;
141 regcache_raw_collect (current_regcache
, regno
, dst
);
145 if (regno
== mips_regnum (current_gdbarch
)->lo
)
147 else if (regno
== mips_regnum (current_gdbarch
)->hi
)
149 else if (regno
== mips_regnum (current_gdbarch
)->pc
)
150 regaddr
= EF_CP0_EPC
;
151 else if (regno
== mips_regnum (current_gdbarch
)->badvaddr
)
152 regaddr
= EF_CP0_BADVADDR
;
153 else if (regno
== MIPS_PS_REGNUM
)
154 regaddr
= EF_CP0_STATUS
;
155 else if (regno
== mips_regnum (current_gdbarch
)->cause
)
156 regaddr
= EF_CP0_CAUSE
;
162 dst
= regp
+ regaddr
;
163 regcache_raw_collect (current_regcache
, regno
, dst
);
167 /* Likewise, unpack an elf_fpregset_t. */
170 mips_supply_fpregset (mips_elf_fpregset_t
*fpregsetp
)
173 char zerobuf
[MAX_REGISTER_SIZE
];
175 memset (zerobuf
, 0, MAX_REGISTER_SIZE
);
177 for (regi
= 0; regi
< 32; regi
++)
178 regcache_raw_supply (current_regcache
, FP0_REGNUM
+ regi
,
179 (char *)(*fpregsetp
+ regi
));
181 regcache_raw_supply (current_regcache
,
182 mips_regnum (current_gdbarch
)->fp_control_status
,
183 (char *)(*fpregsetp
+ 32));
185 /* FIXME: how can we supply FCRIR? The ABI doesn't tell us. */
186 regcache_raw_supply (current_regcache
,
187 mips_regnum (current_gdbarch
)->fp_implementation_revision
,
191 /* Likewise, pack one or all floating point registers into an
195 mips_fill_fpregset (mips_elf_fpregset_t
*fpregsetp
, int regno
)
199 if ((regno
>= FP0_REGNUM
) && (regno
< FP0_REGNUM
+ 32))
201 to
= (char *) (*fpregsetp
+ regno
- FP0_REGNUM
);
202 regcache_raw_collect (current_regcache
, regno
, to
);
204 else if (regno
== mips_regnum (current_gdbarch
)->fp_control_status
)
206 to
= (char *) (*fpregsetp
+ 32);
207 regcache_raw_collect (current_regcache
, regno
, to
);
209 else if (regno
== -1)
213 for (regi
= 0; regi
< 32; regi
++)
214 mips_fill_fpregset (fpregsetp
, FP0_REGNUM
+ regi
);
215 mips_fill_fpregset (fpregsetp
,
216 mips_regnum (current_gdbarch
)->fp_control_status
);
220 /* Map gdb internal register number to ptrace ``address''.
221 These ``addresses'' are normally defined in <asm/ptrace.h>. */
224 mips_linux_register_addr (int regno
, CORE_ADDR blockend
)
228 if (regno
< 0 || regno
>= NUM_REGS
)
229 error (_("Bogon register number %d."), regno
);
233 else if ((regno
>= mips_regnum (current_gdbarch
)->fp0
)
234 && (regno
< mips_regnum (current_gdbarch
)->fp0
+ 32))
235 regaddr
= FPR_BASE
+ (regno
- mips_regnum (current_gdbarch
)->fp0
);
236 else if (regno
== mips_regnum (current_gdbarch
)->pc
)
238 else if (regno
== mips_regnum (current_gdbarch
)->cause
)
240 else if (regno
== mips_regnum (current_gdbarch
)->badvaddr
)
242 else if (regno
== mips_regnum (current_gdbarch
)->lo
)
244 else if (regno
== mips_regnum (current_gdbarch
)->hi
)
246 else if (regno
== mips_regnum (current_gdbarch
)->fp_control_status
)
248 else if (regno
== mips_regnum (current_gdbarch
)->fp_implementation_revision
)
251 error (_("Unknowable register number %d."), regno
);
256 /* Support for 64-bit ABIs. */
258 /* Figure out where the longjmp will land.
259 We expect the first arg to be a pointer to the jmp_buf structure
260 from which we extract the pc (MIPS_LINUX_JB_PC) that we will land
261 at. The pc is copied into PC. This routine returns 1 on
264 /* Details about jmp_buf. */
266 #define MIPS64_LINUX_JB_PC 0
269 mips64_linux_get_longjmp_target (CORE_ADDR
*pc
)
272 void *buf
= alloca (TARGET_PTR_BIT
/ TARGET_CHAR_BIT
);
273 int element_size
= TARGET_PTR_BIT
== 32 ? 4 : 8;
275 jb_addr
= read_register (MIPS_A0_REGNUM
);
277 if (target_read_memory (jb_addr
+ MIPS64_LINUX_JB_PC
* element_size
,
278 buf
, TARGET_PTR_BIT
/ TARGET_CHAR_BIT
))
281 *pc
= extract_unsigned_integer (buf
, TARGET_PTR_BIT
/ TARGET_CHAR_BIT
);
286 /* Register set support functions. These operate on standard 64-bit
287 regsets, but work whether the target is 32-bit or 64-bit. A 32-bit
288 target will still use the 64-bit format for PTRACE_GETREGS. */
290 /* Supply a 64-bit register. */
293 supply_64bit_reg (int regnum
, const gdb_byte
*buf
)
295 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
296 && register_size (current_gdbarch
, regnum
) == 4)
297 regcache_raw_supply (current_regcache
, regnum
, buf
+ 4);
299 regcache_raw_supply (current_regcache
, regnum
, buf
);
302 /* Unpack a 64-bit elf_gregset_t into GDB's register cache. */
305 mips64_supply_gregset (mips64_elf_gregset_t
*gregsetp
)
308 mips64_elf_greg_t
*regp
= *gregsetp
;
309 gdb_byte zerobuf
[MAX_REGISTER_SIZE
];
311 memset (zerobuf
, 0, MAX_REGISTER_SIZE
);
313 for (regi
= MIPS64_EF_REG0
; regi
<= MIPS64_EF_REG31
; regi
++)
314 supply_64bit_reg (regi
- MIPS64_EF_REG0
, (gdb_byte
*)(regp
+ regi
));
316 supply_64bit_reg (mips_regnum (current_gdbarch
)->lo
,
317 (gdb_byte
*) (regp
+ MIPS64_EF_LO
));
318 supply_64bit_reg (mips_regnum (current_gdbarch
)->hi
,
319 (gdb_byte
*) (regp
+ MIPS64_EF_HI
));
321 supply_64bit_reg (mips_regnum (current_gdbarch
)->pc
,
322 (gdb_byte
*) (regp
+ MIPS64_EF_CP0_EPC
));
323 supply_64bit_reg (mips_regnum (current_gdbarch
)->badvaddr
,
324 (gdb_byte
*) (regp
+ MIPS64_EF_CP0_BADVADDR
));
325 supply_64bit_reg (MIPS_PS_REGNUM
,
326 (gdb_byte
*) (regp
+ MIPS64_EF_CP0_STATUS
));
327 supply_64bit_reg (mips_regnum (current_gdbarch
)->cause
,
328 (gdb_byte
*) (regp
+ MIPS64_EF_CP0_CAUSE
));
330 /* Fill inaccessible registers with zero. */
331 regcache_raw_supply (current_regcache
, MIPS_UNUSED_REGNUM
, zerobuf
);
332 for (regi
= MIPS_FIRST_EMBED_REGNUM
;
333 regi
< MIPS_LAST_EMBED_REGNUM
;
335 regcache_raw_supply (current_regcache
, regi
, zerobuf
);
338 /* Pack our registers (or one register) into a 64-bit elf_gregset_t. */
341 mips64_fill_gregset (mips64_elf_gregset_t
*gregsetp
, int regno
)
344 mips64_elf_greg_t
*regp
= *gregsetp
;
349 memset (regp
, 0, sizeof (mips64_elf_gregset_t
));
350 for (regi
= 0; regi
< 32; regi
++)
351 mips64_fill_gregset (gregsetp
, regi
);
352 mips64_fill_gregset (gregsetp
, mips_regnum (current_gdbarch
)->lo
);
353 mips64_fill_gregset (gregsetp
, mips_regnum (current_gdbarch
)->hi
);
354 mips64_fill_gregset (gregsetp
, mips_regnum (current_gdbarch
)->pc
);
355 mips64_fill_gregset (gregsetp
,
356 mips_regnum (current_gdbarch
)->badvaddr
);
357 mips64_fill_gregset (gregsetp
, MIPS_PS_REGNUM
);
358 mips64_fill_gregset (gregsetp
,
359 mips_regnum (current_gdbarch
)->cause
);
365 regaddr
= regno
+ MIPS64_EF_REG0
;
366 else if (regno
== mips_regnum (current_gdbarch
)->lo
)
367 regaddr
= MIPS64_EF_LO
;
368 else if (regno
== mips_regnum (current_gdbarch
)->hi
)
369 regaddr
= MIPS64_EF_HI
;
370 else if (regno
== mips_regnum (current_gdbarch
)->pc
)
371 regaddr
= MIPS64_EF_CP0_EPC
;
372 else if (regno
== mips_regnum (current_gdbarch
)->badvaddr
)
373 regaddr
= MIPS64_EF_CP0_BADVADDR
;
374 else if (regno
== MIPS_PS_REGNUM
)
375 regaddr
= MIPS64_EF_CP0_STATUS
;
376 else if (regno
== mips_regnum (current_gdbarch
)->cause
)
377 regaddr
= MIPS64_EF_CP0_CAUSE
;
383 gdb_byte buf
[MAX_REGISTER_SIZE
];
386 regcache_raw_collect (current_regcache
, regno
, buf
);
387 val
= extract_signed_integer (buf
,
388 register_size (current_gdbarch
, regno
));
389 dst
= regp
+ regaddr
;
390 store_signed_integer (dst
, 8, val
);
394 /* Likewise, unpack an elf_fpregset_t. */
397 mips64_supply_fpregset (mips64_elf_fpregset_t
*fpregsetp
)
401 /* See mips_linux_o32_sigframe_init for a description of the
402 peculiar FP register layout. */
403 if (register_size (current_gdbarch
, FP0_REGNUM
) == 4)
404 for (regi
= 0; regi
< 32; regi
++)
406 gdb_byte
*reg_ptr
= (gdb_byte
*) (*fpregsetp
+ (regi
& ~1));
407 if ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
) != (regi
& 1))
409 regcache_raw_supply (current_regcache
, FP0_REGNUM
+ regi
, reg_ptr
);
412 for (regi
= 0; regi
< 32; regi
++)
413 regcache_raw_supply (current_regcache
, FP0_REGNUM
+ regi
,
414 (char *)(*fpregsetp
+ regi
));
416 supply_32bit_reg (mips_regnum (current_gdbarch
)->fp_control_status
,
417 (gdb_byte
*)(*fpregsetp
+ 32));
419 /* The ABI doesn't tell us how to supply FCRIR, and core dumps don't
420 include it - but the result of PTRACE_GETFPREGS does. The best we
421 can do is to assume that its value is present. */
422 supply_32bit_reg (mips_regnum (current_gdbarch
)->fp_implementation_revision
,
423 (gdb_byte
*)(*fpregsetp
+ 32) + 4);
426 /* Likewise, pack one or all floating point registers into an
430 mips64_fill_fpregset (mips64_elf_fpregset_t
*fpregsetp
, int regno
)
434 if ((regno
>= FP0_REGNUM
) && (regno
< FP0_REGNUM
+ 32))
436 /* See mips_linux_o32_sigframe_init for a description of the
437 peculiar FP register layout. */
438 if (register_size (current_gdbarch
, regno
) == 4)
440 int regi
= regno
- FP0_REGNUM
;
442 to
= (gdb_byte
*) (*fpregsetp
+ (regi
& ~1));
443 if ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
) != (regi
& 1))
445 regcache_raw_collect (current_regcache
, regno
, to
);
449 to
= (gdb_byte
*) (*fpregsetp
+ regno
- FP0_REGNUM
);
450 regcache_raw_collect (current_regcache
, regno
, to
);
453 else if (regno
== mips_regnum (current_gdbarch
)->fp_control_status
)
455 gdb_byte buf
[MAX_REGISTER_SIZE
];
458 regcache_raw_collect (current_regcache
, regno
, buf
);
459 val
= extract_signed_integer (buf
,
460 register_size (current_gdbarch
, regno
));
461 to
= (gdb_byte
*) (*fpregsetp
+ 32);
462 store_signed_integer (to
, 4, val
);
464 else if (regno
== mips_regnum (current_gdbarch
)->fp_implementation_revision
)
466 gdb_byte buf
[MAX_REGISTER_SIZE
];
469 regcache_raw_collect (current_regcache
, regno
, buf
);
470 val
= extract_signed_integer (buf
,
471 register_size (current_gdbarch
, regno
));
472 to
= (gdb_byte
*) (*fpregsetp
+ 32) + 4;
473 store_signed_integer (to
, 4, val
);
475 else if (regno
== -1)
479 for (regi
= 0; regi
< 32; regi
++)
480 mips64_fill_fpregset (fpregsetp
, FP0_REGNUM
+ regi
);
481 mips64_fill_fpregset (fpregsetp
,
482 mips_regnum (current_gdbarch
)->fp_control_status
);
483 mips64_fill_fpregset (fpregsetp
, (mips_regnum (current_gdbarch
)
484 ->fp_implementation_revision
));
489 /* Map gdb internal register number to ptrace ``address''.
490 These ``addresses'' are normally defined in <asm/ptrace.h>. */
493 mips64_linux_register_addr (int regno
, CORE_ADDR blockend
)
497 if (regno
< 0 || regno
>= NUM_REGS
)
498 error (_("Bogon register number %d."), regno
);
502 else if ((regno
>= mips_regnum (current_gdbarch
)->fp0
)
503 && (regno
< mips_regnum (current_gdbarch
)->fp0
+ 32))
504 regaddr
= MIPS64_FPR_BASE
+ (regno
- FP0_REGNUM
);
505 else if (regno
== mips_regnum (current_gdbarch
)->pc
)
507 else if (regno
== mips_regnum (current_gdbarch
)->cause
)
508 regaddr
= MIPS64_CAUSE
;
509 else if (regno
== mips_regnum (current_gdbarch
)->badvaddr
)
510 regaddr
= MIPS64_BADVADDR
;
511 else if (regno
== mips_regnum (current_gdbarch
)->lo
)
512 regaddr
= MIPS64_MMLO
;
513 else if (regno
== mips_regnum (current_gdbarch
)->hi
)
514 regaddr
= MIPS64_MMHI
;
515 else if (regno
== mips_regnum (current_gdbarch
)->fp_control_status
)
516 regaddr
= MIPS64_FPC_CSR
;
517 else if (regno
== mips_regnum (current_gdbarch
)->fp_implementation_revision
)
518 regaddr
= MIPS64_FPC_EIR
;
520 error (_("Unknowable register number %d."), regno
);
525 /* Use a local version of this function to get the correct types for
526 regsets, until multi-arch core support is ready. */
529 fetch_core_registers (char *core_reg_sect
, unsigned core_reg_size
,
530 int which
, CORE_ADDR reg_addr
)
532 mips_elf_gregset_t gregset
;
533 mips_elf_fpregset_t fpregset
;
534 mips64_elf_gregset_t gregset64
;
535 mips64_elf_fpregset_t fpregset64
;
539 if (core_reg_size
== sizeof (gregset
))
541 memcpy ((char *) &gregset
, core_reg_sect
, sizeof (gregset
));
542 mips_supply_gregset (&gregset
);
544 else if (core_reg_size
== sizeof (gregset64
))
546 memcpy ((char *) &gregset64
, core_reg_sect
, sizeof (gregset64
));
547 mips64_supply_gregset (&gregset64
);
551 warning (_("wrong size gregset struct in core file"));
556 if (core_reg_size
== sizeof (fpregset
))
558 memcpy ((char *) &fpregset
, core_reg_sect
, sizeof (fpregset
));
559 mips_supply_fpregset (&fpregset
);
561 else if (core_reg_size
== sizeof (fpregset64
))
563 memcpy ((char *) &fpregset64
, core_reg_sect
,
564 sizeof (fpregset64
));
565 mips64_supply_fpregset (&fpregset64
);
569 warning (_("wrong size fpregset struct in core file"));
574 /* Register that we are able to handle ELF file formats using standard
575 procfs "regset" structures. */
577 static struct core_fns regset_core_fns
=
579 bfd_target_elf_flavour
, /* core_flavour */
580 default_check_format
, /* check_format */
581 default_core_sniffer
, /* core_sniffer */
582 fetch_core_registers
, /* core_read_registers */
586 /* Handle for obtaining pointer to the current register_addr()
587 function for a given architecture. */
588 static struct gdbarch_data
*register_addr_data
;
591 register_addr (int regno
, CORE_ADDR blockend
)
593 CORE_ADDR (*register_addr_ptr
) (int, CORE_ADDR
) =
594 gdbarch_data (current_gdbarch
, register_addr_data
);
596 gdb_assert (register_addr_ptr
!= 0);
598 return register_addr_ptr (regno
, blockend
);
602 set_mips_linux_register_addr (struct gdbarch
*gdbarch
,
603 CORE_ADDR (*register_addr_ptr
) (int,
606 deprecated_set_gdbarch_data (gdbarch
, register_addr_data
,
611 init_register_addr_data (struct gdbarch
*gdbarch
)
616 /* Check the code at PC for a dynamic linker lazy resolution stub.
617 Because they aren't in the .plt section, we pattern-match on the
618 code generated by GNU ld. They look like this:
625 (with the appropriate doubleword instructions for N64). Also
626 return the dynamic symbol index used in the last instruction. */
629 mips_linux_in_dynsym_stub (CORE_ADDR pc
, char *name
)
631 unsigned char buf
[28], *p
;
632 ULONGEST insn
, insn1
;
633 int n64
= (mips_abi (current_gdbarch
) == MIPS_ABI_N64
);
635 read_memory (pc
- 12, buf
, 28);
639 /* ld t9,0x8010(gp) */
644 /* lw t9,0x8010(gp) */
651 insn
= extract_unsigned_integer (p
, 4);
659 insn
= extract_unsigned_integer (p
+ 4, 4);
663 if (insn
!= 0x03e0782d)
669 if (insn
!= 0x03e07821)
673 insn
= extract_unsigned_integer (p
+ 8, 4);
675 if (insn
!= 0x0320f809)
678 insn
= extract_unsigned_integer (p
+ 12, 4);
681 /* daddiu t8,zero,0 */
682 if ((insn
& 0xffff0000) != 0x64180000)
687 /* addiu t8,zero,0 */
688 if ((insn
& 0xffff0000) != 0x24180000)
692 return (insn
& 0xffff);
695 /* Return non-zero iff PC belongs to the dynamic linker resolution
696 code or to a stub. */
699 mips_linux_in_dynsym_resolve_code (CORE_ADDR pc
)
701 /* Check whether PC is in the dynamic linker. This also checks
702 whether it is in the .plt section, which MIPS does not use. */
703 if (in_solib_dynsym_resolve_code (pc
))
706 /* Pattern match for the stub. It would be nice if there were a
707 more efficient way to avoid this check. */
708 if (mips_linux_in_dynsym_stub (pc
, NULL
))
714 /* See the comments for SKIP_SOLIB_RESOLVER at the top of infrun.c,
715 and glibc_skip_solib_resolver in glibc-tdep.c. The normal glibc
716 implementation of this triggers at "fixup" from the same objfile as
717 "_dl_runtime_resolve"; MIPS GNU/Linux can trigger at
718 "__dl_runtime_resolve" directly. An unresolved PLT entry will
719 point to _dl_runtime_resolve, which will first call
720 __dl_runtime_resolve, and then pass control to the resolved
724 mips_linux_skip_resolver (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
726 struct minimal_symbol
*resolver
;
728 resolver
= lookup_minimal_symbol ("__dl_runtime_resolve", NULL
, NULL
);
730 if (resolver
&& SYMBOL_VALUE_ADDRESS (resolver
) == pc
)
731 return frame_pc_unwind (get_current_frame ());
736 /* Signal trampoline support. There are four supported layouts for a
737 signal frame: o32 sigframe, o32 rt_sigframe, n32 rt_sigframe, and
738 n64 rt_sigframe. We handle them all independently; not the most
739 efficient way, but simplest. First, declare all the unwinders. */
741 static void mips_linux_o32_sigframe_init (const struct tramp_frame
*self
,
742 struct frame_info
*next_frame
,
743 struct trad_frame_cache
*this_cache
,
746 static void mips_linux_n32n64_sigframe_init (const struct tramp_frame
*self
,
747 struct frame_info
*next_frame
,
748 struct trad_frame_cache
*this_cache
,
751 #define MIPS_NR_LINUX 4000
752 #define MIPS_NR_N64_LINUX 5000
753 #define MIPS_NR_N32_LINUX 6000
755 #define MIPS_NR_sigreturn MIPS_NR_LINUX + 119
756 #define MIPS_NR_rt_sigreturn MIPS_NR_LINUX + 193
757 #define MIPS_NR_N64_rt_sigreturn MIPS_NR_N64_LINUX + 211
758 #define MIPS_NR_N32_rt_sigreturn MIPS_NR_N32_LINUX + 211
760 #define MIPS_INST_LI_V0_SIGRETURN 0x24020000 + MIPS_NR_sigreturn
761 #define MIPS_INST_LI_V0_RT_SIGRETURN 0x24020000 + MIPS_NR_rt_sigreturn
762 #define MIPS_INST_LI_V0_N64_RT_SIGRETURN 0x24020000 + MIPS_NR_N64_rt_sigreturn
763 #define MIPS_INST_LI_V0_N32_RT_SIGRETURN 0x24020000 + MIPS_NR_N32_rt_sigreturn
764 #define MIPS_INST_SYSCALL 0x0000000c
766 static const struct tramp_frame mips_linux_o32_sigframe
= {
770 { MIPS_INST_LI_V0_SIGRETURN
, -1 },
771 { MIPS_INST_SYSCALL
, -1 },
772 { TRAMP_SENTINEL_INSN
, -1 }
774 mips_linux_o32_sigframe_init
777 static const struct tramp_frame mips_linux_o32_rt_sigframe
= {
781 { MIPS_INST_LI_V0_RT_SIGRETURN
, -1 },
782 { MIPS_INST_SYSCALL
, -1 },
783 { TRAMP_SENTINEL_INSN
, -1 } },
784 mips_linux_o32_sigframe_init
787 static const struct tramp_frame mips_linux_n32_rt_sigframe
= {
791 { MIPS_INST_LI_V0_N32_RT_SIGRETURN
, -1 },
792 { MIPS_INST_SYSCALL
, -1 },
793 { TRAMP_SENTINEL_INSN
, -1 }
795 mips_linux_n32n64_sigframe_init
798 static const struct tramp_frame mips_linux_n64_rt_sigframe
= {
801 { MIPS_INST_LI_V0_N64_RT_SIGRETURN
,
803 TRAMP_SENTINEL_INSN
},
804 mips_linux_n32n64_sigframe_init
808 /* The unwinder for o32 signal frames. The legacy structures look
812 u32 sf_ass[4]; [argument save space for o32]
813 u32 sf_code[2]; [signal trampoline]
814 struct sigcontext sf_sc;
819 unsigned int sc_regmask; [Unused]
820 unsigned int sc_status;
821 unsigned long long sc_pc;
822 unsigned long long sc_regs[32];
823 unsigned long long sc_fpregs[32];
824 unsigned int sc_ownedfp;
825 unsigned int sc_fpc_csr;
826 unsigned int sc_fpc_eir; [Unused]
827 unsigned int sc_used_math;
828 unsigned int sc_ssflags; [Unused]
829 [Alignment hole of four bytes]
830 unsigned long long sc_mdhi;
831 unsigned long long sc_mdlo;
833 unsigned int sc_cause; [Unused]
834 unsigned int sc_badvaddr; [Unused]
836 unsigned long sc_sigset[4]; [kernel's sigset_t]
839 The RT signal frames look like this:
842 u32 rs_ass[4]; [argument save space for o32]
843 u32 rs_code[2] [signal trampoline]
844 struct siginfo rs_info;
845 struct ucontext rs_uc;
849 unsigned long uc_flags;
850 struct ucontext *uc_link;
852 [Alignment hole of four bytes]
853 struct sigcontext uc_mcontext;
858 #define SIGFRAME_CODE_OFFSET (4 * 4)
859 #define SIGFRAME_SIGCONTEXT_OFFSET (6 * 4)
861 #define RTSIGFRAME_SIGINFO_SIZE 128
862 #define STACK_T_SIZE (3 * 4)
863 #define UCONTEXT_SIGCONTEXT_OFFSET (2 * 4 + STACK_T_SIZE + 4)
864 #define RTSIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \
865 + RTSIGFRAME_SIGINFO_SIZE \
866 + UCONTEXT_SIGCONTEXT_OFFSET)
868 #define SIGCONTEXT_PC (1 * 8)
869 #define SIGCONTEXT_REGS (2 * 8)
870 #define SIGCONTEXT_FPREGS (34 * 8)
871 #define SIGCONTEXT_FPCSR (66 * 8 + 4)
872 #define SIGCONTEXT_HI (69 * 8)
873 #define SIGCONTEXT_LO (70 * 8)
874 #define SIGCONTEXT_CAUSE (71 * 8 + 0)
875 #define SIGCONTEXT_BADVADDR (71 * 8 + 4)
877 #define SIGCONTEXT_REG_SIZE 8
880 mips_linux_o32_sigframe_init (const struct tramp_frame
*self
,
881 struct frame_info
*next_frame
,
882 struct trad_frame_cache
*this_cache
,
885 int ireg
, reg_position
;
886 CORE_ADDR sigcontext_base
= func
- SIGFRAME_CODE_OFFSET
;
887 const struct mips_regnum
*regs
= mips_regnum (current_gdbarch
);
890 if (self
== &mips_linux_o32_sigframe
)
891 sigcontext_base
+= SIGFRAME_SIGCONTEXT_OFFSET
;
893 sigcontext_base
+= RTSIGFRAME_SIGCONTEXT_OFFSET
;
895 /* I'm not proud of this hack. Eventually we will have the
896 infrastructure to indicate the size of saved registers on a
897 per-frame basis, but right now we don't; the kernel saves eight
898 bytes but we only want four. Use regs_base to access any
900 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
901 regs_base
= sigcontext_base
+ 4;
903 regs_base
= sigcontext_base
;
906 trad_frame_set_reg_addr (this_cache
, ORIG_ZERO_REGNUM
+ NUM_REGS
,
907 regs_base
+ SIGCONTEXT_REGS
);
910 for (ireg
= 1; ireg
< 32; ireg
++)
911 trad_frame_set_reg_addr (this_cache
,
912 ireg
+ MIPS_ZERO_REGNUM
+ NUM_REGS
,
913 regs_base
+ SIGCONTEXT_REGS
914 + ireg
* SIGCONTEXT_REG_SIZE
);
916 /* The way that floating point registers are saved, unfortunately,
917 depends on the architecture the kernel is built for. For the r3000 and
918 tx39, four bytes of each register are at the beginning of each of the
919 32 eight byte slots. For everything else, the registers are saved
920 using double precision; only the even-numbered slots are initialized,
921 and the high bits are the odd-numbered register. Assume the latter
922 layout, since we can't tell, and it's much more common. Which bits are
923 the "high" bits depends on endianness. */
924 for (ireg
= 0; ireg
< 32; ireg
++)
925 if ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
) != (ireg
& 1))
926 trad_frame_set_reg_addr (this_cache
, ireg
+ regs
->fp0
+ NUM_REGS
,
927 sigcontext_base
+ SIGCONTEXT_FPREGS
+ 4
928 + (ireg
& ~1) * SIGCONTEXT_REG_SIZE
);
930 trad_frame_set_reg_addr (this_cache
, ireg
+ regs
->fp0
+ NUM_REGS
,
931 sigcontext_base
+ SIGCONTEXT_FPREGS
932 + (ireg
& ~1) * SIGCONTEXT_REG_SIZE
);
934 trad_frame_set_reg_addr (this_cache
, regs
->pc
+ NUM_REGS
,
935 regs_base
+ SIGCONTEXT_PC
);
937 trad_frame_set_reg_addr (this_cache
,
938 regs
->fp_control_status
+ NUM_REGS
,
939 sigcontext_base
+ SIGCONTEXT_FPCSR
);
940 trad_frame_set_reg_addr (this_cache
, regs
->hi
+ NUM_REGS
,
941 regs_base
+ SIGCONTEXT_HI
);
942 trad_frame_set_reg_addr (this_cache
, regs
->lo
+ NUM_REGS
,
943 regs_base
+ SIGCONTEXT_LO
);
944 trad_frame_set_reg_addr (this_cache
, regs
->cause
+ NUM_REGS
,
945 sigcontext_base
+ SIGCONTEXT_CAUSE
);
946 trad_frame_set_reg_addr (this_cache
, regs
->badvaddr
+ NUM_REGS
,
947 sigcontext_base
+ SIGCONTEXT_BADVADDR
);
949 /* Choice of the bottom of the sigframe is somewhat arbitrary. */
950 trad_frame_set_id (this_cache
,
951 frame_id_build (func
- SIGFRAME_CODE_OFFSET
,
956 /* For N32/N64 things look different. There is no non-rt signal frame.
958 struct rt_sigframe_n32 {
959 u32 rs_ass[4]; [ argument save space for o32 ]
960 u32 rs_code[2]; [ signal trampoline ]
961 struct siginfo rs_info;
962 struct ucontextn32 rs_uc;
969 struct sigcontext uc_mcontext;
970 sigset_t uc_sigmask; [ mask last for extensibility ]
973 struct rt_sigframe_n32 {
974 u32 rs_ass[4]; [ argument save space for o32 ]
975 u32 rs_code[2]; [ signal trampoline ]
976 struct siginfo rs_info;
977 struct ucontext rs_uc;
981 unsigned long uc_flags;
982 struct ucontext *uc_link;
984 struct sigcontext uc_mcontext;
985 sigset_t uc_sigmask; [ mask last for extensibility ]
988 And the sigcontext is different (this is for both n32 and n64):
991 unsigned long long sc_regs[32];
992 unsigned long long sc_fpregs[32];
993 unsigned long long sc_mdhi;
994 unsigned long long sc_mdlo;
995 unsigned long long sc_pc;
996 unsigned int sc_status;
997 unsigned int sc_fpc_csr;
998 unsigned int sc_fpc_eir;
999 unsigned int sc_used_math;
1000 unsigned int sc_cause;
1001 unsigned int sc_badvaddr;
1005 #define N32_STACK_T_SIZE STACK_T_SIZE
1006 #define N64_STACK_T_SIZE (2 * 8 + 4)
1007 #define N32_UCONTEXT_SIGCONTEXT_OFFSET (2 * 4 + N32_STACK_T_SIZE + 4)
1008 #define N64_UCONTEXT_SIGCONTEXT_OFFSET (2 * 8 + N64_STACK_T_SIZE + 4)
1009 #define N32_SIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \
1010 + RTSIGFRAME_SIGINFO_SIZE \
1011 + N32_UCONTEXT_SIGCONTEXT_OFFSET)
1012 #define N64_SIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \
1013 + RTSIGFRAME_SIGINFO_SIZE \
1014 + N64_UCONTEXT_SIGCONTEXT_OFFSET)
1016 #define N64_SIGCONTEXT_REGS (0 * 8)
1017 #define N64_SIGCONTEXT_FPREGS (32 * 8)
1018 #define N64_SIGCONTEXT_HI (64 * 8)
1019 #define N64_SIGCONTEXT_LO (65 * 8)
1020 #define N64_SIGCONTEXT_PC (66 * 8)
1021 #define N64_SIGCONTEXT_FPCSR (67 * 8 + 1 * 4)
1022 #define N64_SIGCONTEXT_FIR (67 * 8 + 2 * 4)
1023 #define N64_SIGCONTEXT_CAUSE (67 * 8 + 4 * 4)
1024 #define N64_SIGCONTEXT_BADVADDR (67 * 8 + 5 * 4)
1026 #define N64_SIGCONTEXT_REG_SIZE 8
1029 mips_linux_n32n64_sigframe_init (const struct tramp_frame
*self
,
1030 struct frame_info
*next_frame
,
1031 struct trad_frame_cache
*this_cache
,
1034 int ireg
, reg_position
;
1035 CORE_ADDR sigcontext_base
= func
- SIGFRAME_CODE_OFFSET
;
1036 const struct mips_regnum
*regs
= mips_regnum (current_gdbarch
);
1038 if (self
== &mips_linux_n32_rt_sigframe
)
1039 sigcontext_base
+= N32_SIGFRAME_SIGCONTEXT_OFFSET
;
1041 sigcontext_base
+= N64_SIGFRAME_SIGCONTEXT_OFFSET
;
1044 trad_frame_set_reg_addr (this_cache
, ORIG_ZERO_REGNUM
+ NUM_REGS
,
1045 sigcontext_base
+ N64_SIGCONTEXT_REGS
);
1048 for (ireg
= 1; ireg
< 32; ireg
++)
1049 trad_frame_set_reg_addr (this_cache
,
1050 ireg
+ MIPS_ZERO_REGNUM
+ NUM_REGS
,
1051 sigcontext_base
+ N64_SIGCONTEXT_REGS
1052 + ireg
* N64_SIGCONTEXT_REG_SIZE
);
1054 for (ireg
= 0; ireg
< 32; ireg
++)
1055 trad_frame_set_reg_addr (this_cache
, ireg
+ regs
->fp0
+ NUM_REGS
,
1056 sigcontext_base
+ N64_SIGCONTEXT_FPREGS
1057 + ireg
* N64_SIGCONTEXT_REG_SIZE
);
1059 trad_frame_set_reg_addr (this_cache
, regs
->pc
+ NUM_REGS
,
1060 sigcontext_base
+ N64_SIGCONTEXT_PC
);
1062 trad_frame_set_reg_addr (this_cache
,
1063 regs
->fp_control_status
+ NUM_REGS
,
1064 sigcontext_base
+ N64_SIGCONTEXT_FPCSR
);
1065 trad_frame_set_reg_addr (this_cache
, regs
->hi
+ NUM_REGS
,
1066 sigcontext_base
+ N64_SIGCONTEXT_HI
);
1067 trad_frame_set_reg_addr (this_cache
, regs
->lo
+ NUM_REGS
,
1068 sigcontext_base
+ N64_SIGCONTEXT_LO
);
1069 trad_frame_set_reg_addr (this_cache
, regs
->cause
+ NUM_REGS
,
1070 sigcontext_base
+ N64_SIGCONTEXT_CAUSE
);
1071 trad_frame_set_reg_addr (this_cache
, regs
->badvaddr
+ NUM_REGS
,
1072 sigcontext_base
+ N64_SIGCONTEXT_BADVADDR
);
1074 /* Choice of the bottom of the sigframe is somewhat arbitrary. */
1075 trad_frame_set_id (this_cache
,
1076 frame_id_build (func
- SIGFRAME_CODE_OFFSET
,
1080 /* Wrapper functions. These are only used by libthread_db. */
1083 supply_gregset (mips_elf_gregset_t
*gregsetp
)
1085 if (mips_isa_regsize (current_gdbarch
) == 4)
1086 mips_supply_gregset (gregsetp
);
1088 mips64_supply_gregset ((void *) gregsetp
);
1092 fill_gregset (mips_elf_gregset_t
*gregsetp
, int regno
)
1094 if (mips_isa_regsize (current_gdbarch
) == 4)
1095 mips_fill_gregset (gregsetp
, regno
);
1097 mips64_fill_gregset ((void *) gregsetp
, regno
);
1100 /* Likewise, unpack an elf_fpregset_t. */
1103 supply_fpregset (mips_elf_fpregset_t
*fpregsetp
)
1105 if (mips_isa_regsize (current_gdbarch
) == 4)
1106 mips_supply_fpregset (fpregsetp
);
1108 mips64_supply_fpregset ((void *) fpregsetp
);
1111 /* Likewise, pack one or all floating point registers into an
1115 fill_fpregset (mips_elf_fpregset_t
*fpregsetp
, int regno
)
1117 if (mips_isa_regsize (current_gdbarch
) == 4)
1118 mips_fill_fpregset (fpregsetp
, regno
);
1120 mips64_fill_fpregset ((void *) fpregsetp
, regno
);
1123 /* Initialize one of the GNU/Linux OS ABIs. */
1126 mips_linux_init_abi (struct gdbarch_info info
,
1127 struct gdbarch
*gdbarch
)
1129 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1130 enum mips_abi abi
= mips_abi (gdbarch
);
1135 set_gdbarch_get_longjmp_target (gdbarch
,
1136 mips_linux_get_longjmp_target
);
1137 set_solib_svr4_fetch_link_map_offsets
1138 (gdbarch
, svr4_ilp32_fetch_link_map_offsets
);
1139 set_mips_linux_register_addr (gdbarch
, mips_linux_register_addr
);
1140 tramp_frame_prepend_unwinder (gdbarch
, &mips_linux_o32_sigframe
);
1141 tramp_frame_prepend_unwinder (gdbarch
, &mips_linux_o32_rt_sigframe
);
1144 set_gdbarch_get_longjmp_target (gdbarch
,
1145 mips_linux_get_longjmp_target
);
1146 set_solib_svr4_fetch_link_map_offsets
1147 (gdbarch
, svr4_ilp32_fetch_link_map_offsets
);
1148 set_mips_linux_register_addr (gdbarch
, mips64_linux_register_addr
);
1149 set_gdbarch_long_double_bit (gdbarch
, 128);
1150 /* These floatformats should probably be renamed. MIPS uses
1151 the same 128-bit IEEE floating point format that IA-64 uses,
1152 except that the quiet/signalling NaN bit is reversed (GDB
1153 does not distinguish between quiet and signalling NaNs). */
1154 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1155 set_gdbarch_long_double_format (gdbarch
, &floatformat_ia64_quad_big
);
1157 set_gdbarch_long_double_format (gdbarch
, &floatformat_ia64_quad_little
);
1158 tramp_frame_prepend_unwinder (gdbarch
, &mips_linux_n32_rt_sigframe
);
1161 set_gdbarch_get_longjmp_target (gdbarch
,
1162 mips64_linux_get_longjmp_target
);
1163 set_solib_svr4_fetch_link_map_offsets
1164 (gdbarch
, svr4_lp64_fetch_link_map_offsets
);
1165 set_mips_linux_register_addr (gdbarch
, mips64_linux_register_addr
);
1166 set_gdbarch_long_double_bit (gdbarch
, 128);
1167 /* These floatformats should probably be renamed. MIPS uses
1168 the same 128-bit IEEE floating point format that IA-64 uses,
1169 except that the quiet/signalling NaN bit is reversed (GDB
1170 does not distinguish between quiet and signalling NaNs). */
1171 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1172 set_gdbarch_long_double_format (gdbarch
, &floatformat_ia64_quad_big
);
1174 set_gdbarch_long_double_format (gdbarch
, &floatformat_ia64_quad_little
);
1175 tramp_frame_prepend_unwinder (gdbarch
, &mips_linux_n64_rt_sigframe
);
1178 internal_error (__FILE__
, __LINE__
, _("can't handle ABI"));
1182 set_gdbarch_skip_solib_resolver (gdbarch
, mips_linux_skip_resolver
);
1184 set_gdbarch_software_single_step (gdbarch
, mips_software_single_step
);
1186 /* Enable TLS support. */
1187 set_gdbarch_fetch_tls_load_module_address (gdbarch
,
1188 svr4_fetch_objfile_link_map
);
1192 _initialize_mips_linux_tdep (void)
1194 const struct bfd_arch_info
*arch_info
;
1196 register_addr_data
=
1197 gdbarch_data_register_post_init (init_register_addr_data
);
1199 for (arch_info
= bfd_lookup_arch (bfd_arch_mips
, 0);
1201 arch_info
= arch_info
->next
)
1203 gdbarch_register_osabi (bfd_arch_mips
, arch_info
->mach
,
1205 mips_linux_init_abi
);
1208 deprecated_add_core_fns (®set_core_fns
);