1 /* Target-dependent code for GNU/Linux on MIPS processors.
3 Copyright (C) 2001, 2002, 2004, 2005, 2006
4 Free Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street, Fifth Floor,
21 Boston, MA 02110-1301, USA. */
26 #include "solib-svr4.h"
28 #include "mips-tdep.h"
29 #include "gdb_string.h"
30 #include "gdb_assert.h"
33 #include "trad-frame.h"
34 #include "tramp-frame.h"
35 #include "floatformat.h"
37 /* Copied from <asm/elf.h>. */
41 typedef unsigned char elf_greg_t
[4];
42 typedef elf_greg_t elf_gregset_t
[ELF_NGREG
];
44 typedef unsigned char elf_fpreg_t
[8];
45 typedef elf_fpreg_t elf_fpregset_t
[ELF_NFPREG
];
47 /* 0 - 31 are integer registers, 32 - 63 are fp registers. */
62 #define EF_CP0_BADVADDR 41
63 #define EF_CP0_STATUS 42
64 #define EF_CP0_CAUSE 43
68 /* Figure out where the longjmp will land.
69 We expect the first arg to be a pointer to the jmp_buf structure
70 from which we extract the pc (MIPS_LINUX_JB_PC) that we will land
71 at. The pc is copied into PC. This routine returns 1 on
74 #define MIPS_LINUX_JB_ELEMENT_SIZE 4
75 #define MIPS_LINUX_JB_PC 0
78 mips_linux_get_longjmp_target (CORE_ADDR
*pc
)
81 char buf
[TARGET_PTR_BIT
/ TARGET_CHAR_BIT
];
83 jb_addr
= read_register (MIPS_A0_REGNUM
);
85 if (target_read_memory (jb_addr
86 + MIPS_LINUX_JB_PC
* MIPS_LINUX_JB_ELEMENT_SIZE
,
87 buf
, TARGET_PTR_BIT
/ TARGET_CHAR_BIT
))
90 *pc
= extract_unsigned_integer (buf
, TARGET_PTR_BIT
/ TARGET_CHAR_BIT
);
95 /* Transform the bits comprising a 32-bit register to the right size
96 for regcache_raw_supply(). This is needed when mips_isa_regsize()
100 supply_32bit_reg (int regnum
, const void *addr
)
102 char buf
[MAX_REGISTER_SIZE
];
103 store_signed_integer (buf
, register_size (current_gdbarch
, regnum
),
104 extract_signed_integer (addr
, 4));
105 regcache_raw_supply (current_regcache
, regnum
, buf
);
108 /* Unpack an elf_gregset_t into GDB's register cache. */
111 supply_gregset (elf_gregset_t
*gregsetp
)
114 elf_greg_t
*regp
= *gregsetp
;
115 char zerobuf
[MAX_REGISTER_SIZE
];
117 memset (zerobuf
, 0, MAX_REGISTER_SIZE
);
119 for (regi
= EF_REG0
; regi
<= EF_REG31
; regi
++)
120 supply_32bit_reg ((regi
- EF_REG0
), (char *)(regp
+ regi
));
122 supply_32bit_reg (mips_regnum (current_gdbarch
)->lo
,
123 (char *)(regp
+ EF_LO
));
124 supply_32bit_reg (mips_regnum (current_gdbarch
)->hi
,
125 (char *)(regp
+ EF_HI
));
127 supply_32bit_reg (mips_regnum (current_gdbarch
)->pc
,
128 (char *)(regp
+ EF_CP0_EPC
));
129 supply_32bit_reg (mips_regnum (current_gdbarch
)->badvaddr
,
130 (char *)(regp
+ EF_CP0_BADVADDR
));
131 supply_32bit_reg (MIPS_PS_REGNUM
, (char *)(regp
+ EF_CP0_STATUS
));
132 supply_32bit_reg (mips_regnum (current_gdbarch
)->cause
,
133 (char *)(regp
+ EF_CP0_CAUSE
));
135 /* Fill inaccessible registers with zero. */
136 regcache_raw_supply (current_regcache
, MIPS_UNUSED_REGNUM
, zerobuf
);
137 for (regi
= MIPS_FIRST_EMBED_REGNUM
;
138 regi
< MIPS_LAST_EMBED_REGNUM
;
140 regcache_raw_supply (current_regcache
, regi
, zerobuf
);
143 /* Pack our registers (or one register) into an elf_gregset_t. */
146 fill_gregset (elf_gregset_t
*gregsetp
, int regno
)
149 elf_greg_t
*regp
= *gregsetp
;
154 memset (regp
, 0, sizeof (elf_gregset_t
));
155 for (regi
= 0; regi
< 32; regi
++)
156 fill_gregset (gregsetp
, regi
);
157 fill_gregset (gregsetp
, mips_regnum (current_gdbarch
)->lo
);
158 fill_gregset (gregsetp
, mips_regnum (current_gdbarch
)->hi
);
159 fill_gregset (gregsetp
, mips_regnum (current_gdbarch
)->pc
);
160 fill_gregset (gregsetp
, mips_regnum (current_gdbarch
)->badvaddr
);
161 fill_gregset (gregsetp
, MIPS_PS_REGNUM
);
162 fill_gregset (gregsetp
, mips_regnum (current_gdbarch
)->cause
);
169 dst
= regp
+ regno
+ EF_REG0
;
170 regcache_raw_collect (current_regcache
, regno
, dst
);
174 if (regno
== mips_regnum (current_gdbarch
)->lo
)
176 else if (regno
== mips_regnum (current_gdbarch
)->hi
)
178 else if (regno
== mips_regnum (current_gdbarch
)->pc
)
179 regaddr
= EF_CP0_EPC
;
180 else if (regno
== mips_regnum (current_gdbarch
)->badvaddr
)
181 regaddr
= EF_CP0_BADVADDR
;
182 else if (regno
== MIPS_PS_REGNUM
)
183 regaddr
= EF_CP0_STATUS
;
184 else if (regno
== mips_regnum (current_gdbarch
)->cause
)
185 regaddr
= EF_CP0_CAUSE
;
191 dst
= regp
+ regaddr
;
192 regcache_raw_collect (current_regcache
, regno
, dst
);
196 /* Likewise, unpack an elf_fpregset_t. */
199 supply_fpregset (elf_fpregset_t
*fpregsetp
)
202 char zerobuf
[MAX_REGISTER_SIZE
];
204 memset (zerobuf
, 0, MAX_REGISTER_SIZE
);
206 for (regi
= 0; regi
< 32; regi
++)
207 regcache_raw_supply (current_regcache
, FP0_REGNUM
+ regi
,
208 (char *)(*fpregsetp
+ regi
));
210 regcache_raw_supply (current_regcache
,
211 mips_regnum (current_gdbarch
)->fp_control_status
,
212 (char *)(*fpregsetp
+ 32));
214 /* FIXME: how can we supply FCRIR? The ABI doesn't tell us. */
215 regcache_raw_supply (current_regcache
,
216 mips_regnum (current_gdbarch
)->fp_implementation_revision
,
220 /* Likewise, pack one or all floating point registers into an
224 fill_fpregset (elf_fpregset_t
*fpregsetp
, int regno
)
228 if ((regno
>= FP0_REGNUM
) && (regno
< FP0_REGNUM
+ 32))
230 to
= (char *) (*fpregsetp
+ regno
- FP0_REGNUM
);
231 regcache_raw_collect (current_regcache
, regno
, to
);
233 else if (regno
== mips_regnum (current_gdbarch
)->fp_control_status
)
235 to
= (char *) (*fpregsetp
+ 32);
236 regcache_raw_collect (current_regcache
, regno
, to
);
238 else if (regno
== -1)
242 for (regi
= 0; regi
< 32; regi
++)
243 fill_fpregset (fpregsetp
, FP0_REGNUM
+ regi
);
244 fill_fpregset (fpregsetp
,
245 mips_regnum (current_gdbarch
)->fp_control_status
);
249 /* Map gdb internal register number to ptrace ``address''.
250 These ``addresses'' are normally defined in <asm/ptrace.h>. */
253 mips_linux_register_addr (int regno
, CORE_ADDR blockend
)
257 if (regno
< 0 || regno
>= NUM_REGS
)
258 error (_("Bogon register number %d."), regno
);
262 else if ((regno
>= mips_regnum (current_gdbarch
)->fp0
)
263 && (regno
< mips_regnum (current_gdbarch
)->fp0
+ 32))
264 regaddr
= FPR_BASE
+ (regno
- mips_regnum (current_gdbarch
)->fp0
);
265 else if (regno
== mips_regnum (current_gdbarch
)->pc
)
267 else if (regno
== mips_regnum (current_gdbarch
)->cause
)
269 else if (regno
== mips_regnum (current_gdbarch
)->badvaddr
)
271 else if (regno
== mips_regnum (current_gdbarch
)->lo
)
273 else if (regno
== mips_regnum (current_gdbarch
)->hi
)
275 else if (regno
== mips_regnum (current_gdbarch
)->fp_control_status
)
277 else if (regno
== mips_regnum (current_gdbarch
)->fp_implementation_revision
)
280 error (_("Unknowable register number %d."), regno
);
285 /* Support for 64-bit ABIs. */
287 /* Copied from <asm/elf.h>. */
288 #define MIPS64_ELF_NGREG 45
289 #define MIPS64_ELF_NFPREG 33
291 typedef unsigned char mips64_elf_greg_t
[8];
292 typedef mips64_elf_greg_t mips64_elf_gregset_t
[MIPS64_ELF_NGREG
];
294 typedef unsigned char mips64_elf_fpreg_t
[8];
295 typedef mips64_elf_fpreg_t mips64_elf_fpregset_t
[MIPS64_ELF_NFPREG
];
297 /* 0 - 31 are integer registers, 32 - 63 are fp registers. */
298 #define MIPS64_FPR_BASE 32
300 #define MIPS64_CAUSE 65
301 #define MIPS64_BADVADDR 66
302 #define MIPS64_MMHI 67
303 #define MIPS64_MMLO 68
304 #define MIPS64_FPC_CSR 69
305 #define MIPS64_FPC_EIR 70
307 #define MIPS64_EF_REG0 0
308 #define MIPS64_EF_REG31 31
309 #define MIPS64_EF_LO 32
310 #define MIPS64_EF_HI 33
311 #define MIPS64_EF_CP0_EPC 34
312 #define MIPS64_EF_CP0_BADVADDR 35
313 #define MIPS64_EF_CP0_STATUS 36
314 #define MIPS64_EF_CP0_CAUSE 37
316 #define MIPS64_EF_SIZE 304
318 /* Figure out where the longjmp will land.
319 We expect the first arg to be a pointer to the jmp_buf structure
320 from which we extract the pc (MIPS_LINUX_JB_PC) that we will land
321 at. The pc is copied into PC. This routine returns 1 on
324 /* Details about jmp_buf. */
326 #define MIPS64_LINUX_JB_PC 0
329 mips64_linux_get_longjmp_target (CORE_ADDR
*pc
)
332 void *buf
= alloca (TARGET_PTR_BIT
/ TARGET_CHAR_BIT
);
333 int element_size
= TARGET_PTR_BIT
== 32 ? 4 : 8;
335 jb_addr
= read_register (MIPS_A0_REGNUM
);
337 if (target_read_memory (jb_addr
+ MIPS64_LINUX_JB_PC
* element_size
,
338 buf
, TARGET_PTR_BIT
/ TARGET_CHAR_BIT
))
341 *pc
= extract_unsigned_integer (buf
, TARGET_PTR_BIT
/ TARGET_CHAR_BIT
);
346 /* Unpack an elf_gregset_t into GDB's register cache. */
349 mips64_supply_gregset (mips64_elf_gregset_t
*gregsetp
)
352 mips64_elf_greg_t
*regp
= *gregsetp
;
353 char zerobuf
[MAX_REGISTER_SIZE
];
355 memset (zerobuf
, 0, MAX_REGISTER_SIZE
);
357 for (regi
= MIPS64_EF_REG0
; regi
<= MIPS64_EF_REG31
; regi
++)
358 regcache_raw_supply (current_regcache
, (regi
- MIPS64_EF_REG0
),
359 (char *)(regp
+ regi
));
361 regcache_raw_supply (current_regcache
,
362 mips_regnum (current_gdbarch
)->lo
,
363 (char *) (regp
+ MIPS64_EF_LO
));
364 regcache_raw_supply (current_regcache
,
365 mips_regnum (current_gdbarch
)->hi
,
366 (char *) (regp
+ MIPS64_EF_HI
));
368 regcache_raw_supply (current_regcache
,
369 mips_regnum (current_gdbarch
)->pc
,
370 (char *) (regp
+ MIPS64_EF_CP0_EPC
));
371 regcache_raw_supply (current_regcache
,
372 mips_regnum (current_gdbarch
)->badvaddr
,
373 (char *) (regp
+ MIPS64_EF_CP0_BADVADDR
));
374 regcache_raw_supply (current_regcache
, MIPS_PS_REGNUM
,
375 (char *) (regp
+ MIPS64_EF_CP0_STATUS
));
376 regcache_raw_supply (current_regcache
,
377 mips_regnum (current_gdbarch
)->cause
,
378 (char *) (regp
+ MIPS64_EF_CP0_CAUSE
));
380 /* Fill inaccessible registers with zero. */
381 regcache_raw_supply (current_regcache
, MIPS_UNUSED_REGNUM
, zerobuf
);
382 for (regi
= MIPS_FIRST_EMBED_REGNUM
;
383 regi
< MIPS_LAST_EMBED_REGNUM
;
385 regcache_raw_supply (current_regcache
, regi
, zerobuf
);
388 /* Pack our registers (or one register) into an elf_gregset_t. */
391 mips64_fill_gregset (mips64_elf_gregset_t
*gregsetp
, int regno
)
394 mips64_elf_greg_t
*regp
= *gregsetp
;
399 memset (regp
, 0, sizeof (mips64_elf_gregset_t
));
400 for (regi
= 0; regi
< 32; regi
++)
401 mips64_fill_gregset (gregsetp
, regi
);
402 mips64_fill_gregset (gregsetp
, mips_regnum (current_gdbarch
)->lo
);
403 mips64_fill_gregset (gregsetp
, mips_regnum (current_gdbarch
)->hi
);
404 mips64_fill_gregset (gregsetp
, mips_regnum (current_gdbarch
)->pc
);
405 mips64_fill_gregset (gregsetp
,
406 mips_regnum (current_gdbarch
)->badvaddr
);
407 mips64_fill_gregset (gregsetp
, MIPS_PS_REGNUM
);
408 mips64_fill_gregset (gregsetp
,
409 mips_regnum (current_gdbarch
)->cause
);
416 dst
= regp
+ regno
+ MIPS64_EF_REG0
;
417 regcache_raw_collect (current_regcache
, regno
, dst
);
421 if (regno
== mips_regnum (current_gdbarch
)->lo
)
422 regaddr
= MIPS64_EF_LO
;
423 else if (regno
== mips_regnum (current_gdbarch
)->hi
)
424 regaddr
= MIPS64_EF_HI
;
425 else if (regno
== mips_regnum (current_gdbarch
)->pc
)
426 regaddr
= MIPS64_EF_CP0_EPC
;
427 else if (regno
== mips_regnum (current_gdbarch
)->badvaddr
)
428 regaddr
= MIPS64_EF_CP0_BADVADDR
;
429 else if (regno
== MIPS_PS_REGNUM
)
430 regaddr
= MIPS64_EF_CP0_STATUS
;
431 else if (regno
== mips_regnum (current_gdbarch
)->cause
)
432 regaddr
= MIPS64_EF_CP0_CAUSE
;
438 dst
= regp
+ regaddr
;
439 regcache_raw_collect (current_regcache
, regno
, dst
);
443 /* Likewise, unpack an elf_fpregset_t. */
446 mips64_supply_fpregset (mips64_elf_fpregset_t
*fpregsetp
)
449 char zerobuf
[MAX_REGISTER_SIZE
];
451 memset (zerobuf
, 0, MAX_REGISTER_SIZE
);
453 for (regi
= 0; regi
< 32; regi
++)
454 regcache_raw_supply (current_regcache
, FP0_REGNUM
+ regi
,
455 (char *)(*fpregsetp
+ regi
));
457 regcache_raw_supply (current_regcache
,
458 mips_regnum (current_gdbarch
)->fp_control_status
,
459 (char *)(*fpregsetp
+ 32));
461 /* FIXME: how can we supply FCRIR? The ABI doesn't tell us. */
462 regcache_raw_supply (current_regcache
,
463 mips_regnum (current_gdbarch
)->fp_implementation_revision
,
467 /* Likewise, pack one or all floating point registers into an
471 mips64_fill_fpregset (mips64_elf_fpregset_t
*fpregsetp
, int regno
)
475 if ((regno
>= FP0_REGNUM
) && (regno
< FP0_REGNUM
+ 32))
477 to
= (char *) (*fpregsetp
+ regno
- FP0_REGNUM
);
478 regcache_raw_collect (current_regcache
, regno
, to
);
480 else if (regno
== mips_regnum (current_gdbarch
)->fp_control_status
)
482 to
= (char *) (*fpregsetp
+ 32);
483 regcache_raw_collect (current_regcache
, regno
, to
);
485 else if (regno
== -1)
489 for (regi
= 0; regi
< 32; regi
++)
490 mips64_fill_fpregset (fpregsetp
, FP0_REGNUM
+ regi
);
491 mips64_fill_fpregset(fpregsetp
,
492 mips_regnum (current_gdbarch
)->fp_control_status
);
497 /* Map gdb internal register number to ptrace ``address''.
498 These ``addresses'' are normally defined in <asm/ptrace.h>. */
501 mips64_linux_register_addr (int regno
, CORE_ADDR blockend
)
505 if (regno
< 0 || regno
>= NUM_REGS
)
506 error (_("Bogon register number %d."), regno
);
510 else if ((regno
>= mips_regnum (current_gdbarch
)->fp0
)
511 && (regno
< mips_regnum (current_gdbarch
)->fp0
+ 32))
512 regaddr
= MIPS64_FPR_BASE
+ (regno
- FP0_REGNUM
);
513 else if (regno
== mips_regnum (current_gdbarch
)->pc
)
515 else if (regno
== mips_regnum (current_gdbarch
)->cause
)
516 regaddr
= MIPS64_CAUSE
;
517 else if (regno
== mips_regnum (current_gdbarch
)->badvaddr
)
518 regaddr
= MIPS64_BADVADDR
;
519 else if (regno
== mips_regnum (current_gdbarch
)->lo
)
520 regaddr
= MIPS64_MMLO
;
521 else if (regno
== mips_regnum (current_gdbarch
)->hi
)
522 regaddr
= MIPS64_MMHI
;
523 else if (regno
== mips_regnum (current_gdbarch
)->fp_control_status
)
524 regaddr
= MIPS64_FPC_CSR
;
525 else if (regno
== mips_regnum (current_gdbarch
)->fp_implementation_revision
)
526 regaddr
= MIPS64_FPC_EIR
;
528 error (_("Unknowable register number %d."), regno
);
533 /* Use a local version of this function to get the correct types for
534 regsets, until multi-arch core support is ready. */
537 fetch_core_registers (char *core_reg_sect
, unsigned core_reg_size
,
538 int which
, CORE_ADDR reg_addr
)
540 elf_gregset_t gregset
;
541 elf_fpregset_t fpregset
;
542 mips64_elf_gregset_t gregset64
;
543 mips64_elf_fpregset_t fpregset64
;
547 if (core_reg_size
== sizeof (gregset
))
549 memcpy ((char *) &gregset
, core_reg_sect
, sizeof (gregset
));
550 supply_gregset (&gregset
);
552 else if (core_reg_size
== sizeof (gregset64
))
554 memcpy ((char *) &gregset64
, core_reg_sect
, sizeof (gregset64
));
555 mips64_supply_gregset (&gregset64
);
559 warning (_("wrong size gregset struct in core file"));
564 if (core_reg_size
== sizeof (fpregset
))
566 memcpy ((char *) &fpregset
, core_reg_sect
, sizeof (fpregset
));
567 supply_fpregset (&fpregset
);
569 else if (core_reg_size
== sizeof (fpregset64
))
571 memcpy ((char *) &fpregset64
, core_reg_sect
,
572 sizeof (fpregset64
));
573 mips64_supply_fpregset (&fpregset64
);
577 warning (_("wrong size fpregset struct in core file"));
582 /* Register that we are able to handle ELF file formats using standard
583 procfs "regset" structures. */
585 static struct core_fns regset_core_fns
=
587 bfd_target_elf_flavour
, /* core_flavour */
588 default_check_format
, /* check_format */
589 default_core_sniffer
, /* core_sniffer */
590 fetch_core_registers
, /* core_read_registers */
594 /* Handle for obtaining pointer to the current register_addr()
595 function for a given architecture. */
596 static struct gdbarch_data
*register_addr_data
;
599 register_addr (int regno
, CORE_ADDR blockend
)
601 CORE_ADDR (*register_addr_ptr
) (int, CORE_ADDR
) =
602 gdbarch_data (current_gdbarch
, register_addr_data
);
604 gdb_assert (register_addr_ptr
!= 0);
606 return register_addr_ptr (regno
, blockend
);
610 set_mips_linux_register_addr (struct gdbarch
*gdbarch
,
611 CORE_ADDR (*register_addr_ptr
) (int,
614 deprecated_set_gdbarch_data (gdbarch
, register_addr_data
,
619 init_register_addr_data (struct gdbarch
*gdbarch
)
624 /* Check the code at PC for a dynamic linker lazy resolution stub.
625 Because they aren't in the .plt section, we pattern-match on the
626 code generated by GNU ld. They look like this:
633 (with the appropriate doubleword instructions for N64). Also
634 return the dynamic symbol index used in the last instruction. */
637 mips_linux_in_dynsym_stub (CORE_ADDR pc
, char *name
)
639 unsigned char buf
[28], *p
;
640 ULONGEST insn
, insn1
;
641 int n64
= (mips_abi (current_gdbarch
) == MIPS_ABI_N64
);
643 read_memory (pc
- 12, buf
, 28);
647 /* ld t9,0x8010(gp) */
652 /* lw t9,0x8010(gp) */
659 insn
= extract_unsigned_integer (p
, 4);
667 insn
= extract_unsigned_integer (p
+ 4, 4);
671 if (insn
!= 0x03e0782d)
677 if (insn
!= 0x03e07821)
681 insn
= extract_unsigned_integer (p
+ 8, 4);
683 if (insn
!= 0x0320f809)
686 insn
= extract_unsigned_integer (p
+ 12, 4);
689 /* daddiu t8,zero,0 */
690 if ((insn
& 0xffff0000) != 0x64180000)
695 /* addiu t8,zero,0 */
696 if ((insn
& 0xffff0000) != 0x24180000)
700 return (insn
& 0xffff);
703 /* Return non-zero iff PC belongs to the dynamic linker resolution
704 code or to a stub. */
707 mips_linux_in_dynsym_resolve_code (CORE_ADDR pc
)
709 /* Check whether PC is in the dynamic linker. This also checks
710 whether it is in the .plt section, which MIPS does not use. */
711 if (in_solib_dynsym_resolve_code (pc
))
714 /* Pattern match for the stub. It would be nice if there were a
715 more efficient way to avoid this check. */
716 if (mips_linux_in_dynsym_stub (pc
, NULL
))
722 /* See the comments for SKIP_SOLIB_RESOLVER at the top of infrun.c,
723 and glibc_skip_solib_resolver in glibc-tdep.c. The normal glibc
724 implementation of this triggers at "fixup" from the same objfile as
725 "_dl_runtime_resolve"; MIPS GNU/Linux can trigger at
726 "__dl_runtime_resolve" directly. An unresolved PLT entry will
727 point to _dl_runtime_resolve, which will first call
728 __dl_runtime_resolve, and then pass control to the resolved
732 mips_linux_skip_resolver (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
734 struct minimal_symbol
*resolver
;
736 resolver
= lookup_minimal_symbol ("__dl_runtime_resolve", NULL
, NULL
);
738 if (resolver
&& SYMBOL_VALUE_ADDRESS (resolver
) == pc
)
739 return frame_pc_unwind (get_current_frame ());
744 /* Signal trampoline support. There are four supported layouts for a
745 signal frame: o32 sigframe, o32 rt_sigframe, n32 rt_sigframe, and
746 n64 rt_sigframe. We handle them all independently; not the most
747 efficient way, but simplest. First, declare all the unwinders. */
749 static void mips_linux_o32_sigframe_init (const struct tramp_frame
*self
,
750 struct frame_info
*next_frame
,
751 struct trad_frame_cache
*this_cache
,
754 static void mips_linux_n32n64_sigframe_init (const struct tramp_frame
*self
,
755 struct frame_info
*next_frame
,
756 struct trad_frame_cache
*this_cache
,
759 #define MIPS_NR_LINUX 4000
760 #define MIPS_NR_N64_LINUX 5000
761 #define MIPS_NR_N32_LINUX 6000
763 #define MIPS_NR_sigreturn MIPS_NR_LINUX + 119
764 #define MIPS_NR_rt_sigreturn MIPS_NR_LINUX + 193
765 #define MIPS_NR_N64_rt_sigreturn MIPS_NR_N64_LINUX + 211
766 #define MIPS_NR_N32_rt_sigreturn MIPS_NR_N32_LINUX + 211
768 #define MIPS_INST_LI_V0_SIGRETURN 0x24020000 + MIPS_NR_sigreturn
769 #define MIPS_INST_LI_V0_RT_SIGRETURN 0x24020000 + MIPS_NR_rt_sigreturn
770 #define MIPS_INST_LI_V0_N64_RT_SIGRETURN 0x24020000 + MIPS_NR_N64_rt_sigreturn
771 #define MIPS_INST_LI_V0_N32_RT_SIGRETURN 0x24020000 + MIPS_NR_N32_rt_sigreturn
772 #define MIPS_INST_SYSCALL 0x0000000c
774 static const struct tramp_frame mips_linux_o32_sigframe
= {
778 { MIPS_INST_LI_V0_SIGRETURN
, -1 },
779 { MIPS_INST_SYSCALL
, -1 },
780 { TRAMP_SENTINEL_INSN
, -1 }
782 mips_linux_o32_sigframe_init
785 static const struct tramp_frame mips_linux_o32_rt_sigframe
= {
789 { MIPS_INST_LI_V0_RT_SIGRETURN
, -1 },
790 { MIPS_INST_SYSCALL
, -1 },
791 { TRAMP_SENTINEL_INSN
, -1 } },
792 mips_linux_o32_sigframe_init
795 static const struct tramp_frame mips_linux_n32_rt_sigframe
= {
799 { MIPS_INST_LI_V0_N32_RT_SIGRETURN
, -1 },
800 { MIPS_INST_SYSCALL
, -1 },
801 { TRAMP_SENTINEL_INSN
, -1 }
803 mips_linux_n32n64_sigframe_init
806 static const struct tramp_frame mips_linux_n64_rt_sigframe
= {
809 { MIPS_INST_LI_V0_N64_RT_SIGRETURN
,
811 TRAMP_SENTINEL_INSN
},
812 mips_linux_n32n64_sigframe_init
816 /* The unwinder for o32 signal frames. The legacy structures look
820 u32 sf_ass[4]; [argument save space for o32]
821 u32 sf_code[2]; [signal trampoline]
822 struct sigcontext sf_sc;
827 unsigned int sc_regmask; [Unused]
828 unsigned int sc_status;
829 unsigned long long sc_pc;
830 unsigned long long sc_regs[32];
831 unsigned long long sc_fpregs[32];
832 unsigned int sc_ownedfp;
833 unsigned int sc_fpc_csr;
834 unsigned int sc_fpc_eir; [Unused]
835 unsigned int sc_used_math;
836 unsigned int sc_ssflags; [Unused]
837 [Alignment hole of four bytes]
838 unsigned long long sc_mdhi;
839 unsigned long long sc_mdlo;
841 unsigned int sc_cause; [Unused]
842 unsigned int sc_badvaddr; [Unused]
844 unsigned long sc_sigset[4]; [kernel's sigset_t]
847 The RT signal frames look like this:
850 u32 rs_ass[4]; [argument save space for o32]
851 u32 rs_code[2] [signal trampoline]
852 struct siginfo rs_info;
853 struct ucontext rs_uc;
857 unsigned long uc_flags;
858 struct ucontext *uc_link;
860 [Alignment hole of four bytes]
861 struct sigcontext uc_mcontext;
866 #define SIGFRAME_CODE_OFFSET (4 * 4)
867 #define SIGFRAME_SIGCONTEXT_OFFSET (6 * 4)
869 #define RTSIGFRAME_SIGINFO_SIZE 128
870 #define STACK_T_SIZE (3 * 4)
871 #define UCONTEXT_SIGCONTEXT_OFFSET (2 * 4 + STACK_T_SIZE + 4)
872 #define RTSIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \
873 + RTSIGFRAME_SIGINFO_SIZE \
874 + UCONTEXT_SIGCONTEXT_OFFSET)
876 #define SIGCONTEXT_PC (1 * 8)
877 #define SIGCONTEXT_REGS (2 * 8)
878 #define SIGCONTEXT_FPREGS (34 * 8)
879 #define SIGCONTEXT_FPCSR (66 * 8 + 4)
880 #define SIGCONTEXT_HI (69 * 8)
881 #define SIGCONTEXT_LO (70 * 8)
882 #define SIGCONTEXT_CAUSE (71 * 8 + 0)
883 #define SIGCONTEXT_BADVADDR (71 * 8 + 4)
885 #define SIGCONTEXT_REG_SIZE 8
888 mips_linux_o32_sigframe_init (const struct tramp_frame
*self
,
889 struct frame_info
*next_frame
,
890 struct trad_frame_cache
*this_cache
,
893 int ireg
, reg_position
;
894 CORE_ADDR sigcontext_base
= func
- SIGFRAME_CODE_OFFSET
;
895 const struct mips_regnum
*regs
= mips_regnum (current_gdbarch
);
898 if (self
== &mips_linux_o32_sigframe
)
899 sigcontext_base
+= SIGFRAME_SIGCONTEXT_OFFSET
;
901 sigcontext_base
+= RTSIGFRAME_SIGCONTEXT_OFFSET
;
903 /* I'm not proud of this hack. Eventually we will have the
904 infrastructure to indicate the size of saved registers on a
905 per-frame basis, but right now we don't; the kernel saves eight
906 bytes but we only want four. Use regs_base to access any
908 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
909 regs_base
= sigcontext_base
+ 4;
911 regs_base
= sigcontext_base
;
914 trad_frame_set_reg_addr (this_cache
, ORIG_ZERO_REGNUM
+ NUM_REGS
,
915 regs_base
+ SIGCONTEXT_REGS
);
918 for (ireg
= 1; ireg
< 32; ireg
++)
919 trad_frame_set_reg_addr (this_cache
,
920 ireg
+ MIPS_ZERO_REGNUM
+ NUM_REGS
,
921 regs_base
+ SIGCONTEXT_REGS
922 + ireg
* SIGCONTEXT_REG_SIZE
);
924 /* The way that floating point registers are saved, unfortunately,
925 depends on the architecture the kernel is built for. For the r3000 and
926 tx39, four bytes of each register are at the beginning of each of the
927 32 eight byte slots. For everything else, the registers are saved
928 using double precision; only the even-numbered slots are initialized,
929 and the high bits are the odd-numbered register. Assume the latter
930 layout, since we can't tell, and it's much more common. Which bits are
931 the "high" bits depends on endianness. */
932 for (ireg
= 0; ireg
< 32; ireg
++)
933 if ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
) != (ireg
& 1))
934 trad_frame_set_reg_addr (this_cache
, ireg
+ regs
->fp0
+ NUM_REGS
,
935 sigcontext_base
+ SIGCONTEXT_FPREGS
+ 4
936 + (ireg
& ~1) * SIGCONTEXT_REG_SIZE
);
938 trad_frame_set_reg_addr (this_cache
, ireg
+ regs
->fp0
+ NUM_REGS
,
939 sigcontext_base
+ SIGCONTEXT_FPREGS
940 + (ireg
& ~1) * SIGCONTEXT_REG_SIZE
);
942 trad_frame_set_reg_addr (this_cache
, regs
->pc
+ NUM_REGS
,
943 regs_base
+ SIGCONTEXT_PC
);
945 trad_frame_set_reg_addr (this_cache
,
946 regs
->fp_control_status
+ NUM_REGS
,
947 sigcontext_base
+ SIGCONTEXT_FPCSR
);
948 trad_frame_set_reg_addr (this_cache
, regs
->hi
+ NUM_REGS
,
949 regs_base
+ SIGCONTEXT_HI
);
950 trad_frame_set_reg_addr (this_cache
, regs
->lo
+ NUM_REGS
,
951 regs_base
+ SIGCONTEXT_LO
);
952 trad_frame_set_reg_addr (this_cache
, regs
->cause
+ NUM_REGS
,
953 sigcontext_base
+ SIGCONTEXT_CAUSE
);
954 trad_frame_set_reg_addr (this_cache
, regs
->badvaddr
+ NUM_REGS
,
955 sigcontext_base
+ SIGCONTEXT_BADVADDR
);
957 /* Choice of the bottom of the sigframe is somewhat arbitrary. */
958 trad_frame_set_id (this_cache
,
959 frame_id_build (func
- SIGFRAME_CODE_OFFSET
,
964 /* For N32/N64 things look different. There is no non-rt signal frame.
966 struct rt_sigframe_n32 {
967 u32 rs_ass[4]; [ argument save space for o32 ]
968 u32 rs_code[2]; [ signal trampoline ]
969 struct siginfo rs_info;
970 struct ucontextn32 rs_uc;
977 struct sigcontext uc_mcontext;
978 sigset_t uc_sigmask; [ mask last for extensibility ]
981 struct rt_sigframe_n32 {
982 u32 rs_ass[4]; [ argument save space for o32 ]
983 u32 rs_code[2]; [ signal trampoline ]
984 struct siginfo rs_info;
985 struct ucontext rs_uc;
989 unsigned long uc_flags;
990 struct ucontext *uc_link;
992 struct sigcontext uc_mcontext;
993 sigset_t uc_sigmask; [ mask last for extensibility ]
996 And the sigcontext is different (this is for both n32 and n64):
999 unsigned long long sc_regs[32];
1000 unsigned long long sc_fpregs[32];
1001 unsigned long long sc_mdhi;
1002 unsigned long long sc_mdlo;
1003 unsigned long long sc_pc;
1004 unsigned int sc_status;
1005 unsigned int sc_fpc_csr;
1006 unsigned int sc_fpc_eir;
1007 unsigned int sc_used_math;
1008 unsigned int sc_cause;
1009 unsigned int sc_badvaddr;
1013 #define N32_STACK_T_SIZE STACK_T_SIZE
1014 #define N64_STACK_T_SIZE (2 * 8 + 4)
1015 #define N32_UCONTEXT_SIGCONTEXT_OFFSET (2 * 4 + N32_STACK_T_SIZE + 4)
1016 #define N64_UCONTEXT_SIGCONTEXT_OFFSET (2 * 8 + N64_STACK_T_SIZE + 4)
1017 #define N32_SIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \
1018 + RTSIGFRAME_SIGINFO_SIZE \
1019 + N32_UCONTEXT_SIGCONTEXT_OFFSET)
1020 #define N64_SIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \
1021 + RTSIGFRAME_SIGINFO_SIZE \
1022 + N64_UCONTEXT_SIGCONTEXT_OFFSET)
1024 #define N64_SIGCONTEXT_REGS (0 * 8)
1025 #define N64_SIGCONTEXT_FPREGS (32 * 8)
1026 #define N64_SIGCONTEXT_HI (64 * 8)
1027 #define N64_SIGCONTEXT_LO (65 * 8)
1028 #define N64_SIGCONTEXT_PC (66 * 8)
1029 #define N64_SIGCONTEXT_FPCSR (67 * 8 + 1 * 4)
1030 #define N64_SIGCONTEXT_FIR (67 * 8 + 2 * 4)
1031 #define N64_SIGCONTEXT_CAUSE (67 * 8 + 4 * 4)
1032 #define N64_SIGCONTEXT_BADVADDR (67 * 8 + 5 * 4)
1034 #define N64_SIGCONTEXT_REG_SIZE 8
1037 mips_linux_n32n64_sigframe_init (const struct tramp_frame
*self
,
1038 struct frame_info
*next_frame
,
1039 struct trad_frame_cache
*this_cache
,
1042 int ireg
, reg_position
;
1043 CORE_ADDR sigcontext_base
= func
- SIGFRAME_CODE_OFFSET
;
1044 const struct mips_regnum
*regs
= mips_regnum (current_gdbarch
);
1046 if (self
== &mips_linux_n32_rt_sigframe
)
1047 sigcontext_base
+= N32_SIGFRAME_SIGCONTEXT_OFFSET
;
1049 sigcontext_base
+= N64_SIGFRAME_SIGCONTEXT_OFFSET
;
1052 trad_frame_set_reg_addr (this_cache
, ORIG_ZERO_REGNUM
+ NUM_REGS
,
1053 sigcontext_base
+ N64_SIGCONTEXT_REGS
);
1056 for (ireg
= 1; ireg
< 32; ireg
++)
1057 trad_frame_set_reg_addr (this_cache
,
1058 ireg
+ MIPS_ZERO_REGNUM
+ NUM_REGS
,
1059 sigcontext_base
+ N64_SIGCONTEXT_REGS
1060 + ireg
* N64_SIGCONTEXT_REG_SIZE
);
1062 for (ireg
= 0; ireg
< 32; ireg
++)
1063 trad_frame_set_reg_addr (this_cache
, ireg
+ regs
->fp0
+ NUM_REGS
,
1064 sigcontext_base
+ N64_SIGCONTEXT_FPREGS
1065 + ireg
* N64_SIGCONTEXT_REG_SIZE
);
1067 trad_frame_set_reg_addr (this_cache
, regs
->pc
+ NUM_REGS
,
1068 sigcontext_base
+ N64_SIGCONTEXT_PC
);
1070 trad_frame_set_reg_addr (this_cache
,
1071 regs
->fp_control_status
+ NUM_REGS
,
1072 sigcontext_base
+ N64_SIGCONTEXT_FPCSR
);
1073 trad_frame_set_reg_addr (this_cache
, regs
->hi
+ NUM_REGS
,
1074 sigcontext_base
+ N64_SIGCONTEXT_HI
);
1075 trad_frame_set_reg_addr (this_cache
, regs
->lo
+ NUM_REGS
,
1076 sigcontext_base
+ N64_SIGCONTEXT_LO
);
1077 trad_frame_set_reg_addr (this_cache
, regs
->cause
+ NUM_REGS
,
1078 sigcontext_base
+ N64_SIGCONTEXT_CAUSE
);
1079 trad_frame_set_reg_addr (this_cache
, regs
->badvaddr
+ NUM_REGS
,
1080 sigcontext_base
+ N64_SIGCONTEXT_BADVADDR
);
1082 /* Choice of the bottom of the sigframe is somewhat arbitrary. */
1083 trad_frame_set_id (this_cache
,
1084 frame_id_build (func
- SIGFRAME_CODE_OFFSET
,
1088 /* Initialize one of the GNU/Linux OS ABIs. */
1091 mips_linux_init_abi (struct gdbarch_info info
,
1092 struct gdbarch
*gdbarch
)
1094 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1095 enum mips_abi abi
= mips_abi (gdbarch
);
1100 set_gdbarch_get_longjmp_target (gdbarch
,
1101 mips_linux_get_longjmp_target
);
1102 set_solib_svr4_fetch_link_map_offsets
1103 (gdbarch
, svr4_ilp32_fetch_link_map_offsets
);
1104 set_mips_linux_register_addr (gdbarch
, mips_linux_register_addr
);
1105 tramp_frame_prepend_unwinder (gdbarch
, &mips_linux_o32_sigframe
);
1106 tramp_frame_prepend_unwinder (gdbarch
, &mips_linux_o32_rt_sigframe
);
1109 set_gdbarch_get_longjmp_target (gdbarch
,
1110 mips_linux_get_longjmp_target
);
1111 set_solib_svr4_fetch_link_map_offsets
1112 (gdbarch
, svr4_ilp32_fetch_link_map_offsets
);
1113 set_mips_linux_register_addr (gdbarch
, mips64_linux_register_addr
);
1114 set_gdbarch_long_double_bit (gdbarch
, 128);
1115 /* These floatformats should probably be renamed. MIPS uses
1116 the same 128-bit IEEE floating point format that IA-64 uses,
1117 except that the quiet/signalling NaN bit is reversed (GDB
1118 does not distinguish between quiet and signalling NaNs). */
1119 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1120 set_gdbarch_long_double_format (gdbarch
, &floatformat_ia64_quad_big
);
1122 set_gdbarch_long_double_format (gdbarch
, &floatformat_ia64_quad_little
);
1123 tramp_frame_prepend_unwinder (gdbarch
, &mips_linux_n32_rt_sigframe
);
1126 set_gdbarch_get_longjmp_target (gdbarch
,
1127 mips64_linux_get_longjmp_target
);
1128 set_solib_svr4_fetch_link_map_offsets
1129 (gdbarch
, svr4_lp64_fetch_link_map_offsets
);
1130 set_mips_linux_register_addr (gdbarch
, mips64_linux_register_addr
);
1131 set_gdbarch_long_double_bit (gdbarch
, 128);
1132 /* These floatformats should probably be renamed. MIPS uses
1133 the same 128-bit IEEE floating point format that IA-64 uses,
1134 except that the quiet/signalling NaN bit is reversed (GDB
1135 does not distinguish between quiet and signalling NaNs). */
1136 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1137 set_gdbarch_long_double_format (gdbarch
, &floatformat_ia64_quad_big
);
1139 set_gdbarch_long_double_format (gdbarch
, &floatformat_ia64_quad_little
);
1140 tramp_frame_prepend_unwinder (gdbarch
, &mips_linux_n64_rt_sigframe
);
1143 internal_error (__FILE__
, __LINE__
, _("can't handle ABI"));
1147 set_gdbarch_skip_solib_resolver (gdbarch
, mips_linux_skip_resolver
);
1149 set_gdbarch_software_single_step (gdbarch
, mips_software_single_step
);
1151 /* Enable TLS support. */
1152 set_gdbarch_fetch_tls_load_module_address (gdbarch
,
1153 svr4_fetch_objfile_link_map
);
1157 _initialize_mips_linux_tdep (void)
1159 const struct bfd_arch_info
*arch_info
;
1161 register_addr_data
=
1162 gdbarch_data_register_post_init (init_register_addr_data
);
1164 for (arch_info
= bfd_lookup_arch (bfd_arch_mips
, 0);
1166 arch_info
= arch_info
->next
)
1168 gdbarch_register_osabi (bfd_arch_mips
, arch_info
->mach
,
1170 mips_linux_init_abi
);
1173 deprecated_add_core_fns (®set_core_fns
);