1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988-2012 Free Software Foundation, Inc.
5 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
6 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
8 This file is part of GDB.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program. If not, see <http://www.gnu.org/licenses/>. */
24 #include "gdb_string.h"
25 #include "gdb_assert.h"
37 #include "arch-utils.h"
40 #include "mips-tdep.h"
42 #include "reggroups.h"
43 #include "opcode/mips.h"
47 #include "sim-regno.h"
49 #include "frame-unwind.h"
50 #include "frame-base.h"
51 #include "trad-frame.h"
53 #include "floatformat.h"
55 #include "target-descriptions.h"
56 #include "dwarf2-frame.h"
57 #include "user-regs.h"
61 static const struct objfile_data
*mips_pdr_data
;
63 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
65 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
66 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
67 #define ST0_FR (1 << 26)
69 /* The sizes of floating point registers. */
73 MIPS_FPU_SINGLE_REGSIZE
= 4,
74 MIPS_FPU_DOUBLE_REGSIZE
= 8
83 static const char *mips_abi_string
;
85 static const char *const mips_abi_strings
[] = {
96 /* The standard register names, and all the valid aliases for them. */
103 /* Aliases for o32 and most other ABIs. */
104 const struct register_alias mips_o32_aliases
[] = {
111 /* Aliases for n32 and n64. */
112 const struct register_alias mips_n32_n64_aliases
[] = {
119 /* Aliases for ABI-independent registers. */
120 const struct register_alias mips_register_aliases
[] = {
121 /* The architecture manuals specify these ABI-independent names for
123 #define R(n) { "r" #n, n }
124 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
125 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
126 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
127 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
130 /* k0 and k1 are sometimes called these instead (for "kernel
135 /* This is the traditional GDB name for the CP0 status register. */
136 { "sr", MIPS_PS_REGNUM
},
138 /* This is the traditional GDB name for the CP0 BadVAddr register. */
139 { "bad", MIPS_EMBED_BADVADDR_REGNUM
},
141 /* This is the traditional GDB name for the FCSR. */
142 { "fsr", MIPS_EMBED_FP0_REGNUM
+ 32 }
145 const struct register_alias mips_numeric_register_aliases
[] = {
146 #define R(n) { #n, n }
147 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
148 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
149 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
150 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
154 #ifndef MIPS_DEFAULT_FPU_TYPE
155 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
157 static int mips_fpu_type_auto
= 1;
158 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
160 static int mips_debug
= 0;
162 /* Properties (for struct target_desc) describing the g/G packet
164 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
165 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
167 struct target_desc
*mips_tdesc_gp32
;
168 struct target_desc
*mips_tdesc_gp64
;
170 const struct mips_regnum
*
171 mips_regnum (struct gdbarch
*gdbarch
)
173 return gdbarch_tdep (gdbarch
)->regnum
;
177 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
179 return mips_regnum (gdbarch
)->fp0
+ 12;
182 #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \
184 || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64)
186 #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) \
187 (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum)
189 #define MIPS_LAST_ARG_REGNUM(gdbarch) \
190 (gdbarch_tdep (gdbarch)->mips_last_arg_regnum)
192 #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type)
194 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
195 functions to test, set, or clear bit 0 of addresses. */
198 is_mips16_addr (CORE_ADDR addr
)
204 unmake_mips16_addr (CORE_ADDR addr
)
206 return ((addr
) & ~(CORE_ADDR
) 1);
210 make_mips16_addr (CORE_ADDR addr
)
212 return ((addr
) | (CORE_ADDR
) 1);
215 /* Return the MIPS ABI associated with GDBARCH. */
217 mips_abi (struct gdbarch
*gdbarch
)
219 return gdbarch_tdep (gdbarch
)->mips_abi
;
223 mips_isa_regsize (struct gdbarch
*gdbarch
)
225 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
227 /* If we know how big the registers are, use that size. */
228 if (tdep
->register_size_valid_p
)
229 return tdep
->register_size
;
231 /* Fall back to the previous behavior. */
232 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
233 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
236 /* Return the currently configured (or set) saved register size. */
239 mips_abi_regsize (struct gdbarch
*gdbarch
)
241 switch (mips_abi (gdbarch
))
243 case MIPS_ABI_EABI32
:
249 case MIPS_ABI_EABI64
:
251 case MIPS_ABI_UNKNOWN
:
254 internal_error (__FILE__
, __LINE__
, _("bad switch"));
258 /* Functions for setting and testing a bit in a minimal symbol that
259 marks it as 16-bit function. The MSB of the minimal symbol's
260 "info" field is used for this purpose.
262 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special",
263 i.e. refers to a 16-bit function, and sets a "special" bit in a
264 minimal symbol to mark it as a 16-bit function
266 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
269 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
271 if (((elf_symbol_type
*) (sym
))->internal_elf_sym
.st_other
== STO_MIPS16
)
273 MSYMBOL_TARGET_FLAG_1 (msym
) = 1;
278 msymbol_is_special (struct minimal_symbol
*msym
)
280 return MSYMBOL_TARGET_FLAG_1 (msym
);
283 /* XFER a value from the big/little/left end of the register.
284 Depending on the size of the value it might occupy the entire
285 register or just part of it. Make an allowance for this, aligning
286 things accordingly. */
289 mips_xfer_register (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
290 int reg_num
, int length
,
291 enum bfd_endian endian
, gdb_byte
*in
,
292 const gdb_byte
*out
, int buf_offset
)
296 gdb_assert (reg_num
>= gdbarch_num_regs (gdbarch
));
297 /* Need to transfer the left or right part of the register, based on
298 the targets byte order. */
302 reg_offset
= register_size (gdbarch
, reg_num
) - length
;
304 case BFD_ENDIAN_LITTLE
:
307 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
311 internal_error (__FILE__
, __LINE__
, _("bad switch"));
314 fprintf_unfiltered (gdb_stderr
,
315 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
316 reg_num
, reg_offset
, buf_offset
, length
);
317 if (mips_debug
&& out
!= NULL
)
320 fprintf_unfiltered (gdb_stdlog
, "out ");
321 for (i
= 0; i
< length
; i
++)
322 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
325 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
328 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
330 if (mips_debug
&& in
!= NULL
)
333 fprintf_unfiltered (gdb_stdlog
, "in ");
334 for (i
= 0; i
< length
; i
++)
335 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
338 fprintf_unfiltered (gdb_stdlog
, "\n");
341 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
342 compatiblity mode. A return value of 1 means that we have
343 physical 64-bit registers, but should treat them as 32-bit registers. */
346 mips2_fp_compat (struct frame_info
*frame
)
348 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
349 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
351 if (register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) == 4)
355 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
356 in all the places we deal with FP registers. PR gdb/413. */
357 /* Otherwise check the FR bit in the status register - it controls
358 the FP compatiblity mode. If it is clear we are in compatibility
360 if ((get_frame_register_unsigned (frame
, MIPS_PS_REGNUM
) & ST0_FR
) == 0)
367 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
369 static CORE_ADDR
heuristic_proc_start (struct gdbarch
*, CORE_ADDR
);
371 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
373 /* The list of available "set mips " and "show mips " commands. */
375 static struct cmd_list_element
*setmipscmdlist
= NULL
;
376 static struct cmd_list_element
*showmipscmdlist
= NULL
;
378 /* Integer registers 0 thru 31 are handled explicitly by
379 mips_register_name(). Processor specific registers 32 and above
380 are listed in the following tables. */
383 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
387 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
388 "sr", "lo", "hi", "bad", "cause", "pc",
389 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
390 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
391 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
392 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
396 /* Names of IDT R3041 registers. */
398 static const char *mips_r3041_reg_names
[] = {
399 "sr", "lo", "hi", "bad", "cause", "pc",
400 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
401 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
402 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
403 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
404 "fsr", "fir", "", /*"fp" */ "",
405 "", "", "bus", "ccfg", "", "", "", "",
406 "", "", "port", "cmp", "", "", "epc", "prid",
409 /* Names of tx39 registers. */
411 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
412 "sr", "lo", "hi", "bad", "cause", "pc",
413 "", "", "", "", "", "", "", "",
414 "", "", "", "", "", "", "", "",
415 "", "", "", "", "", "", "", "",
416 "", "", "", "", "", "", "", "",
418 "", "", "", "", "", "", "", "",
419 "", "", "config", "cache", "debug", "depc", "epc",
422 /* Names of IRIX registers. */
423 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
424 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
425 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
426 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
427 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
428 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
431 /* Names of registers with Linux kernels. */
432 static const char *mips_linux_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
433 "sr", "lo", "hi", "bad", "cause", "pc",
434 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
435 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
436 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
437 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
442 /* Return the name of the register corresponding to REGNO. */
444 mips_register_name (struct gdbarch
*gdbarch
, int regno
)
446 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
447 /* GPR names for all ABIs other than n32/n64. */
448 static char *mips_gpr_names
[] = {
449 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
450 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
451 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
452 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
455 /* GPR names for n32 and n64 ABIs. */
456 static char *mips_n32_n64_gpr_names
[] = {
457 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
458 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
459 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
460 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
463 enum mips_abi abi
= mips_abi (gdbarch
);
465 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
466 but then don't make the raw register names visible. This (upper)
467 range of user visible register numbers are the pseudo-registers.
469 This approach was adopted accommodate the following scenario:
470 It is possible to debug a 64-bit device using a 32-bit
471 programming model. In such instances, the raw registers are
472 configured to be 64-bits wide, while the pseudo registers are
473 configured to be 32-bits wide. The registers that the user
474 sees - the pseudo registers - match the users expectations
475 given the programming model being used. */
476 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
477 if (regno
< gdbarch_num_regs (gdbarch
))
480 /* The MIPS integer registers are always mapped from 0 to 31. The
481 names of the registers (which reflects the conventions regarding
482 register use) vary depending on the ABI. */
483 if (0 <= rawnum
&& rawnum
< 32)
485 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
486 return mips_n32_n64_gpr_names
[rawnum
];
488 return mips_gpr_names
[rawnum
];
490 else if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
491 return tdesc_register_name (gdbarch
, rawnum
);
492 else if (32 <= rawnum
&& rawnum
< gdbarch_num_regs (gdbarch
))
494 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
495 if (tdep
->mips_processor_reg_names
[rawnum
- 32])
496 return tdep
->mips_processor_reg_names
[rawnum
- 32];
500 internal_error (__FILE__
, __LINE__
,
501 _("mips_register_name: bad register number %d"), rawnum
);
504 /* Return the groups that a MIPS register can be categorised into. */
507 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
508 struct reggroup
*reggroup
)
513 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
514 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
515 if (reggroup
== all_reggroup
)
517 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
518 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
519 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
520 (gdbarch), as not all architectures are multi-arch. */
521 raw_p
= rawnum
< gdbarch_num_regs (gdbarch
);
522 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
523 || gdbarch_register_name (gdbarch
, regnum
)[0] == '\0')
525 if (reggroup
== float_reggroup
)
526 return float_p
&& pseudo
;
527 if (reggroup
== vector_reggroup
)
528 return vector_p
&& pseudo
;
529 if (reggroup
== general_reggroup
)
530 return (!vector_p
&& !float_p
) && pseudo
;
531 /* Save the pseudo registers. Need to make certain that any code
532 extracting register values from a saved register cache also uses
534 if (reggroup
== save_reggroup
)
535 return raw_p
&& pseudo
;
536 /* Restore the same pseudo register. */
537 if (reggroup
== restore_reggroup
)
538 return raw_p
&& pseudo
;
542 /* Return the groups that a MIPS register can be categorised into.
543 This version is only used if we have a target description which
544 describes real registers (and their groups). */
547 mips_tdesc_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
548 struct reggroup
*reggroup
)
550 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
551 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
554 /* Only save, restore, and display the pseudo registers. Need to
555 make certain that any code extracting register values from a
556 saved register cache also uses pseudo registers.
558 Note: saving and restoring the pseudo registers is slightly
559 strange; if we have 64 bits, we should save and restore all
560 64 bits. But this is hard and has little benefit. */
564 ret
= tdesc_register_in_reggroup_p (gdbarch
, rawnum
, reggroup
);
568 return mips_register_reggroup_p (gdbarch
, regnum
, reggroup
);
571 /* Map the symbol table registers which live in the range [1 *
572 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
573 registers. Take care of alignment and size problems. */
575 static enum register_status
576 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
577 int cookednum
, gdb_byte
*buf
)
579 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
580 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
581 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
582 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
583 return regcache_raw_read (regcache
, rawnum
, buf
);
584 else if (register_size (gdbarch
, rawnum
) >
585 register_size (gdbarch
, cookednum
))
587 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
588 return regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
591 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
593 enum register_status status
;
595 status
= regcache_raw_read_signed (regcache
, rawnum
, ®val
);
596 if (status
== REG_VALID
)
597 store_signed_integer (buf
, 4, byte_order
, regval
);
602 internal_error (__FILE__
, __LINE__
, _("bad register size"));
606 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
607 struct regcache
*regcache
, int cookednum
,
610 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
611 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
612 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
613 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
614 regcache_raw_write (regcache
, rawnum
, buf
);
615 else if (register_size (gdbarch
, rawnum
) >
616 register_size (gdbarch
, cookednum
))
618 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
619 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
622 /* Sign extend the shortened version of the register prior
623 to placing it in the raw register. This is required for
624 some mips64 parts in order to avoid unpredictable behavior. */
625 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
626 LONGEST regval
= extract_signed_integer (buf
, 4, byte_order
);
627 regcache_raw_write_signed (regcache
, rawnum
, regval
);
631 internal_error (__FILE__
, __LINE__
, _("bad register size"));
635 mips_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
636 struct agent_expr
*ax
, int reg
)
638 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
639 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
640 && reg
< 2 * gdbarch_num_regs (gdbarch
));
642 ax_reg_mask (ax
, rawnum
);
648 mips_ax_pseudo_register_push_stack (struct gdbarch
*gdbarch
,
649 struct agent_expr
*ax
, int reg
)
651 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
652 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
653 && reg
< 2 * gdbarch_num_regs (gdbarch
));
654 if (register_size (gdbarch
, rawnum
) >= register_size (gdbarch
, reg
))
658 if (register_size (gdbarch
, rawnum
) > register_size (gdbarch
, reg
))
660 if (!gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
661 || gdbarch_byte_order (gdbarch
) != BFD_ENDIAN_BIG
)
664 ax_simple (ax
, aop_lsh
);
667 ax_simple (ax
, aop_rsh_signed
);
671 internal_error (__FILE__
, __LINE__
, _("bad register size"));
676 /* Table to translate MIPS16 register field to actual register number. */
677 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
679 /* Heuristic_proc_start may hunt through the text section for a long
680 time across a 2400 baud serial line. Allows the user to limit this
683 static unsigned int heuristic_fence_post
= 0;
685 /* Number of bytes of storage in the actual machine representation for
686 register N. NOTE: This defines the pseudo register type so need to
687 rebuild the architecture vector. */
689 static int mips64_transfers_32bit_regs_p
= 0;
692 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
693 struct cmd_list_element
*c
)
695 struct gdbarch_info info
;
696 gdbarch_info_init (&info
);
697 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
698 instead of relying on globals. Doing that would let generic code
699 handle the search for this specific architecture. */
700 if (!gdbarch_update_p (info
))
702 mips64_transfers_32bit_regs_p
= 0;
703 error (_("32-bit compatibility mode not supported"));
707 /* Convert to/from a register and the corresponding memory value. */
709 /* This predicate tests for the case of an 8 byte floating point
710 value that is being transferred to or from a pair of floating point
711 registers each of which are (or are considered to be) only 4 bytes
714 mips_convert_register_float_case_p (struct gdbarch
*gdbarch
, int regnum
,
717 return (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
718 && register_size (gdbarch
, regnum
) == 4
719 && (regnum
% gdbarch_num_regs (gdbarch
))
720 >= mips_regnum (gdbarch
)->fp0
721 && (regnum
% gdbarch_num_regs (gdbarch
))
722 < mips_regnum (gdbarch
)->fp0
+ 32
723 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
726 /* This predicate tests for the case of a value of less than 8
727 bytes in width that is being transfered to or from an 8 byte
728 general purpose register. */
730 mips_convert_register_gpreg_case_p (struct gdbarch
*gdbarch
, int regnum
,
733 int num_regs
= gdbarch_num_regs (gdbarch
);
735 return (register_size (gdbarch
, regnum
) == 8
736 && regnum
% num_regs
> 0 && regnum
% num_regs
< 32
737 && TYPE_LENGTH (type
) < 8);
741 mips_convert_register_p (struct gdbarch
*gdbarch
,
742 int regnum
, struct type
*type
)
744 return mips_convert_register_float_case_p (gdbarch
, regnum
, type
)
745 || mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
);
749 mips_register_to_value (struct frame_info
*frame
, int regnum
,
750 struct type
*type
, gdb_byte
*to
,
751 int *optimizedp
, int *unavailablep
)
753 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
755 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
757 get_frame_register (frame
, regnum
+ 0, to
+ 4);
758 get_frame_register (frame
, regnum
+ 1, to
+ 0);
760 if (!get_frame_register_bytes (frame
, regnum
+ 0, 0, 4, to
+ 4,
761 optimizedp
, unavailablep
))
764 if (!get_frame_register_bytes (frame
, regnum
+ 1, 0, 4, to
+ 0,
765 optimizedp
, unavailablep
))
767 *optimizedp
= *unavailablep
= 0;
770 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
772 int len
= TYPE_LENGTH (type
);
775 offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 8 - len
: 0;
776 if (!get_frame_register_bytes (frame
, regnum
, offset
, len
, to
,
777 optimizedp
, unavailablep
))
780 *optimizedp
= *unavailablep
= 0;
785 internal_error (__FILE__
, __LINE__
,
786 _("mips_register_to_value: unrecognized case"));
791 mips_value_to_register (struct frame_info
*frame
, int regnum
,
792 struct type
*type
, const gdb_byte
*from
)
794 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
796 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
798 put_frame_register (frame
, regnum
+ 0, from
+ 4);
799 put_frame_register (frame
, regnum
+ 1, from
+ 0);
801 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
804 int len
= TYPE_LENGTH (type
);
806 /* Sign extend values, irrespective of type, that are stored to
807 a 64-bit general purpose register. (32-bit unsigned values
808 are stored as signed quantities within a 64-bit register.
809 When performing an operation, in compiled code, that combines
810 a 32-bit unsigned value with a signed 64-bit value, a type
811 conversion is first performed that zeroes out the high 32 bits.) */
812 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
815 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, -1);
817 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, 0);
818 put_frame_register_bytes (frame
, regnum
, 0, 8 - len
, fill
);
819 put_frame_register_bytes (frame
, regnum
, 8 - len
, len
, from
);
823 if (from
[len
-1] & 0x80)
824 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, -1);
826 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, 0);
827 put_frame_register_bytes (frame
, regnum
, 0, len
, from
);
828 put_frame_register_bytes (frame
, regnum
, len
, 8 - len
, fill
);
833 internal_error (__FILE__
, __LINE__
,
834 _("mips_value_to_register: unrecognized case"));
838 /* Return the GDB type object for the "standard" data type of data in
842 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
844 gdb_assert (regnum
>= 0 && regnum
< 2 * gdbarch_num_regs (gdbarch
));
845 if ((regnum
% gdbarch_num_regs (gdbarch
)) >= mips_regnum (gdbarch
)->fp0
846 && (regnum
% gdbarch_num_regs (gdbarch
))
847 < mips_regnum (gdbarch
)->fp0
+ 32)
849 /* The floating-point registers raw, or cooked, always match
850 mips_isa_regsize(), and also map 1:1, byte for byte. */
851 if (mips_isa_regsize (gdbarch
) == 4)
852 return builtin_type (gdbarch
)->builtin_float
;
854 return builtin_type (gdbarch
)->builtin_double
;
856 else if (regnum
< gdbarch_num_regs (gdbarch
))
858 /* The raw or ISA registers. These are all sized according to
860 if (mips_isa_regsize (gdbarch
) == 4)
861 return builtin_type (gdbarch
)->builtin_int32
;
863 return builtin_type (gdbarch
)->builtin_int64
;
867 int rawnum
= regnum
- gdbarch_num_regs (gdbarch
);
869 /* The cooked or ABI registers. These are sized according to
870 the ABI (with a few complications). */
871 if (rawnum
== mips_regnum (gdbarch
)->fp_control_status
872 || rawnum
== mips_regnum (gdbarch
)->fp_implementation_revision
)
873 return builtin_type (gdbarch
)->builtin_int32
;
874 else if (gdbarch_osabi (gdbarch
) != GDB_OSABI_IRIX
875 && gdbarch_osabi (gdbarch
) != GDB_OSABI_LINUX
876 && rawnum
>= MIPS_FIRST_EMBED_REGNUM
877 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
878 /* The pseudo/cooked view of the embedded registers is always
879 32-bit. The raw view is handled below. */
880 return builtin_type (gdbarch
)->builtin_int32
;
881 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
882 /* The target, while possibly using a 64-bit register buffer,
883 is only transfering 32-bits of each integer register.
884 Reflect this in the cooked/pseudo (ABI) register value. */
885 return builtin_type (gdbarch
)->builtin_int32
;
886 else if (mips_abi_regsize (gdbarch
) == 4)
887 /* The ABI is restricted to 32-bit registers (the ISA could be
889 return builtin_type (gdbarch
)->builtin_int32
;
892 return builtin_type (gdbarch
)->builtin_int64
;
896 /* Return the GDB type for the pseudo register REGNUM, which is the
897 ABI-level view. This function is only called if there is a target
898 description which includes registers, so we know precisely the
899 types of hardware registers. */
902 mips_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
904 const int num_regs
= gdbarch_num_regs (gdbarch
);
905 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
906 int rawnum
= regnum
% num_regs
;
907 struct type
*rawtype
;
909 gdb_assert (regnum
>= num_regs
&& regnum
< 2 * num_regs
);
911 /* Absent registers are still absent. */
912 rawtype
= gdbarch_register_type (gdbarch
, rawnum
);
913 if (TYPE_LENGTH (rawtype
) == 0)
916 if (rawnum
>= mips_regnum (gdbarch
)->fp0
917 && rawnum
< mips_regnum (gdbarch
)->fp0
+ 32)
918 /* Present the floating point registers however the hardware did;
919 do not try to convert between FPU layouts. */
922 /* Use pointer types for registers if we can. For n32 we can not,
923 since we do not have a 64-bit pointer type. */
924 if (mips_abi_regsize (gdbarch
)
925 == TYPE_LENGTH (builtin_type (gdbarch
)->builtin_data_ptr
))
927 if (rawnum
== MIPS_SP_REGNUM
928 || rawnum
== mips_regnum (gdbarch
)->badvaddr
)
929 return builtin_type (gdbarch
)->builtin_data_ptr
;
930 else if (rawnum
== mips_regnum (gdbarch
)->pc
)
931 return builtin_type (gdbarch
)->builtin_func_ptr
;
934 if (mips_abi_regsize (gdbarch
) == 4 && TYPE_LENGTH (rawtype
) == 8
935 && ((rawnum
>= MIPS_ZERO_REGNUM
&& rawnum
<= MIPS_PS_REGNUM
)
936 || rawnum
== mips_regnum (gdbarch
)->lo
937 || rawnum
== mips_regnum (gdbarch
)->hi
938 || rawnum
== mips_regnum (gdbarch
)->badvaddr
939 || rawnum
== mips_regnum (gdbarch
)->cause
940 || rawnum
== mips_regnum (gdbarch
)->pc
941 || (mips_regnum (gdbarch
)->dspacc
!= -1
942 && rawnum
>= mips_regnum (gdbarch
)->dspacc
943 && rawnum
< mips_regnum (gdbarch
)->dspacc
+ 6)))
944 return builtin_type (gdbarch
)->builtin_int32
;
946 if (gdbarch_osabi (gdbarch
) != GDB_OSABI_IRIX
947 && gdbarch_osabi (gdbarch
) != GDB_OSABI_LINUX
948 && rawnum
>= MIPS_EMBED_FP0_REGNUM
+ 32
949 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
951 /* The pseudo/cooked view of embedded registers is always
952 32-bit, even if the target transfers 64-bit values for them.
953 New targets relying on XML descriptions should only transfer
954 the necessary 32 bits, but older versions of GDB expected 64,
955 so allow the target to provide 64 bits without interfering
956 with the displayed type. */
957 return builtin_type (gdbarch
)->builtin_int32
;
960 /* For all other registers, pass through the hardware type. */
964 /* Should the upper word of 64-bit addresses be zeroed? */
965 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
968 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
970 switch (mask_address_var
)
972 case AUTO_BOOLEAN_TRUE
:
974 case AUTO_BOOLEAN_FALSE
:
977 case AUTO_BOOLEAN_AUTO
:
978 return tdep
->default_mask_address_p
;
980 internal_error (__FILE__
, __LINE__
,
981 _("mips_mask_address_p: bad switch"));
987 show_mask_address (struct ui_file
*file
, int from_tty
,
988 struct cmd_list_element
*c
, const char *value
)
990 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch
);
992 deprecated_show_value_hack (file
, from_tty
, c
, value
);
993 switch (mask_address_var
)
995 case AUTO_BOOLEAN_TRUE
:
996 printf_filtered ("The 32 bit mips address mask is enabled\n");
998 case AUTO_BOOLEAN_FALSE
:
999 printf_filtered ("The 32 bit mips address mask is disabled\n");
1001 case AUTO_BOOLEAN_AUTO
:
1003 ("The 32 bit address mask is set automatically. Currently %s\n",
1004 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
1007 internal_error (__FILE__
, __LINE__
, _("show_mask_address: bad switch"));
1012 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
1015 mips_pc_is_mips16 (CORE_ADDR memaddr
)
1017 struct minimal_symbol
*sym
;
1019 /* A flag indicating that this is a MIPS16 function is stored by
1020 elfread.c in the high bit of the info field. Use this to decide
1021 if the function is MIPS16 or normal MIPS. Otherwise if bit 0 of
1022 the address is set, assume this is a MIPS16 address. */
1023 sym
= lookup_minimal_symbol_by_pc (memaddr
);
1025 return msymbol_is_special (sym
);
1027 return is_mips16_addr (memaddr
);
1030 /* MIPS believes that the PC has a sign extended value. Perhaps the
1031 all registers should be sign extended for simplicity? */
1034 mips_read_pc (struct regcache
*regcache
)
1037 int regnum
= mips_regnum (get_regcache_arch (regcache
))->pc
;
1038 regcache_cooked_read_signed (regcache
, regnum
, &pc
);
1039 if (is_mips16_addr (pc
))
1040 pc
= unmake_mips16_addr (pc
);
1045 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1049 pc
= frame_unwind_register_signed
1050 (next_frame
, gdbarch_num_regs (gdbarch
) + mips_regnum (gdbarch
)->pc
);
1051 if (is_mips16_addr (pc
))
1052 pc
= unmake_mips16_addr (pc
);
1057 mips_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1059 return frame_unwind_register_signed
1060 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
);
1063 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
1064 dummy frame. The frame ID's base needs to match the TOS value
1065 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
1068 static struct frame_id
1069 mips_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1071 return frame_id_build
1072 (get_frame_register_signed (this_frame
,
1073 gdbarch_num_regs (gdbarch
)
1075 get_frame_pc (this_frame
));
1079 mips_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1081 int regnum
= mips_regnum (get_regcache_arch (regcache
))->pc
;
1082 if (mips_pc_is_mips16 (pc
))
1083 regcache_cooked_write_unsigned (regcache
, regnum
, make_mips16_addr (pc
));
1085 regcache_cooked_write_unsigned (regcache
, regnum
, pc
);
1088 /* Fetch and return instruction from the specified location. If the PC
1089 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
1092 mips_fetch_instruction (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
1094 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1095 gdb_byte buf
[MIPS_INSN32_SIZE
];
1099 if (mips_pc_is_mips16 (addr
))
1101 instlen
= MIPS_INSN16_SIZE
;
1102 addr
= unmake_mips16_addr (addr
);
1105 instlen
= MIPS_INSN32_SIZE
;
1106 status
= target_read_memory (addr
, buf
, instlen
);
1108 memory_error (status
, addr
);
1109 return extract_unsigned_integer (buf
, instlen
, byte_order
);
1112 /* These are the fields of 32 bit mips instructions. */
1113 #define mips32_op(x) (x >> 26)
1114 #define itype_op(x) (x >> 26)
1115 #define itype_rs(x) ((x >> 21) & 0x1f)
1116 #define itype_rt(x) ((x >> 16) & 0x1f)
1117 #define itype_immediate(x) (x & 0xffff)
1119 #define jtype_op(x) (x >> 26)
1120 #define jtype_target(x) (x & 0x03ffffff)
1122 #define rtype_op(x) (x >> 26)
1123 #define rtype_rs(x) ((x >> 21) & 0x1f)
1124 #define rtype_rt(x) ((x >> 16) & 0x1f)
1125 #define rtype_rd(x) ((x >> 11) & 0x1f)
1126 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1127 #define rtype_funct(x) (x & 0x3f)
1130 mips32_relative_offset (ULONGEST inst
)
1132 return ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 2;
1135 /* Determine the address of the next instruction executed after the INST
1136 floating condition branch instruction at PC. COUNT specifies the
1137 number of the floating condition bits tested by the branch. */
1140 mips32_bc1_pc (struct gdbarch
*gdbarch
, struct frame_info
*frame
,
1141 ULONGEST inst
, CORE_ADDR pc
, int count
)
1143 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
1144 int cnum
= (itype_rt (inst
) >> 2) & (count
- 1);
1145 int tf
= itype_rt (inst
) & 1;
1146 int mask
= (1 << count
) - 1;
1151 /* No way to handle; it'll most likely trap anyway. */
1154 fcs
= get_frame_register_unsigned (frame
, fcsr
);
1155 cond
= ((fcs
>> 24) & 0xfe) | ((fcs
>> 23) & 0x01);
1157 if (((cond
>> cnum
) & mask
) != mask
* !tf
)
1158 pc
+= mips32_relative_offset (inst
);
1165 /* Determine where to set a single step breakpoint while considering
1166 branch prediction. */
1168 mips32_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1170 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1173 inst
= mips_fetch_instruction (gdbarch
, pc
);
1174 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch
1177 if (itype_op (inst
) >> 2 == 5)
1178 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1180 op
= (itype_op (inst
) & 0x03);
1190 goto greater_branch
;
1195 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
1196 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1197 pc
= mips32_bc1_pc (gdbarch
, frame
, inst
, pc
+ 4, 1);
1198 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 9
1199 && (itype_rt (inst
) & 2) == 0)
1200 /* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */
1201 pc
= mips32_bc1_pc (gdbarch
, frame
, inst
, pc
+ 4, 2);
1202 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 10
1203 && (itype_rt (inst
) & 2) == 0)
1204 /* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */
1205 pc
= mips32_bc1_pc (gdbarch
, frame
, inst
, pc
+ 4, 4);
1207 pc
+= 4; /* Not a branch, next instruction is easy. */
1210 { /* This gets way messy. */
1212 /* Further subdivide into SPECIAL, REGIMM and other. */
1213 switch (op
= itype_op (inst
) & 0x07) /* Extract bits 28,27,26. */
1215 case 0: /* SPECIAL */
1216 op
= rtype_funct (inst
);
1221 /* Set PC to that address. */
1222 pc
= get_frame_register_signed (frame
, rtype_rs (inst
));
1224 case 12: /* SYSCALL */
1226 struct gdbarch_tdep
*tdep
;
1228 tdep
= gdbarch_tdep (get_frame_arch (frame
));
1229 if (tdep
->syscall_next_pc
!= NULL
)
1230 pc
= tdep
->syscall_next_pc (frame
);
1239 break; /* end SPECIAL */
1240 case 1: /* REGIMM */
1242 op
= itype_rt (inst
); /* branch condition */
1247 case 16: /* BLTZAL */
1248 case 18: /* BLTZALL */
1250 if (get_frame_register_signed (frame
, itype_rs (inst
)) < 0)
1251 pc
+= mips32_relative_offset (inst
) + 4;
1253 pc
+= 8; /* after the delay slot */
1257 case 17: /* BGEZAL */
1258 case 19: /* BGEZALL */
1259 if (get_frame_register_signed (frame
, itype_rs (inst
)) >= 0)
1260 pc
+= mips32_relative_offset (inst
) + 4;
1262 pc
+= 8; /* after the delay slot */
1264 case 0x1c: /* BPOSGE32 */
1265 case 0x1e: /* BPOSGE64 */
1267 if (itype_rs (inst
) == 0)
1269 unsigned int pos
= (op
& 2) ? 64 : 32;
1270 int dspctl
= mips_regnum (gdbarch
)->dspctl
;
1273 /* No way to handle; it'll most likely trap anyway. */
1276 if ((get_frame_register_unsigned (frame
,
1277 dspctl
) & 0x7f) >= pos
)
1278 pc
+= mips32_relative_offset (inst
);
1283 /* All of the other instructions in the REGIMM category */
1288 break; /* end REGIMM */
1293 reg
= jtype_target (inst
) << 2;
1294 /* Upper four bits get never changed... */
1295 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
1298 /* FIXME case JALX : */
1301 reg
= jtype_target (inst
) << 2;
1302 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff) + 1; /* yes, +1 */
1303 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1305 break; /* The new PC will be alternate mode */
1306 case 4: /* BEQ, BEQL */
1308 if (get_frame_register_signed (frame
, itype_rs (inst
)) ==
1309 get_frame_register_signed (frame
, itype_rt (inst
)))
1310 pc
+= mips32_relative_offset (inst
) + 4;
1314 case 5: /* BNE, BNEL */
1316 if (get_frame_register_signed (frame
, itype_rs (inst
)) !=
1317 get_frame_register_signed (frame
, itype_rt (inst
)))
1318 pc
+= mips32_relative_offset (inst
) + 4;
1322 case 6: /* BLEZ, BLEZL */
1323 if (get_frame_register_signed (frame
, itype_rs (inst
)) <= 0)
1324 pc
+= mips32_relative_offset (inst
) + 4;
1330 greater_branch
: /* BGTZ, BGTZL */
1331 if (get_frame_register_signed (frame
, itype_rs (inst
)) > 0)
1332 pc
+= mips32_relative_offset (inst
) + 4;
1339 } /* mips32_next_pc */
1341 /* Decoding the next place to set a breakpoint is irregular for the
1342 mips 16 variant, but fortunately, there fewer instructions. We have
1343 to cope ith extensions for 16 bit instructions and a pair of actual
1344 32 bit instructions. We dont want to set a single step instruction
1345 on the extend instruction either. */
1347 /* Lots of mips16 instruction formats */
1348 /* Predicting jumps requires itype,ritype,i8type
1349 and their extensions extItype,extritype,extI8type. */
1350 enum mips16_inst_fmts
1352 itype
, /* 0 immediate 5,10 */
1353 ritype
, /* 1 5,3,8 */
1354 rrtype
, /* 2 5,3,3,5 */
1355 rritype
, /* 3 5,3,3,5 */
1356 rrrtype
, /* 4 5,3,3,3,2 */
1357 rriatype
, /* 5 5,3,3,1,4 */
1358 shifttype
, /* 6 5,3,3,3,2 */
1359 i8type
, /* 7 5,3,8 */
1360 i8movtype
, /* 8 5,3,3,5 */
1361 i8mov32rtype
, /* 9 5,3,5,3 */
1362 i64type
, /* 10 5,3,8 */
1363 ri64type
, /* 11 5,3,3,5 */
1364 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1365 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1366 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1367 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1368 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1369 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1370 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1371 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1372 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1373 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1375 /* I am heaping all the fields of the formats into one structure and
1376 then, only the fields which are involved in instruction extension. */
1380 unsigned int regx
; /* Function in i8 type. */
1385 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1386 for the bits which make up the immediate extension. */
1389 extended_offset (unsigned int extension
)
1393 value
= (extension
>> 16) & 0x1f; /* Extract 15:11. */
1395 value
|= (extension
>> 21) & 0x3f; /* Extract 10:5. */
1397 value
|= extension
& 0x1f; /* Extract 4:0. */
1402 /* Only call this function if you know that this is an extendable
1403 instruction. It won't malfunction, but why make excess remote memory
1404 references? If the immediate operands get sign extended or something,
1405 do it after the extension is performed. */
1406 /* FIXME: Every one of these cases needs to worry about sign extension
1407 when the offset is to be used in relative addressing. */
1410 fetch_mips_16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1412 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1414 pc
&= 0xfffffffe; /* Clear the low order bit. */
1415 target_read_memory (pc
, buf
, 2);
1416 return extract_unsigned_integer (buf
, 2, byte_order
);
1420 unpack_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
,
1421 unsigned int extension
,
1423 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
1428 switch (insn_format
)
1435 value
= extended_offset ((extension
<< 16) | inst
);
1436 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
1440 value
= inst
& 0x7ff;
1441 value
= (value
^ 0x400) - 0x400; /* Sign-extend. */
1450 { /* A register identifier and an offset. */
1451 /* Most of the fields are the same as I type but the
1452 immediate value is of a different length. */
1456 value
= extended_offset ((extension
<< 16) | inst
);
1457 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
1461 value
= inst
& 0xff; /* 8 bits */
1462 value
= (value
^ 0x80) - 0x80; /* Sign-extend. */
1465 regx
= (inst
>> 8) & 0x07; /* i8 funct */
1471 unsigned long value
;
1472 unsigned int nexthalf
;
1473 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1474 value
= value
<< 16;
1475 nexthalf
= mips_fetch_instruction (gdbarch
, pc
+ 2); /* low bit
1484 internal_error (__FILE__
, __LINE__
, _("bad switch"));
1486 upk
->offset
= offset
;
1493 add_offset_16 (CORE_ADDR pc
, int offset
)
1495 return ((offset
<< 2) | ((pc
+ 2) & (~(CORE_ADDR
) 0x0fffffff)));
1499 extended_mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
,
1500 unsigned int extension
, unsigned int insn
)
1502 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1503 int op
= (insn
>> 11);
1506 case 2: /* Branch */
1509 struct upk_mips16 upk
;
1510 unpack_mips16 (gdbarch
, pc
, extension
, insn
, itype
, &upk
);
1511 pc
+= (upk
.offset
<< 1) + 2;
1514 case 3: /* JAL , JALX - Watch out, these are 32 bit
1517 struct upk_mips16 upk
;
1518 unpack_mips16 (gdbarch
, pc
, extension
, insn
, jalxtype
, &upk
);
1519 pc
= add_offset_16 (pc
, upk
.offset
);
1520 if ((insn
>> 10) & 0x01) /* Exchange mode */
1521 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode. */
1528 struct upk_mips16 upk
;
1530 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
1531 reg
= get_frame_register_signed (frame
, mips16_to_32_reg
[upk
.regx
]);
1533 pc
+= (upk
.offset
<< 1) + 2;
1540 struct upk_mips16 upk
;
1542 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
1543 reg
= get_frame_register_signed (frame
, mips16_to_32_reg
[upk
.regx
]);
1545 pc
+= (upk
.offset
<< 1) + 2;
1550 case 12: /* I8 Formats btez btnez */
1552 struct upk_mips16 upk
;
1554 unpack_mips16 (gdbarch
, pc
, extension
, insn
, i8type
, &upk
);
1555 /* upk.regx contains the opcode */
1556 reg
= get_frame_register_signed (frame
, 24); /* Test register is 24 */
1557 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1558 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1559 /* pc = add_offset_16(pc,upk.offset) ; */
1560 pc
+= (upk
.offset
<< 1) + 2;
1565 case 29: /* RR Formats JR, JALR, JALR-RA */
1567 struct upk_mips16 upk
;
1568 /* upk.fmt = rrtype; */
1573 upk
.regx
= (insn
>> 8) & 0x07;
1574 upk
.regy
= (insn
>> 5) & 0x07;
1575 if ((upk
.regy
& 1) == 0)
1576 reg
= mips16_to_32_reg
[upk
.regx
];
1578 reg
= 31; /* Function return instruction. */
1579 pc
= get_frame_register_signed (frame
, reg
);
1586 /* This is an instruction extension. Fetch the real instruction
1587 (which follows the extension) and decode things based on
1591 pc
= extended_mips16_next_pc (frame
, pc
, insn
,
1592 fetch_mips_16 (gdbarch
, pc
));
1605 mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1607 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1608 unsigned int insn
= fetch_mips_16 (gdbarch
, pc
);
1609 return extended_mips16_next_pc (frame
, pc
, 0, insn
);
1612 /* The mips_next_pc function supports single_step when the remote
1613 target monitor or stub is not developed enough to do a single_step.
1614 It works by decoding the current instruction and predicting where a
1615 branch will go. This isnt hard because all the data is available.
1616 The MIPS32 and MIPS16 variants are quite different. */
1618 mips_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1620 if (mips_pc_is_mips16 (pc
))
1621 return mips16_next_pc (frame
, pc
);
1623 return mips32_next_pc (frame
, pc
);
1626 struct mips_frame_cache
1629 struct trad_frame_saved_reg
*saved_regs
;
1632 /* Set a register's saved stack address in temp_saved_regs. If an
1633 address has already been set for this register, do nothing; this
1634 way we will only recognize the first save of a given register in a
1637 For simplicity, save the address in both [0 .. gdbarch_num_regs) and
1638 [gdbarch_num_regs .. 2*gdbarch_num_regs).
1639 Strictly speaking, only the second range is used as it is only second
1640 range (the ABI instead of ISA registers) that comes into play when finding
1641 saved registers in a frame. */
1644 set_reg_offset (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
,
1645 int regnum
, CORE_ADDR offset
)
1647 if (this_cache
!= NULL
1648 && this_cache
->saved_regs
[regnum
].addr
== -1)
1650 this_cache
->saved_regs
[regnum
+ 0 * gdbarch_num_regs (gdbarch
)].addr
1652 this_cache
->saved_regs
[regnum
+ 1 * gdbarch_num_regs (gdbarch
)].addr
1658 /* Fetch the immediate value from a MIPS16 instruction.
1659 If the previous instruction was an EXTEND, use it to extend
1660 the upper bits of the immediate value. This is a helper function
1661 for mips16_scan_prologue. */
1664 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
1665 unsigned short inst
, /* current instruction */
1666 int nbits
, /* number of bits in imm field */
1667 int scale
, /* scale factor to be applied to imm */
1668 int is_signed
) /* is the imm field signed? */
1672 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1674 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1675 if (offset
& 0x8000) /* check for negative extend */
1676 offset
= 0 - (0x10000 - (offset
& 0xffff));
1677 return offset
| (inst
& 0x1f);
1681 int max_imm
= 1 << nbits
;
1682 int mask
= max_imm
- 1;
1683 int sign_bit
= max_imm
>> 1;
1685 offset
= inst
& mask
;
1686 if (is_signed
&& (offset
& sign_bit
))
1687 offset
= 0 - (max_imm
- offset
);
1688 return offset
* scale
;
1693 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1694 the associated FRAME_CACHE if not null.
1695 Return the address of the first instruction past the prologue. */
1698 mips16_scan_prologue (struct gdbarch
*gdbarch
,
1699 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1700 struct frame_info
*this_frame
,
1701 struct mips_frame_cache
*this_cache
)
1704 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer. */
1706 long frame_offset
= 0; /* Size of stack frame. */
1707 long frame_adjust
= 0; /* Offset of FP from SP. */
1708 int frame_reg
= MIPS_SP_REGNUM
;
1709 unsigned short prev_inst
= 0; /* saved copy of previous instruction. */
1710 unsigned inst
= 0; /* current instruction */
1711 unsigned entry_inst
= 0; /* the entry instruction */
1712 unsigned save_inst
= 0; /* the save instruction */
1715 int extend_bytes
= 0;
1716 int prev_extend_bytes
;
1717 CORE_ADDR end_prologue_addr
= 0;
1719 /* Can be called when there's no process, and hence when there's no
1721 if (this_frame
!= NULL
)
1722 sp
= get_frame_register_signed (this_frame
,
1723 gdbarch_num_regs (gdbarch
)
1728 if (limit_pc
> start_pc
+ 200)
1729 limit_pc
= start_pc
+ 200;
1731 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN16_SIZE
)
1733 /* Save the previous instruction. If it's an EXTEND, we'll extract
1734 the immediate offset extension from it in mips16_get_imm. */
1737 /* Fetch and decode the instruction. */
1738 inst
= (unsigned short) mips_fetch_instruction (gdbarch
, cur_pc
);
1740 /* Normally we ignore extend instructions. However, if it is
1741 not followed by a valid prologue instruction, then this
1742 instruction is not part of the prologue either. We must
1743 remember in this case to adjust the end_prologue_addr back
1745 if ((inst
& 0xf800) == 0xf000) /* extend */
1747 extend_bytes
= MIPS_INSN16_SIZE
;
1751 prev_extend_bytes
= extend_bytes
;
1754 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1755 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1757 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1758 if (offset
< 0) /* Negative stack adjustment? */
1759 frame_offset
-= offset
;
1761 /* Exit loop if a positive stack adjustment is found, which
1762 usually means that the stack cleanup code in the function
1763 epilogue is reached. */
1766 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1768 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1769 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1770 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1772 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1774 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1775 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1776 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1778 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1780 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1781 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1783 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1785 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1786 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1788 else if (inst
== 0x673d) /* move $s1, $sp */
1793 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1795 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1796 frame_addr
= sp
+ offset
;
1798 frame_adjust
= offset
;
1800 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1802 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1803 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1804 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
1806 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1808 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1809 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1810 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
1812 else if ((inst
& 0xf81f) == 0xe809
1813 && (inst
& 0x700) != 0x700) /* entry */
1814 entry_inst
= inst
; /* Save for later processing. */
1815 else if ((inst
& 0xff80) == 0x6480) /* save */
1817 save_inst
= inst
; /* Save for later processing. */
1818 if (prev_extend_bytes
) /* extend */
1819 save_inst
|= prev_inst
<< 16;
1821 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1822 cur_pc
+= MIPS_INSN16_SIZE
; /* 32-bit instruction */
1823 else if ((inst
& 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
1825 /* This instruction is part of the prologue, but we don't
1826 need to do anything special to handle it. */
1830 /* This instruction is not an instruction typically found
1831 in a prologue, so we must have reached the end of the
1833 if (end_prologue_addr
== 0)
1834 end_prologue_addr
= cur_pc
- prev_extend_bytes
;
1838 /* The entry instruction is typically the first instruction in a function,
1839 and it stores registers at offsets relative to the value of the old SP
1840 (before the prologue). But the value of the sp parameter to this
1841 function is the new SP (after the prologue has been executed). So we
1842 can't calculate those offsets until we've seen the entire prologue,
1843 and can calculate what the old SP must have been. */
1844 if (entry_inst
!= 0)
1846 int areg_count
= (entry_inst
>> 8) & 7;
1847 int sreg_count
= (entry_inst
>> 6) & 3;
1849 /* The entry instruction always subtracts 32 from the SP. */
1852 /* Now we can calculate what the SP must have been at the
1853 start of the function prologue. */
1856 /* Check if a0-a3 were saved in the caller's argument save area. */
1857 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
1859 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1860 offset
+= mips_abi_regsize (gdbarch
);
1863 /* Check if the ra register was pushed on the stack. */
1865 if (entry_inst
& 0x20)
1867 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1868 offset
-= mips_abi_regsize (gdbarch
);
1871 /* Check if the s0 and s1 registers were pushed on the stack. */
1872 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1874 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1875 offset
-= mips_abi_regsize (gdbarch
);
1879 /* The SAVE instruction is similar to ENTRY, except that defined by the
1880 MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the
1881 size of the frame is specified as an immediate field of instruction
1882 and an extended variation exists which lets additional registers and
1883 frame space to be specified. The instruction always treats registers
1884 as 32-bit so its usefulness for 64-bit ABIs is questionable. */
1885 if (save_inst
!= 0 && mips_abi_regsize (gdbarch
) == 4)
1887 static int args_table
[16] = {
1888 0, 0, 0, 0, 1, 1, 1, 1,
1889 2, 2, 2, 0, 3, 3, 4, -1,
1891 static int astatic_table
[16] = {
1892 0, 1, 2, 3, 0, 1, 2, 3,
1893 0, 1, 2, 4, 0, 1, 0, -1,
1895 int aregs
= (save_inst
>> 16) & 0xf;
1896 int xsregs
= (save_inst
>> 24) & 0x7;
1897 int args
= args_table
[aregs
];
1898 int astatic
= astatic_table
[aregs
];
1903 warning (_("Invalid number of argument registers encoded in SAVE."));
1908 warning (_("Invalid number of static registers encoded in SAVE."));
1912 /* For standard SAVE the frame size of 0 means 128. */
1913 frame_size
= ((save_inst
>> 16) & 0xf0) | (save_inst
& 0xf);
1914 if (frame_size
== 0 && (save_inst
>> 16) == 0)
1917 frame_offset
+= frame_size
;
1919 /* Now we can calculate what the SP must have been at the
1920 start of the function prologue. */
1923 /* Check if A0-A3 were saved in the caller's argument save area. */
1924 for (reg
= MIPS_A0_REGNUM
, offset
= 0; reg
< args
+ 4; reg
++)
1926 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1927 offset
+= mips_abi_regsize (gdbarch
);
1932 /* Check if the RA register was pushed on the stack. */
1933 if (save_inst
& 0x40)
1935 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1936 offset
-= mips_abi_regsize (gdbarch
);
1939 /* Check if the S8 register was pushed on the stack. */
1942 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ offset
);
1943 offset
-= mips_abi_regsize (gdbarch
);
1946 /* Check if S2-S7 were pushed on the stack. */
1947 for (reg
= 18 + xsregs
- 1; reg
> 18 - 1; reg
--)
1949 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1950 offset
-= mips_abi_regsize (gdbarch
);
1953 /* Check if the S1 register was pushed on the stack. */
1954 if (save_inst
& 0x10)
1956 set_reg_offset (gdbarch
, this_cache
, 17, sp
+ offset
);
1957 offset
-= mips_abi_regsize (gdbarch
);
1959 /* Check if the S0 register was pushed on the stack. */
1960 if (save_inst
& 0x20)
1962 set_reg_offset (gdbarch
, this_cache
, 16, sp
+ offset
);
1963 offset
-= mips_abi_regsize (gdbarch
);
1966 /* Check if A0-A3 were pushed on the stack. */
1967 for (reg
= MIPS_A0_REGNUM
+ 3; reg
> MIPS_A0_REGNUM
+ 3 - astatic
; reg
--)
1969 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1970 offset
-= mips_abi_regsize (gdbarch
);
1974 if (this_cache
!= NULL
)
1977 (get_frame_register_signed (this_frame
,
1978 gdbarch_num_regs (gdbarch
) + frame_reg
)
1979 + frame_offset
- frame_adjust
);
1980 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
1981 be able to get rid of the assignment below, evetually. But it's
1982 still needed for now. */
1983 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
1984 + mips_regnum (gdbarch
)->pc
]
1985 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
1988 /* If we didn't reach the end of the prologue when scanning the function
1989 instructions, then set end_prologue_addr to the address of the
1990 instruction immediately after the last one we scanned. */
1991 if (end_prologue_addr
== 0)
1992 end_prologue_addr
= cur_pc
;
1994 return end_prologue_addr
;
1997 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
1998 Procedures that use the 32-bit instruction set are handled by the
1999 mips_insn32 unwinder. */
2001 static struct mips_frame_cache
*
2002 mips_insn16_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2004 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2005 struct mips_frame_cache
*cache
;
2007 if ((*this_cache
) != NULL
)
2008 return (*this_cache
);
2009 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2010 (*this_cache
) = cache
;
2011 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2013 /* Analyze the function prologue. */
2015 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2016 CORE_ADDR start_addr
;
2018 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2019 if (start_addr
== 0)
2020 start_addr
= heuristic_proc_start (gdbarch
, pc
);
2021 /* We can't analyze the prologue if we couldn't find the begining
2023 if (start_addr
== 0)
2026 mips16_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
, *this_cache
);
2029 /* gdbarch_sp_regnum contains the value and not the address. */
2030 trad_frame_set_value (cache
->saved_regs
,
2031 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
2034 return (*this_cache
);
2038 mips_insn16_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2039 struct frame_id
*this_id
)
2041 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2043 /* This marks the outermost frame. */
2044 if (info
->base
== 0)
2046 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
2049 static struct value
*
2050 mips_insn16_frame_prev_register (struct frame_info
*this_frame
,
2051 void **this_cache
, int regnum
)
2053 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2055 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
2059 mips_insn16_frame_sniffer (const struct frame_unwind
*self
,
2060 struct frame_info
*this_frame
, void **this_cache
)
2062 CORE_ADDR pc
= get_frame_pc (this_frame
);
2063 if (mips_pc_is_mips16 (pc
))
2068 static const struct frame_unwind mips_insn16_frame_unwind
=
2071 default_frame_unwind_stop_reason
,
2072 mips_insn16_frame_this_id
,
2073 mips_insn16_frame_prev_register
,
2075 mips_insn16_frame_sniffer
2079 mips_insn16_frame_base_address (struct frame_info
*this_frame
,
2082 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2087 static const struct frame_base mips_insn16_frame_base
=
2089 &mips_insn16_frame_unwind
,
2090 mips_insn16_frame_base_address
,
2091 mips_insn16_frame_base_address
,
2092 mips_insn16_frame_base_address
2095 static const struct frame_base
*
2096 mips_insn16_frame_base_sniffer (struct frame_info
*this_frame
)
2098 CORE_ADDR pc
= get_frame_pc (this_frame
);
2099 if (mips_pc_is_mips16 (pc
))
2100 return &mips_insn16_frame_base
;
2105 /* Mark all the registers as unset in the saved_regs array
2106 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
2109 reset_saved_regs (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
)
2111 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
2115 const int num_regs
= gdbarch_num_regs (gdbarch
);
2118 for (i
= 0; i
< num_regs
; i
++)
2120 this_cache
->saved_regs
[i
].addr
= -1;
2125 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
2126 the associated FRAME_CACHE if not null.
2127 Return the address of the first instruction past the prologue. */
2130 mips32_scan_prologue (struct gdbarch
*gdbarch
,
2131 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2132 struct frame_info
*this_frame
,
2133 struct mips_frame_cache
*this_cache
)
2136 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for
2140 int frame_reg
= MIPS_SP_REGNUM
;
2142 CORE_ADDR end_prologue_addr
= 0;
2143 int seen_sp_adjust
= 0;
2144 int load_immediate_bytes
= 0;
2145 int in_delay_slot
= 0;
2146 int regsize_is_64_bits
= (mips_abi_regsize (gdbarch
) == 8);
2148 /* Can be called when there's no process, and hence when there's no
2150 if (this_frame
!= NULL
)
2151 sp
= get_frame_register_signed (this_frame
,
2152 gdbarch_num_regs (gdbarch
)
2157 if (limit_pc
> start_pc
+ 200)
2158 limit_pc
= start_pc
+ 200;
2163 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN32_SIZE
)
2165 unsigned long inst
, high_word
, low_word
;
2168 /* Fetch the instruction. */
2169 inst
= (unsigned long) mips_fetch_instruction (gdbarch
, cur_pc
);
2171 /* Save some code by pre-extracting some useful fields. */
2172 high_word
= (inst
>> 16) & 0xffff;
2173 low_word
= inst
& 0xffff;
2174 reg
= high_word
& 0x1f;
2176 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
2177 || high_word
== 0x23bd /* addi $sp,$sp,-i */
2178 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
2180 if (low_word
& 0x8000) /* Negative stack adjustment? */
2181 frame_offset
+= 0x10000 - low_word
;
2183 /* Exit loop if a positive stack adjustment is found, which
2184 usually means that the stack cleanup code in the function
2185 epilogue is reached. */
2189 else if (((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
2190 && !regsize_is_64_bits
)
2192 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ low_word
);
2194 else if (((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
2195 && regsize_is_64_bits
)
2197 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
2198 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ low_word
);
2200 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
2202 /* Old gcc frame, r30 is virtual frame pointer. */
2203 if ((long) low_word
!= frame_offset
)
2204 frame_addr
= sp
+ low_word
;
2205 else if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
2207 unsigned alloca_adjust
;
2210 frame_addr
= get_frame_register_signed
2211 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
2213 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
2214 if (alloca_adjust
> 0)
2216 /* FP > SP + frame_size. This may be because of
2217 an alloca or somethings similar. Fix sp to
2218 "pre-alloca" value, and try again. */
2219 sp
+= alloca_adjust
;
2220 /* Need to reset the status of all registers. Otherwise,
2221 we will hit a guard that prevents the new address
2222 for each register to be recomputed during the second
2224 reset_saved_regs (gdbarch
, this_cache
);
2229 /* move $30,$sp. With different versions of gas this will be either
2230 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
2231 Accept any one of these. */
2232 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2234 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
2235 if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
2237 unsigned alloca_adjust
;
2240 frame_addr
= get_frame_register_signed
2241 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
2243 alloca_adjust
= (unsigned) (frame_addr
- sp
);
2244 if (alloca_adjust
> 0)
2246 /* FP > SP + frame_size. This may be because of
2247 an alloca or somethings similar. Fix sp to
2248 "pre-alloca" value, and try again. */
2250 /* Need to reset the status of all registers. Otherwise,
2251 we will hit a guard that prevents the new address
2252 for each register to be recomputed during the second
2254 reset_saved_regs (gdbarch
, this_cache
);
2259 else if ((high_word
& 0xFFE0) == 0xafc0 /* sw reg,offset($30) */
2260 && !regsize_is_64_bits
)
2262 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ low_word
);
2264 else if ((high_word
& 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
2265 || (high_word
& 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
2266 || (inst
& 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
2267 || high_word
== 0x3c1c /* lui $gp,n */
2268 || high_word
== 0x279c /* addiu $gp,$gp,n */
2269 || inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
2270 || inst
== 0x033ce021 /* addu $gp,$t9,$gp */
2273 /* These instructions are part of the prologue, but we don't
2274 need to do anything special to handle them. */
2276 /* The instructions below load $at or $t0 with an immediate
2277 value in preparation for a stack adjustment via
2278 subu $sp,$sp,[$at,$t0]. These instructions could also
2279 initialize a local variable, so we accept them only before
2280 a stack adjustment instruction was seen. */
2281 else if (!seen_sp_adjust
2282 && (high_word
== 0x3c01 /* lui $at,n */
2283 || high_word
== 0x3c08 /* lui $t0,n */
2284 || high_word
== 0x3421 /* ori $at,$at,n */
2285 || high_word
== 0x3508 /* ori $t0,$t0,n */
2286 || high_word
== 0x3401 /* ori $at,$zero,n */
2287 || high_word
== 0x3408 /* ori $t0,$zero,n */
2290 if (end_prologue_addr
== 0)
2291 load_immediate_bytes
+= MIPS_INSN32_SIZE
; /* FIXME! */
2295 /* This instruction is not an instruction typically found
2296 in a prologue, so we must have reached the end of the
2298 /* FIXME: brobecker/2004-10-10: Can't we just break out of this
2299 loop now? Why would we need to continue scanning the function
2301 if (end_prologue_addr
== 0)
2302 end_prologue_addr
= cur_pc
;
2304 /* Check for branches and jumps. For now, only jump to
2305 register are caught (i.e. returns). */
2306 if ((itype_op (inst
) & 0x07) == 0 && rtype_funct (inst
) == 8)
2310 /* If the previous instruction was a jump, we must have reached
2311 the end of the prologue by now. Stop scanning so that we do
2312 not go past the function return. */
2317 if (this_cache
!= NULL
)
2320 (get_frame_register_signed (this_frame
,
2321 gdbarch_num_regs (gdbarch
) + frame_reg
)
2323 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
2324 this assignment below, eventually. But it's still needed
2326 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2327 + mips_regnum (gdbarch
)->pc
]
2328 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2332 /* If we didn't reach the end of the prologue when scanning the function
2333 instructions, then set end_prologue_addr to the address of the
2334 instruction immediately after the last one we scanned. */
2335 /* brobecker/2004-10-10: I don't think this would ever happen, but
2336 we may as well be careful and do our best if we have a null
2337 end_prologue_addr. */
2338 if (end_prologue_addr
== 0)
2339 end_prologue_addr
= cur_pc
;
2341 /* In a frameless function, we might have incorrectly
2342 skipped some load immediate instructions. Undo the skipping
2343 if the load immediate was not followed by a stack adjustment. */
2344 if (load_immediate_bytes
&& !seen_sp_adjust
)
2345 end_prologue_addr
-= load_immediate_bytes
;
2347 return end_prologue_addr
;
2350 /* Heuristic unwinder for procedures using 32-bit instructions (covers
2351 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
2352 instructions (a.k.a. MIPS16) are handled by the mips_insn16
2355 static struct mips_frame_cache
*
2356 mips_insn32_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2358 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2359 struct mips_frame_cache
*cache
;
2361 if ((*this_cache
) != NULL
)
2362 return (*this_cache
);
2364 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2365 (*this_cache
) = cache
;
2366 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2368 /* Analyze the function prologue. */
2370 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2371 CORE_ADDR start_addr
;
2373 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2374 if (start_addr
== 0)
2375 start_addr
= heuristic_proc_start (gdbarch
, pc
);
2376 /* We can't analyze the prologue if we couldn't find the begining
2378 if (start_addr
== 0)
2381 mips32_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
, *this_cache
);
2384 /* gdbarch_sp_regnum contains the value and not the address. */
2385 trad_frame_set_value (cache
->saved_regs
,
2386 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
2389 return (*this_cache
);
2393 mips_insn32_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2394 struct frame_id
*this_id
)
2396 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
2398 /* This marks the outermost frame. */
2399 if (info
->base
== 0)
2401 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
2404 static struct value
*
2405 mips_insn32_frame_prev_register (struct frame_info
*this_frame
,
2406 void **this_cache
, int regnum
)
2408 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
2410 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
2414 mips_insn32_frame_sniffer (const struct frame_unwind
*self
,
2415 struct frame_info
*this_frame
, void **this_cache
)
2417 CORE_ADDR pc
= get_frame_pc (this_frame
);
2418 if (! mips_pc_is_mips16 (pc
))
2423 static const struct frame_unwind mips_insn32_frame_unwind
=
2426 default_frame_unwind_stop_reason
,
2427 mips_insn32_frame_this_id
,
2428 mips_insn32_frame_prev_register
,
2430 mips_insn32_frame_sniffer
2434 mips_insn32_frame_base_address (struct frame_info
*this_frame
,
2437 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
2442 static const struct frame_base mips_insn32_frame_base
=
2444 &mips_insn32_frame_unwind
,
2445 mips_insn32_frame_base_address
,
2446 mips_insn32_frame_base_address
,
2447 mips_insn32_frame_base_address
2450 static const struct frame_base
*
2451 mips_insn32_frame_base_sniffer (struct frame_info
*this_frame
)
2453 CORE_ADDR pc
= get_frame_pc (this_frame
);
2454 if (! mips_pc_is_mips16 (pc
))
2455 return &mips_insn32_frame_base
;
2460 static struct trad_frame_cache
*
2461 mips_stub_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2464 CORE_ADDR start_addr
;
2465 CORE_ADDR stack_addr
;
2466 struct trad_frame_cache
*this_trad_cache
;
2467 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2468 int num_regs
= gdbarch_num_regs (gdbarch
);
2470 if ((*this_cache
) != NULL
)
2471 return (*this_cache
);
2472 this_trad_cache
= trad_frame_cache_zalloc (this_frame
);
2473 (*this_cache
) = this_trad_cache
;
2475 /* The return address is in the link register. */
2476 trad_frame_set_reg_realreg (this_trad_cache
,
2477 gdbarch_pc_regnum (gdbarch
),
2478 num_regs
+ MIPS_RA_REGNUM
);
2480 /* Frame ID, since it's a frameless / stackless function, no stack
2481 space is allocated and SP on entry is the current SP. */
2482 pc
= get_frame_pc (this_frame
);
2483 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2484 stack_addr
= get_frame_register_signed (this_frame
,
2485 num_regs
+ MIPS_SP_REGNUM
);
2486 trad_frame_set_id (this_trad_cache
, frame_id_build (stack_addr
, start_addr
));
2488 /* Assume that the frame's base is the same as the
2490 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
2492 return this_trad_cache
;
2496 mips_stub_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2497 struct frame_id
*this_id
)
2499 struct trad_frame_cache
*this_trad_cache
2500 = mips_stub_frame_cache (this_frame
, this_cache
);
2501 trad_frame_get_id (this_trad_cache
, this_id
);
2504 static struct value
*
2505 mips_stub_frame_prev_register (struct frame_info
*this_frame
,
2506 void **this_cache
, int regnum
)
2508 struct trad_frame_cache
*this_trad_cache
2509 = mips_stub_frame_cache (this_frame
, this_cache
);
2510 return trad_frame_get_register (this_trad_cache
, this_frame
, regnum
);
2514 mips_stub_frame_sniffer (const struct frame_unwind
*self
,
2515 struct frame_info
*this_frame
, void **this_cache
)
2518 struct obj_section
*s
;
2519 CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2520 struct minimal_symbol
*msym
;
2522 /* Use the stub unwinder for unreadable code. */
2523 if (target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
2526 if (in_plt_section (pc
, NULL
))
2529 /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */
2530 s
= find_pc_section (pc
);
2533 && strcmp (bfd_get_section_name (s
->objfile
->obfd
, s
->the_bfd_section
),
2534 ".MIPS.stubs") == 0)
2537 /* Calling a PIC function from a non-PIC function passes through a
2538 stub. The stub for foo is named ".pic.foo". */
2539 msym
= lookup_minimal_symbol_by_pc (pc
);
2541 && SYMBOL_LINKAGE_NAME (msym
) != NULL
2542 && strncmp (SYMBOL_LINKAGE_NAME (msym
), ".pic.", 5) == 0)
2548 static const struct frame_unwind mips_stub_frame_unwind
=
2551 default_frame_unwind_stop_reason
,
2552 mips_stub_frame_this_id
,
2553 mips_stub_frame_prev_register
,
2555 mips_stub_frame_sniffer
2559 mips_stub_frame_base_address (struct frame_info
*this_frame
,
2562 struct trad_frame_cache
*this_trad_cache
2563 = mips_stub_frame_cache (this_frame
, this_cache
);
2564 return trad_frame_get_this_base (this_trad_cache
);
2567 static const struct frame_base mips_stub_frame_base
=
2569 &mips_stub_frame_unwind
,
2570 mips_stub_frame_base_address
,
2571 mips_stub_frame_base_address
,
2572 mips_stub_frame_base_address
2575 static const struct frame_base
*
2576 mips_stub_frame_base_sniffer (struct frame_info
*this_frame
)
2578 if (mips_stub_frame_sniffer (&mips_stub_frame_unwind
, this_frame
, NULL
))
2579 return &mips_stub_frame_base
;
2584 /* mips_addr_bits_remove - remove useless address bits */
2587 mips_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2589 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2591 if (is_mips16_addr (addr
))
2592 addr
= unmake_mips16_addr (addr
);
2594 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
2595 /* This hack is a work-around for existing boards using PMON, the
2596 simulator, and any other 64-bit targets that doesn't have true
2597 64-bit addressing. On these targets, the upper 32 bits of
2598 addresses are ignored by the hardware. Thus, the PC or SP are
2599 likely to have been sign extended to all 1s by instruction
2600 sequences that load 32-bit addresses. For example, a typical
2601 piece of code that loads an address is this:
2603 lui $r2, <upper 16 bits>
2604 ori $r2, <lower 16 bits>
2606 But the lui sign-extends the value such that the upper 32 bits
2607 may be all 1s. The workaround is simply to mask off these
2608 bits. In the future, gcc may be changed to support true 64-bit
2609 addressing, and this masking will have to be disabled. */
2610 return addr
&= 0xffffffffUL
;
2615 /* Instructions used during single-stepping of atomic sequences. */
2616 #define LL_OPCODE 0x30
2617 #define LLD_OPCODE 0x34
2618 #define SC_OPCODE 0x38
2619 #define SCD_OPCODE 0x3c
2621 /* Checks for an atomic sequence of instructions beginning with a LL/LLD
2622 instruction and ending with a SC/SCD instruction. If such a sequence
2623 is found, attempt to step through it. A breakpoint is placed at the end of
2627 deal_with_atomic_sequence (struct gdbarch
*gdbarch
,
2628 struct address_space
*aspace
, CORE_ADDR pc
)
2630 CORE_ADDR breaks
[2] = {-1, -1};
2632 CORE_ADDR branch_bp
; /* Breakpoint at branch instruction's destination. */
2636 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
2637 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
2642 insn
= mips_fetch_instruction (gdbarch
, loc
);
2643 /* Assume all atomic sequences start with a ll/lld instruction. */
2644 if (itype_op (insn
) != LL_OPCODE
&& itype_op (insn
) != LLD_OPCODE
)
2647 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
2649 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
2652 loc
+= MIPS_INSN32_SIZE
;
2653 insn
= mips_fetch_instruction (gdbarch
, loc
);
2655 /* Assume that there is at most one branch in the atomic
2656 sequence. If a branch is found, put a breakpoint in its
2657 destination address. */
2658 switch (itype_op (insn
))
2660 case 0: /* SPECIAL */
2661 if (rtype_funct (insn
) >> 1 == 4) /* JR, JALR */
2662 return 0; /* fallback to the standard single-step code. */
2664 case 1: /* REGIMM */
2665 is_branch
= ((itype_rt (insn
) & 0xc) == 0 /* B{LT,GE}Z* */
2666 || ((itype_rt (insn
) & 0x1e) == 0
2667 && itype_rs (insn
) == 0)); /* BPOSGE* */
2671 return 0; /* fallback to the standard single-step code. */
2678 case 22: /* BLEZL */
2679 case 23: /* BGTTL */
2683 is_branch
= ((itype_rs (insn
) == 9 || itype_rs (insn
) == 10)
2684 && (itype_rt (insn
) & 0x2) == 0);
2685 if (is_branch
) /* BC1ANY2F, BC1ANY2T, BC1ANY4F, BC1ANY4T */
2690 is_branch
= (itype_rs (insn
) == 8); /* BCzF, BCzFL, BCzT, BCzTL */
2695 branch_bp
= loc
+ mips32_relative_offset (insn
) + 4;
2696 if (last_breakpoint
>= 1)
2697 return 0; /* More than one branch found, fallback to the
2698 standard single-step code. */
2699 breaks
[1] = branch_bp
;
2703 if (itype_op (insn
) == SC_OPCODE
|| itype_op (insn
) == SCD_OPCODE
)
2707 /* Assume that the atomic sequence ends with a sc/scd instruction. */
2708 if (itype_op (insn
) != SC_OPCODE
&& itype_op (insn
) != SCD_OPCODE
)
2711 loc
+= MIPS_INSN32_SIZE
;
2713 /* Insert a breakpoint right after the end of the atomic sequence. */
2716 /* Check for duplicated breakpoints. Check also for a breakpoint
2717 placed (branch instruction's destination) in the atomic sequence. */
2718 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
2719 last_breakpoint
= 0;
2721 /* Effectively inserts the breakpoints. */
2722 for (index
= 0; index
<= last_breakpoint
; index
++)
2723 insert_single_step_breakpoint (gdbarch
, aspace
, breaks
[index
]);
2728 /* mips_software_single_step() is called just before we want to resume
2729 the inferior, if we want to single-step it but there is no hardware
2730 or kernel single-step support (MIPS on GNU/Linux for example). We find
2731 the target of the coming instruction and breakpoint it. */
2734 mips_software_single_step (struct frame_info
*frame
)
2736 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2737 struct address_space
*aspace
= get_frame_address_space (frame
);
2738 CORE_ADDR pc
, next_pc
;
2740 pc
= get_frame_pc (frame
);
2741 if (deal_with_atomic_sequence (gdbarch
, aspace
, pc
))
2744 next_pc
= mips_next_pc (frame
, pc
);
2746 insert_single_step_breakpoint (gdbarch
, aspace
, next_pc
);
2750 /* Test whether the PC points to the return instruction at the
2751 end of a function. */
2754 mips_about_to_return (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2756 if (mips_pc_is_mips16 (pc
))
2757 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
2758 generates a "jr $ra"; other times it generates code to load
2759 the return address from the stack to an accessible register (such
2760 as $a3), then a "jr" using that register. This second case
2761 is almost impossible to distinguish from an indirect jump
2762 used for switch statements, so we don't even try. */
2763 return mips_fetch_instruction (gdbarch
, pc
) == 0xe820; /* jr $ra */
2765 return mips_fetch_instruction (gdbarch
, pc
) == 0x3e00008; /* jr $ra */
2769 /* This fencepost looks highly suspicious to me. Removing it also
2770 seems suspicious as it could affect remote debugging across serial
2774 heuristic_proc_start (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2780 struct inferior
*inf
;
2782 pc
= gdbarch_addr_bits_remove (gdbarch
, pc
);
2784 fence
= start_pc
- heuristic_fence_post
;
2788 if (heuristic_fence_post
== UINT_MAX
|| fence
< VM_MIN_ADDRESS
)
2789 fence
= VM_MIN_ADDRESS
;
2791 instlen
= mips_pc_is_mips16 (pc
) ? MIPS_INSN16_SIZE
: MIPS_INSN32_SIZE
;
2793 inf
= current_inferior ();
2795 /* Search back for previous return. */
2796 for (start_pc
-= instlen
;; start_pc
-= instlen
)
2797 if (start_pc
< fence
)
2799 /* It's not clear to me why we reach this point when
2800 stop_soon, but with this test, at least we
2801 don't print out warnings for every child forked (eg, on
2802 decstation). 22apr93 rich@cygnus.com. */
2803 if (inf
->control
.stop_soon
== NO_STOP_QUIETLY
)
2805 static int blurb_printed
= 0;
2807 warning (_("GDB can't find the start of the function at %s."),
2808 paddress (gdbarch
, pc
));
2812 /* This actually happens frequently in embedded
2813 development, when you first connect to a board
2814 and your stack pointer and pc are nowhere in
2815 particular. This message needs to give people
2816 in that situation enough information to
2817 determine that it's no big deal. */
2818 printf_filtered ("\n\
2819 GDB is unable to find the start of the function at %s\n\
2820 and thus can't determine the size of that function's stack frame.\n\
2821 This means that GDB may be unable to access that stack frame, or\n\
2822 the frames below it.\n\
2823 This problem is most likely caused by an invalid program counter or\n\
2825 However, if you think GDB should simply search farther back\n\
2826 from %s for code which looks like the beginning of a\n\
2827 function, you can increase the range of the search using the `set\n\
2828 heuristic-fence-post' command.\n",
2829 paddress (gdbarch
, pc
), paddress (gdbarch
, pc
));
2836 else if (mips_pc_is_mips16 (start_pc
))
2838 unsigned short inst
;
2840 /* On MIPS16, any one of the following is likely to be the
2841 start of a function:
2847 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'. */
2848 inst
= mips_fetch_instruction (gdbarch
, start_pc
);
2849 if ((inst
& 0xff80) == 0x6480) /* save */
2851 if (start_pc
- instlen
>= fence
)
2853 inst
= mips_fetch_instruction (gdbarch
, start_pc
- instlen
);
2854 if ((inst
& 0xf800) == 0xf000) /* extend */
2855 start_pc
-= instlen
;
2859 else if (((inst
& 0xf81f) == 0xe809
2860 && (inst
& 0x700) != 0x700) /* entry */
2861 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
2862 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
2863 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
2865 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2866 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2871 else if (mips_about_to_return (gdbarch
, start_pc
))
2873 /* Skip return and its delay slot. */
2874 start_pc
+= 2 * MIPS_INSN32_SIZE
;
2881 struct mips_objfile_private
2887 /* According to the current ABI, should the type be passed in a
2888 floating-point register (assuming that there is space)? When there
2889 is no FPU, FP are not even considered as possible candidates for
2890 FP registers and, consequently this returns false - forces FP
2891 arguments into integer registers. */
2894 fp_register_arg_p (struct gdbarch
*gdbarch
, enum type_code typecode
,
2895 struct type
*arg_type
)
2897 return ((typecode
== TYPE_CODE_FLT
2898 || (MIPS_EABI (gdbarch
)
2899 && (typecode
== TYPE_CODE_STRUCT
2900 || typecode
== TYPE_CODE_UNION
)
2901 && TYPE_NFIELDS (arg_type
) == 1
2902 && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type
, 0)))
2904 && MIPS_FPU_TYPE(gdbarch
) != MIPS_FPU_NONE
);
2907 /* On o32, argument passing in GPRs depends on the alignment of the type being
2908 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2911 mips_type_needs_double_align (struct type
*type
)
2913 enum type_code typecode
= TYPE_CODE (type
);
2915 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
2917 else if (typecode
== TYPE_CODE_STRUCT
)
2919 if (TYPE_NFIELDS (type
) < 1)
2921 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
2923 else if (typecode
== TYPE_CODE_UNION
)
2927 n
= TYPE_NFIELDS (type
);
2928 for (i
= 0; i
< n
; i
++)
2929 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
2936 /* Adjust the address downward (direction of stack growth) so that it
2937 is correctly aligned for a new stack frame. */
2939 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2941 return align_down (addr
, 16);
2945 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2946 struct regcache
*regcache
, CORE_ADDR bp_addr
,
2947 int nargs
, struct value
**args
, CORE_ADDR sp
,
2948 int struct_return
, CORE_ADDR struct_addr
)
2954 int stack_offset
= 0;
2955 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2956 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2957 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
2958 int regsize
= mips_abi_regsize (gdbarch
);
2960 /* For shared libraries, "t9" needs to point at the function
2962 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
2964 /* Set the return address register to point to the entry point of
2965 the program, where a breakpoint lies in wait. */
2966 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
2968 /* First ensure that the stack and structure return address (if any)
2969 are properly aligned. The stack has to be at least 64-bit
2970 aligned even on 32-bit machines, because doubles must be 64-bit
2971 aligned. For n32 and n64, stack frames need to be 128-bit
2972 aligned, so we round to this widest known alignment. */
2974 sp
= align_down (sp
, 16);
2975 struct_addr
= align_down (struct_addr
, 16);
2977 /* Now make space on the stack for the args. We allocate more
2978 than necessary for EABI, because the first few arguments are
2979 passed in registers, but that's OK. */
2980 for (argnum
= 0; argnum
< nargs
; argnum
++)
2981 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), regsize
);
2982 sp
-= align_up (len
, 16);
2985 fprintf_unfiltered (gdb_stdlog
,
2986 "mips_eabi_push_dummy_call: sp=%s allocated %ld\n",
2987 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
2989 /* Initialize the integer and float register pointers. */
2990 argreg
= MIPS_A0_REGNUM
;
2991 float_argreg
= mips_fpa0_regnum (gdbarch
);
2993 /* The struct_return pointer occupies the first parameter-passing reg. */
2997 fprintf_unfiltered (gdb_stdlog
,
2998 "mips_eabi_push_dummy_call: "
2999 "struct_return reg=%d %s\n",
3000 argreg
, paddress (gdbarch
, struct_addr
));
3001 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3004 /* Now load as many as possible of the first arguments into
3005 registers, and push the rest onto the stack. Loop thru args
3006 from first to last. */
3007 for (argnum
= 0; argnum
< nargs
; argnum
++)
3009 const gdb_byte
*val
;
3010 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
3011 struct value
*arg
= args
[argnum
];
3012 struct type
*arg_type
= check_typedef (value_type (arg
));
3013 int len
= TYPE_LENGTH (arg_type
);
3014 enum type_code typecode
= TYPE_CODE (arg_type
);
3017 fprintf_unfiltered (gdb_stdlog
,
3018 "mips_eabi_push_dummy_call: %d len=%d type=%d",
3019 argnum
+ 1, len
, (int) typecode
);
3021 /* Function pointer arguments to mips16 code need to be made into
3023 if (typecode
== TYPE_CODE_PTR
3024 && TYPE_CODE (TYPE_TARGET_TYPE (arg_type
)) == TYPE_CODE_FUNC
)
3026 CORE_ADDR addr
= extract_signed_integer (value_contents (arg
),
3028 if (mips_pc_is_mips16 (addr
))
3030 store_signed_integer (valbuf
, len
, byte_order
,
3031 make_mips16_addr (addr
));
3035 val
= value_contents (arg
);
3037 /* The EABI passes structures that do not fit in a register by
3039 else if (len
> regsize
3040 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
3042 store_unsigned_integer (valbuf
, regsize
, byte_order
,
3043 value_address (arg
));
3044 typecode
= TYPE_CODE_PTR
;
3048 fprintf_unfiltered (gdb_stdlog
, " push");
3051 val
= value_contents (arg
);
3053 /* 32-bit ABIs always start floating point arguments in an
3054 even-numbered floating point register. Round the FP register
3055 up before the check to see if there are any FP registers
3056 left. Non MIPS_EABI targets also pass the FP in the integer
3057 registers so also round up normal registers. */
3058 if (regsize
< 8 && fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3060 if ((float_argreg
& 1))
3064 /* Floating point arguments passed in registers have to be
3065 treated specially. On 32-bit architectures, doubles
3066 are passed in register pairs; the even register gets
3067 the low word, and the odd register gets the high word.
3068 On non-EABI processors, the first two floating point arguments are
3069 also copied to general registers, because MIPS16 functions
3070 don't use float registers for arguments. This duplication of
3071 arguments in general registers can't hurt non-MIPS16 functions
3072 because those registers are normally skipped. */
3073 /* MIPS_EABI squeezes a struct that contains a single floating
3074 point value into an FP register instead of pushing it onto the
3076 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
3077 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
3079 /* EABI32 will pass doubles in consecutive registers, even on
3080 64-bit cores. At one time, we used to check the size of
3081 `float_argreg' to determine whether or not to pass doubles
3082 in consecutive registers, but this is not sufficient for
3083 making the ABI determination. */
3084 if (len
== 8 && mips_abi (gdbarch
) == MIPS_ABI_EABI32
)
3086 int low_offset
= gdbarch_byte_order (gdbarch
)
3087 == BFD_ENDIAN_BIG
? 4 : 0;
3090 /* Write the low word of the double to the even register(s). */
3091 regval
= extract_signed_integer (val
+ low_offset
,
3094 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3095 float_argreg
, phex (regval
, 4));
3096 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
3098 /* Write the high word of the double to the odd register(s). */
3099 regval
= extract_signed_integer (val
+ 4 - low_offset
,
3102 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3103 float_argreg
, phex (regval
, 4));
3104 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
3108 /* This is a floating point value that fits entirely
3109 in a single register. */
3110 /* On 32 bit ABI's the float_argreg is further adjusted
3111 above to ensure that it is even register aligned. */
3112 LONGEST regval
= extract_signed_integer (val
, len
, byte_order
);
3114 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3115 float_argreg
, phex (regval
, len
));
3116 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
3121 /* Copy the argument to general registers or the stack in
3122 register-sized pieces. Large arguments are split between
3123 registers and stack. */
3124 /* Note: structs whose size is not a multiple of regsize
3125 are treated specially: Irix cc passes
3126 them in registers where gcc sometimes puts them on the
3127 stack. For maximum compatibility, we will put them in
3129 int odd_sized_struct
= (len
> regsize
&& len
% regsize
!= 0);
3131 /* Note: Floating-point values that didn't fit into an FP
3132 register are only written to memory. */
3135 /* Remember if the argument was written to the stack. */
3136 int stack_used_p
= 0;
3137 int partial_len
= (len
< regsize
? len
: regsize
);
3140 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3143 /* Write this portion of the argument to the stack. */
3144 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
3146 || fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3148 /* Should shorter than int integer values be
3149 promoted to int before being stored? */
3150 int longword_offset
= 0;
3153 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
3156 && (typecode
== TYPE_CODE_INT
3157 || typecode
== TYPE_CODE_PTR
3158 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3159 longword_offset
= regsize
- len
;
3160 else if ((typecode
== TYPE_CODE_STRUCT
3161 || typecode
== TYPE_CODE_UNION
)
3162 && TYPE_LENGTH (arg_type
) < regsize
)
3163 longword_offset
= regsize
- len
;
3168 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
3169 paddress (gdbarch
, stack_offset
));
3170 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
3171 paddress (gdbarch
, longword_offset
));
3174 addr
= sp
+ stack_offset
+ longword_offset
;
3179 fprintf_unfiltered (gdb_stdlog
, " @%s ",
3180 paddress (gdbarch
, addr
));
3181 for (i
= 0; i
< partial_len
; i
++)
3183 fprintf_unfiltered (gdb_stdlog
, "%02x",
3187 write_memory (addr
, val
, partial_len
);
3190 /* Note!!! This is NOT an else clause. Odd sized
3191 structs may go thru BOTH paths. Floating point
3192 arguments will not. */
3193 /* Write this portion of the argument to a general
3194 purpose register. */
3195 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
)
3196 && !fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3199 extract_signed_integer (val
, partial_len
, byte_order
);
3202 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3204 phex (regval
, regsize
));
3205 regcache_cooked_write_signed (regcache
, argreg
, regval
);
3212 /* Compute the offset into the stack at which we will
3213 copy the next parameter.
3215 In the new EABI (and the NABI32), the stack_offset
3216 only needs to be adjusted when it has been used. */
3219 stack_offset
+= align_up (partial_len
, regsize
);
3223 fprintf_unfiltered (gdb_stdlog
, "\n");
3226 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3228 /* Return adjusted stack pointer. */
3232 /* Determine the return value convention being used. */
3234 static enum return_value_convention
3235 mips_eabi_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
3236 struct type
*type
, struct regcache
*regcache
,
3237 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3239 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3240 int fp_return_type
= 0;
3241 int offset
, regnum
, xfer
;
3243 if (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
3244 return RETURN_VALUE_STRUCT_CONVENTION
;
3246 /* Floating point type? */
3247 if (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3249 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
3251 /* Structs with a single field of float type
3252 are returned in a floating point register. */
3253 if ((TYPE_CODE (type
) == TYPE_CODE_STRUCT
3254 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3255 && TYPE_NFIELDS (type
) == 1)
3257 struct type
*fieldtype
= TYPE_FIELD_TYPE (type
, 0);
3259 if (TYPE_CODE (check_typedef (fieldtype
)) == TYPE_CODE_FLT
)
3266 /* A floating-point value belongs in the least significant part
3269 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3270 regnum
= mips_regnum (gdbarch
)->fp0
;
3274 /* An integer value goes in V0/V1. */
3276 fprintf_unfiltered (gdb_stderr
, "Return scalar in $v0\n");
3277 regnum
= MIPS_V0_REGNUM
;
3280 offset
< TYPE_LENGTH (type
);
3281 offset
+= mips_abi_regsize (gdbarch
), regnum
++)
3283 xfer
= mips_abi_regsize (gdbarch
);
3284 if (offset
+ xfer
> TYPE_LENGTH (type
))
3285 xfer
= TYPE_LENGTH (type
) - offset
;
3286 mips_xfer_register (gdbarch
, regcache
,
3287 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
3288 gdbarch_byte_order (gdbarch
), readbuf
, writebuf
,
3292 return RETURN_VALUE_REGISTER_CONVENTION
;
3296 /* N32/N64 ABI stuff. */
3298 /* Search for a naturally aligned double at OFFSET inside a struct
3299 ARG_TYPE. The N32 / N64 ABIs pass these in floating point
3303 mips_n32n64_fp_arg_chunk_p (struct gdbarch
*gdbarch
, struct type
*arg_type
,
3308 if (TYPE_CODE (arg_type
) != TYPE_CODE_STRUCT
)
3311 if (MIPS_FPU_TYPE (gdbarch
) != MIPS_FPU_DOUBLE
)
3314 if (TYPE_LENGTH (arg_type
) < offset
+ MIPS64_REGSIZE
)
3317 for (i
= 0; i
< TYPE_NFIELDS (arg_type
); i
++)
3320 struct type
*field_type
;
3322 /* We're only looking at normal fields. */
3323 if (field_is_static (&TYPE_FIELD (arg_type
, i
))
3324 || (TYPE_FIELD_BITPOS (arg_type
, i
) % 8) != 0)
3327 /* If we have gone past the offset, there is no double to pass. */
3328 pos
= TYPE_FIELD_BITPOS (arg_type
, i
) / 8;
3332 field_type
= check_typedef (TYPE_FIELD_TYPE (arg_type
, i
));
3334 /* If this field is entirely before the requested offset, go
3335 on to the next one. */
3336 if (pos
+ TYPE_LENGTH (field_type
) <= offset
)
3339 /* If this is our special aligned double, we can stop. */
3340 if (TYPE_CODE (field_type
) == TYPE_CODE_FLT
3341 && TYPE_LENGTH (field_type
) == MIPS64_REGSIZE
)
3344 /* This field starts at or before the requested offset, and
3345 overlaps it. If it is a structure, recurse inwards. */
3346 return mips_n32n64_fp_arg_chunk_p (gdbarch
, field_type
, offset
- pos
);
3353 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3354 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3355 int nargs
, struct value
**args
, CORE_ADDR sp
,
3356 int struct_return
, CORE_ADDR struct_addr
)
3362 int stack_offset
= 0;
3363 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3364 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3365 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3367 /* For shared libraries, "t9" needs to point at the function
3369 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3371 /* Set the return address register to point to the entry point of
3372 the program, where a breakpoint lies in wait. */
3373 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3375 /* First ensure that the stack and structure return address (if any)
3376 are properly aligned. The stack has to be at least 64-bit
3377 aligned even on 32-bit machines, because doubles must be 64-bit
3378 aligned. For n32 and n64, stack frames need to be 128-bit
3379 aligned, so we round to this widest known alignment. */
3381 sp
= align_down (sp
, 16);
3382 struct_addr
= align_down (struct_addr
, 16);
3384 /* Now make space on the stack for the args. */
3385 for (argnum
= 0; argnum
< nargs
; argnum
++)
3386 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), MIPS64_REGSIZE
);
3387 sp
-= align_up (len
, 16);
3390 fprintf_unfiltered (gdb_stdlog
,
3391 "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n",
3392 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
3394 /* Initialize the integer and float register pointers. */
3395 argreg
= MIPS_A0_REGNUM
;
3396 float_argreg
= mips_fpa0_regnum (gdbarch
);
3398 /* The struct_return pointer occupies the first parameter-passing reg. */
3402 fprintf_unfiltered (gdb_stdlog
,
3403 "mips_n32n64_push_dummy_call: "
3404 "struct_return reg=%d %s\n",
3405 argreg
, paddress (gdbarch
, struct_addr
));
3406 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3409 /* Now load as many as possible of the first arguments into
3410 registers, and push the rest onto the stack. Loop thru args
3411 from first to last. */
3412 for (argnum
= 0; argnum
< nargs
; argnum
++)
3414 const gdb_byte
*val
;
3415 struct value
*arg
= args
[argnum
];
3416 struct type
*arg_type
= check_typedef (value_type (arg
));
3417 int len
= TYPE_LENGTH (arg_type
);
3418 enum type_code typecode
= TYPE_CODE (arg_type
);
3421 fprintf_unfiltered (gdb_stdlog
,
3422 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
3423 argnum
+ 1, len
, (int) typecode
);
3425 val
= value_contents (arg
);
3427 /* A 128-bit long double value requires an even-odd pair of
3428 floating-point registers. */
3430 && fp_register_arg_p (gdbarch
, typecode
, arg_type
)
3431 && (float_argreg
& 1))
3437 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
3438 && argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
3440 /* This is a floating point value that fits entirely
3441 in a single register or a pair of registers. */
3442 int reglen
= (len
<= MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
3443 LONGEST regval
= extract_unsigned_integer (val
, reglen
, byte_order
);
3445 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3446 float_argreg
, phex (regval
, reglen
));
3447 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
3450 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3451 argreg
, phex (regval
, reglen
));
3452 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3457 regval
= extract_unsigned_integer (val
+ reglen
,
3458 reglen
, byte_order
);
3460 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3461 float_argreg
, phex (regval
, reglen
));
3462 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
3465 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3466 argreg
, phex (regval
, reglen
));
3467 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3474 /* Copy the argument to general registers or the stack in
3475 register-sized pieces. Large arguments are split between
3476 registers and stack. */
3477 /* For N32/N64, structs, unions, or other composite types are
3478 treated as a sequence of doublewords, and are passed in integer
3479 or floating point registers as though they were simple scalar
3480 parameters to the extent that they fit, with any excess on the
3481 stack packed according to the normal memory layout of the
3483 The caller does not reserve space for the register arguments;
3484 the callee is responsible for reserving it if required. */
3485 /* Note: Floating-point values that didn't fit into an FP
3486 register are only written to memory. */
3489 /* Remember if the argument was written to the stack. */
3490 int stack_used_p
= 0;
3491 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
3494 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3497 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3498 gdb_assert (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
));
3500 /* Write this portion of the argument to the stack. */
3501 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
))
3503 /* Should shorter than int integer values be
3504 promoted to int before being stored? */
3505 int longword_offset
= 0;
3508 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
3510 if ((typecode
== TYPE_CODE_INT
3511 || typecode
== TYPE_CODE_PTR
)
3513 longword_offset
= MIPS64_REGSIZE
- len
;
3518 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
3519 paddress (gdbarch
, stack_offset
));
3520 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
3521 paddress (gdbarch
, longword_offset
));
3524 addr
= sp
+ stack_offset
+ longword_offset
;
3529 fprintf_unfiltered (gdb_stdlog
, " @%s ",
3530 paddress (gdbarch
, addr
));
3531 for (i
= 0; i
< partial_len
; i
++)
3533 fprintf_unfiltered (gdb_stdlog
, "%02x",
3537 write_memory (addr
, val
, partial_len
);
3540 /* Note!!! This is NOT an else clause. Odd sized
3541 structs may go thru BOTH paths. */
3542 /* Write this portion of the argument to a general
3543 purpose register. */
3544 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
3548 /* Sign extend pointers, 32-bit integers and signed
3549 16-bit and 8-bit integers; everything else is taken
3552 if ((partial_len
== 4
3553 && (typecode
== TYPE_CODE_PTR
3554 || typecode
== TYPE_CODE_INT
))
3556 && typecode
== TYPE_CODE_INT
3557 && !TYPE_UNSIGNED (arg_type
)))
3558 regval
= extract_signed_integer (val
, partial_len
,
3561 regval
= extract_unsigned_integer (val
, partial_len
,
3564 /* A non-floating-point argument being passed in a
3565 general register. If a struct or union, and if
3566 the remaining length is smaller than the register
3567 size, we have to adjust the register value on
3570 It does not seem to be necessary to do the
3571 same for integral types. */
3573 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
3574 && partial_len
< MIPS64_REGSIZE
3575 && (typecode
== TYPE_CODE_STRUCT
3576 || typecode
== TYPE_CODE_UNION
))
3577 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
3581 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3583 phex (regval
, MIPS64_REGSIZE
));
3584 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3586 if (mips_n32n64_fp_arg_chunk_p (gdbarch
, arg_type
,
3587 TYPE_LENGTH (arg_type
) - len
))
3590 fprintf_filtered (gdb_stdlog
, " - fpreg=%d val=%s",
3592 phex (regval
, MIPS64_REGSIZE
));
3593 regcache_cooked_write_unsigned (regcache
, float_argreg
,
3604 /* Compute the offset into the stack at which we will
3605 copy the next parameter.
3607 In N32 (N64?), the stack_offset only needs to be
3608 adjusted when it has been used. */
3611 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
3615 fprintf_unfiltered (gdb_stdlog
, "\n");
3618 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3620 /* Return adjusted stack pointer. */
3624 static enum return_value_convention
3625 mips_n32n64_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
3626 struct type
*type
, struct regcache
*regcache
,
3627 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3629 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3631 /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004
3633 Function results are returned in $2 (and $3 if needed), or $f0 (and $f2
3634 if needed), as appropriate for the type. Composite results (struct,
3635 union, or array) are returned in $2/$f0 and $3/$f2 according to the
3638 * A struct with only one or two floating point fields is returned in $f0
3639 (and $f2 if necessary). This is a generalization of the Fortran COMPLEX
3642 * Any other composite results of at most 128 bits are returned in
3643 $2 (first 64 bits) and $3 (remainder, if necessary).
3645 * Larger composite results are handled by converting the function to a
3646 procedure with an implicit first parameter, which is a pointer to an area
3647 reserved by the caller to receive the result. [The o32-bit ABI requires
3648 that all composite results be handled by conversion to implicit first
3649 parameters. The MIPS/SGI Fortran implementation has always made a
3650 specific exception to return COMPLEX results in the floating point
3653 if (TYPE_LENGTH (type
) > 2 * MIPS64_REGSIZE
)
3654 return RETURN_VALUE_STRUCT_CONVENTION
;
3655 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3656 && TYPE_LENGTH (type
) == 16
3657 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3659 /* A 128-bit floating-point value fills both $f0 and $f2. The
3660 two registers are used in the same as memory order, so the
3661 eight bytes with the lower memory address are in $f0. */
3663 fprintf_unfiltered (gdb_stderr
, "Return float in $f0 and $f2\n");
3664 mips_xfer_register (gdbarch
, regcache
,
3665 gdbarch_num_regs (gdbarch
)
3666 + mips_regnum (gdbarch
)->fp0
,
3667 8, gdbarch_byte_order (gdbarch
),
3668 readbuf
, writebuf
, 0);
3669 mips_xfer_register (gdbarch
, regcache
,
3670 gdbarch_num_regs (gdbarch
)
3671 + mips_regnum (gdbarch
)->fp0
+ 2,
3672 8, gdbarch_byte_order (gdbarch
),
3673 readbuf
? readbuf
+ 8 : readbuf
,
3674 writebuf
? writebuf
+ 8 : writebuf
, 0);
3675 return RETURN_VALUE_REGISTER_CONVENTION
;
3677 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3678 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3680 /* A single or double floating-point value that fits in FP0. */
3682 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3683 mips_xfer_register (gdbarch
, regcache
,
3684 gdbarch_num_regs (gdbarch
)
3685 + mips_regnum (gdbarch
)->fp0
,
3687 gdbarch_byte_order (gdbarch
),
3688 readbuf
, writebuf
, 0);
3689 return RETURN_VALUE_REGISTER_CONVENTION
;
3691 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3692 && TYPE_NFIELDS (type
) <= 2
3693 && TYPE_NFIELDS (type
) >= 1
3694 && ((TYPE_NFIELDS (type
) == 1
3695 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
3697 || (TYPE_NFIELDS (type
) == 2
3698 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
3700 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 1)))
3701 == TYPE_CODE_FLT
))))
3703 /* A struct that contains one or two floats. Each value is part
3704 in the least significant part of their floating point
3705 register (or GPR, for soft float). */
3708 for (field
= 0, regnum
= (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
3709 ? mips_regnum (gdbarch
)->fp0
3711 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3713 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3716 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3718 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)) == 16)
3720 /* A 16-byte long double field goes in two consecutive
3722 mips_xfer_register (gdbarch
, regcache
,
3723 gdbarch_num_regs (gdbarch
) + regnum
,
3725 gdbarch_byte_order (gdbarch
),
3726 readbuf
, writebuf
, offset
);
3727 mips_xfer_register (gdbarch
, regcache
,
3728 gdbarch_num_regs (gdbarch
) + regnum
+ 1,
3730 gdbarch_byte_order (gdbarch
),
3731 readbuf
, writebuf
, offset
+ 8);
3734 mips_xfer_register (gdbarch
, regcache
,
3735 gdbarch_num_regs (gdbarch
) + regnum
,
3736 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3737 gdbarch_byte_order (gdbarch
),
3738 readbuf
, writebuf
, offset
);
3740 return RETURN_VALUE_REGISTER_CONVENTION
;
3742 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3743 || TYPE_CODE (type
) == TYPE_CODE_UNION
3744 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
3746 /* A composite type. Extract the left justified value,
3747 regardless of the byte order. I.e. DO NOT USE
3751 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3752 offset
< TYPE_LENGTH (type
);
3753 offset
+= register_size (gdbarch
, regnum
), regnum
++)
3755 int xfer
= register_size (gdbarch
, regnum
);
3756 if (offset
+ xfer
> TYPE_LENGTH (type
))
3757 xfer
= TYPE_LENGTH (type
) - offset
;
3759 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3760 offset
, xfer
, regnum
);
3761 mips_xfer_register (gdbarch
, regcache
,
3762 gdbarch_num_regs (gdbarch
) + regnum
,
3763 xfer
, BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
,
3766 return RETURN_VALUE_REGISTER_CONVENTION
;
3770 /* A scalar extract each part but least-significant-byte
3774 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3775 offset
< TYPE_LENGTH (type
);
3776 offset
+= register_size (gdbarch
, regnum
), regnum
++)
3778 int xfer
= register_size (gdbarch
, regnum
);
3779 if (offset
+ xfer
> TYPE_LENGTH (type
))
3780 xfer
= TYPE_LENGTH (type
) - offset
;
3782 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3783 offset
, xfer
, regnum
);
3784 mips_xfer_register (gdbarch
, regcache
,
3785 gdbarch_num_regs (gdbarch
) + regnum
,
3786 xfer
, gdbarch_byte_order (gdbarch
),
3787 readbuf
, writebuf
, offset
);
3789 return RETURN_VALUE_REGISTER_CONVENTION
;
3793 /* O32 ABI stuff. */
3796 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3797 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3798 int nargs
, struct value
**args
, CORE_ADDR sp
,
3799 int struct_return
, CORE_ADDR struct_addr
)
3805 int stack_offset
= 0;
3806 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3807 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3808 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3810 /* For shared libraries, "t9" needs to point at the function
3812 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3814 /* Set the return address register to point to the entry point of
3815 the program, where a breakpoint lies in wait. */
3816 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3818 /* First ensure that the stack and structure return address (if any)
3819 are properly aligned. The stack has to be at least 64-bit
3820 aligned even on 32-bit machines, because doubles must be 64-bit
3821 aligned. For n32 and n64, stack frames need to be 128-bit
3822 aligned, so we round to this widest known alignment. */
3824 sp
= align_down (sp
, 16);
3825 struct_addr
= align_down (struct_addr
, 16);
3827 /* Now make space on the stack for the args. */
3828 for (argnum
= 0; argnum
< nargs
; argnum
++)
3830 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
3831 int arglen
= TYPE_LENGTH (arg_type
);
3833 /* Align to double-word if necessary. */
3834 if (mips_type_needs_double_align (arg_type
))
3835 len
= align_up (len
, MIPS32_REGSIZE
* 2);
3836 /* Allocate space on the stack. */
3837 len
+= align_up (arglen
, MIPS32_REGSIZE
);
3839 sp
-= align_up (len
, 16);
3842 fprintf_unfiltered (gdb_stdlog
,
3843 "mips_o32_push_dummy_call: sp=%s allocated %ld\n",
3844 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
3846 /* Initialize the integer and float register pointers. */
3847 argreg
= MIPS_A0_REGNUM
;
3848 float_argreg
= mips_fpa0_regnum (gdbarch
);
3850 /* The struct_return pointer occupies the first parameter-passing reg. */
3854 fprintf_unfiltered (gdb_stdlog
,
3855 "mips_o32_push_dummy_call: "
3856 "struct_return reg=%d %s\n",
3857 argreg
, paddress (gdbarch
, struct_addr
));
3858 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3859 stack_offset
+= MIPS32_REGSIZE
;
3862 /* Now load as many as possible of the first arguments into
3863 registers, and push the rest onto the stack. Loop thru args
3864 from first to last. */
3865 for (argnum
= 0; argnum
< nargs
; argnum
++)
3867 const gdb_byte
*val
;
3868 struct value
*arg
= args
[argnum
];
3869 struct type
*arg_type
= check_typedef (value_type (arg
));
3870 int len
= TYPE_LENGTH (arg_type
);
3871 enum type_code typecode
= TYPE_CODE (arg_type
);
3874 fprintf_unfiltered (gdb_stdlog
,
3875 "mips_o32_push_dummy_call: %d len=%d type=%d",
3876 argnum
+ 1, len
, (int) typecode
);
3878 val
= value_contents (arg
);
3880 /* 32-bit ABIs always start floating point arguments in an
3881 even-numbered floating point register. Round the FP register
3882 up before the check to see if there are any FP registers
3883 left. O32/O64 targets also pass the FP in the integer
3884 registers so also round up normal registers. */
3885 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3887 if ((float_argreg
& 1))
3891 /* Floating point arguments passed in registers have to be
3892 treated specially. On 32-bit architectures, doubles
3893 are passed in register pairs; the even register gets
3894 the low word, and the odd register gets the high word.
3895 On O32/O64, the first two floating point arguments are
3896 also copied to general registers, because MIPS16 functions
3897 don't use float registers for arguments. This duplication of
3898 arguments in general registers can't hurt non-MIPS16 functions
3899 because those registers are normally skipped. */
3901 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
3902 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
3904 if (register_size (gdbarch
, float_argreg
) < 8 && len
== 8)
3906 int low_offset
= gdbarch_byte_order (gdbarch
)
3907 == BFD_ENDIAN_BIG
? 4 : 0;
3908 unsigned long regval
;
3910 /* Write the low word of the double to the even register(s). */
3911 regval
= extract_unsigned_integer (val
+ low_offset
,
3914 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3915 float_argreg
, phex (regval
, 4));
3916 regcache_cooked_write_unsigned (regcache
,
3917 float_argreg
++, regval
);
3919 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3920 argreg
, phex (regval
, 4));
3921 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3923 /* Write the high word of the double to the odd register(s). */
3924 regval
= extract_unsigned_integer (val
+ 4 - low_offset
,
3927 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3928 float_argreg
, phex (regval
, 4));
3929 regcache_cooked_write_unsigned (regcache
,
3930 float_argreg
++, regval
);
3933 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3934 argreg
, phex (regval
, 4));
3935 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3939 /* This is a floating point value that fits entirely
3940 in a single register. */
3941 /* On 32 bit ABI's the float_argreg is further adjusted
3942 above to ensure that it is even register aligned. */
3943 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
3945 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3946 float_argreg
, phex (regval
, len
));
3947 regcache_cooked_write_unsigned (regcache
,
3948 float_argreg
++, regval
);
3949 /* Although two FP registers are reserved for each
3950 argument, only one corresponding integer register is
3953 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3954 argreg
, phex (regval
, len
));
3955 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3957 /* Reserve space for the FP register. */
3958 stack_offset
+= align_up (len
, MIPS32_REGSIZE
);
3962 /* Copy the argument to general registers or the stack in
3963 register-sized pieces. Large arguments are split between
3964 registers and stack. */
3965 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
3966 are treated specially: Irix cc passes
3967 them in registers where gcc sometimes puts them on the
3968 stack. For maximum compatibility, we will put them in
3970 int odd_sized_struct
= (len
> MIPS32_REGSIZE
3971 && len
% MIPS32_REGSIZE
!= 0);
3972 /* Structures should be aligned to eight bytes (even arg registers)
3973 on MIPS_ABI_O32, if their first member has double precision. */
3974 if (mips_type_needs_double_align (arg_type
))
3979 stack_offset
+= MIPS32_REGSIZE
;
3984 /* Remember if the argument was written to the stack. */
3985 int stack_used_p
= 0;
3986 int partial_len
= (len
< MIPS32_REGSIZE
? len
: MIPS32_REGSIZE
);
3989 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3992 /* Write this portion of the argument to the stack. */
3993 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
3994 || odd_sized_struct
)
3996 /* Should shorter than int integer values be
3997 promoted to int before being stored? */
3998 int longword_offset
= 0;
4004 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
4005 paddress (gdbarch
, stack_offset
));
4006 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
4007 paddress (gdbarch
, longword_offset
));
4010 addr
= sp
+ stack_offset
+ longword_offset
;
4015 fprintf_unfiltered (gdb_stdlog
, " @%s ",
4016 paddress (gdbarch
, addr
));
4017 for (i
= 0; i
< partial_len
; i
++)
4019 fprintf_unfiltered (gdb_stdlog
, "%02x",
4023 write_memory (addr
, val
, partial_len
);
4026 /* Note!!! This is NOT an else clause. Odd sized
4027 structs may go thru BOTH paths. */
4028 /* Write this portion of the argument to a general
4029 purpose register. */
4030 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
4032 LONGEST regval
= extract_signed_integer (val
, partial_len
,
4034 /* Value may need to be sign extended, because
4035 mips_isa_regsize() != mips_abi_regsize(). */
4037 /* A non-floating-point argument being passed in a
4038 general register. If a struct or union, and if
4039 the remaining length is smaller than the register
4040 size, we have to adjust the register value on
4043 It does not seem to be necessary to do the
4044 same for integral types.
4046 Also don't do this adjustment on O64 binaries.
4048 cagney/2001-07-23: gdb/179: Also, GCC, when
4049 outputting LE O32 with sizeof (struct) <
4050 mips_abi_regsize(), generates a left shift
4051 as part of storing the argument in a register
4052 (the left shift isn't generated when
4053 sizeof (struct) >= mips_abi_regsize()). Since
4054 it is quite possible that this is GCC
4055 contradicting the LE/O32 ABI, GDB has not been
4056 adjusted to accommodate this. Either someone
4057 needs to demonstrate that the LE/O32 ABI
4058 specifies such a left shift OR this new ABI gets
4059 identified as such and GDB gets tweaked
4062 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
4063 && partial_len
< MIPS32_REGSIZE
4064 && (typecode
== TYPE_CODE_STRUCT
4065 || typecode
== TYPE_CODE_UNION
))
4066 regval
<<= ((MIPS32_REGSIZE
- partial_len
)
4070 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4072 phex (regval
, MIPS32_REGSIZE
));
4073 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4076 /* Prevent subsequent floating point arguments from
4077 being passed in floating point registers. */
4078 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
4084 /* Compute the offset into the stack at which we will
4085 copy the next parameter.
4087 In older ABIs, the caller reserved space for
4088 registers that contained arguments. This was loosely
4089 refered to as their "home". Consequently, space is
4090 always allocated. */
4092 stack_offset
+= align_up (partial_len
, MIPS32_REGSIZE
);
4096 fprintf_unfiltered (gdb_stdlog
, "\n");
4099 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4101 /* Return adjusted stack pointer. */
4105 static enum return_value_convention
4106 mips_o32_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
4107 struct type
*type
, struct regcache
*regcache
,
4108 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4110 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4112 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4113 || TYPE_CODE (type
) == TYPE_CODE_UNION
4114 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
4115 return RETURN_VALUE_STRUCT_CONVENTION
;
4116 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4117 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4119 /* A single-precision floating-point value. It fits in the
4120 least significant part of FP0. */
4122 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4123 mips_xfer_register (gdbarch
, regcache
,
4124 gdbarch_num_regs (gdbarch
)
4125 + mips_regnum (gdbarch
)->fp0
,
4127 gdbarch_byte_order (gdbarch
),
4128 readbuf
, writebuf
, 0);
4129 return RETURN_VALUE_REGISTER_CONVENTION
;
4131 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4132 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4134 /* A double-precision floating-point value. The most
4135 significant part goes in FP1, and the least significant in
4138 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
4139 switch (gdbarch_byte_order (gdbarch
))
4141 case BFD_ENDIAN_LITTLE
:
4142 mips_xfer_register (gdbarch
, regcache
,
4143 gdbarch_num_regs (gdbarch
)
4144 + mips_regnum (gdbarch
)->fp0
+
4145 0, 4, gdbarch_byte_order (gdbarch
),
4146 readbuf
, writebuf
, 0);
4147 mips_xfer_register (gdbarch
, regcache
,
4148 gdbarch_num_regs (gdbarch
)
4149 + mips_regnum (gdbarch
)->fp0
+ 1,
4150 4, gdbarch_byte_order (gdbarch
),
4151 readbuf
, writebuf
, 4);
4153 case BFD_ENDIAN_BIG
:
4154 mips_xfer_register (gdbarch
, regcache
,
4155 gdbarch_num_regs (gdbarch
)
4156 + mips_regnum (gdbarch
)->fp0
+ 1,
4157 4, gdbarch_byte_order (gdbarch
),
4158 readbuf
, writebuf
, 0);
4159 mips_xfer_register (gdbarch
, regcache
,
4160 gdbarch_num_regs (gdbarch
)
4161 + mips_regnum (gdbarch
)->fp0
+ 0,
4162 4, gdbarch_byte_order (gdbarch
),
4163 readbuf
, writebuf
, 4);
4166 internal_error (__FILE__
, __LINE__
, _("bad switch"));
4168 return RETURN_VALUE_REGISTER_CONVENTION
;
4171 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4172 && TYPE_NFIELDS (type
) <= 2
4173 && TYPE_NFIELDS (type
) >= 1
4174 && ((TYPE_NFIELDS (type
) == 1
4175 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4177 || (TYPE_NFIELDS (type
) == 2
4178 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4180 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
4182 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4184 /* A struct that contains one or two floats. Each value is part
4185 in the least significant part of their floating point
4187 gdb_byte reg
[MAX_REGISTER_SIZE
];
4190 for (field
= 0, regnum
= mips_regnum (gdbarch
)->fp0
;
4191 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
4193 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
4196 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
4198 mips_xfer_register (gdbarch
, regcache
,
4199 gdbarch_num_regs (gdbarch
) + regnum
,
4200 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
4201 gdbarch_byte_order (gdbarch
),
4202 readbuf
, writebuf
, offset
);
4204 return RETURN_VALUE_REGISTER_CONVENTION
;
4208 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4209 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
4211 /* A structure or union. Extract the left justified value,
4212 regardless of the byte order. I.e. DO NOT USE
4216 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
4217 offset
< TYPE_LENGTH (type
);
4218 offset
+= register_size (gdbarch
, regnum
), regnum
++)
4220 int xfer
= register_size (gdbarch
, regnum
);
4221 if (offset
+ xfer
> TYPE_LENGTH (type
))
4222 xfer
= TYPE_LENGTH (type
) - offset
;
4224 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
4225 offset
, xfer
, regnum
);
4226 mips_xfer_register (gdbarch
, regcache
,
4227 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
4228 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
4230 return RETURN_VALUE_REGISTER_CONVENTION
;
4235 /* A scalar extract each part but least-significant-byte
4236 justified. o32 thinks registers are 4 byte, regardless of
4240 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
4241 offset
< TYPE_LENGTH (type
);
4242 offset
+= MIPS32_REGSIZE
, regnum
++)
4244 int xfer
= MIPS32_REGSIZE
;
4245 if (offset
+ xfer
> TYPE_LENGTH (type
))
4246 xfer
= TYPE_LENGTH (type
) - offset
;
4248 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4249 offset
, xfer
, regnum
);
4250 mips_xfer_register (gdbarch
, regcache
,
4251 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
4252 gdbarch_byte_order (gdbarch
),
4253 readbuf
, writebuf
, offset
);
4255 return RETURN_VALUE_REGISTER_CONVENTION
;
4259 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
4263 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4264 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4266 struct value
**args
, CORE_ADDR sp
,
4267 int struct_return
, CORE_ADDR struct_addr
)
4273 int stack_offset
= 0;
4274 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4275 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4276 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4278 /* For shared libraries, "t9" needs to point at the function
4280 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4282 /* Set the return address register to point to the entry point of
4283 the program, where a breakpoint lies in wait. */
4284 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4286 /* First ensure that the stack and structure return address (if any)
4287 are properly aligned. The stack has to be at least 64-bit
4288 aligned even on 32-bit machines, because doubles must be 64-bit
4289 aligned. For n32 and n64, stack frames need to be 128-bit
4290 aligned, so we round to this widest known alignment. */
4292 sp
= align_down (sp
, 16);
4293 struct_addr
= align_down (struct_addr
, 16);
4295 /* Now make space on the stack for the args. */
4296 for (argnum
= 0; argnum
< nargs
; argnum
++)
4298 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
4299 int arglen
= TYPE_LENGTH (arg_type
);
4301 /* Allocate space on the stack. */
4302 len
+= align_up (arglen
, MIPS64_REGSIZE
);
4304 sp
-= align_up (len
, 16);
4307 fprintf_unfiltered (gdb_stdlog
,
4308 "mips_o64_push_dummy_call: sp=%s allocated %ld\n",
4309 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
4311 /* Initialize the integer and float register pointers. */
4312 argreg
= MIPS_A0_REGNUM
;
4313 float_argreg
= mips_fpa0_regnum (gdbarch
);
4315 /* The struct_return pointer occupies the first parameter-passing reg. */
4319 fprintf_unfiltered (gdb_stdlog
,
4320 "mips_o64_push_dummy_call: "
4321 "struct_return reg=%d %s\n",
4322 argreg
, paddress (gdbarch
, struct_addr
));
4323 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4324 stack_offset
+= MIPS64_REGSIZE
;
4327 /* Now load as many as possible of the first arguments into
4328 registers, and push the rest onto the stack. Loop thru args
4329 from first to last. */
4330 for (argnum
= 0; argnum
< nargs
; argnum
++)
4332 const gdb_byte
*val
;
4333 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
4334 struct value
*arg
= args
[argnum
];
4335 struct type
*arg_type
= check_typedef (value_type (arg
));
4336 int len
= TYPE_LENGTH (arg_type
);
4337 enum type_code typecode
= TYPE_CODE (arg_type
);
4340 fprintf_unfiltered (gdb_stdlog
,
4341 "mips_o64_push_dummy_call: %d len=%d type=%d",
4342 argnum
+ 1, len
, (int) typecode
);
4344 val
= value_contents (arg
);
4346 /* Function pointer arguments to mips16 code need to be made into
4348 if (typecode
== TYPE_CODE_PTR
4349 && TYPE_CODE (TYPE_TARGET_TYPE (arg_type
)) == TYPE_CODE_FUNC
)
4351 CORE_ADDR addr
= extract_signed_integer (value_contents (arg
),
4353 if (mips_pc_is_mips16 (addr
))
4355 store_signed_integer (valbuf
, len
, byte_order
,
4356 make_mips16_addr (addr
));
4361 /* Floating point arguments passed in registers have to be
4362 treated specially. On 32-bit architectures, doubles
4363 are passed in register pairs; the even register gets
4364 the low word, and the odd register gets the high word.
4365 On O32/O64, the first two floating point arguments are
4366 also copied to general registers, because MIPS16 functions
4367 don't use float registers for arguments. This duplication of
4368 arguments in general registers can't hurt non-MIPS16 functions
4369 because those registers are normally skipped. */
4371 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4372 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
4374 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
4376 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4377 float_argreg
, phex (regval
, len
));
4378 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
4380 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4381 argreg
, phex (regval
, len
));
4382 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4384 /* Reserve space for the FP register. */
4385 stack_offset
+= align_up (len
, MIPS64_REGSIZE
);
4389 /* Copy the argument to general registers or the stack in
4390 register-sized pieces. Large arguments are split between
4391 registers and stack. */
4392 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
4393 are treated specially: Irix cc passes them in registers
4394 where gcc sometimes puts them on the stack. For maximum
4395 compatibility, we will put them in both places. */
4396 int odd_sized_struct
= (len
> MIPS64_REGSIZE
4397 && len
% MIPS64_REGSIZE
!= 0);
4400 /* Remember if the argument was written to the stack. */
4401 int stack_used_p
= 0;
4402 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
4405 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4408 /* Write this portion of the argument to the stack. */
4409 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
4410 || odd_sized_struct
)
4412 /* Should shorter than int integer values be
4413 promoted to int before being stored? */
4414 int longword_offset
= 0;
4417 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4419 if ((typecode
== TYPE_CODE_INT
4420 || typecode
== TYPE_CODE_PTR
4421 || typecode
== TYPE_CODE_FLT
)
4423 longword_offset
= MIPS64_REGSIZE
- len
;
4428 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
4429 paddress (gdbarch
, stack_offset
));
4430 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
4431 paddress (gdbarch
, longword_offset
));
4434 addr
= sp
+ stack_offset
+ longword_offset
;
4439 fprintf_unfiltered (gdb_stdlog
, " @%s ",
4440 paddress (gdbarch
, addr
));
4441 for (i
= 0; i
< partial_len
; i
++)
4443 fprintf_unfiltered (gdb_stdlog
, "%02x",
4447 write_memory (addr
, val
, partial_len
);
4450 /* Note!!! This is NOT an else clause. Odd sized
4451 structs may go thru BOTH paths. */
4452 /* Write this portion of the argument to a general
4453 purpose register. */
4454 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
4456 LONGEST regval
= extract_signed_integer (val
, partial_len
,
4458 /* Value may need to be sign extended, because
4459 mips_isa_regsize() != mips_abi_regsize(). */
4461 /* A non-floating-point argument being passed in a
4462 general register. If a struct or union, and if
4463 the remaining length is smaller than the register
4464 size, we have to adjust the register value on
4467 It does not seem to be necessary to do the
4468 same for integral types. */
4470 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
4471 && partial_len
< MIPS64_REGSIZE
4472 && (typecode
== TYPE_CODE_STRUCT
4473 || typecode
== TYPE_CODE_UNION
))
4474 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
4478 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4480 phex (regval
, MIPS64_REGSIZE
));
4481 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4484 /* Prevent subsequent floating point arguments from
4485 being passed in floating point registers. */
4486 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
4492 /* Compute the offset into the stack at which we will
4493 copy the next parameter.
4495 In older ABIs, the caller reserved space for
4496 registers that contained arguments. This was loosely
4497 refered to as their "home". Consequently, space is
4498 always allocated. */
4500 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
4504 fprintf_unfiltered (gdb_stdlog
, "\n");
4507 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4509 /* Return adjusted stack pointer. */
4513 static enum return_value_convention
4514 mips_o64_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
4515 struct type
*type
, struct regcache
*regcache
,
4516 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4518 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4520 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4521 || TYPE_CODE (type
) == TYPE_CODE_UNION
4522 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
4523 return RETURN_VALUE_STRUCT_CONVENTION
;
4524 else if (fp_register_arg_p (gdbarch
, TYPE_CODE (type
), type
))
4526 /* A floating-point value. It fits in the least significant
4529 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4530 mips_xfer_register (gdbarch
, regcache
,
4531 gdbarch_num_regs (gdbarch
)
4532 + mips_regnum (gdbarch
)->fp0
,
4534 gdbarch_byte_order (gdbarch
),
4535 readbuf
, writebuf
, 0);
4536 return RETURN_VALUE_REGISTER_CONVENTION
;
4540 /* A scalar extract each part but least-significant-byte
4544 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
4545 offset
< TYPE_LENGTH (type
);
4546 offset
+= MIPS64_REGSIZE
, regnum
++)
4548 int xfer
= MIPS64_REGSIZE
;
4549 if (offset
+ xfer
> TYPE_LENGTH (type
))
4550 xfer
= TYPE_LENGTH (type
) - offset
;
4552 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4553 offset
, xfer
, regnum
);
4554 mips_xfer_register (gdbarch
, regcache
,
4555 gdbarch_num_regs (gdbarch
) + regnum
,
4556 xfer
, gdbarch_byte_order (gdbarch
),
4557 readbuf
, writebuf
, offset
);
4559 return RETURN_VALUE_REGISTER_CONVENTION
;
4563 /* Floating point register management.
4565 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
4566 64bit operations, these early MIPS cpus treat fp register pairs
4567 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
4568 registers and offer a compatibility mode that emulates the MIPS2 fp
4569 model. When operating in MIPS2 fp compat mode, later cpu's split
4570 double precision floats into two 32-bit chunks and store them in
4571 consecutive fp regs. To display 64-bit floats stored in this
4572 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
4573 Throw in user-configurable endianness and you have a real mess.
4575 The way this works is:
4576 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
4577 double-precision value will be split across two logical registers.
4578 The lower-numbered logical register will hold the low-order bits,
4579 regardless of the processor's endianness.
4580 - If we are on a 64-bit processor, and we are looking for a
4581 single-precision value, it will be in the low ordered bits
4582 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
4583 save slot in memory.
4584 - If we are in 64-bit mode, everything is straightforward.
4586 Note that this code only deals with "live" registers at the top of the
4587 stack. We will attempt to deal with saved registers later, when
4588 the raw/cooked register interface is in place. (We need a general
4589 interface that can deal with dynamic saved register sizes -- fp
4590 regs could be 32 bits wide in one frame and 64 on the frame above
4593 /* Copy a 32-bit single-precision value from the current frame
4594 into rare_buffer. */
4597 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
4598 gdb_byte
*rare_buffer
)
4600 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4601 int raw_size
= register_size (gdbarch
, regno
);
4602 gdb_byte
*raw_buffer
= alloca (raw_size
);
4604 if (!frame_register_read (frame
, regno
, raw_buffer
))
4605 error (_("can't read register %d (%s)"),
4606 regno
, gdbarch_register_name (gdbarch
, regno
));
4609 /* We have a 64-bit value for this register. Find the low-order
4613 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4618 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
4622 memcpy (rare_buffer
, raw_buffer
, 4);
4626 /* Copy a 64-bit double-precision value from the current frame into
4627 rare_buffer. This may include getting half of it from the next
4631 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
4632 gdb_byte
*rare_buffer
)
4634 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4635 int raw_size
= register_size (gdbarch
, regno
);
4637 if (raw_size
== 8 && !mips2_fp_compat (frame
))
4639 /* We have a 64-bit value for this register, and we should use
4641 if (!frame_register_read (frame
, regno
, rare_buffer
))
4642 error (_("can't read register %d (%s)"),
4643 regno
, gdbarch_register_name (gdbarch
, regno
));
4647 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
4649 if ((rawnum
- mips_regnum (gdbarch
)->fp0
) & 1)
4650 internal_error (__FILE__
, __LINE__
,
4651 _("mips_read_fp_register_double: bad access to "
4652 "odd-numbered FP register"));
4654 /* mips_read_fp_register_single will find the correct 32 bits from
4656 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4658 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
4659 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
4663 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
4664 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
4670 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
4672 { /* Do values for FP (float) regs. */
4673 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4674 gdb_byte
*raw_buffer
;
4675 double doub
, flt1
; /* Doubles extracted from raw hex data. */
4678 raw_buffer
= alloca (2 * register_size (gdbarch
,
4679 mips_regnum (gdbarch
)->fp0
));
4681 fprintf_filtered (file
, "%s:", gdbarch_register_name (gdbarch
, regnum
));
4682 fprintf_filtered (file
, "%*s",
4683 4 - (int) strlen (gdbarch_register_name (gdbarch
, regnum
)),
4686 if (register_size (gdbarch
, regnum
) == 4 || mips2_fp_compat (frame
))
4688 struct value_print_options opts
;
4690 /* 4-byte registers: Print hex and floating. Also print even
4691 numbered registers as doubles. */
4692 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4693 flt1
= unpack_double (builtin_type (gdbarch
)->builtin_float
,
4696 get_formatted_print_options (&opts
, 'x');
4697 print_scalar_formatted (raw_buffer
,
4698 builtin_type (gdbarch
)->builtin_uint32
,
4701 fprintf_filtered (file
, " flt: ");
4703 fprintf_filtered (file
, " <invalid float> ");
4705 fprintf_filtered (file
, "%-17.9g", flt1
);
4707 if ((regnum
- gdbarch_num_regs (gdbarch
)) % 2 == 0)
4709 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4710 doub
= unpack_double (builtin_type (gdbarch
)->builtin_double
,
4713 fprintf_filtered (file
, " dbl: ");
4715 fprintf_filtered (file
, "<invalid double>");
4717 fprintf_filtered (file
, "%-24.17g", doub
);
4722 struct value_print_options opts
;
4724 /* Eight byte registers: print each one as hex, float and double. */
4725 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4726 flt1
= unpack_double (builtin_type (gdbarch
)->builtin_float
,
4729 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4730 doub
= unpack_double (builtin_type (gdbarch
)->builtin_double
,
4733 get_formatted_print_options (&opts
, 'x');
4734 print_scalar_formatted (raw_buffer
,
4735 builtin_type (gdbarch
)->builtin_uint64
,
4738 fprintf_filtered (file
, " flt: ");
4740 fprintf_filtered (file
, "<invalid float>");
4742 fprintf_filtered (file
, "%-17.9g", flt1
);
4744 fprintf_filtered (file
, " dbl: ");
4746 fprintf_filtered (file
, "<invalid double>");
4748 fprintf_filtered (file
, "%-24.17g", doub
);
4753 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
4756 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4758 struct value_print_options opts
;
4761 if (TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4763 mips_print_fp_register (file
, frame
, regnum
);
4767 val
= get_frame_register_value (frame
, regnum
);
4768 if (value_optimized_out (val
))
4770 fprintf_filtered (file
, "%s: [Invalid]",
4771 gdbarch_register_name (gdbarch
, regnum
));
4775 fputs_filtered (gdbarch_register_name (gdbarch
, regnum
), file
);
4777 /* The problem with printing numeric register names (r26, etc.) is that
4778 the user can't use them on input. Probably the best solution is to
4779 fix it so that either the numeric or the funky (a2, etc.) names
4780 are accepted on input. */
4781 if (regnum
< MIPS_NUMREGS
)
4782 fprintf_filtered (file
, "(r%d): ", regnum
);
4784 fprintf_filtered (file
, ": ");
4786 get_formatted_print_options (&opts
, 'x');
4787 val_print_scalar_formatted (value_type (val
),
4788 value_contents_for_printing (val
),
4789 value_embedded_offset (val
),
4794 /* Replacement for generic do_registers_info.
4795 Print regs in pretty columns. */
4798 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4801 fprintf_filtered (file
, " ");
4802 mips_print_fp_register (file
, frame
, regnum
);
4803 fprintf_filtered (file
, "\n");
4808 /* Print a row's worth of GP (int) registers, with name labels above. */
4811 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4814 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4815 /* Do values for GP (int) regs. */
4816 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
4817 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols
4822 /* For GP registers, we print a separate row of names above the vals. */
4823 for (col
= 0, regnum
= start_regnum
;
4824 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
4825 + gdbarch_num_pseudo_regs (gdbarch
);
4828 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
4829 continue; /* unused register */
4830 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4832 break; /* End the row: reached FP register. */
4833 /* Large registers are handled separately. */
4834 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
4837 break; /* End the row before this register. */
4839 /* Print this register on a row by itself. */
4840 mips_print_register (file
, frame
, regnum
);
4841 fprintf_filtered (file
, "\n");
4845 fprintf_filtered (file
, " ");
4846 fprintf_filtered (file
,
4847 mips_abi_regsize (gdbarch
) == 8 ? "%17s" : "%9s",
4848 gdbarch_register_name (gdbarch
, regnum
));
4855 /* Print the R0 to R31 names. */
4856 if ((start_regnum
% gdbarch_num_regs (gdbarch
)) < MIPS_NUMREGS
)
4857 fprintf_filtered (file
, "\n R%-4d",
4858 start_regnum
% gdbarch_num_regs (gdbarch
));
4860 fprintf_filtered (file
, "\n ");
4862 /* Now print the values in hex, 4 or 8 to the row. */
4863 for (col
= 0, regnum
= start_regnum
;
4864 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
4865 + gdbarch_num_pseudo_regs (gdbarch
);
4868 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
4869 continue; /* unused register */
4870 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4872 break; /* End row: reached FP register. */
4873 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
4874 break; /* End row: large register. */
4876 /* OK: get the data in raw format. */
4877 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4878 error (_("can't read register %d (%s)"),
4879 regnum
, gdbarch_register_name (gdbarch
, regnum
));
4880 /* pad small registers */
4882 byte
< (mips_abi_regsize (gdbarch
)
4883 - register_size (gdbarch
, regnum
)); byte
++)
4884 printf_filtered (" ");
4885 /* Now print the register value in hex, endian order. */
4886 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4888 register_size (gdbarch
, regnum
) - register_size (gdbarch
, regnum
);
4889 byte
< register_size (gdbarch
, regnum
); byte
++)
4890 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
4892 for (byte
= register_size (gdbarch
, regnum
) - 1;
4894 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
4895 fprintf_filtered (file
, " ");
4898 if (col
> 0) /* ie. if we actually printed anything... */
4899 fprintf_filtered (file
, "\n");
4904 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command. */
4907 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
4908 struct frame_info
*frame
, int regnum
, int all
)
4910 if (regnum
!= -1) /* Do one specified register. */
4912 gdb_assert (regnum
>= gdbarch_num_regs (gdbarch
));
4913 if (*(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
4914 error (_("Not a valid register for the current processor type"));
4916 mips_print_register (file
, frame
, regnum
);
4917 fprintf_filtered (file
, "\n");
4920 /* Do all (or most) registers. */
4922 regnum
= gdbarch_num_regs (gdbarch
);
4923 while (regnum
< gdbarch_num_regs (gdbarch
)
4924 + gdbarch_num_pseudo_regs (gdbarch
))
4926 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4929 if (all
) /* True for "INFO ALL-REGISTERS" command. */
4930 regnum
= print_fp_register_row (file
, frame
, regnum
);
4932 regnum
+= MIPS_NUMREGS
; /* Skip floating point regs. */
4935 regnum
= print_gp_register_row (file
, frame
, regnum
);
4940 /* Is this a branch with a delay slot? */
4943 is_delayed (unsigned long insn
)
4946 for (i
= 0; i
< NUMOPCODES
; ++i
)
4947 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
4948 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
4950 return (i
< NUMOPCODES
4951 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
4952 | INSN_COND_BRANCH_DELAY
4953 | INSN_COND_BRANCH_LIKELY
)));
4957 mips_single_step_through_delay (struct gdbarch
*gdbarch
,
4958 struct frame_info
*frame
)
4960 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4961 CORE_ADDR pc
= get_frame_pc (frame
);
4962 gdb_byte buf
[MIPS_INSN32_SIZE
];
4964 /* There is no branch delay slot on MIPS16. */
4965 if (mips_pc_is_mips16 (pc
))
4968 if (!breakpoint_here_p (get_frame_address_space (frame
), pc
+ 4))
4971 if (!safe_frame_unwind_memory (frame
, pc
, buf
, sizeof buf
))
4972 /* If error reading memory, guess that it is not a delayed
4975 return is_delayed (extract_unsigned_integer (buf
, sizeof buf
, byte_order
));
4978 /* To skip prologues, I use this predicate. Returns either PC itself
4979 if the code at PC does not look like a function prologue; otherwise
4980 returns an address that (if we're lucky) follows the prologue. If
4981 LENIENT, then we must skip everything which is involved in setting
4982 up the frame (it's OK to skip more, just so long as we don't skip
4983 anything which might clobber the registers which are being saved.
4984 We must skip more in the case where part of the prologue is in the
4985 delay slot of a non-prologue instruction). */
4988 mips_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4991 CORE_ADDR func_addr
;
4993 /* See if we can determine the end of the prologue via the symbol table.
4994 If so, then return either PC, or the PC after the prologue, whichever
4996 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
4998 CORE_ADDR post_prologue_pc
4999 = skip_prologue_using_sal (gdbarch
, func_addr
);
5000 if (post_prologue_pc
!= 0)
5001 return max (pc
, post_prologue_pc
);
5004 /* Can't determine prologue from the symbol table, need to examine
5007 /* Find an upper limit on the function prologue using the debug
5008 information. If the debug information could not be used to provide
5009 that bound, then use an arbitrary large number as the upper bound. */
5010 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
5012 limit_pc
= pc
+ 100; /* Magic. */
5014 if (mips_pc_is_mips16 (pc
))
5015 return mips16_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
5017 return mips32_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
5020 /* Check whether the PC is in a function epilogue (32-bit version).
5021 This is a helper function for mips_in_function_epilogue_p. */
5023 mips32_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
5025 CORE_ADDR func_addr
= 0, func_end
= 0;
5027 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
5029 /* The MIPS epilogue is max. 12 bytes long. */
5030 CORE_ADDR addr
= func_end
- 12;
5032 if (addr
< func_addr
+ 4)
5033 addr
= func_addr
+ 4;
5037 for (; pc
< func_end
; pc
+= MIPS_INSN32_SIZE
)
5039 unsigned long high_word
;
5042 inst
= mips_fetch_instruction (gdbarch
, pc
);
5043 high_word
= (inst
>> 16) & 0xffff;
5045 if (high_word
!= 0x27bd /* addiu $sp,$sp,offset */
5046 && high_word
!= 0x67bd /* daddiu $sp,$sp,offset */
5047 && inst
!= 0x03e00008 /* jr $ra */
5048 && inst
!= 0x00000000) /* nop */
5058 /* Check whether the PC is in a function epilogue (16-bit version).
5059 This is a helper function for mips_in_function_epilogue_p. */
5061 mips16_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
5063 CORE_ADDR func_addr
= 0, func_end
= 0;
5065 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
5067 /* The MIPS epilogue is max. 12 bytes long. */
5068 CORE_ADDR addr
= func_end
- 12;
5070 if (addr
< func_addr
+ 4)
5071 addr
= func_addr
+ 4;
5075 for (; pc
< func_end
; pc
+= MIPS_INSN16_SIZE
)
5077 unsigned short inst
;
5079 inst
= mips_fetch_instruction (gdbarch
, pc
);
5081 if ((inst
& 0xf800) == 0xf000) /* extend */
5084 if (inst
!= 0x6300 /* addiu $sp,offset */
5085 && inst
!= 0xfb00 /* daddiu $sp,$sp,offset */
5086 && inst
!= 0xe820 /* jr $ra */
5087 && inst
!= 0xe8a0 /* jrc $ra */
5088 && inst
!= 0x6500) /* nop */
5098 /* The epilogue is defined here as the area at the end of a function,
5099 after an instruction which destroys the function's stack frame. */
5101 mips_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
5103 if (mips_pc_is_mips16 (pc
))
5104 return mips16_in_function_epilogue_p (gdbarch
, pc
);
5106 return mips32_in_function_epilogue_p (gdbarch
, pc
);
5109 /* Root of all "set mips "/"show mips " commands. This will eventually be
5110 used for all MIPS-specific commands. */
5113 show_mips_command (char *args
, int from_tty
)
5115 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
5119 set_mips_command (char *args
, int from_tty
)
5122 ("\"set mips\" must be followed by an appropriate subcommand.\n");
5123 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
5126 /* Commands to show/set the MIPS FPU type. */
5129 show_mipsfpu_command (char *args
, int from_tty
)
5133 if (gdbarch_bfd_arch_info (target_gdbarch
)->arch
!= bfd_arch_mips
)
5136 ("The MIPS floating-point coprocessor is unknown "
5137 "because the current architecture is not MIPS.\n");
5141 switch (MIPS_FPU_TYPE (target_gdbarch
))
5143 case MIPS_FPU_SINGLE
:
5144 fpu
= "single-precision";
5146 case MIPS_FPU_DOUBLE
:
5147 fpu
= "double-precision";
5150 fpu
= "absent (none)";
5153 internal_error (__FILE__
, __LINE__
, _("bad switch"));
5155 if (mips_fpu_type_auto
)
5156 printf_unfiltered ("The MIPS floating-point coprocessor "
5157 "is set automatically (currently %s)\n",
5161 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
5166 set_mipsfpu_command (char *args
, int from_tty
)
5168 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", "
5169 "\"single\",\"none\" or \"auto\".\n");
5170 show_mipsfpu_command (args
, from_tty
);
5174 set_mipsfpu_single_command (char *args
, int from_tty
)
5176 struct gdbarch_info info
;
5177 gdbarch_info_init (&info
);
5178 mips_fpu_type
= MIPS_FPU_SINGLE
;
5179 mips_fpu_type_auto
= 0;
5180 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5181 instead of relying on globals. Doing that would let generic code
5182 handle the search for this specific architecture. */
5183 if (!gdbarch_update_p (info
))
5184 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
5188 set_mipsfpu_double_command (char *args
, int from_tty
)
5190 struct gdbarch_info info
;
5191 gdbarch_info_init (&info
);
5192 mips_fpu_type
= MIPS_FPU_DOUBLE
;
5193 mips_fpu_type_auto
= 0;
5194 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5195 instead of relying on globals. Doing that would let generic code
5196 handle the search for this specific architecture. */
5197 if (!gdbarch_update_p (info
))
5198 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
5202 set_mipsfpu_none_command (char *args
, int from_tty
)
5204 struct gdbarch_info info
;
5205 gdbarch_info_init (&info
);
5206 mips_fpu_type
= MIPS_FPU_NONE
;
5207 mips_fpu_type_auto
= 0;
5208 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5209 instead of relying on globals. Doing that would let generic code
5210 handle the search for this specific architecture. */
5211 if (!gdbarch_update_p (info
))
5212 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
5216 set_mipsfpu_auto_command (char *args
, int from_tty
)
5218 mips_fpu_type_auto
= 1;
5221 /* Attempt to identify the particular processor model by reading the
5222 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
5223 the relevant processor still exists (it dates back to '94) and
5224 secondly this is not the way to do this. The processor type should
5225 be set by forcing an architecture change. */
5228 deprecated_mips_set_processor_regs_hack (void)
5230 struct regcache
*regcache
= get_current_regcache ();
5231 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
5232 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5235 regcache_cooked_read_unsigned (regcache
, MIPS_PRID_REGNUM
, &prid
);
5236 if ((prid
& ~0xf) == 0x700)
5237 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
5240 /* Just like reinit_frame_cache, but with the right arguments to be
5241 callable as an sfunc. */
5244 reinit_frame_cache_sfunc (char *args
, int from_tty
,
5245 struct cmd_list_element
*c
)
5247 reinit_frame_cache ();
5251 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
5253 /* FIXME: cagney/2003-06-26: Is this even necessary? The
5254 disassembler needs to be able to locally determine the ISA, and
5255 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
5257 if (mips_pc_is_mips16 (memaddr
))
5258 info
->mach
= bfd_mach_mips16
;
5260 /* Round down the instruction address to the appropriate boundary. */
5261 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
5263 /* Set the disassembler options. */
5264 if (!info
->disassembler_options
)
5265 /* This string is not recognized explicitly by the disassembler,
5266 but it tells the disassembler to not try to guess the ABI from
5267 the bfd elf headers, such that, if the user overrides the ABI
5268 of a program linked as NewABI, the disassembly will follow the
5269 register naming conventions specified by the user. */
5270 info
->disassembler_options
= "gpr-names=32";
5272 /* Call the appropriate disassembler based on the target endian-ness. */
5273 if (info
->endian
== BFD_ENDIAN_BIG
)
5274 return print_insn_big_mips (memaddr
, info
);
5276 return print_insn_little_mips (memaddr
, info
);
5280 gdb_print_insn_mips_n32 (bfd_vma memaddr
, struct disassemble_info
*info
)
5282 /* Set up the disassembler info, so that we get the right
5283 register names from libopcodes. */
5284 info
->disassembler_options
= "gpr-names=n32";
5285 info
->flavour
= bfd_target_elf_flavour
;
5287 return gdb_print_insn_mips (memaddr
, info
);
5291 gdb_print_insn_mips_n64 (bfd_vma memaddr
, struct disassemble_info
*info
)
5293 /* Set up the disassembler info, so that we get the right
5294 register names from libopcodes. */
5295 info
->disassembler_options
= "gpr-names=64";
5296 info
->flavour
= bfd_target_elf_flavour
;
5298 return gdb_print_insn_mips (memaddr
, info
);
5301 /* This function implements gdbarch_breakpoint_from_pc. It uses the
5302 program counter value to determine whether a 16- or 32-bit breakpoint
5303 should be used. It returns a pointer to a string of bytes that encode a
5304 breakpoint instruction, stores the length of the string to *lenptr, and
5305 adjusts pc (if necessary) to point to the actual memory location where
5306 the breakpoint should be inserted. */
5308 static const gdb_byte
*
5309 mips_breakpoint_from_pc (struct gdbarch
*gdbarch
,
5310 CORE_ADDR
*pcptr
, int *lenptr
)
5312 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
5314 if (mips_pc_is_mips16 (*pcptr
))
5316 static gdb_byte mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
5317 *pcptr
= unmake_mips16_addr (*pcptr
);
5318 *lenptr
= sizeof (mips16_big_breakpoint
);
5319 return mips16_big_breakpoint
;
5323 /* The IDT board uses an unusual breakpoint value, and
5324 sometimes gets confused when it sees the usual MIPS
5325 breakpoint instruction. */
5326 static gdb_byte big_breakpoint
[] = { 0, 0x5, 0, 0xd };
5327 static gdb_byte pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
5328 static gdb_byte idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
5329 /* Likewise, IRIX appears to expect a different breakpoint,
5330 although this is not apparent until you try to use pthreads. */
5331 static gdb_byte irix_big_breakpoint
[] = { 0, 0, 0, 0xd };
5333 *lenptr
= sizeof (big_breakpoint
);
5335 if (strcmp (target_shortname
, "mips") == 0)
5336 return idt_big_breakpoint
;
5337 else if (strcmp (target_shortname
, "ddb") == 0
5338 || strcmp (target_shortname
, "pmon") == 0
5339 || strcmp (target_shortname
, "lsi") == 0)
5340 return pmon_big_breakpoint
;
5341 else if (gdbarch_osabi (gdbarch
) == GDB_OSABI_IRIX
)
5342 return irix_big_breakpoint
;
5344 return big_breakpoint
;
5349 if (mips_pc_is_mips16 (*pcptr
))
5351 static gdb_byte mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
5352 *pcptr
= unmake_mips16_addr (*pcptr
);
5353 *lenptr
= sizeof (mips16_little_breakpoint
);
5354 return mips16_little_breakpoint
;
5358 static gdb_byte little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
5359 static gdb_byte pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
5360 static gdb_byte idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
5362 *lenptr
= sizeof (little_breakpoint
);
5364 if (strcmp (target_shortname
, "mips") == 0)
5365 return idt_little_breakpoint
;
5366 else if (strcmp (target_shortname
, "ddb") == 0
5367 || strcmp (target_shortname
, "pmon") == 0
5368 || strcmp (target_shortname
, "lsi") == 0)
5369 return pmon_little_breakpoint
;
5371 return little_breakpoint
;
5376 /* Return non-zero if the ADDR instruction has a branch delay slot
5377 (i.e. it is a jump or branch instruction). This function is based
5378 on mips32_next_pc. */
5381 mips32_instruction_has_delay_slot (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
5383 gdb_byte buf
[MIPS_INSN32_SIZE
];
5390 status
= target_read_memory (addr
, buf
, MIPS_INSN32_SIZE
);
5394 inst
= mips_fetch_instruction (gdbarch
, addr
);
5395 op
= itype_op (inst
);
5396 if ((inst
& 0xe0000000) != 0)
5398 rs
= itype_rs (inst
);
5399 rt
= itype_rt (inst
);
5400 return (op
>> 2 == 5 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
5401 || op
== 29 /* JALX: bits 011101 */
5404 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
5405 || (rs
== 9 && (rt
& 0x2) == 0)
5406 /* BC1ANY2F, BC1ANY2T: bits 010001 01001 */
5407 || (rs
== 10 && (rt
& 0x2) == 0))));
5408 /* BC1ANY4F, BC1ANY4T: bits 010001 01010 */
5411 switch (op
& 0x07) /* extract bits 28,27,26 */
5413 case 0: /* SPECIAL */
5414 op
= rtype_funct (inst
);
5415 return (op
== 8 /* JR */
5416 || op
== 9); /* JALR */
5417 break; /* end SPECIAL */
5418 case 1: /* REGIMM */
5419 rs
= itype_rs (inst
);
5420 rt
= itype_rt (inst
); /* branch condition */
5421 return ((rt
& 0xc) == 0
5422 /* BLTZ, BLTZL, BGEZ, BGEZL: bits 000xx */
5423 /* BLTZAL, BLTZALL, BGEZAL, BGEZALL: 100xx */
5424 || ((rt
& 0x1e) == 0x1c && rs
== 0));
5425 /* BPOSGE32, BPOSGE64: bits 1110x */
5426 break; /* end REGIMM */
5427 default: /* J, JAL, BEQ, BNE, BLEZ, BGTZ */
5433 /* Return non-zero if the ADDR instruction, which must be a 32-bit
5434 instruction if MUSTBE32 is set or can be any instruction otherwise,
5435 has a branch delay slot (i.e. it is a non-compact jump instruction). */
5438 mips16_instruction_has_delay_slot (struct gdbarch
*gdbarch
, CORE_ADDR addr
,
5441 gdb_byte buf
[MIPS_INSN16_SIZE
];
5442 unsigned short inst
;
5445 status
= target_read_memory (addr
, buf
, MIPS_INSN16_SIZE
);
5449 inst
= mips_fetch_instruction (gdbarch
, addr
);
5451 return (inst
& 0xf89f) == 0xe800; /* JR/JALR (16-bit instruction) */
5452 return (inst
& 0xf800) == 0x1800; /* JAL/JALX (32-bit instruction) */
5455 /* Calculate the starting address of the MIPS memory segment BPADDR is in.
5456 This assumes KSSEG exists. */
5459 mips_segment_boundary (CORE_ADDR bpaddr
)
5461 CORE_ADDR mask
= CORE_ADDR_MAX
;
5464 if (sizeof (CORE_ADDR
) == 8)
5465 /* Get the topmost two bits of bpaddr in a 32-bit safe manner (avoid
5466 a compiler warning produced where CORE_ADDR is a 32-bit type even
5467 though in that case this is dead code). */
5468 switch (bpaddr
>> ((sizeof (CORE_ADDR
) << 3) - 2) & 3)
5471 if (bpaddr
== (bfd_signed_vma
) (int32_t) bpaddr
)
5472 segsize
= 29; /* 32-bit compatibility segment */
5474 segsize
= 62; /* xkseg */
5476 case 2: /* xkphys */
5479 default: /* xksseg (1), xkuseg/kuseg (0) */
5483 else if (bpaddr
& 0x80000000) /* kernel segment */
5486 segsize
= 31; /* user segment */
5488 return bpaddr
& mask
;
5491 /* Move the breakpoint at BPADDR out of any branch delay slot by shifting
5492 it backwards if necessary. Return the address of the new location. */
5495 mips_adjust_breakpoint_address (struct gdbarch
*gdbarch
, CORE_ADDR bpaddr
)
5497 CORE_ADDR prev_addr
, next_addr
;
5499 CORE_ADDR func_addr
;
5501 /* If a breakpoint is set on the instruction in a branch delay slot,
5502 GDB gets confused. When the breakpoint is hit, the PC isn't on
5503 the instruction in the branch delay slot, the PC will point to
5504 the branch instruction. Since the PC doesn't match any known
5505 breakpoints, GDB reports a trap exception.
5507 There are two possible fixes for this problem.
5509 1) When the breakpoint gets hit, see if the BD bit is set in the
5510 Cause register (which indicates the last exception occurred in a
5511 branch delay slot). If the BD bit is set, fix the PC to point to
5512 the instruction in the branch delay slot.
5514 2) When the user sets the breakpoint, don't allow him to set the
5515 breakpoint on the instruction in the branch delay slot. Instead
5516 move the breakpoint to the branch instruction (which will have
5519 The problem with the first solution is that if the user then
5520 single-steps the processor, the branch instruction will get
5521 skipped (since GDB thinks the PC is on the instruction in the
5524 So, we'll use the second solution. To do this we need to know if
5525 the instruction we're trying to set the breakpoint on is in the
5526 branch delay slot. */
5528 boundary
= mips_segment_boundary (bpaddr
);
5530 /* Make sure we don't scan back before the beginning of the current
5531 function, since we may fetch constant data or insns that look like
5532 a jump. Of course we might do that anyway if the compiler has
5533 moved constants inline. :-( */
5534 if (find_pc_partial_function (bpaddr
, NULL
, &func_addr
, NULL
)
5535 && func_addr
> boundary
&& func_addr
<= bpaddr
)
5536 boundary
= func_addr
;
5538 if (!mips_pc_is_mips16 (bpaddr
))
5540 if (bpaddr
== boundary
)
5543 /* If the previous instruction has a branch delay slot, we have
5544 to move the breakpoint to the branch instruction. */
5545 prev_addr
= bpaddr
- 4;
5546 if (mips32_instruction_has_delay_slot (gdbarch
, prev_addr
))
5551 struct minimal_symbol
*sym
;
5552 CORE_ADDR addr
, jmpaddr
;
5555 boundary
= unmake_mips16_addr (boundary
);
5557 /* The only MIPS16 instructions with delay slots are JAL, JALX,
5558 JALR and JR. An absolute JAL/JALX is always 4 bytes long,
5559 so try for that first, then try the 2 byte JALR/JR.
5560 FIXME: We have to assume that bpaddr is not the second half
5561 of an extended instruction. */
5565 for (i
= 1; i
< 4; i
++)
5567 if (unmake_mips16_addr (addr
) == boundary
)
5570 if (i
== 1 && mips16_instruction_has_delay_slot (gdbarch
, addr
, 0))
5571 /* Looks like a JR/JALR at [target-1], but it could be
5572 the second word of a previous JAL/JALX, so record it
5573 and check back one more. */
5576 && mips16_instruction_has_delay_slot (gdbarch
, addr
, 1))
5579 /* Looks like a JAL/JALX at [target-2], but it could also
5580 be the second word of a previous JAL/JALX, record it,
5581 and check back one more. */
5584 /* Looks like a JAL/JALX at [target-3], so any previously
5585 recorded JAL/JALX or JR/JALR must be wrong, because:
5588 -2: JAL-ext (can't be JAL/JALX)
5589 -1: bdslot (can't be JR/JALR)
5592 Of course it could be another JAL-ext which looks
5593 like a JAL, but in that case we'd have broken out
5594 of this loop at [target-2]:
5598 -2: bdslot (can't be jmp)
5605 /* Not a jump instruction: if we're at [target-1] this
5606 could be the second word of a JAL/JALX, so continue;
5607 otherwise we're done. */
5620 /* If PC is in a mips16 call or return stub, return the address of the target
5621 PC, which is either the callee or the caller. There are several
5622 cases which must be handled:
5624 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5625 target PC is in $31 ($ra).
5626 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5627 and the target PC is in $2.
5628 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5629 before the jal instruction, this is effectively a call stub
5630 and the target PC is in $2. Otherwise this is effectively
5631 a return stub and the target PC is in $18.
5633 See the source code for the stubs in gcc/config/mips/mips16.S for
5637 mips_skip_mips16_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
5639 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5641 CORE_ADDR start_addr
;
5643 /* Find the starting address and name of the function containing the PC. */
5644 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
5647 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5648 target PC is in $31 ($ra). */
5649 if (strcmp (name
, "__mips16_ret_sf") == 0
5650 || strcmp (name
, "__mips16_ret_df") == 0)
5651 return get_frame_register_signed (frame
, MIPS_RA_REGNUM
);
5653 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5655 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5656 and the target PC is in $2. */
5657 if (name
[19] >= '0' && name
[19] <= '9')
5658 return get_frame_register_signed (frame
, 2);
5660 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5661 before the jal instruction, this is effectively a call stub
5662 and the target PC is in $2. Otherwise this is effectively
5663 a return stub and the target PC is in $18. */
5664 else if (name
[19] == 's' || name
[19] == 'd')
5666 if (pc
== start_addr
)
5668 /* Check if the target of the stub is a compiler-generated
5669 stub. Such a stub for a function bar might have a name
5670 like __fn_stub_bar, and might look like this:
5675 la $1,bar (becomes a lui/addiu pair)
5677 So scan down to the lui/addi and extract the target
5678 address from those two instructions. */
5680 CORE_ADDR target_pc
= get_frame_register_signed (frame
, 2);
5683 /* See if the name of the target function is __fn_stub_*. */
5684 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) ==
5687 if (strncmp (name
, "__fn_stub_", 10) != 0
5688 && strcmp (name
, "etext") != 0
5689 && strcmp (name
, "_etext") != 0)
5692 /* Scan through this _fn_stub_ code for the lui/addiu pair.
5693 The limit on the search is arbitrarily set to 20
5694 instructions. FIXME. */
5695 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSN32_SIZE
)
5697 ULONGEST inst
= mips_fetch_instruction (gdbarch
, target_pc
);
5698 CORE_ADDR addr
= inst
;
5700 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
5701 pc
= (((addr
& 0xffff) ^ 0x8000) - 0x8000) << 16;
5703 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
5704 return pc
+ ((addr
& 0xffff) ^ 0x8000) - 0x8000;
5708 /* Couldn't find the lui/addui pair, so return stub address. */
5712 /* This is the 'return' part of a call stub. The return
5713 address is in $r18. */
5714 return get_frame_register_signed (frame
, 18);
5717 return 0; /* not a stub */
5720 /* If the current PC is the start of a non-PIC-to-PIC stub, return the
5721 PC of the stub target. The stub just loads $t9 and jumps to it,
5722 so that $t9 has the correct value at function entry. */
5725 mips_skip_pic_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
5727 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5728 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5729 struct minimal_symbol
*msym
;
5731 gdb_byte stub_code
[16];
5732 int32_t stub_words
[4];
5734 /* The stub for foo is named ".pic.foo", and is either two
5735 instructions inserted before foo or a three instruction sequence
5736 which jumps to foo. */
5737 msym
= lookup_minimal_symbol_by_pc (pc
);
5739 || SYMBOL_VALUE_ADDRESS (msym
) != pc
5740 || SYMBOL_LINKAGE_NAME (msym
) == NULL
5741 || strncmp (SYMBOL_LINKAGE_NAME (msym
), ".pic.", 5) != 0)
5744 /* A two-instruction header. */
5745 if (MSYMBOL_SIZE (msym
) == 8)
5748 /* A three-instruction (plus delay slot) trampoline. */
5749 if (MSYMBOL_SIZE (msym
) == 16)
5751 if (target_read_memory (pc
, stub_code
, 16) != 0)
5753 for (i
= 0; i
< 4; i
++)
5754 stub_words
[i
] = extract_unsigned_integer (stub_code
+ i
* 4,
5757 /* A stub contains these instructions:
5760 addiu t9, t9, %lo(target)
5763 This works even for N64, since stubs are only generated with
5765 if ((stub_words
[0] & 0xffff0000U
) == 0x3c190000
5766 && (stub_words
[1] & 0xfc000000U
) == 0x08000000
5767 && (stub_words
[2] & 0xffff0000U
) == 0x27390000
5768 && stub_words
[3] == 0x00000000)
5769 return (((stub_words
[0] & 0x0000ffff) << 16)
5770 + (stub_words
[2] & 0x0000ffff));
5773 /* Not a recognized stub. */
5778 mips_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
5780 CORE_ADDR target_pc
;
5782 target_pc
= mips_skip_mips16_trampoline_code (frame
, pc
);
5786 target_pc
= find_solib_trampoline_target (frame
, pc
);
5790 target_pc
= mips_skip_pic_trampoline_code (frame
, pc
);
5797 /* Convert a dbx stab register number (from `r' declaration) to a GDB
5798 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
5801 mips_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
5804 if (num
>= 0 && num
< 32)
5806 else if (num
>= 38 && num
< 70)
5807 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 38;
5809 regnum
= mips_regnum (gdbarch
)->hi
;
5811 regnum
= mips_regnum (gdbarch
)->lo
;
5812 else if (mips_regnum (gdbarch
)->dspacc
!= -1 && num
>= 72 && num
< 78)
5813 regnum
= num
+ mips_regnum (gdbarch
)->dspacc
- 72;
5815 /* This will hopefully (eventually) provoke a warning. Should
5816 we be calling complaint() here? */
5817 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
5818 return gdbarch_num_regs (gdbarch
) + regnum
;
5822 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
5823 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
5826 mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
5829 if (num
>= 0 && num
< 32)
5831 else if (num
>= 32 && num
< 64)
5832 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 32;
5834 regnum
= mips_regnum (gdbarch
)->hi
;
5836 regnum
= mips_regnum (gdbarch
)->lo
;
5837 else if (mips_regnum (gdbarch
)->dspacc
!= -1 && num
>= 66 && num
< 72)
5838 regnum
= num
+ mips_regnum (gdbarch
)->dspacc
- 66;
5840 /* This will hopefully (eventually) provoke a warning. Should we
5841 be calling complaint() here? */
5842 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
5843 return gdbarch_num_regs (gdbarch
) + regnum
;
5847 mips_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
5849 /* Only makes sense to supply raw registers. */
5850 gdb_assert (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
));
5851 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
5852 decide if it is valid. Should instead define a standard sim/gdb
5853 register numbering scheme. */
5854 if (gdbarch_register_name (gdbarch
,
5855 gdbarch_num_regs (gdbarch
) + regnum
) != NULL
5856 && gdbarch_register_name (gdbarch
,
5857 gdbarch_num_regs (gdbarch
)
5858 + regnum
)[0] != '\0')
5861 return LEGACY_SIM_REGNO_IGNORE
;
5865 /* Convert an integer into an address. Extracting the value signed
5866 guarantees a correctly sign extended address. */
5869 mips_integer_to_address (struct gdbarch
*gdbarch
,
5870 struct type
*type
, const gdb_byte
*buf
)
5872 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5873 return extract_signed_integer (buf
, TYPE_LENGTH (type
), byte_order
);
5876 /* Dummy virtual frame pointer method. This is no more or less accurate
5877 than most other architectures; we just need to be explicit about it,
5878 because the pseudo-register gdbarch_sp_regnum will otherwise lead to
5879 an assertion failure. */
5882 mips_virtual_frame_pointer (struct gdbarch
*gdbarch
,
5883 CORE_ADDR pc
, int *reg
, LONGEST
*offset
)
5885 *reg
= MIPS_SP_REGNUM
;
5890 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
5892 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
5893 const char *name
= bfd_get_section_name (abfd
, sect
);
5895 if (*abip
!= MIPS_ABI_UNKNOWN
)
5898 if (strncmp (name
, ".mdebug.", 8) != 0)
5901 if (strcmp (name
, ".mdebug.abi32") == 0)
5902 *abip
= MIPS_ABI_O32
;
5903 else if (strcmp (name
, ".mdebug.abiN32") == 0)
5904 *abip
= MIPS_ABI_N32
;
5905 else if (strcmp (name
, ".mdebug.abi64") == 0)
5906 *abip
= MIPS_ABI_N64
;
5907 else if (strcmp (name
, ".mdebug.abiO64") == 0)
5908 *abip
= MIPS_ABI_O64
;
5909 else if (strcmp (name
, ".mdebug.eabi32") == 0)
5910 *abip
= MIPS_ABI_EABI32
;
5911 else if (strcmp (name
, ".mdebug.eabi64") == 0)
5912 *abip
= MIPS_ABI_EABI64
;
5914 warning (_("unsupported ABI %s."), name
+ 8);
5918 mips_find_long_section (bfd
*abfd
, asection
*sect
, void *obj
)
5920 int *lbp
= (int *) obj
;
5921 const char *name
= bfd_get_section_name (abfd
, sect
);
5923 if (strncmp (name
, ".gcc_compiled_long32", 20) == 0)
5925 else if (strncmp (name
, ".gcc_compiled_long64", 20) == 0)
5927 else if (strncmp (name
, ".gcc_compiled_long", 18) == 0)
5928 warning (_("unrecognized .gcc_compiled_longXX"));
5931 static enum mips_abi
5932 global_mips_abi (void)
5936 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
5937 if (mips_abi_strings
[i
] == mips_abi_string
)
5938 return (enum mips_abi
) i
;
5940 internal_error (__FILE__
, __LINE__
, _("unknown ABI string"));
5944 mips_register_g_packet_guesses (struct gdbarch
*gdbarch
)
5946 /* If the size matches the set of 32-bit or 64-bit integer registers,
5947 assume that's what we've got. */
5948 register_remote_g_packet_guess (gdbarch
, 38 * 4, mips_tdesc_gp32
);
5949 register_remote_g_packet_guess (gdbarch
, 38 * 8, mips_tdesc_gp64
);
5951 /* If the size matches the full set of registers GDB traditionally
5952 knows about, including floating point, for either 32-bit or
5953 64-bit, assume that's what we've got. */
5954 register_remote_g_packet_guess (gdbarch
, 90 * 4, mips_tdesc_gp32
);
5955 register_remote_g_packet_guess (gdbarch
, 90 * 8, mips_tdesc_gp64
);
5957 /* Otherwise we don't have a useful guess. */
5960 static struct value
*
5961 value_of_mips_user_reg (struct frame_info
*frame
, const void *baton
)
5963 const int *reg_p
= baton
;
5964 return value_of_register (*reg_p
, frame
);
5967 static struct gdbarch
*
5968 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
5970 struct gdbarch
*gdbarch
;
5971 struct gdbarch_tdep
*tdep
;
5973 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
5975 enum mips_fpu_type fpu_type
;
5976 struct tdesc_arch_data
*tdesc_data
= NULL
;
5977 int elf_fpu_type
= 0;
5978 const char **reg_names
;
5979 struct mips_regnum mips_regnum
, *regnum
;
5983 /* Fill in the OS dependent register numbers and names. */
5984 if (info
.osabi
== GDB_OSABI_IRIX
)
5986 mips_regnum
.fp0
= 32;
5987 mips_regnum
.pc
= 64;
5988 mips_regnum
.cause
= 65;
5989 mips_regnum
.badvaddr
= 66;
5990 mips_regnum
.hi
= 67;
5991 mips_regnum
.lo
= 68;
5992 mips_regnum
.fp_control_status
= 69;
5993 mips_regnum
.fp_implementation_revision
= 70;
5994 mips_regnum
.dspacc
= dspacc
= -1;
5995 mips_regnum
.dspctl
= dspctl
= -1;
5997 reg_names
= mips_irix_reg_names
;
5999 else if (info
.osabi
== GDB_OSABI_LINUX
)
6001 mips_regnum
.fp0
= 38;
6002 mips_regnum
.pc
= 37;
6003 mips_regnum
.cause
= 36;
6004 mips_regnum
.badvaddr
= 35;
6005 mips_regnum
.hi
= 34;
6006 mips_regnum
.lo
= 33;
6007 mips_regnum
.fp_control_status
= 70;
6008 mips_regnum
.fp_implementation_revision
= 71;
6009 mips_regnum
.dspacc
= -1;
6010 mips_regnum
.dspctl
= -1;
6014 reg_names
= mips_linux_reg_names
;
6018 mips_regnum
.lo
= MIPS_EMBED_LO_REGNUM
;
6019 mips_regnum
.hi
= MIPS_EMBED_HI_REGNUM
;
6020 mips_regnum
.badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
6021 mips_regnum
.cause
= MIPS_EMBED_CAUSE_REGNUM
;
6022 mips_regnum
.pc
= MIPS_EMBED_PC_REGNUM
;
6023 mips_regnum
.fp0
= MIPS_EMBED_FP0_REGNUM
;
6024 mips_regnum
.fp_control_status
= 70;
6025 mips_regnum
.fp_implementation_revision
= 71;
6026 mips_regnum
.dspacc
= dspacc
= -1;
6027 mips_regnum
.dspctl
= dspctl
= -1;
6028 num_regs
= MIPS_LAST_EMBED_REGNUM
+ 1;
6029 if (info
.bfd_arch_info
!= NULL
6030 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
6031 reg_names
= mips_tx39_reg_names
;
6033 reg_names
= mips_generic_reg_names
;
6036 /* Check any target description for validity. */
6037 if (tdesc_has_registers (info
.target_desc
))
6039 static const char *const mips_gprs
[] = {
6040 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
6041 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
6042 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
6043 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
6045 static const char *const mips_fprs
[] = {
6046 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
6047 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
6048 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
6049 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
6052 const struct tdesc_feature
*feature
;
6055 feature
= tdesc_find_feature (info
.target_desc
,
6056 "org.gnu.gdb.mips.cpu");
6057 if (feature
== NULL
)
6060 tdesc_data
= tdesc_data_alloc ();
6063 for (i
= MIPS_ZERO_REGNUM
; i
<= MIPS_RA_REGNUM
; i
++)
6064 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
6068 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6069 mips_regnum
.lo
, "lo");
6070 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6071 mips_regnum
.hi
, "hi");
6072 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6073 mips_regnum
.pc
, "pc");
6077 tdesc_data_cleanup (tdesc_data
);
6081 feature
= tdesc_find_feature (info
.target_desc
,
6082 "org.gnu.gdb.mips.cp0");
6083 if (feature
== NULL
)
6085 tdesc_data_cleanup (tdesc_data
);
6090 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6091 mips_regnum
.badvaddr
, "badvaddr");
6092 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6093 MIPS_PS_REGNUM
, "status");
6094 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6095 mips_regnum
.cause
, "cause");
6099 tdesc_data_cleanup (tdesc_data
);
6103 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
6104 backend is not prepared for that, though. */
6105 feature
= tdesc_find_feature (info
.target_desc
,
6106 "org.gnu.gdb.mips.fpu");
6107 if (feature
== NULL
)
6109 tdesc_data_cleanup (tdesc_data
);
6114 for (i
= 0; i
< 32; i
++)
6115 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6116 i
+ mips_regnum
.fp0
, mips_fprs
[i
]);
6118 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6119 mips_regnum
.fp_control_status
,
6122 &= tdesc_numbered_register (feature
, tdesc_data
,
6123 mips_regnum
.fp_implementation_revision
,
6128 tdesc_data_cleanup (tdesc_data
);
6134 feature
= tdesc_find_feature (info
.target_desc
,
6135 "org.gnu.gdb.mips.dsp");
6136 /* The DSP registers are optional; it's OK if they are absent. */
6137 if (feature
!= NULL
)
6141 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6142 dspacc
+ i
++, "hi1");
6143 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6144 dspacc
+ i
++, "lo1");
6145 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6146 dspacc
+ i
++, "hi2");
6147 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6148 dspacc
+ i
++, "lo2");
6149 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6150 dspacc
+ i
++, "hi3");
6151 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6152 dspacc
+ i
++, "lo3");
6154 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6159 tdesc_data_cleanup (tdesc_data
);
6163 mips_regnum
.dspacc
= dspacc
;
6164 mips_regnum
.dspctl
= dspctl
;
6168 /* It would be nice to detect an attempt to use a 64-bit ABI
6169 when only 32-bit registers are provided. */
6173 /* First of all, extract the elf_flags, if available. */
6174 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
6175 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
6176 else if (arches
!= NULL
)
6177 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
6181 fprintf_unfiltered (gdb_stdlog
,
6182 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
6184 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
6185 switch ((elf_flags
& EF_MIPS_ABI
))
6187 case E_MIPS_ABI_O32
:
6188 found_abi
= MIPS_ABI_O32
;
6190 case E_MIPS_ABI_O64
:
6191 found_abi
= MIPS_ABI_O64
;
6193 case E_MIPS_ABI_EABI32
:
6194 found_abi
= MIPS_ABI_EABI32
;
6196 case E_MIPS_ABI_EABI64
:
6197 found_abi
= MIPS_ABI_EABI64
;
6200 if ((elf_flags
& EF_MIPS_ABI2
))
6201 found_abi
= MIPS_ABI_N32
;
6203 found_abi
= MIPS_ABI_UNKNOWN
;
6207 /* GCC creates a pseudo-section whose name describes the ABI. */
6208 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
6209 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
6211 /* If we have no useful BFD information, use the ABI from the last
6212 MIPS architecture (if there is one). */
6213 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
6214 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
6216 /* Try the architecture for any hint of the correct ABI. */
6217 if (found_abi
== MIPS_ABI_UNKNOWN
6218 && info
.bfd_arch_info
!= NULL
6219 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
6221 switch (info
.bfd_arch_info
->mach
)
6223 case bfd_mach_mips3900
:
6224 found_abi
= MIPS_ABI_EABI32
;
6226 case bfd_mach_mips4100
:
6227 case bfd_mach_mips5000
:
6228 found_abi
= MIPS_ABI_EABI64
;
6230 case bfd_mach_mips8000
:
6231 case bfd_mach_mips10000
:
6232 /* On Irix, ELF64 executables use the N64 ABI. The
6233 pseudo-sections which describe the ABI aren't present
6234 on IRIX. (Even for executables created by gcc.) */
6235 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
6236 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
6237 found_abi
= MIPS_ABI_N64
;
6239 found_abi
= MIPS_ABI_N32
;
6244 /* Default 64-bit objects to N64 instead of O32. */
6245 if (found_abi
== MIPS_ABI_UNKNOWN
6246 && info
.abfd
!= NULL
6247 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
6248 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
6249 found_abi
= MIPS_ABI_N64
;
6252 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
6255 /* What has the user specified from the command line? */
6256 wanted_abi
= global_mips_abi ();
6258 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
6261 /* Now that we have found what the ABI for this binary would be,
6262 check whether the user is overriding it. */
6263 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
6264 mips_abi
= wanted_abi
;
6265 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
6266 mips_abi
= found_abi
;
6268 mips_abi
= MIPS_ABI_O32
;
6270 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
6273 /* Also used when doing an architecture lookup. */
6275 fprintf_unfiltered (gdb_stdlog
,
6276 "mips_gdbarch_init: "
6277 "mips64_transfers_32bit_regs_p = %d\n",
6278 mips64_transfers_32bit_regs_p
);
6280 /* Determine the MIPS FPU type. */
6283 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
6284 elf_fpu_type
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
6285 Tag_GNU_MIPS_ABI_FP
);
6286 #endif /* HAVE_ELF */
6288 if (!mips_fpu_type_auto
)
6289 fpu_type
= mips_fpu_type
;
6290 else if (elf_fpu_type
!= 0)
6292 switch (elf_fpu_type
)
6295 fpu_type
= MIPS_FPU_DOUBLE
;
6298 fpu_type
= MIPS_FPU_SINGLE
;
6302 /* Soft float or unknown. */
6303 fpu_type
= MIPS_FPU_NONE
;
6307 else if (info
.bfd_arch_info
!= NULL
6308 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
6309 switch (info
.bfd_arch_info
->mach
)
6311 case bfd_mach_mips3900
:
6312 case bfd_mach_mips4100
:
6313 case bfd_mach_mips4111
:
6314 case bfd_mach_mips4120
:
6315 fpu_type
= MIPS_FPU_NONE
;
6317 case bfd_mach_mips4650
:
6318 fpu_type
= MIPS_FPU_SINGLE
;
6321 fpu_type
= MIPS_FPU_DOUBLE
;
6324 else if (arches
!= NULL
)
6325 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
6327 fpu_type
= MIPS_FPU_DOUBLE
;
6329 fprintf_unfiltered (gdb_stdlog
,
6330 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
6332 /* Check for blatant incompatibilities. */
6334 /* If we have only 32-bit registers, then we can't debug a 64-bit
6336 if (info
.target_desc
6337 && tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
6338 && mips_abi
!= MIPS_ABI_EABI32
6339 && mips_abi
!= MIPS_ABI_O32
)
6341 if (tdesc_data
!= NULL
)
6342 tdesc_data_cleanup (tdesc_data
);
6346 /* Try to find a pre-existing architecture. */
6347 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
6349 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
6351 /* MIPS needs to be pedantic about which ABI the object is
6353 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
6355 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
6357 /* Need to be pedantic about which register virtual size is
6359 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
6360 != mips64_transfers_32bit_regs_p
)
6362 /* Be pedantic about which FPU is selected. */
6363 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
6366 if (tdesc_data
!= NULL
)
6367 tdesc_data_cleanup (tdesc_data
);
6368 return arches
->gdbarch
;
6371 /* Need a new architecture. Fill in a target specific vector. */
6372 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
6373 gdbarch
= gdbarch_alloc (&info
, tdep
);
6374 tdep
->elf_flags
= elf_flags
;
6375 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
6376 tdep
->found_abi
= found_abi
;
6377 tdep
->mips_abi
= mips_abi
;
6378 tdep
->mips_fpu_type
= fpu_type
;
6379 tdep
->register_size_valid_p
= 0;
6380 tdep
->register_size
= 0;
6381 tdep
->gregset
= NULL
;
6382 tdep
->gregset64
= NULL
;
6383 tdep
->fpregset
= NULL
;
6384 tdep
->fpregset64
= NULL
;
6386 if (info
.target_desc
)
6388 /* Some useful properties can be inferred from the target. */
6389 if (tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
)
6391 tdep
->register_size_valid_p
= 1;
6392 tdep
->register_size
= 4;
6394 else if (tdesc_property (info
.target_desc
, PROPERTY_GP64
) != NULL
)
6396 tdep
->register_size_valid_p
= 1;
6397 tdep
->register_size
= 8;
6401 /* Initially set everything according to the default ABI/ISA. */
6402 set_gdbarch_short_bit (gdbarch
, 16);
6403 set_gdbarch_int_bit (gdbarch
, 32);
6404 set_gdbarch_float_bit (gdbarch
, 32);
6405 set_gdbarch_double_bit (gdbarch
, 64);
6406 set_gdbarch_long_double_bit (gdbarch
, 64);
6407 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
6408 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
6409 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
6411 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
6412 mips_ax_pseudo_register_collect
);
6413 set_gdbarch_ax_pseudo_register_push_stack
6414 (gdbarch
, mips_ax_pseudo_register_push_stack
);
6416 set_gdbarch_elf_make_msymbol_special (gdbarch
,
6417 mips_elf_make_msymbol_special
);
6419 regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
, struct mips_regnum
);
6420 *regnum
= mips_regnum
;
6421 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
6422 set_gdbarch_num_regs (gdbarch
, num_regs
);
6423 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
6424 set_gdbarch_register_name (gdbarch
, mips_register_name
);
6425 set_gdbarch_virtual_frame_pointer (gdbarch
, mips_virtual_frame_pointer
);
6426 tdep
->mips_processor_reg_names
= reg_names
;
6427 tdep
->regnum
= regnum
;
6432 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
6433 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
6434 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
6435 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
6436 tdep
->default_mask_address_p
= 0;
6437 set_gdbarch_long_bit (gdbarch
, 32);
6438 set_gdbarch_ptr_bit (gdbarch
, 32);
6439 set_gdbarch_long_long_bit (gdbarch
, 64);
6442 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
6443 set_gdbarch_return_value (gdbarch
, mips_o64_return_value
);
6444 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
6445 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
6446 tdep
->default_mask_address_p
= 0;
6447 set_gdbarch_long_bit (gdbarch
, 32);
6448 set_gdbarch_ptr_bit (gdbarch
, 32);
6449 set_gdbarch_long_long_bit (gdbarch
, 64);
6451 case MIPS_ABI_EABI32
:
6452 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
6453 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
6454 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
6455 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6456 tdep
->default_mask_address_p
= 0;
6457 set_gdbarch_long_bit (gdbarch
, 32);
6458 set_gdbarch_ptr_bit (gdbarch
, 32);
6459 set_gdbarch_long_long_bit (gdbarch
, 64);
6461 case MIPS_ABI_EABI64
:
6462 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
6463 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
6464 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
6465 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6466 tdep
->default_mask_address_p
= 0;
6467 set_gdbarch_long_bit (gdbarch
, 64);
6468 set_gdbarch_ptr_bit (gdbarch
, 64);
6469 set_gdbarch_long_long_bit (gdbarch
, 64);
6472 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
6473 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
6474 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
6475 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6476 tdep
->default_mask_address_p
= 0;
6477 set_gdbarch_long_bit (gdbarch
, 32);
6478 set_gdbarch_ptr_bit (gdbarch
, 32);
6479 set_gdbarch_long_long_bit (gdbarch
, 64);
6480 set_gdbarch_long_double_bit (gdbarch
, 128);
6481 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
6484 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
6485 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
6486 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
6487 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6488 tdep
->default_mask_address_p
= 0;
6489 set_gdbarch_long_bit (gdbarch
, 64);
6490 set_gdbarch_ptr_bit (gdbarch
, 64);
6491 set_gdbarch_long_long_bit (gdbarch
, 64);
6492 set_gdbarch_long_double_bit (gdbarch
, 128);
6493 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
6496 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
6499 /* GCC creates a pseudo-section whose name specifies the size of
6500 longs, since -mlong32 or -mlong64 may be used independent of
6501 other options. How those options affect pointer sizes is ABI and
6502 architecture dependent, so use them to override the default sizes
6503 set by the ABI. This table shows the relationship between ABI,
6504 -mlongXX, and size of pointers:
6506 ABI -mlongXX ptr bits
6507 --- -------- --------
6521 Note that for o32 and eabi32, pointers are always 32 bits
6522 regardless of any -mlongXX option. For all others, pointers and
6523 longs are the same, as set by -mlongXX or set by defaults. */
6525 if (info
.abfd
!= NULL
)
6529 bfd_map_over_sections (info
.abfd
, mips_find_long_section
, &long_bit
);
6532 set_gdbarch_long_bit (gdbarch
, long_bit
);
6536 case MIPS_ABI_EABI32
:
6541 case MIPS_ABI_EABI64
:
6542 set_gdbarch_ptr_bit (gdbarch
, long_bit
);
6545 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
6550 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
6551 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
6554 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
6555 flag in object files because to do so would make it impossible to
6556 link with libraries compiled without "-gp32". This is
6557 unnecessarily restrictive.
6559 We could solve this problem by adding "-gp32" multilibs to gcc,
6560 but to set this flag before gcc is built with such multilibs will
6561 break too many systems.''
6563 But even more unhelpfully, the default linker output target for
6564 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
6565 for 64-bit programs - you need to change the ABI to change this,
6566 and not all gcc targets support that currently. Therefore using
6567 this flag to detect 32-bit mode would do the wrong thing given
6568 the current gcc - it would make GDB treat these 64-bit programs
6569 as 32-bit programs by default. */
6571 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
6572 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
6574 /* Add/remove bits from an address. The MIPS needs be careful to
6575 ensure that all 32 bit addresses are sign extended to 64 bits. */
6576 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
6578 /* Unwind the frame. */
6579 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
6580 set_gdbarch_unwind_sp (gdbarch
, mips_unwind_sp
);
6581 set_gdbarch_dummy_id (gdbarch
, mips_dummy_id
);
6583 /* Map debug register numbers onto internal register numbers. */
6584 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
6585 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
6586 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6587 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
6588 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6589 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
6591 /* MIPS version of CALL_DUMMY. */
6593 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
6594 replaced by a command, and all targets will default to on stack
6595 (regardless of the stack's execute status). */
6596 set_gdbarch_call_dummy_location (gdbarch
, AT_SYMBOL
);
6597 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
6599 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
6600 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
6601 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
6603 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
6604 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
6605 set_gdbarch_adjust_breakpoint_address (gdbarch
,
6606 mips_adjust_breakpoint_address
);
6608 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
6610 set_gdbarch_in_function_epilogue_p (gdbarch
, mips_in_function_epilogue_p
);
6612 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
6613 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
6614 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
6616 set_gdbarch_register_type (gdbarch
, mips_register_type
);
6618 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
6620 if (mips_abi
== MIPS_ABI_N32
)
6621 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips_n32
);
6622 else if (mips_abi
== MIPS_ABI_N64
)
6623 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips_n64
);
6625 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
6627 /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint,
6628 HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint
6629 need to all be folded into the target vector. Since they are
6630 being used as guards for target_stopped_by_watchpoint, why not have
6631 target_stopped_by_watchpoint return the type of watchpoint that the code
6633 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
6635 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_trampoline_code
);
6637 set_gdbarch_single_step_through_delay (gdbarch
,
6638 mips_single_step_through_delay
);
6640 /* Virtual tables. */
6641 set_gdbarch_vbit_in_delta (gdbarch
, 1);
6643 mips_register_g_packet_guesses (gdbarch
);
6645 /* Hook in OS ABI-specific overrides, if they have been registered. */
6646 info
.tdep_info
= (void *) tdesc_data
;
6647 gdbarch_init_osabi (info
, gdbarch
);
6649 /* The hook may have adjusted num_regs, fetch the final value and
6650 set pc_regnum and sp_regnum now that it has been fixed. */
6651 /* FIXME: cagney/2003-11-15: For MIPS, hasn't gdbarch_pc_regnum been
6652 replaced by gdbarch_read_pc? */
6653 num_regs
= gdbarch_num_regs (gdbarch
);
6654 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
6655 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
6657 /* Unwind the frame. */
6658 dwarf2_append_unwinders (gdbarch
);
6659 frame_unwind_append_unwinder (gdbarch
, &mips_stub_frame_unwind
);
6660 frame_unwind_append_unwinder (gdbarch
, &mips_insn16_frame_unwind
);
6661 frame_unwind_append_unwinder (gdbarch
, &mips_insn32_frame_unwind
);
6662 frame_base_append_sniffer (gdbarch
, dwarf2_frame_base_sniffer
);
6663 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
6664 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
6665 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
6669 set_tdesc_pseudo_register_type (gdbarch
, mips_pseudo_register_type
);
6670 tdesc_use_registers (gdbarch
, info
.target_desc
, tdesc_data
);
6672 /* Override the normal target description methods to handle our
6673 dual real and pseudo registers. */
6674 set_gdbarch_register_name (gdbarch
, mips_register_name
);
6675 set_gdbarch_register_reggroup_p (gdbarch
,
6676 mips_tdesc_register_reggroup_p
);
6678 num_regs
= gdbarch_num_regs (gdbarch
);
6679 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
6680 set_gdbarch_pc_regnum (gdbarch
, tdep
->regnum
->pc
+ num_regs
);
6681 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
6684 /* Add ABI-specific aliases for the registers. */
6685 if (mips_abi
== MIPS_ABI_N32
|| mips_abi
== MIPS_ABI_N64
)
6686 for (i
= 0; i
< ARRAY_SIZE (mips_n32_n64_aliases
); i
++)
6687 user_reg_add (gdbarch
, mips_n32_n64_aliases
[i
].name
,
6688 value_of_mips_user_reg
, &mips_n32_n64_aliases
[i
].regnum
);
6690 for (i
= 0; i
< ARRAY_SIZE (mips_o32_aliases
); i
++)
6691 user_reg_add (gdbarch
, mips_o32_aliases
[i
].name
,
6692 value_of_mips_user_reg
, &mips_o32_aliases
[i
].regnum
);
6694 /* Add some other standard aliases. */
6695 for (i
= 0; i
< ARRAY_SIZE (mips_register_aliases
); i
++)
6696 user_reg_add (gdbarch
, mips_register_aliases
[i
].name
,
6697 value_of_mips_user_reg
, &mips_register_aliases
[i
].regnum
);
6699 for (i
= 0; i
< ARRAY_SIZE (mips_numeric_register_aliases
); i
++)
6700 user_reg_add (gdbarch
, mips_numeric_register_aliases
[i
].name
,
6701 value_of_mips_user_reg
,
6702 &mips_numeric_register_aliases
[i
].regnum
);
6708 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
6710 struct gdbarch_info info
;
6712 /* Force the architecture to update, and (if it's a MIPS architecture)
6713 mips_gdbarch_init will take care of the rest. */
6714 gdbarch_info_init (&info
);
6715 gdbarch_update_p (info
);
6718 /* Print out which MIPS ABI is in use. */
6721 show_mips_abi (struct ui_file
*file
,
6723 struct cmd_list_element
*ignored_cmd
,
6724 const char *ignored_value
)
6726 if (gdbarch_bfd_arch_info (target_gdbarch
)->arch
!= bfd_arch_mips
)
6729 "The MIPS ABI is unknown because the current architecture "
6733 enum mips_abi global_abi
= global_mips_abi ();
6734 enum mips_abi actual_abi
= mips_abi (target_gdbarch
);
6735 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
6737 if (global_abi
== MIPS_ABI_UNKNOWN
)
6740 "The MIPS ABI is set automatically (currently \"%s\").\n",
6742 else if (global_abi
== actual_abi
)
6745 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
6749 /* Probably shouldn't happen... */
6750 fprintf_filtered (file
,
6751 "The (auto detected) MIPS ABI \"%s\" is in use "
6752 "even though the user setting was \"%s\".\n",
6753 actual_abi_str
, mips_abi_strings
[global_abi
]);
6759 mips_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
6761 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
6765 int ef_mips_32bitmode
;
6766 /* Determine the ISA. */
6767 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
6785 /* Determine the size of a pointer. */
6786 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
6787 fprintf_unfiltered (file
,
6788 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
6790 fprintf_unfiltered (file
,
6791 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
6793 fprintf_unfiltered (file
,
6794 "mips_dump_tdep: ef_mips_arch = %d\n",
6796 fprintf_unfiltered (file
,
6797 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
6798 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
6799 fprintf_unfiltered (file
,
6801 "mips_mask_address_p() %d (default %d)\n",
6802 mips_mask_address_p (tdep
),
6803 tdep
->default_mask_address_p
);
6805 fprintf_unfiltered (file
,
6806 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
6807 MIPS_DEFAULT_FPU_TYPE
,
6808 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
6809 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
6810 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
6812 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n",
6813 MIPS_EABI (gdbarch
));
6814 fprintf_unfiltered (file
,
6815 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
6816 MIPS_FPU_TYPE (gdbarch
),
6817 (MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_NONE
? "none"
6818 : MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_SINGLE
? "single"
6819 : MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_DOUBLE
? "double"
6823 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
6826 _initialize_mips_tdep (void)
6828 static struct cmd_list_element
*mipsfpulist
= NULL
;
6829 struct cmd_list_element
*c
;
6831 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
6832 if (MIPS_ABI_LAST
+ 1
6833 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
6834 internal_error (__FILE__
, __LINE__
, _("mips_abi_strings out of sync"));
6836 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
6838 mips_pdr_data
= register_objfile_data ();
6840 /* Create feature sets with the appropriate properties. The values
6841 are not important. */
6842 mips_tdesc_gp32
= allocate_target_description ();
6843 set_tdesc_property (mips_tdesc_gp32
, PROPERTY_GP32
, "");
6845 mips_tdesc_gp64
= allocate_target_description ();
6846 set_tdesc_property (mips_tdesc_gp64
, PROPERTY_GP64
, "");
6848 /* Add root prefix command for all "set mips"/"show mips" commands. */
6849 add_prefix_cmd ("mips", no_class
, set_mips_command
,
6850 _("Various MIPS specific commands."),
6851 &setmipscmdlist
, "set mips ", 0, &setlist
);
6853 add_prefix_cmd ("mips", no_class
, show_mips_command
,
6854 _("Various MIPS specific commands."),
6855 &showmipscmdlist
, "show mips ", 0, &showlist
);
6857 /* Allow the user to override the ABI. */
6858 add_setshow_enum_cmd ("abi", class_obscure
, mips_abi_strings
,
6859 &mips_abi_string
, _("\
6860 Set the MIPS ABI used by this program."), _("\
6861 Show the MIPS ABI used by this program."), _("\
6862 This option can be set to one of:\n\
6863 auto - the default ABI associated with the current binary\n\
6872 &setmipscmdlist
, &showmipscmdlist
);
6874 /* Let the user turn off floating point and set the fence post for
6875 heuristic_proc_start. */
6877 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
6878 _("Set use of MIPS floating-point coprocessor."),
6879 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
6880 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
6881 _("Select single-precision MIPS floating-point coprocessor."),
6883 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
6884 _("Select double-precision MIPS floating-point coprocessor."),
6886 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
6887 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
6888 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
6889 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
6890 _("Select no MIPS floating-point coprocessor."), &mipsfpulist
);
6891 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
6892 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
6893 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
6894 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
6895 _("Select MIPS floating-point coprocessor automatically."),
6897 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
6898 _("Show current use of MIPS floating-point coprocessor target."),
6901 /* We really would like to have both "0" and "unlimited" work, but
6902 command.c doesn't deal with that. So make it a var_zinteger
6903 because the user can always use "999999" or some such for unlimited. */
6904 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support
,
6905 &heuristic_fence_post
, _("\
6906 Set the distance searched for the start of a function."), _("\
6907 Show the distance searched for the start of a function."), _("\
6908 If you are debugging a stripped executable, GDB needs to search through the\n\
6909 program for the start of a function. This command sets the distance of the\n\
6910 search. The only need to set it is when debugging a stripped executable."),
6911 reinit_frame_cache_sfunc
,
6912 NULL
, /* FIXME: i18n: The distance searched for
6913 the start of a function is %s. */
6914 &setlist
, &showlist
);
6916 /* Allow the user to control whether the upper bits of 64-bit
6917 addresses should be zeroed. */
6918 add_setshow_auto_boolean_cmd ("mask-address", no_class
,
6919 &mask_address_var
, _("\
6920 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
6921 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
6922 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\
6923 allow GDB to determine the correct value."),
6924 NULL
, show_mask_address
,
6925 &setmipscmdlist
, &showmipscmdlist
);
6927 /* Allow the user to control the size of 32 bit registers within the
6928 raw remote packet. */
6929 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
6930 &mips64_transfers_32bit_regs_p
, _("\
6931 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
6933 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
6935 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6936 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6937 64 bits for others. Use \"off\" to disable compatibility mode"),
6938 set_mips64_transfers_32bit_regs
,
6939 NULL
, /* FIXME: i18n: Compatibility with 64-bit
6940 MIPS target that transfers 32-bit
6941 quantities is %s. */
6942 &setlist
, &showlist
);
6944 /* Debug this files internals. */
6945 add_setshow_zinteger_cmd ("mips", class_maintenance
,
6947 Set mips debugging."), _("\
6948 Show mips debugging."), _("\
6949 When non-zero, mips specific debugging is enabled."),
6951 NULL
, /* FIXME: i18n: Mips debugging is
6953 &setdebuglist
, &showdebuglist
);