1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software
7 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
8 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
10 This file is part of GDB.
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the Free Software
24 Foundation, Inc., 59 Temple Place - Suite 330,
25 Boston, MA 02111-1307, USA. */
28 #include "gdb_string.h"
29 #include "gdb_assert.h"
41 #include "arch-utils.h"
44 #include "mips-tdep.h"
46 #include "reggroups.h"
47 #include "opcode/mips.h"
51 #include "sim-regno.h"
53 #include "frame-unwind.h"
54 #include "frame-base.h"
55 #include "trad-frame.h"
57 #include "floatformat.h"
59 static const struct objfile_data
*mips_pdr_data
;
61 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
63 /* A useful bit in the CP0 status register (PS_REGNUM). */
64 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
65 #define ST0_FR (1 << 26)
67 /* The sizes of floating point registers. */
71 MIPS_FPU_SINGLE_REGSIZE
= 4,
72 MIPS_FPU_DOUBLE_REGSIZE
= 8
76 static const char *mips_abi_string
;
78 static const char *mips_abi_strings
[] = {
89 struct frame_extra_info
91 mips_extra_func_info_t proc_desc
;
95 /* Various MIPS ISA options (related to stack analysis) can be
96 overridden dynamically. Establish an enum/array for managing
99 static const char size_auto
[] = "auto";
100 static const char size_32
[] = "32";
101 static const char size_64
[] = "64";
103 static const char *size_enums
[] = {
110 /* Some MIPS boards don't support floating point while others only
111 support single-precision floating-point operations. */
115 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
116 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
117 MIPS_FPU_NONE
/* No floating point. */
120 #ifndef MIPS_DEFAULT_FPU_TYPE
121 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
123 static int mips_fpu_type_auto
= 1;
124 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
126 static int mips_debug
= 0;
128 /* MIPS specific per-architecture information */
131 /* from the elf header */
135 enum mips_abi mips_abi
;
136 enum mips_abi found_abi
;
137 enum mips_fpu_type mips_fpu_type
;
138 int mips_last_arg_regnum
;
139 int mips_last_fp_arg_regnum
;
140 int default_mask_address_p
;
141 /* Is the target using 64-bit raw integer registers but only
142 storing a left-aligned 32-bit value in each? */
143 int mips64_transfers_32bit_regs_p
;
144 /* Indexes for various registers. IRIX and embedded have
145 different values. This contains the "public" fields. Don't
146 add any that do not need to be public. */
147 const struct mips_regnum
*regnum
;
148 /* Register names table for the current register set. */
149 const char **mips_processor_reg_names
;
153 n32n64_floatformat_always_valid (const struct floatformat
*fmt
,
159 /* FIXME: brobecker/2004-08-08: Long Double values are 128 bit long.
160 They are implemented as a pair of 64bit doubles where the high
161 part holds the result of the operation rounded to double, and
162 the low double holds the difference between the exact result and
163 the rounded result. So "high" + "low" contains the result with
164 added precision. Unfortunately, the floatformat structure used
165 by GDB is not powerful enough to describe this format. As a temporary
166 measure, we define a 128bit floatformat that only uses the high part.
167 We lose a bit of precision but that's probably the best we can do
168 for now with the current infrastructure. */
170 static const struct floatformat floatformat_n32n64_long_double_big
=
172 floatformat_big
, 128, 0, 1, 11, 1023, 2047, 12, 52,
173 floatformat_intbit_no
,
174 "floatformat_ieee_double_big",
175 n32n64_floatformat_always_valid
178 const struct mips_regnum
*
179 mips_regnum (struct gdbarch
*gdbarch
)
181 return gdbarch_tdep (gdbarch
)->regnum
;
185 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
187 return mips_regnum (gdbarch
)->fp0
+ 12;
190 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
191 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
193 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
195 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
197 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
199 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
200 functions to test, set, or clear bit 0 of addresses. */
203 is_mips16_addr (CORE_ADDR addr
)
209 make_mips16_addr (CORE_ADDR addr
)
215 unmake_mips16_addr (CORE_ADDR addr
)
217 return ((addr
) & ~1);
220 /* Return the contents of register REGNUM as a signed integer. */
223 read_signed_register (int regnum
)
225 void *buf
= alloca (register_size (current_gdbarch
, regnum
));
226 deprecated_read_register_gen (regnum
, buf
);
227 return (extract_signed_integer
228 (buf
, register_size (current_gdbarch
, regnum
)));
232 read_signed_register_pid (int regnum
, ptid_t ptid
)
237 if (ptid_equal (ptid
, inferior_ptid
))
238 return read_signed_register (regnum
);
240 save_ptid
= inferior_ptid
;
242 inferior_ptid
= ptid
;
244 retval
= read_signed_register (regnum
);
246 inferior_ptid
= save_ptid
;
251 /* Return the MIPS ABI associated with GDBARCH. */
253 mips_abi (struct gdbarch
*gdbarch
)
255 return gdbarch_tdep (gdbarch
)->mips_abi
;
259 mips_isa_regsize (struct gdbarch
*gdbarch
)
261 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
262 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
265 /* Return the currently configured (or set) saved register size. */
267 static const char *mips_abi_regsize_string
= size_auto
;
270 mips_abi_regsize (struct gdbarch
*gdbarch
)
272 if (mips_abi_regsize_string
== size_auto
)
273 switch (mips_abi (gdbarch
))
275 case MIPS_ABI_EABI32
:
281 case MIPS_ABI_EABI64
:
283 case MIPS_ABI_UNKNOWN
:
286 internal_error (__FILE__
, __LINE__
, "bad switch");
288 else if (mips_abi_regsize_string
== size_64
)
290 else /* if (mips_abi_regsize_string == size_32) */
294 /* Functions for setting and testing a bit in a minimal symbol that
295 marks it as 16-bit function. The MSB of the minimal symbol's
296 "info" field is used for this purpose.
298 ELF_MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special",
299 i.e. refers to a 16-bit function, and sets a "special" bit in a
300 minimal symbol to mark it as a 16-bit function
302 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
305 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
307 if (((elf_symbol_type
*) (sym
))->internal_elf_sym
.st_other
== STO_MIPS16
)
309 MSYMBOL_INFO (msym
) = (char *)
310 (((long) MSYMBOL_INFO (msym
)) | 0x80000000);
311 SYMBOL_VALUE_ADDRESS (msym
) |= 1;
316 msymbol_is_special (struct minimal_symbol
*msym
)
318 return (((long) MSYMBOL_INFO (msym
) & 0x80000000) != 0);
321 /* XFER a value from the big/little/left end of the register.
322 Depending on the size of the value it might occupy the entire
323 register or just part of it. Make an allowance for this, aligning
324 things accordingly. */
327 mips_xfer_register (struct regcache
*regcache
, int reg_num
, int length
,
328 enum bfd_endian endian
, bfd_byte
* in
,
329 const bfd_byte
* out
, int buf_offset
)
332 gdb_assert (reg_num
>= NUM_REGS
);
333 /* Need to transfer the left or right part of the register, based on
334 the targets byte order. */
338 reg_offset
= register_size (current_gdbarch
, reg_num
) - length
;
340 case BFD_ENDIAN_LITTLE
:
343 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
347 internal_error (__FILE__
, __LINE__
, "bad switch");
350 fprintf_unfiltered (gdb_stderr
,
351 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
352 reg_num
, reg_offset
, buf_offset
, length
);
353 if (mips_debug
&& out
!= NULL
)
356 fprintf_unfiltered (gdb_stdlog
, "out ");
357 for (i
= 0; i
< length
; i
++)
358 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
361 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
364 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
366 if (mips_debug
&& in
!= NULL
)
369 fprintf_unfiltered (gdb_stdlog
, "in ");
370 for (i
= 0; i
< length
; i
++)
371 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
374 fprintf_unfiltered (gdb_stdlog
, "\n");
377 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
378 compatiblity mode. A return value of 1 means that we have
379 physical 64-bit registers, but should treat them as 32-bit registers. */
382 mips2_fp_compat (void)
384 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
386 if (register_size (current_gdbarch
, mips_regnum (current_gdbarch
)->fp0
) ==
391 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
392 in all the places we deal with FP registers. PR gdb/413. */
393 /* Otherwise check the FR bit in the status register - it controls
394 the FP compatiblity mode. If it is clear we are in compatibility
396 if ((read_register (PS_REGNUM
) & ST0_FR
) == 0)
403 /* The amount of space reserved on the stack for registers. This is
404 different to MIPS_ABI_REGSIZE as it determines the alignment of
405 data allocated after the registers have run out. */
407 static const char *mips_stack_argsize_string
= size_auto
;
410 mips_stack_argsize (struct gdbarch
*gdbarch
)
412 if (mips_stack_argsize_string
== size_auto
)
413 return mips_abi_regsize (gdbarch
);
414 else if (mips_stack_argsize_string
== size_64
)
416 else /* if (mips_stack_argsize_string == size_32) */
420 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
422 struct mips_frame_cache
;
423 static mips_extra_func_info_t
heuristic_proc_desc (CORE_ADDR
, CORE_ADDR
,
425 struct mips_frame_cache
*);
426 static mips_extra_func_info_t
non_heuristic_proc_desc (CORE_ADDR pc
,
429 static CORE_ADDR
heuristic_proc_start (CORE_ADDR
);
431 static CORE_ADDR
read_next_frame_reg (struct frame_info
*, int);
433 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
435 static CORE_ADDR
after_prologue (CORE_ADDR pc
);
437 static struct type
*mips_float_register_type (void);
438 static struct type
*mips_double_register_type (void);
440 /* The list of available "set mips " and "show mips " commands */
442 static struct cmd_list_element
*setmipscmdlist
= NULL
;
443 static struct cmd_list_element
*showmipscmdlist
= NULL
;
445 /* Integer registers 0 thru 31 are handled explicitly by
446 mips_register_name(). Processor specific registers 32 and above
447 are listed in the followign tables. */
450 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
454 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
455 "sr", "lo", "hi", "bad", "cause", "pc",
456 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
457 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
458 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
459 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
460 "fsr", "fir", "" /*"fp" */ , "",
461 "", "", "", "", "", "", "", "",
462 "", "", "", "", "", "", "", "",
465 /* Names of IDT R3041 registers. */
467 static const char *mips_r3041_reg_names
[] = {
468 "sr", "lo", "hi", "bad", "cause", "pc",
469 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
470 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
471 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
472 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
473 "fsr", "fir", "", /*"fp" */ "",
474 "", "", "bus", "ccfg", "", "", "", "",
475 "", "", "port", "cmp", "", "", "epc", "prid",
478 /* Names of tx39 registers. */
480 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
481 "sr", "lo", "hi", "bad", "cause", "pc",
482 "", "", "", "", "", "", "", "",
483 "", "", "", "", "", "", "", "",
484 "", "", "", "", "", "", "", "",
485 "", "", "", "", "", "", "", "",
487 "", "", "", "", "", "", "", "",
488 "", "", "config", "cache", "debug", "depc", "epc", ""
491 /* Names of IRIX registers. */
492 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
493 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
494 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
495 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
496 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
497 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
501 /* Return the name of the register corresponding to REGNO. */
503 mips_register_name (int regno
)
505 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
506 /* GPR names for all ABIs other than n32/n64. */
507 static char *mips_gpr_names
[] = {
508 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
509 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
510 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
511 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
514 /* GPR names for n32 and n64 ABIs. */
515 static char *mips_n32_n64_gpr_names
[] = {
516 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
517 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
518 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
519 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
522 enum mips_abi abi
= mips_abi (current_gdbarch
);
524 /* Map [NUM_REGS .. 2*NUM_REGS) onto the raw registers, but then
525 don't make the raw register names visible. */
526 int rawnum
= regno
% NUM_REGS
;
527 if (regno
< NUM_REGS
)
530 /* The MIPS integer registers are always mapped from 0 to 31. The
531 names of the registers (which reflects the conventions regarding
532 register use) vary depending on the ABI. */
533 if (0 <= rawnum
&& rawnum
< 32)
535 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
536 return mips_n32_n64_gpr_names
[rawnum
];
538 return mips_gpr_names
[rawnum
];
540 else if (32 <= rawnum
&& rawnum
< NUM_REGS
)
542 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
543 return tdep
->mips_processor_reg_names
[rawnum
- 32];
546 internal_error (__FILE__
, __LINE__
,
547 "mips_register_name: bad register number %d", rawnum
);
550 /* Return the groups that a MIPS register can be categorised into. */
553 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
554 struct reggroup
*reggroup
)
559 int rawnum
= regnum
% NUM_REGS
;
560 int pseudo
= regnum
/ NUM_REGS
;
561 if (reggroup
== all_reggroup
)
563 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
564 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
565 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
566 (gdbarch), as not all architectures are multi-arch. */
567 raw_p
= rawnum
< NUM_REGS
;
568 if (REGISTER_NAME (regnum
) == NULL
|| REGISTER_NAME (regnum
)[0] == '\0')
570 if (reggroup
== float_reggroup
)
571 return float_p
&& pseudo
;
572 if (reggroup
== vector_reggroup
)
573 return vector_p
&& pseudo
;
574 if (reggroup
== general_reggroup
)
575 return (!vector_p
&& !float_p
) && pseudo
;
576 /* Save the pseudo registers. Need to make certain that any code
577 extracting register values from a saved register cache also uses
579 if (reggroup
== save_reggroup
)
580 return raw_p
&& pseudo
;
581 /* Restore the same pseudo register. */
582 if (reggroup
== restore_reggroup
)
583 return raw_p
&& pseudo
;
587 /* Map the symbol table registers which live in the range [1 *
588 NUM_REGS .. 2 * NUM_REGS) back onto the corresponding raw
589 registers. Take care of alignment and size problems. */
592 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
593 int cookednum
, void *buf
)
595 int rawnum
= cookednum
% NUM_REGS
;
596 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
597 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
598 regcache_raw_read (regcache
, rawnum
, buf
);
599 else if (register_size (gdbarch
, rawnum
) >
600 register_size (gdbarch
, cookednum
))
602 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
603 || TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
604 regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
606 regcache_raw_read_part (regcache
, rawnum
, 4, 4, buf
);
609 internal_error (__FILE__
, __LINE__
, "bad register size");
613 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
614 struct regcache
*regcache
, int cookednum
,
617 int rawnum
= cookednum
% NUM_REGS
;
618 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
619 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
620 regcache_raw_write (regcache
, rawnum
, buf
);
621 else if (register_size (gdbarch
, rawnum
) >
622 register_size (gdbarch
, cookednum
))
624 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
625 || TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
626 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
628 regcache_raw_write_part (regcache
, rawnum
, 4, 4, buf
);
631 internal_error (__FILE__
, __LINE__
, "bad register size");
634 /* Table to translate MIPS16 register field to actual register number. */
635 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
637 /* Heuristic_proc_start may hunt through the text section for a long
638 time across a 2400 baud serial line. Allows the user to limit this
641 static unsigned int heuristic_fence_post
= 0;
643 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
644 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
645 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
646 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
647 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
648 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
649 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
650 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
651 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
652 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
653 /* FIXME drow/2002-06-10: If a pointer on the host is bigger than a long,
654 this will corrupt pdr.iline. Fortunately we don't use it. */
655 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
656 #define _PROC_MAGIC_ 0x0F0F0F0F
658 /* Number of bytes of storage in the actual machine representation for
659 register N. NOTE: This defines the pseudo register type so need to
660 rebuild the architecture vector. */
662 static int mips64_transfers_32bit_regs_p
= 0;
665 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
666 struct cmd_list_element
*c
)
668 struct gdbarch_info info
;
669 gdbarch_info_init (&info
);
670 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
671 instead of relying on globals. Doing that would let generic code
672 handle the search for this specific architecture. */
673 if (!gdbarch_update_p (info
))
675 mips64_transfers_32bit_regs_p
= 0;
676 error ("32-bit compatibility mode not supported");
680 /* Convert to/from a register and the corresponding memory value. */
683 mips_convert_register_p (int regnum
, struct type
*type
)
685 return (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
686 && register_size (current_gdbarch
, regnum
) == 4
687 && (regnum
% NUM_REGS
) >= mips_regnum (current_gdbarch
)->fp0
688 && (regnum
% NUM_REGS
) < mips_regnum (current_gdbarch
)->fp0
+ 32
689 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
693 mips_register_to_value (struct frame_info
*frame
, int regnum
,
694 struct type
*type
, void *to
)
696 get_frame_register (frame
, regnum
+ 0, (char *) to
+ 4);
697 get_frame_register (frame
, regnum
+ 1, (char *) to
+ 0);
701 mips_value_to_register (struct frame_info
*frame
, int regnum
,
702 struct type
*type
, const void *from
)
704 put_frame_register (frame
, regnum
+ 0, (const char *) from
+ 4);
705 put_frame_register (frame
, regnum
+ 1, (const char *) from
+ 0);
708 /* Return the GDB type object for the "standard" data type of data in
712 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
714 gdb_assert (regnum
>= 0 && regnum
< 2 * NUM_REGS
);
715 if ((regnum
% NUM_REGS
) >= mips_regnum (current_gdbarch
)->fp0
716 && (regnum
% NUM_REGS
) < mips_regnum (current_gdbarch
)->fp0
+ 32)
718 /* The floating-point registers raw, or cooked, always match
719 mips_isa_regsize(), and also map 1:1, byte for byte. */
720 switch (gdbarch_byte_order (gdbarch
))
723 if (mips_isa_regsize (gdbarch
) == 4)
724 return builtin_type_ieee_single_big
;
726 return builtin_type_ieee_double_big
;
727 case BFD_ENDIAN_LITTLE
:
728 if (mips_isa_regsize (gdbarch
) == 4)
729 return builtin_type_ieee_single_little
;
731 return builtin_type_ieee_double_little
;
732 case BFD_ENDIAN_UNKNOWN
:
734 internal_error (__FILE__
, __LINE__
, "bad switch");
737 else if (regnum
< NUM_REGS
)
739 /* The raw or ISA registers. These are all sized according to
741 if (mips_isa_regsize (gdbarch
) == 4)
742 return builtin_type_int32
;
744 return builtin_type_int64
;
748 /* The cooked or ABI registers. These are sized according to
749 the ABI (with a few complications). */
750 if (regnum
>= (NUM_REGS
751 + mips_regnum (current_gdbarch
)->fp_control_status
)
752 && regnum
<= NUM_REGS
+ LAST_EMBED_REGNUM
)
753 /* The pseudo/cooked view of the embedded registers is always
754 32-bit. The raw view is handled below. */
755 return builtin_type_int32
;
756 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
757 /* The target, while possibly using a 64-bit register buffer,
758 is only transfering 32-bits of each integer register.
759 Reflect this in the cooked/pseudo (ABI) register value. */
760 return builtin_type_int32
;
761 else if (mips_abi_regsize (gdbarch
) == 4)
762 /* The ABI is restricted to 32-bit registers (the ISA could be
764 return builtin_type_int32
;
767 return builtin_type_int64
;
771 /* TARGET_READ_SP -- Remove useless bits from the stack pointer. */
776 return read_signed_register (MIPS_SP_REGNUM
);
779 /* Should the upper word of 64-bit addresses be zeroed? */
780 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
783 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
785 switch (mask_address_var
)
787 case AUTO_BOOLEAN_TRUE
:
789 case AUTO_BOOLEAN_FALSE
:
792 case AUTO_BOOLEAN_AUTO
:
793 return tdep
->default_mask_address_p
;
795 internal_error (__FILE__
, __LINE__
, "mips_mask_address_p: bad switch");
801 show_mask_address (char *cmd
, int from_tty
, struct cmd_list_element
*c
)
803 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
804 switch (mask_address_var
)
806 case AUTO_BOOLEAN_TRUE
:
807 printf_filtered ("The 32 bit mips address mask is enabled\n");
809 case AUTO_BOOLEAN_FALSE
:
810 printf_filtered ("The 32 bit mips address mask is disabled\n");
812 case AUTO_BOOLEAN_AUTO
:
814 ("The 32 bit address mask is set automatically. Currently %s\n",
815 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
818 internal_error (__FILE__
, __LINE__
, "show_mask_address: bad switch");
823 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
826 pc_is_mips16 (bfd_vma memaddr
)
828 struct minimal_symbol
*sym
;
830 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
831 if (is_mips16_addr (memaddr
))
834 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
835 the high bit of the info field. Use this to decide if the function is
836 MIPS16 or normal MIPS. */
837 sym
= lookup_minimal_symbol_by_pc (memaddr
);
839 return msymbol_is_special (sym
);
844 /* MIPS believes that the PC has a sign extended value. Perhaps the
845 all registers should be sign extended for simplicity? */
848 mips_read_pc (ptid_t ptid
)
850 return read_signed_register_pid (mips_regnum (current_gdbarch
)->pc
, ptid
);
854 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
856 return frame_unwind_register_signed (next_frame
,
857 NUM_REGS
+ mips_regnum (gdbarch
)->pc
);
860 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
861 dummy frame. The frame ID's base needs to match the TOS value
862 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
865 static struct frame_id
866 mips_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
868 return frame_id_build (frame_unwind_register_signed (next_frame
, NUM_REGS
+ MIPS_SP_REGNUM
),
869 frame_pc_unwind (next_frame
));
873 mips_write_pc (CORE_ADDR pc
, ptid_t ptid
)
875 write_register_pid (mips_regnum (current_gdbarch
)->pc
, pc
, ptid
);
878 /* This returns the PC of the first inst after the prologue. If we can't
879 find the prologue, then return 0. */
882 after_prologue (CORE_ADDR pc
)
884 mips_extra_func_info_t proc_desc
;
885 struct symtab_and_line sal
;
886 CORE_ADDR func_addr
, func_end
;
887 CORE_ADDR startaddr
= 0;
889 /* Pass a NULL next_frame to heuristic_proc_desc. We should not
890 attempt to read the stack pointer from the current machine state,
891 because the current machine state has nothing to do with the
892 information we need from the proc_desc; and the process may or
893 may not exist right now. */
894 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
897 /* IF this is the topmost frame AND (this proc does not have
898 debugging information OR the PC is in the procedure prologue)
899 THEN create a "heuristic" proc_desc (by analyzing the actual
900 code) to replace the "official" proc_desc. */
901 struct symtab_and_line val
;
902 if (PROC_SYMBOL (proc_desc
))
904 val
= find_pc_line (BLOCK_START
905 (SYMBOL_BLOCK_VALUE (PROC_SYMBOL (proc_desc
))),
907 val
.pc
= val
.end
? val
.end
: pc
;
909 if (!PROC_SYMBOL (proc_desc
) || pc
< val
.pc
)
911 mips_extra_func_info_t found_heuristic
=
912 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc
), pc
, NULL
, NULL
);
914 proc_desc
= found_heuristic
;
920 startaddr
= heuristic_proc_start (pc
);
922 proc_desc
= heuristic_proc_desc (startaddr
, pc
, NULL
, NULL
);
927 /* If function is frameless, then we need to do it the hard way. I
928 strongly suspect that frameless always means prologueless... */
929 if (PROC_FRAME_REG (proc_desc
) == MIPS_SP_REGNUM
930 && PROC_FRAME_OFFSET (proc_desc
) == 0)
934 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
935 return 0; /* Unknown */
937 sal
= find_pc_line (func_addr
, 0);
939 if (sal
.end
< func_end
)
942 /* The line after the prologue is after the end of the function. In this
943 case, tell the caller to find the prologue the hard way. */
948 /* Decode a MIPS16 instruction that saves a register in the stack, and
949 set the appropriate bit in the general register or float register mask
950 to indicate which register is saved. This is a helper function
951 for mips_find_saved_regs. */
954 mips16_decode_reg_save (t_inst inst
, unsigned long *gen_mask
)
956 if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
958 int reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
959 *gen_mask
|= (1 << reg
);
961 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
963 int reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
964 *gen_mask
|= (1 << reg
);
966 else if ((inst
& 0xff00) == 0x6200 /* sw $ra,n($sp) */
967 || (inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
968 *gen_mask
|= (1 << RA_REGNUM
);
972 /* Fetch and return instruction from the specified location. If the PC
973 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
976 mips_fetch_instruction (CORE_ADDR addr
)
978 char buf
[MIPS_INSTLEN
];
982 if (pc_is_mips16 (addr
))
984 instlen
= MIPS16_INSTLEN
;
985 addr
= unmake_mips16_addr (addr
);
988 instlen
= MIPS_INSTLEN
;
989 status
= deprecated_read_memory_nobpt (addr
, buf
, instlen
);
991 memory_error (status
, addr
);
992 return extract_unsigned_integer (buf
, instlen
);
996 mips16_fetch_instruction (CORE_ADDR addr
)
998 char buf
[MIPS_INSTLEN
];
1002 instlen
= MIPS16_INSTLEN
;
1003 addr
= unmake_mips16_addr (addr
);
1004 status
= deprecated_read_memory_nobpt (addr
, buf
, instlen
);
1006 memory_error (status
, addr
);
1007 return extract_unsigned_integer (buf
, instlen
);
1010 /* These the fields of 32 bit mips instructions */
1011 #define mips32_op(x) (x >> 26)
1012 #define itype_op(x) (x >> 26)
1013 #define itype_rs(x) ((x >> 21) & 0x1f)
1014 #define itype_rt(x) ((x >> 16) & 0x1f)
1015 #define itype_immediate(x) (x & 0xffff)
1017 #define jtype_op(x) (x >> 26)
1018 #define jtype_target(x) (x & 0x03ffffff)
1020 #define rtype_op(x) (x >> 26)
1021 #define rtype_rs(x) ((x >> 21) & 0x1f)
1022 #define rtype_rt(x) ((x >> 16) & 0x1f)
1023 #define rtype_rd(x) ((x >> 11) & 0x1f)
1024 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1025 #define rtype_funct(x) (x & 0x3f)
1028 mips32_relative_offset (unsigned long inst
)
1031 x
= itype_immediate (inst
);
1032 if (x
& 0x8000) /* sign bit set */
1034 x
|= 0xffff0000; /* sign extension */
1040 /* Determine whate to set a single step breakpoint while considering
1041 branch prediction */
1043 mips32_next_pc (CORE_ADDR pc
)
1047 inst
= mips_fetch_instruction (pc
);
1048 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch instruction */
1050 if (itype_op (inst
) >> 2 == 5)
1051 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1053 op
= (itype_op (inst
) & 0x03);
1063 goto greater_branch
;
1068 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
1069 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1071 int tf
= itype_rt (inst
) & 0x01;
1072 int cnum
= itype_rt (inst
) >> 2;
1074 read_signed_register (mips_regnum (current_gdbarch
)->
1076 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
1078 if (((cond
>> cnum
) & 0x01) == tf
)
1079 pc
+= mips32_relative_offset (inst
) + 4;
1084 pc
+= 4; /* Not a branch, next instruction is easy */
1087 { /* This gets way messy */
1089 /* Further subdivide into SPECIAL, REGIMM and other */
1090 switch (op
= itype_op (inst
) & 0x07) /* extract bits 28,27,26 */
1092 case 0: /* SPECIAL */
1093 op
= rtype_funct (inst
);
1098 /* Set PC to that address */
1099 pc
= read_signed_register (rtype_rs (inst
));
1105 break; /* end SPECIAL */
1106 case 1: /* REGIMM */
1108 op
= itype_rt (inst
); /* branch condition */
1113 case 16: /* BLTZAL */
1114 case 18: /* BLTZALL */
1116 if (read_signed_register (itype_rs (inst
)) < 0)
1117 pc
+= mips32_relative_offset (inst
) + 4;
1119 pc
+= 8; /* after the delay slot */
1123 case 17: /* BGEZAL */
1124 case 19: /* BGEZALL */
1125 if (read_signed_register (itype_rs (inst
)) >= 0)
1126 pc
+= mips32_relative_offset (inst
) + 4;
1128 pc
+= 8; /* after the delay slot */
1130 /* All of the other instructions in the REGIMM category */
1135 break; /* end REGIMM */
1140 reg
= jtype_target (inst
) << 2;
1141 /* Upper four bits get never changed... */
1142 pc
= reg
+ ((pc
+ 4) & 0xf0000000);
1145 /* FIXME case JALX : */
1148 reg
= jtype_target (inst
) << 2;
1149 pc
= reg
+ ((pc
+ 4) & 0xf0000000) + 1; /* yes, +1 */
1150 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1152 break; /* The new PC will be alternate mode */
1153 case 4: /* BEQ, BEQL */
1155 if (read_signed_register (itype_rs (inst
)) ==
1156 read_signed_register (itype_rt (inst
)))
1157 pc
+= mips32_relative_offset (inst
) + 4;
1161 case 5: /* BNE, BNEL */
1163 if (read_signed_register (itype_rs (inst
)) !=
1164 read_signed_register (itype_rt (inst
)))
1165 pc
+= mips32_relative_offset (inst
) + 4;
1169 case 6: /* BLEZ, BLEZL */
1170 if (read_signed_register (itype_rs (inst
) <= 0))
1171 pc
+= mips32_relative_offset (inst
) + 4;
1177 greater_branch
: /* BGTZ, BGTZL */
1178 if (read_signed_register (itype_rs (inst
) > 0))
1179 pc
+= mips32_relative_offset (inst
) + 4;
1186 } /* mips32_next_pc */
1188 /* Decoding the next place to set a breakpoint is irregular for the
1189 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1190 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1191 We dont want to set a single step instruction on the extend instruction
1195 /* Lots of mips16 instruction formats */
1196 /* Predicting jumps requires itype,ritype,i8type
1197 and their extensions extItype,extritype,extI8type
1199 enum mips16_inst_fmts
1201 itype
, /* 0 immediate 5,10 */
1202 ritype
, /* 1 5,3,8 */
1203 rrtype
, /* 2 5,3,3,5 */
1204 rritype
, /* 3 5,3,3,5 */
1205 rrrtype
, /* 4 5,3,3,3,2 */
1206 rriatype
, /* 5 5,3,3,1,4 */
1207 shifttype
, /* 6 5,3,3,3,2 */
1208 i8type
, /* 7 5,3,8 */
1209 i8movtype
, /* 8 5,3,3,5 */
1210 i8mov32rtype
, /* 9 5,3,5,3 */
1211 i64type
, /* 10 5,3,8 */
1212 ri64type
, /* 11 5,3,3,5 */
1213 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1214 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1215 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1216 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1217 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1218 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1219 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1220 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1221 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1222 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1224 /* I am heaping all the fields of the formats into one structure and
1225 then, only the fields which are involved in instruction extension */
1229 unsigned int regx
; /* Function in i8 type */
1234 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1235 for the bits which make up the immediatate extension. */
1238 extended_offset (unsigned int extension
)
1241 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
1243 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
1245 value
|= extension
& 0x01f; /* extract 4:0 */
1249 /* Only call this function if you know that this is an extendable
1250 instruction, It wont malfunction, but why make excess remote memory references?
1251 If the immediate operands get sign extended or somthing, do it after
1252 the extension is performed.
1254 /* FIXME: Every one of these cases needs to worry about sign extension
1255 when the offset is to be used in relative addressing */
1259 fetch_mips_16 (CORE_ADDR pc
)
1262 pc
&= 0xfffffffe; /* clear the low order bit */
1263 target_read_memory (pc
, buf
, 2);
1264 return extract_unsigned_integer (buf
, 2);
1268 unpack_mips16 (CORE_ADDR pc
,
1269 unsigned int extension
,
1271 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
1276 switch (insn_format
)
1283 value
= extended_offset (extension
);
1284 value
= value
<< 11; /* rom for the original value */
1285 value
|= inst
& 0x7ff; /* eleven bits from instruction */
1289 value
= inst
& 0x7ff;
1290 /* FIXME : Consider sign extension */
1299 { /* A register identifier and an offset */
1300 /* Most of the fields are the same as I type but the
1301 immediate value is of a different length */
1305 value
= extended_offset (extension
);
1306 value
= value
<< 8; /* from the original instruction */
1307 value
|= inst
& 0xff; /* eleven bits from instruction */
1308 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
1309 if (value
& 0x4000) /* test the sign bit , bit 26 */
1311 value
&= ~0x3fff; /* remove the sign bit */
1317 value
= inst
& 0xff; /* 8 bits */
1318 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
1319 /* FIXME: Do sign extension , this format needs it */
1320 if (value
& 0x80) /* THIS CONFUSES ME */
1322 value
&= 0xef; /* remove the sign bit */
1332 unsigned long value
;
1333 unsigned int nexthalf
;
1334 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1335 value
= value
<< 16;
1336 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
1344 internal_error (__FILE__
, __LINE__
, "bad switch");
1346 upk
->offset
= offset
;
1353 add_offset_16 (CORE_ADDR pc
, int offset
)
1355 return ((offset
<< 2) | ((pc
+ 2) & (0xf0000000)));
1359 extended_mips16_next_pc (CORE_ADDR pc
,
1360 unsigned int extension
, unsigned int insn
)
1362 int op
= (insn
>> 11);
1365 case 2: /* Branch */
1368 struct upk_mips16 upk
;
1369 unpack_mips16 (pc
, extension
, insn
, itype
, &upk
);
1370 offset
= upk
.offset
;
1376 pc
+= (offset
<< 1) + 2;
1379 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1381 struct upk_mips16 upk
;
1382 unpack_mips16 (pc
, extension
, insn
, jalxtype
, &upk
);
1383 pc
= add_offset_16 (pc
, upk
.offset
);
1384 if ((insn
>> 10) & 0x01) /* Exchange mode */
1385 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1392 struct upk_mips16 upk
;
1394 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1395 reg
= read_signed_register (upk
.regx
);
1397 pc
+= (upk
.offset
<< 1) + 2;
1404 struct upk_mips16 upk
;
1406 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1407 reg
= read_signed_register (upk
.regx
);
1409 pc
+= (upk
.offset
<< 1) + 2;
1414 case 12: /* I8 Formats btez btnez */
1416 struct upk_mips16 upk
;
1418 unpack_mips16 (pc
, extension
, insn
, i8type
, &upk
);
1419 /* upk.regx contains the opcode */
1420 reg
= read_signed_register (24); /* Test register is 24 */
1421 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1422 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1423 /* pc = add_offset_16(pc,upk.offset) ; */
1424 pc
+= (upk
.offset
<< 1) + 2;
1429 case 29: /* RR Formats JR, JALR, JALR-RA */
1431 struct upk_mips16 upk
;
1432 /* upk.fmt = rrtype; */
1437 upk
.regx
= (insn
>> 8) & 0x07;
1438 upk
.regy
= (insn
>> 5) & 0x07;
1446 break; /* Function return instruction */
1452 break; /* BOGUS Guess */
1454 pc
= read_signed_register (reg
);
1461 /* This is an instruction extension. Fetch the real instruction
1462 (which follows the extension) and decode things based on
1466 pc
= extended_mips16_next_pc (pc
, insn
, fetch_mips_16 (pc
));
1479 mips16_next_pc (CORE_ADDR pc
)
1481 unsigned int insn
= fetch_mips_16 (pc
);
1482 return extended_mips16_next_pc (pc
, 0, insn
);
1485 /* The mips_next_pc function supports single_step when the remote
1486 target monitor or stub is not developed enough to do a single_step.
1487 It works by decoding the current instruction and predicting where a
1488 branch will go. This isnt hard because all the data is available.
1489 The MIPS32 and MIPS16 variants are quite different */
1491 mips_next_pc (CORE_ADDR pc
)
1494 return mips16_next_pc (pc
);
1496 return mips32_next_pc (pc
);
1499 struct mips_frame_cache
1502 struct trad_frame_saved_reg
*saved_regs
;
1506 static struct mips_frame_cache
*
1507 mips_mdebug_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1509 CORE_ADDR startaddr
= 0;
1510 mips_extra_func_info_t proc_desc
;
1511 struct mips_frame_cache
*cache
;
1512 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
1513 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1514 /* r0 bit means kernel trap */
1516 /* What registers have been saved? Bitmasks. */
1517 unsigned long gen_mask
, float_mask
;
1519 if ((*this_cache
) != NULL
)
1520 return (*this_cache
);
1521 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1522 (*this_cache
) = cache
;
1523 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1525 /* Get the mdebug proc descriptor. */
1526 proc_desc
= non_heuristic_proc_desc (frame_pc_unwind (next_frame
),
1528 /* Must be true. This is only called when the sniffer detected a
1530 gdb_assert (proc_desc
!= NULL
);
1532 /* Extract the frame's base. */
1533 cache
->base
= (frame_unwind_register_signed (next_frame
, NUM_REGS
+ PROC_FRAME_REG (proc_desc
))
1534 + PROC_FRAME_OFFSET (proc_desc
) - PROC_FRAME_ADJUST (proc_desc
));
1536 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1537 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
1538 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
1540 /* Must be true. The in_prologue case is left for the heuristic
1541 unwinder. This is always used on kernel traps. */
1542 gdb_assert (!in_prologue (frame_pc_unwind (next_frame
), PROC_LOW_ADDR (proc_desc
))
1545 /* Fill in the offsets for the registers which gen_mask says were
1548 CORE_ADDR reg_position
= (cache
->base
+ PROC_REG_OFFSET (proc_desc
));
1551 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
1552 if (gen_mask
& 0x80000000)
1554 cache
->saved_regs
[NUM_REGS
+ ireg
].addr
= reg_position
;
1555 reg_position
-= mips_abi_regsize (gdbarch
);
1559 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse
1560 order of that normally used by gcc. Therefore, we have to fetch
1561 the first instruction of the function, and if it's an entry
1562 instruction that saves $s0 or $s1, correct their saved addresses. */
1563 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
1565 ULONGEST inst
= mips16_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
1566 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700)
1570 int sreg_count
= (inst
>> 6) & 3;
1572 /* Check if the ra register was pushed on the stack. */
1573 CORE_ADDR reg_position
= (cache
->base
1574 + PROC_REG_OFFSET (proc_desc
));
1576 reg_position
-= mips_abi_regsize (gdbarch
);
1578 /* Check if the s0 and s1 registers were pushed on the
1580 /* NOTE: cagney/2004-02-08: Huh? This is doing no such
1582 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1584 cache
->saved_regs
[NUM_REGS
+ reg
].addr
= reg_position
;
1585 reg_position
-= mips_abi_regsize (gdbarch
);
1590 /* Fill in the offsets for the registers which float_mask says were
1593 CORE_ADDR reg_position
= (cache
->base
1594 + PROC_FREG_OFFSET (proc_desc
));
1596 /* Fill in the offsets for the float registers which float_mask
1598 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
1599 if (float_mask
& 0x80000000)
1601 if (mips_abi_regsize (gdbarch
) == 4
1602 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1604 /* On a big endian 32 bit ABI, floating point registers
1605 are paired to form doubles such that the most
1606 significant part is in $f[N+1] and the least
1607 significant in $f[N] vis: $f[N+1] ||| $f[N]. The
1608 registers are also spilled as a pair and stored as a
1611 When little-endian the least significant part is
1612 stored first leading to the memory order $f[N] and
1615 Unfortunately, when big-endian the most significant
1616 part of the double is stored first, and the least
1617 significant is stored second. This leads to the
1618 registers being ordered in memory as firt $f[N+1] and
1621 For the big-endian case make certain that the
1622 addresses point at the correct (swapped) locations
1623 $f[N] and $f[N+1] pair (keep in mind that
1624 reg_position is decremented each time through the
1627 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1628 .addr
= reg_position
- mips_abi_regsize (gdbarch
);
1630 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1631 .addr
= reg_position
+ mips_abi_regsize (gdbarch
);
1634 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1635 .addr
= reg_position
;
1636 reg_position
-= mips_abi_regsize (gdbarch
);
1639 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->pc
]
1640 = cache
->saved_regs
[NUM_REGS
+ RA_REGNUM
];
1643 /* SP_REGNUM, contains the value and not the address. */
1644 trad_frame_set_value (cache
->saved_regs
, NUM_REGS
+ MIPS_SP_REGNUM
, cache
->base
);
1646 return (*this_cache
);
1650 mips_mdebug_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
1651 struct frame_id
*this_id
)
1653 struct mips_frame_cache
*info
= mips_mdebug_frame_cache (next_frame
,
1655 (*this_id
) = frame_id_build (info
->base
, frame_func_unwind (next_frame
));
1659 mips_mdebug_frame_prev_register (struct frame_info
*next_frame
,
1661 int regnum
, int *optimizedp
,
1662 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1663 int *realnump
, void *valuep
)
1665 struct mips_frame_cache
*info
= mips_mdebug_frame_cache (next_frame
,
1667 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
1668 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
1671 static const struct frame_unwind mips_mdebug_frame_unwind
=
1674 mips_mdebug_frame_this_id
,
1675 mips_mdebug_frame_prev_register
1678 static const struct frame_unwind
*
1679 mips_mdebug_frame_sniffer (struct frame_info
*next_frame
)
1681 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1682 CORE_ADDR startaddr
= 0;
1683 mips_extra_func_info_t proc_desc
;
1686 /* Only use the mdebug frame unwinder on mdebug frames where all the
1687 registers have been saved. Leave hard cases such as no mdebug or
1688 in prologue for the heuristic unwinders. */
1690 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
1691 if (proc_desc
== NULL
)
1694 /* Not sure exactly what kernel_trap means, but if it means the
1695 kernel saves the registers without a prologue doing it, we better
1696 not examine the prologue to see whether registers have been saved
1698 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1700 return &mips_mdebug_frame_unwind
;
1702 /* In any frame other than the innermost or a frame interrupted by a
1703 signal, we assume that all registers have been saved. This
1704 assumes that all register saves in a function happen before the
1705 first function call. */
1706 if (!in_prologue (pc
, PROC_LOW_ADDR (proc_desc
)))
1707 return &mips_mdebug_frame_unwind
;
1713 mips_mdebug_frame_base_address (struct frame_info
*next_frame
,
1716 struct mips_frame_cache
*info
= mips_mdebug_frame_cache (next_frame
,
1721 static const struct frame_base mips_mdebug_frame_base
= {
1722 &mips_mdebug_frame_unwind
,
1723 mips_mdebug_frame_base_address
,
1724 mips_mdebug_frame_base_address
,
1725 mips_mdebug_frame_base_address
1728 static const struct frame_base
*
1729 mips_mdebug_frame_base_sniffer (struct frame_info
*next_frame
)
1731 if (mips_mdebug_frame_sniffer (next_frame
) != NULL
)
1732 return &mips_mdebug_frame_base
;
1737 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
1738 Procedures that use the 32-bit instruction set are handled by the
1739 mips_insn32 unwinder. */
1741 static struct mips_frame_cache
*
1742 mips_insn16_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1744 mips_extra_func_info_t proc_desc
;
1745 struct mips_frame_cache
*cache
;
1746 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
1747 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1748 /* r0 bit means kernel trap */
1750 /* What registers have been saved? Bitmasks. */
1751 unsigned long gen_mask
, float_mask
;
1753 if ((*this_cache
) != NULL
)
1754 return (*this_cache
);
1755 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1756 (*this_cache
) = cache
;
1757 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1759 /* Synthesize a proc descriptor. */
1761 const CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1762 CORE_ADDR start_addr
;
1764 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
1765 if (start_addr
== 0)
1766 start_addr
= heuristic_proc_start (pc
);
1769 proc_desc
= heuristic_proc_desc (start_addr
, pc
, next_frame
, *this_cache
);
1771 proc_desc
= heuristic_proc_desc (start_addr
, pc
, next_frame
, NULL
);
1775 /* Extract the frame's base. */
1776 cache
->base
= (frame_unwind_register_signed (next_frame
, NUM_REGS
+ PROC_FRAME_REG (proc_desc
))
1777 + PROC_FRAME_OFFSET (proc_desc
) - PROC_FRAME_ADJUST (proc_desc
));
1779 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1780 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
1781 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
1783 /* In any frame other than the innermost or a frame interrupted by a
1784 signal, we assume that all registers have been saved. This
1785 assumes that all register saves in a function happen before the
1786 first function call. */
1787 if (in_prologue (frame_pc_unwind (next_frame
), PROC_LOW_ADDR (proc_desc
))
1788 /* Not sure exactly what kernel_trap means, but if it means the
1789 kernel saves the registers without a prologue doing it, we
1790 better not examine the prologue to see whether registers
1791 have been saved yet. */
1794 /* We need to figure out whether the registers that the
1795 proc_desc claims are saved have been saved yet. */
1799 /* Bitmasks; set if we have found a save for the register. */
1800 unsigned long gen_save_found
= 0;
1801 unsigned long float_save_found
= 0;
1804 /* If the address is odd, assume this is MIPS16 code. */
1805 addr
= PROC_LOW_ADDR (proc_desc
);
1807 /* Scan through this function's instructions preceding the
1808 current PC, and look for those that save registers. */
1809 while (addr
< frame_pc_unwind (next_frame
))
1811 mips16_decode_reg_save (mips16_fetch_instruction (addr
),
1813 addr
+= MIPS16_INSTLEN
;
1815 gen_mask
= gen_save_found
;
1816 float_mask
= float_save_found
;
1819 /* Fill in the offsets for the registers which gen_mask says were
1822 CORE_ADDR reg_position
= (cache
->base
1823 + PROC_REG_OFFSET (proc_desc
));
1825 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
1826 if (gen_mask
& 0x80000000)
1828 cache
->saved_regs
[NUM_REGS
+ ireg
].addr
= reg_position
;
1829 reg_position
-= mips_abi_regsize (gdbarch
);
1833 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse
1834 order of that normally used by gcc. Therefore, we have to fetch
1835 the first instruction of the function, and if it's an entry
1836 instruction that saves $s0 or $s1, correct their saved addresses. */
1838 ULONGEST inst
= mips16_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
1839 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700)
1843 int sreg_count
= (inst
>> 6) & 3;
1845 /* Check if the ra register was pushed on the stack. */
1846 CORE_ADDR reg_position
= (cache
->base
1847 + PROC_REG_OFFSET (proc_desc
));
1849 reg_position
-= mips_abi_regsize (gdbarch
);
1851 /* Check if the s0 and s1 registers were pushed on the
1853 /* NOTE: cagney/2004-02-08: Huh? This is doing no such
1855 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1857 cache
->saved_regs
[NUM_REGS
+ reg
].addr
= reg_position
;
1858 reg_position
-= mips_abi_regsize (gdbarch
);
1863 /* Fill in the offsets for the registers which float_mask says were
1866 CORE_ADDR reg_position
= (cache
->base
1867 + PROC_FREG_OFFSET (proc_desc
));
1869 /* Fill in the offsets for the float registers which float_mask
1871 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
1872 if (float_mask
& 0x80000000)
1874 if (mips_abi_regsize (gdbarch
) == 4
1875 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1877 /* On a big endian 32 bit ABI, floating point registers
1878 are paired to form doubles such that the most
1879 significant part is in $f[N+1] and the least
1880 significant in $f[N] vis: $f[N+1] ||| $f[N]. The
1881 registers are also spilled as a pair and stored as a
1884 When little-endian the least significant part is
1885 stored first leading to the memory order $f[N] and
1888 Unfortunately, when big-endian the most significant
1889 part of the double is stored first, and the least
1890 significant is stored second. This leads to the
1891 registers being ordered in memory as firt $f[N+1] and
1894 For the big-endian case make certain that the
1895 addresses point at the correct (swapped) locations
1896 $f[N] and $f[N+1] pair (keep in mind that
1897 reg_position is decremented each time through the
1900 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1901 .addr
= reg_position
- mips_abi_regsize (gdbarch
);
1903 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1904 .addr
= reg_position
+ mips_abi_regsize (gdbarch
);
1907 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1908 .addr
= reg_position
;
1909 reg_position
-= mips_abi_regsize (gdbarch
);
1912 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->pc
]
1913 = cache
->saved_regs
[NUM_REGS
+ RA_REGNUM
];
1916 /* SP_REGNUM, contains the value and not the address. */
1917 trad_frame_set_value (cache
->saved_regs
, NUM_REGS
+ MIPS_SP_REGNUM
, cache
->base
);
1919 return (*this_cache
);
1923 mips_insn16_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
1924 struct frame_id
*this_id
)
1926 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1928 (*this_id
) = frame_id_build (info
->base
, frame_func_unwind (next_frame
));
1932 mips_insn16_frame_prev_register (struct frame_info
*next_frame
,
1934 int regnum
, int *optimizedp
,
1935 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1936 int *realnump
, void *valuep
)
1938 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1940 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
1941 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
1944 static const struct frame_unwind mips_insn16_frame_unwind
=
1947 mips_insn16_frame_this_id
,
1948 mips_insn16_frame_prev_register
1951 static const struct frame_unwind
*
1952 mips_insn16_frame_sniffer (struct frame_info
*next_frame
)
1954 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1955 if (pc_is_mips16 (pc
))
1956 return &mips_insn16_frame_unwind
;
1961 mips_insn16_frame_base_address (struct frame_info
*next_frame
,
1964 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1969 static const struct frame_base mips_insn16_frame_base
=
1971 &mips_insn16_frame_unwind
,
1972 mips_insn16_frame_base_address
,
1973 mips_insn16_frame_base_address
,
1974 mips_insn16_frame_base_address
1977 static const struct frame_base
*
1978 mips_insn16_frame_base_sniffer (struct frame_info
*next_frame
)
1980 if (mips_insn16_frame_sniffer (next_frame
) != NULL
)
1981 return &mips_insn16_frame_base
;
1986 /* Heuristic unwinder for procedures using 32-bit instructions (covers
1987 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
1988 instructions (a.k.a. MIPS16) are handled by the mips_insn16
1991 static struct mips_frame_cache
*
1992 mips_insn32_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1994 mips_extra_func_info_t proc_desc
;
1995 struct mips_frame_cache
*cache
;
1996 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
1997 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1998 /* r0 bit means kernel trap */
2000 /* What registers have been saved? Bitmasks. */
2001 unsigned long gen_mask
, float_mask
;
2003 if ((*this_cache
) != NULL
)
2004 return (*this_cache
);
2006 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2007 (*this_cache
) = cache
;
2008 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
2010 /* Synthesize a proc descriptor. */
2012 const CORE_ADDR pc
= frame_pc_unwind (next_frame
);
2013 CORE_ADDR start_addr
;
2015 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2016 if (start_addr
== 0)
2017 start_addr
= heuristic_proc_start (pc
);
2019 proc_desc
= heuristic_proc_desc (start_addr
, pc
, next_frame
, *this_cache
);
2022 if (proc_desc
== NULL
)
2023 /* I'm not sure how/whether this can happen. Normally when we
2024 can't find a proc_desc, we "synthesize" one using
2025 heuristic_proc_desc and set the saved_regs right away. */
2028 /* SP_REGNUM, contains the value and not the address. */
2029 trad_frame_set_value (cache
->saved_regs
, NUM_REGS
+ MIPS_SP_REGNUM
, cache
->base
);
2031 return (*this_cache
);
2035 mips_insn32_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
2036 struct frame_id
*this_id
)
2038 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2040 (*this_id
) = frame_id_build (info
->base
, frame_func_unwind (next_frame
));
2044 mips_insn32_frame_prev_register (struct frame_info
*next_frame
,
2046 int regnum
, int *optimizedp
,
2047 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
2048 int *realnump
, void *valuep
)
2050 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2052 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
2053 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
2056 static const struct frame_unwind mips_insn32_frame_unwind
=
2059 mips_insn32_frame_this_id
,
2060 mips_insn32_frame_prev_register
2063 static const struct frame_unwind
*
2064 mips_insn32_frame_sniffer (struct frame_info
*next_frame
)
2066 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
2067 if (! pc_is_mips16 (pc
))
2068 return &mips_insn32_frame_unwind
;
2073 mips_insn32_frame_base_address (struct frame_info
*next_frame
,
2076 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2081 static const struct frame_base mips_insn32_frame_base
=
2083 &mips_insn32_frame_unwind
,
2084 mips_insn32_frame_base_address
,
2085 mips_insn32_frame_base_address
,
2086 mips_insn32_frame_base_address
2089 static const struct frame_base
*
2090 mips_insn32_frame_base_sniffer (struct frame_info
*next_frame
)
2092 if (mips_insn32_frame_sniffer (next_frame
) != NULL
)
2093 return &mips_insn32_frame_base
;
2098 static struct trad_frame_cache
*
2099 mips_stub_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
2102 CORE_ADDR start_addr
;
2103 CORE_ADDR stack_addr
;
2104 struct trad_frame_cache
*this_trad_cache
;
2106 if ((*this_cache
) != NULL
)
2107 return (*this_cache
);
2108 this_trad_cache
= trad_frame_cache_zalloc (next_frame
);
2109 (*this_cache
) = this_trad_cache
;
2111 /* The return address is in the link register. */
2112 trad_frame_set_reg_realreg (this_trad_cache
, PC_REGNUM
, RA_REGNUM
);
2114 /* Frame ID, since it's a frameless / stackless function, no stack
2115 space is allocated and SP on entry is the current SP. */
2116 pc
= frame_pc_unwind (next_frame
);
2117 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2118 stack_addr
= frame_unwind_register_signed (next_frame
, SP_REGNUM
);
2119 trad_frame_set_id (this_trad_cache
, frame_id_build (start_addr
, stack_addr
));
2121 /* Assume that the frame's base is the same as the
2123 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
2125 return this_trad_cache
;
2129 mips_stub_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
2130 struct frame_id
*this_id
)
2132 struct trad_frame_cache
*this_trad_cache
2133 = mips_stub_frame_cache (next_frame
, this_cache
);
2134 trad_frame_get_id (this_trad_cache
, this_id
);
2138 mips_stub_frame_prev_register (struct frame_info
*next_frame
,
2140 int regnum
, int *optimizedp
,
2141 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
2142 int *realnump
, void *valuep
)
2144 struct trad_frame_cache
*this_trad_cache
2145 = mips_stub_frame_cache (next_frame
, this_cache
);
2146 trad_frame_get_register (this_trad_cache
, next_frame
, regnum
, optimizedp
,
2147 lvalp
, addrp
, realnump
, valuep
);
2150 static const struct frame_unwind mips_stub_frame_unwind
=
2153 mips_stub_frame_this_id
,
2154 mips_stub_frame_prev_register
2157 static const struct frame_unwind
*
2158 mips_stub_frame_sniffer (struct frame_info
*next_frame
)
2160 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
2161 if (in_plt_section (pc
, NULL
))
2162 return &mips_stub_frame_unwind
;
2168 mips_stub_frame_base_address (struct frame_info
*next_frame
,
2171 struct trad_frame_cache
*this_trad_cache
2172 = mips_stub_frame_cache (next_frame
, this_cache
);
2173 return trad_frame_get_this_base (this_trad_cache
);
2176 static const struct frame_base mips_stub_frame_base
=
2178 &mips_stub_frame_unwind
,
2179 mips_stub_frame_base_address
,
2180 mips_stub_frame_base_address
,
2181 mips_stub_frame_base_address
2184 static const struct frame_base
*
2185 mips_stub_frame_base_sniffer (struct frame_info
*next_frame
)
2187 if (mips_stub_frame_sniffer (next_frame
) != NULL
)
2188 return &mips_stub_frame_base
;
2194 read_next_frame_reg (struct frame_info
*fi
, int regno
)
2196 /* Always a pseudo. */
2197 gdb_assert (regno
>= NUM_REGS
);
2201 regcache_cooked_read_signed (current_regcache
, regno
, &val
);
2205 return frame_unwind_register_signed (fi
, regno
);
2209 /* mips_addr_bits_remove - remove useless address bits */
2212 mips_addr_bits_remove (CORE_ADDR addr
)
2214 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2215 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
2216 /* This hack is a work-around for existing boards using PMON, the
2217 simulator, and any other 64-bit targets that doesn't have true
2218 64-bit addressing. On these targets, the upper 32 bits of
2219 addresses are ignored by the hardware. Thus, the PC or SP are
2220 likely to have been sign extended to all 1s by instruction
2221 sequences that load 32-bit addresses. For example, a typical
2222 piece of code that loads an address is this:
2224 lui $r2, <upper 16 bits>
2225 ori $r2, <lower 16 bits>
2227 But the lui sign-extends the value such that the upper 32 bits
2228 may be all 1s. The workaround is simply to mask off these
2229 bits. In the future, gcc may be changed to support true 64-bit
2230 addressing, and this masking will have to be disabled. */
2231 return addr
&= 0xffffffffUL
;
2236 /* mips_software_single_step() is called just before we want to resume
2237 the inferior, if we want to single-step it but there is no hardware
2238 or kernel single-step support (MIPS on GNU/Linux for example). We find
2239 the target of the coming instruction and breakpoint it.
2241 single_step is also called just after the inferior stops. If we had
2242 set up a simulated single-step, we undo our damage. */
2245 mips_software_single_step (enum target_signal sig
, int insert_breakpoints_p
)
2247 static CORE_ADDR next_pc
;
2248 typedef char binsn_quantum
[BREAKPOINT_MAX
];
2249 static binsn_quantum break_mem
;
2252 if (insert_breakpoints_p
)
2254 pc
= read_register (mips_regnum (current_gdbarch
)->pc
);
2255 next_pc
= mips_next_pc (pc
);
2257 target_insert_breakpoint (next_pc
, break_mem
);
2260 target_remove_breakpoint (next_pc
, break_mem
);
2263 static struct mips_extra_func_info temp_proc_desc
;
2265 /* Set a register's saved stack address in temp_saved_regs. If an
2266 address has already been set for this register, do nothing; this
2267 way we will only recognize the first save of a given register in a
2270 For simplicity, save the address in both [0 .. NUM_REGS) and
2271 [NUM_REGS .. 2*NUM_REGS). Strictly speaking, only the second range
2272 is used as it is only second range (the ABI instead of ISA
2273 registers) that comes into play when finding saved registers in a
2277 set_reg_offset (struct mips_frame_cache
*this_cache
, int regnum
,
2280 if (this_cache
!= NULL
2281 && this_cache
->saved_regs
[regnum
].addr
== -1)
2283 this_cache
->saved_regs
[regnum
+ 0 * NUM_REGS
].addr
= offset
;
2284 this_cache
->saved_regs
[regnum
+ 1 * NUM_REGS
].addr
= offset
;
2289 /* Test whether the PC points to the return instruction at the
2290 end of a function. */
2293 mips_about_to_return (CORE_ADDR pc
)
2295 if (pc_is_mips16 (pc
))
2296 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
2297 generates a "jr $ra"; other times it generates code to load
2298 the return address from the stack to an accessible register (such
2299 as $a3), then a "jr" using that register. This second case
2300 is almost impossible to distinguish from an indirect jump
2301 used for switch statements, so we don't even try. */
2302 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
2304 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
2308 /* This fencepost looks highly suspicious to me. Removing it also
2309 seems suspicious as it could affect remote debugging across serial
2313 heuristic_proc_start (CORE_ADDR pc
)
2320 pc
= ADDR_BITS_REMOVE (pc
);
2322 fence
= start_pc
- heuristic_fence_post
;
2326 if (heuristic_fence_post
== UINT_MAX
|| fence
< VM_MIN_ADDRESS
)
2327 fence
= VM_MIN_ADDRESS
;
2329 instlen
= pc_is_mips16 (pc
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
2331 /* search back for previous return */
2332 for (start_pc
-= instlen
;; start_pc
-= instlen
)
2333 if (start_pc
< fence
)
2335 /* It's not clear to me why we reach this point when
2336 stop_soon, but with this test, at least we
2337 don't print out warnings for every child forked (eg, on
2338 decstation). 22apr93 rich@cygnus.com. */
2339 if (stop_soon
== NO_STOP_QUIETLY
)
2341 static int blurb_printed
= 0;
2343 warning ("GDB can't find the start of the function at 0x%s.",
2348 /* This actually happens frequently in embedded
2349 development, when you first connect to a board
2350 and your stack pointer and pc are nowhere in
2351 particular. This message needs to give people
2352 in that situation enough information to
2353 determine that it's no big deal. */
2354 printf_filtered ("\n\
2355 GDB is unable to find the start of the function at 0x%s\n\
2356 and thus can't determine the size of that function's stack frame.\n\
2357 This means that GDB may be unable to access that stack frame, or\n\
2358 the frames below it.\n\
2359 This problem is most likely caused by an invalid program counter or\n\
2361 However, if you think GDB should simply search farther back\n\
2362 from 0x%s for code which looks like the beginning of a\n\
2363 function, you can increase the range of the search using the `set\n\
2364 heuristic-fence-post' command.\n", paddr_nz (pc
), paddr_nz (pc
));
2371 else if (pc_is_mips16 (start_pc
))
2373 unsigned short inst
;
2375 /* On MIPS16, any one of the following is likely to be the
2376 start of a function:
2380 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
2381 inst
= mips_fetch_instruction (start_pc
);
2382 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
2383 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
2384 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
2385 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
2387 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2388 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2393 else if (mips_about_to_return (start_pc
))
2395 start_pc
+= 2 * MIPS_INSTLEN
; /* skip return, and its delay slot */
2402 /* Fetch the immediate value from a MIPS16 instruction.
2403 If the previous instruction was an EXTEND, use it to extend
2404 the upper bits of the immediate value. This is a helper function
2405 for mips16_heuristic_proc_desc. */
2408 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
2409 unsigned short inst
, /* current instruction */
2410 int nbits
, /* number of bits in imm field */
2411 int scale
, /* scale factor to be applied to imm */
2412 int is_signed
) /* is the imm field signed? */
2416 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
2418 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
2419 if (offset
& 0x8000) /* check for negative extend */
2420 offset
= 0 - (0x10000 - (offset
& 0xffff));
2421 return offset
| (inst
& 0x1f);
2425 int max_imm
= 1 << nbits
;
2426 int mask
= max_imm
- 1;
2427 int sign_bit
= max_imm
>> 1;
2429 offset
= inst
& mask
;
2430 if (is_signed
&& (offset
& sign_bit
))
2431 offset
= 0 - (max_imm
- offset
);
2432 return offset
* scale
;
2437 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
2438 stream from start_pc to limit_pc. */
2441 mips16_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2443 struct frame_info
*next_frame
,
2444 struct mips_frame_cache
*this_cache
)
2447 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
2448 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
2449 unsigned inst
= 0; /* current instruction */
2450 unsigned entry_inst
= 0; /* the entry instruction */
2452 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2454 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0; /* size of stack frame */
2455 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
2457 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS16_INSTLEN
)
2459 /* Save the previous instruction. If it's an EXTEND, we'll extract
2460 the immediate offset extension from it in mips16_get_imm. */
2463 /* Fetch and decode the instruction. */
2464 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
2465 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2466 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2468 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
2469 if (offset
< 0) /* negative stack adjustment? */
2470 PROC_FRAME_OFFSET (&temp_proc_desc
) -= offset
;
2472 /* Exit loop if a positive stack adjustment is found, which
2473 usually means that the stack cleanup code in the function
2474 epilogue is reached. */
2477 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
2479 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2480 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
2481 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
2482 set_reg_offset (this_cache
, reg
, sp
+ offset
);
2484 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
2486 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2487 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2488 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
2489 set_reg_offset (this_cache
, reg
, sp
+ offset
);
2491 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
2493 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2494 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
2495 set_reg_offset (this_cache
, RA_REGNUM
, sp
+ offset
);
2497 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
2499 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
2500 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
2501 set_reg_offset (this_cache
, RA_REGNUM
, sp
+ offset
);
2503 else if (inst
== 0x673d) /* move $s1, $sp */
2506 PROC_FRAME_REG (&temp_proc_desc
) = 17;
2508 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
2510 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2511 frame_addr
= sp
+ offset
;
2512 PROC_FRAME_REG (&temp_proc_desc
) = 17;
2513 PROC_FRAME_ADJUST (&temp_proc_desc
) = offset
;
2515 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
2517 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
2518 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2519 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2520 set_reg_offset (this_cache
, reg
, frame_addr
+ offset
);
2522 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
2524 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2525 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2526 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2527 set_reg_offset (this_cache
, reg
, frame_addr
+ offset
);
2529 else if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
2530 entry_inst
= inst
; /* save for later processing */
2531 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
2532 cur_pc
+= MIPS16_INSTLEN
; /* 32-bit instruction */
2535 /* The entry instruction is typically the first instruction in a function,
2536 and it stores registers at offsets relative to the value of the old SP
2537 (before the prologue). But the value of the sp parameter to this
2538 function is the new SP (after the prologue has been executed). So we
2539 can't calculate those offsets until we've seen the entire prologue,
2540 and can calculate what the old SP must have been. */
2541 if (entry_inst
!= 0)
2543 int areg_count
= (entry_inst
>> 8) & 7;
2544 int sreg_count
= (entry_inst
>> 6) & 3;
2546 /* The entry instruction always subtracts 32 from the SP. */
2547 PROC_FRAME_OFFSET (&temp_proc_desc
) += 32;
2549 /* Now we can calculate what the SP must have been at the
2550 start of the function prologue. */
2551 sp
+= PROC_FRAME_OFFSET (&temp_proc_desc
);
2553 /* Check if a0-a3 were saved in the caller's argument save area. */
2554 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
2556 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2557 set_reg_offset (this_cache
, reg
, sp
+ offset
);
2558 offset
+= mips_abi_regsize (current_gdbarch
);
2561 /* Check if the ra register was pushed on the stack. */
2563 if (entry_inst
& 0x20)
2565 PROC_REG_MASK (&temp_proc_desc
) |= 1 << RA_REGNUM
;
2566 set_reg_offset (this_cache
, RA_REGNUM
, sp
+ offset
);
2567 offset
-= mips_abi_regsize (current_gdbarch
);
2570 /* Check if the s0 and s1 registers were pushed on the stack. */
2571 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
2573 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2574 set_reg_offset (this_cache
, reg
, sp
+ offset
);
2575 offset
-= mips_abi_regsize (current_gdbarch
);
2580 /* Mark all the registers as unset in the saved_regs array
2581 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
2584 reset_saved_regs (struct mips_frame_cache
*this_cache
)
2586 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
2590 const int num_regs
= NUM_REGS
;
2593 for (i
= 0; i
< num_regs
; i
++)
2595 this_cache
->saved_regs
[i
].addr
= -1;
2601 mips32_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2602 CORE_ADDR sp
, struct frame_info
*next_frame
,
2603 struct mips_frame_cache
*this_cache
)
2606 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
2608 int frame_reg
= MIPS_SP_REGNUM
;
2613 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSTLEN
)
2615 unsigned long inst
, high_word
, low_word
;
2618 /* Fetch the instruction. */
2619 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
2621 /* Save some code by pre-extracting some useful fields. */
2622 high_word
= (inst
>> 16) & 0xffff;
2623 low_word
= inst
& 0xffff;
2624 reg
= high_word
& 0x1f;
2626 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
2627 || high_word
== 0x23bd /* addi $sp,$sp,-i */
2628 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
2630 if (low_word
& 0x8000) /* negative stack adjustment? */
2631 frame_offset
+= 0x10000 - low_word
;
2633 /* Exit loop if a positive stack adjustment is found, which
2634 usually means that the stack cleanup code in the function
2635 epilogue is reached. */
2638 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
2640 set_reg_offset (this_cache
, reg
, sp
+ low_word
);
2642 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
2644 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and
2646 set_reg_offset (this_cache
, reg
, sp
+ low_word
);
2648 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
2650 /* Old gcc frame, r30 is virtual frame pointer. */
2651 if ((long) low_word
!= frame_offset
)
2652 frame_addr
= sp
+ low_word
;
2653 else if (frame_reg
== MIPS_SP_REGNUM
)
2655 unsigned alloca_adjust
;
2658 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
2659 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
2660 if (alloca_adjust
> 0)
2662 /* FP > SP + frame_size. This may be because of
2663 an alloca or somethings similar. Fix sp to
2664 "pre-alloca" value, and try again. */
2665 sp
+= alloca_adjust
;
2666 /* Need to reset the status of all registers. Otherwise,
2667 we will hit a guard that prevents the new address
2668 for each register to be recomputed during the second
2670 reset_saved_regs (this_cache
);
2675 /* move $30,$sp. With different versions of gas this will be either
2676 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
2677 Accept any one of these. */
2678 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2680 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
2681 if (frame_reg
== MIPS_SP_REGNUM
)
2683 unsigned alloca_adjust
;
2686 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
2687 alloca_adjust
= (unsigned) (frame_addr
- sp
);
2688 if (alloca_adjust
> 0)
2690 /* FP > SP + frame_size. This may be because of
2691 an alloca or somethings similar. Fix sp to
2692 "pre-alloca" value, and try again. */
2694 /* Need to reset the status of all registers. Otherwise,
2695 we will hit a guard that prevents the new address
2696 for each register to be recomputed during the second
2698 reset_saved_regs (this_cache
);
2703 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
2705 set_reg_offset (this_cache
, reg
, frame_addr
+ low_word
);
2709 if (this_cache
!= NULL
)
2712 (frame_unwind_register_signed (next_frame
, NUM_REGS
+ frame_reg
)
2714 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
2715 this assignment below, eventually. But it's still needed
2717 this_cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->pc
]
2718 = this_cache
->saved_regs
[NUM_REGS
+ RA_REGNUM
];
2722 static mips_extra_func_info_t
2723 heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2724 struct frame_info
*next_frame
,
2725 struct mips_frame_cache
*this_cache
)
2729 /* Can be called when there's no process, and hence when there's no
2731 if (next_frame
!= NULL
)
2732 sp
= read_next_frame_reg (next_frame
, NUM_REGS
+ MIPS_SP_REGNUM
);
2738 memset (&temp_proc_desc
, '\0', sizeof (temp_proc_desc
));
2739 PROC_LOW_ADDR (&temp_proc_desc
) = start_pc
;
2740 PROC_FRAME_REG (&temp_proc_desc
) = MIPS_SP_REGNUM
;
2741 PROC_PC_REG (&temp_proc_desc
) = RA_REGNUM
;
2743 if (start_pc
+ 200 < limit_pc
)
2744 limit_pc
= start_pc
+ 200;
2745 if (pc_is_mips16 (start_pc
))
2746 mips16_heuristic_proc_desc (start_pc
, limit_pc
, sp
,
2747 next_frame
, this_cache
);
2749 mips32_heuristic_proc_desc (start_pc
, limit_pc
, sp
,
2750 next_frame
, this_cache
);
2751 return &temp_proc_desc
;
2754 struct mips_objfile_private
2760 /* Global used to communicate between non_heuristic_proc_desc and
2761 compare_pdr_entries within qsort (). */
2762 static bfd
*the_bfd
;
2765 compare_pdr_entries (const void *a
, const void *b
)
2767 CORE_ADDR lhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) a
);
2768 CORE_ADDR rhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) b
);
2772 else if (lhs
== rhs
)
2778 static mips_extra_func_info_t
2779 non_heuristic_proc_desc (CORE_ADDR pc
, CORE_ADDR
*addrptr
)
2781 CORE_ADDR startaddr
;
2782 mips_extra_func_info_t proc_desc
;
2783 struct block
*b
= block_for_pc (pc
);
2785 struct obj_section
*sec
;
2786 struct mips_objfile_private
*priv
;
2788 find_pc_partial_function (pc
, NULL
, &startaddr
, NULL
);
2790 *addrptr
= startaddr
;
2794 sec
= find_pc_section (pc
);
2797 priv
= (struct mips_objfile_private
*) objfile_data (sec
->objfile
, mips_pdr_data
);
2799 /* Search the ".pdr" section generated by GAS. This includes most of
2800 the information normally found in ECOFF PDRs. */
2802 the_bfd
= sec
->objfile
->obfd
;
2804 && (the_bfd
->format
== bfd_object
2805 && bfd_get_flavour (the_bfd
) == bfd_target_elf_flavour
2806 && elf_elfheader (the_bfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
))
2808 /* Right now GAS only outputs the address as a four-byte sequence.
2809 This means that we should not bother with this method on 64-bit
2810 targets (until that is fixed). */
2812 priv
= obstack_alloc (&sec
->objfile
->objfile_obstack
,
2813 sizeof (struct mips_objfile_private
));
2815 set_objfile_data (sec
->objfile
, mips_pdr_data
, priv
);
2817 else if (priv
== NULL
)
2821 priv
= obstack_alloc (&sec
->objfile
->objfile_obstack
,
2822 sizeof (struct mips_objfile_private
));
2824 bfdsec
= bfd_get_section_by_name (sec
->objfile
->obfd
, ".pdr");
2827 priv
->size
= bfd_section_size (sec
->objfile
->obfd
, bfdsec
);
2828 priv
->contents
= obstack_alloc (&sec
->objfile
->objfile_obstack
,
2830 bfd_get_section_contents (sec
->objfile
->obfd
, bfdsec
,
2831 priv
->contents
, 0, priv
->size
);
2833 /* In general, the .pdr section is sorted. However, in the
2834 presence of multiple code sections (and other corner cases)
2835 it can become unsorted. Sort it so that we can use a faster
2837 qsort (priv
->contents
, priv
->size
/ 32, 32,
2838 compare_pdr_entries
);
2843 set_objfile_data (sec
->objfile
, mips_pdr_data
, priv
);
2847 if (priv
->size
!= 0)
2854 high
= priv
->size
/ 32;
2856 /* We've found a .pdr section describing this objfile. We want to
2857 find the entry which describes this code address. The .pdr
2858 information is not very descriptive; we have only a function
2859 start address. We have to look for the closest entry, because
2860 the local symbol at the beginning of this function may have
2861 been stripped - so if we ask the symbol table for the start
2862 address we may get a preceding global function. */
2864 /* First, find the last .pdr entry starting at or before PC. */
2867 mid
= (low
+ high
) / 2;
2869 ptr
= priv
->contents
+ mid
* 32;
2870 pdr_pc
= bfd_get_signed_32 (sec
->objfile
->obfd
, ptr
);
2871 pdr_pc
+= ANOFFSET (sec
->objfile
->section_offsets
,
2872 SECT_OFF_TEXT (sec
->objfile
));
2879 while (low
!= high
);
2881 /* Both low and high point one past the PDR of interest. If
2882 both are zero, that means this PC is before any region
2883 covered by a PDR, i.e. pdr_pc for the first PDR entry is
2887 ptr
= priv
->contents
+ (low
- 1) * 32;
2888 pdr_pc
= bfd_get_signed_32 (sec
->objfile
->obfd
, ptr
);
2889 pdr_pc
+= ANOFFSET (sec
->objfile
->section_offsets
,
2890 SECT_OFF_TEXT (sec
->objfile
));
2893 /* We don't have a range, so we have no way to know for sure
2894 whether we're in the correct PDR or a PDR for a preceding
2895 function and the current function was a stripped local
2896 symbol. But if the PDR's PC is at least as great as the
2897 best guess from the symbol table, assume that it does cover
2898 the right area; if a .pdr section is present at all then
2899 nearly every function will have an entry. The biggest exception
2900 will be the dynamic linker stubs; conveniently these are
2901 placed before .text instead of after. */
2903 if (pc
>= pdr_pc
&& pdr_pc
>= startaddr
)
2905 struct symbol
*sym
= find_pc_function (pc
);
2910 /* Fill in what we need of the proc_desc. */
2911 proc_desc
= (mips_extra_func_info_t
)
2912 obstack_alloc (&sec
->objfile
->objfile_obstack
,
2913 sizeof (struct mips_extra_func_info
));
2914 PROC_LOW_ADDR (proc_desc
) = pdr_pc
;
2916 /* Only used for dummy frames. */
2917 PROC_HIGH_ADDR (proc_desc
) = 0;
2919 PROC_FRAME_OFFSET (proc_desc
)
2920 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 20);
2921 PROC_FRAME_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2923 PROC_FRAME_ADJUST (proc_desc
) = 0;
2924 PROC_REG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2926 PROC_FREG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2928 PROC_REG_OFFSET (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2930 PROC_FREG_OFFSET (proc_desc
)
2931 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 16);
2932 PROC_PC_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2934 proc_desc
->pdr
.isym
= (long) sym
;
2944 if (startaddr
> BLOCK_START (b
))
2946 /* This is the "pathological" case referred to in a comment in
2947 print_frame_info. It might be better to move this check into
2952 sym
= lookup_symbol (MIPS_EFI_SYMBOL_NAME
, b
, LABEL_DOMAIN
, 0, NULL
);
2954 /* If we never found a PDR for this function in symbol reading, then
2955 examine prologues to find the information. */
2958 proc_desc
= (mips_extra_func_info_t
) SYMBOL_VALUE (sym
);
2959 if (PROC_FRAME_REG (proc_desc
) == -1)
2968 /* MIPS stack frames are almost impenetrable. When execution stops,
2969 we basically have to look at symbol information for the function
2970 that we stopped in, which tells us *which* register (if any) is
2971 the base of the frame pointer, and what offset from that register
2972 the frame itself is at.
2974 This presents a problem when trying to examine a stack in memory
2975 (that isn't executing at the moment), using the "frame" command. We
2976 don't have a PC, nor do we have any registers except SP.
2978 This routine takes two arguments, SP and PC, and tries to make the
2979 cached frames look as if these two arguments defined a frame on the
2980 cache. This allows the rest of info frame to extract the important
2981 arguments without difficulty. */
2984 setup_arbitrary_frame (int argc
, CORE_ADDR
*argv
)
2987 error ("MIPS frame specifications require two arguments: sp and pc");
2989 return create_new_frame (argv
[0], argv
[1]);
2992 /* According to the current ABI, should the type be passed in a
2993 floating-point register (assuming that there is space)? When there
2994 is no FPU, FP are not even considered as possibile candidates for
2995 FP registers and, consequently this returns false - forces FP
2996 arguments into integer registers. */
2999 fp_register_arg_p (enum type_code typecode
, struct type
*arg_type
)
3001 return ((typecode
== TYPE_CODE_FLT
3003 && (typecode
== TYPE_CODE_STRUCT
3004 || typecode
== TYPE_CODE_UNION
)
3005 && TYPE_NFIELDS (arg_type
) == 1
3006 && TYPE_CODE (TYPE_FIELD_TYPE (arg_type
, 0)) == TYPE_CODE_FLT
))
3007 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
);
3010 /* On o32, argument passing in GPRs depends on the alignment of the type being
3011 passed. Return 1 if this type must be aligned to a doubleword boundary. */
3014 mips_type_needs_double_align (struct type
*type
)
3016 enum type_code typecode
= TYPE_CODE (type
);
3018 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
3020 else if (typecode
== TYPE_CODE_STRUCT
)
3022 if (TYPE_NFIELDS (type
) < 1)
3024 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
3026 else if (typecode
== TYPE_CODE_UNION
)
3030 n
= TYPE_NFIELDS (type
);
3031 for (i
= 0; i
< n
; i
++)
3032 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
3039 /* Adjust the address downward (direction of stack growth) so that it
3040 is correctly aligned for a new stack frame. */
3042 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
3044 return align_down (addr
, 16);
3047 /* Determine how a return value is stored within the MIPS register
3048 file, given the return type `valtype'. */
3050 struct return_value_word
3059 return_value_location (struct type
*valtype
,
3060 struct return_value_word
*hi
,
3061 struct return_value_word
*lo
)
3063 int len
= TYPE_LENGTH (valtype
);
3064 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3066 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
3067 && ((MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
&& (len
== 4 || len
== 8))
3068 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
&& len
== 4)))
3070 if (mips_abi_regsize (current_gdbarch
) < 8 && len
== 8)
3072 /* We need to break a 64bit float in two 32 bit halves and
3073 spread them across a floating-point register pair. */
3074 lo
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3075 hi
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 0 : 4;
3076 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3077 && register_size (current_gdbarch
,
3078 mips_regnum (current_gdbarch
)->
3079 fp0
) == 8) ? 4 : 0);
3080 hi
->reg_offset
= lo
->reg_offset
;
3081 lo
->reg
= mips_regnum (current_gdbarch
)->fp0
+ 0;
3082 hi
->reg
= mips_regnum (current_gdbarch
)->fp0
+ 1;
3088 /* The floating point value fits in a single floating-point
3090 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3091 && register_size (current_gdbarch
,
3092 mips_regnum (current_gdbarch
)->
3094 && len
== 4) ? 4 : 0);
3095 lo
->reg
= mips_regnum (current_gdbarch
)->fp0
;
3106 /* Locate a result possibly spread across two registers. */
3108 lo
->reg
= regnum
+ 0;
3109 hi
->reg
= regnum
+ 1;
3110 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3111 && len
< mips_abi_regsize (current_gdbarch
))
3113 /* "un-left-justify" the value in the low register */
3114 lo
->reg_offset
= mips_abi_regsize (current_gdbarch
) - len
;
3119 else if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
&& len
> mips_abi_regsize (current_gdbarch
) /* odd-size structs */
3120 && len
< mips_abi_regsize (current_gdbarch
) * 2
3121 && (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
3122 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
3124 /* "un-left-justify" the value spread across two registers. */
3125 lo
->reg_offset
= 2 * mips_abi_regsize (current_gdbarch
) - len
;
3126 lo
->len
= mips_abi_regsize (current_gdbarch
) - lo
->reg_offset
;
3128 hi
->len
= len
- lo
->len
;
3132 /* Only perform a partial copy of the second register. */
3135 if (len
> mips_abi_regsize (current_gdbarch
))
3137 lo
->len
= mips_abi_regsize (current_gdbarch
);
3138 hi
->len
= len
- mips_abi_regsize (current_gdbarch
);
3146 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3147 && register_size (current_gdbarch
, regnum
) == 8
3148 && mips_abi_regsize (current_gdbarch
) == 4)
3150 /* Account for the fact that only the least-signficant part
3151 of the register is being used */
3152 lo
->reg_offset
+= 4;
3153 hi
->reg_offset
+= 4;
3156 hi
->buf_offset
= lo
->len
;
3160 /* Should call_function allocate stack space for a struct return? */
3163 mips_eabi_use_struct_convention (int gcc_p
, struct type
*type
)
3165 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3166 return (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (current_gdbarch
));
3169 /* Should call_function pass struct by reference?
3170 For each architecture, structs are passed either by
3171 value or by reference, depending on their size. */
3174 mips_eabi_reg_struct_has_addr (int gcc_p
, struct type
*type
)
3176 enum type_code typecode
= TYPE_CODE (check_typedef (type
));
3177 int len
= TYPE_LENGTH (check_typedef (type
));
3178 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3180 if (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
3181 return (len
> mips_abi_regsize (current_gdbarch
));
3187 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3188 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3189 int nargs
, struct value
**args
, CORE_ADDR sp
,
3190 int struct_return
, CORE_ADDR struct_addr
)
3196 int stack_offset
= 0;
3197 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3198 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3200 /* For shared libraries, "t9" needs to point at the function
3202 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3204 /* Set the return address register to point to the entry point of
3205 the program, where a breakpoint lies in wait. */
3206 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3208 /* First ensure that the stack and structure return address (if any)
3209 are properly aligned. The stack has to be at least 64-bit
3210 aligned even on 32-bit machines, because doubles must be 64-bit
3211 aligned. For n32 and n64, stack frames need to be 128-bit
3212 aligned, so we round to this widest known alignment. */
3214 sp
= align_down (sp
, 16);
3215 struct_addr
= align_down (struct_addr
, 16);
3217 /* Now make space on the stack for the args. We allocate more
3218 than necessary for EABI, because the first few arguments are
3219 passed in registers, but that's OK. */
3220 for (argnum
= 0; argnum
< nargs
; argnum
++)
3221 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3222 mips_stack_argsize (gdbarch
));
3223 sp
-= align_up (len
, 16);
3226 fprintf_unfiltered (gdb_stdlog
,
3227 "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n",
3228 paddr_nz (sp
), (long) align_up (len
, 16));
3230 /* Initialize the integer and float register pointers. */
3232 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3234 /* The struct_return pointer occupies the first parameter-passing reg. */
3238 fprintf_unfiltered (gdb_stdlog
,
3239 "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n",
3240 argreg
, paddr_nz (struct_addr
));
3241 write_register (argreg
++, struct_addr
);
3244 /* Now load as many as possible of the first arguments into
3245 registers, and push the rest onto the stack. Loop thru args
3246 from first to last. */
3247 for (argnum
= 0; argnum
< nargs
; argnum
++)
3250 char valbuf
[MAX_REGISTER_SIZE
];
3251 struct value
*arg
= args
[argnum
];
3252 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3253 int len
= TYPE_LENGTH (arg_type
);
3254 enum type_code typecode
= TYPE_CODE (arg_type
);
3257 fprintf_unfiltered (gdb_stdlog
,
3258 "mips_eabi_push_dummy_call: %d len=%d type=%d",
3259 argnum
+ 1, len
, (int) typecode
);
3261 /* The EABI passes structures that do not fit in a register by
3263 if (len
> mips_abi_regsize (gdbarch
)
3264 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
3266 store_unsigned_integer (valbuf
, mips_abi_regsize (gdbarch
),
3267 VALUE_ADDRESS (arg
));
3268 typecode
= TYPE_CODE_PTR
;
3269 len
= mips_abi_regsize (gdbarch
);
3272 fprintf_unfiltered (gdb_stdlog
, " push");
3275 val
= (char *) VALUE_CONTENTS (arg
);
3277 /* 32-bit ABIs always start floating point arguments in an
3278 even-numbered floating point register. Round the FP register
3279 up before the check to see if there are any FP registers
3280 left. Non MIPS_EABI targets also pass the FP in the integer
3281 registers so also round up normal registers. */
3282 if (mips_abi_regsize (gdbarch
) < 8
3283 && fp_register_arg_p (typecode
, arg_type
))
3285 if ((float_argreg
& 1))
3289 /* Floating point arguments passed in registers have to be
3290 treated specially. On 32-bit architectures, doubles
3291 are passed in register pairs; the even register gets
3292 the low word, and the odd register gets the high word.
3293 On non-EABI processors, the first two floating point arguments are
3294 also copied to general registers, because MIPS16 functions
3295 don't use float registers for arguments. This duplication of
3296 arguments in general registers can't hurt non-MIPS16 functions
3297 because those registers are normally skipped. */
3298 /* MIPS_EABI squeezes a struct that contains a single floating
3299 point value into an FP register instead of pushing it onto the
3301 if (fp_register_arg_p (typecode
, arg_type
)
3302 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3304 if (mips_abi_regsize (gdbarch
) < 8 && len
== 8)
3306 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3307 unsigned long regval
;
3309 /* Write the low word of the double to the even register(s). */
3310 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3312 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3313 float_argreg
, phex (regval
, 4));
3314 write_register (float_argreg
++, regval
);
3316 /* Write the high word of the double to the odd register(s). */
3317 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3319 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3320 float_argreg
, phex (regval
, 4));
3321 write_register (float_argreg
++, regval
);
3325 /* This is a floating point value that fits entirely
3326 in a single register. */
3327 /* On 32 bit ABI's the float_argreg is further adjusted
3328 above to ensure that it is even register aligned. */
3329 LONGEST regval
= extract_unsigned_integer (val
, len
);
3331 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3332 float_argreg
, phex (regval
, len
));
3333 write_register (float_argreg
++, regval
);
3338 /* Copy the argument to general registers or the stack in
3339 register-sized pieces. Large arguments are split between
3340 registers and stack. */
3341 /* Note: structs whose size is not a multiple of
3342 mips_abi_regsize() are treated specially: Irix cc passes
3343 them in registers where gcc sometimes puts them on the
3344 stack. For maximum compatibility, we will put them in
3346 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
3347 && (len
% mips_abi_regsize (gdbarch
) != 0));
3349 /* Note: Floating-point values that didn't fit into an FP
3350 register are only written to memory. */
3353 /* Remember if the argument was written to the stack. */
3354 int stack_used_p
= 0;
3355 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
3356 ? len
: mips_abi_regsize (gdbarch
));
3359 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3362 /* Write this portion of the argument to the stack. */
3363 if (argreg
> MIPS_LAST_ARG_REGNUM
3365 || fp_register_arg_p (typecode
, arg_type
))
3367 /* Should shorter than int integer values be
3368 promoted to int before being stored? */
3369 int longword_offset
= 0;
3372 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3374 if (mips_stack_argsize (gdbarch
) == 8
3375 && (typecode
== TYPE_CODE_INT
3376 || typecode
== TYPE_CODE_PTR
3377 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3378 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
3379 else if ((typecode
== TYPE_CODE_STRUCT
3380 || typecode
== TYPE_CODE_UNION
)
3381 && (TYPE_LENGTH (arg_type
)
3382 < mips_stack_argsize (gdbarch
)))
3383 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
3388 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3389 paddr_nz (stack_offset
));
3390 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3391 paddr_nz (longword_offset
));
3394 addr
= sp
+ stack_offset
+ longword_offset
;
3399 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3401 for (i
= 0; i
< partial_len
; i
++)
3403 fprintf_unfiltered (gdb_stdlog
, "%02x",
3407 write_memory (addr
, val
, partial_len
);
3410 /* Note!!! This is NOT an else clause. Odd sized
3411 structs may go thru BOTH paths. Floating point
3412 arguments will not. */
3413 /* Write this portion of the argument to a general
3414 purpose register. */
3415 if (argreg
<= MIPS_LAST_ARG_REGNUM
3416 && !fp_register_arg_p (typecode
, arg_type
))
3419 extract_unsigned_integer (val
, partial_len
);
3422 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3425 mips_abi_regsize (gdbarch
)));
3426 write_register (argreg
, regval
);
3433 /* Compute the the offset into the stack at which we
3434 will copy the next parameter.
3436 In the new EABI (and the NABI32), the stack_offset
3437 only needs to be adjusted when it has been used. */
3440 stack_offset
+= align_up (partial_len
,
3441 mips_stack_argsize (gdbarch
));
3445 fprintf_unfiltered (gdb_stdlog
, "\n");
3448 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3450 /* Return adjusted stack pointer. */
3454 /* Given a return value in `regbuf' with a type `valtype', extract and
3455 copy its value into `valbuf'. */
3458 mips_eabi_extract_return_value (struct type
*valtype
,
3459 char regbuf
[], char *valbuf
)
3461 struct return_value_word lo
;
3462 struct return_value_word hi
;
3463 return_value_location (valtype
, &hi
, &lo
);
3465 memcpy (valbuf
+ lo
.buf_offset
,
3466 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ lo
.reg
) +
3467 lo
.reg_offset
, lo
.len
);
3470 memcpy (valbuf
+ hi
.buf_offset
,
3471 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ hi
.reg
) +
3472 hi
.reg_offset
, hi
.len
);
3475 /* Given a return value in `valbuf' with a type `valtype', write it's
3476 value into the appropriate register. */
3479 mips_eabi_store_return_value (struct type
*valtype
, char *valbuf
)
3481 char raw_buffer
[MAX_REGISTER_SIZE
];
3482 struct return_value_word lo
;
3483 struct return_value_word hi
;
3484 return_value_location (valtype
, &hi
, &lo
);
3486 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3487 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
3488 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo
.reg
),
3489 raw_buffer
, register_size (current_gdbarch
,
3494 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3495 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
3496 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi
.reg
),
3498 register_size (current_gdbarch
,
3503 /* N32/N64 ABI stuff. */
3506 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3507 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3508 int nargs
, struct value
**args
, CORE_ADDR sp
,
3509 int struct_return
, CORE_ADDR struct_addr
)
3515 int stack_offset
= 0;
3516 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3517 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3519 /* For shared libraries, "t9" needs to point at the function
3521 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3523 /* Set the return address register to point to the entry point of
3524 the program, where a breakpoint lies in wait. */
3525 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3527 /* First ensure that the stack and structure return address (if any)
3528 are properly aligned. The stack has to be at least 64-bit
3529 aligned even on 32-bit machines, because doubles must be 64-bit
3530 aligned. For n32 and n64, stack frames need to be 128-bit
3531 aligned, so we round to this widest known alignment. */
3533 sp
= align_down (sp
, 16);
3534 struct_addr
= align_down (struct_addr
, 16);
3536 /* Now make space on the stack for the args. */
3537 for (argnum
= 0; argnum
< nargs
; argnum
++)
3538 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3539 mips_stack_argsize (gdbarch
));
3540 sp
-= align_up (len
, 16);
3543 fprintf_unfiltered (gdb_stdlog
,
3544 "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n",
3545 paddr_nz (sp
), (long) align_up (len
, 16));
3547 /* Initialize the integer and float register pointers. */
3549 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3551 /* The struct_return pointer occupies the first parameter-passing reg. */
3555 fprintf_unfiltered (gdb_stdlog
,
3556 "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n",
3557 argreg
, paddr_nz (struct_addr
));
3558 write_register (argreg
++, struct_addr
);
3561 /* Now load as many as possible of the first arguments into
3562 registers, and push the rest onto the stack. Loop thru args
3563 from first to last. */
3564 for (argnum
= 0; argnum
< nargs
; argnum
++)
3567 struct value
*arg
= args
[argnum
];
3568 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3569 int len
= TYPE_LENGTH (arg_type
);
3570 enum type_code typecode
= TYPE_CODE (arg_type
);
3573 fprintf_unfiltered (gdb_stdlog
,
3574 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
3575 argnum
+ 1, len
, (int) typecode
);
3577 val
= (char *) VALUE_CONTENTS (arg
);
3579 if (fp_register_arg_p (typecode
, arg_type
)
3580 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3582 /* This is a floating point value that fits entirely
3583 in a single register. */
3584 /* On 32 bit ABI's the float_argreg is further adjusted
3585 above to ensure that it is even register aligned. */
3586 LONGEST regval
= extract_unsigned_integer (val
, len
);
3588 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3589 float_argreg
, phex (regval
, len
));
3590 write_register (float_argreg
++, regval
);
3593 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3594 argreg
, phex (regval
, len
));
3595 write_register (argreg
, regval
);
3600 /* Copy the argument to general registers or the stack in
3601 register-sized pieces. Large arguments are split between
3602 registers and stack. */
3603 /* Note: structs whose size is not a multiple of
3604 mips_abi_regsize() are treated specially: Irix cc passes
3605 them in registers where gcc sometimes puts them on the
3606 stack. For maximum compatibility, we will put them in
3608 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
3609 && (len
% mips_abi_regsize (gdbarch
) != 0));
3610 /* Note: Floating-point values that didn't fit into an FP
3611 register are only written to memory. */
3614 /* Rememer if the argument was written to the stack. */
3615 int stack_used_p
= 0;
3616 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
3617 ? len
: mips_abi_regsize (gdbarch
));
3620 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3623 /* Write this portion of the argument to the stack. */
3624 if (argreg
> MIPS_LAST_ARG_REGNUM
3626 || fp_register_arg_p (typecode
, arg_type
))
3628 /* Should shorter than int integer values be
3629 promoted to int before being stored? */
3630 int longword_offset
= 0;
3633 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3635 if (mips_stack_argsize (gdbarch
) == 8
3636 && (typecode
== TYPE_CODE_INT
3637 || typecode
== TYPE_CODE_PTR
3638 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3639 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
3644 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3645 paddr_nz (stack_offset
));
3646 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3647 paddr_nz (longword_offset
));
3650 addr
= sp
+ stack_offset
+ longword_offset
;
3655 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3657 for (i
= 0; i
< partial_len
; i
++)
3659 fprintf_unfiltered (gdb_stdlog
, "%02x",
3663 write_memory (addr
, val
, partial_len
);
3666 /* Note!!! This is NOT an else clause. Odd sized
3667 structs may go thru BOTH paths. Floating point
3668 arguments will not. */
3669 /* Write this portion of the argument to a general
3670 purpose register. */
3671 if (argreg
<= MIPS_LAST_ARG_REGNUM
3672 && !fp_register_arg_p (typecode
, arg_type
))
3675 extract_unsigned_integer (val
, partial_len
);
3677 /* A non-floating-point argument being passed in a
3678 general register. If a struct or union, and if
3679 the remaining length is smaller than the register
3680 size, we have to adjust the register value on
3683 It does not seem to be necessary to do the
3684 same for integral types.
3686 cagney/2001-07-23: gdb/179: Also, GCC, when
3687 outputting LE O32 with sizeof (struct) <
3688 mips_abi_regsize(), generates a left shift as
3689 part of storing the argument in a register a
3690 register (the left shift isn't generated when
3691 sizeof (struct) >= mips_abi_regsize()). Since
3692 it is quite possible that this is GCC
3693 contradicting the LE/O32 ABI, GDB has not been
3694 adjusted to accommodate this. Either someone
3695 needs to demonstrate that the LE/O32 ABI
3696 specifies such a left shift OR this new ABI gets
3697 identified as such and GDB gets tweaked
3700 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3701 && partial_len
< mips_abi_regsize (gdbarch
)
3702 && (typecode
== TYPE_CODE_STRUCT
||
3703 typecode
== TYPE_CODE_UNION
))
3704 regval
<<= ((mips_abi_regsize (gdbarch
) - partial_len
) *
3708 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3711 mips_abi_regsize (gdbarch
)));
3712 write_register (argreg
, regval
);
3719 /* Compute the the offset into the stack at which we
3720 will copy the next parameter.
3722 In N32 (N64?), the stack_offset only needs to be
3723 adjusted when it has been used. */
3726 stack_offset
+= align_up (partial_len
,
3727 mips_stack_argsize (gdbarch
));
3731 fprintf_unfiltered (gdb_stdlog
, "\n");
3734 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3736 /* Return adjusted stack pointer. */
3740 static enum return_value_convention
3741 mips_n32n64_return_value (struct gdbarch
*gdbarch
,
3742 struct type
*type
, struct regcache
*regcache
,
3743 void *readbuf
, const void *writebuf
)
3745 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3746 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3747 || TYPE_CODE (type
) == TYPE_CODE_UNION
3748 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
3749 || TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
3750 return RETURN_VALUE_STRUCT_CONVENTION
;
3751 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3752 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3754 /* A floating-point value belongs in the least significant part
3757 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3758 mips_xfer_register (regcache
,
3759 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
3761 TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3762 return RETURN_VALUE_REGISTER_CONVENTION
;
3764 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3765 && TYPE_NFIELDS (type
) <= 2
3766 && TYPE_NFIELDS (type
) >= 1
3767 && ((TYPE_NFIELDS (type
) == 1
3768 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3770 || (TYPE_NFIELDS (type
) == 2
3771 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3773 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
3775 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3777 /* A struct that contains one or two floats. Each value is part
3778 in the least significant part of their floating point
3782 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
3783 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3785 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3788 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3790 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
3791 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3792 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3794 return RETURN_VALUE_REGISTER_CONVENTION
;
3796 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3797 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3799 /* A structure or union. Extract the left justified value,
3800 regardless of the byte order. I.e. DO NOT USE
3804 for (offset
= 0, regnum
= V0_REGNUM
;
3805 offset
< TYPE_LENGTH (type
);
3806 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3808 int xfer
= register_size (current_gdbarch
, regnum
);
3809 if (offset
+ xfer
> TYPE_LENGTH (type
))
3810 xfer
= TYPE_LENGTH (type
) - offset
;
3812 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3813 offset
, xfer
, regnum
);
3814 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3815 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
3817 return RETURN_VALUE_REGISTER_CONVENTION
;
3821 /* A scalar extract each part but least-significant-byte
3825 for (offset
= 0, regnum
= V0_REGNUM
;
3826 offset
< TYPE_LENGTH (type
);
3827 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3829 int xfer
= register_size (current_gdbarch
, regnum
);
3830 if (offset
+ xfer
> TYPE_LENGTH (type
))
3831 xfer
= TYPE_LENGTH (type
) - offset
;
3833 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3834 offset
, xfer
, regnum
);
3835 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3836 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3838 return RETURN_VALUE_REGISTER_CONVENTION
;
3842 /* O32 ABI stuff. */
3845 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3846 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3847 int nargs
, struct value
**args
, CORE_ADDR sp
,
3848 int struct_return
, CORE_ADDR struct_addr
)
3854 int stack_offset
= 0;
3855 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3856 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3858 /* For shared libraries, "t9" needs to point at the function
3860 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3862 /* Set the return address register to point to the entry point of
3863 the program, where a breakpoint lies in wait. */
3864 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3866 /* First ensure that the stack and structure return address (if any)
3867 are properly aligned. The stack has to be at least 64-bit
3868 aligned even on 32-bit machines, because doubles must be 64-bit
3869 aligned. For n32 and n64, stack frames need to be 128-bit
3870 aligned, so we round to this widest known alignment. */
3872 sp
= align_down (sp
, 16);
3873 struct_addr
= align_down (struct_addr
, 16);
3875 /* Now make space on the stack for the args. */
3876 for (argnum
= 0; argnum
< nargs
; argnum
++)
3877 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3878 mips_stack_argsize (gdbarch
));
3879 sp
-= align_up (len
, 16);
3882 fprintf_unfiltered (gdb_stdlog
,
3883 "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n",
3884 paddr_nz (sp
), (long) align_up (len
, 16));
3886 /* Initialize the integer and float register pointers. */
3888 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3890 /* The struct_return pointer occupies the first parameter-passing reg. */
3894 fprintf_unfiltered (gdb_stdlog
,
3895 "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n",
3896 argreg
, paddr_nz (struct_addr
));
3897 write_register (argreg
++, struct_addr
);
3898 stack_offset
+= mips_stack_argsize (gdbarch
);
3901 /* Now load as many as possible of the first arguments into
3902 registers, and push the rest onto the stack. Loop thru args
3903 from first to last. */
3904 for (argnum
= 0; argnum
< nargs
; argnum
++)
3907 struct value
*arg
= args
[argnum
];
3908 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3909 int len
= TYPE_LENGTH (arg_type
);
3910 enum type_code typecode
= TYPE_CODE (arg_type
);
3913 fprintf_unfiltered (gdb_stdlog
,
3914 "mips_o32_push_dummy_call: %d len=%d type=%d",
3915 argnum
+ 1, len
, (int) typecode
);
3917 val
= (char *) VALUE_CONTENTS (arg
);
3919 /* 32-bit ABIs always start floating point arguments in an
3920 even-numbered floating point register. Round the FP register
3921 up before the check to see if there are any FP registers
3922 left. O32/O64 targets also pass the FP in the integer
3923 registers so also round up normal registers. */
3924 if (mips_abi_regsize (gdbarch
) < 8
3925 && fp_register_arg_p (typecode
, arg_type
))
3927 if ((float_argreg
& 1))
3931 /* Floating point arguments passed in registers have to be
3932 treated specially. On 32-bit architectures, doubles
3933 are passed in register pairs; the even register gets
3934 the low word, and the odd register gets the high word.
3935 On O32/O64, the first two floating point arguments are
3936 also copied to general registers, because MIPS16 functions
3937 don't use float registers for arguments. This duplication of
3938 arguments in general registers can't hurt non-MIPS16 functions
3939 because those registers are normally skipped. */
3941 if (fp_register_arg_p (typecode
, arg_type
)
3942 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3944 if (mips_abi_regsize (gdbarch
) < 8 && len
== 8)
3946 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3947 unsigned long regval
;
3949 /* Write the low word of the double to the even register(s). */
3950 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3952 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3953 float_argreg
, phex (regval
, 4));
3954 write_register (float_argreg
++, regval
);
3956 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3957 argreg
, phex (regval
, 4));
3958 write_register (argreg
++, regval
);
3960 /* Write the high word of the double to the odd register(s). */
3961 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3963 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3964 float_argreg
, phex (regval
, 4));
3965 write_register (float_argreg
++, regval
);
3968 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3969 argreg
, phex (regval
, 4));
3970 write_register (argreg
++, regval
);
3974 /* This is a floating point value that fits entirely
3975 in a single register. */
3976 /* On 32 bit ABI's the float_argreg is further adjusted
3977 above to ensure that it is even register aligned. */
3978 LONGEST regval
= extract_unsigned_integer (val
, len
);
3980 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3981 float_argreg
, phex (regval
, len
));
3982 write_register (float_argreg
++, regval
);
3983 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3984 registers for each argument. The below is (my
3985 guess) to ensure that the corresponding integer
3986 register has reserved the same space. */
3988 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3989 argreg
, phex (regval
, len
));
3990 write_register (argreg
, regval
);
3991 argreg
+= (mips_abi_regsize (gdbarch
) == 8) ? 1 : 2;
3993 /* Reserve space for the FP register. */
3994 stack_offset
+= align_up (len
, mips_stack_argsize (gdbarch
));
3998 /* Copy the argument to general registers or the stack in
3999 register-sized pieces. Large arguments are split between
4000 registers and stack. */
4001 /* Note: structs whose size is not a multiple of
4002 mips_abi_regsize() are treated specially: Irix cc passes
4003 them in registers where gcc sometimes puts them on the
4004 stack. For maximum compatibility, we will put them in
4006 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
4007 && (len
% mips_abi_regsize (gdbarch
) != 0));
4008 /* Structures should be aligned to eight bytes (even arg registers)
4009 on MIPS_ABI_O32, if their first member has double precision. */
4010 if (mips_abi_regsize (gdbarch
) < 8
4011 && mips_type_needs_double_align (arg_type
))
4016 /* Note: Floating-point values that didn't fit into an FP
4017 register are only written to memory. */
4020 /* Remember if the argument was written to the stack. */
4021 int stack_used_p
= 0;
4022 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
4023 ? len
: mips_abi_regsize (gdbarch
));
4026 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4029 /* Write this portion of the argument to the stack. */
4030 if (argreg
> MIPS_LAST_ARG_REGNUM
4032 || fp_register_arg_p (typecode
, arg_type
))
4034 /* Should shorter than int integer values be
4035 promoted to int before being stored? */
4036 int longword_offset
= 0;
4039 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4041 if (mips_stack_argsize (gdbarch
) == 8
4042 && (typecode
== TYPE_CODE_INT
4043 || typecode
== TYPE_CODE_PTR
4044 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
4045 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
4050 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
4051 paddr_nz (stack_offset
));
4052 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
4053 paddr_nz (longword_offset
));
4056 addr
= sp
+ stack_offset
+ longword_offset
;
4061 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
4063 for (i
= 0; i
< partial_len
; i
++)
4065 fprintf_unfiltered (gdb_stdlog
, "%02x",
4069 write_memory (addr
, val
, partial_len
);
4072 /* Note!!! This is NOT an else clause. Odd sized
4073 structs may go thru BOTH paths. Floating point
4074 arguments will not. */
4075 /* Write this portion of the argument to a general
4076 purpose register. */
4077 if (argreg
<= MIPS_LAST_ARG_REGNUM
4078 && !fp_register_arg_p (typecode
, arg_type
))
4080 LONGEST regval
= extract_signed_integer (val
, partial_len
);
4081 /* Value may need to be sign extended, because
4082 mips_isa_regsize() != mips_abi_regsize(). */
4084 /* A non-floating-point argument being passed in a
4085 general register. If a struct or union, and if
4086 the remaining length is smaller than the register
4087 size, we have to adjust the register value on
4090 It does not seem to be necessary to do the
4091 same for integral types.
4093 Also don't do this adjustment on O64 binaries.
4095 cagney/2001-07-23: gdb/179: Also, GCC, when
4096 outputting LE O32 with sizeof (struct) <
4097 mips_abi_regsize(), generates a left shift as
4098 part of storing the argument in a register a
4099 register (the left shift isn't generated when
4100 sizeof (struct) >= mips_abi_regsize()). Since
4101 it is quite possible that this is GCC
4102 contradicting the LE/O32 ABI, GDB has not been
4103 adjusted to accommodate this. Either someone
4104 needs to demonstrate that the LE/O32 ABI
4105 specifies such a left shift OR this new ABI gets
4106 identified as such and GDB gets tweaked
4109 if (mips_abi_regsize (gdbarch
) < 8
4110 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4111 && partial_len
< mips_abi_regsize (gdbarch
)
4112 && (typecode
== TYPE_CODE_STRUCT
||
4113 typecode
== TYPE_CODE_UNION
))
4114 regval
<<= ((mips_abi_regsize (gdbarch
) - partial_len
) *
4118 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4121 mips_abi_regsize (gdbarch
)));
4122 write_register (argreg
, regval
);
4125 /* Prevent subsequent floating point arguments from
4126 being passed in floating point registers. */
4127 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
4133 /* Compute the the offset into the stack at which we
4134 will copy the next parameter.
4136 In older ABIs, the caller reserved space for
4137 registers that contained arguments. This was loosely
4138 refered to as their "home". Consequently, space is
4139 always allocated. */
4141 stack_offset
+= align_up (partial_len
,
4142 mips_stack_argsize (gdbarch
));
4146 fprintf_unfiltered (gdb_stdlog
, "\n");
4149 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4151 /* Return adjusted stack pointer. */
4155 static enum return_value_convention
4156 mips_o32_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
4157 struct regcache
*regcache
,
4158 void *readbuf
, const void *writebuf
)
4160 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4162 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4163 || TYPE_CODE (type
) == TYPE_CODE_UNION
4164 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
4165 return RETURN_VALUE_STRUCT_CONVENTION
;
4166 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4167 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4169 /* A single-precision floating-point value. It fits in the
4170 least significant part of FP0. */
4172 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4173 mips_xfer_register (regcache
,
4174 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
4176 TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
4177 return RETURN_VALUE_REGISTER_CONVENTION
;
4179 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4180 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4182 /* A double-precision floating-point value. The most
4183 significant part goes in FP1, and the least significant in
4186 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
4187 switch (TARGET_BYTE_ORDER
)
4189 case BFD_ENDIAN_LITTLE
:
4190 mips_xfer_register (regcache
,
4191 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
4192 0, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
4193 mips_xfer_register (regcache
,
4194 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
4195 1, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 4);
4197 case BFD_ENDIAN_BIG
:
4198 mips_xfer_register (regcache
,
4199 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
4200 1, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
4201 mips_xfer_register (regcache
,
4202 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
4203 0, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 4);
4206 internal_error (__FILE__
, __LINE__
, "bad switch");
4208 return RETURN_VALUE_REGISTER_CONVENTION
;
4211 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4212 && TYPE_NFIELDS (type
) <= 2
4213 && TYPE_NFIELDS (type
) >= 1
4214 && ((TYPE_NFIELDS (type
) == 1
4215 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4217 || (TYPE_NFIELDS (type
) == 2
4218 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4220 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
4222 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4224 /* A struct that contains one or two floats. Each value is part
4225 in the least significant part of their floating point
4227 bfd_byte reg
[MAX_REGISTER_SIZE
];
4230 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
4231 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
4233 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
4236 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
4238 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
4239 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
4240 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
4242 return RETURN_VALUE_REGISTER_CONVENTION
;
4246 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4247 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
4249 /* A structure or union. Extract the left justified value,
4250 regardless of the byte order. I.e. DO NOT USE
4254 for (offset
= 0, regnum
= V0_REGNUM
;
4255 offset
< TYPE_LENGTH (type
);
4256 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
4258 int xfer
= register_size (current_gdbarch
, regnum
);
4259 if (offset
+ xfer
> TYPE_LENGTH (type
))
4260 xfer
= TYPE_LENGTH (type
) - offset
;
4262 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
4263 offset
, xfer
, regnum
);
4264 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
4265 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
4267 return RETURN_VALUE_REGISTER_CONVENTION
;
4272 /* A scalar extract each part but least-significant-byte
4273 justified. o32 thinks registers are 4 byte, regardless of
4274 the ISA. mips_stack_argsize controls this. */
4277 for (offset
= 0, regnum
= V0_REGNUM
;
4278 offset
< TYPE_LENGTH (type
);
4279 offset
+= mips_stack_argsize (gdbarch
), regnum
++)
4281 int xfer
= mips_stack_argsize (gdbarch
);
4282 if (offset
+ xfer
> TYPE_LENGTH (type
))
4283 xfer
= TYPE_LENGTH (type
) - offset
;
4285 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4286 offset
, xfer
, regnum
);
4287 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
4288 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
4290 return RETURN_VALUE_REGISTER_CONVENTION
;
4294 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
4298 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4299 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4301 struct value
**args
, CORE_ADDR sp
,
4302 int struct_return
, CORE_ADDR struct_addr
)
4308 int stack_offset
= 0;
4309 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4310 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4312 /* For shared libraries, "t9" needs to point at the function
4314 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
4316 /* Set the return address register to point to the entry point of
4317 the program, where a breakpoint lies in wait. */
4318 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
4320 /* First ensure that the stack and structure return address (if any)
4321 are properly aligned. The stack has to be at least 64-bit
4322 aligned even on 32-bit machines, because doubles must be 64-bit
4323 aligned. For n32 and n64, stack frames need to be 128-bit
4324 aligned, so we round to this widest known alignment. */
4326 sp
= align_down (sp
, 16);
4327 struct_addr
= align_down (struct_addr
, 16);
4329 /* Now make space on the stack for the args. */
4330 for (argnum
= 0; argnum
< nargs
; argnum
++)
4331 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
4332 mips_stack_argsize (gdbarch
));
4333 sp
-= align_up (len
, 16);
4336 fprintf_unfiltered (gdb_stdlog
,
4337 "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n",
4338 paddr_nz (sp
), (long) align_up (len
, 16));
4340 /* Initialize the integer and float register pointers. */
4342 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
4344 /* The struct_return pointer occupies the first parameter-passing reg. */
4348 fprintf_unfiltered (gdb_stdlog
,
4349 "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n",
4350 argreg
, paddr_nz (struct_addr
));
4351 write_register (argreg
++, struct_addr
);
4352 stack_offset
+= mips_stack_argsize (gdbarch
);
4355 /* Now load as many as possible of the first arguments into
4356 registers, and push the rest onto the stack. Loop thru args
4357 from first to last. */
4358 for (argnum
= 0; argnum
< nargs
; argnum
++)
4361 struct value
*arg
= args
[argnum
];
4362 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
4363 int len
= TYPE_LENGTH (arg_type
);
4364 enum type_code typecode
= TYPE_CODE (arg_type
);
4367 fprintf_unfiltered (gdb_stdlog
,
4368 "mips_o64_push_dummy_call: %d len=%d type=%d",
4369 argnum
+ 1, len
, (int) typecode
);
4371 val
= (char *) VALUE_CONTENTS (arg
);
4373 /* 32-bit ABIs always start floating point arguments in an
4374 even-numbered floating point register. Round the FP register
4375 up before the check to see if there are any FP registers
4376 left. O32/O64 targets also pass the FP in the integer
4377 registers so also round up normal registers. */
4378 if (mips_abi_regsize (gdbarch
) < 8
4379 && fp_register_arg_p (typecode
, arg_type
))
4381 if ((float_argreg
& 1))
4385 /* Floating point arguments passed in registers have to be
4386 treated specially. On 32-bit architectures, doubles
4387 are passed in register pairs; the even register gets
4388 the low word, and the odd register gets the high word.
4389 On O32/O64, the first two floating point arguments are
4390 also copied to general registers, because MIPS16 functions
4391 don't use float registers for arguments. This duplication of
4392 arguments in general registers can't hurt non-MIPS16 functions
4393 because those registers are normally skipped. */
4395 if (fp_register_arg_p (typecode
, arg_type
)
4396 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
4398 if (mips_abi_regsize (gdbarch
) < 8 && len
== 8)
4400 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
4401 unsigned long regval
;
4403 /* Write the low word of the double to the even register(s). */
4404 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
4406 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4407 float_argreg
, phex (regval
, 4));
4408 write_register (float_argreg
++, regval
);
4410 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4411 argreg
, phex (regval
, 4));
4412 write_register (argreg
++, regval
);
4414 /* Write the high word of the double to the odd register(s). */
4415 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
4417 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4418 float_argreg
, phex (regval
, 4));
4419 write_register (float_argreg
++, regval
);
4422 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4423 argreg
, phex (regval
, 4));
4424 write_register (argreg
++, regval
);
4428 /* This is a floating point value that fits entirely
4429 in a single register. */
4430 /* On 32 bit ABI's the float_argreg is further adjusted
4431 above to ensure that it is even register aligned. */
4432 LONGEST regval
= extract_unsigned_integer (val
, len
);
4434 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4435 float_argreg
, phex (regval
, len
));
4436 write_register (float_argreg
++, regval
);
4437 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
4438 registers for each argument. The below is (my
4439 guess) to ensure that the corresponding integer
4440 register has reserved the same space. */
4442 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4443 argreg
, phex (regval
, len
));
4444 write_register (argreg
, regval
);
4445 argreg
+= (mips_abi_regsize (gdbarch
) == 8) ? 1 : 2;
4447 /* Reserve space for the FP register. */
4448 stack_offset
+= align_up (len
, mips_stack_argsize (gdbarch
));
4452 /* Copy the argument to general registers or the stack in
4453 register-sized pieces. Large arguments are split between
4454 registers and stack. */
4455 /* Note: structs whose size is not a multiple of
4456 mips_abi_regsize() are treated specially: Irix cc passes
4457 them in registers where gcc sometimes puts them on the
4458 stack. For maximum compatibility, we will put them in
4460 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
4461 && (len
% mips_abi_regsize (gdbarch
) != 0));
4462 /* Structures should be aligned to eight bytes (even arg registers)
4463 on MIPS_ABI_O32, if their first member has double precision. */
4464 if (mips_abi_regsize (gdbarch
) < 8
4465 && mips_type_needs_double_align (arg_type
))
4470 /* Note: Floating-point values that didn't fit into an FP
4471 register are only written to memory. */
4474 /* Remember if the argument was written to the stack. */
4475 int stack_used_p
= 0;
4476 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
4477 ? len
: mips_abi_regsize (gdbarch
));
4480 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4483 /* Write this portion of the argument to the stack. */
4484 if (argreg
> MIPS_LAST_ARG_REGNUM
4486 || fp_register_arg_p (typecode
, arg_type
))
4488 /* Should shorter than int integer values be
4489 promoted to int before being stored? */
4490 int longword_offset
= 0;
4493 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4495 if (mips_stack_argsize (gdbarch
) == 8
4496 && (typecode
== TYPE_CODE_INT
4497 || typecode
== TYPE_CODE_PTR
4498 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
4499 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
4504 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
4505 paddr_nz (stack_offset
));
4506 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
4507 paddr_nz (longword_offset
));
4510 addr
= sp
+ stack_offset
+ longword_offset
;
4515 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
4517 for (i
= 0; i
< partial_len
; i
++)
4519 fprintf_unfiltered (gdb_stdlog
, "%02x",
4523 write_memory (addr
, val
, partial_len
);
4526 /* Note!!! This is NOT an else clause. Odd sized
4527 structs may go thru BOTH paths. Floating point
4528 arguments will not. */
4529 /* Write this portion of the argument to a general
4530 purpose register. */
4531 if (argreg
<= MIPS_LAST_ARG_REGNUM
4532 && !fp_register_arg_p (typecode
, arg_type
))
4534 LONGEST regval
= extract_signed_integer (val
, partial_len
);
4535 /* Value may need to be sign extended, because
4536 mips_isa_regsize() != mips_abi_regsize(). */
4538 /* A non-floating-point argument being passed in a
4539 general register. If a struct or union, and if
4540 the remaining length is smaller than the register
4541 size, we have to adjust the register value on
4544 It does not seem to be necessary to do the
4545 same for integral types.
4547 Also don't do this adjustment on O64 binaries.
4549 cagney/2001-07-23: gdb/179: Also, GCC, when
4550 outputting LE O32 with sizeof (struct) <
4551 mips_abi_regsize(), generates a left shift as
4552 part of storing the argument in a register a
4553 register (the left shift isn't generated when
4554 sizeof (struct) >= mips_abi_regsize()). Since
4555 it is quite possible that this is GCC
4556 contradicting the LE/O32 ABI, GDB has not been
4557 adjusted to accommodate this. Either someone
4558 needs to demonstrate that the LE/O32 ABI
4559 specifies such a left shift OR this new ABI gets
4560 identified as such and GDB gets tweaked
4563 if (mips_abi_regsize (gdbarch
) < 8
4564 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4565 && partial_len
< mips_abi_regsize (gdbarch
)
4566 && (typecode
== TYPE_CODE_STRUCT
||
4567 typecode
== TYPE_CODE_UNION
))
4568 regval
<<= ((mips_abi_regsize (gdbarch
) - partial_len
) *
4572 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4575 mips_abi_regsize (gdbarch
)));
4576 write_register (argreg
, regval
);
4579 /* Prevent subsequent floating point arguments from
4580 being passed in floating point registers. */
4581 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
4587 /* Compute the the offset into the stack at which we
4588 will copy the next parameter.
4590 In older ABIs, the caller reserved space for
4591 registers that contained arguments. This was loosely
4592 refered to as their "home". Consequently, space is
4593 always allocated. */
4595 stack_offset
+= align_up (partial_len
,
4596 mips_stack_argsize (gdbarch
));
4600 fprintf_unfiltered (gdb_stdlog
, "\n");
4603 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4605 /* Return adjusted stack pointer. */
4610 mips_o64_extract_return_value (struct type
*valtype
,
4611 char regbuf
[], char *valbuf
)
4613 struct return_value_word lo
;
4614 struct return_value_word hi
;
4615 return_value_location (valtype
, &hi
, &lo
);
4617 memcpy (valbuf
+ lo
.buf_offset
,
4618 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ lo
.reg
) +
4619 lo
.reg_offset
, lo
.len
);
4622 memcpy (valbuf
+ hi
.buf_offset
,
4623 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ hi
.reg
) +
4624 hi
.reg_offset
, hi
.len
);
4628 mips_o64_store_return_value (struct type
*valtype
, char *valbuf
)
4630 char raw_buffer
[MAX_REGISTER_SIZE
];
4631 struct return_value_word lo
;
4632 struct return_value_word hi
;
4633 return_value_location (valtype
, &hi
, &lo
);
4635 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4636 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
4637 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo
.reg
),
4638 raw_buffer
, register_size (current_gdbarch
,
4643 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4644 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
4645 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi
.reg
),
4647 register_size (current_gdbarch
,
4652 /* Floating point register management.
4654 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
4655 64bit operations, these early MIPS cpus treat fp register pairs
4656 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
4657 registers and offer a compatibility mode that emulates the MIPS2 fp
4658 model. When operating in MIPS2 fp compat mode, later cpu's split
4659 double precision floats into two 32-bit chunks and store them in
4660 consecutive fp regs. To display 64-bit floats stored in this
4661 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
4662 Throw in user-configurable endianness and you have a real mess.
4664 The way this works is:
4665 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
4666 double-precision value will be split across two logical registers.
4667 The lower-numbered logical register will hold the low-order bits,
4668 regardless of the processor's endianness.
4669 - If we are on a 64-bit processor, and we are looking for a
4670 single-precision value, it will be in the low ordered bits
4671 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
4672 save slot in memory.
4673 - If we are in 64-bit mode, everything is straightforward.
4675 Note that this code only deals with "live" registers at the top of the
4676 stack. We will attempt to deal with saved registers later, when
4677 the raw/cooked register interface is in place. (We need a general
4678 interface that can deal with dynamic saved register sizes -- fp
4679 regs could be 32 bits wide in one frame and 64 on the frame above
4682 static struct type
*
4683 mips_float_register_type (void)
4685 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4686 return builtin_type_ieee_single_big
;
4688 return builtin_type_ieee_single_little
;
4691 static struct type
*
4692 mips_double_register_type (void)
4694 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4695 return builtin_type_ieee_double_big
;
4697 return builtin_type_ieee_double_little
;
4700 /* Copy a 32-bit single-precision value from the current frame
4701 into rare_buffer. */
4704 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
4707 int raw_size
= register_size (current_gdbarch
, regno
);
4708 char *raw_buffer
= alloca (raw_size
);
4710 if (!frame_register_read (frame
, regno
, raw_buffer
))
4711 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
4714 /* We have a 64-bit value for this register. Find the low-order
4718 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4723 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
4727 memcpy (rare_buffer
, raw_buffer
, 4);
4731 /* Copy a 64-bit double-precision value from the current frame into
4732 rare_buffer. This may include getting half of it from the next
4736 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
4739 int raw_size
= register_size (current_gdbarch
, regno
);
4741 if (raw_size
== 8 && !mips2_fp_compat ())
4743 /* We have a 64-bit value for this register, and we should use
4745 if (!frame_register_read (frame
, regno
, rare_buffer
))
4746 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
4750 if ((regno
- mips_regnum (current_gdbarch
)->fp0
) & 1)
4751 internal_error (__FILE__
, __LINE__
,
4752 "mips_read_fp_register_double: bad access to "
4753 "odd-numbered FP register");
4755 /* mips_read_fp_register_single will find the correct 32 bits from
4757 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4759 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
4760 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
4764 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
4765 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
4771 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
4773 { /* do values for FP (float) regs */
4775 double doub
, flt1
; /* doubles extracted from raw hex data */
4779 (char *) alloca (2 *
4780 register_size (current_gdbarch
,
4781 mips_regnum (current_gdbarch
)->fp0
));
4783 fprintf_filtered (file
, "%s:", REGISTER_NAME (regnum
));
4784 fprintf_filtered (file
, "%*s", 4 - (int) strlen (REGISTER_NAME (regnum
)),
4787 if (register_size (current_gdbarch
, regnum
) == 4 || mips2_fp_compat ())
4789 /* 4-byte registers: Print hex and floating. Also print even
4790 numbered registers as doubles. */
4791 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4792 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4794 print_scalar_formatted (raw_buffer
, builtin_type_uint32
, 'x', 'w',
4797 fprintf_filtered (file
, " flt: ");
4799 fprintf_filtered (file
, " <invalid float> ");
4801 fprintf_filtered (file
, "%-17.9g", flt1
);
4803 if (regnum
% 2 == 0)
4805 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4806 doub
= unpack_double (mips_double_register_type (), raw_buffer
,
4809 fprintf_filtered (file
, " dbl: ");
4811 fprintf_filtered (file
, "<invalid double>");
4813 fprintf_filtered (file
, "%-24.17g", doub
);
4818 /* Eight byte registers: print each one as hex, float and double. */
4819 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4820 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4822 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4823 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv2
);
4826 print_scalar_formatted (raw_buffer
, builtin_type_uint64
, 'x', 'g',
4829 fprintf_filtered (file
, " flt: ");
4831 fprintf_filtered (file
, "<invalid float>");
4833 fprintf_filtered (file
, "%-17.9g", flt1
);
4835 fprintf_filtered (file
, " dbl: ");
4837 fprintf_filtered (file
, "<invalid double>");
4839 fprintf_filtered (file
, "%-24.17g", doub
);
4844 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
4845 int regnum
, int all
)
4847 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4848 char raw_buffer
[MAX_REGISTER_SIZE
];
4851 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4853 mips_print_fp_register (file
, frame
, regnum
);
4857 /* Get the data in raw format. */
4858 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4860 fprintf_filtered (file
, "%s: [Invalid]", REGISTER_NAME (regnum
));
4864 fputs_filtered (REGISTER_NAME (regnum
), file
);
4866 /* The problem with printing numeric register names (r26, etc.) is that
4867 the user can't use them on input. Probably the best solution is to
4868 fix it so that either the numeric or the funky (a2, etc.) names
4869 are accepted on input. */
4870 if (regnum
< MIPS_NUMREGS
)
4871 fprintf_filtered (file
, "(r%d): ", regnum
);
4873 fprintf_filtered (file
, ": ");
4875 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4877 register_size (current_gdbarch
,
4878 regnum
) - register_size (current_gdbarch
, regnum
);
4882 print_scalar_formatted (raw_buffer
+ offset
,
4883 gdbarch_register_type (gdbarch
, regnum
), 'x', 0,
4887 /* Replacement for generic do_registers_info.
4888 Print regs in pretty columns. */
4891 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4894 fprintf_filtered (file
, " ");
4895 mips_print_fp_register (file
, frame
, regnum
);
4896 fprintf_filtered (file
, "\n");
4901 /* Print a row's worth of GP (int) registers, with name labels above */
4904 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4907 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4908 /* do values for GP (int) regs */
4909 char raw_buffer
[MAX_REGISTER_SIZE
];
4910 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols per row */
4914 /* For GP registers, we print a separate row of names above the vals */
4915 fprintf_filtered (file
, " ");
4916 for (col
= 0, regnum
= start_regnum
;
4917 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
; regnum
++)
4919 if (*REGISTER_NAME (regnum
) == '\0')
4920 continue; /* unused register */
4921 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
4923 break; /* end the row: reached FP register */
4924 fprintf_filtered (file
,
4925 mips_abi_regsize (current_gdbarch
) == 8 ? "%17s" : "%9s",
4926 REGISTER_NAME (regnum
));
4929 /* print the R0 to R31 names */
4930 if ((start_regnum
% NUM_REGS
) < MIPS_NUMREGS
)
4931 fprintf_filtered (file
, "\n R%-4d", start_regnum
% NUM_REGS
);
4933 fprintf_filtered (file
, "\n ");
4935 /* now print the values in hex, 4 or 8 to the row */
4936 for (col
= 0, regnum
= start_regnum
;
4937 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
; regnum
++)
4939 if (*REGISTER_NAME (regnum
) == '\0')
4940 continue; /* unused register */
4941 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
4943 break; /* end row: reached FP register */
4944 /* OK: get the data in raw format. */
4945 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4946 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
4947 /* pad small registers */
4949 byte
< (mips_abi_regsize (current_gdbarch
)
4950 - register_size (current_gdbarch
, regnum
)); byte
++)
4951 printf_filtered (" ");
4952 /* Now print the register value in hex, endian order. */
4953 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4955 register_size (current_gdbarch
,
4956 regnum
) - register_size (current_gdbarch
, regnum
);
4957 byte
< register_size (current_gdbarch
, regnum
); byte
++)
4958 fprintf_filtered (file
, "%02x", (unsigned char) raw_buffer
[byte
]);
4960 for (byte
= register_size (current_gdbarch
, regnum
) - 1;
4962 fprintf_filtered (file
, "%02x", (unsigned char) raw_buffer
[byte
]);
4963 fprintf_filtered (file
, " ");
4966 if (col
> 0) /* ie. if we actually printed anything... */
4967 fprintf_filtered (file
, "\n");
4972 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
4975 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
4976 struct frame_info
*frame
, int regnum
, int all
)
4978 if (regnum
!= -1) /* do one specified register */
4980 gdb_assert (regnum
>= NUM_REGS
);
4981 if (*(REGISTER_NAME (regnum
)) == '\0')
4982 error ("Not a valid register for the current processor type");
4984 mips_print_register (file
, frame
, regnum
, 0);
4985 fprintf_filtered (file
, "\n");
4988 /* do all (or most) registers */
4991 while (regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
)
4993 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
4996 if (all
) /* true for "INFO ALL-REGISTERS" command */
4997 regnum
= print_fp_register_row (file
, frame
, regnum
);
4999 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
5002 regnum
= print_gp_register_row (file
, frame
, regnum
);
5007 /* Is this a branch with a delay slot? */
5009 static int is_delayed (unsigned long);
5012 is_delayed (unsigned long insn
)
5015 for (i
= 0; i
< NUMOPCODES
; ++i
)
5016 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
5017 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
5019 return (i
< NUMOPCODES
5020 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
5021 | INSN_COND_BRANCH_DELAY
5022 | INSN_COND_BRANCH_LIKELY
)));
5026 mips_step_skips_delay (CORE_ADDR pc
)
5028 char buf
[MIPS_INSTLEN
];
5030 /* There is no branch delay slot on MIPS16. */
5031 if (pc_is_mips16 (pc
))
5034 if (target_read_memory (pc
, buf
, MIPS_INSTLEN
) != 0)
5035 /* If error reading memory, guess that it is not a delayed branch. */
5037 return is_delayed ((unsigned long)
5038 extract_unsigned_integer (buf
, MIPS_INSTLEN
));
5041 /* Skip the PC past function prologue instructions (32-bit version).
5042 This is a helper function for mips_skip_prologue. */
5045 mips32_skip_prologue (CORE_ADDR pc
)
5049 int seen_sp_adjust
= 0;
5050 int load_immediate_bytes
= 0;
5052 /* Find an upper bound on the prologue. */
5053 end_pc
= skip_prologue_using_sal (pc
);
5055 end_pc
= pc
+ 100; /* Magic. */
5057 /* Skip the typical prologue instructions. These are the stack adjustment
5058 instruction and the instructions that save registers on the stack
5059 or in the gcc frame. */
5060 for (; pc
< end_pc
; pc
+= MIPS_INSTLEN
)
5062 unsigned long high_word
;
5064 inst
= mips_fetch_instruction (pc
);
5065 high_word
= (inst
>> 16) & 0xffff;
5067 if (high_word
== 0x27bd /* addiu $sp,$sp,offset */
5068 || high_word
== 0x67bd) /* daddiu $sp,$sp,offset */
5070 else if (inst
== 0x03a1e823 || /* subu $sp,$sp,$at */
5071 inst
== 0x03a8e823) /* subu $sp,$sp,$t0 */
5073 else if (((inst
& 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
5074 || (inst
& 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
5075 && (inst
& 0x001F0000)) /* reg != $zero */
5078 else if ((inst
& 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
5080 else if ((inst
& 0xF3E00000) == 0xA3C00000 && (inst
& 0x001F0000))
5082 continue; /* reg != $zero */
5084 /* move $s8,$sp. With different versions of gas this will be either
5085 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
5086 Accept any one of these. */
5087 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
5090 else if ((inst
& 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
5092 else if (high_word
== 0x3c1c) /* lui $gp,n */
5094 else if (high_word
== 0x279c) /* addiu $gp,$gp,n */
5096 else if (inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
5097 || inst
== 0x033ce021) /* addu $gp,$t9,$gp */
5099 /* The following instructions load $at or $t0 with an immediate
5100 value in preparation for a stack adjustment via
5101 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
5102 a local variable, so we accept them only before a stack adjustment
5103 instruction was seen. */
5104 else if (!seen_sp_adjust
)
5106 if (high_word
== 0x3c01 || /* lui $at,n */
5107 high_word
== 0x3c08) /* lui $t0,n */
5109 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
5112 else if (high_word
== 0x3421 || /* ori $at,$at,n */
5113 high_word
== 0x3508 || /* ori $t0,$t0,n */
5114 high_word
== 0x3401 || /* ori $at,$zero,n */
5115 high_word
== 0x3408) /* ori $t0,$zero,n */
5117 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
5127 /* In a frameless function, we might have incorrectly
5128 skipped some load immediate instructions. Undo the skipping
5129 if the load immediate was not followed by a stack adjustment. */
5130 if (load_immediate_bytes
&& !seen_sp_adjust
)
5131 pc
-= load_immediate_bytes
;
5135 /* Skip the PC past function prologue instructions (16-bit version).
5136 This is a helper function for mips_skip_prologue. */
5139 mips16_skip_prologue (CORE_ADDR pc
)
5142 int extend_bytes
= 0;
5143 int prev_extend_bytes
;
5145 /* Table of instructions likely to be found in a function prologue. */
5148 unsigned short inst
;
5149 unsigned short mask
;
5155 , /* addiu $sp,offset */
5158 , /* daddiu $sp,offset */
5161 , /* sw reg,n($sp) */
5164 , /* sd reg,n($sp) */
5167 , /* sw $ra,n($sp) */
5170 , /* sd $ra,n($sp) */
5176 , /* sw $a0-$a3,n($s1) */
5179 , /* move reg,$a0-$a3 */
5182 , /* entry pseudo-op */
5185 , /* addiu $s1,$sp,n */
5187 0, 0} /* end of table marker */
5190 /* Find an upper bound on the prologue. */
5191 end_pc
= skip_prologue_using_sal (pc
);
5193 end_pc
= pc
+ 100; /* Magic. */
5195 /* Skip the typical prologue instructions. These are the stack adjustment
5196 instruction and the instructions that save registers on the stack
5197 or in the gcc frame. */
5198 for (; pc
< end_pc
; pc
+= MIPS16_INSTLEN
)
5200 unsigned short inst
;
5203 inst
= mips_fetch_instruction (pc
);
5205 /* Normally we ignore an extend instruction. However, if it is
5206 not followed by a valid prologue instruction, we must adjust
5207 the pc back over the extend so that it won't be considered
5208 part of the prologue. */
5209 if ((inst
& 0xf800) == 0xf000) /* extend */
5211 extend_bytes
= MIPS16_INSTLEN
;
5214 prev_extend_bytes
= extend_bytes
;
5217 /* Check for other valid prologue instructions besides extend. */
5218 for (i
= 0; table
[i
].mask
!= 0; i
++)
5219 if ((inst
& table
[i
].mask
) == table
[i
].inst
) /* found, get out */
5221 if (table
[i
].mask
!= 0) /* it was in table? */
5222 continue; /* ignore it */
5226 /* Return the current pc, adjusted backwards by 2 if
5227 the previous instruction was an extend. */
5228 return pc
- prev_extend_bytes
;
5234 /* To skip prologues, I use this predicate. Returns either PC itself
5235 if the code at PC does not look like a function prologue; otherwise
5236 returns an address that (if we're lucky) follows the prologue. If
5237 LENIENT, then we must skip everything which is involved in setting
5238 up the frame (it's OK to skip more, just so long as we don't skip
5239 anything which might clobber the registers which are being saved.
5240 We must skip more in the case where part of the prologue is in the
5241 delay slot of a non-prologue instruction). */
5244 mips_skip_prologue (CORE_ADDR pc
)
5246 /* See if we can determine the end of the prologue via the symbol table.
5247 If so, then return either PC, or the PC after the prologue, whichever
5250 CORE_ADDR post_prologue_pc
= after_prologue (pc
);
5252 if (post_prologue_pc
!= 0)
5253 return max (pc
, post_prologue_pc
);
5255 /* Can't determine prologue from the symbol table, need to examine
5258 if (pc_is_mips16 (pc
))
5259 return mips16_skip_prologue (pc
);
5261 return mips32_skip_prologue (pc
);
5264 /* Root of all "set mips "/"show mips " commands. This will eventually be
5265 used for all MIPS-specific commands. */
5268 show_mips_command (char *args
, int from_tty
)
5270 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
5274 set_mips_command (char *args
, int from_tty
)
5277 ("\"set mips\" must be followed by an appropriate subcommand.\n");
5278 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
5281 /* Commands to show/set the MIPS FPU type. */
5284 show_mipsfpu_command (char *args
, int from_tty
)
5287 switch (MIPS_FPU_TYPE
)
5289 case MIPS_FPU_SINGLE
:
5290 fpu
= "single-precision";
5292 case MIPS_FPU_DOUBLE
:
5293 fpu
= "double-precision";
5296 fpu
= "absent (none)";
5299 internal_error (__FILE__
, __LINE__
, "bad switch");
5301 if (mips_fpu_type_auto
)
5303 ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
5307 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
5312 set_mipsfpu_command (char *args
, int from_tty
)
5315 ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
5316 show_mipsfpu_command (args
, from_tty
);
5320 set_mipsfpu_single_command (char *args
, int from_tty
)
5322 struct gdbarch_info info
;
5323 gdbarch_info_init (&info
);
5324 mips_fpu_type
= MIPS_FPU_SINGLE
;
5325 mips_fpu_type_auto
= 0;
5326 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5327 instead of relying on globals. Doing that would let generic code
5328 handle the search for this specific architecture. */
5329 if (!gdbarch_update_p (info
))
5330 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
5334 set_mipsfpu_double_command (char *args
, int from_tty
)
5336 struct gdbarch_info info
;
5337 gdbarch_info_init (&info
);
5338 mips_fpu_type
= MIPS_FPU_DOUBLE
;
5339 mips_fpu_type_auto
= 0;
5340 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5341 instead of relying on globals. Doing that would let generic code
5342 handle the search for this specific architecture. */
5343 if (!gdbarch_update_p (info
))
5344 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
5348 set_mipsfpu_none_command (char *args
, int from_tty
)
5350 struct gdbarch_info info
;
5351 gdbarch_info_init (&info
);
5352 mips_fpu_type
= MIPS_FPU_NONE
;
5353 mips_fpu_type_auto
= 0;
5354 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5355 instead of relying on globals. Doing that would let generic code
5356 handle the search for this specific architecture. */
5357 if (!gdbarch_update_p (info
))
5358 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
5362 set_mipsfpu_auto_command (char *args
, int from_tty
)
5364 mips_fpu_type_auto
= 1;
5367 /* Attempt to identify the particular processor model by reading the
5368 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
5369 the relevant processor still exists (it dates back to '94) and
5370 secondly this is not the way to do this. The processor type should
5371 be set by forcing an architecture change. */
5374 deprecated_mips_set_processor_regs_hack (void)
5376 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
5379 prid
= read_register (PRID_REGNUM
);
5381 if ((prid
& ~0xf) == 0x700)
5382 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
5385 /* Just like reinit_frame_cache, but with the right arguments to be
5386 callable as an sfunc. */
5389 reinit_frame_cache_sfunc (char *args
, int from_tty
,
5390 struct cmd_list_element
*c
)
5392 reinit_frame_cache ();
5396 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
5398 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
5399 mips_extra_func_info_t proc_desc
;
5401 /* Search for the function containing this address. Set the low bit
5402 of the address when searching, in case we were given an even address
5403 that is the start of a 16-bit function. If we didn't do this,
5404 the search would fail because the symbol table says the function
5405 starts at an odd address, i.e. 1 byte past the given address. */
5406 memaddr
= ADDR_BITS_REMOVE (memaddr
);
5407 proc_desc
= non_heuristic_proc_desc (make_mips16_addr (memaddr
), NULL
);
5409 /* Make an attempt to determine if this is a 16-bit function. If
5410 the procedure descriptor exists and the address therein is odd,
5411 it's definitely a 16-bit function. Otherwise, we have to just
5412 guess that if the address passed in is odd, it's 16-bits. */
5413 /* FIXME: cagney/2003-06-26: Is this even necessary? The
5414 disassembler needs to be able to locally determine the ISA, and
5415 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
5419 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
5420 info
->mach
= bfd_mach_mips16
;
5424 if (pc_is_mips16 (memaddr
))
5425 info
->mach
= bfd_mach_mips16
;
5428 /* Round down the instruction address to the appropriate boundary. */
5429 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
5431 /* Set the disassembler options. */
5432 if (tdep
->mips_abi
== MIPS_ABI_N32
|| tdep
->mips_abi
== MIPS_ABI_N64
)
5434 /* Set up the disassembler info, so that we get the right
5435 register names from libopcodes. */
5436 if (tdep
->mips_abi
== MIPS_ABI_N32
)
5437 info
->disassembler_options
= "gpr-names=n32";
5439 info
->disassembler_options
= "gpr-names=64";
5440 info
->flavour
= bfd_target_elf_flavour
;
5443 /* This string is not recognized explicitly by the disassembler,
5444 but it tells the disassembler to not try to guess the ABI from
5445 the bfd elf headers, such that, if the user overrides the ABI
5446 of a program linked as NewABI, the disassembly will follow the
5447 register naming conventions specified by the user. */
5448 info
->disassembler_options
= "gpr-names=32";
5450 /* Call the appropriate disassembler based on the target endian-ness. */
5451 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5452 return print_insn_big_mips (memaddr
, info
);
5454 return print_insn_little_mips (memaddr
, info
);
5457 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
5458 counter value to determine whether a 16- or 32-bit breakpoint should be
5459 used. It returns a pointer to a string of bytes that encode a breakpoint
5460 instruction, stores the length of the string to *lenptr, and adjusts pc
5461 (if necessary) to point to the actual memory location where the
5462 breakpoint should be inserted. */
5464 static const unsigned char *
5465 mips_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
5467 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5469 if (pc_is_mips16 (*pcptr
))
5471 static unsigned char mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
5472 *pcptr
= unmake_mips16_addr (*pcptr
);
5473 *lenptr
= sizeof (mips16_big_breakpoint
);
5474 return mips16_big_breakpoint
;
5478 /* The IDT board uses an unusual breakpoint value, and
5479 sometimes gets confused when it sees the usual MIPS
5480 breakpoint instruction. */
5481 static unsigned char big_breakpoint
[] = { 0, 0x5, 0, 0xd };
5482 static unsigned char pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
5483 static unsigned char idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
5485 *lenptr
= sizeof (big_breakpoint
);
5487 if (strcmp (target_shortname
, "mips") == 0)
5488 return idt_big_breakpoint
;
5489 else if (strcmp (target_shortname
, "ddb") == 0
5490 || strcmp (target_shortname
, "pmon") == 0
5491 || strcmp (target_shortname
, "lsi") == 0)
5492 return pmon_big_breakpoint
;
5494 return big_breakpoint
;
5499 if (pc_is_mips16 (*pcptr
))
5501 static unsigned char mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
5502 *pcptr
= unmake_mips16_addr (*pcptr
);
5503 *lenptr
= sizeof (mips16_little_breakpoint
);
5504 return mips16_little_breakpoint
;
5508 static unsigned char little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
5509 static unsigned char pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
5510 static unsigned char idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
5512 *lenptr
= sizeof (little_breakpoint
);
5514 if (strcmp (target_shortname
, "mips") == 0)
5515 return idt_little_breakpoint
;
5516 else if (strcmp (target_shortname
, "ddb") == 0
5517 || strcmp (target_shortname
, "pmon") == 0
5518 || strcmp (target_shortname
, "lsi") == 0)
5519 return pmon_little_breakpoint
;
5521 return little_breakpoint
;
5526 /* If PC is in a mips16 call or return stub, return the address of the target
5527 PC, which is either the callee or the caller. There are several
5528 cases which must be handled:
5530 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5531 target PC is in $31 ($ra).
5532 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5533 and the target PC is in $2.
5534 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5535 before the jal instruction, this is effectively a call stub
5536 and the the target PC is in $2. Otherwise this is effectively
5537 a return stub and the target PC is in $18.
5539 See the source code for the stubs in gcc/config/mips/mips16.S for
5542 This function implements the SKIP_TRAMPOLINE_CODE macro.
5546 mips_skip_stub (CORE_ADDR pc
)
5549 CORE_ADDR start_addr
;
5551 /* Find the starting address and name of the function containing the PC. */
5552 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
5555 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5556 target PC is in $31 ($ra). */
5557 if (strcmp (name
, "__mips16_ret_sf") == 0
5558 || strcmp (name
, "__mips16_ret_df") == 0)
5559 return read_signed_register (RA_REGNUM
);
5561 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5563 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5564 and the target PC is in $2. */
5565 if (name
[19] >= '0' && name
[19] <= '9')
5566 return read_signed_register (2);
5568 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5569 before the jal instruction, this is effectively a call stub
5570 and the the target PC is in $2. Otherwise this is effectively
5571 a return stub and the target PC is in $18. */
5572 else if (name
[19] == 's' || name
[19] == 'd')
5574 if (pc
== start_addr
)
5576 /* Check if the target of the stub is a compiler-generated
5577 stub. Such a stub for a function bar might have a name
5578 like __fn_stub_bar, and might look like this:
5583 la $1,bar (becomes a lui/addiu pair)
5585 So scan down to the lui/addi and extract the target
5586 address from those two instructions. */
5588 CORE_ADDR target_pc
= read_signed_register (2);
5592 /* See if the name of the target function is __fn_stub_*. */
5593 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) ==
5596 if (strncmp (name
, "__fn_stub_", 10) != 0
5597 && strcmp (name
, "etext") != 0
5598 && strcmp (name
, "_etext") != 0)
5601 /* Scan through this _fn_stub_ code for the lui/addiu pair.
5602 The limit on the search is arbitrarily set to 20
5603 instructions. FIXME. */
5604 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSTLEN
)
5606 inst
= mips_fetch_instruction (target_pc
);
5607 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
5608 pc
= (inst
<< 16) & 0xffff0000; /* high word */
5609 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
5610 return pc
| (inst
& 0xffff); /* low word */
5613 /* Couldn't find the lui/addui pair, so return stub address. */
5617 /* This is the 'return' part of a call stub. The return
5618 address is in $r18. */
5619 return read_signed_register (18);
5622 return 0; /* not a stub */
5626 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
5627 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
5630 mips_in_call_stub (CORE_ADDR pc
, char *name
)
5632 CORE_ADDR start_addr
;
5634 /* Find the starting address of the function containing the PC. If the
5635 caller didn't give us a name, look it up at the same time. */
5636 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) ==
5640 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5642 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
5643 if (name
[19] >= '0' && name
[19] <= '9')
5645 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5646 before the jal instruction, this is effectively a call stub. */
5647 else if (name
[19] == 's' || name
[19] == 'd')
5648 return pc
== start_addr
;
5651 return 0; /* not a stub */
5655 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
5656 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
5659 mips_in_return_stub (CORE_ADDR pc
, char *name
)
5661 CORE_ADDR start_addr
;
5663 /* Find the starting address of the function containing the PC. */
5664 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
5667 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
5668 if (strcmp (name
, "__mips16_ret_sf") == 0
5669 || strcmp (name
, "__mips16_ret_df") == 0)
5672 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
5673 i.e. after the jal instruction, this is effectively a return stub. */
5674 if (strncmp (name
, "__mips16_call_stub_", 19) == 0
5675 && (name
[19] == 's' || name
[19] == 'd') && pc
!= start_addr
)
5678 return 0; /* not a stub */
5682 /* Return non-zero if the PC is in a library helper function that
5683 should be ignored. This implements the
5684 DEPRECATED_IGNORE_HELPER_CALL macro. */
5687 mips_ignore_helper (CORE_ADDR pc
)
5691 /* Find the starting address and name of the function containing the PC. */
5692 if (find_pc_partial_function (pc
, &name
, NULL
, NULL
) == 0)
5695 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
5696 that we want to ignore. */
5697 return (strcmp (name
, "__mips16_ret_sf") == 0
5698 || strcmp (name
, "__mips16_ret_df") == 0);
5702 /* Convert a dbx stab register number (from `r' declaration) to a GDB
5703 [1 * NUM_REGS .. 2 * NUM_REGS) REGNUM. */
5706 mips_stab_reg_to_regnum (int num
)
5709 if (num
>= 0 && num
< 32)
5711 else if (num
>= 38 && num
< 70)
5712 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 38;
5714 regnum
= mips_regnum (current_gdbarch
)->hi
;
5716 regnum
= mips_regnum (current_gdbarch
)->lo
;
5718 /* This will hopefully (eventually) provoke a warning. Should
5719 we be calling complaint() here? */
5720 return NUM_REGS
+ NUM_PSEUDO_REGS
;
5721 return NUM_REGS
+ regnum
;
5725 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
5726 NUM_REGS .. 2 * NUM_REGS) REGNUM. */
5729 mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num
)
5732 if (num
>= 0 && num
< 32)
5734 else if (num
>= 32 && num
< 64)
5735 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 32;
5737 regnum
= mips_regnum (current_gdbarch
)->hi
;
5739 regnum
= mips_regnum (current_gdbarch
)->lo
;
5741 /* This will hopefully (eventually) provoke a warning. Should we
5742 be calling complaint() here? */
5743 return NUM_REGS
+ NUM_PSEUDO_REGS
;
5744 return NUM_REGS
+ regnum
;
5748 mips_register_sim_regno (int regnum
)
5750 /* Only makes sense to supply raw registers. */
5751 gdb_assert (regnum
>= 0 && regnum
< NUM_REGS
);
5752 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
5753 decide if it is valid. Should instead define a standard sim/gdb
5754 register numbering scheme. */
5755 if (REGISTER_NAME (NUM_REGS
+ regnum
) != NULL
5756 && REGISTER_NAME (NUM_REGS
+ regnum
)[0] != '\0')
5759 return LEGACY_SIM_REGNO_IGNORE
;
5763 /* Convert an integer into an address. By first converting the value
5764 into a pointer and then extracting it signed, the address is
5765 guarenteed to be correctly sign extended. */
5768 mips_integer_to_address (struct type
*type
, void *buf
)
5770 char *tmp
= alloca (TYPE_LENGTH (builtin_type_void_data_ptr
));
5771 LONGEST val
= unpack_long (type
, buf
);
5772 store_signed_integer (tmp
, TYPE_LENGTH (builtin_type_void_data_ptr
), val
);
5773 return extract_signed_integer (tmp
,
5774 TYPE_LENGTH (builtin_type_void_data_ptr
));
5778 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
5780 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
5781 const char *name
= bfd_get_section_name (abfd
, sect
);
5783 if (*abip
!= MIPS_ABI_UNKNOWN
)
5786 if (strncmp (name
, ".mdebug.", 8) != 0)
5789 if (strcmp (name
, ".mdebug.abi32") == 0)
5790 *abip
= MIPS_ABI_O32
;
5791 else if (strcmp (name
, ".mdebug.abiN32") == 0)
5792 *abip
= MIPS_ABI_N32
;
5793 else if (strcmp (name
, ".mdebug.abi64") == 0)
5794 *abip
= MIPS_ABI_N64
;
5795 else if (strcmp (name
, ".mdebug.abiO64") == 0)
5796 *abip
= MIPS_ABI_O64
;
5797 else if (strcmp (name
, ".mdebug.eabi32") == 0)
5798 *abip
= MIPS_ABI_EABI32
;
5799 else if (strcmp (name
, ".mdebug.eabi64") == 0)
5800 *abip
= MIPS_ABI_EABI64
;
5802 warning ("unsupported ABI %s.", name
+ 8);
5805 static enum mips_abi
5806 global_mips_abi (void)
5810 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
5811 if (mips_abi_strings
[i
] == mips_abi_string
)
5812 return (enum mips_abi
) i
;
5814 internal_error (__FILE__
, __LINE__
, "unknown ABI string");
5817 static struct gdbarch
*
5818 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
5820 struct gdbarch
*gdbarch
;
5821 struct gdbarch_tdep
*tdep
;
5823 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
5825 enum mips_fpu_type fpu_type
;
5827 /* First of all, extract the elf_flags, if available. */
5828 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
5829 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
5830 else if (arches
!= NULL
)
5831 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
5835 fprintf_unfiltered (gdb_stdlog
,
5836 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
5838 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
5839 switch ((elf_flags
& EF_MIPS_ABI
))
5841 case E_MIPS_ABI_O32
:
5842 found_abi
= MIPS_ABI_O32
;
5844 case E_MIPS_ABI_O64
:
5845 found_abi
= MIPS_ABI_O64
;
5847 case E_MIPS_ABI_EABI32
:
5848 found_abi
= MIPS_ABI_EABI32
;
5850 case E_MIPS_ABI_EABI64
:
5851 found_abi
= MIPS_ABI_EABI64
;
5854 if ((elf_flags
& EF_MIPS_ABI2
))
5855 found_abi
= MIPS_ABI_N32
;
5857 found_abi
= MIPS_ABI_UNKNOWN
;
5861 /* GCC creates a pseudo-section whose name describes the ABI. */
5862 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
5863 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
5865 /* If we have no useful BFD information, use the ABI from the last
5866 MIPS architecture (if there is one). */
5867 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
5868 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
5870 /* Try the architecture for any hint of the correct ABI. */
5871 if (found_abi
== MIPS_ABI_UNKNOWN
5872 && info
.bfd_arch_info
!= NULL
5873 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5875 switch (info
.bfd_arch_info
->mach
)
5877 case bfd_mach_mips3900
:
5878 found_abi
= MIPS_ABI_EABI32
;
5880 case bfd_mach_mips4100
:
5881 case bfd_mach_mips5000
:
5882 found_abi
= MIPS_ABI_EABI64
;
5884 case bfd_mach_mips8000
:
5885 case bfd_mach_mips10000
:
5886 /* On Irix, ELF64 executables use the N64 ABI. The
5887 pseudo-sections which describe the ABI aren't present
5888 on IRIX. (Even for executables created by gcc.) */
5889 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
5890 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5891 found_abi
= MIPS_ABI_N64
;
5893 found_abi
= MIPS_ABI_N32
;
5899 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
5902 /* What has the user specified from the command line? */
5903 wanted_abi
= global_mips_abi ();
5905 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
5908 /* Now that we have found what the ABI for this binary would be,
5909 check whether the user is overriding it. */
5910 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
5911 mips_abi
= wanted_abi
;
5912 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
5913 mips_abi
= found_abi
;
5915 mips_abi
= MIPS_ABI_O32
;
5917 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
5920 /* Also used when doing an architecture lookup. */
5922 fprintf_unfiltered (gdb_stdlog
,
5923 "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n",
5924 mips64_transfers_32bit_regs_p
);
5926 /* Determine the MIPS FPU type. */
5927 if (!mips_fpu_type_auto
)
5928 fpu_type
= mips_fpu_type
;
5929 else if (info
.bfd_arch_info
!= NULL
5930 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5931 switch (info
.bfd_arch_info
->mach
)
5933 case bfd_mach_mips3900
:
5934 case bfd_mach_mips4100
:
5935 case bfd_mach_mips4111
:
5936 case bfd_mach_mips4120
:
5937 fpu_type
= MIPS_FPU_NONE
;
5939 case bfd_mach_mips4650
:
5940 fpu_type
= MIPS_FPU_SINGLE
;
5943 fpu_type
= MIPS_FPU_DOUBLE
;
5946 else if (arches
!= NULL
)
5947 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
5949 fpu_type
= MIPS_FPU_DOUBLE
;
5951 fprintf_unfiltered (gdb_stdlog
,
5952 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
5954 /* try to find a pre-existing architecture */
5955 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
5957 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
5959 /* MIPS needs to be pedantic about which ABI the object is
5961 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
5963 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
5965 /* Need to be pedantic about which register virtual size is
5967 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
5968 != mips64_transfers_32bit_regs_p
)
5970 /* Be pedantic about which FPU is selected. */
5971 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
5973 return arches
->gdbarch
;
5976 /* Need a new architecture. Fill in a target specific vector. */
5977 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
5978 gdbarch
= gdbarch_alloc (&info
, tdep
);
5979 tdep
->elf_flags
= elf_flags
;
5980 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
5981 tdep
->found_abi
= found_abi
;
5982 tdep
->mips_abi
= mips_abi
;
5983 tdep
->mips_fpu_type
= fpu_type
;
5985 /* Initially set everything according to the default ABI/ISA. */
5986 set_gdbarch_short_bit (gdbarch
, 16);
5987 set_gdbarch_int_bit (gdbarch
, 32);
5988 set_gdbarch_float_bit (gdbarch
, 32);
5989 set_gdbarch_double_bit (gdbarch
, 64);
5990 set_gdbarch_long_double_bit (gdbarch
, 64);
5991 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
5992 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
5993 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
5995 set_gdbarch_elf_make_msymbol_special (gdbarch
,
5996 mips_elf_make_msymbol_special
);
5998 /* Fill in the OS dependant register numbers and names. */
6000 const char **reg_names
;
6001 struct mips_regnum
*regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
,
6002 struct mips_regnum
);
6003 if (info
.osabi
== GDB_OSABI_IRIX
)
6008 regnum
->badvaddr
= 66;
6011 regnum
->fp_control_status
= 69;
6012 regnum
->fp_implementation_revision
= 70;
6014 reg_names
= mips_irix_reg_names
;
6018 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
6019 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
6020 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
6021 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
6022 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
6023 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
6024 regnum
->fp_control_status
= 70;
6025 regnum
->fp_implementation_revision
= 71;
6027 if (info
.bfd_arch_info
!= NULL
6028 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
6029 reg_names
= mips_tx39_reg_names
;
6031 reg_names
= mips_generic_reg_names
;
6033 /* FIXME: cagney/2003-11-15: For MIPS, hasn't PC_REGNUM been
6034 replaced by read_pc? */
6035 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
6036 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
6037 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
6038 set_gdbarch_num_regs (gdbarch
, num_regs
);
6039 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
6040 set_gdbarch_register_name (gdbarch
, mips_register_name
);
6041 tdep
->mips_processor_reg_names
= reg_names
;
6042 tdep
->regnum
= regnum
;
6048 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
6049 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
6050 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
6051 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
6052 tdep
->default_mask_address_p
= 0;
6053 set_gdbarch_long_bit (gdbarch
, 32);
6054 set_gdbarch_ptr_bit (gdbarch
, 32);
6055 set_gdbarch_long_long_bit (gdbarch
, 64);
6058 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
6059 set_gdbarch_deprecated_store_return_value (gdbarch
,
6060 mips_o64_store_return_value
);
6061 set_gdbarch_deprecated_extract_return_value (gdbarch
,
6062 mips_o64_extract_return_value
);
6063 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
6064 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
6065 tdep
->default_mask_address_p
= 0;
6066 set_gdbarch_long_bit (gdbarch
, 32);
6067 set_gdbarch_ptr_bit (gdbarch
, 32);
6068 set_gdbarch_long_long_bit (gdbarch
, 64);
6069 set_gdbarch_deprecated_use_struct_convention (gdbarch
, always_use_struct_convention
);
6071 case MIPS_ABI_EABI32
:
6072 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
6073 set_gdbarch_deprecated_store_return_value (gdbarch
,
6074 mips_eabi_store_return_value
);
6075 set_gdbarch_deprecated_extract_return_value (gdbarch
,
6076 mips_eabi_extract_return_value
);
6077 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
6078 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6079 tdep
->default_mask_address_p
= 0;
6080 set_gdbarch_long_bit (gdbarch
, 32);
6081 set_gdbarch_ptr_bit (gdbarch
, 32);
6082 set_gdbarch_long_long_bit (gdbarch
, 64);
6083 set_gdbarch_deprecated_reg_struct_has_addr
6084 (gdbarch
, mips_eabi_reg_struct_has_addr
);
6085 set_gdbarch_deprecated_use_struct_convention (gdbarch
, mips_eabi_use_struct_convention
);
6087 case MIPS_ABI_EABI64
:
6088 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
6089 set_gdbarch_deprecated_store_return_value (gdbarch
,
6090 mips_eabi_store_return_value
);
6091 set_gdbarch_deprecated_extract_return_value (gdbarch
,
6092 mips_eabi_extract_return_value
);
6093 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
6094 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6095 tdep
->default_mask_address_p
= 0;
6096 set_gdbarch_long_bit (gdbarch
, 64);
6097 set_gdbarch_ptr_bit (gdbarch
, 64);
6098 set_gdbarch_long_long_bit (gdbarch
, 64);
6099 set_gdbarch_deprecated_reg_struct_has_addr
6100 (gdbarch
, mips_eabi_reg_struct_has_addr
);
6101 set_gdbarch_deprecated_use_struct_convention (gdbarch
, mips_eabi_use_struct_convention
);
6104 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
6105 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
6106 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
6107 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6108 tdep
->default_mask_address_p
= 0;
6109 set_gdbarch_long_bit (gdbarch
, 32);
6110 set_gdbarch_ptr_bit (gdbarch
, 32);
6111 set_gdbarch_long_long_bit (gdbarch
, 64);
6112 set_gdbarch_long_double_bit (gdbarch
, 128);
6113 set_gdbarch_long_double_format (gdbarch
,
6114 &floatformat_n32n64_long_double_big
);
6117 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
6118 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
6119 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
6120 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6121 tdep
->default_mask_address_p
= 0;
6122 set_gdbarch_long_bit (gdbarch
, 64);
6123 set_gdbarch_ptr_bit (gdbarch
, 64);
6124 set_gdbarch_long_long_bit (gdbarch
, 64);
6125 set_gdbarch_long_double_bit (gdbarch
, 128);
6126 set_gdbarch_long_double_format (gdbarch
,
6127 &floatformat_n32n64_long_double_big
);
6130 internal_error (__FILE__
, __LINE__
, "unknown ABI in switch");
6133 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
6134 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
6137 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
6138 flag in object files because to do so would make it impossible to
6139 link with libraries compiled without "-gp32". This is
6140 unnecessarily restrictive.
6142 We could solve this problem by adding "-gp32" multilibs to gcc,
6143 but to set this flag before gcc is built with such multilibs will
6144 break too many systems.''
6146 But even more unhelpfully, the default linker output target for
6147 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
6148 for 64-bit programs - you need to change the ABI to change this,
6149 and not all gcc targets support that currently. Therefore using
6150 this flag to detect 32-bit mode would do the wrong thing given
6151 the current gcc - it would make GDB treat these 64-bit programs
6152 as 32-bit programs by default. */
6154 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
6155 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
6156 set_gdbarch_read_sp (gdbarch
, mips_read_sp
);
6158 /* Add/remove bits from an address. The MIPS needs be careful to
6159 ensure that all 32 bit addresses are sign extended to 64 bits. */
6160 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
6162 /* Unwind the frame. */
6163 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
6164 set_gdbarch_unwind_dummy_id (gdbarch
, mips_unwind_dummy_id
);
6166 /* Map debug register numbers onto internal register numbers. */
6167 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
6168 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
6169 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6170 set_gdbarch_dwarf_reg_to_regnum (gdbarch
,
6171 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6172 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
6173 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6174 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
6176 /* MIPS version of CALL_DUMMY */
6178 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
6179 replaced by a command, and all targets will default to on stack
6180 (regardless of the stack's execute status). */
6181 set_gdbarch_call_dummy_location (gdbarch
, AT_SYMBOL
);
6182 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
6184 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
6185 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
6186 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
6188 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
6189 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
6191 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
6193 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
6194 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
6195 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
6197 set_gdbarch_register_type (gdbarch
, mips_register_type
);
6199 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
6201 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
6203 /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT,
6204 HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT
6205 need to all be folded into the target vector. Since they are
6206 being used as guards for STOPPED_BY_WATCHPOINT, why not have
6207 STOPPED_BY_WATCHPOINT return the type of watchpoint that the code
6209 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
6211 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_stub
);
6213 /* NOTE drow/2004-02-11: We overload the core solib trampoline code
6214 to support MIPS16. This is a bad thing. Make sure not to do it
6215 if we have an OS ABI that actually supports shared libraries, since
6216 shared library support is more important. If we have an OS someday
6217 that supports both shared libraries and MIPS16, we'll have to find
6218 a better place for these. */
6219 if (info
.osabi
== GDB_OSABI_UNKNOWN
)
6221 set_gdbarch_in_solib_call_trampoline (gdbarch
, mips_in_call_stub
);
6222 set_gdbarch_in_solib_return_trampoline (gdbarch
, mips_in_return_stub
);
6225 /* Hook in OS ABI-specific overrides, if they have been registered. */
6226 gdbarch_init_osabi (info
, gdbarch
);
6228 /* Unwind the frame. */
6229 frame_unwind_append_sniffer (gdbarch
, mips_stub_frame_sniffer
);
6230 frame_unwind_append_sniffer (gdbarch
, mips_mdebug_frame_sniffer
);
6231 frame_unwind_append_sniffer (gdbarch
, mips_insn16_frame_sniffer
);
6232 frame_unwind_append_sniffer (gdbarch
, mips_insn32_frame_sniffer
);
6233 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
6234 frame_base_append_sniffer (gdbarch
, mips_mdebug_frame_base_sniffer
);
6235 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
6236 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
6242 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
6244 struct gdbarch_info info
;
6246 /* Force the architecture to update, and (if it's a MIPS architecture)
6247 mips_gdbarch_init will take care of the rest. */
6248 gdbarch_info_init (&info
);
6249 gdbarch_update_p (info
);
6252 /* Print out which MIPS ABI is in use. */
6255 show_mips_abi (char *ignore_args
, int from_tty
)
6257 if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
!= bfd_arch_mips
)
6259 ("The MIPS ABI is unknown because the current architecture is not MIPS.\n");
6262 enum mips_abi global_abi
= global_mips_abi ();
6263 enum mips_abi actual_abi
= mips_abi (current_gdbarch
);
6264 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
6266 if (global_abi
== MIPS_ABI_UNKNOWN
)
6268 ("The MIPS ABI is set automatically (currently \"%s\").\n",
6270 else if (global_abi
== actual_abi
)
6272 ("The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
6276 /* Probably shouldn't happen... */
6278 ("The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n",
6279 actual_abi_str
, mips_abi_strings
[global_abi
]);
6285 mips_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
6287 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
6291 int ef_mips_32bitmode
;
6292 /* determine the ISA */
6293 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
6311 /* determine the size of a pointer */
6312 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
6313 fprintf_unfiltered (file
,
6314 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
6316 fprintf_unfiltered (file
,
6317 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
6319 fprintf_unfiltered (file
,
6320 "mips_dump_tdep: ef_mips_arch = %d\n",
6322 fprintf_unfiltered (file
,
6323 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
6324 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
6325 fprintf_unfiltered (file
,
6326 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
6327 mips_mask_address_p (tdep
),
6328 tdep
->default_mask_address_p
);
6330 fprintf_unfiltered (file
,
6331 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
6332 MIPS_DEFAULT_FPU_TYPE
,
6333 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
6334 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
6335 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
6337 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n", MIPS_EABI
);
6338 fprintf_unfiltered (file
,
6339 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
6341 (MIPS_FPU_TYPE
== MIPS_FPU_NONE
? "none"
6342 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
6343 : MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
6345 fprintf_unfiltered (file
,
6346 "mips_dump_tdep: mips_stack_argsize() = %d\n",
6347 mips_stack_argsize (current_gdbarch
));
6348 fprintf_unfiltered (file
, "mips_dump_tdep: A0_REGNUM = %d\n", A0_REGNUM
);
6349 fprintf_unfiltered (file
,
6350 "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n",
6351 XSTRING (ADDR_BITS_REMOVE (ADDR
)));
6352 fprintf_unfiltered (file
,
6353 "mips_dump_tdep: ATTACH_DETACH # %s\n",
6354 XSTRING (ATTACH_DETACH
));
6355 fprintf_unfiltered (file
,
6356 "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n",
6357 XSTRING (DWARF_REG_TO_REGNUM (REGNUM
)));
6358 fprintf_unfiltered (file
,
6359 "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n",
6360 XSTRING (ECOFF_REG_TO_REGNUM (REGNUM
)));
6361 fprintf_unfiltered (file
,
6362 "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n",
6363 FIRST_EMBED_REGNUM
);
6364 fprintf_unfiltered (file
,
6365 "mips_dump_tdep: DEPRECATED_IGNORE_HELPER_CALL # %s\n",
6366 XSTRING (DEPRECATED_IGNORE_HELPER_CALL (PC
)));
6367 fprintf_unfiltered (file
,
6368 "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n",
6369 XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC
, NAME
)));
6370 fprintf_unfiltered (file
,
6371 "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n",
6372 XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC
, NAME
)));
6373 fprintf_unfiltered (file
,
6374 "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n",
6376 #ifdef MACHINE_CPROC_FP_OFFSET
6377 fprintf_unfiltered (file
,
6378 "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n",
6379 MACHINE_CPROC_FP_OFFSET
);
6381 #ifdef MACHINE_CPROC_PC_OFFSET
6382 fprintf_unfiltered (file
,
6383 "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n",
6384 MACHINE_CPROC_PC_OFFSET
);
6386 #ifdef MACHINE_CPROC_SP_OFFSET
6387 fprintf_unfiltered (file
,
6388 "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n",
6389 MACHINE_CPROC_SP_OFFSET
);
6391 fprintf_unfiltered (file
,
6392 "mips_dump_tdep: MIPS16_INSTLEN = %d\n",
6394 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n");
6395 fprintf_unfiltered (file
,
6396 "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n");
6397 fprintf_unfiltered (file
,
6398 "mips_dump_tdep: MIPS_INSTLEN = %d\n", MIPS_INSTLEN
);
6399 fprintf_unfiltered (file
,
6400 "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n",
6401 MIPS_LAST_ARG_REGNUM
,
6402 MIPS_LAST_ARG_REGNUM
- A0_REGNUM
+ 1);
6403 fprintf_unfiltered (file
,
6404 "mips_dump_tdep: MIPS_NUMREGS = %d\n", MIPS_NUMREGS
);
6405 fprintf_unfiltered (file
,
6406 "mips_dump_tdep: mips_abi_regsize() = %d\n",
6407 mips_abi_regsize (current_gdbarch
));
6408 fprintf_unfiltered (file
,
6409 "mips_dump_tdep: PRID_REGNUM = %d\n", PRID_REGNUM
);
6410 fprintf_unfiltered (file
,
6411 "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n");
6412 fprintf_unfiltered (file
,
6413 "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n");
6414 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_FRAME_REG = function?\n");
6415 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_FREG_MASK = function?\n");
6416 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_FREG_OFFSET = function?\n");
6417 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_HIGH_ADDR = function?\n");
6418 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_LOW_ADDR = function?\n");
6419 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_PC_REG = function?\n");
6420 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_REG_MASK = function?\n");
6421 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_REG_OFFSET = function?\n");
6422 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_SYMBOL = function?\n");
6423 fprintf_unfiltered (file
, "mips_dump_tdep: PS_REGNUM = %d\n", PS_REGNUM
);
6424 fprintf_unfiltered (file
, "mips_dump_tdep: RA_REGNUM = %d\n", RA_REGNUM
);
6426 fprintf_unfiltered (file
,
6427 "mips_dump_tdep: SAVED_BYTES = %d\n", SAVED_BYTES
);
6430 fprintf_unfiltered (file
, "mips_dump_tdep: SAVED_FP = %d\n", SAVED_FP
);
6433 fprintf_unfiltered (file
, "mips_dump_tdep: SAVED_PC = %d\n", SAVED_PC
);
6435 fprintf_unfiltered (file
,
6436 "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n",
6437 XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS
, ARGS
)));
6438 fprintf_unfiltered (file
,
6439 "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n",
6440 XSTRING (SKIP_TRAMPOLINE_CODE (PC
)));
6441 fprintf_unfiltered (file
,
6442 "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n",
6443 XSTRING (SOFTWARE_SINGLE_STEP (SIG
, BP_P
)));
6444 fprintf_unfiltered (file
,
6445 "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n",
6446 SOFTWARE_SINGLE_STEP_P ());
6447 fprintf_unfiltered (file
,
6448 "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n",
6449 XSTRING (STAB_REG_TO_REGNUM (REGNUM
)));
6450 #ifdef STACK_END_ADDR
6451 fprintf_unfiltered (file
,
6452 "mips_dump_tdep: STACK_END_ADDR = %d\n",
6455 fprintf_unfiltered (file
,
6456 "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n",
6457 XSTRING (STEP_SKIPS_DELAY (PC
)));
6458 fprintf_unfiltered (file
,
6459 "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n",
6460 STEP_SKIPS_DELAY_P
);
6461 fprintf_unfiltered (file
,
6462 "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n",
6463 XSTRING (STOPPED_BY_WATCHPOINT (WS
)));
6464 fprintf_unfiltered (file
, "mips_dump_tdep: T9_REGNUM = %d\n", T9_REGNUM
);
6465 fprintf_unfiltered (file
,
6466 "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n");
6467 fprintf_unfiltered (file
,
6468 "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n",
6469 XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT
6470 (TYPE
, CNT
, OTHERTYPE
)));
6472 fprintf_unfiltered (file
,
6473 "mips_dump_tdep: TRACE_CLEAR # %s\n",
6474 XSTRING (TRACE_CLEAR (THREAD
, STATE
)));
6477 fprintf_unfiltered (file
,
6478 "mips_dump_tdep: TRACE_FLAVOR = %d\n", TRACE_FLAVOR
);
6480 #ifdef TRACE_FLAVOR_SIZE
6481 fprintf_unfiltered (file
,
6482 "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n",
6486 fprintf_unfiltered (file
,
6487 "mips_dump_tdep: TRACE_SET # %s\n",
6488 XSTRING (TRACE_SET (X
, STATE
)));
6490 #ifdef UNUSED_REGNUM
6491 fprintf_unfiltered (file
,
6492 "mips_dump_tdep: UNUSED_REGNUM = %d\n", UNUSED_REGNUM
);
6494 fprintf_unfiltered (file
, "mips_dump_tdep: V0_REGNUM = %d\n", V0_REGNUM
);
6495 fprintf_unfiltered (file
,
6496 "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n",
6497 (long) VM_MIN_ADDRESS
);
6498 fprintf_unfiltered (file
,
6499 "mips_dump_tdep: ZERO_REGNUM = %d\n", ZERO_REGNUM
);
6502 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
6505 _initialize_mips_tdep (void)
6507 static struct cmd_list_element
*mipsfpulist
= NULL
;
6508 struct cmd_list_element
*c
;
6510 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
6511 if (MIPS_ABI_LAST
+ 1
6512 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
6513 internal_error (__FILE__
, __LINE__
, "mips_abi_strings out of sync");
6515 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
6517 mips_pdr_data
= register_objfile_data ();
6519 /* Add root prefix command for all "set mips"/"show mips" commands */
6520 add_prefix_cmd ("mips", no_class
, set_mips_command
,
6521 "Various MIPS specific commands.",
6522 &setmipscmdlist
, "set mips ", 0, &setlist
);
6524 add_prefix_cmd ("mips", no_class
, show_mips_command
,
6525 "Various MIPS specific commands.",
6526 &showmipscmdlist
, "show mips ", 0, &showlist
);
6528 /* Allow the user to override the saved register size. */
6529 deprecated_add_show_from_set (add_set_enum_cmd ("saved-gpreg-size",
6532 &mips_abi_regsize_string
, "\
6533 Set size of general purpose registers saved on the stack.\n\
6534 This option can be set to one of:\n\
6535 32 - Force GDB to treat saved GP registers as 32-bit\n\
6536 64 - Force GDB to treat saved GP registers as 64-bit\n\
6537 auto - Allow GDB to use the target's default setting or autodetect the\n\
6538 saved GP register size from information contained in the executable.\n\
6539 (default: auto)", &setmipscmdlist
), &showmipscmdlist
);
6541 /* Allow the user to override the argument stack size. */
6542 deprecated_add_show_from_set
6543 (add_set_enum_cmd ("stack-arg-size",
6546 &mips_stack_argsize_string
, "\
6547 Set the amount of stack space reserved for each argument.\n\
6548 This option can be set to one of:\n\
6549 32 - Force GDB to allocate 32-bit chunks per argument\n\
6550 64 - Force GDB to allocate 64-bit chunks per argument\n\
6551 auto - Allow GDB to determine the correct setting from the current\n\
6552 target and executable (default)", &setmipscmdlist
),
6555 /* Allow the user to override the ABI. */
6556 c
= add_set_enum_cmd
6557 ("abi", class_obscure
, mips_abi_strings
, &mips_abi_string
,
6558 "Set the ABI used by this program.\n"
6559 "This option can be set to one of:\n"
6560 " auto - the default ABI associated with the current binary\n"
6562 " o64\n" " n32\n" " n64\n" " eabi32\n" " eabi64", &setmipscmdlist
);
6563 set_cmd_sfunc (c
, mips_abi_update
);
6564 add_cmd ("abi", class_obscure
, show_mips_abi
,
6565 "Show ABI in use by MIPS target", &showmipscmdlist
);
6567 /* Let the user turn off floating point and set the fence post for
6568 heuristic_proc_start. */
6570 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
6571 "Set use of MIPS floating-point coprocessor.",
6572 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
6573 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
6574 "Select single-precision MIPS floating-point coprocessor.",
6576 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
6577 "Select double-precision MIPS floating-point coprocessor.",
6579 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
6580 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
6581 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
6582 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
6583 "Select no MIPS floating-point coprocessor.", &mipsfpulist
);
6584 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
6585 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
6586 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
6587 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
6588 "Select MIPS floating-point coprocessor automatically.",
6590 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
6591 "Show current use of MIPS floating-point coprocessor target.",
6594 /* We really would like to have both "0" and "unlimited" work, but
6595 command.c doesn't deal with that. So make it a var_zinteger
6596 because the user can always use "999999" or some such for unlimited. */
6597 c
= add_set_cmd ("heuristic-fence-post", class_support
, var_zinteger
,
6598 (char *) &heuristic_fence_post
, "\
6599 Set the distance searched for the start of a function.\n\
6600 If you are debugging a stripped executable, GDB needs to search through the\n\
6601 program for the start of a function. This command sets the distance of the\n\
6602 search. The only need to set it is when debugging a stripped executable.", &setlist
);
6603 /* We need to throw away the frame cache when we set this, since it
6604 might change our ability to get backtraces. */
6605 set_cmd_sfunc (c
, reinit_frame_cache_sfunc
);
6606 deprecated_add_show_from_set (c
, &showlist
);
6608 /* Allow the user to control whether the upper bits of 64-bit
6609 addresses should be zeroed. */
6610 add_setshow_auto_boolean_cmd ("mask-address", no_class
, &mask_address_var
, "\
6611 Set zeroing of upper 32 bits of 64-bit addresses.", "\
6612 Show zeroing of upper 32 bits of 64-bit addresses.", "\
6613 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
6614 allow GDB to determine the correct value.\n", "\
6615 Zerroing of upper 32 bits of 64-bit address is %s.",
6616 NULL
, show_mask_address
, &setmipscmdlist
, &showmipscmdlist
);
6618 /* Allow the user to control the size of 32 bit registers within the
6619 raw remote packet. */
6620 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
6621 &mips64_transfers_32bit_regs_p
, "\
6622 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities.", "\
6623 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities.", "\
6624 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6625 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6626 64 bits for others. Use \"off\" to disable compatibility mode", "\
6627 Compatibility with 64-bit MIPS target that transfers 32-bit quantities is %s.",
6628 set_mips64_transfers_32bit_regs
, NULL
, &setlist
, &showlist
);
6630 /* Debug this files internals. */
6631 deprecated_add_show_from_set
6632 (add_set_cmd ("mips", class_maintenance
, var_zinteger
,
6633 &mips_debug
, "Set mips debugging.\n\
6634 When non-zero, mips specific debugging is enabled.", &setdebuglist
),