1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
6 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
7 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
9 This file is part of GDB.
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software
23 Foundation, Inc., 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
27 #include "gdb_string.h"
39 #include "arch-utils.h"
42 #include "opcode/mips.h"
47 /* A useful bit in the CP0 status register (PS_REGNUM). */
48 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
49 #define ST0_FR (1 << 26)
51 /* The sizes of floating point registers. */
55 MIPS_FPU_SINGLE_REGSIZE
= 4,
56 MIPS_FPU_DOUBLE_REGSIZE
= 8
59 /* All the possible MIPS ABIs. */
71 struct frame_extra_info
73 mips_extra_func_info_t proc_desc
;
77 /* Various MIPS ISA options (related to stack analysis) can be
78 overridden dynamically. Establish an enum/array for managing
81 static const char size_auto
[] = "auto";
82 static const char size_32
[] = "32";
83 static const char size_64
[] = "64";
85 static const char *size_enums
[] = {
92 /* Some MIPS boards don't support floating point while others only
93 support single-precision floating-point operations. See also
94 FP_REGISTER_DOUBLE. */
98 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
99 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
100 MIPS_FPU_NONE
/* No floating point. */
103 #ifndef MIPS_DEFAULT_FPU_TYPE
104 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
106 static int mips_fpu_type_auto
= 1;
107 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
108 #define MIPS_FPU_TYPE mips_fpu_type
110 /* Do not use "TARGET_IS_MIPS64" to test the size of floating point registers */
111 #ifndef FP_REGISTER_DOUBLE
112 #define FP_REGISTER_DOUBLE (REGISTER_VIRTUAL_SIZE(FP0_REGNUM) == 8)
115 static int mips_debug
= 0;
117 /* MIPS specific per-architecture information */
120 /* from the elf header */
123 enum mips_abi mips_abi
;
124 const char *mips_abi_string
;
125 enum mips_fpu_type mips_fpu_type
;
126 int mips_last_arg_regnum
;
127 int mips_last_fp_arg_regnum
;
128 int mips_default_saved_regsize
;
129 int mips_fp_register_double
;
130 int mips_regs_have_home_p
;
131 int mips_default_stack_argsize
;
132 int gdb_target_is_mips64
;
133 int default_mask_address_p
;
138 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
139 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
143 #undef MIPS_LAST_FP_ARG_REGNUM
144 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
148 #undef MIPS_LAST_ARG_REGNUM
149 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
154 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
157 /* Return the currently configured (or set) saved register size. */
160 #undef MIPS_DEFAULT_SAVED_REGSIZE
161 #define MIPS_DEFAULT_SAVED_REGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_saved_regsize)
162 #elif !defined (MIPS_DEFAULT_SAVED_REGSIZE)
163 #define MIPS_DEFAULT_SAVED_REGSIZE MIPS_REGSIZE
166 static const char *mips_saved_regsize_string
= size_auto
;
168 #define MIPS_SAVED_REGSIZE (mips_saved_regsize())
171 mips_saved_regsize (void)
173 if (mips_saved_regsize_string
== size_auto
)
174 return MIPS_DEFAULT_SAVED_REGSIZE
;
175 else if (mips_saved_regsize_string
== size_64
)
177 else /* if (mips_saved_regsize_string == size_32) */
181 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
182 compatiblity mode. A return value of 1 means that we have
183 physical 64-bit registers, but should treat them as 32-bit registers. */
186 mips2_fp_compat (void)
188 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
190 if (REGISTER_RAW_SIZE (FP0_REGNUM
) == 4)
194 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
195 in all the places we deal with FP registers. PR gdb/413. */
196 /* Otherwise check the FR bit in the status register - it controls
197 the FP compatiblity mode. If it is clear we are in compatibility
199 if ((read_register (PS_REGNUM
) & ST0_FR
) == 0)
206 /* Indicate that the ABI makes use of double-precision registers
207 provided by the FPU (rather than combining pairs of registers to
208 form double-precision values). Do not use "TARGET_IS_MIPS64" to
209 determine if the ABI is using double-precision registers. See also
212 #undef FP_REGISTER_DOUBLE
213 #define FP_REGISTER_DOUBLE (gdbarch_tdep (current_gdbarch)->mips_fp_register_double)
216 /* Does the caller allocate a ``home'' for each register used in the
217 function call? The N32 ABI and MIPS_EABI do not, the others do. */
220 #undef MIPS_REGS_HAVE_HOME_P
221 #define MIPS_REGS_HAVE_HOME_P (gdbarch_tdep (current_gdbarch)->mips_regs_have_home_p)
222 #elif !defined (MIPS_REGS_HAVE_HOME_P)
223 #define MIPS_REGS_HAVE_HOME_P (!MIPS_EABI)
226 /* The amount of space reserved on the stack for registers. This is
227 different to MIPS_SAVED_REGSIZE as it determines the alignment of
228 data allocated after the registers have run out. */
231 #undef MIPS_DEFAULT_STACK_ARGSIZE
232 #define MIPS_DEFAULT_STACK_ARGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_stack_argsize)
233 #elif !defined (MIPS_DEFAULT_STACK_ARGSIZE)
234 #define MIPS_DEFAULT_STACK_ARGSIZE (MIPS_DEFAULT_SAVED_REGSIZE)
237 #define MIPS_STACK_ARGSIZE (mips_stack_argsize ())
239 static const char *mips_stack_argsize_string
= size_auto
;
242 mips_stack_argsize (void)
244 if (mips_stack_argsize_string
== size_auto
)
245 return MIPS_DEFAULT_STACK_ARGSIZE
;
246 else if (mips_stack_argsize_string
== size_64
)
248 else /* if (mips_stack_argsize_string == size_32) */
253 #undef GDB_TARGET_IS_MIPS64
254 #define GDB_TARGET_IS_MIPS64 (gdbarch_tdep (current_gdbarch)->gdb_target_is_mips64 + 0)
258 #undef MIPS_DEFAULT_MASK_ADDRESS_P
259 #define MIPS_DEFAULT_MASK_ADDRESS_P (gdbarch_tdep (current_gdbarch)->default_mask_address_p)
260 #elif !defined (MIPS_DEFAULT_MASK_ADDRESS_P)
261 #define MIPS_DEFAULT_MASK_ADDRESS_P (0)
264 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
266 int gdb_print_insn_mips (bfd_vma
, disassemble_info
*);
268 static void mips_print_register (int, int);
270 static mips_extra_func_info_t
271 heuristic_proc_desc (CORE_ADDR
, CORE_ADDR
, struct frame_info
*, int);
273 static CORE_ADDR
heuristic_proc_start (CORE_ADDR
);
275 static CORE_ADDR
read_next_frame_reg (struct frame_info
*, int);
277 int mips_set_processor_type (char *);
279 static void mips_show_processor_type_command (char *, int);
281 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
283 static mips_extra_func_info_t
284 find_proc_desc (CORE_ADDR pc
, struct frame_info
*next_frame
, int cur_frame
);
286 static CORE_ADDR
after_prologue (CORE_ADDR pc
,
287 mips_extra_func_info_t proc_desc
);
289 static void mips_read_fp_register_single (int regno
, char *rare_buffer
);
290 static void mips_read_fp_register_double (int regno
, char *rare_buffer
);
292 static struct type
*mips_float_register_type (void);
293 static struct type
*mips_double_register_type (void);
295 /* This value is the model of MIPS in use. It is derived from the value
296 of the PrID register. */
298 char *mips_processor_type
;
300 char *tmp_mips_processor_type
;
302 /* The list of available "set mips " and "show mips " commands */
304 static struct cmd_list_element
*setmipscmdlist
= NULL
;
305 static struct cmd_list_element
*showmipscmdlist
= NULL
;
307 /* A set of original names, to be used when restoring back to generic
308 registers from a specific set. */
310 char *mips_generic_reg_names
[] = MIPS_REGISTER_NAMES
;
311 char **mips_processor_reg_names
= mips_generic_reg_names
;
314 mips_register_name (int i
)
316 return mips_processor_reg_names
[i
];
319 /* Names of IDT R3041 registers. */
321 char *mips_r3041_reg_names
[] = {
322 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
323 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
324 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
325 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
326 "sr", "lo", "hi", "bad", "cause","pc",
327 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
328 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
329 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
330 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
331 "fsr", "fir", "fp", "",
332 "", "", "bus", "ccfg", "", "", "", "",
333 "", "", "port", "cmp", "", "", "epc", "prid",
336 /* Names of IDT R3051 registers. */
338 char *mips_r3051_reg_names
[] = {
339 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
340 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
341 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
342 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
343 "sr", "lo", "hi", "bad", "cause","pc",
344 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
345 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
346 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
347 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
348 "fsr", "fir", "fp", "",
349 "inx", "rand", "elo", "", "ctxt", "", "", "",
350 "", "", "ehi", "", "", "", "epc", "prid",
353 /* Names of IDT R3081 registers. */
355 char *mips_r3081_reg_names
[] = {
356 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
357 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
358 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
359 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
360 "sr", "lo", "hi", "bad", "cause","pc",
361 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
362 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
363 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
364 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
365 "fsr", "fir", "fp", "",
366 "inx", "rand", "elo", "cfg", "ctxt", "", "", "",
367 "", "", "ehi", "", "", "", "epc", "prid",
370 /* Names of LSI 33k registers. */
372 char *mips_lsi33k_reg_names
[] = {
373 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
374 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
375 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
376 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
377 "epc", "hi", "lo", "sr", "cause","badvaddr",
378 "dcic", "bpc", "bda", "", "", "", "", "",
379 "", "", "", "", "", "", "", "",
380 "", "", "", "", "", "", "", "",
381 "", "", "", "", "", "", "", "",
383 "", "", "", "", "", "", "", "",
384 "", "", "", "", "", "", "", "",
390 } mips_processor_type_table
[] = {
391 { "generic", mips_generic_reg_names
},
392 { "r3041", mips_r3041_reg_names
},
393 { "r3051", mips_r3051_reg_names
},
394 { "r3071", mips_r3081_reg_names
},
395 { "r3081", mips_r3081_reg_names
},
396 { "lsi33k", mips_lsi33k_reg_names
},
404 /* Table to translate MIPS16 register field to actual register number. */
405 static int mips16_to_32_reg
[8] =
406 {16, 17, 2, 3, 4, 5, 6, 7};
408 /* Heuristic_proc_start may hunt through the text section for a long
409 time across a 2400 baud serial line. Allows the user to limit this
412 static unsigned int heuristic_fence_post
= 0;
414 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
415 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
416 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
417 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
418 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
419 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
420 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
421 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
422 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
423 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
424 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
425 #define _PROC_MAGIC_ 0x0F0F0F0F
426 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
427 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
429 struct linked_proc_info
431 struct mips_extra_func_info info
;
432 struct linked_proc_info
*next
;
434 *linked_proc_desc_table
= NULL
;
437 mips_print_extra_frame_info (struct frame_info
*fi
)
441 && fi
->extra_info
->proc_desc
442 && fi
->extra_info
->proc_desc
->pdr
.framereg
< NUM_REGS
)
443 printf_filtered (" frame pointer is at %s+%s\n",
444 REGISTER_NAME (fi
->extra_info
->proc_desc
->pdr
.framereg
),
445 paddr_d (fi
->extra_info
->proc_desc
->pdr
.frameoffset
));
448 /* Number of bytes of storage in the actual machine representation for
449 register N. NOTE: This indirectly defines the register size
450 transfered by the GDB protocol. */
452 static int mips64_transfers_32bit_regs_p
= 0;
455 mips_register_raw_size (int reg_nr
)
457 if (mips64_transfers_32bit_regs_p
)
458 return REGISTER_VIRTUAL_SIZE (reg_nr
);
459 else if (reg_nr
>= FP0_REGNUM
&& reg_nr
< FP0_REGNUM
+ 32
460 && FP_REGISTER_DOUBLE
)
461 /* For MIPS_ABI_N32 (for example) we need 8 byte floating point
468 /* Convert between RAW and VIRTUAL registers. The RAW register size
469 defines the remote-gdb packet. */
472 mips_register_convertible (int reg_nr
)
474 if (mips64_transfers_32bit_regs_p
)
477 return (REGISTER_RAW_SIZE (reg_nr
) > REGISTER_VIRTUAL_SIZE (reg_nr
));
481 mips_register_convert_to_virtual (int n
, struct type
*virtual_type
,
482 char *raw_buf
, char *virt_buf
)
484 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
486 raw_buf
+ (REGISTER_RAW_SIZE (n
) - TYPE_LENGTH (virtual_type
)),
487 TYPE_LENGTH (virtual_type
));
491 TYPE_LENGTH (virtual_type
));
495 mips_register_convert_to_raw (struct type
*virtual_type
, int n
,
496 char *virt_buf
, char *raw_buf
)
498 memset (raw_buf
, 0, REGISTER_RAW_SIZE (n
));
499 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
500 memcpy (raw_buf
+ (REGISTER_RAW_SIZE (n
) - TYPE_LENGTH (virtual_type
)),
502 TYPE_LENGTH (virtual_type
));
506 TYPE_LENGTH (virtual_type
));
509 /* Should the upper word of 64-bit addresses be zeroed? */
510 enum cmd_auto_boolean mask_address_var
= CMD_AUTO_BOOLEAN_AUTO
;
513 mips_mask_address_p (void)
515 switch (mask_address_var
)
517 case CMD_AUTO_BOOLEAN_TRUE
:
519 case CMD_AUTO_BOOLEAN_FALSE
:
522 case CMD_AUTO_BOOLEAN_AUTO
:
523 return MIPS_DEFAULT_MASK_ADDRESS_P
;
525 internal_error (__FILE__
, __LINE__
,
526 "mips_mask_address_p: bad switch");
532 show_mask_address (char *cmd
, int from_tty
)
534 switch (mask_address_var
)
536 case CMD_AUTO_BOOLEAN_TRUE
:
537 printf_filtered ("The 32 bit mips address mask is enabled\n");
539 case CMD_AUTO_BOOLEAN_FALSE
:
540 printf_filtered ("The 32 bit mips address mask is disabled\n");
542 case CMD_AUTO_BOOLEAN_AUTO
:
543 printf_filtered ("The 32 bit address mask is set automatically. Currently %s\n",
544 mips_mask_address_p () ? "enabled" : "disabled");
547 internal_error (__FILE__
, __LINE__
,
548 "show_mask_address: bad switch");
553 /* Should call_function allocate stack space for a struct return? */
555 mips_use_struct_convention (int gcc_p
, struct type
*type
)
558 return (TYPE_LENGTH (type
) > 2 * MIPS_SAVED_REGSIZE
);
560 return 1; /* Structures are returned by ref in extra arg0 */
563 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
566 pc_is_mips16 (bfd_vma memaddr
)
568 struct minimal_symbol
*sym
;
570 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
571 if (IS_MIPS16_ADDR (memaddr
))
574 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
575 the high bit of the info field. Use this to decide if the function is
576 MIPS16 or normal MIPS. */
577 sym
= lookup_minimal_symbol_by_pc (memaddr
);
579 return MSYMBOL_IS_SPECIAL (sym
);
584 /* MIPS believes that the PC has a sign extended value. Perhaphs the
585 all registers should be sign extended for simplicity? */
588 mips_read_pc (ptid_t ptid
)
590 return read_signed_register_pid (PC_REGNUM
, ptid
);
593 /* This returns the PC of the first inst after the prologue. If we can't
594 find the prologue, then return 0. */
597 after_prologue (CORE_ADDR pc
,
598 mips_extra_func_info_t proc_desc
)
600 struct symtab_and_line sal
;
601 CORE_ADDR func_addr
, func_end
;
603 /* Pass cur_frame == 0 to find_proc_desc. We should not attempt
604 to read the stack pointer from the current machine state, because
605 the current machine state has nothing to do with the information
606 we need from the proc_desc; and the process may or may not exist
609 proc_desc
= find_proc_desc (pc
, NULL
, 0);
613 /* If function is frameless, then we need to do it the hard way. I
614 strongly suspect that frameless always means prologueless... */
615 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
616 && PROC_FRAME_OFFSET (proc_desc
) == 0)
620 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
621 return 0; /* Unknown */
623 sal
= find_pc_line (func_addr
, 0);
625 if (sal
.end
< func_end
)
628 /* The line after the prologue is after the end of the function. In this
629 case, tell the caller to find the prologue the hard way. */
634 /* Decode a MIPS32 instruction that saves a register in the stack, and
635 set the appropriate bit in the general register mask or float register mask
636 to indicate which register is saved. This is a helper function
637 for mips_find_saved_regs. */
640 mips32_decode_reg_save (t_inst inst
, unsigned long *gen_mask
,
641 unsigned long *float_mask
)
645 if ((inst
& 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
646 || (inst
& 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
647 || (inst
& 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
649 /* It might be possible to use the instruction to
650 find the offset, rather than the code below which
651 is based on things being in a certain order in the
652 frame, but figuring out what the instruction's offset
653 is relative to might be a little tricky. */
654 reg
= (inst
& 0x001f0000) >> 16;
655 *gen_mask
|= (1 << reg
);
657 else if ((inst
& 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
658 || (inst
& 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
659 || (inst
& 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */
662 reg
= ((inst
& 0x001f0000) >> 16);
663 *float_mask
|= (1 << reg
);
667 /* Decode a MIPS16 instruction that saves a register in the stack, and
668 set the appropriate bit in the general register or float register mask
669 to indicate which register is saved. This is a helper function
670 for mips_find_saved_regs. */
673 mips16_decode_reg_save (t_inst inst
, unsigned long *gen_mask
)
675 if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
677 int reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
678 *gen_mask
|= (1 << reg
);
680 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
682 int reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
683 *gen_mask
|= (1 << reg
);
685 else if ((inst
& 0xff00) == 0x6200 /* sw $ra,n($sp) */
686 || (inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
687 *gen_mask
|= (1 << RA_REGNUM
);
691 /* Fetch and return instruction from the specified location. If the PC
692 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
695 mips_fetch_instruction (CORE_ADDR addr
)
697 char buf
[MIPS_INSTLEN
];
701 if (pc_is_mips16 (addr
))
703 instlen
= MIPS16_INSTLEN
;
704 addr
= UNMAKE_MIPS16_ADDR (addr
);
707 instlen
= MIPS_INSTLEN
;
708 status
= read_memory_nobpt (addr
, buf
, instlen
);
710 memory_error (status
, addr
);
711 return extract_unsigned_integer (buf
, instlen
);
715 /* These the fields of 32 bit mips instructions */
716 #define mips32_op(x) (x >> 26)
717 #define itype_op(x) (x >> 26)
718 #define itype_rs(x) ((x >> 21) & 0x1f)
719 #define itype_rt(x) ((x >> 16) & 0x1f)
720 #define itype_immediate(x) (x & 0xffff)
722 #define jtype_op(x) (x >> 26)
723 #define jtype_target(x) (x & 0x03ffffff)
725 #define rtype_op(x) (x >> 26)
726 #define rtype_rs(x) ((x >> 21) & 0x1f)
727 #define rtype_rt(x) ((x >> 16) & 0x1f)
728 #define rtype_rd(x) ((x >> 11) & 0x1f)
729 #define rtype_shamt(x) ((x >> 6) & 0x1f)
730 #define rtype_funct(x) (x & 0x3f)
733 mips32_relative_offset (unsigned long inst
)
736 x
= itype_immediate (inst
);
737 if (x
& 0x8000) /* sign bit set */
739 x
|= 0xffff0000; /* sign extension */
745 /* Determine whate to set a single step breakpoint while considering
748 mips32_next_pc (CORE_ADDR pc
)
752 inst
= mips_fetch_instruction (pc
);
753 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch instruction */
755 if (itype_op (inst
) >> 2 == 5)
756 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
758 op
= (itype_op (inst
) & 0x03);
773 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
774 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
776 int tf
= itype_rt (inst
) & 0x01;
777 int cnum
= itype_rt (inst
) >> 2;
778 int fcrcs
= read_signed_register (FCRCS_REGNUM
);
779 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
781 if (((cond
>> cnum
) & 0x01) == tf
)
782 pc
+= mips32_relative_offset (inst
) + 4;
787 pc
+= 4; /* Not a branch, next instruction is easy */
790 { /* This gets way messy */
792 /* Further subdivide into SPECIAL, REGIMM and other */
793 switch (op
= itype_op (inst
) & 0x07) /* extract bits 28,27,26 */
795 case 0: /* SPECIAL */
796 op
= rtype_funct (inst
);
801 /* Set PC to that address */
802 pc
= read_signed_register (rtype_rs (inst
));
808 break; /* end SPECIAL */
811 op
= itype_rt (inst
); /* branch condition */
816 case 16: /* BLTZAL */
817 case 18: /* BLTZALL */
819 if (read_signed_register (itype_rs (inst
)) < 0)
820 pc
+= mips32_relative_offset (inst
) + 4;
822 pc
+= 8; /* after the delay slot */
826 case 17: /* BGEZAL */
827 case 19: /* BGEZALL */
828 greater_equal_branch
:
829 if (read_signed_register (itype_rs (inst
)) >= 0)
830 pc
+= mips32_relative_offset (inst
) + 4;
832 pc
+= 8; /* after the delay slot */
834 /* All of the other instructions in the REGIMM category */
839 break; /* end REGIMM */
844 reg
= jtype_target (inst
) << 2;
845 /* Upper four bits get never changed... */
846 pc
= reg
+ ((pc
+ 4) & 0xf0000000);
849 /* FIXME case JALX : */
852 reg
= jtype_target (inst
) << 2;
853 pc
= reg
+ ((pc
+ 4) & 0xf0000000) + 1; /* yes, +1 */
854 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
856 break; /* The new PC will be alternate mode */
857 case 4: /* BEQ, BEQL */
859 if (read_signed_register (itype_rs (inst
)) ==
860 read_signed_register (itype_rt (inst
)))
861 pc
+= mips32_relative_offset (inst
) + 4;
865 case 5: /* BNE, BNEL */
867 if (read_signed_register (itype_rs (inst
)) !=
868 read_signed_register (itype_rt (inst
)))
869 pc
+= mips32_relative_offset (inst
) + 4;
873 case 6: /* BLEZ, BLEZL */
875 if (read_signed_register (itype_rs (inst
) <= 0))
876 pc
+= mips32_relative_offset (inst
) + 4;
882 greater_branch
: /* BGTZ, BGTZL */
883 if (read_signed_register (itype_rs (inst
) > 0))
884 pc
+= mips32_relative_offset (inst
) + 4;
891 } /* mips32_next_pc */
893 /* Decoding the next place to set a breakpoint is irregular for the
894 mips 16 variant, but fortunately, there fewer instructions. We have to cope
895 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
896 We dont want to set a single step instruction on the extend instruction
900 /* Lots of mips16 instruction formats */
901 /* Predicting jumps requires itype,ritype,i8type
902 and their extensions extItype,extritype,extI8type
904 enum mips16_inst_fmts
906 itype
, /* 0 immediate 5,10 */
907 ritype
, /* 1 5,3,8 */
908 rrtype
, /* 2 5,3,3,5 */
909 rritype
, /* 3 5,3,3,5 */
910 rrrtype
, /* 4 5,3,3,3,2 */
911 rriatype
, /* 5 5,3,3,1,4 */
912 shifttype
, /* 6 5,3,3,3,2 */
913 i8type
, /* 7 5,3,8 */
914 i8movtype
, /* 8 5,3,3,5 */
915 i8mov32rtype
, /* 9 5,3,5,3 */
916 i64type
, /* 10 5,3,8 */
917 ri64type
, /* 11 5,3,3,5 */
918 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
919 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
920 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
921 extRRItype
, /* 15 5,5,5,5,3,3,5 */
922 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
923 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
924 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
925 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
926 extRi64type
, /* 20 5,6,5,5,3,3,5 */
927 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
929 /* I am heaping all the fields of the formats into one structure and
930 then, only the fields which are involved in instruction extension */
934 unsigned int regx
; /* Function in i8 type */
939 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
940 for the bits which make up the immediatate extension. */
943 extended_offset (unsigned int extension
)
946 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
948 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
950 value
|= extension
& 0x01f; /* extract 4:0 */
954 /* Only call this function if you know that this is an extendable
955 instruction, It wont malfunction, but why make excess remote memory references?
956 If the immediate operands get sign extended or somthing, do it after
957 the extension is performed.
959 /* FIXME: Every one of these cases needs to worry about sign extension
960 when the offset is to be used in relative addressing */
964 fetch_mips_16 (CORE_ADDR pc
)
967 pc
&= 0xfffffffe; /* clear the low order bit */
968 target_read_memory (pc
, buf
, 2);
969 return extract_unsigned_integer (buf
, 2);
973 unpack_mips16 (CORE_ADDR pc
,
974 unsigned int extension
,
976 enum mips16_inst_fmts insn_format
,
977 struct upk_mips16
*upk
)
989 value
= extended_offset (extension
);
990 value
= value
<< 11; /* rom for the original value */
991 value
|= inst
& 0x7ff; /* eleven bits from instruction */
995 value
= inst
& 0x7ff;
996 /* FIXME : Consider sign extension */
1005 { /* A register identifier and an offset */
1006 /* Most of the fields are the same as I type but the
1007 immediate value is of a different length */
1011 value
= extended_offset (extension
);
1012 value
= value
<< 8; /* from the original instruction */
1013 value
|= inst
& 0xff; /* eleven bits from instruction */
1014 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
1015 if (value
& 0x4000) /* test the sign bit , bit 26 */
1017 value
&= ~0x3fff; /* remove the sign bit */
1023 value
= inst
& 0xff; /* 8 bits */
1024 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
1025 /* FIXME: Do sign extension , this format needs it */
1026 if (value
& 0x80) /* THIS CONFUSES ME */
1028 value
&= 0xef; /* remove the sign bit */
1038 unsigned long value
;
1039 unsigned int nexthalf
;
1040 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1041 value
= value
<< 16;
1042 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
1050 internal_error (__FILE__
, __LINE__
,
1053 upk
->offset
= offset
;
1060 add_offset_16 (CORE_ADDR pc
, int offset
)
1062 return ((offset
<< 2) | ((pc
+ 2) & (0xf0000000)));
1067 extended_mips16_next_pc (CORE_ADDR pc
,
1068 unsigned int extension
,
1071 int op
= (insn
>> 11);
1074 case 2: /* Branch */
1077 struct upk_mips16 upk
;
1078 unpack_mips16 (pc
, extension
, insn
, itype
, &upk
);
1079 offset
= upk
.offset
;
1085 pc
+= (offset
<< 1) + 2;
1088 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1090 struct upk_mips16 upk
;
1091 unpack_mips16 (pc
, extension
, insn
, jalxtype
, &upk
);
1092 pc
= add_offset_16 (pc
, upk
.offset
);
1093 if ((insn
>> 10) & 0x01) /* Exchange mode */
1094 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1101 struct upk_mips16 upk
;
1103 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1104 reg
= read_signed_register (upk
.regx
);
1106 pc
+= (upk
.offset
<< 1) + 2;
1113 struct upk_mips16 upk
;
1115 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1116 reg
= read_signed_register (upk
.regx
);
1118 pc
+= (upk
.offset
<< 1) + 2;
1123 case 12: /* I8 Formats btez btnez */
1125 struct upk_mips16 upk
;
1127 unpack_mips16 (pc
, extension
, insn
, i8type
, &upk
);
1128 /* upk.regx contains the opcode */
1129 reg
= read_signed_register (24); /* Test register is 24 */
1130 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1131 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1132 /* pc = add_offset_16(pc,upk.offset) ; */
1133 pc
+= (upk
.offset
<< 1) + 2;
1138 case 29: /* RR Formats JR, JALR, JALR-RA */
1140 struct upk_mips16 upk
;
1141 /* upk.fmt = rrtype; */
1146 upk
.regx
= (insn
>> 8) & 0x07;
1147 upk
.regy
= (insn
>> 5) & 0x07;
1155 break; /* Function return instruction */
1161 break; /* BOGUS Guess */
1163 pc
= read_signed_register (reg
);
1170 /* This is an instruction extension. Fetch the real instruction
1171 (which follows the extension) and decode things based on
1175 pc
= extended_mips16_next_pc (pc
, insn
, fetch_mips_16 (pc
));
1188 mips16_next_pc (CORE_ADDR pc
)
1190 unsigned int insn
= fetch_mips_16 (pc
);
1191 return extended_mips16_next_pc (pc
, 0, insn
);
1194 /* The mips_next_pc function supports single_step when the remote
1195 target monitor or stub is not developed enough to do a single_step.
1196 It works by decoding the current instruction and predicting where a
1197 branch will go. This isnt hard because all the data is available.
1198 The MIPS32 and MIPS16 variants are quite different */
1200 mips_next_pc (CORE_ADDR pc
)
1203 return mips16_next_pc (pc
);
1205 return mips32_next_pc (pc
);
1208 /* Guaranteed to set fci->saved_regs to some values (it never leaves it
1212 mips_find_saved_regs (struct frame_info
*fci
)
1215 CORE_ADDR reg_position
;
1216 /* r0 bit means kernel trap */
1218 /* What registers have been saved? Bitmasks. */
1219 unsigned long gen_mask
, float_mask
;
1220 mips_extra_func_info_t proc_desc
;
1223 frame_saved_regs_zalloc (fci
);
1225 /* If it is the frame for sigtramp, the saved registers are located
1226 in a sigcontext structure somewhere on the stack.
1227 If the stack layout for sigtramp changes we might have to change these
1228 constants and the companion fixup_sigtramp in mdebugread.c */
1229 #ifndef SIGFRAME_BASE
1230 /* To satisfy alignment restrictions, sigcontext is located 4 bytes
1231 above the sigtramp frame. */
1232 #define SIGFRAME_BASE MIPS_REGSIZE
1233 /* FIXME! Are these correct?? */
1234 #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * MIPS_REGSIZE)
1235 #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * MIPS_REGSIZE)
1236 #define SIGFRAME_FPREGSAVE_OFF \
1237 (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * MIPS_REGSIZE + 3 * MIPS_REGSIZE)
1239 #ifndef SIGFRAME_REG_SIZE
1240 /* FIXME! Is this correct?? */
1241 #define SIGFRAME_REG_SIZE MIPS_REGSIZE
1243 if (fci
->signal_handler_caller
)
1245 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1247 reg_position
= fci
->frame
+ SIGFRAME_REGSAVE_OFF
1248 + ireg
* SIGFRAME_REG_SIZE
;
1249 fci
->saved_regs
[ireg
] = reg_position
;
1251 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1253 reg_position
= fci
->frame
+ SIGFRAME_FPREGSAVE_OFF
1254 + ireg
* SIGFRAME_REG_SIZE
;
1255 fci
->saved_regs
[FP0_REGNUM
+ ireg
] = reg_position
;
1257 fci
->saved_regs
[PC_REGNUM
] = fci
->frame
+ SIGFRAME_PC_OFF
;
1261 proc_desc
= fci
->extra_info
->proc_desc
;
1262 if (proc_desc
== NULL
)
1263 /* I'm not sure how/whether this can happen. Normally when we can't
1264 find a proc_desc, we "synthesize" one using heuristic_proc_desc
1265 and set the saved_regs right away. */
1268 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1269 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
1270 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
1272 if ( /* In any frame other than the innermost or a frame interrupted by
1273 a signal, we assume that all registers have been saved.
1274 This assumes that all register saves in a function happen before
1275 the first function call. */
1276 (fci
->next
== NULL
|| fci
->next
->signal_handler_caller
)
1278 /* In a dummy frame we know exactly where things are saved. */
1279 && !PROC_DESC_IS_DUMMY (proc_desc
)
1281 /* Don't bother unless we are inside a function prologue. Outside the
1282 prologue, we know where everything is. */
1284 && in_prologue (fci
->pc
, PROC_LOW_ADDR (proc_desc
))
1286 /* Not sure exactly what kernel_trap means, but if it means
1287 the kernel saves the registers without a prologue doing it,
1288 we better not examine the prologue to see whether registers
1289 have been saved yet. */
1292 /* We need to figure out whether the registers that the proc_desc
1293 claims are saved have been saved yet. */
1297 /* Bitmasks; set if we have found a save for the register. */
1298 unsigned long gen_save_found
= 0;
1299 unsigned long float_save_found
= 0;
1302 /* If the address is odd, assume this is MIPS16 code. */
1303 addr
= PROC_LOW_ADDR (proc_desc
);
1304 instlen
= pc_is_mips16 (addr
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1306 /* Scan through this function's instructions preceding the current
1307 PC, and look for those that save registers. */
1308 while (addr
< fci
->pc
)
1310 inst
= mips_fetch_instruction (addr
);
1311 if (pc_is_mips16 (addr
))
1312 mips16_decode_reg_save (inst
, &gen_save_found
);
1314 mips32_decode_reg_save (inst
, &gen_save_found
, &float_save_found
);
1317 gen_mask
= gen_save_found
;
1318 float_mask
= float_save_found
;
1321 /* Fill in the offsets for the registers which gen_mask says
1323 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
1324 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
1325 if (gen_mask
& 0x80000000)
1327 fci
->saved_regs
[ireg
] = reg_position
;
1328 reg_position
-= MIPS_SAVED_REGSIZE
;
1331 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse order
1332 of that normally used by gcc. Therefore, we have to fetch the first
1333 instruction of the function, and if it's an entry instruction that
1334 saves $s0 or $s1, correct their saved addresses. */
1335 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
1337 inst
= mips_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
1338 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1341 int sreg_count
= (inst
>> 6) & 3;
1343 /* Check if the ra register was pushed on the stack. */
1344 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
1346 reg_position
-= MIPS_SAVED_REGSIZE
;
1348 /* Check if the s0 and s1 registers were pushed on the stack. */
1349 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1351 fci
->saved_regs
[reg
] = reg_position
;
1352 reg_position
-= MIPS_SAVED_REGSIZE
;
1357 /* Fill in the offsets for the registers which float_mask says
1359 reg_position
= fci
->frame
+ PROC_FREG_OFFSET (proc_desc
);
1361 /* The freg_offset points to where the first *double* register
1362 is saved. So skip to the high-order word. */
1363 if (!GDB_TARGET_IS_MIPS64
)
1364 reg_position
+= MIPS_SAVED_REGSIZE
;
1366 /* Fill in the offsets for the float registers which float_mask says
1368 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
1369 if (float_mask
& 0x80000000)
1371 fci
->saved_regs
[FP0_REGNUM
+ ireg
] = reg_position
;
1372 reg_position
-= MIPS_SAVED_REGSIZE
;
1375 fci
->saved_regs
[PC_REGNUM
] = fci
->saved_regs
[RA_REGNUM
];
1379 read_next_frame_reg (struct frame_info
*fi
, int regno
)
1381 for (; fi
; fi
= fi
->next
)
1383 /* We have to get the saved sp from the sigcontext
1384 if it is a signal handler frame. */
1385 if (regno
== SP_REGNUM
&& !fi
->signal_handler_caller
)
1389 if (fi
->saved_regs
== NULL
)
1390 mips_find_saved_regs (fi
);
1391 if (fi
->saved_regs
[regno
])
1392 return read_memory_integer (ADDR_BITS_REMOVE (fi
->saved_regs
[regno
]), MIPS_SAVED_REGSIZE
);
1395 return read_signed_register (regno
);
1398 /* mips_addr_bits_remove - remove useless address bits */
1401 mips_addr_bits_remove (CORE_ADDR addr
)
1403 if (GDB_TARGET_IS_MIPS64
)
1405 if (mips_mask_address_p () && (addr
>> 32 == (CORE_ADDR
) 0xffffffff))
1407 /* This hack is a work-around for existing boards using
1408 PMON, the simulator, and any other 64-bit targets that
1409 doesn't have true 64-bit addressing. On these targets,
1410 the upper 32 bits of addresses are ignored by the
1411 hardware. Thus, the PC or SP are likely to have been
1412 sign extended to all 1s by instruction sequences that
1413 load 32-bit addresses. For example, a typical piece of
1414 code that loads an address is this:
1415 lui $r2, <upper 16 bits>
1416 ori $r2, <lower 16 bits>
1417 But the lui sign-extends the value such that the upper 32
1418 bits may be all 1s. The workaround is simply to mask off
1419 these bits. In the future, gcc may be changed to support
1420 true 64-bit addressing, and this masking will have to be
1422 addr
&= (CORE_ADDR
) 0xffffffff;
1425 else if (mips_mask_address_p ())
1427 /* FIXME: This is wrong! mips_addr_bits_remove() shouldn't be
1428 masking off bits, instead, the actual target should be asking
1429 for the address to be converted to a valid pointer. */
1430 /* Even when GDB is configured for some 32-bit targets
1431 (e.g. mips-elf), BFD is configured to handle 64-bit targets,
1432 so CORE_ADDR is 64 bits. So we still have to mask off
1433 useless bits from addresses. */
1434 addr
&= (CORE_ADDR
) 0xffffffff;
1439 /* mips_software_single_step() is called just before we want to resume
1440 the inferior, if we want to single-step it but there is no hardware
1441 or kernel single-step support (MIPS on GNU/Linux for example). We find
1442 the target of the coming instruction and breakpoint it.
1444 single_step is also called just after the inferior stops. If we had
1445 set up a simulated single-step, we undo our damage. */
1448 mips_software_single_step (enum target_signal sig
, int insert_breakpoints_p
)
1450 static CORE_ADDR next_pc
;
1451 typedef char binsn_quantum
[BREAKPOINT_MAX
];
1452 static binsn_quantum break_mem
;
1455 if (insert_breakpoints_p
)
1457 pc
= read_register (PC_REGNUM
);
1458 next_pc
= mips_next_pc (pc
);
1460 target_insert_breakpoint (next_pc
, break_mem
);
1463 target_remove_breakpoint (next_pc
, break_mem
);
1467 mips_init_frame_pc_first (int fromleaf
, struct frame_info
*prev
)
1471 pc
= ((fromleaf
) ? SAVED_PC_AFTER_CALL (prev
->next
) :
1472 prev
->next
? FRAME_SAVED_PC (prev
->next
) : read_pc ());
1473 tmp
= mips_skip_stub (pc
);
1474 prev
->pc
= tmp
? tmp
: pc
;
1479 mips_frame_saved_pc (struct frame_info
*frame
)
1482 mips_extra_func_info_t proc_desc
= frame
->extra_info
->proc_desc
;
1483 /* We have to get the saved pc from the sigcontext
1484 if it is a signal handler frame. */
1485 int pcreg
= frame
->signal_handler_caller
? PC_REGNUM
1486 : (proc_desc
? PROC_PC_REG (proc_desc
) : RA_REGNUM
);
1488 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
1489 saved_pc
= read_memory_integer (frame
->frame
- MIPS_SAVED_REGSIZE
, MIPS_SAVED_REGSIZE
);
1491 saved_pc
= read_next_frame_reg (frame
, pcreg
);
1493 return ADDR_BITS_REMOVE (saved_pc
);
1496 static struct mips_extra_func_info temp_proc_desc
;
1497 static CORE_ADDR temp_saved_regs
[NUM_REGS
];
1499 /* Set a register's saved stack address in temp_saved_regs. If an address
1500 has already been set for this register, do nothing; this way we will
1501 only recognize the first save of a given register in a function prologue.
1502 This is a helper function for mips{16,32}_heuristic_proc_desc. */
1505 set_reg_offset (int regno
, CORE_ADDR offset
)
1507 if (temp_saved_regs
[regno
] == 0)
1508 temp_saved_regs
[regno
] = offset
;
1512 /* Test whether the PC points to the return instruction at the
1513 end of a function. */
1516 mips_about_to_return (CORE_ADDR pc
)
1518 if (pc_is_mips16 (pc
))
1519 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
1520 generates a "jr $ra"; other times it generates code to load
1521 the return address from the stack to an accessible register (such
1522 as $a3), then a "jr" using that register. This second case
1523 is almost impossible to distinguish from an indirect jump
1524 used for switch statements, so we don't even try. */
1525 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
1527 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
1531 /* This fencepost looks highly suspicious to me. Removing it also
1532 seems suspicious as it could affect remote debugging across serial
1536 heuristic_proc_start (CORE_ADDR pc
)
1543 pc
= ADDR_BITS_REMOVE (pc
);
1545 fence
= start_pc
- heuristic_fence_post
;
1549 if (heuristic_fence_post
== UINT_MAX
1550 || fence
< VM_MIN_ADDRESS
)
1551 fence
= VM_MIN_ADDRESS
;
1553 instlen
= pc_is_mips16 (pc
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1555 /* search back for previous return */
1556 for (start_pc
-= instlen
;; start_pc
-= instlen
)
1557 if (start_pc
< fence
)
1559 /* It's not clear to me why we reach this point when
1560 stop_soon_quietly, but with this test, at least we
1561 don't print out warnings for every child forked (eg, on
1562 decstation). 22apr93 rich@cygnus.com. */
1563 if (!stop_soon_quietly
)
1565 static int blurb_printed
= 0;
1567 warning ("Warning: GDB can't find the start of the function at 0x%s.",
1572 /* This actually happens frequently in embedded
1573 development, when you first connect to a board
1574 and your stack pointer and pc are nowhere in
1575 particular. This message needs to give people
1576 in that situation enough information to
1577 determine that it's no big deal. */
1578 printf_filtered ("\n\
1579 GDB is unable to find the start of the function at 0x%s\n\
1580 and thus can't determine the size of that function's stack frame.\n\
1581 This means that GDB may be unable to access that stack frame, or\n\
1582 the frames below it.\n\
1583 This problem is most likely caused by an invalid program counter or\n\
1585 However, if you think GDB should simply search farther back\n\
1586 from 0x%s for code which looks like the beginning of a\n\
1587 function, you can increase the range of the search using the `set\n\
1588 heuristic-fence-post' command.\n",
1589 paddr_nz (pc
), paddr_nz (pc
));
1596 else if (pc_is_mips16 (start_pc
))
1598 unsigned short inst
;
1600 /* On MIPS16, any one of the following is likely to be the
1601 start of a function:
1605 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
1606 inst
= mips_fetch_instruction (start_pc
);
1607 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1608 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
1609 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
1610 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
1612 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1613 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1618 else if (mips_about_to_return (start_pc
))
1620 start_pc
+= 2 * MIPS_INSTLEN
; /* skip return, and its delay slot */
1627 /* Fetch the immediate value from a MIPS16 instruction.
1628 If the previous instruction was an EXTEND, use it to extend
1629 the upper bits of the immediate value. This is a helper function
1630 for mips16_heuristic_proc_desc. */
1633 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
1634 unsigned short inst
, /* current instruction */
1635 int nbits
, /* number of bits in imm field */
1636 int scale
, /* scale factor to be applied to imm */
1637 int is_signed
) /* is the imm field signed? */
1641 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1643 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1644 if (offset
& 0x8000) /* check for negative extend */
1645 offset
= 0 - (0x10000 - (offset
& 0xffff));
1646 return offset
| (inst
& 0x1f);
1650 int max_imm
= 1 << nbits
;
1651 int mask
= max_imm
- 1;
1652 int sign_bit
= max_imm
>> 1;
1654 offset
= inst
& mask
;
1655 if (is_signed
&& (offset
& sign_bit
))
1656 offset
= 0 - (max_imm
- offset
);
1657 return offset
* scale
;
1662 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
1663 stream from start_pc to limit_pc. */
1666 mips16_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1667 struct frame_info
*next_frame
, CORE_ADDR sp
)
1670 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1671 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1672 unsigned inst
= 0; /* current instruction */
1673 unsigned entry_inst
= 0; /* the entry instruction */
1676 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0; /* size of stack frame */
1677 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
1679 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS16_INSTLEN
)
1681 /* Save the previous instruction. If it's an EXTEND, we'll extract
1682 the immediate offset extension from it in mips16_get_imm. */
1685 /* Fetch and decode the instruction. */
1686 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
1687 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1688 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1690 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1691 if (offset
< 0) /* negative stack adjustment? */
1692 PROC_FRAME_OFFSET (&temp_proc_desc
) -= offset
;
1694 /* Exit loop if a positive stack adjustment is found, which
1695 usually means that the stack cleanup code in the function
1696 epilogue is reached. */
1699 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1701 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1702 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1703 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
1704 set_reg_offset (reg
, sp
+ offset
);
1706 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1708 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1709 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1710 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
1711 set_reg_offset (reg
, sp
+ offset
);
1713 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1715 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1716 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
1717 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1719 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1721 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1722 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
1723 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1725 else if (inst
== 0x673d) /* move $s1, $sp */
1728 PROC_FRAME_REG (&temp_proc_desc
) = 17;
1730 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1732 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1733 frame_addr
= sp
+ offset
;
1734 PROC_FRAME_REG (&temp_proc_desc
) = 17;
1735 PROC_FRAME_ADJUST (&temp_proc_desc
) = offset
;
1737 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1739 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1740 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1741 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1742 set_reg_offset (reg
, frame_addr
+ offset
);
1744 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1746 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1747 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1748 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1749 set_reg_offset (reg
, frame_addr
+ offset
);
1751 else if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1752 entry_inst
= inst
; /* save for later processing */
1753 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1754 cur_pc
+= MIPS16_INSTLEN
; /* 32-bit instruction */
1757 /* The entry instruction is typically the first instruction in a function,
1758 and it stores registers at offsets relative to the value of the old SP
1759 (before the prologue). But the value of the sp parameter to this
1760 function is the new SP (after the prologue has been executed). So we
1761 can't calculate those offsets until we've seen the entire prologue,
1762 and can calculate what the old SP must have been. */
1763 if (entry_inst
!= 0)
1765 int areg_count
= (entry_inst
>> 8) & 7;
1766 int sreg_count
= (entry_inst
>> 6) & 3;
1768 /* The entry instruction always subtracts 32 from the SP. */
1769 PROC_FRAME_OFFSET (&temp_proc_desc
) += 32;
1771 /* Now we can calculate what the SP must have been at the
1772 start of the function prologue. */
1773 sp
+= PROC_FRAME_OFFSET (&temp_proc_desc
);
1775 /* Check if a0-a3 were saved in the caller's argument save area. */
1776 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
1778 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1779 set_reg_offset (reg
, sp
+ offset
);
1780 offset
+= MIPS_SAVED_REGSIZE
;
1783 /* Check if the ra register was pushed on the stack. */
1785 if (entry_inst
& 0x20)
1787 PROC_REG_MASK (&temp_proc_desc
) |= 1 << RA_REGNUM
;
1788 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1789 offset
-= MIPS_SAVED_REGSIZE
;
1792 /* Check if the s0 and s1 registers were pushed on the stack. */
1793 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1795 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1796 set_reg_offset (reg
, sp
+ offset
);
1797 offset
-= MIPS_SAVED_REGSIZE
;
1803 mips32_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1804 struct frame_info
*next_frame
, CORE_ADDR sp
)
1807 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
1809 memset (temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
1810 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0;
1811 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
1812 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSTLEN
)
1814 unsigned long inst
, high_word
, low_word
;
1817 /* Fetch the instruction. */
1818 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
1820 /* Save some code by pre-extracting some useful fields. */
1821 high_word
= (inst
>> 16) & 0xffff;
1822 low_word
= inst
& 0xffff;
1823 reg
= high_word
& 0x1f;
1825 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
1826 || high_word
== 0x23bd /* addi $sp,$sp,-i */
1827 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
1829 if (low_word
& 0x8000) /* negative stack adjustment? */
1830 PROC_FRAME_OFFSET (&temp_proc_desc
) += 0x10000 - low_word
;
1832 /* Exit loop if a positive stack adjustment is found, which
1833 usually means that the stack cleanup code in the function
1834 epilogue is reached. */
1837 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
1839 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1840 set_reg_offset (reg
, sp
+ low_word
);
1842 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
1844 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra,
1845 but the register size used is only 32 bits. Make the address
1846 for the saved register point to the lower 32 bits. */
1847 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1848 set_reg_offset (reg
, sp
+ low_word
+ 8 - MIPS_REGSIZE
);
1850 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
1852 /* Old gcc frame, r30 is virtual frame pointer. */
1853 if ((long) low_word
!= PROC_FRAME_OFFSET (&temp_proc_desc
))
1854 frame_addr
= sp
+ low_word
;
1855 else if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
1857 unsigned alloca_adjust
;
1858 PROC_FRAME_REG (&temp_proc_desc
) = 30;
1859 frame_addr
= read_next_frame_reg (next_frame
, 30);
1860 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
1861 if (alloca_adjust
> 0)
1863 /* FP > SP + frame_size. This may be because
1864 * of an alloca or somethings similar.
1865 * Fix sp to "pre-alloca" value, and try again.
1867 sp
+= alloca_adjust
;
1872 /* move $30,$sp. With different versions of gas this will be either
1873 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
1874 Accept any one of these. */
1875 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
1877 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
1878 if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
1880 unsigned alloca_adjust
;
1881 PROC_FRAME_REG (&temp_proc_desc
) = 30;
1882 frame_addr
= read_next_frame_reg (next_frame
, 30);
1883 alloca_adjust
= (unsigned) (frame_addr
- sp
);
1884 if (alloca_adjust
> 0)
1886 /* FP > SP + frame_size. This may be because
1887 * of an alloca or somethings similar.
1888 * Fix sp to "pre-alloca" value, and try again.
1890 sp
+= alloca_adjust
;
1895 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
1897 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1898 set_reg_offset (reg
, frame_addr
+ low_word
);
1903 static mips_extra_func_info_t
1904 heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1905 struct frame_info
*next_frame
, int cur_frame
)
1910 sp
= read_next_frame_reg (next_frame
, SP_REGNUM
);
1916 memset (&temp_proc_desc
, '\0', sizeof (temp_proc_desc
));
1917 memset (&temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
1918 PROC_LOW_ADDR (&temp_proc_desc
) = start_pc
;
1919 PROC_FRAME_REG (&temp_proc_desc
) = SP_REGNUM
;
1920 PROC_PC_REG (&temp_proc_desc
) = RA_REGNUM
;
1922 if (start_pc
+ 200 < limit_pc
)
1923 limit_pc
= start_pc
+ 200;
1924 if (pc_is_mips16 (start_pc
))
1925 mips16_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
1927 mips32_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
1928 return &temp_proc_desc
;
1931 static mips_extra_func_info_t
1932 non_heuristic_proc_desc (CORE_ADDR pc
, CORE_ADDR
*addrptr
)
1934 CORE_ADDR startaddr
;
1935 mips_extra_func_info_t proc_desc
;
1936 struct block
*b
= block_for_pc (pc
);
1939 find_pc_partial_function (pc
, NULL
, &startaddr
, NULL
);
1941 *addrptr
= startaddr
;
1942 if (b
== NULL
|| PC_IN_CALL_DUMMY (pc
, 0, 0))
1946 if (startaddr
> BLOCK_START (b
))
1947 /* This is the "pathological" case referred to in a comment in
1948 print_frame_info. It might be better to move this check into
1952 sym
= lookup_symbol (MIPS_EFI_SYMBOL_NAME
, b
, LABEL_NAMESPACE
, 0, NULL
);
1955 /* If we never found a PDR for this function in symbol reading, then
1956 examine prologues to find the information. */
1959 proc_desc
= (mips_extra_func_info_t
) SYMBOL_VALUE (sym
);
1960 if (PROC_FRAME_REG (proc_desc
) == -1)
1970 static mips_extra_func_info_t
1971 find_proc_desc (CORE_ADDR pc
, struct frame_info
*next_frame
, int cur_frame
)
1973 mips_extra_func_info_t proc_desc
;
1974 CORE_ADDR startaddr
;
1976 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
1980 /* IF this is the topmost frame AND
1981 * (this proc does not have debugging information OR
1982 * the PC is in the procedure prologue)
1983 * THEN create a "heuristic" proc_desc (by analyzing
1984 * the actual code) to replace the "official" proc_desc.
1986 if (next_frame
== NULL
)
1988 struct symtab_and_line val
;
1989 struct symbol
*proc_symbol
=
1990 PROC_DESC_IS_DUMMY (proc_desc
) ? 0 : PROC_SYMBOL (proc_desc
);
1994 val
= find_pc_line (BLOCK_START
1995 (SYMBOL_BLOCK_VALUE (proc_symbol
)),
1997 val
.pc
= val
.end
? val
.end
: pc
;
1999 if (!proc_symbol
|| pc
< val
.pc
)
2001 mips_extra_func_info_t found_heuristic
=
2002 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc
),
2003 pc
, next_frame
, cur_frame
);
2004 if (found_heuristic
)
2005 proc_desc
= found_heuristic
;
2011 /* Is linked_proc_desc_table really necessary? It only seems to be used
2012 by procedure call dummys. However, the procedures being called ought
2013 to have their own proc_descs, and even if they don't,
2014 heuristic_proc_desc knows how to create them! */
2016 register struct linked_proc_info
*link
;
2018 for (link
= linked_proc_desc_table
; link
; link
= link
->next
)
2019 if (PROC_LOW_ADDR (&link
->info
) <= pc
2020 && PROC_HIGH_ADDR (&link
->info
) > pc
)
2024 startaddr
= heuristic_proc_start (pc
);
2027 heuristic_proc_desc (startaddr
, pc
, next_frame
, cur_frame
);
2033 get_frame_pointer (struct frame_info
*frame
,
2034 mips_extra_func_info_t proc_desc
)
2036 return ADDR_BITS_REMOVE (
2037 read_next_frame_reg (frame
, PROC_FRAME_REG (proc_desc
)) +
2038 PROC_FRAME_OFFSET (proc_desc
) - PROC_FRAME_ADJUST (proc_desc
));
2041 mips_extra_func_info_t cached_proc_desc
;
2044 mips_frame_chain (struct frame_info
*frame
)
2046 mips_extra_func_info_t proc_desc
;
2048 CORE_ADDR saved_pc
= FRAME_SAVED_PC (frame
);
2050 if (saved_pc
== 0 || inside_entry_file (saved_pc
))
2053 /* Check if the PC is inside a call stub. If it is, fetch the
2054 PC of the caller of that stub. */
2055 if ((tmp
= mips_skip_stub (saved_pc
)) != 0)
2058 /* Look up the procedure descriptor for this PC. */
2059 proc_desc
= find_proc_desc (saved_pc
, frame
, 1);
2063 cached_proc_desc
= proc_desc
;
2065 /* If no frame pointer and frame size is zero, we must be at end
2066 of stack (or otherwise hosed). If we don't check frame size,
2067 we loop forever if we see a zero size frame. */
2068 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
2069 && PROC_FRAME_OFFSET (proc_desc
) == 0
2070 /* The previous frame from a sigtramp frame might be frameless
2071 and have frame size zero. */
2072 && !frame
->signal_handler_caller
)
2075 return get_frame_pointer (frame
, proc_desc
);
2079 mips_init_extra_frame_info (int fromleaf
, struct frame_info
*fci
)
2083 /* Use proc_desc calculated in frame_chain */
2084 mips_extra_func_info_t proc_desc
=
2085 fci
->next
? cached_proc_desc
: find_proc_desc (fci
->pc
, fci
->next
, 1);
2087 fci
->extra_info
= (struct frame_extra_info
*)
2088 frame_obstack_alloc (sizeof (struct frame_extra_info
));
2090 fci
->saved_regs
= NULL
;
2091 fci
->extra_info
->proc_desc
=
2092 proc_desc
== &temp_proc_desc
? 0 : proc_desc
;
2095 /* Fixup frame-pointer - only needed for top frame */
2096 /* This may not be quite right, if proc has a real frame register.
2097 Get the value of the frame relative sp, procedure might have been
2098 interrupted by a signal at it's very start. */
2099 if (fci
->pc
== PROC_LOW_ADDR (proc_desc
)
2100 && !PROC_DESC_IS_DUMMY (proc_desc
))
2101 fci
->frame
= read_next_frame_reg (fci
->next
, SP_REGNUM
);
2103 fci
->frame
= get_frame_pointer (fci
->next
, proc_desc
);
2105 if (proc_desc
== &temp_proc_desc
)
2109 /* Do not set the saved registers for a sigtramp frame,
2110 mips_find_saved_registers will do that for us.
2111 We can't use fci->signal_handler_caller, it is not yet set. */
2112 find_pc_partial_function (fci
->pc
, &name
,
2113 (CORE_ADDR
*) NULL
, (CORE_ADDR
*) NULL
);
2114 if (!PC_IN_SIGTRAMP (fci
->pc
, name
))
2116 frame_saved_regs_zalloc (fci
);
2117 memcpy (fci
->saved_regs
, temp_saved_regs
, SIZEOF_FRAME_SAVED_REGS
);
2118 fci
->saved_regs
[PC_REGNUM
]
2119 = fci
->saved_regs
[RA_REGNUM
];
2123 /* hack: if argument regs are saved, guess these contain args */
2124 /* assume we can't tell how many args for now */
2125 fci
->extra_info
->num_args
= -1;
2126 for (regnum
= MIPS_LAST_ARG_REGNUM
; regnum
>= A0_REGNUM
; regnum
--)
2128 if (PROC_REG_MASK (proc_desc
) & (1 << regnum
))
2130 fci
->extra_info
->num_args
= regnum
- A0_REGNUM
+ 1;
2137 /* MIPS stack frames are almost impenetrable. When execution stops,
2138 we basically have to look at symbol information for the function
2139 that we stopped in, which tells us *which* register (if any) is
2140 the base of the frame pointer, and what offset from that register
2141 the frame itself is at.
2143 This presents a problem when trying to examine a stack in memory
2144 (that isn't executing at the moment), using the "frame" command. We
2145 don't have a PC, nor do we have any registers except SP.
2147 This routine takes two arguments, SP and PC, and tries to make the
2148 cached frames look as if these two arguments defined a frame on the
2149 cache. This allows the rest of info frame to extract the important
2150 arguments without difficulty. */
2153 setup_arbitrary_frame (int argc
, CORE_ADDR
*argv
)
2156 error ("MIPS frame specifications require two arguments: sp and pc");
2158 return create_new_frame (argv
[0], argv
[1]);
2161 /* According to the current ABI, should the type be passed in a
2162 floating-point register (assuming that there is space)? When there
2163 is no FPU, FP are not even considered as possibile candidates for
2164 FP registers and, consequently this returns false - forces FP
2165 arguments into integer registers. */
2168 fp_register_arg_p (enum type_code typecode
, struct type
*arg_type
)
2170 return ((typecode
== TYPE_CODE_FLT
2172 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
2173 && TYPE_NFIELDS (arg_type
) == 1
2174 && TYPE_CODE (TYPE_FIELD_TYPE (arg_type
, 0)) == TYPE_CODE_FLT
))
2175 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
);
2178 /* On o32, argument passing in GPRs depends on the alignment of the type being
2179 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2182 mips_type_needs_double_align (struct type
*type
)
2184 enum type_code typecode
= TYPE_CODE (type
);
2186 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
2188 else if (typecode
== TYPE_CODE_STRUCT
)
2190 if (TYPE_NFIELDS (type
) < 1)
2192 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
2194 else if (typecode
== TYPE_CODE_UNION
)
2198 n
= TYPE_NFIELDS (type
);
2199 for (i
= 0; i
< n
; i
++)
2200 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
2208 mips_push_arguments (int nargs
,
2209 struct value
**args
,
2212 CORE_ADDR struct_addr
)
2218 int stack_offset
= 0;
2220 /* Macros to round N up or down to the next A boundary; A must be
2222 #define ROUND_DOWN(n,a) ((n) & ~((a)-1))
2223 #define ROUND_UP(n,a) (((n)+(a)-1) & ~((a)-1))
2225 /* First ensure that the stack and structure return address (if any)
2226 are properly aligned. The stack has to be at least 64-bit aligned
2227 even on 32-bit machines, because doubles must be 64-bit aligned.
2228 On at least one MIPS variant, stack frames need to be 128-bit
2229 aligned, so we round to this widest known alignment. */
2230 sp
= ROUND_DOWN (sp
, 16);
2231 struct_addr
= ROUND_DOWN (struct_addr
, 16);
2233 /* Now make space on the stack for the args. We allocate more
2234 than necessary for EABI, because the first few arguments are
2235 passed in registers, but that's OK. */
2236 for (argnum
= 0; argnum
< nargs
; argnum
++)
2237 len
+= ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])), MIPS_STACK_ARGSIZE
);
2238 sp
-= ROUND_UP (len
, 16);
2241 fprintf_unfiltered (gdb_stdlog
, "mips_push_arguments: sp=0x%lx allocated %d\n",
2242 (long) sp
, ROUND_UP (len
, 16));
2244 /* Initialize the integer and float register pointers. */
2246 float_argreg
= FPA0_REGNUM
;
2248 /* the struct_return pointer occupies the first parameter-passing reg */
2252 fprintf_unfiltered (gdb_stdlog
,
2253 "mips_push_arguments: struct_return reg=%d 0x%lx\n",
2254 argreg
, (long) struct_addr
);
2255 write_register (argreg
++, struct_addr
);
2256 if (MIPS_REGS_HAVE_HOME_P
)
2257 stack_offset
+= MIPS_STACK_ARGSIZE
;
2260 /* Now load as many as possible of the first arguments into
2261 registers, and push the rest onto the stack. Loop thru args
2262 from first to last. */
2263 for (argnum
= 0; argnum
< nargs
; argnum
++)
2266 char valbuf
[MAX_REGISTER_RAW_SIZE
];
2267 struct value
*arg
= args
[argnum
];
2268 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
2269 int len
= TYPE_LENGTH (arg_type
);
2270 enum type_code typecode
= TYPE_CODE (arg_type
);
2273 fprintf_unfiltered (gdb_stdlog
,
2274 "mips_push_arguments: %d len=%d type=%d",
2275 argnum
+ 1, len
, (int) typecode
);
2277 /* The EABI passes structures that do not fit in a register by
2278 reference. In all other cases, pass the structure by value. */
2280 && len
> MIPS_SAVED_REGSIZE
2281 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
2283 store_address (valbuf
, MIPS_SAVED_REGSIZE
, VALUE_ADDRESS (arg
));
2284 typecode
= TYPE_CODE_PTR
;
2285 len
= MIPS_SAVED_REGSIZE
;
2288 fprintf_unfiltered (gdb_stdlog
, " push");
2291 val
= (char *) VALUE_CONTENTS (arg
);
2293 /* 32-bit ABIs always start floating point arguments in an
2294 even-numbered floating point register. Round the FP register
2295 up before the check to see if there are any FP registers
2296 left. Non MIPS_EABI targets also pass the FP in the integer
2297 registers so also round up normal registers. */
2298 if (!FP_REGISTER_DOUBLE
2299 && fp_register_arg_p (typecode
, arg_type
))
2301 if ((float_argreg
& 1))
2305 /* Floating point arguments passed in registers have to be
2306 treated specially. On 32-bit architectures, doubles
2307 are passed in register pairs; the even register gets
2308 the low word, and the odd register gets the high word.
2309 On non-EABI processors, the first two floating point arguments are
2310 also copied to general registers, because MIPS16 functions
2311 don't use float registers for arguments. This duplication of
2312 arguments in general registers can't hurt non-MIPS16 functions
2313 because those registers are normally skipped. */
2314 /* MIPS_EABI squeezes a struct that contains a single floating
2315 point value into an FP register instead of pushing it onto the
2317 if (fp_register_arg_p (typecode
, arg_type
)
2318 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
2320 if (!FP_REGISTER_DOUBLE
&& len
== 8)
2322 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
2323 unsigned long regval
;
2325 /* Write the low word of the double to the even register(s). */
2326 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
2328 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2329 float_argreg
, phex (regval
, 4));
2330 write_register (float_argreg
++, regval
);
2334 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
2335 argreg
, phex (regval
, 4));
2336 write_register (argreg
++, regval
);
2339 /* Write the high word of the double to the odd register(s). */
2340 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
2342 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2343 float_argreg
, phex (regval
, 4));
2344 write_register (float_argreg
++, regval
);
2348 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
2349 argreg
, phex (regval
, 4));
2350 write_register (argreg
++, regval
);
2356 /* This is a floating point value that fits entirely
2357 in a single register. */
2358 /* On 32 bit ABI's the float_argreg is further adjusted
2359 above to ensure that it is even register aligned. */
2360 LONGEST regval
= extract_unsigned_integer (val
, len
);
2362 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2363 float_argreg
, phex (regval
, len
));
2364 write_register (float_argreg
++, regval
);
2367 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
2368 registers for each argument. The below is (my
2369 guess) to ensure that the corresponding integer
2370 register has reserved the same space. */
2372 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
2373 argreg
, phex (regval
, len
));
2374 write_register (argreg
, regval
);
2375 argreg
+= FP_REGISTER_DOUBLE
? 1 : 2;
2378 /* Reserve space for the FP register. */
2379 if (MIPS_REGS_HAVE_HOME_P
)
2380 stack_offset
+= ROUND_UP (len
, MIPS_STACK_ARGSIZE
);
2384 /* Copy the argument to general registers or the stack in
2385 register-sized pieces. Large arguments are split between
2386 registers and stack. */
2387 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
2388 are treated specially: Irix cc passes them in registers
2389 where gcc sometimes puts them on the stack. For maximum
2390 compatibility, we will put them in both places. */
2391 int odd_sized_struct
= ((len
> MIPS_SAVED_REGSIZE
) &&
2392 (len
% MIPS_SAVED_REGSIZE
!= 0));
2393 /* Structures should be aligned to eight bytes (even arg registers)
2394 on MIPS_ABI_O32 if their first member has double precision. */
2395 if (gdbarch_tdep (current_gdbarch
)->mips_abi
== MIPS_ABI_O32
2396 && mips_type_needs_double_align (arg_type
))
2401 /* Note: Floating-point values that didn't fit into an FP
2402 register are only written to memory. */
2405 /* Rememer if the argument was written to the stack. */
2406 int stack_used_p
= 0;
2407 int partial_len
= len
< MIPS_SAVED_REGSIZE
? len
: MIPS_SAVED_REGSIZE
;
2410 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
2413 /* Write this portion of the argument to the stack. */
2414 if (argreg
> MIPS_LAST_ARG_REGNUM
2416 || fp_register_arg_p (typecode
, arg_type
))
2418 /* Should shorter than int integer values be
2419 promoted to int before being stored? */
2420 int longword_offset
= 0;
2423 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2425 if (MIPS_STACK_ARGSIZE
== 8 &&
2426 (typecode
== TYPE_CODE_INT
||
2427 typecode
== TYPE_CODE_PTR
||
2428 typecode
== TYPE_CODE_FLT
) && len
<= 4)
2429 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
2430 else if ((typecode
== TYPE_CODE_STRUCT
||
2431 typecode
== TYPE_CODE_UNION
) &&
2432 TYPE_LENGTH (arg_type
) < MIPS_STACK_ARGSIZE
)
2433 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
2438 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%lx",
2439 (long) stack_offset
);
2440 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%lx",
2441 (long) longword_offset
);
2444 addr
= sp
+ stack_offset
+ longword_offset
;
2449 fprintf_unfiltered (gdb_stdlog
, " @0x%lx ", (long) addr
);
2450 for (i
= 0; i
< partial_len
; i
++)
2452 fprintf_unfiltered (gdb_stdlog
, "%02x", val
[i
] & 0xff);
2455 write_memory (addr
, val
, partial_len
);
2458 /* Note!!! This is NOT an else clause. Odd sized
2459 structs may go thru BOTH paths. Floating point
2460 arguments will not. */
2461 /* Write this portion of the argument to a general
2462 purpose register. */
2463 if (argreg
<= MIPS_LAST_ARG_REGNUM
2464 && !fp_register_arg_p (typecode
, arg_type
))
2466 LONGEST regval
= extract_unsigned_integer (val
, partial_len
);
2468 /* A non-floating-point argument being passed in a
2469 general register. If a struct or union, and if
2470 the remaining length is smaller than the register
2471 size, we have to adjust the register value on
2474 It does not seem to be necessary to do the
2475 same for integral types.
2477 Also don't do this adjustment on EABI and O64
2480 cagney/2001-07-23: gdb/179: Also, GCC, when
2481 outputting LE O32 with sizeof (struct) <
2482 MIPS_SAVED_REGSIZE, generates a left shift as
2483 part of storing the argument in a register a
2484 register (the left shift isn't generated when
2485 sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it
2486 is quite possible that this is GCC contradicting
2487 the LE/O32 ABI, GDB has not been adjusted to
2488 accommodate this. Either someone needs to
2489 demonstrate that the LE/O32 ABI specifies such a
2490 left shift OR this new ABI gets identified as
2491 such and GDB gets tweaked accordingly. */
2494 && MIPS_SAVED_REGSIZE
< 8
2495 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
2496 && partial_len
< MIPS_SAVED_REGSIZE
2497 && (typecode
== TYPE_CODE_STRUCT
||
2498 typecode
== TYPE_CODE_UNION
))
2499 regval
<<= ((MIPS_SAVED_REGSIZE
- partial_len
) *
2503 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
2505 phex (regval
, MIPS_SAVED_REGSIZE
));
2506 write_register (argreg
, regval
);
2509 /* If this is the old ABI, prevent subsequent floating
2510 point arguments from being passed in floating point
2513 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
2519 /* Compute the the offset into the stack at which we
2520 will copy the next parameter.
2522 In older ABIs, the caller reserved space for
2523 registers that contained arguments. This was loosely
2524 refered to as their "home". Consequently, space is
2527 In the new EABI (and the NABI32), the stack_offset
2528 only needs to be adjusted when it has been used.. */
2530 if (MIPS_REGS_HAVE_HOME_P
|| stack_used_p
)
2531 stack_offset
+= ROUND_UP (partial_len
, MIPS_STACK_ARGSIZE
);
2535 fprintf_unfiltered (gdb_stdlog
, "\n");
2538 /* Return adjusted stack pointer. */
2543 mips_push_return_address (CORE_ADDR pc
, CORE_ADDR sp
)
2545 /* Set the return address register to point to the entry
2546 point of the program, where a breakpoint lies in wait. */
2547 write_register (RA_REGNUM
, CALL_DUMMY_ADDRESS ());
2552 mips_push_register (CORE_ADDR
* sp
, int regno
)
2554 char buffer
[MAX_REGISTER_RAW_SIZE
];
2557 if (MIPS_SAVED_REGSIZE
< REGISTER_RAW_SIZE (regno
))
2559 regsize
= MIPS_SAVED_REGSIZE
;
2560 offset
= (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
2561 ? REGISTER_RAW_SIZE (regno
) - MIPS_SAVED_REGSIZE
2566 regsize
= REGISTER_RAW_SIZE (regno
);
2570 read_register_gen (regno
, buffer
);
2571 write_memory (*sp
, buffer
+ offset
, regsize
);
2574 /* MASK(i,j) == (1<<i) + (1<<(i+1)) + ... + (1<<j)). Assume i<=j<(MIPS_NUMREGS-1). */
2575 #define MASK(i,j) (((1 << ((j)+1))-1) ^ ((1 << (i))-1))
2578 mips_push_dummy_frame (void)
2581 struct linked_proc_info
*link
= (struct linked_proc_info
*)
2582 xmalloc (sizeof (struct linked_proc_info
));
2583 mips_extra_func_info_t proc_desc
= &link
->info
;
2584 CORE_ADDR sp
= ADDR_BITS_REMOVE (read_signed_register (SP_REGNUM
));
2585 CORE_ADDR old_sp
= sp
;
2586 link
->next
= linked_proc_desc_table
;
2587 linked_proc_desc_table
= link
;
2589 /* FIXME! are these correct ? */
2590 #define PUSH_FP_REGNUM 16 /* must be a register preserved across calls */
2591 #define GEN_REG_SAVE_MASK MASK(1,16)|MASK(24,28)|(1<<(MIPS_NUMREGS-1))
2592 #define FLOAT_REG_SAVE_MASK MASK(0,19)
2593 #define FLOAT_SINGLE_REG_SAVE_MASK \
2594 ((1<<18)|(1<<16)|(1<<14)|(1<<12)|(1<<10)|(1<<8)|(1<<6)|(1<<4)|(1<<2)|(1<<0))
2596 * The registers we must save are all those not preserved across
2597 * procedure calls. Dest_Reg (see tm-mips.h) must also be saved.
2598 * In addition, we must save the PC, PUSH_FP_REGNUM, MMLO/-HI
2599 * and FP Control/Status registers.
2602 * Dummy frame layout:
2605 * Saved MMHI, MMLO, FPC_CSR
2610 * Saved D18 (i.e. F19, F18)
2612 * Saved D0 (i.e. F1, F0)
2613 * Argument build area and stack arguments written via mips_push_arguments
2617 /* Save special registers (PC, MMHI, MMLO, FPC_CSR) */
2618 PROC_FRAME_REG (proc_desc
) = PUSH_FP_REGNUM
;
2619 PROC_FRAME_OFFSET (proc_desc
) = 0;
2620 PROC_FRAME_ADJUST (proc_desc
) = 0;
2621 mips_push_register (&sp
, PC_REGNUM
);
2622 mips_push_register (&sp
, HI_REGNUM
);
2623 mips_push_register (&sp
, LO_REGNUM
);
2624 mips_push_register (&sp
, MIPS_FPU_TYPE
== MIPS_FPU_NONE
? 0 : FCRCS_REGNUM
);
2626 /* Save general CPU registers */
2627 PROC_REG_MASK (proc_desc
) = GEN_REG_SAVE_MASK
;
2628 /* PROC_REG_OFFSET is the offset of the first saved register from FP. */
2629 PROC_REG_OFFSET (proc_desc
) = sp
- old_sp
- MIPS_SAVED_REGSIZE
;
2630 for (ireg
= 32; --ireg
>= 0;)
2631 if (PROC_REG_MASK (proc_desc
) & (1 << ireg
))
2632 mips_push_register (&sp
, ireg
);
2634 /* Save floating point registers starting with high order word */
2635 PROC_FREG_MASK (proc_desc
) =
2636 MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? FLOAT_REG_SAVE_MASK
2637 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? FLOAT_SINGLE_REG_SAVE_MASK
: 0;
2638 /* PROC_FREG_OFFSET is the offset of the first saved *double* register
2640 PROC_FREG_OFFSET (proc_desc
) = sp
- old_sp
- 8;
2641 for (ireg
= 32; --ireg
>= 0;)
2642 if (PROC_FREG_MASK (proc_desc
) & (1 << ireg
))
2643 mips_push_register (&sp
, ireg
+ FP0_REGNUM
);
2645 /* Update the frame pointer for the call dummy and the stack pointer.
2646 Set the procedure's starting and ending addresses to point to the
2647 call dummy address at the entry point. */
2648 write_register (PUSH_FP_REGNUM
, old_sp
);
2649 write_register (SP_REGNUM
, sp
);
2650 PROC_LOW_ADDR (proc_desc
) = CALL_DUMMY_ADDRESS ();
2651 PROC_HIGH_ADDR (proc_desc
) = CALL_DUMMY_ADDRESS () + 4;
2652 SET_PROC_DESC_IS_DUMMY (proc_desc
);
2653 PROC_PC_REG (proc_desc
) = RA_REGNUM
;
2657 mips_pop_frame (void)
2659 register int regnum
;
2660 struct frame_info
*frame
= get_current_frame ();
2661 CORE_ADDR new_sp
= FRAME_FP (frame
);
2663 mips_extra_func_info_t proc_desc
= frame
->extra_info
->proc_desc
;
2665 write_register (PC_REGNUM
, FRAME_SAVED_PC (frame
));
2666 if (frame
->saved_regs
== NULL
)
2667 mips_find_saved_regs (frame
);
2668 for (regnum
= 0; regnum
< NUM_REGS
; regnum
++)
2670 if (regnum
!= SP_REGNUM
&& regnum
!= PC_REGNUM
2671 && frame
->saved_regs
[regnum
])
2672 write_register (regnum
,
2673 read_memory_integer (frame
->saved_regs
[regnum
],
2674 MIPS_SAVED_REGSIZE
));
2676 write_register (SP_REGNUM
, new_sp
);
2677 flush_cached_frames ();
2679 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
2681 struct linked_proc_info
*pi_ptr
, *prev_ptr
;
2683 for (pi_ptr
= linked_proc_desc_table
, prev_ptr
= NULL
;
2685 prev_ptr
= pi_ptr
, pi_ptr
= pi_ptr
->next
)
2687 if (&pi_ptr
->info
== proc_desc
)
2692 error ("Can't locate dummy extra frame info\n");
2694 if (prev_ptr
!= NULL
)
2695 prev_ptr
->next
= pi_ptr
->next
;
2697 linked_proc_desc_table
= pi_ptr
->next
;
2701 write_register (HI_REGNUM
,
2702 read_memory_integer (new_sp
- 2 * MIPS_SAVED_REGSIZE
,
2703 MIPS_SAVED_REGSIZE
));
2704 write_register (LO_REGNUM
,
2705 read_memory_integer (new_sp
- 3 * MIPS_SAVED_REGSIZE
,
2706 MIPS_SAVED_REGSIZE
));
2707 if (MIPS_FPU_TYPE
!= MIPS_FPU_NONE
)
2708 write_register (FCRCS_REGNUM
,
2709 read_memory_integer (new_sp
- 4 * MIPS_SAVED_REGSIZE
,
2710 MIPS_SAVED_REGSIZE
));
2714 /* Floating point register management.
2716 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
2717 64bit operations, these early MIPS cpus treat fp register pairs
2718 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
2719 registers and offer a compatibility mode that emulates the MIPS2 fp
2720 model. When operating in MIPS2 fp compat mode, later cpu's split
2721 double precision floats into two 32-bit chunks and store them in
2722 consecutive fp regs. To display 64-bit floats stored in this
2723 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
2724 Throw in user-configurable endianness and you have a real mess.
2726 The way this works is:
2727 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
2728 double-precision value will be split across two logical registers.
2729 The lower-numbered logical register will hold the low-order bits,
2730 regardless of the processor's endianness.
2731 - If we are on a 64-bit processor, and we are looking for a
2732 single-precision value, it will be in the low ordered bits
2733 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
2734 save slot in memory.
2735 - If we are in 64-bit mode, everything is straightforward.
2737 Note that this code only deals with "live" registers at the top of the
2738 stack. We will attempt to deal with saved registers later, when
2739 the raw/cooked register interface is in place. (We need a general
2740 interface that can deal with dynamic saved register sizes -- fp
2741 regs could be 32 bits wide in one frame and 64 on the frame above
2744 static struct type
*
2745 mips_float_register_type (void)
2747 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2748 return builtin_type_ieee_single_big
;
2750 return builtin_type_ieee_single_little
;
2753 static struct type
*
2754 mips_double_register_type (void)
2756 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2757 return builtin_type_ieee_double_big
;
2759 return builtin_type_ieee_double_little
;
2762 /* Copy a 32-bit single-precision value from the current frame
2763 into rare_buffer. */
2766 mips_read_fp_register_single (int regno
, char *rare_buffer
)
2768 int raw_size
= REGISTER_RAW_SIZE (regno
);
2769 char *raw_buffer
= alloca (raw_size
);
2771 if (!frame_register_read (selected_frame
, regno
, raw_buffer
))
2772 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
2775 /* We have a 64-bit value for this register. Find the low-order
2779 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2784 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
2788 memcpy (rare_buffer
, raw_buffer
, 4);
2792 /* Copy a 64-bit double-precision value from the current frame into
2793 rare_buffer. This may include getting half of it from the next
2797 mips_read_fp_register_double (int regno
, char *rare_buffer
)
2799 int raw_size
= REGISTER_RAW_SIZE (regno
);
2801 if (raw_size
== 8 && !mips2_fp_compat ())
2803 /* We have a 64-bit value for this register, and we should use
2805 if (!frame_register_read (selected_frame
, regno
, rare_buffer
))
2806 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
2810 if ((regno
- FP0_REGNUM
) & 1)
2811 internal_error (__FILE__
, __LINE__
,
2812 "mips_read_fp_register_double: bad access to "
2813 "odd-numbered FP register");
2815 /* mips_read_fp_register_single will find the correct 32 bits from
2817 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2819 mips_read_fp_register_single (regno
, rare_buffer
+ 4);
2820 mips_read_fp_register_single (regno
+ 1, rare_buffer
);
2824 mips_read_fp_register_single (regno
, rare_buffer
);
2825 mips_read_fp_register_single (regno
+ 1, rare_buffer
+ 4);
2831 mips_print_register (int regnum
, int all
)
2833 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
2835 /* Get the data in raw format. */
2836 if (!frame_register_read (selected_frame
, regnum
, raw_buffer
))
2838 printf_filtered ("%s: [Invalid]", REGISTER_NAME (regnum
));
2842 /* If we have a actual 32-bit floating point register (or we are in
2843 32-bit compatibility mode), and the register is even-numbered,
2844 also print it as a double (spanning two registers). */
2845 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
2846 && (REGISTER_RAW_SIZE (regnum
) == 4
2847 || mips2_fp_compat ())
2848 && !((regnum
- FP0_REGNUM
) & 1))
2850 char dbuffer
[2 * MAX_REGISTER_RAW_SIZE
];
2852 mips_read_fp_register_double (regnum
, dbuffer
);
2854 printf_filtered ("(d%d: ", regnum
- FP0_REGNUM
);
2855 val_print (mips_double_register_type (), dbuffer
, 0, 0,
2856 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2857 printf_filtered ("); ");
2859 fputs_filtered (REGISTER_NAME (regnum
), gdb_stdout
);
2861 /* The problem with printing numeric register names (r26, etc.) is that
2862 the user can't use them on input. Probably the best solution is to
2863 fix it so that either the numeric or the funky (a2, etc.) names
2864 are accepted on input. */
2865 if (regnum
< MIPS_NUMREGS
)
2866 printf_filtered ("(r%d): ", regnum
);
2868 printf_filtered (": ");
2870 /* If virtual format is floating, print it that way. */
2871 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2872 if (REGISTER_RAW_SIZE (regnum
) == 8 && !mips2_fp_compat ())
2874 /* We have a meaningful 64-bit value in this register. Show
2875 it as a 32-bit float and a 64-bit double. */
2876 int offset
= 4 * (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
);
2878 printf_filtered (" (float) ");
2879 val_print (mips_float_register_type (), raw_buffer
+ offset
, 0, 0,
2880 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2881 printf_filtered (", (double) ");
2882 val_print (mips_double_register_type (), raw_buffer
, 0, 0,
2883 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2886 val_print (REGISTER_VIRTUAL_TYPE (regnum
), raw_buffer
, 0, 0,
2887 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2888 /* Else print as integer in hex. */
2893 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2894 offset
= REGISTER_RAW_SIZE (regnum
) - REGISTER_VIRTUAL_SIZE (regnum
);
2898 print_scalar_formatted (raw_buffer
+ offset
,
2899 REGISTER_VIRTUAL_TYPE (regnum
),
2900 'x', 0, gdb_stdout
);
2904 /* Replacement for generic do_registers_info.
2905 Print regs in pretty columns. */
2908 do_fp_register_row (int regnum
)
2909 { /* do values for FP (float) regs */
2911 double doub
, flt1
, flt2
; /* doubles extracted from raw hex data */
2912 int inv1
, inv2
, inv3
;
2914 raw_buffer
= (char *) alloca (2 * REGISTER_RAW_SIZE (FP0_REGNUM
));
2916 if (REGISTER_RAW_SIZE (regnum
) == 4 || mips2_fp_compat ())
2918 /* 4-byte registers: we can fit two registers per row. */
2919 /* Also print every pair of 4-byte regs as an 8-byte double. */
2920 mips_read_fp_register_single (regnum
, raw_buffer
);
2921 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
2923 mips_read_fp_register_single (regnum
+ 1, raw_buffer
);
2924 flt2
= unpack_double (mips_float_register_type (), raw_buffer
, &inv2
);
2926 mips_read_fp_register_double (regnum
, raw_buffer
);
2927 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv3
);
2929 printf_filtered (" %-5s", REGISTER_NAME (regnum
));
2931 printf_filtered (": <invalid float>");
2933 printf_filtered ("%-17.9g", flt1
);
2935 printf_filtered (" %-5s", REGISTER_NAME (regnum
+ 1));
2937 printf_filtered (": <invalid float>");
2939 printf_filtered ("%-17.9g", flt2
);
2941 printf_filtered (" dbl: ");
2943 printf_filtered ("<invalid double>");
2945 printf_filtered ("%-24.17g", doub
);
2946 printf_filtered ("\n");
2948 /* may want to do hex display here (future enhancement) */
2953 /* Eight byte registers: print each one as float AND as double. */
2954 mips_read_fp_register_single (regnum
, raw_buffer
);
2955 flt1
= unpack_double (mips_double_register_type (), raw_buffer
, &inv1
);
2957 mips_read_fp_register_double (regnum
, raw_buffer
);
2958 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv3
);
2960 printf_filtered (" %-5s: ", REGISTER_NAME (regnum
));
2962 printf_filtered ("<invalid float>");
2964 printf_filtered ("flt: %-17.9g", flt1
);
2966 printf_filtered (" dbl: ");
2968 printf_filtered ("<invalid double>");
2970 printf_filtered ("%-24.17g", doub
);
2972 printf_filtered ("\n");
2973 /* may want to do hex display here (future enhancement) */
2979 /* Print a row's worth of GP (int) registers, with name labels above */
2982 do_gp_register_row (int regnum
)
2984 /* do values for GP (int) regs */
2985 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
2986 int ncols
= (MIPS_REGSIZE
== 8 ? 4 : 8); /* display cols per row */
2988 int start_regnum
= regnum
;
2989 int numregs
= NUM_REGS
;
2992 /* For GP registers, we print a separate row of names above the vals */
2993 printf_filtered (" ");
2994 for (col
= 0; col
< ncols
&& regnum
< numregs
; regnum
++)
2996 if (*REGISTER_NAME (regnum
) == '\0')
2997 continue; /* unused register */
2998 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2999 break; /* end the row: reached FP register */
3000 printf_filtered (MIPS_REGSIZE
== 8 ? "%17s" : "%9s",
3001 REGISTER_NAME (regnum
));
3004 printf_filtered (start_regnum
< MIPS_NUMREGS
? "\n R%-4d" : "\n ",
3005 start_regnum
); /* print the R0 to R31 names */
3007 regnum
= start_regnum
; /* go back to start of row */
3008 /* now print the values in hex, 4 or 8 to the row */
3009 for (col
= 0; col
< ncols
&& regnum
< numregs
; regnum
++)
3011 if (*REGISTER_NAME (regnum
) == '\0')
3012 continue; /* unused register */
3013 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
3014 break; /* end row: reached FP register */
3015 /* OK: get the data in raw format. */
3016 if (!frame_register_read (selected_frame
, regnum
, raw_buffer
))
3017 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
3018 /* pad small registers */
3019 for (byte
= 0; byte
< (MIPS_REGSIZE
- REGISTER_VIRTUAL_SIZE (regnum
)); byte
++)
3020 printf_filtered (" ");
3021 /* Now print the register value in hex, endian order. */
3022 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3023 for (byte
= REGISTER_RAW_SIZE (regnum
) - REGISTER_VIRTUAL_SIZE (regnum
);
3024 byte
< REGISTER_RAW_SIZE (regnum
);
3026 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
3028 for (byte
= REGISTER_VIRTUAL_SIZE (regnum
) - 1;
3031 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
3032 printf_filtered (" ");
3035 if (col
> 0) /* ie. if we actually printed anything... */
3036 printf_filtered ("\n");
3041 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
3044 mips_do_registers_info (int regnum
, int fpregs
)
3046 if (regnum
!= -1) /* do one specified register */
3048 if (*(REGISTER_NAME (regnum
)) == '\0')
3049 error ("Not a valid register for the current processor type");
3051 mips_print_register (regnum
, 0);
3052 printf_filtered ("\n");
3055 /* do all (or most) registers */
3058 while (regnum
< NUM_REGS
)
3060 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
3061 if (fpregs
) /* true for "INFO ALL-REGISTERS" command */
3062 regnum
= do_fp_register_row (regnum
); /* FP regs */
3064 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
3066 regnum
= do_gp_register_row (regnum
); /* GP (int) regs */
3071 /* Return number of args passed to a frame. described by FIP.
3072 Can return -1, meaning no way to tell. */
3075 mips_frame_num_args (struct frame_info
*frame
)
3080 /* Is this a branch with a delay slot? */
3082 static int is_delayed (unsigned long);
3085 is_delayed (unsigned long insn
)
3088 for (i
= 0; i
< NUMOPCODES
; ++i
)
3089 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
3090 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
3092 return (i
< NUMOPCODES
3093 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
3094 | INSN_COND_BRANCH_DELAY
3095 | INSN_COND_BRANCH_LIKELY
)));
3099 mips_step_skips_delay (CORE_ADDR pc
)
3101 char buf
[MIPS_INSTLEN
];
3103 /* There is no branch delay slot on MIPS16. */
3104 if (pc_is_mips16 (pc
))
3107 if (target_read_memory (pc
, buf
, MIPS_INSTLEN
) != 0)
3108 /* If error reading memory, guess that it is not a delayed branch. */
3110 return is_delayed ((unsigned long) extract_unsigned_integer (buf
, MIPS_INSTLEN
));
3114 /* Skip the PC past function prologue instructions (32-bit version).
3115 This is a helper function for mips_skip_prologue. */
3118 mips32_skip_prologue (CORE_ADDR pc
)
3122 int seen_sp_adjust
= 0;
3123 int load_immediate_bytes
= 0;
3125 /* Skip the typical prologue instructions. These are the stack adjustment
3126 instruction and the instructions that save registers on the stack
3127 or in the gcc frame. */
3128 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS_INSTLEN
)
3130 unsigned long high_word
;
3132 inst
= mips_fetch_instruction (pc
);
3133 high_word
= (inst
>> 16) & 0xffff;
3135 if (high_word
== 0x27bd /* addiu $sp,$sp,offset */
3136 || high_word
== 0x67bd) /* daddiu $sp,$sp,offset */
3138 else if (inst
== 0x03a1e823 || /* subu $sp,$sp,$at */
3139 inst
== 0x03a8e823) /* subu $sp,$sp,$t0 */
3141 else if (((inst
& 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
3142 || (inst
& 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
3143 && (inst
& 0x001F0000)) /* reg != $zero */
3146 else if ((inst
& 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
3148 else if ((inst
& 0xF3E00000) == 0xA3C00000 && (inst
& 0x001F0000))
3150 continue; /* reg != $zero */
3152 /* move $s8,$sp. With different versions of gas this will be either
3153 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
3154 Accept any one of these. */
3155 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
3158 else if ((inst
& 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
3160 else if (high_word
== 0x3c1c) /* lui $gp,n */
3162 else if (high_word
== 0x279c) /* addiu $gp,$gp,n */
3164 else if (inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
3165 || inst
== 0x033ce021) /* addu $gp,$t9,$gp */
3167 /* The following instructions load $at or $t0 with an immediate
3168 value in preparation for a stack adjustment via
3169 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
3170 a local variable, so we accept them only before a stack adjustment
3171 instruction was seen. */
3172 else if (!seen_sp_adjust
)
3174 if (high_word
== 0x3c01 || /* lui $at,n */
3175 high_word
== 0x3c08) /* lui $t0,n */
3177 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
3180 else if (high_word
== 0x3421 || /* ori $at,$at,n */
3181 high_word
== 0x3508 || /* ori $t0,$t0,n */
3182 high_word
== 0x3401 || /* ori $at,$zero,n */
3183 high_word
== 0x3408) /* ori $t0,$zero,n */
3185 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
3195 /* In a frameless function, we might have incorrectly
3196 skipped some load immediate instructions. Undo the skipping
3197 if the load immediate was not followed by a stack adjustment. */
3198 if (load_immediate_bytes
&& !seen_sp_adjust
)
3199 pc
-= load_immediate_bytes
;
3203 /* Skip the PC past function prologue instructions (16-bit version).
3204 This is a helper function for mips_skip_prologue. */
3207 mips16_skip_prologue (CORE_ADDR pc
)
3210 int extend_bytes
= 0;
3211 int prev_extend_bytes
;
3213 /* Table of instructions likely to be found in a function prologue. */
3216 unsigned short inst
;
3217 unsigned short mask
;
3224 , /* addiu $sp,offset */
3228 , /* daddiu $sp,offset */
3232 , /* sw reg,n($sp) */
3236 , /* sd reg,n($sp) */
3240 , /* sw $ra,n($sp) */
3244 , /* sd $ra,n($sp) */
3252 , /* sw $a0-$a3,n($s1) */
3256 , /* move reg,$a0-$a3 */
3260 , /* entry pseudo-op */
3264 , /* addiu $s1,$sp,n */
3267 } /* end of table marker */
3270 /* Skip the typical prologue instructions. These are the stack adjustment
3271 instruction and the instructions that save registers on the stack
3272 or in the gcc frame. */
3273 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS16_INSTLEN
)
3275 unsigned short inst
;
3278 inst
= mips_fetch_instruction (pc
);
3280 /* Normally we ignore an extend instruction. However, if it is
3281 not followed by a valid prologue instruction, we must adjust
3282 the pc back over the extend so that it won't be considered
3283 part of the prologue. */
3284 if ((inst
& 0xf800) == 0xf000) /* extend */
3286 extend_bytes
= MIPS16_INSTLEN
;
3289 prev_extend_bytes
= extend_bytes
;
3292 /* Check for other valid prologue instructions besides extend. */
3293 for (i
= 0; table
[i
].mask
!= 0; i
++)
3294 if ((inst
& table
[i
].mask
) == table
[i
].inst
) /* found, get out */
3296 if (table
[i
].mask
!= 0) /* it was in table? */
3297 continue; /* ignore it */
3301 /* Return the current pc, adjusted backwards by 2 if
3302 the previous instruction was an extend. */
3303 return pc
- prev_extend_bytes
;
3309 /* To skip prologues, I use this predicate. Returns either PC itself
3310 if the code at PC does not look like a function prologue; otherwise
3311 returns an address that (if we're lucky) follows the prologue. If
3312 LENIENT, then we must skip everything which is involved in setting
3313 up the frame (it's OK to skip more, just so long as we don't skip
3314 anything which might clobber the registers which are being saved.
3315 We must skip more in the case where part of the prologue is in the
3316 delay slot of a non-prologue instruction). */
3319 mips_skip_prologue (CORE_ADDR pc
)
3321 /* See if we can determine the end of the prologue via the symbol table.
3322 If so, then return either PC, or the PC after the prologue, whichever
3325 CORE_ADDR post_prologue_pc
= after_prologue (pc
, NULL
);
3327 if (post_prologue_pc
!= 0)
3328 return max (pc
, post_prologue_pc
);
3330 /* Can't determine prologue from the symbol table, need to examine
3333 if (pc_is_mips16 (pc
))
3334 return mips16_skip_prologue (pc
);
3336 return mips32_skip_prologue (pc
);
3339 /* Determine how a return value is stored within the MIPS register
3340 file, given the return type `valtype'. */
3342 struct return_value_word
3351 return_value_location (struct type
*valtype
,
3352 struct return_value_word
*hi
,
3353 struct return_value_word
*lo
)
3355 int len
= TYPE_LENGTH (valtype
);
3357 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
3358 && ((MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
&& (len
== 4 || len
== 8))
3359 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
&& len
== 4)))
3361 if (!FP_REGISTER_DOUBLE
&& len
== 8)
3363 /* We need to break a 64bit float in two 32 bit halves and
3364 spread them across a floating-point register pair. */
3365 lo
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3366 hi
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 0 : 4;
3367 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3368 && REGISTER_RAW_SIZE (FP0_REGNUM
) == 8)
3370 hi
->reg_offset
= lo
->reg_offset
;
3371 lo
->reg
= FP0_REGNUM
+ 0;
3372 hi
->reg
= FP0_REGNUM
+ 1;
3378 /* The floating point value fits in a single floating-point
3380 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3381 && REGISTER_RAW_SIZE (FP0_REGNUM
) == 8
3384 lo
->reg
= FP0_REGNUM
;
3395 /* Locate a result possibly spread across two registers. */
3397 lo
->reg
= regnum
+ 0;
3398 hi
->reg
= regnum
+ 1;
3399 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3400 && len
< MIPS_SAVED_REGSIZE
)
3402 /* "un-left-justify" the value in the low register */
3403 lo
->reg_offset
= MIPS_SAVED_REGSIZE
- len
;
3408 else if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3409 && len
> MIPS_SAVED_REGSIZE
/* odd-size structs */
3410 && len
< MIPS_SAVED_REGSIZE
* 2
3411 && (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
3412 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
3414 /* "un-left-justify" the value spread across two registers. */
3415 lo
->reg_offset
= 2 * MIPS_SAVED_REGSIZE
- len
;
3416 lo
->len
= MIPS_SAVED_REGSIZE
- lo
->reg_offset
;
3418 hi
->len
= len
- lo
->len
;
3422 /* Only perform a partial copy of the second register. */
3425 if (len
> MIPS_SAVED_REGSIZE
)
3427 lo
->len
= MIPS_SAVED_REGSIZE
;
3428 hi
->len
= len
- MIPS_SAVED_REGSIZE
;
3436 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3437 && REGISTER_RAW_SIZE (regnum
) == 8
3438 && MIPS_SAVED_REGSIZE
== 4)
3440 /* Account for the fact that only the least-signficant part
3441 of the register is being used */
3442 lo
->reg_offset
+= 4;
3443 hi
->reg_offset
+= 4;
3446 hi
->buf_offset
= lo
->len
;
3450 /* Given a return value in `regbuf' with a type `valtype', extract and
3451 copy its value into `valbuf'. */
3454 mips_extract_return_value (struct type
*valtype
,
3455 char regbuf
[REGISTER_BYTES
],
3458 struct return_value_word lo
;
3459 struct return_value_word hi
;
3460 return_value_location (valtype
, &hi
, &lo
);
3462 memcpy (valbuf
+ lo
.buf_offset
,
3463 regbuf
+ REGISTER_BYTE (lo
.reg
) + lo
.reg_offset
,
3467 memcpy (valbuf
+ hi
.buf_offset
,
3468 regbuf
+ REGISTER_BYTE (hi
.reg
) + hi
.reg_offset
,
3472 /* Given a return value in `valbuf' with a type `valtype', write it's
3473 value into the appropriate register. */
3476 mips_store_return_value (struct type
*valtype
, char *valbuf
)
3478 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
3479 struct return_value_word lo
;
3480 struct return_value_word hi
;
3481 return_value_location (valtype
, &hi
, &lo
);
3483 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3484 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
3485 write_register_bytes (REGISTER_BYTE (lo
.reg
),
3487 REGISTER_RAW_SIZE (lo
.reg
));
3491 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3492 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
3493 write_register_bytes (REGISTER_BYTE (hi
.reg
),
3495 REGISTER_RAW_SIZE (hi
.reg
));
3499 /* Exported procedure: Is PC in the signal trampoline code */
3502 in_sigtramp (CORE_ADDR pc
, char *ignore
)
3504 if (sigtramp_address
== 0)
3506 return (pc
>= sigtramp_address
&& pc
< sigtramp_end
);
3509 /* Root of all "set mips "/"show mips " commands. This will eventually be
3510 used for all MIPS-specific commands. */
3513 show_mips_command (char *args
, int from_tty
)
3515 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
3519 set_mips_command (char *args
, int from_tty
)
3521 printf_unfiltered ("\"set mips\" must be followed by an appropriate subcommand.\n");
3522 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
3525 /* Commands to show/set the MIPS FPU type. */
3528 show_mipsfpu_command (char *args
, int from_tty
)
3531 switch (MIPS_FPU_TYPE
)
3533 case MIPS_FPU_SINGLE
:
3534 fpu
= "single-precision";
3536 case MIPS_FPU_DOUBLE
:
3537 fpu
= "double-precision";
3540 fpu
= "absent (none)";
3543 internal_error (__FILE__
, __LINE__
, "bad switch");
3545 if (mips_fpu_type_auto
)
3546 printf_unfiltered ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
3549 printf_unfiltered ("The MIPS floating-point coprocessor is assumed to be %s\n",
3555 set_mipsfpu_command (char *args
, int from_tty
)
3557 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
3558 show_mipsfpu_command (args
, from_tty
);
3562 set_mipsfpu_single_command (char *args
, int from_tty
)
3564 mips_fpu_type
= MIPS_FPU_SINGLE
;
3565 mips_fpu_type_auto
= 0;
3568 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_SINGLE
;
3573 set_mipsfpu_double_command (char *args
, int from_tty
)
3575 mips_fpu_type
= MIPS_FPU_DOUBLE
;
3576 mips_fpu_type_auto
= 0;
3579 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_DOUBLE
;
3584 set_mipsfpu_none_command (char *args
, int from_tty
)
3586 mips_fpu_type
= MIPS_FPU_NONE
;
3587 mips_fpu_type_auto
= 0;
3590 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_NONE
;
3595 set_mipsfpu_auto_command (char *args
, int from_tty
)
3597 mips_fpu_type_auto
= 1;
3600 /* Command to set the processor type. */
3603 mips_set_processor_type_command (char *args
, int from_tty
)
3607 if (tmp_mips_processor_type
== NULL
|| *tmp_mips_processor_type
== '\0')
3609 printf_unfiltered ("The known MIPS processor types are as follows:\n\n");
3610 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
3611 printf_unfiltered ("%s\n", mips_processor_type_table
[i
].name
);
3613 /* Restore the value. */
3614 tmp_mips_processor_type
= xstrdup (mips_processor_type
);
3619 if (!mips_set_processor_type (tmp_mips_processor_type
))
3621 error ("Unknown processor type `%s'.", tmp_mips_processor_type
);
3622 /* Restore its value. */
3623 tmp_mips_processor_type
= xstrdup (mips_processor_type
);
3628 mips_show_processor_type_command (char *args
, int from_tty
)
3632 /* Modify the actual processor type. */
3635 mips_set_processor_type (char *str
)
3642 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
3644 if (strcasecmp (str
, mips_processor_type_table
[i
].name
) == 0)
3646 mips_processor_type
= str
;
3647 mips_processor_reg_names
= mips_processor_type_table
[i
].regnames
;
3649 /* FIXME tweak fpu flag too */
3656 /* Attempt to identify the particular processor model by reading the
3660 mips_read_processor_type (void)
3664 prid
= read_register (PRID_REGNUM
);
3666 if ((prid
& ~0xf) == 0x700)
3667 return savestring ("r3041", strlen ("r3041"));
3672 /* Just like reinit_frame_cache, but with the right arguments to be
3673 callable as an sfunc. */
3676 reinit_frame_cache_sfunc (char *args
, int from_tty
,
3677 struct cmd_list_element
*c
)
3679 reinit_frame_cache ();
3683 gdb_print_insn_mips (bfd_vma memaddr
, disassemble_info
*info
)
3685 mips_extra_func_info_t proc_desc
;
3687 /* Search for the function containing this address. Set the low bit
3688 of the address when searching, in case we were given an even address
3689 that is the start of a 16-bit function. If we didn't do this,
3690 the search would fail because the symbol table says the function
3691 starts at an odd address, i.e. 1 byte past the given address. */
3692 memaddr
= ADDR_BITS_REMOVE (memaddr
);
3693 proc_desc
= non_heuristic_proc_desc (MAKE_MIPS16_ADDR (memaddr
), NULL
);
3695 /* Make an attempt to determine if this is a 16-bit function. If
3696 the procedure descriptor exists and the address therein is odd,
3697 it's definitely a 16-bit function. Otherwise, we have to just
3698 guess that if the address passed in is odd, it's 16-bits. */
3700 info
->mach
= pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)) ?
3701 bfd_mach_mips16
: TM_PRINT_INSN_MACH
;
3703 info
->mach
= pc_is_mips16 (memaddr
) ?
3704 bfd_mach_mips16
: TM_PRINT_INSN_MACH
;
3706 /* Round down the instruction address to the appropriate boundary. */
3707 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
3709 /* Call the appropriate disassembler based on the target endian-ness. */
3710 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3711 return print_insn_big_mips (memaddr
, info
);
3713 return print_insn_little_mips (memaddr
, info
);
3716 /* Old-style breakpoint macros.
3717 The IDT board uses an unusual breakpoint value, and sometimes gets
3718 confused when it sees the usual MIPS breakpoint instruction. */
3720 #define BIG_BREAKPOINT {0, 0x5, 0, 0xd}
3721 #define LITTLE_BREAKPOINT {0xd, 0, 0x5, 0}
3722 #define PMON_BIG_BREAKPOINT {0, 0, 0, 0xd}
3723 #define PMON_LITTLE_BREAKPOINT {0xd, 0, 0, 0}
3724 #define IDT_BIG_BREAKPOINT {0, 0, 0x0a, 0xd}
3725 #define IDT_LITTLE_BREAKPOINT {0xd, 0x0a, 0, 0}
3726 #define MIPS16_BIG_BREAKPOINT {0xe8, 0xa5}
3727 #define MIPS16_LITTLE_BREAKPOINT {0xa5, 0xe8}
3729 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
3730 counter value to determine whether a 16- or 32-bit breakpoint should be
3731 used. It returns a pointer to a string of bytes that encode a breakpoint
3732 instruction, stores the length of the string to *lenptr, and adjusts pc
3733 (if necessary) to point to the actual memory location where the
3734 breakpoint should be inserted. */
3736 const unsigned char *
3737 mips_breakpoint_from_pc (CORE_ADDR
* pcptr
, int *lenptr
)
3739 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3741 if (pc_is_mips16 (*pcptr
))
3743 static unsigned char mips16_big_breakpoint
[] =
3744 MIPS16_BIG_BREAKPOINT
;
3745 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
3746 *lenptr
= sizeof (mips16_big_breakpoint
);
3747 return mips16_big_breakpoint
;
3751 static unsigned char big_breakpoint
[] = BIG_BREAKPOINT
;
3752 static unsigned char pmon_big_breakpoint
[] = PMON_BIG_BREAKPOINT
;
3753 static unsigned char idt_big_breakpoint
[] = IDT_BIG_BREAKPOINT
;
3755 *lenptr
= sizeof (big_breakpoint
);
3757 if (strcmp (target_shortname
, "mips") == 0)
3758 return idt_big_breakpoint
;
3759 else if (strcmp (target_shortname
, "ddb") == 0
3760 || strcmp (target_shortname
, "pmon") == 0
3761 || strcmp (target_shortname
, "lsi") == 0)
3762 return pmon_big_breakpoint
;
3764 return big_breakpoint
;
3769 if (pc_is_mips16 (*pcptr
))
3771 static unsigned char mips16_little_breakpoint
[] =
3772 MIPS16_LITTLE_BREAKPOINT
;
3773 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
3774 *lenptr
= sizeof (mips16_little_breakpoint
);
3775 return mips16_little_breakpoint
;
3779 static unsigned char little_breakpoint
[] = LITTLE_BREAKPOINT
;
3780 static unsigned char pmon_little_breakpoint
[] =
3781 PMON_LITTLE_BREAKPOINT
;
3782 static unsigned char idt_little_breakpoint
[] =
3783 IDT_LITTLE_BREAKPOINT
;
3785 *lenptr
= sizeof (little_breakpoint
);
3787 if (strcmp (target_shortname
, "mips") == 0)
3788 return idt_little_breakpoint
;
3789 else if (strcmp (target_shortname
, "ddb") == 0
3790 || strcmp (target_shortname
, "pmon") == 0
3791 || strcmp (target_shortname
, "lsi") == 0)
3792 return pmon_little_breakpoint
;
3794 return little_breakpoint
;
3799 /* If PC is in a mips16 call or return stub, return the address of the target
3800 PC, which is either the callee or the caller. There are several
3801 cases which must be handled:
3803 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
3804 target PC is in $31 ($ra).
3805 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
3806 and the target PC is in $2.
3807 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3808 before the jal instruction, this is effectively a call stub
3809 and the the target PC is in $2. Otherwise this is effectively
3810 a return stub and the target PC is in $18.
3812 See the source code for the stubs in gcc/config/mips/mips16.S for
3815 This function implements the SKIP_TRAMPOLINE_CODE macro.
3819 mips_skip_stub (CORE_ADDR pc
)
3822 CORE_ADDR start_addr
;
3824 /* Find the starting address and name of the function containing the PC. */
3825 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
3828 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
3829 target PC is in $31 ($ra). */
3830 if (strcmp (name
, "__mips16_ret_sf") == 0
3831 || strcmp (name
, "__mips16_ret_df") == 0)
3832 return read_signed_register (RA_REGNUM
);
3834 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
3836 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
3837 and the target PC is in $2. */
3838 if (name
[19] >= '0' && name
[19] <= '9')
3839 return read_signed_register (2);
3841 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3842 before the jal instruction, this is effectively a call stub
3843 and the the target PC is in $2. Otherwise this is effectively
3844 a return stub and the target PC is in $18. */
3845 else if (name
[19] == 's' || name
[19] == 'd')
3847 if (pc
== start_addr
)
3849 /* Check if the target of the stub is a compiler-generated
3850 stub. Such a stub for a function bar might have a name
3851 like __fn_stub_bar, and might look like this:
3856 la $1,bar (becomes a lui/addiu pair)
3858 So scan down to the lui/addi and extract the target
3859 address from those two instructions. */
3861 CORE_ADDR target_pc
= read_signed_register (2);
3865 /* See if the name of the target function is __fn_stub_*. */
3866 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) == 0)
3868 if (strncmp (name
, "__fn_stub_", 10) != 0
3869 && strcmp (name
, "etext") != 0
3870 && strcmp (name
, "_etext") != 0)
3873 /* Scan through this _fn_stub_ code for the lui/addiu pair.
3874 The limit on the search is arbitrarily set to 20
3875 instructions. FIXME. */
3876 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSTLEN
)
3878 inst
= mips_fetch_instruction (target_pc
);
3879 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
3880 pc
= (inst
<< 16) & 0xffff0000; /* high word */
3881 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
3882 return pc
| (inst
& 0xffff); /* low word */
3885 /* Couldn't find the lui/addui pair, so return stub address. */
3889 /* This is the 'return' part of a call stub. The return
3890 address is in $r18. */
3891 return read_signed_register (18);
3894 return 0; /* not a stub */
3898 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
3899 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
3902 mips_in_call_stub (CORE_ADDR pc
, char *name
)
3904 CORE_ADDR start_addr
;
3906 /* Find the starting address of the function containing the PC. If the
3907 caller didn't give us a name, look it up at the same time. */
3908 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) == 0)
3911 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
3913 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
3914 if (name
[19] >= '0' && name
[19] <= '9')
3916 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3917 before the jal instruction, this is effectively a call stub. */
3918 else if (name
[19] == 's' || name
[19] == 'd')
3919 return pc
== start_addr
;
3922 return 0; /* not a stub */
3926 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
3927 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
3930 mips_in_return_stub (CORE_ADDR pc
, char *name
)
3932 CORE_ADDR start_addr
;
3934 /* Find the starting address of the function containing the PC. */
3935 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
3938 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
3939 if (strcmp (name
, "__mips16_ret_sf") == 0
3940 || strcmp (name
, "__mips16_ret_df") == 0)
3943 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
3944 i.e. after the jal instruction, this is effectively a return stub. */
3945 if (strncmp (name
, "__mips16_call_stub_", 19) == 0
3946 && (name
[19] == 's' || name
[19] == 'd')
3947 && pc
!= start_addr
)
3950 return 0; /* not a stub */
3954 /* Return non-zero if the PC is in a library helper function that should
3955 be ignored. This implements the IGNORE_HELPER_CALL macro. */
3958 mips_ignore_helper (CORE_ADDR pc
)
3962 /* Find the starting address and name of the function containing the PC. */
3963 if (find_pc_partial_function (pc
, &name
, NULL
, NULL
) == 0)
3966 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
3967 that we want to ignore. */
3968 return (strcmp (name
, "__mips16_ret_sf") == 0
3969 || strcmp (name
, "__mips16_ret_df") == 0);
3973 /* Return a location where we can set a breakpoint that will be hit
3974 when an inferior function call returns. This is normally the
3975 program's entry point. Executables that don't have an entry
3976 point (e.g. programs in ROM) should define a symbol __CALL_DUMMY_ADDRESS
3977 whose address is the location where the breakpoint should be placed. */
3980 mips_call_dummy_address (void)
3982 struct minimal_symbol
*sym
;
3984 sym
= lookup_minimal_symbol ("__CALL_DUMMY_ADDRESS", NULL
, NULL
);
3986 return SYMBOL_VALUE_ADDRESS (sym
);
3988 return entry_point_address ();
3992 /* If the current gcc for this target does not produce correct debugging
3993 information for float parameters, both prototyped and unprototyped, then
3994 define this macro. This forces gdb to always assume that floats are
3995 passed as doubles and then converted in the callee.
3997 For the mips chip, it appears that the debug info marks the parameters as
3998 floats regardless of whether the function is prototyped, but the actual
3999 values are passed as doubles for the non-prototyped case and floats for
4000 the prototyped case. Thus we choose to make the non-prototyped case work
4001 for C and break the prototyped case, since the non-prototyped case is
4002 probably much more common. (FIXME). */
4005 mips_coerce_float_to_double (struct type
*formal
, struct type
*actual
)
4007 return current_language
->la_language
== language_c
;
4010 /* When debugging a 64 MIPS target running a 32 bit ABI, the size of
4011 the register stored on the stack (32) is different to its real raw
4012 size (64). The below ensures that registers are fetched from the
4013 stack using their ABI size and then stored into the RAW_BUFFER
4014 using their raw size.
4016 The alternative to adding this function would be to add an ABI
4017 macro - REGISTER_STACK_SIZE(). */
4020 mips_get_saved_register (char *raw_buffer
,
4023 struct frame_info
*frame
,
4025 enum lval_type
*lval
)
4029 if (!target_has_registers
)
4030 error ("No registers.");
4032 /* Normal systems don't optimize out things with register numbers. */
4033 if (optimized
!= NULL
)
4035 addr
= find_saved_register (frame
, regnum
);
4039 *lval
= lval_memory
;
4040 if (regnum
== SP_REGNUM
)
4042 if (raw_buffer
!= NULL
)
4044 /* Put it back in target format. */
4045 store_address (raw_buffer
, REGISTER_RAW_SIZE (regnum
),
4052 if (raw_buffer
!= NULL
)
4056 /* Only MIPS_SAVED_REGSIZE bytes of GP registers are
4058 val
= read_memory_integer (addr
, MIPS_SAVED_REGSIZE
);
4060 val
= read_memory_integer (addr
, REGISTER_RAW_SIZE (regnum
));
4061 store_address (raw_buffer
, REGISTER_RAW_SIZE (regnum
), val
);
4067 *lval
= lval_register
;
4068 addr
= REGISTER_BYTE (regnum
);
4069 if (raw_buffer
!= NULL
)
4070 read_register_gen (regnum
, raw_buffer
);
4076 /* Immediately after a function call, return the saved pc.
4077 Can't always go through the frames for this because on some machines
4078 the new frame is not set up until the new function executes
4079 some instructions. */
4082 mips_saved_pc_after_call (struct frame_info
*frame
)
4084 return read_signed_register (RA_REGNUM
);
4088 /* Convert a dbx stab register number (from `r' declaration) to a gdb
4092 mips_stab_reg_to_regnum (int num
)
4097 return num
+ FP0_REGNUM
- 38;
4100 /* Convert a ecoff register number to a gdb REGNUM */
4103 mips_ecoff_reg_to_regnum (int num
)
4108 return num
+ FP0_REGNUM
- 32;
4111 /* Convert an integer into an address. By first converting the value
4112 into a pointer and then extracting it signed, the address is
4113 guarenteed to be correctly sign extended. */
4116 mips_integer_to_address (struct type
*type
, void *buf
)
4118 char *tmp
= alloca (TYPE_LENGTH (builtin_type_void_data_ptr
));
4119 LONGEST val
= unpack_long (type
, buf
);
4120 store_signed_integer (tmp
, TYPE_LENGTH (builtin_type_void_data_ptr
), val
);
4121 return extract_signed_integer (tmp
,
4122 TYPE_LENGTH (builtin_type_void_data_ptr
));
4125 static struct gdbarch
*
4126 mips_gdbarch_init (struct gdbarch_info info
,
4127 struct gdbarch_list
*arches
)
4129 static LONGEST mips_call_dummy_words
[] =
4131 struct gdbarch
*gdbarch
;
4132 struct gdbarch_tdep
*tdep
;
4134 enum mips_abi mips_abi
;
4136 /* Reset the disassembly info, in case it was set to something
4138 tm_print_insn_info
.flavour
= bfd_target_unknown_flavour
;
4139 tm_print_insn_info
.arch
= bfd_arch_unknown
;
4140 tm_print_insn_info
.mach
= 0;
4142 /* Extract the elf_flags if available */
4143 if (info
.abfd
!= NULL
4144 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
4145 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
4149 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
4150 switch ((elf_flags
& EF_MIPS_ABI
))
4152 case E_MIPS_ABI_O32
:
4153 mips_abi
= MIPS_ABI_O32
;
4155 case E_MIPS_ABI_O64
:
4156 mips_abi
= MIPS_ABI_O64
;
4158 case E_MIPS_ABI_EABI32
:
4159 mips_abi
= MIPS_ABI_EABI32
;
4161 case E_MIPS_ABI_EABI64
:
4162 mips_abi
= MIPS_ABI_EABI64
;
4165 if ((elf_flags
& EF_MIPS_ABI2
))
4166 mips_abi
= MIPS_ABI_N32
;
4168 mips_abi
= MIPS_ABI_UNKNOWN
;
4172 /* Try the architecture for any hint of the corect ABI */
4173 if (mips_abi
== MIPS_ABI_UNKNOWN
4174 && info
.bfd_arch_info
!= NULL
4175 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
4177 switch (info
.bfd_arch_info
->mach
)
4179 case bfd_mach_mips3900
:
4180 mips_abi
= MIPS_ABI_EABI32
;
4182 case bfd_mach_mips4100
:
4183 case bfd_mach_mips5000
:
4184 mips_abi
= MIPS_ABI_EABI64
;
4186 case bfd_mach_mips8000
:
4187 case bfd_mach_mips10000
:
4188 mips_abi
= MIPS_ABI_N32
;
4192 #ifdef MIPS_DEFAULT_ABI
4193 if (mips_abi
== MIPS_ABI_UNKNOWN
)
4194 mips_abi
= MIPS_DEFAULT_ABI
;
4199 fprintf_unfiltered (gdb_stdlog
,
4200 "mips_gdbarch_init: elf_flags = 0x%08x\n",
4202 fprintf_unfiltered (gdb_stdlog
,
4203 "mips_gdbarch_init: mips_abi = %d\n",
4207 /* try to find a pre-existing architecture */
4208 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
4210 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
4212 /* MIPS needs to be pedantic about which ABI the object is
4214 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
4216 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
4218 return arches
->gdbarch
;
4221 /* Need a new architecture. Fill in a target specific vector. */
4222 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
4223 gdbarch
= gdbarch_alloc (&info
, tdep
);
4224 tdep
->elf_flags
= elf_flags
;
4226 /* Initially set everything according to the default ABI/ISA. */
4227 set_gdbarch_short_bit (gdbarch
, 16);
4228 set_gdbarch_int_bit (gdbarch
, 32);
4229 set_gdbarch_float_bit (gdbarch
, 32);
4230 set_gdbarch_double_bit (gdbarch
, 64);
4231 set_gdbarch_long_double_bit (gdbarch
, 64);
4232 set_gdbarch_register_raw_size (gdbarch
, mips_register_raw_size
);
4233 tdep
->mips_abi
= mips_abi
;
4238 tdep
->mips_abi_string
= "o32";
4239 tdep
->mips_default_saved_regsize
= 4;
4240 tdep
->mips_default_stack_argsize
= 4;
4241 tdep
->mips_fp_register_double
= 0;
4242 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
4243 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 4 - 1;
4244 tdep
->mips_regs_have_home_p
= 1;
4245 tdep
->gdb_target_is_mips64
= 0;
4246 tdep
->default_mask_address_p
= 0;
4247 set_gdbarch_long_bit (gdbarch
, 32);
4248 set_gdbarch_ptr_bit (gdbarch
, 32);
4249 set_gdbarch_long_long_bit (gdbarch
, 64);
4252 tdep
->mips_abi_string
= "o64";
4253 tdep
->mips_default_saved_regsize
= 8;
4254 tdep
->mips_default_stack_argsize
= 8;
4255 tdep
->mips_fp_register_double
= 1;
4256 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
4257 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 4 - 1;
4258 tdep
->mips_regs_have_home_p
= 1;
4259 tdep
->gdb_target_is_mips64
= 1;
4260 tdep
->default_mask_address_p
= 0;
4261 set_gdbarch_long_bit (gdbarch
, 32);
4262 set_gdbarch_ptr_bit (gdbarch
, 32);
4263 set_gdbarch_long_long_bit (gdbarch
, 64);
4265 case MIPS_ABI_EABI32
:
4266 tdep
->mips_abi_string
= "eabi32";
4267 tdep
->mips_default_saved_regsize
= 4;
4268 tdep
->mips_default_stack_argsize
= 4;
4269 tdep
->mips_fp_register_double
= 0;
4270 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
4271 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 8 - 1;
4272 tdep
->mips_regs_have_home_p
= 0;
4273 tdep
->gdb_target_is_mips64
= 0;
4274 tdep
->default_mask_address_p
= 0;
4275 set_gdbarch_long_bit (gdbarch
, 32);
4276 set_gdbarch_ptr_bit (gdbarch
, 32);
4277 set_gdbarch_long_long_bit (gdbarch
, 64);
4279 case MIPS_ABI_EABI64
:
4280 tdep
->mips_abi_string
= "eabi64";
4281 tdep
->mips_default_saved_regsize
= 8;
4282 tdep
->mips_default_stack_argsize
= 8;
4283 tdep
->mips_fp_register_double
= 1;
4284 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
4285 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 8 - 1;
4286 tdep
->mips_regs_have_home_p
= 0;
4287 tdep
->gdb_target_is_mips64
= 1;
4288 tdep
->default_mask_address_p
= 0;
4289 set_gdbarch_long_bit (gdbarch
, 64);
4290 set_gdbarch_ptr_bit (gdbarch
, 64);
4291 set_gdbarch_long_long_bit (gdbarch
, 64);
4294 tdep
->mips_abi_string
= "n32";
4295 tdep
->mips_default_saved_regsize
= 4;
4296 tdep
->mips_default_stack_argsize
= 8;
4297 tdep
->mips_fp_register_double
= 1;
4298 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
4299 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 8 - 1;
4300 tdep
->mips_regs_have_home_p
= 0;
4301 tdep
->gdb_target_is_mips64
= 0;
4302 tdep
->default_mask_address_p
= 0;
4303 set_gdbarch_long_bit (gdbarch
, 32);
4304 set_gdbarch_ptr_bit (gdbarch
, 32);
4305 set_gdbarch_long_long_bit (gdbarch
, 64);
4307 /* Set up the disassembler info, so that we get the right
4308 register names from libopcodes. */
4309 tm_print_insn_info
.flavour
= bfd_target_elf_flavour
;
4310 tm_print_insn_info
.arch
= bfd_arch_mips
;
4311 if (info
.bfd_arch_info
!= NULL
4312 && info
.bfd_arch_info
->arch
== bfd_arch_mips
4313 && info
.bfd_arch_info
->mach
)
4314 tm_print_insn_info
.mach
= info
.bfd_arch_info
->mach
;
4316 tm_print_insn_info
.mach
= bfd_mach_mips8000
;
4319 tdep
->mips_abi_string
= "default";
4320 tdep
->mips_default_saved_regsize
= MIPS_REGSIZE
;
4321 tdep
->mips_default_stack_argsize
= MIPS_REGSIZE
;
4322 tdep
->mips_fp_register_double
= (REGISTER_VIRTUAL_SIZE (FP0_REGNUM
) == 8);
4323 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
4324 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 8 - 1;
4325 tdep
->mips_regs_have_home_p
= 1;
4326 tdep
->gdb_target_is_mips64
= 0;
4327 tdep
->default_mask_address_p
= 0;
4328 set_gdbarch_long_bit (gdbarch
, 32);
4329 set_gdbarch_ptr_bit (gdbarch
, 32);
4330 set_gdbarch_long_long_bit (gdbarch
, 64);
4334 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
4335 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
4338 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
4339 flag in object files because to do so would make it impossible to
4340 link with libraries compiled without "-gp32". This is
4341 unnecessarily restrictive.
4343 We could solve this problem by adding "-gp32" multilibs to gcc,
4344 but to set this flag before gcc is built with such multilibs will
4345 break too many systems.''
4347 But even more unhelpfully, the default linker output target for
4348 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
4349 for 64-bit programs - you need to change the ABI to change this,
4350 and not all gcc targets support that currently. Therefore using
4351 this flag to detect 32-bit mode would do the wrong thing given
4352 the current gcc - it would make GDB treat these 64-bit programs
4353 as 32-bit programs by default. */
4355 /* enable/disable the MIPS FPU */
4356 if (!mips_fpu_type_auto
)
4357 tdep
->mips_fpu_type
= mips_fpu_type
;
4358 else if (info
.bfd_arch_info
!= NULL
4359 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
4360 switch (info
.bfd_arch_info
->mach
)
4362 case bfd_mach_mips3900
:
4363 case bfd_mach_mips4100
:
4364 case bfd_mach_mips4111
:
4365 tdep
->mips_fpu_type
= MIPS_FPU_NONE
;
4367 case bfd_mach_mips4650
:
4368 tdep
->mips_fpu_type
= MIPS_FPU_SINGLE
;
4371 tdep
->mips_fpu_type
= MIPS_FPU_DOUBLE
;
4375 tdep
->mips_fpu_type
= MIPS_FPU_DOUBLE
;
4377 /* MIPS version of register names. NOTE: At present the MIPS
4378 register name management is part way between the old -
4379 #undef/#define REGISTER_NAMES and the new REGISTER_NAME(nr).
4380 Further work on it is required. */
4381 set_gdbarch_register_name (gdbarch
, mips_register_name
);
4382 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
4383 set_gdbarch_write_pc (gdbarch
, generic_target_write_pc
);
4384 set_gdbarch_read_fp (gdbarch
, generic_target_read_fp
);
4385 set_gdbarch_read_sp (gdbarch
, generic_target_read_sp
);
4386 set_gdbarch_write_sp (gdbarch
, generic_target_write_sp
);
4388 /* Add/remove bits from an address. The MIPS needs be careful to
4389 ensure that all 32 bit addresses are sign extended to 64 bits. */
4390 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
4392 /* There's a mess in stack frame creation. See comments in
4393 blockframe.c near reference to INIT_FRAME_PC_FIRST. */
4394 set_gdbarch_init_frame_pc_first (gdbarch
, mips_init_frame_pc_first
);
4395 set_gdbarch_init_frame_pc (gdbarch
, init_frame_pc_noop
);
4397 /* Map debug register numbers onto internal register numbers. */
4398 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
4399 set_gdbarch_ecoff_reg_to_regnum (gdbarch
, mips_ecoff_reg_to_regnum
);
4401 /* Initialize a frame */
4402 set_gdbarch_init_extra_frame_info (gdbarch
, mips_init_extra_frame_info
);
4404 /* MIPS version of CALL_DUMMY */
4406 set_gdbarch_call_dummy_p (gdbarch
, 1);
4407 set_gdbarch_call_dummy_stack_adjust_p (gdbarch
, 0);
4408 set_gdbarch_use_generic_dummy_frames (gdbarch
, 0);
4409 set_gdbarch_call_dummy_location (gdbarch
, AT_ENTRY_POINT
);
4410 set_gdbarch_call_dummy_address (gdbarch
, mips_call_dummy_address
);
4411 set_gdbarch_call_dummy_start_offset (gdbarch
, 0);
4412 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch
, 1);
4413 set_gdbarch_call_dummy_breakpoint_offset (gdbarch
, 0);
4414 set_gdbarch_call_dummy_length (gdbarch
, 0);
4415 set_gdbarch_pc_in_call_dummy (gdbarch
, pc_in_call_dummy_at_entry_point
);
4416 set_gdbarch_call_dummy_words (gdbarch
, mips_call_dummy_words
);
4417 set_gdbarch_sizeof_call_dummy_words (gdbarch
, sizeof (mips_call_dummy_words
));
4418 set_gdbarch_push_return_address (gdbarch
, mips_push_return_address
);
4419 set_gdbarch_push_arguments (gdbarch
, mips_push_arguments
);
4420 set_gdbarch_register_convertible (gdbarch
, generic_register_convertible_not
);
4421 set_gdbarch_coerce_float_to_double (gdbarch
, mips_coerce_float_to_double
);
4423 set_gdbarch_frame_chain_valid (gdbarch
, func_frame_chain_valid
);
4424 set_gdbarch_get_saved_register (gdbarch
, mips_get_saved_register
);
4426 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
4427 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
4428 set_gdbarch_decr_pc_after_break (gdbarch
, 0);
4430 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
4431 set_gdbarch_saved_pc_after_call (gdbarch
, mips_saved_pc_after_call
);
4433 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
4434 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
4435 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
4440 mips_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
4442 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4446 int ef_mips_32bitmode
;
4447 /* determine the ISA */
4448 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
4466 /* determine the size of a pointer */
4467 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
4468 fprintf_unfiltered (file
,
4469 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
4471 fprintf_unfiltered (file
,
4472 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
4474 fprintf_unfiltered (file
,
4475 "mips_dump_tdep: ef_mips_arch = %d\n",
4477 fprintf_unfiltered (file
,
4478 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
4480 tdep
->mips_abi_string
);
4481 fprintf_unfiltered (file
,
4482 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
4483 mips_mask_address_p (),
4484 tdep
->default_mask_address_p
);
4486 fprintf_unfiltered (file
,
4487 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
4488 FP_REGISTER_DOUBLE
);
4489 fprintf_unfiltered (file
,
4490 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
4491 MIPS_DEFAULT_FPU_TYPE
,
4492 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
4493 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
4494 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
4496 fprintf_unfiltered (file
,
4497 "mips_dump_tdep: MIPS_EABI = %d\n",
4499 fprintf_unfiltered (file
,
4500 "mips_dump_tdep: MIPS_LAST_FP_ARG_REGNUM = %d (%d regs)\n",
4501 MIPS_LAST_FP_ARG_REGNUM
,
4502 MIPS_LAST_FP_ARG_REGNUM
- FPA0_REGNUM
+ 1);
4503 fprintf_unfiltered (file
,
4504 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
4506 (MIPS_FPU_TYPE
== MIPS_FPU_NONE
? "none"
4507 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
4508 : MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
4510 fprintf_unfiltered (file
,
4511 "mips_dump_tdep: MIPS_DEFAULT_SAVED_REGSIZE = %d\n",
4512 MIPS_DEFAULT_SAVED_REGSIZE
);
4513 fprintf_unfiltered (file
,
4514 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
4515 FP_REGISTER_DOUBLE
);
4516 fprintf_unfiltered (file
,
4517 "mips_dump_tdep: MIPS_REGS_HAVE_HOME_P = %d\n",
4518 MIPS_REGS_HAVE_HOME_P
);
4519 fprintf_unfiltered (file
,
4520 "mips_dump_tdep: MIPS_DEFAULT_STACK_ARGSIZE = %d\n",
4521 MIPS_DEFAULT_STACK_ARGSIZE
);
4522 fprintf_unfiltered (file
,
4523 "mips_dump_tdep: MIPS_STACK_ARGSIZE = %d\n",
4524 MIPS_STACK_ARGSIZE
);
4525 fprintf_unfiltered (file
,
4526 "mips_dump_tdep: MIPS_REGSIZE = %d\n",
4528 fprintf_unfiltered (file
,
4529 "mips_dump_tdep: A0_REGNUM = %d\n",
4531 fprintf_unfiltered (file
,
4532 "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n",
4533 XSTRING (ADDR_BITS_REMOVE(ADDR
)));
4534 fprintf_unfiltered (file
,
4535 "mips_dump_tdep: ATTACH_DETACH # %s\n",
4536 XSTRING (ATTACH_DETACH
));
4537 fprintf_unfiltered (file
,
4538 "mips_dump_tdep: BADVADDR_REGNUM = %d\n",
4540 fprintf_unfiltered (file
,
4541 "mips_dump_tdep: BIG_BREAKPOINT = delete?\n");
4542 fprintf_unfiltered (file
,
4543 "mips_dump_tdep: CAUSE_REGNUM = %d\n",
4545 fprintf_unfiltered (file
,
4546 "mips_dump_tdep: CPLUS_MARKER = %c\n",
4548 fprintf_unfiltered (file
,
4549 "mips_dump_tdep: DEFAULT_MIPS_TYPE = %s\n",
4551 fprintf_unfiltered (file
,
4552 "mips_dump_tdep: DO_REGISTERS_INFO # %s\n",
4553 XSTRING (DO_REGISTERS_INFO
));
4554 fprintf_unfiltered (file
,
4555 "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n",
4556 XSTRING (DWARF_REG_TO_REGNUM (REGNUM
)));
4557 fprintf_unfiltered (file
,
4558 "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n",
4559 XSTRING (ECOFF_REG_TO_REGNUM (REGNUM
)));
4560 fprintf_unfiltered (file
,
4561 "mips_dump_tdep: ELF_MAKE_MSYMBOL_SPECIAL # %s\n",
4562 XSTRING (ELF_MAKE_MSYMBOL_SPECIAL (SYM
, MSYM
)));
4563 fprintf_unfiltered (file
,
4564 "mips_dump_tdep: FCRCS_REGNUM = %d\n",
4566 fprintf_unfiltered (file
,
4567 "mips_dump_tdep: FCRIR_REGNUM = %d\n",
4569 fprintf_unfiltered (file
,
4570 "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n",
4571 FIRST_EMBED_REGNUM
);
4572 fprintf_unfiltered (file
,
4573 "mips_dump_tdep: FPA0_REGNUM = %d\n",
4575 fprintf_unfiltered (file
,
4576 "mips_dump_tdep: GDB_TARGET_IS_MIPS64 = %d\n",
4577 GDB_TARGET_IS_MIPS64
);
4578 fprintf_unfiltered (file
,
4579 "mips_dump_tdep: GDB_TARGET_MASK_DISAS_PC # %s\n",
4580 XSTRING (GDB_TARGET_MASK_DISAS_PC (PC
)));
4581 fprintf_unfiltered (file
,
4582 "mips_dump_tdep: GDB_TARGET_UNMASK_DISAS_PC # %s\n",
4583 XSTRING (GDB_TARGET_UNMASK_DISAS_PC (PC
)));
4584 fprintf_unfiltered (file
,
4585 "mips_dump_tdep: GEN_REG_SAVE_MASK = %d\n",
4587 fprintf_unfiltered (file
,
4588 "mips_dump_tdep: HAVE_NONSTEPPABLE_WATCHPOINT # %s\n",
4589 XSTRING (HAVE_NONSTEPPABLE_WATCHPOINT
));
4590 fprintf_unfiltered (file
,
4591 "mips_dump_tdep: HI_REGNUM = %d\n",
4593 fprintf_unfiltered (file
,
4594 "mips_dump_tdep: IDT_BIG_BREAKPOINT = delete?\n");
4595 fprintf_unfiltered (file
,
4596 "mips_dump_tdep: IDT_LITTLE_BREAKPOINT = delete?\n");
4597 fprintf_unfiltered (file
,
4598 "mips_dump_tdep: IGNORE_HELPER_CALL # %s\n",
4599 XSTRING (IGNORE_HELPER_CALL (PC
)));
4600 fprintf_unfiltered (file
,
4601 "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n",
4602 XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC
, NAME
)));
4603 fprintf_unfiltered (file
,
4604 "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n",
4605 XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC
, NAME
)));
4606 fprintf_unfiltered (file
,
4607 "mips_dump_tdep: IS_MIPS16_ADDR = FIXME!\n");
4608 fprintf_unfiltered (file
,
4609 "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n",
4611 fprintf_unfiltered (file
,
4612 "mips_dump_tdep: LITTLE_BREAKPOINT = delete?\n");
4613 fprintf_unfiltered (file
,
4614 "mips_dump_tdep: LO_REGNUM = %d\n",
4616 #ifdef MACHINE_CPROC_FP_OFFSET
4617 fprintf_unfiltered (file
,
4618 "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n",
4619 MACHINE_CPROC_FP_OFFSET
);
4621 #ifdef MACHINE_CPROC_PC_OFFSET
4622 fprintf_unfiltered (file
,
4623 "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n",
4624 MACHINE_CPROC_PC_OFFSET
);
4626 #ifdef MACHINE_CPROC_SP_OFFSET
4627 fprintf_unfiltered (file
,
4628 "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n",
4629 MACHINE_CPROC_SP_OFFSET
);
4631 fprintf_unfiltered (file
,
4632 "mips_dump_tdep: MAKE_MIPS16_ADDR = FIXME!\n");
4633 fprintf_unfiltered (file
,
4634 "mips_dump_tdep: MIPS16_BIG_BREAKPOINT = delete?\n");
4635 fprintf_unfiltered (file
,
4636 "mips_dump_tdep: MIPS16_INSTLEN = %d\n",
4638 fprintf_unfiltered (file
,
4639 "mips_dump_tdep: MIPS16_LITTLE_BREAKPOINT = delete?\n");
4640 fprintf_unfiltered (file
,
4641 "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n");
4642 fprintf_unfiltered (file
,
4643 "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n");
4644 fprintf_unfiltered (file
,
4645 "mips_dump_tdep: MIPS_INSTLEN = %d\n",
4647 fprintf_unfiltered (file
,
4648 "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n",
4649 MIPS_LAST_ARG_REGNUM
,
4650 MIPS_LAST_ARG_REGNUM
- A0_REGNUM
+ 1);
4651 fprintf_unfiltered (file
,
4652 "mips_dump_tdep: MIPS_NUMREGS = %d\n",
4654 fprintf_unfiltered (file
,
4655 "mips_dump_tdep: MIPS_REGISTER_NAMES = delete?\n");
4656 fprintf_unfiltered (file
,
4657 "mips_dump_tdep: MIPS_SAVED_REGSIZE = %d\n",
4658 MIPS_SAVED_REGSIZE
);
4659 fprintf_unfiltered (file
,
4660 "mips_dump_tdep: MSYMBOL_IS_SPECIAL = function?\n");
4661 fprintf_unfiltered (file
,
4662 "mips_dump_tdep: MSYMBOL_SIZE # %s\n",
4663 XSTRING (MSYMBOL_SIZE (MSYM
)));
4664 fprintf_unfiltered (file
,
4665 "mips_dump_tdep: OP_LDFPR = used?\n");
4666 fprintf_unfiltered (file
,
4667 "mips_dump_tdep: OP_LDGPR = used?\n");
4668 fprintf_unfiltered (file
,
4669 "mips_dump_tdep: PMON_BIG_BREAKPOINT = delete?\n");
4670 fprintf_unfiltered (file
,
4671 "mips_dump_tdep: PMON_LITTLE_BREAKPOINT = delete?\n");
4672 fprintf_unfiltered (file
,
4673 "mips_dump_tdep: PRID_REGNUM = %d\n",
4675 fprintf_unfiltered (file
,
4676 "mips_dump_tdep: PRINT_EXTRA_FRAME_INFO # %s\n",
4677 XSTRING (PRINT_EXTRA_FRAME_INFO (FRAME
)));
4678 fprintf_unfiltered (file
,
4679 "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n");
4680 fprintf_unfiltered (file
,
4681 "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n");
4682 fprintf_unfiltered (file
,
4683 "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n");
4684 fprintf_unfiltered (file
,
4685 "mips_dump_tdep: PROC_FRAME_REG = function?\n");
4686 fprintf_unfiltered (file
,
4687 "mips_dump_tdep: PROC_FREG_MASK = function?\n");
4688 fprintf_unfiltered (file
,
4689 "mips_dump_tdep: PROC_FREG_OFFSET = function?\n");
4690 fprintf_unfiltered (file
,
4691 "mips_dump_tdep: PROC_HIGH_ADDR = function?\n");
4692 fprintf_unfiltered (file
,
4693 "mips_dump_tdep: PROC_LOW_ADDR = function?\n");
4694 fprintf_unfiltered (file
,
4695 "mips_dump_tdep: PROC_PC_REG = function?\n");
4696 fprintf_unfiltered (file
,
4697 "mips_dump_tdep: PROC_REG_MASK = function?\n");
4698 fprintf_unfiltered (file
,
4699 "mips_dump_tdep: PROC_REG_OFFSET = function?\n");
4700 fprintf_unfiltered (file
,
4701 "mips_dump_tdep: PROC_SYMBOL = function?\n");
4702 fprintf_unfiltered (file
,
4703 "mips_dump_tdep: PS_REGNUM = %d\n",
4705 fprintf_unfiltered (file
,
4706 "mips_dump_tdep: PUSH_FP_REGNUM = %d\n",
4708 fprintf_unfiltered (file
,
4709 "mips_dump_tdep: RA_REGNUM = %d\n",
4711 fprintf_unfiltered (file
,
4712 "mips_dump_tdep: REGISTER_CONVERT_FROM_TYPE # %s\n",
4713 XSTRING (REGISTER_CONVERT_FROM_TYPE (REGNUM
, VALTYPE
, RAW_BUFFER
)));
4714 fprintf_unfiltered (file
,
4715 "mips_dump_tdep: REGISTER_CONVERT_TO_TYPE # %s\n",
4716 XSTRING (REGISTER_CONVERT_TO_TYPE (REGNUM
, VALTYPE
, RAW_BUFFER
)));
4717 fprintf_unfiltered (file
,
4718 "mips_dump_tdep: REGISTER_NAMES = delete?\n");
4719 fprintf_unfiltered (file
,
4720 "mips_dump_tdep: ROUND_DOWN = function?\n");
4721 fprintf_unfiltered (file
,
4722 "mips_dump_tdep: ROUND_UP = function?\n");
4724 fprintf_unfiltered (file
,
4725 "mips_dump_tdep: SAVED_BYTES = %d\n",
4729 fprintf_unfiltered (file
,
4730 "mips_dump_tdep: SAVED_FP = %d\n",
4734 fprintf_unfiltered (file
,
4735 "mips_dump_tdep: SAVED_PC = %d\n",
4738 fprintf_unfiltered (file
,
4739 "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n",
4740 XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS
, ARGS
)));
4741 fprintf_unfiltered (file
,
4742 "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n");
4743 fprintf_unfiltered (file
,
4744 "mips_dump_tdep: SIGFRAME_BASE = %d\n",
4746 fprintf_unfiltered (file
,
4747 "mips_dump_tdep: SIGFRAME_FPREGSAVE_OFF = %d\n",
4748 SIGFRAME_FPREGSAVE_OFF
);
4749 fprintf_unfiltered (file
,
4750 "mips_dump_tdep: SIGFRAME_PC_OFF = %d\n",
4752 fprintf_unfiltered (file
,
4753 "mips_dump_tdep: SIGFRAME_REGSAVE_OFF = %d\n",
4754 SIGFRAME_REGSAVE_OFF
);
4755 fprintf_unfiltered (file
,
4756 "mips_dump_tdep: SIGFRAME_REG_SIZE = %d\n",
4758 fprintf_unfiltered (file
,
4759 "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n",
4760 XSTRING (SKIP_TRAMPOLINE_CODE (PC
)));
4761 fprintf_unfiltered (file
,
4762 "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n",
4763 XSTRING (SOFTWARE_SINGLE_STEP (SIG
, BP_P
)));
4764 fprintf_unfiltered (file
,
4765 "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n",
4766 SOFTWARE_SINGLE_STEP_P ());
4767 fprintf_unfiltered (file
,
4768 "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n",
4769 XSTRING (STAB_REG_TO_REGNUM (REGNUM
)));
4770 #ifdef STACK_END_ADDR
4771 fprintf_unfiltered (file
,
4772 "mips_dump_tdep: STACK_END_ADDR = %d\n",
4775 fprintf_unfiltered (file
,
4776 "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n",
4777 XSTRING (STEP_SKIPS_DELAY (PC
)));
4778 fprintf_unfiltered (file
,
4779 "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n",
4780 STEP_SKIPS_DELAY_P
);
4781 fprintf_unfiltered (file
,
4782 "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n",
4783 XSTRING (STOPPED_BY_WATCHPOINT (WS
)));
4784 fprintf_unfiltered (file
,
4785 "mips_dump_tdep: T9_REGNUM = %d\n",
4787 fprintf_unfiltered (file
,
4788 "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n");
4789 fprintf_unfiltered (file
,
4790 "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n",
4791 XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT (TYPE
,CNT
,OTHERTYPE
)));
4792 fprintf_unfiltered (file
,
4793 "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n",
4794 XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS
));
4795 fprintf_unfiltered (file
,
4796 "mips_dump_tdep: TARGET_MIPS = used?\n");
4797 fprintf_unfiltered (file
,
4798 "mips_dump_tdep: TM_PRINT_INSN_MACH # %s\n",
4799 XSTRING (TM_PRINT_INSN_MACH
));
4801 fprintf_unfiltered (file
,
4802 "mips_dump_tdep: TRACE_CLEAR # %s\n",
4803 XSTRING (TRACE_CLEAR (THREAD
, STATE
)));
4806 fprintf_unfiltered (file
,
4807 "mips_dump_tdep: TRACE_FLAVOR = %d\n",
4810 #ifdef TRACE_FLAVOR_SIZE
4811 fprintf_unfiltered (file
,
4812 "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n",
4816 fprintf_unfiltered (file
,
4817 "mips_dump_tdep: TRACE_SET # %s\n",
4818 XSTRING (TRACE_SET (X
,STATE
)));
4820 fprintf_unfiltered (file
,
4821 "mips_dump_tdep: UNMAKE_MIPS16_ADDR = function?\n");
4822 #ifdef UNUSED_REGNUM
4823 fprintf_unfiltered (file
,
4824 "mips_dump_tdep: UNUSED_REGNUM = %d\n",
4827 fprintf_unfiltered (file
,
4828 "mips_dump_tdep: V0_REGNUM = %d\n",
4830 fprintf_unfiltered (file
,
4831 "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n",
4832 (long) VM_MIN_ADDRESS
);
4834 fprintf_unfiltered (file
,
4835 "mips_dump_tdep: VX_NUM_REGS = %d (used?)\n",
4838 fprintf_unfiltered (file
,
4839 "mips_dump_tdep: ZERO_REGNUM = %d\n",
4841 fprintf_unfiltered (file
,
4842 "mips_dump_tdep: _PROC_MAGIC_ = %d\n",
4847 _initialize_mips_tdep (void)
4849 static struct cmd_list_element
*mipsfpulist
= NULL
;
4850 struct cmd_list_element
*c
;
4852 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
4853 if (!tm_print_insn
) /* Someone may have already set it */
4854 tm_print_insn
= gdb_print_insn_mips
;
4856 /* Add root prefix command for all "set mips"/"show mips" commands */
4857 add_prefix_cmd ("mips", no_class
, set_mips_command
,
4858 "Various MIPS specific commands.",
4859 &setmipscmdlist
, "set mips ", 0, &setlist
);
4861 add_prefix_cmd ("mips", no_class
, show_mips_command
,
4862 "Various MIPS specific commands.",
4863 &showmipscmdlist
, "show mips ", 0, &showlist
);
4865 /* Allow the user to override the saved register size. */
4866 add_show_from_set (add_set_enum_cmd ("saved-gpreg-size",
4869 &mips_saved_regsize_string
, "\
4870 Set size of general purpose registers saved on the stack.\n\
4871 This option can be set to one of:\n\
4872 32 - Force GDB to treat saved GP registers as 32-bit\n\
4873 64 - Force GDB to treat saved GP registers as 64-bit\n\
4874 auto - Allow GDB to use the target's default setting or autodetect the\n\
4875 saved GP register size from information contained in the executable.\n\
4880 /* Allow the user to override the argument stack size. */
4881 add_show_from_set (add_set_enum_cmd ("stack-arg-size",
4884 &mips_stack_argsize_string
, "\
4885 Set the amount of stack space reserved for each argument.\n\
4886 This option can be set to one of:\n\
4887 32 - Force GDB to allocate 32-bit chunks per argument\n\
4888 64 - Force GDB to allocate 64-bit chunks per argument\n\
4889 auto - Allow GDB to determine the correct setting from the current\n\
4890 target and executable (default)",
4894 /* Let the user turn off floating point and set the fence post for
4895 heuristic_proc_start. */
4897 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
4898 "Set use of MIPS floating-point coprocessor.",
4899 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
4900 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
4901 "Select single-precision MIPS floating-point coprocessor.",
4903 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
4904 "Select double-precision MIPS floating-point coprocessor.",
4906 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
4907 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
4908 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
4909 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
4910 "Select no MIPS floating-point coprocessor.",
4912 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
4913 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
4914 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
4915 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
4916 "Select MIPS floating-point coprocessor automatically.",
4918 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
4919 "Show current use of MIPS floating-point coprocessor target.",
4923 c
= add_set_cmd ("processor", class_support
, var_string_noescape
,
4924 (char *) &tmp_mips_processor_type
,
4925 "Set the type of MIPS processor in use.\n\
4926 Set this to be able to access processor-type-specific registers.\n\
4929 set_cmd_cfunc (c
, mips_set_processor_type_command
);
4930 c
= add_show_from_set (c
, &showlist
);
4931 set_cmd_cfunc (c
, mips_show_processor_type_command
);
4933 tmp_mips_processor_type
= xstrdup (DEFAULT_MIPS_TYPE
);
4934 mips_set_processor_type_command (xstrdup (DEFAULT_MIPS_TYPE
), 0);
4937 /* We really would like to have both "0" and "unlimited" work, but
4938 command.c doesn't deal with that. So make it a var_zinteger
4939 because the user can always use "999999" or some such for unlimited. */
4940 c
= add_set_cmd ("heuristic-fence-post", class_support
, var_zinteger
,
4941 (char *) &heuristic_fence_post
,
4943 Set the distance searched for the start of a function.\n\
4944 If you are debugging a stripped executable, GDB needs to search through the\n\
4945 program for the start of a function. This command sets the distance of the\n\
4946 search. The only need to set it is when debugging a stripped executable.",
4948 /* We need to throw away the frame cache when we set this, since it
4949 might change our ability to get backtraces. */
4950 set_cmd_sfunc (c
, reinit_frame_cache_sfunc
);
4951 add_show_from_set (c
, &showlist
);
4953 /* Allow the user to control whether the upper bits of 64-bit
4954 addresses should be zeroed. */
4955 c
= add_set_auto_boolean_cmd ("mask-address", no_class
, &mask_address_var
,
4956 "Set zeroing of upper 32 bits of 64-bit addresses.\n\
4957 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to allow GDB to determine\n\
4958 the correct value.\n",
4960 add_cmd ("mask-address", no_class
, show_mask_address
,
4961 "Show current mask-address value", &showmipscmdlist
);
4963 /* Allow the user to control the size of 32 bit registers within the
4964 raw remote packet. */
4965 add_show_from_set (add_set_cmd ("remote-mips64-transfers-32bit-regs",
4968 (char *)&mips64_transfers_32bit_regs_p
, "\
4969 Set compatibility with MIPS targets that transfers 32 and 64 bit quantities.\n\
4970 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
4971 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
4972 64 bits for others. Use \"off\" to disable compatibility mode",
4976 /* Debug this files internals. */
4977 add_show_from_set (add_set_cmd ("mips", class_maintenance
, var_zinteger
,
4978 &mips_debug
, "Set mips debugging.\n\
4979 When non-zero, mips specific debugging is enabled.", &setdebuglist
),