1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
2 Copyright 1988-1999, Free Software Foundation, Inc.
3 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
4 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
24 #include "gdb_string.h"
36 #include "arch-utils.h"
38 #include "opcode/mips.h"
43 /* All the possible MIPS ABIs. */
55 struct frame_extra_info
57 mips_extra_func_info_t proc_desc
;
61 /* Various MIPS ISA options (related to stack analysis) can be
62 overridden dynamically. Establish an enum/array for managing
65 static char size_auto
[] = "auto";
66 static char size_32
[] = "32";
67 static char size_64
[] = "64";
69 static char *size_enums
[] = {
76 /* Some MIPS boards don't support floating point while others only
77 support single-precision floating-point operations. See also
78 FP_REGISTER_DOUBLE. */
82 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
83 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
84 MIPS_FPU_NONE
/* No floating point. */
87 #ifndef MIPS_DEFAULT_FPU_TYPE
88 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
90 static int mips_fpu_type_auto
= 1;
91 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
92 #define MIPS_FPU_TYPE mips_fpu_type
94 /* Do not use "TARGET_IS_MIPS64" to test the size of floating point registers */
95 #ifndef FP_REGISTER_DOUBLE
96 #define FP_REGISTER_DOUBLE (REGISTER_VIRTUAL_SIZE(FP0_REGNUM) == 8)
100 /* MIPS specific per-architecture information */
103 /* from the elf header */
106 enum mips_abi mips_abi
;
107 enum mips_fpu_type mips_fpu_type
;
108 int mips_last_arg_regnum
;
109 int mips_last_fp_arg_regnum
;
110 int mips_default_saved_regsize
;
111 int mips_fp_register_double
;
112 int mips_regs_have_home_p
;
113 int mips_default_stack_argsize
;
118 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
119 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
123 #undef MIPS_LAST_FP_ARG_REGNUM
124 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
128 #undef MIPS_LAST_ARG_REGNUM
129 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
134 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
137 /* Return the currently configured (or set) saved register size. */
140 #undef MIPS_DEFAULT_SAVED_REGSIZE
141 #define MIPS_DEFAULT_SAVED_REGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_saved_regsize)
142 #elif !defined (MIPS_DEFAULT_SAVED_REGSIZE)
143 #define MIPS_DEFAULT_SAVED_REGSIZE MIPS_REGSIZE
146 static char *mips_saved_regsize_string
= size_auto
;
148 #define MIPS_SAVED_REGSIZE (mips_saved_regsize())
151 mips_saved_regsize ()
153 if (mips_saved_regsize_string
== size_auto
)
154 return MIPS_DEFAULT_SAVED_REGSIZE
;
155 else if (mips_saved_regsize_string
== size_64
)
157 else /* if (mips_saved_regsize_string == size_32) */
161 /* Indicate that the ABI makes use of double-precision registers
162 provided by the FPU (rather than combining pairs of registers to
163 form double-precision values). Do not use "TARGET_IS_MIPS64" to
164 determine if the ABI is using double-precision registers. See also
167 #undef FP_REGISTER_DOUBLE
168 #define FP_REGISTER_DOUBLE (gdbarch_tdep (current_gdbarch)->mips_fp_register_double)
171 /* Does the caller allocate a ``home'' for each register used in the
172 function call? The N32 ABI and MIPS_EABI do not, the others do. */
175 #undef MIPS_REGS_HAVE_HOME_P
176 #define MIPS_REGS_HAVE_HOME_P (gdbarch_tdep (current_gdbarch)->mips_regs_have_home_p)
177 #elif !defined (MIPS_REGS_HAVE_HOME_P)
178 #define MIPS_REGS_HAVE_HOME_P (!MIPS_EABI)
181 /* The amount of space reserved on the stack for registers. This is
182 different to MIPS_SAVED_REGSIZE as it determines the alignment of
183 data allocated after the registers have run out. */
186 #undef MIPS_DEFAULT_STACK_ARGSIZE
187 #define MIPS_DEFAULT_STACK_ARGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_stack_argsize)
188 #elif !defined (MIPS_DEFAULT_STACK_ARGSIZE)
189 #define MIPS_DEFAULT_STACK_ARGSIZE (MIPS_DEFAULT_SAVED_REGSIZE)
192 #define MIPS_STACK_ARGSIZE (mips_stack_argsize ())
194 static char *mips_stack_argsize_string
= size_auto
;
197 mips_stack_argsize (void)
199 if (mips_stack_argsize_string
== size_auto
)
200 return MIPS_DEFAULT_STACK_ARGSIZE
;
201 else if (mips_stack_argsize_string
== size_64
)
203 else /* if (mips_stack_argsize_string == size_32) */
209 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
212 static int mips_in_lenient_prologue
PARAMS ((CORE_ADDR
, CORE_ADDR
));
215 int gdb_print_insn_mips
PARAMS ((bfd_vma
, disassemble_info
*));
217 static void mips_print_register
PARAMS ((int, int));
219 static mips_extra_func_info_t
220 heuristic_proc_desc
PARAMS ((CORE_ADDR
, CORE_ADDR
, struct frame_info
*));
222 static CORE_ADDR heuristic_proc_start
PARAMS ((CORE_ADDR
));
224 static CORE_ADDR read_next_frame_reg
PARAMS ((struct frame_info
*, int));
226 int mips_set_processor_type
PARAMS ((char *));
228 static void mips_show_processor_type_command
PARAMS ((char *, int));
230 static void reinit_frame_cache_sfunc
PARAMS ((char *, int,
231 struct cmd_list_element
*));
233 static mips_extra_func_info_t
234 find_proc_desc
PARAMS ((CORE_ADDR pc
, struct frame_info
* next_frame
));
236 static CORE_ADDR after_prologue
PARAMS ((CORE_ADDR pc
,
237 mips_extra_func_info_t proc_desc
));
239 /* This value is the model of MIPS in use. It is derived from the value
240 of the PrID register. */
242 char *mips_processor_type
;
244 char *tmp_mips_processor_type
;
246 /* A set of original names, to be used when restoring back to generic
247 registers from a specific set. */
249 char *mips_generic_reg_names
[] = MIPS_REGISTER_NAMES
;
250 char **mips_processor_reg_names
= mips_generic_reg_names
;
252 /* The list of available "set mips " and "show mips " commands */
253 static struct cmd_list_element
*setmipscmdlist
= NULL
;
254 static struct cmd_list_element
*showmipscmdlist
= NULL
;
257 mips_register_name (i
)
260 return mips_processor_reg_names
[i
];
263 /* Names of IDT R3041 registers. */
265 char *mips_r3041_reg_names
[] = {
266 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
267 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
268 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
269 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
270 "sr", "lo", "hi", "bad", "cause","pc",
271 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
272 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
273 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
274 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
275 "fsr", "fir", "fp", "",
276 "", "", "bus", "ccfg", "", "", "", "",
277 "", "", "port", "cmp", "", "", "epc", "prid",
280 /* Names of IDT R3051 registers. */
282 char *mips_r3051_reg_names
[] = {
283 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
284 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
285 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
286 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
287 "sr", "lo", "hi", "bad", "cause","pc",
288 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
289 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
290 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
291 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
292 "fsr", "fir", "fp", "",
293 "inx", "rand", "elo", "", "ctxt", "", "", "",
294 "", "", "ehi", "", "", "", "epc", "prid",
297 /* Names of IDT R3081 registers. */
299 char *mips_r3081_reg_names
[] = {
300 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
301 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
302 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
303 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
304 "sr", "lo", "hi", "bad", "cause","pc",
305 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
306 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
307 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
308 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
309 "fsr", "fir", "fp", "",
310 "inx", "rand", "elo", "cfg", "ctxt", "", "", "",
311 "", "", "ehi", "", "", "", "epc", "prid",
314 /* Names of LSI 33k registers. */
316 char *mips_lsi33k_reg_names
[] = {
317 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
318 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
319 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
320 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
321 "epc", "hi", "lo", "sr", "cause","badvaddr",
322 "dcic", "bpc", "bda", "", "", "", "", "",
323 "", "", "", "", "", "", "", "",
324 "", "", "", "", "", "", "", "",
325 "", "", "", "", "", "", "", "",
327 "", "", "", "", "", "", "", "",
328 "", "", "", "", "", "", "", "",
334 } mips_processor_type_table
[] = {
335 { "generic", mips_generic_reg_names
},
336 { "r3041", mips_r3041_reg_names
},
337 { "r3051", mips_r3051_reg_names
},
338 { "r3071", mips_r3081_reg_names
},
339 { "r3081", mips_r3081_reg_names
},
340 { "lsi33k", mips_lsi33k_reg_names
},
348 /* Table to translate MIPS16 register field to actual register number. */
349 static int mips16_to_32_reg
[8] =
350 {16, 17, 2, 3, 4, 5, 6, 7};
352 /* Heuristic_proc_start may hunt through the text section for a long
353 time across a 2400 baud serial line. Allows the user to limit this
356 static unsigned int heuristic_fence_post
= 0;
358 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
359 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
360 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
361 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
362 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
363 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
364 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
365 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
366 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
367 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
368 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
369 #define _PROC_MAGIC_ 0x0F0F0F0F
370 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
371 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
373 struct linked_proc_info
375 struct mips_extra_func_info info
;
376 struct linked_proc_info
*next
;
378 *linked_proc_desc_table
= NULL
;
381 mips_print_extra_frame_info (fi
)
382 struct frame_info
*fi
;
386 && fi
->extra_info
->proc_desc
387 && fi
->extra_info
->proc_desc
->pdr
.framereg
< NUM_REGS
)
388 printf_filtered (" frame pointer is at %s+%s\n",
389 REGISTER_NAME (fi
->extra_info
->proc_desc
->pdr
.framereg
),
390 paddr_d (fi
->extra_info
->proc_desc
->pdr
.frameoffset
));
393 /* Convert between RAW and VIRTUAL registers. The RAW register size
394 defines the remote-gdb packet. */
396 static int mips64_transfers_32bit_regs_p
= 0;
399 mips_register_raw_size (reg_nr
)
402 if (mips64_transfers_32bit_regs_p
)
403 return REGISTER_VIRTUAL_SIZE (reg_nr
);
409 mips_register_convertible (reg_nr
)
412 if (mips64_transfers_32bit_regs_p
)
415 return (REGISTER_RAW_SIZE (reg_nr
) > REGISTER_VIRTUAL_SIZE (reg_nr
));
419 mips_register_convert_to_virtual (n
, virtual_type
, raw_buf
, virt_buf
)
421 struct type
*virtual_type
;
425 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
427 raw_buf
+ (REGISTER_RAW_SIZE (n
) - TYPE_LENGTH (virtual_type
)),
428 TYPE_LENGTH (virtual_type
));
432 TYPE_LENGTH (virtual_type
));
436 mips_register_convert_to_raw (virtual_type
, n
, virt_buf
, raw_buf
)
437 struct type
*virtual_type
;
442 memset (raw_buf
, 0, REGISTER_RAW_SIZE (n
));
443 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
444 memcpy (raw_buf
+ (REGISTER_RAW_SIZE (n
) - TYPE_LENGTH (virtual_type
)),
446 TYPE_LENGTH (virtual_type
));
450 TYPE_LENGTH (virtual_type
));
453 /* Should the upper word of 64-bit addresses be zeroed? */
454 static int mask_address_p
= 1;
456 /* Should call_function allocate stack space for a struct return? */
458 mips_use_struct_convention (gcc_p
, type
)
463 return (TYPE_LENGTH (type
) > 2 * MIPS_SAVED_REGSIZE
);
465 return 1; /* Structures are returned by ref in extra arg0 */
468 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
471 pc_is_mips16 (bfd_vma memaddr
)
473 struct minimal_symbol
*sym
;
475 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
476 if (IS_MIPS16_ADDR (memaddr
))
479 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
480 the high bit of the info field. Use this to decide if the function is
481 MIPS16 or normal MIPS. */
482 sym
= lookup_minimal_symbol_by_pc (memaddr
);
484 return MSYMBOL_IS_SPECIAL (sym
);
490 /* This returns the PC of the first inst after the prologue. If we can't
491 find the prologue, then return 0. */
494 after_prologue (pc
, proc_desc
)
496 mips_extra_func_info_t proc_desc
;
498 struct symtab_and_line sal
;
499 CORE_ADDR func_addr
, func_end
;
502 proc_desc
= find_proc_desc (pc
, NULL
);
506 /* If function is frameless, then we need to do it the hard way. I
507 strongly suspect that frameless always means prologueless... */
508 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
509 && PROC_FRAME_OFFSET (proc_desc
) == 0)
513 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
514 return 0; /* Unknown */
516 sal
= find_pc_line (func_addr
, 0);
518 if (sal
.end
< func_end
)
521 /* The line after the prologue is after the end of the function. In this
522 case, tell the caller to find the prologue the hard way. */
527 /* Decode a MIPS32 instruction that saves a register in the stack, and
528 set the appropriate bit in the general register mask or float register mask
529 to indicate which register is saved. This is a helper function
530 for mips_find_saved_regs. */
533 mips32_decode_reg_save (inst
, gen_mask
, float_mask
)
535 unsigned long *gen_mask
;
536 unsigned long *float_mask
;
540 if ((inst
& 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
541 || (inst
& 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
542 || (inst
& 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
544 /* It might be possible to use the instruction to
545 find the offset, rather than the code below which
546 is based on things being in a certain order in the
547 frame, but figuring out what the instruction's offset
548 is relative to might be a little tricky. */
549 reg
= (inst
& 0x001f0000) >> 16;
550 *gen_mask
|= (1 << reg
);
552 else if ((inst
& 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
553 || (inst
& 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
554 || (inst
& 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */
557 reg
= ((inst
& 0x001f0000) >> 16);
558 *float_mask
|= (1 << reg
);
562 /* Decode a MIPS16 instruction that saves a register in the stack, and
563 set the appropriate bit in the general register or float register mask
564 to indicate which register is saved. This is a helper function
565 for mips_find_saved_regs. */
568 mips16_decode_reg_save (inst
, gen_mask
)
570 unsigned long *gen_mask
;
572 if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
574 int reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
575 *gen_mask
|= (1 << reg
);
577 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
579 int reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
580 *gen_mask
|= (1 << reg
);
582 else if ((inst
& 0xff00) == 0x6200 /* sw $ra,n($sp) */
583 || (inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
584 *gen_mask
|= (1 << RA_REGNUM
);
588 /* Fetch and return instruction from the specified location. If the PC
589 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
592 mips_fetch_instruction (addr
)
595 char buf
[MIPS_INSTLEN
];
599 if (pc_is_mips16 (addr
))
601 instlen
= MIPS16_INSTLEN
;
602 addr
= UNMAKE_MIPS16_ADDR (addr
);
605 instlen
= MIPS_INSTLEN
;
606 status
= read_memory_nobpt (addr
, buf
, instlen
);
608 memory_error (status
, addr
);
609 return extract_unsigned_integer (buf
, instlen
);
613 /* These the fields of 32 bit mips instructions */
614 #define mips32_op(x) (x >> 25)
615 #define itype_op(x) (x >> 25)
616 #define itype_rs(x) ((x >> 21)& 0x1f)
617 #define itype_rt(x) ((x >> 16) & 0x1f)
618 #define itype_immediate(x) ( x & 0xffff)
620 #define jtype_op(x) (x >> 25)
621 #define jtype_target(x) ( x & 0x03fffff)
623 #define rtype_op(x) (x >>25)
624 #define rtype_rs(x) ((x>>21) & 0x1f)
625 #define rtype_rt(x) ((x>>16) & 0x1f)
626 #define rtype_rd(x) ((x>>11) & 0x1f)
627 #define rtype_shamt(x) ((x>>6) & 0x1f)
628 #define rtype_funct(x) (x & 0x3f )
631 mips32_relative_offset (unsigned long inst
)
634 x
= itype_immediate (inst
);
635 if (x
& 0x8000) /* sign bit set */
637 x
|= 0xffff0000; /* sign extension */
643 /* Determine whate to set a single step breakpoint while considering
646 mips32_next_pc (CORE_ADDR pc
)
650 inst
= mips_fetch_instruction (pc
);
651 if ((inst
& 0xe0000000) != 0) /* Not a special, junp or branch instruction */
653 if ((inst
>> 27) == 5) /* BEQL BNEZ BLEZL BGTZE , bits 0101xx */
655 op
= ((inst
>> 25) & 0x03);
659 goto equal_branch
; /* BEQL */
661 goto neq_branch
; /* BNEZ */
663 goto less_branch
; /* BLEZ */
665 goto greater_branch
; /* BGTZ */
671 pc
+= 4; /* Not a branch, next instruction is easy */
674 { /* This gets way messy */
676 /* Further subdivide into SPECIAL, REGIMM and other */
677 switch (op
= ((inst
>> 26) & 0x07)) /* extract bits 28,27,26 */
679 case 0: /* SPECIAL */
680 op
= rtype_funct (inst
);
685 pc
= read_register (rtype_rs (inst
)); /* Set PC to that address */
691 break; /* end special */
694 op
= jtype_op (inst
); /* branch condition */
695 switch (jtype_op (inst
))
699 case 16: /* BLTZALL */
700 case 18: /* BLTZALL */
702 if (read_register (itype_rs (inst
)) < 0)
703 pc
+= mips32_relative_offset (inst
) + 4;
705 pc
+= 8; /* after the delay slot */
709 case 17: /* BGEZAL */
710 case 19: /* BGEZALL */
711 greater_equal_branch
:
712 if (read_register (itype_rs (inst
)) >= 0)
713 pc
+= mips32_relative_offset (inst
) + 4;
715 pc
+= 8; /* after the delay slot */
717 /* All of the other intructions in the REGIMM catagory */
722 break; /* end REGIMM */
727 reg
= jtype_target (inst
) << 2;
728 pc
= reg
+ ((pc
+ 4) & 0xf0000000);
729 /* Whats this mysterious 0xf000000 adjustment ??? */
732 /* FIXME case JALX : */
735 reg
= jtype_target (inst
) << 2;
736 pc
= reg
+ ((pc
+ 4) & 0xf0000000) + 1; /* yes, +1 */
737 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
739 break; /* The new PC will be alternate mode */
740 case 4: /* BEQ , BEQL */
742 if (read_register (itype_rs (inst
)) ==
743 read_register (itype_rt (inst
)))
744 pc
+= mips32_relative_offset (inst
) + 4;
748 case 5: /* BNE , BNEL */
750 if (read_register (itype_rs (inst
)) !=
751 read_register (itype_rs (inst
)))
752 pc
+= mips32_relative_offset (inst
) + 4;
756 case 6: /* BLEZ , BLEZL */
758 if (read_register (itype_rs (inst
) <= 0))
759 pc
+= mips32_relative_offset (inst
) + 4;
764 greater_branch
: /* BGTZ BGTZL */
765 if (read_register (itype_rs (inst
) > 0))
766 pc
+= mips32_relative_offset (inst
) + 4;
775 } /* mips32_next_pc */
777 /* Decoding the next place to set a breakpoint is irregular for the
778 mips 16 variant, but fortunatly, there fewer instructions. We have to cope
779 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
780 We dont want to set a single step instruction on the extend instruction
784 /* Lots of mips16 instruction formats */
785 /* Predicting jumps requires itype,ritype,i8type
786 and their extensions extItype,extritype,extI8type
788 enum mips16_inst_fmts
790 itype
, /* 0 immediate 5,10 */
791 ritype
, /* 1 5,3,8 */
792 rrtype
, /* 2 5,3,3,5 */
793 rritype
, /* 3 5,3,3,5 */
794 rrrtype
, /* 4 5,3,3,3,2 */
795 rriatype
, /* 5 5,3,3,1,4 */
796 shifttype
, /* 6 5,3,3,3,2 */
797 i8type
, /* 7 5,3,8 */
798 i8movtype
, /* 8 5,3,3,5 */
799 i8mov32rtype
, /* 9 5,3,5,3 */
800 i64type
, /* 10 5,3,8 */
801 ri64type
, /* 11 5,3,3,5 */
802 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
803 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
804 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
805 extRRItype
, /* 15 5,5,5,5,3,3,5 */
806 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
807 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
808 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
809 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
810 extRi64type
, /* 20 5,6,5,5,3,3,5 */
811 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
813 /* I am heaping all the fields of the formats into one structure and then,
814 only the fields which are involved in instruction extension */
818 enum mips16_inst_fmts fmt
;
819 unsigned long offset
;
820 unsigned int regx
; /* Function in i8 type */
827 print_unpack (char *comment
,
828 struct upk_mips16
*u
)
830 printf ("%s %04x ,f(%d) off(%s) (x(%x) y(%x)\n",
831 comment
, u
->inst
, u
->fmt
, paddr (u
->offset
), u
->regx
, u
->regy
);
834 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same
835 format for the bits which make up the immediatate extension.
838 extended_offset (unsigned long extension
)
841 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
843 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
845 value
|= extension
& 0x01f; /* extract 4:0 */
849 /* Only call this function if you know that this is an extendable
850 instruction, It wont malfunction, but why make excess remote memory references?
851 If the immediate operands get sign extended or somthing, do it after
852 the extension is performed.
854 /* FIXME: Every one of these cases needs to worry about sign extension
855 when the offset is to be used in relative addressing */
858 static unsigned short
859 fetch_mips_16 (CORE_ADDR pc
)
862 pc
&= 0xfffffffe; /* clear the low order bit */
863 target_read_memory (pc
, buf
, 2);
864 return extract_unsigned_integer (buf
, 2);
868 unpack_mips16 (CORE_ADDR pc
,
869 struct upk_mips16
*upk
)
872 unsigned long extension
;
874 extpc
= (pc
- 4) & ~0x01; /* Extensions are 32 bit instructions */
875 /* Decrement to previous address and loose the 16bit mode flag */
876 /* return if the instruction was extendable, but not actually extended */
877 extended
= ((mips32_op (extension
) == 30) ? 1 : 0);
880 extension
= mips_fetch_instruction (extpc
);
889 value
= extended_offset (extension
);
890 value
= value
<< 11; /* rom for the original value */
891 value
|= upk
->inst
& 0x7ff; /* eleven bits from instruction */
895 value
= upk
->inst
& 0x7ff;
896 /* FIXME : Consider sign extension */
903 { /* A register identifier and an offset */
904 /* Most of the fields are the same as I type but the
905 immediate value is of a different length */
909 value
= extended_offset (extension
);
910 value
= value
<< 8; /* from the original instruction */
911 value
|= upk
->inst
& 0xff; /* eleven bits from instruction */
912 upk
->regx
= (extension
>> 8) & 0x07; /* or i8 funct */
913 if (value
& 0x4000) /* test the sign bit , bit 26 */
915 value
&= ~0x3fff; /* remove the sign bit */
921 value
= upk
->inst
& 0xff; /* 8 bits */
922 upk
->regx
= (upk
->inst
>> 8) & 0x07; /* or i8 funct */
923 /* FIXME: Do sign extension , this format needs it */
924 if (value
& 0x80) /* THIS CONFUSES ME */
926 value
&= 0xef; /* remove the sign bit */
937 unsigned short nexthalf
;
938 value
= ((upk
->inst
& 0x1f) << 5) | ((upk
->inst
>> 5) & 0x1f);
940 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
946 printf_filtered ("Decoding unimplemented instruction format type\n");
949 /* print_unpack("UPK",upk) ; */
953 #define mips16_op(x) (x >> 11)
955 /* This is a map of the opcodes which ae known to perform branches */
956 static unsigned char map16
[32] =
957 {0, 0, 1, 1, 1, 1, 0, 0,
958 0, 0, 0, 0, 1, 0, 0, 0,
959 0, 0, 0, 0, 0, 0, 0, 0,
960 0, 0, 0, 0, 0, 1, 1, 0
964 add_offset_16 (CORE_ADDR pc
, int offset
)
966 return ((offset
<< 2) | ((pc
+ 2) & (0xf0000000)));
972 static struct upk_mips16 upk
;
975 mips16_next_pc (CORE_ADDR pc
)
979 /* inst = mips_fetch_instruction(pc) ; - This doesnt always work */
980 inst
= fetch_mips_16 (pc
);
982 op
= mips16_op (upk
.inst
);
990 unpack_mips16 (pc
, &upk
);
999 pc
+= (offset
<< 1) + 2;
1002 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1004 unpack_mips16 (pc
, &upk
);
1005 pc
= add_offset_16 (pc
, upk
.offset
);
1006 if ((upk
.inst
>> 10) & 0x01) /* Exchange mode */
1007 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1013 unpack_mips16 (pc
, &upk
);
1014 reg
= read_register (upk
.regx
);
1016 pc
+= (upk
.offset
<< 1) + 2;
1022 unpack_mips16 (pc
, &upk
);
1023 reg
= read_register (upk
.regx
);
1025 pc
+= (upk
.offset
<< 1) + 2;
1029 case 12: /* I8 Formats btez btnez */
1031 unpack_mips16 (pc
, &upk
);
1032 /* upk.regx contains the opcode */
1033 reg
= read_register (24); /* Test register is 24 */
1034 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1035 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1036 /* pc = add_offset_16(pc,upk.offset) ; */
1037 pc
+= (upk
.offset
<< 1) + 2;
1041 case 29: /* RR Formats JR, JALR, JALR-RA */
1043 op
= upk
.inst
& 0x1f;
1046 upk
.regx
= (upk
.inst
>> 8) & 0x07;
1047 upk
.regy
= (upk
.inst
>> 5) & 0x07;
1055 break; /* Function return instruction */
1061 break; /* BOGUS Guess */
1063 pc
= read_register (reg
);
1068 case 30: /* This is an extend instruction */
1069 pc
+= 4; /* Dont be setting breakpints on the second half */
1072 printf ("Filtered - next PC probably incorrrect due to jump inst\n");
1078 pc
+= 2; /* just a good old instruction */
1079 /* See if we CAN actually break on the next instruction */
1080 /* printf("NXTm16PC %08x\n",(unsigned long)pc) ; */
1082 } /* mips16_next_pc */
1084 /* The mips_next_pc function supports single_tep when the remote target monitor or
1085 stub is not developed enough to so a single_step.
1086 It works by decoding the current instruction and predicting where a branch
1087 will go. This isnt hard because all the data is available.
1088 The MIPS32 and MIPS16 variants are quite different
1091 mips_next_pc (CORE_ADDR pc
)
1094 /* inst = mips_fetch_instruction(pc) ; */
1095 /* if (pc_is_mips16) <----- This is failing */
1097 return mips16_next_pc (pc
);
1099 return mips32_next_pc (pc
);
1100 } /* mips_next_pc */
1102 /* Guaranteed to set fci->saved_regs to some values (it never leaves it
1106 mips_find_saved_regs (fci
)
1107 struct frame_info
*fci
;
1110 CORE_ADDR reg_position
;
1111 /* r0 bit means kernel trap */
1113 /* What registers have been saved? Bitmasks. */
1114 unsigned long gen_mask
, float_mask
;
1115 mips_extra_func_info_t proc_desc
;
1118 frame_saved_regs_zalloc (fci
);
1120 /* If it is the frame for sigtramp, the saved registers are located
1121 in a sigcontext structure somewhere on the stack.
1122 If the stack layout for sigtramp changes we might have to change these
1123 constants and the companion fixup_sigtramp in mdebugread.c */
1124 #ifndef SIGFRAME_BASE
1125 /* To satisfy alignment restrictions, sigcontext is located 4 bytes
1126 above the sigtramp frame. */
1127 #define SIGFRAME_BASE MIPS_REGSIZE
1128 /* FIXME! Are these correct?? */
1129 #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * MIPS_REGSIZE)
1130 #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * MIPS_REGSIZE)
1131 #define SIGFRAME_FPREGSAVE_OFF \
1132 (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * MIPS_REGSIZE + 3 * MIPS_REGSIZE)
1134 #ifndef SIGFRAME_REG_SIZE
1135 /* FIXME! Is this correct?? */
1136 #define SIGFRAME_REG_SIZE MIPS_REGSIZE
1138 if (fci
->signal_handler_caller
)
1140 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1142 reg_position
= fci
->frame
+ SIGFRAME_REGSAVE_OFF
1143 + ireg
* SIGFRAME_REG_SIZE
;
1144 fci
->saved_regs
[ireg
] = reg_position
;
1146 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1148 reg_position
= fci
->frame
+ SIGFRAME_FPREGSAVE_OFF
1149 + ireg
* SIGFRAME_REG_SIZE
;
1150 fci
->saved_regs
[FP0_REGNUM
+ ireg
] = reg_position
;
1152 fci
->saved_regs
[PC_REGNUM
] = fci
->frame
+ SIGFRAME_PC_OFF
;
1156 proc_desc
= fci
->extra_info
->proc_desc
;
1157 if (proc_desc
== NULL
)
1158 /* I'm not sure how/whether this can happen. Normally when we can't
1159 find a proc_desc, we "synthesize" one using heuristic_proc_desc
1160 and set the saved_regs right away. */
1163 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1164 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
1165 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
1167 if ( /* In any frame other than the innermost or a frame interrupted by
1168 a signal, we assume that all registers have been saved.
1169 This assumes that all register saves in a function happen before
1170 the first function call. */
1171 (fci
->next
== NULL
|| fci
->next
->signal_handler_caller
)
1173 /* In a dummy frame we know exactly where things are saved. */
1174 && !PROC_DESC_IS_DUMMY (proc_desc
)
1176 /* Don't bother unless we are inside a function prologue. Outside the
1177 prologue, we know where everything is. */
1179 && in_prologue (fci
->pc
, PROC_LOW_ADDR (proc_desc
))
1181 /* Not sure exactly what kernel_trap means, but if it means
1182 the kernel saves the registers without a prologue doing it,
1183 we better not examine the prologue to see whether registers
1184 have been saved yet. */
1187 /* We need to figure out whether the registers that the proc_desc
1188 claims are saved have been saved yet. */
1192 /* Bitmasks; set if we have found a save for the register. */
1193 unsigned long gen_save_found
= 0;
1194 unsigned long float_save_found
= 0;
1197 /* If the address is odd, assume this is MIPS16 code. */
1198 addr
= PROC_LOW_ADDR (proc_desc
);
1199 instlen
= pc_is_mips16 (addr
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1201 /* Scan through this function's instructions preceding the current
1202 PC, and look for those that save registers. */
1203 while (addr
< fci
->pc
)
1205 inst
= mips_fetch_instruction (addr
);
1206 if (pc_is_mips16 (addr
))
1207 mips16_decode_reg_save (inst
, &gen_save_found
);
1209 mips32_decode_reg_save (inst
, &gen_save_found
, &float_save_found
);
1212 gen_mask
= gen_save_found
;
1213 float_mask
= float_save_found
;
1216 /* Fill in the offsets for the registers which gen_mask says
1218 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
1219 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
1220 if (gen_mask
& 0x80000000)
1222 fci
->saved_regs
[ireg
] = reg_position
;
1223 reg_position
-= MIPS_SAVED_REGSIZE
;
1226 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse order
1227 of that normally used by gcc. Therefore, we have to fetch the first
1228 instruction of the function, and if it's an entry instruction that
1229 saves $s0 or $s1, correct their saved addresses. */
1230 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
1232 inst
= mips_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
1233 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1236 int sreg_count
= (inst
>> 6) & 3;
1238 /* Check if the ra register was pushed on the stack. */
1239 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
1241 reg_position
-= MIPS_SAVED_REGSIZE
;
1243 /* Check if the s0 and s1 registers were pushed on the stack. */
1244 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1246 fci
->saved_regs
[reg
] = reg_position
;
1247 reg_position
-= MIPS_SAVED_REGSIZE
;
1252 /* Fill in the offsets for the registers which float_mask says
1254 reg_position
= fci
->frame
+ PROC_FREG_OFFSET (proc_desc
);
1256 /* The freg_offset points to where the first *double* register
1257 is saved. So skip to the high-order word. */
1258 if (!GDB_TARGET_IS_MIPS64
)
1259 reg_position
+= MIPS_SAVED_REGSIZE
;
1261 /* Fill in the offsets for the float registers which float_mask says
1263 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
1264 if (float_mask
& 0x80000000)
1266 fci
->saved_regs
[FP0_REGNUM
+ ireg
] = reg_position
;
1267 reg_position
-= MIPS_SAVED_REGSIZE
;
1270 fci
->saved_regs
[PC_REGNUM
] = fci
->saved_regs
[RA_REGNUM
];
1274 read_next_frame_reg (fi
, regno
)
1275 struct frame_info
*fi
;
1278 for (; fi
; fi
= fi
->next
)
1280 /* We have to get the saved sp from the sigcontext
1281 if it is a signal handler frame. */
1282 if (regno
== SP_REGNUM
&& !fi
->signal_handler_caller
)
1286 if (fi
->saved_regs
== NULL
)
1287 mips_find_saved_regs (fi
);
1288 if (fi
->saved_regs
[regno
])
1289 return read_memory_integer (ADDR_BITS_REMOVE (fi
->saved_regs
[regno
]), MIPS_SAVED_REGSIZE
);
1292 return read_register (regno
);
1295 /* mips_addr_bits_remove - remove useless address bits */
1298 mips_addr_bits_remove (addr
)
1301 #if GDB_TARGET_IS_MIPS64
1302 if (mask_address_p
&& (addr
>> 32 == (CORE_ADDR
) 0xffffffff))
1304 /* This hack is a work-around for existing boards using PMON,
1305 the simulator, and any other 64-bit targets that doesn't have
1306 true 64-bit addressing. On these targets, the upper 32 bits
1307 of addresses are ignored by the hardware. Thus, the PC or SP
1308 are likely to have been sign extended to all 1s by instruction
1309 sequences that load 32-bit addresses. For example, a typical
1310 piece of code that loads an address is this:
1311 lui $r2, <upper 16 bits>
1312 ori $r2, <lower 16 bits>
1313 But the lui sign-extends the value such that the upper 32 bits
1314 may be all 1s. The workaround is simply to mask off these bits.
1315 In the future, gcc may be changed to support true 64-bit
1316 addressing, and this masking will have to be disabled. */
1317 addr
&= (CORE_ADDR
) 0xffffffff;
1320 /* Even when GDB is configured for some 32-bit targets (e.g. mips-elf),
1321 BFD is configured to handle 64-bit targets, so CORE_ADDR is 64 bits.
1322 So we still have to mask off useless bits from addresses. */
1323 addr
&= (CORE_ADDR
) 0xffffffff;
1330 mips_init_frame_pc_first (fromleaf
, prev
)
1332 struct frame_info
*prev
;
1336 pc
= ((fromleaf
) ? SAVED_PC_AFTER_CALL (prev
->next
) :
1337 prev
->next
? FRAME_SAVED_PC (prev
->next
) : read_pc ());
1338 tmp
= mips_skip_stub (pc
);
1339 prev
->pc
= tmp
? tmp
: pc
;
1344 mips_frame_saved_pc (frame
)
1345 struct frame_info
*frame
;
1348 mips_extra_func_info_t proc_desc
= frame
->extra_info
->proc_desc
;
1349 /* We have to get the saved pc from the sigcontext
1350 if it is a signal handler frame. */
1351 int pcreg
= frame
->signal_handler_caller
? PC_REGNUM
1352 : (proc_desc
? PROC_PC_REG (proc_desc
) : RA_REGNUM
);
1354 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
1355 saved_pc
= read_memory_integer (frame
->frame
- MIPS_SAVED_REGSIZE
, MIPS_SAVED_REGSIZE
);
1357 saved_pc
= read_next_frame_reg (frame
, pcreg
);
1359 return ADDR_BITS_REMOVE (saved_pc
);
1362 static struct mips_extra_func_info temp_proc_desc
;
1363 static CORE_ADDR temp_saved_regs
[NUM_REGS
];
1365 /* Set a register's saved stack address in temp_saved_regs. If an address
1366 has already been set for this register, do nothing; this way we will
1367 only recognize the first save of a given register in a function prologue.
1368 This is a helper function for mips{16,32}_heuristic_proc_desc. */
1371 set_reg_offset (regno
, offset
)
1375 if (temp_saved_regs
[regno
] == 0)
1376 temp_saved_regs
[regno
] = offset
;
1380 /* Test whether the PC points to the return instruction at the
1381 end of a function. */
1384 mips_about_to_return (pc
)
1387 if (pc_is_mips16 (pc
))
1388 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
1389 generates a "jr $ra"; other times it generates code to load
1390 the return address from the stack to an accessible register (such
1391 as $a3), then a "jr" using that register. This second case
1392 is almost impossible to distinguish from an indirect jump
1393 used for switch statements, so we don't even try. */
1394 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
1396 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
1400 /* This fencepost looks highly suspicious to me. Removing it also
1401 seems suspicious as it could affect remote debugging across serial
1405 heuristic_proc_start (pc
)
1413 pc
= ADDR_BITS_REMOVE (pc
);
1415 fence
= start_pc
- heuristic_fence_post
;
1419 if (heuristic_fence_post
== UINT_MAX
1420 || fence
< VM_MIN_ADDRESS
)
1421 fence
= VM_MIN_ADDRESS
;
1423 instlen
= pc_is_mips16 (pc
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1425 /* search back for previous return */
1426 for (start_pc
-= instlen
;; start_pc
-= instlen
)
1427 if (start_pc
< fence
)
1429 /* It's not clear to me why we reach this point when
1430 stop_soon_quietly, but with this test, at least we
1431 don't print out warnings for every child forked (eg, on
1432 decstation). 22apr93 rich@cygnus.com. */
1433 if (!stop_soon_quietly
)
1435 static int blurb_printed
= 0;
1437 warning ("Warning: GDB can't find the start of the function at 0x%s.",
1442 /* This actually happens frequently in embedded
1443 development, when you first connect to a board
1444 and your stack pointer and pc are nowhere in
1445 particular. This message needs to give people
1446 in that situation enough information to
1447 determine that it's no big deal. */
1448 printf_filtered ("\n\
1449 GDB is unable to find the start of the function at 0x%s\n\
1450 and thus can't determine the size of that function's stack frame.\n\
1451 This means that GDB may be unable to access that stack frame, or\n\
1452 the frames below it.\n\
1453 This problem is most likely caused by an invalid program counter or\n\
1455 However, if you think GDB should simply search farther back\n\
1456 from 0x%s for code which looks like the beginning of a\n\
1457 function, you can increase the range of the search using the `set\n\
1458 heuristic-fence-post' command.\n",
1459 paddr_nz (pc
), paddr_nz (pc
));
1466 else if (pc_is_mips16 (start_pc
))
1468 unsigned short inst
;
1470 /* On MIPS16, any one of the following is likely to be the
1471 start of a function:
1475 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
1476 inst
= mips_fetch_instruction (start_pc
);
1477 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1478 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
1479 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
1480 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
1482 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1483 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1488 else if (mips_about_to_return (start_pc
))
1490 start_pc
+= 2 * MIPS_INSTLEN
; /* skip return, and its delay slot */
1495 /* skip nops (usually 1) 0 - is this */
1496 while (start_pc
< pc
&& read_memory_integer (start_pc
, MIPS_INSTLEN
) == 0)
1497 start_pc
+= MIPS_INSTLEN
;
1502 /* Fetch the immediate value from a MIPS16 instruction.
1503 If the previous instruction was an EXTEND, use it to extend
1504 the upper bits of the immediate value. This is a helper function
1505 for mips16_heuristic_proc_desc. */
1508 mips16_get_imm (prev_inst
, inst
, nbits
, scale
, is_signed
)
1509 unsigned short prev_inst
; /* previous instruction */
1510 unsigned short inst
; /* current instruction */
1511 int nbits
; /* number of bits in imm field */
1512 int scale
; /* scale factor to be applied to imm */
1513 int is_signed
; /* is the imm field signed? */
1517 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1519 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1520 if (offset
& 0x8000) /* check for negative extend */
1521 offset
= 0 - (0x10000 - (offset
& 0xffff));
1522 return offset
| (inst
& 0x1f);
1526 int max_imm
= 1 << nbits
;
1527 int mask
= max_imm
- 1;
1528 int sign_bit
= max_imm
>> 1;
1530 offset
= inst
& mask
;
1531 if (is_signed
&& (offset
& sign_bit
))
1532 offset
= 0 - (max_imm
- offset
);
1533 return offset
* scale
;
1538 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
1539 stream from start_pc to limit_pc. */
1542 mips16_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
)
1543 CORE_ADDR start_pc
, limit_pc
;
1544 struct frame_info
*next_frame
;
1548 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1549 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1550 unsigned inst
= 0; /* current instruction */
1551 unsigned entry_inst
= 0; /* the entry instruction */
1554 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0; /* size of stack frame */
1555 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
1557 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS16_INSTLEN
)
1559 /* Save the previous instruction. If it's an EXTEND, we'll extract
1560 the immediate offset extension from it in mips16_get_imm. */
1563 /* Fetch and decode the instruction. */
1564 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
1565 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1566 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1568 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1569 if (offset
< 0) /* negative stack adjustment? */
1570 PROC_FRAME_OFFSET (&temp_proc_desc
) -= offset
;
1572 /* Exit loop if a positive stack adjustment is found, which
1573 usually means that the stack cleanup code in the function
1574 epilogue is reached. */
1577 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1579 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1580 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1581 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
1582 set_reg_offset (reg
, sp
+ offset
);
1584 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1586 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1587 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1588 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
1589 set_reg_offset (reg
, sp
+ offset
);
1591 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1593 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1594 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
1595 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1597 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1599 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1600 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
1601 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1603 else if (inst
== 0x673d) /* move $s1, $sp */
1606 PROC_FRAME_REG (&temp_proc_desc
) = 17;
1608 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1610 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1611 frame_addr
= sp
+ offset
;
1612 PROC_FRAME_REG (&temp_proc_desc
) = 17;
1613 PROC_FRAME_ADJUST (&temp_proc_desc
) = offset
;
1615 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1617 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1618 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1619 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1620 set_reg_offset (reg
, frame_addr
+ offset
);
1622 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1624 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1625 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1626 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1627 set_reg_offset (reg
, frame_addr
+ offset
);
1629 else if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1630 entry_inst
= inst
; /* save for later processing */
1631 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1632 cur_pc
+= MIPS16_INSTLEN
; /* 32-bit instruction */
1635 /* The entry instruction is typically the first instruction in a function,
1636 and it stores registers at offsets relative to the value of the old SP
1637 (before the prologue). But the value of the sp parameter to this
1638 function is the new SP (after the prologue has been executed). So we
1639 can't calculate those offsets until we've seen the entire prologue,
1640 and can calculate what the old SP must have been. */
1641 if (entry_inst
!= 0)
1643 int areg_count
= (entry_inst
>> 8) & 7;
1644 int sreg_count
= (entry_inst
>> 6) & 3;
1646 /* The entry instruction always subtracts 32 from the SP. */
1647 PROC_FRAME_OFFSET (&temp_proc_desc
) += 32;
1649 /* Now we can calculate what the SP must have been at the
1650 start of the function prologue. */
1651 sp
+= PROC_FRAME_OFFSET (&temp_proc_desc
);
1653 /* Check if a0-a3 were saved in the caller's argument save area. */
1654 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
1656 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1657 set_reg_offset (reg
, sp
+ offset
);
1658 offset
+= MIPS_SAVED_REGSIZE
;
1661 /* Check if the ra register was pushed on the stack. */
1663 if (entry_inst
& 0x20)
1665 PROC_REG_MASK (&temp_proc_desc
) |= 1 << RA_REGNUM
;
1666 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1667 offset
-= MIPS_SAVED_REGSIZE
;
1670 /* Check if the s0 and s1 registers were pushed on the stack. */
1671 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1673 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1674 set_reg_offset (reg
, sp
+ offset
);
1675 offset
-= MIPS_SAVED_REGSIZE
;
1681 mips32_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
)
1682 CORE_ADDR start_pc
, limit_pc
;
1683 struct frame_info
*next_frame
;
1687 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
1689 memset (temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
1690 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0;
1691 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
1692 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSTLEN
)
1694 unsigned long inst
, high_word
, low_word
;
1697 /* Fetch the instruction. */
1698 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
1700 /* Save some code by pre-extracting some useful fields. */
1701 high_word
= (inst
>> 16) & 0xffff;
1702 low_word
= inst
& 0xffff;
1703 reg
= high_word
& 0x1f;
1705 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
1706 || high_word
== 0x23bd /* addi $sp,$sp,-i */
1707 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
1709 if (low_word
& 0x8000) /* negative stack adjustment? */
1710 PROC_FRAME_OFFSET (&temp_proc_desc
) += 0x10000 - low_word
;
1712 /* Exit loop if a positive stack adjustment is found, which
1713 usually means that the stack cleanup code in the function
1714 epilogue is reached. */
1717 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
1719 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1720 set_reg_offset (reg
, sp
+ low_word
);
1722 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
1724 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra,
1725 but the register size used is only 32 bits. Make the address
1726 for the saved register point to the lower 32 bits. */
1727 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1728 set_reg_offset (reg
, sp
+ low_word
+ 8 - MIPS_REGSIZE
);
1730 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
1732 /* Old gcc frame, r30 is virtual frame pointer. */
1733 if ((long) low_word
!= PROC_FRAME_OFFSET (&temp_proc_desc
))
1734 frame_addr
= sp
+ low_word
;
1735 else if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
1737 unsigned alloca_adjust
;
1738 PROC_FRAME_REG (&temp_proc_desc
) = 30;
1739 frame_addr
= read_next_frame_reg (next_frame
, 30);
1740 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
1741 if (alloca_adjust
> 0)
1743 /* FP > SP + frame_size. This may be because
1744 * of an alloca or somethings similar.
1745 * Fix sp to "pre-alloca" value, and try again.
1747 sp
+= alloca_adjust
;
1752 /* move $30,$sp. With different versions of gas this will be either
1753 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
1754 Accept any one of these. */
1755 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
1757 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
1758 if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
1760 unsigned alloca_adjust
;
1761 PROC_FRAME_REG (&temp_proc_desc
) = 30;
1762 frame_addr
= read_next_frame_reg (next_frame
, 30);
1763 alloca_adjust
= (unsigned) (frame_addr
- sp
);
1764 if (alloca_adjust
> 0)
1766 /* FP > SP + frame_size. This may be because
1767 * of an alloca or somethings similar.
1768 * Fix sp to "pre-alloca" value, and try again.
1770 sp
+= alloca_adjust
;
1775 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
1777 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1778 set_reg_offset (reg
, frame_addr
+ low_word
);
1783 static mips_extra_func_info_t
1784 heuristic_proc_desc (start_pc
, limit_pc
, next_frame
)
1785 CORE_ADDR start_pc
, limit_pc
;
1786 struct frame_info
*next_frame
;
1788 CORE_ADDR sp
= read_next_frame_reg (next_frame
, SP_REGNUM
);
1792 memset (&temp_proc_desc
, '\0', sizeof (temp_proc_desc
));
1793 memset (&temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
1794 PROC_LOW_ADDR (&temp_proc_desc
) = start_pc
;
1795 PROC_FRAME_REG (&temp_proc_desc
) = SP_REGNUM
;
1796 PROC_PC_REG (&temp_proc_desc
) = RA_REGNUM
;
1798 if (start_pc
+ 200 < limit_pc
)
1799 limit_pc
= start_pc
+ 200;
1800 if (pc_is_mips16 (start_pc
))
1801 mips16_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
1803 mips32_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
1804 return &temp_proc_desc
;
1807 static mips_extra_func_info_t
1808 non_heuristic_proc_desc (pc
, addrptr
)
1812 CORE_ADDR startaddr
;
1813 mips_extra_func_info_t proc_desc
;
1814 struct block
*b
= block_for_pc (pc
);
1817 find_pc_partial_function (pc
, NULL
, &startaddr
, NULL
);
1819 *addrptr
= startaddr
;
1820 if (b
== NULL
|| PC_IN_CALL_DUMMY (pc
, 0, 0))
1824 if (startaddr
> BLOCK_START (b
))
1825 /* This is the "pathological" case referred to in a comment in
1826 print_frame_info. It might be better to move this check into
1830 sym
= lookup_symbol (MIPS_EFI_SYMBOL_NAME
, b
, LABEL_NAMESPACE
, 0, NULL
);
1833 /* If we never found a PDR for this function in symbol reading, then
1834 examine prologues to find the information. */
1837 proc_desc
= (mips_extra_func_info_t
) SYMBOL_VALUE (sym
);
1838 if (PROC_FRAME_REG (proc_desc
) == -1)
1848 static mips_extra_func_info_t
1849 find_proc_desc (pc
, next_frame
)
1851 struct frame_info
*next_frame
;
1853 mips_extra_func_info_t proc_desc
;
1854 CORE_ADDR startaddr
;
1856 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
1860 /* IF this is the topmost frame AND
1861 * (this proc does not have debugging information OR
1862 * the PC is in the procedure prologue)
1863 * THEN create a "heuristic" proc_desc (by analyzing
1864 * the actual code) to replace the "official" proc_desc.
1866 if (next_frame
== NULL
)
1868 struct symtab_and_line val
;
1869 struct symbol
*proc_symbol
=
1870 PROC_DESC_IS_DUMMY (proc_desc
) ? 0 : PROC_SYMBOL (proc_desc
);
1874 val
= find_pc_line (BLOCK_START
1875 (SYMBOL_BLOCK_VALUE (proc_symbol
)),
1877 val
.pc
= val
.end
? val
.end
: pc
;
1879 if (!proc_symbol
|| pc
< val
.pc
)
1881 mips_extra_func_info_t found_heuristic
=
1882 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc
),
1884 if (found_heuristic
)
1885 proc_desc
= found_heuristic
;
1891 /* Is linked_proc_desc_table really necessary? It only seems to be used
1892 by procedure call dummys. However, the procedures being called ought
1893 to have their own proc_descs, and even if they don't,
1894 heuristic_proc_desc knows how to create them! */
1896 register struct linked_proc_info
*link
;
1898 for (link
= linked_proc_desc_table
; link
; link
= link
->next
)
1899 if (PROC_LOW_ADDR (&link
->info
) <= pc
1900 && PROC_HIGH_ADDR (&link
->info
) > pc
)
1904 startaddr
= heuristic_proc_start (pc
);
1907 heuristic_proc_desc (startaddr
, pc
, next_frame
);
1913 get_frame_pointer (frame
, proc_desc
)
1914 struct frame_info
*frame
;
1915 mips_extra_func_info_t proc_desc
;
1917 return ADDR_BITS_REMOVE (
1918 read_next_frame_reg (frame
, PROC_FRAME_REG (proc_desc
)) +
1919 PROC_FRAME_OFFSET (proc_desc
) - PROC_FRAME_ADJUST (proc_desc
));
1922 mips_extra_func_info_t cached_proc_desc
;
1925 mips_frame_chain (frame
)
1926 struct frame_info
*frame
;
1928 mips_extra_func_info_t proc_desc
;
1930 CORE_ADDR saved_pc
= FRAME_SAVED_PC (frame
);
1932 if (saved_pc
== 0 || inside_entry_file (saved_pc
))
1935 /* Check if the PC is inside a call stub. If it is, fetch the
1936 PC of the caller of that stub. */
1937 if ((tmp
= mips_skip_stub (saved_pc
)) != 0)
1940 /* Look up the procedure descriptor for this PC. */
1941 proc_desc
= find_proc_desc (saved_pc
, frame
);
1945 cached_proc_desc
= proc_desc
;
1947 /* If no frame pointer and frame size is zero, we must be at end
1948 of stack (or otherwise hosed). If we don't check frame size,
1949 we loop forever if we see a zero size frame. */
1950 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
1951 && PROC_FRAME_OFFSET (proc_desc
) == 0
1952 /* The previous frame from a sigtramp frame might be frameless
1953 and have frame size zero. */
1954 && !frame
->signal_handler_caller
)
1957 return get_frame_pointer (frame
, proc_desc
);
1961 mips_init_extra_frame_info (fromleaf
, fci
)
1963 struct frame_info
*fci
;
1967 /* Use proc_desc calculated in frame_chain */
1968 mips_extra_func_info_t proc_desc
=
1969 fci
->next
? cached_proc_desc
: find_proc_desc (fci
->pc
, fci
->next
);
1971 fci
->extra_info
= (struct frame_extra_info
*)
1972 frame_obstack_alloc (sizeof (struct frame_extra_info
));
1974 fci
->saved_regs
= NULL
;
1975 fci
->extra_info
->proc_desc
=
1976 proc_desc
== &temp_proc_desc
? 0 : proc_desc
;
1979 /* Fixup frame-pointer - only needed for top frame */
1980 /* This may not be quite right, if proc has a real frame register.
1981 Get the value of the frame relative sp, procedure might have been
1982 interrupted by a signal at it's very start. */
1983 if (fci
->pc
== PROC_LOW_ADDR (proc_desc
)
1984 && !PROC_DESC_IS_DUMMY (proc_desc
))
1985 fci
->frame
= read_next_frame_reg (fci
->next
, SP_REGNUM
);
1987 fci
->frame
= get_frame_pointer (fci
->next
, proc_desc
);
1989 if (proc_desc
== &temp_proc_desc
)
1993 /* Do not set the saved registers for a sigtramp frame,
1994 mips_find_saved_registers will do that for us.
1995 We can't use fci->signal_handler_caller, it is not yet set. */
1996 find_pc_partial_function (fci
->pc
, &name
,
1997 (CORE_ADDR
*) NULL
, (CORE_ADDR
*) NULL
);
1998 if (!IN_SIGTRAMP (fci
->pc
, name
))
2000 frame_saved_regs_zalloc (fci
);
2001 memcpy (fci
->saved_regs
, temp_saved_regs
, SIZEOF_FRAME_SAVED_REGS
);
2002 fci
->saved_regs
[PC_REGNUM
]
2003 = fci
->saved_regs
[RA_REGNUM
];
2007 /* hack: if argument regs are saved, guess these contain args */
2008 /* assume we can't tell how many args for now */
2009 fci
->extra_info
->num_args
= -1;
2010 for (regnum
= MIPS_LAST_ARG_REGNUM
; regnum
>= A0_REGNUM
; regnum
--)
2012 if (PROC_REG_MASK (proc_desc
) & (1 << regnum
))
2014 fci
->extra_info
->num_args
= regnum
- A0_REGNUM
+ 1;
2021 /* MIPS stack frames are almost impenetrable. When execution stops,
2022 we basically have to look at symbol information for the function
2023 that we stopped in, which tells us *which* register (if any) is
2024 the base of the frame pointer, and what offset from that register
2025 the frame itself is at.
2027 This presents a problem when trying to examine a stack in memory
2028 (that isn't executing at the moment), using the "frame" command. We
2029 don't have a PC, nor do we have any registers except SP.
2031 This routine takes two arguments, SP and PC, and tries to make the
2032 cached frames look as if these two arguments defined a frame on the
2033 cache. This allows the rest of info frame to extract the important
2034 arguments without difficulty. */
2037 setup_arbitrary_frame (argc
, argv
)
2042 error ("MIPS frame specifications require two arguments: sp and pc");
2044 return create_new_frame (argv
[0], argv
[1]);
2048 mips_push_arguments (nargs
, args
, sp
, struct_return
, struct_addr
)
2053 CORE_ADDR struct_addr
;
2059 int stack_offset
= 0;
2061 /* Macros to round N up or down to the next A boundary; A must be
2063 #define ROUND_DOWN(n,a) ((n) & ~((a)-1))
2064 #define ROUND_UP(n,a) (((n)+(a)-1) & ~((a)-1))
2066 /* First ensure that the stack and structure return address (if any)
2067 are properly aligned. The stack has to be at least 64-bit aligned
2068 even on 32-bit machines, because doubles must be 64-bit aligned.
2069 On at least one MIPS variant, stack frames need to be 128-bit
2070 aligned, so we round to this widest known alignment. */
2071 sp
= ROUND_DOWN (sp
, 16);
2072 struct_addr
= ROUND_DOWN (struct_addr
, MIPS_SAVED_REGSIZE
);
2074 /* Now make space on the stack for the args. We allocate more
2075 than necessary for EABI, because the first few arguments are
2076 passed in registers, but that's OK. */
2077 for (argnum
= 0; argnum
< nargs
; argnum
++)
2078 len
+= ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])), MIPS_SAVED_REGSIZE
);
2079 sp
-= ROUND_UP (len
, 16);
2081 /* Initialize the integer and float register pointers. */
2083 float_argreg
= FPA0_REGNUM
;
2085 /* the struct_return pointer occupies the first parameter-passing reg */
2087 write_register (argreg
++, struct_addr
);
2089 /* Now load as many as possible of the first arguments into
2090 registers, and push the rest onto the stack. Loop thru args
2091 from first to last. */
2092 for (argnum
= 0; argnum
< nargs
; argnum
++)
2095 char valbuf
[MAX_REGISTER_RAW_SIZE
];
2096 value_ptr arg
= args
[argnum
];
2097 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
2098 int len
= TYPE_LENGTH (arg_type
);
2099 enum type_code typecode
= TYPE_CODE (arg_type
);
2101 /* The EABI passes structures that do not fit in a register by
2102 reference. In all other cases, pass the structure by value. */
2103 if (MIPS_EABI
&& len
> MIPS_SAVED_REGSIZE
&&
2104 (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
2106 store_address (valbuf
, MIPS_SAVED_REGSIZE
, VALUE_ADDRESS (arg
));
2107 typecode
= TYPE_CODE_PTR
;
2108 len
= MIPS_SAVED_REGSIZE
;
2112 val
= (char *) VALUE_CONTENTS (arg
);
2114 /* 32-bit ABIs always start floating point arguments in an
2115 even-numbered floating point register. */
2116 if (!FP_REGISTER_DOUBLE
&& typecode
== TYPE_CODE_FLT
2117 && (float_argreg
& 1))
2120 /* Floating point arguments passed in registers have to be
2121 treated specially. On 32-bit architectures, doubles
2122 are passed in register pairs; the even register gets
2123 the low word, and the odd register gets the high word.
2124 On non-EABI processors, the first two floating point arguments are
2125 also copied to general registers, because MIPS16 functions
2126 don't use float registers for arguments. This duplication of
2127 arguments in general registers can't hurt non-MIPS16 functions
2128 because those registers are normally skipped. */
2129 if (typecode
== TYPE_CODE_FLT
2130 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
2131 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
)
2133 if (!FP_REGISTER_DOUBLE
&& len
== 8)
2135 int low_offset
= TARGET_BYTE_ORDER
== BIG_ENDIAN
? 4 : 0;
2136 unsigned long regval
;
2138 /* Write the low word of the double to the even register(s). */
2139 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
2140 write_register (float_argreg
++, regval
);
2142 write_register (argreg
+ 1, regval
);
2144 /* Write the high word of the double to the odd register(s). */
2145 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
2146 write_register (float_argreg
++, regval
);
2149 write_register (argreg
, regval
);
2156 /* This is a floating point value that fits entirely
2157 in a single register. */
2158 /* On 32 bit ABI's the float_argreg is further adjusted
2159 above to ensure that it is even register aligned. */
2160 CORE_ADDR regval
= extract_address (val
, len
);
2161 write_register (float_argreg
++, regval
);
2164 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
2165 registers for each argument. The below is (my
2166 guess) to ensure that the corresponding integer
2167 register has reserved the same space. */
2168 write_register (argreg
, regval
);
2169 argreg
+= FP_REGISTER_DOUBLE
? 1 : 2;
2175 /* Copy the argument to general registers or the stack in
2176 register-sized pieces. Large arguments are split between
2177 registers and stack. */
2178 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
2179 are treated specially: Irix cc passes them in registers
2180 where gcc sometimes puts them on the stack. For maximum
2181 compatibility, we will put them in both places. */
2183 int odd_sized_struct
= ((len
> MIPS_SAVED_REGSIZE
) &&
2184 (len
% MIPS_SAVED_REGSIZE
!= 0));
2187 int partial_len
= len
< MIPS_SAVED_REGSIZE
? len
: MIPS_SAVED_REGSIZE
;
2189 if (argreg
> MIPS_LAST_ARG_REGNUM
|| odd_sized_struct
)
2191 /* Write this portion of the argument to the stack. */
2192 /* Should shorter than int integer values be
2193 promoted to int before being stored? */
2195 int longword_offset
= 0;
2196 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2198 if (MIPS_STACK_ARGSIZE
== 8 &&
2199 (typecode
== TYPE_CODE_INT
||
2200 typecode
== TYPE_CODE_PTR
||
2201 typecode
== TYPE_CODE_FLT
) && len
<= 4)
2202 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
2203 else if ((typecode
== TYPE_CODE_STRUCT
||
2204 typecode
== TYPE_CODE_UNION
) &&
2205 TYPE_LENGTH (arg_type
) < MIPS_STACK_ARGSIZE
)
2206 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
2209 write_memory (sp
+ stack_offset
+ longword_offset
,
2213 /* Note!!! This is NOT an else clause.
2214 Odd sized structs may go thru BOTH paths. */
2215 if (argreg
<= MIPS_LAST_ARG_REGNUM
)
2217 CORE_ADDR regval
= extract_address (val
, partial_len
);
2219 /* A non-floating-point argument being passed in a
2220 general register. If a struct or union, and if
2221 the remaining length is smaller than the register
2222 size, we have to adjust the register value on
2225 It does not seem to be necessary to do the
2226 same for integral types.
2228 Also don't do this adjustment on EABI and O64
2232 && MIPS_SAVED_REGSIZE
< 8
2233 && TARGET_BYTE_ORDER
== BIG_ENDIAN
2234 && partial_len
< MIPS_SAVED_REGSIZE
2235 && (typecode
== TYPE_CODE_STRUCT
||
2236 typecode
== TYPE_CODE_UNION
))
2237 regval
<<= ((MIPS_SAVED_REGSIZE
- partial_len
) *
2240 write_register (argreg
, regval
);
2243 /* If this is the old ABI, prevent subsequent floating
2244 point arguments from being passed in floating point
2247 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
2253 /* The offset onto the stack at which we will start
2254 copying parameters (after the registers are used up)
2255 begins at (4 * MIPS_REGSIZE) in the old ABI. This
2256 leaves room for the "home" area for register parameters.
2258 In the new EABI (and the NABI32), the 8 register parameters
2259 do not have "home" stack space reserved for them, so the
2260 stack offset does not get incremented until after
2261 we have used up the 8 parameter registers. */
2263 if (MIPS_REGS_HAVE_HOME_P
|| argnum
>= 8)
2264 stack_offset
+= ROUND_UP (partial_len
, MIPS_STACK_ARGSIZE
);
2269 /* Return adjusted stack pointer. */
2274 mips_push_return_address (pc
, sp
)
2278 /* Set the return address register to point to the entry
2279 point of the program, where a breakpoint lies in wait. */
2280 write_register (RA_REGNUM
, CALL_DUMMY_ADDRESS ());
2285 mips_push_register (CORE_ADDR
* sp
, int regno
)
2287 char buffer
[MAX_REGISTER_RAW_SIZE
];
2290 if (MIPS_SAVED_REGSIZE
< REGISTER_RAW_SIZE (regno
))
2292 regsize
= MIPS_SAVED_REGSIZE
;
2293 offset
= (TARGET_BYTE_ORDER
== BIG_ENDIAN
2294 ? REGISTER_RAW_SIZE (regno
) - MIPS_SAVED_REGSIZE
2299 regsize
= REGISTER_RAW_SIZE (regno
);
2303 read_register_gen (regno
, buffer
);
2304 write_memory (*sp
, buffer
+ offset
, regsize
);
2307 /* MASK(i,j) == (1<<i) + (1<<(i+1)) + ... + (1<<j)). Assume i<=j<(MIPS_NUMREGS-1). */
2308 #define MASK(i,j) (((1 << ((j)+1))-1) ^ ((1 << (i))-1))
2311 mips_push_dummy_frame ()
2314 struct linked_proc_info
*link
= (struct linked_proc_info
*)
2315 xmalloc (sizeof (struct linked_proc_info
));
2316 mips_extra_func_info_t proc_desc
= &link
->info
;
2317 CORE_ADDR sp
= ADDR_BITS_REMOVE (read_register (SP_REGNUM
));
2318 CORE_ADDR old_sp
= sp
;
2319 link
->next
= linked_proc_desc_table
;
2320 linked_proc_desc_table
= link
;
2322 /* FIXME! are these correct ? */
2323 #define PUSH_FP_REGNUM 16 /* must be a register preserved across calls */
2324 #define GEN_REG_SAVE_MASK MASK(1,16)|MASK(24,28)|(1<<(MIPS_NUMREGS-1))
2325 #define FLOAT_REG_SAVE_MASK MASK(0,19)
2326 #define FLOAT_SINGLE_REG_SAVE_MASK \
2327 ((1<<18)|(1<<16)|(1<<14)|(1<<12)|(1<<10)|(1<<8)|(1<<6)|(1<<4)|(1<<2)|(1<<0))
2329 * The registers we must save are all those not preserved across
2330 * procedure calls. Dest_Reg (see tm-mips.h) must also be saved.
2331 * In addition, we must save the PC, PUSH_FP_REGNUM, MMLO/-HI
2332 * and FP Control/Status registers.
2335 * Dummy frame layout:
2338 * Saved MMHI, MMLO, FPC_CSR
2343 * Saved D18 (i.e. F19, F18)
2345 * Saved D0 (i.e. F1, F0)
2346 * Argument build area and stack arguments written via mips_push_arguments
2350 /* Save special registers (PC, MMHI, MMLO, FPC_CSR) */
2351 PROC_FRAME_REG (proc_desc
) = PUSH_FP_REGNUM
;
2352 PROC_FRAME_OFFSET (proc_desc
) = 0;
2353 PROC_FRAME_ADJUST (proc_desc
) = 0;
2354 mips_push_register (&sp
, PC_REGNUM
);
2355 mips_push_register (&sp
, HI_REGNUM
);
2356 mips_push_register (&sp
, LO_REGNUM
);
2357 mips_push_register (&sp
, MIPS_FPU_TYPE
== MIPS_FPU_NONE
? 0 : FCRCS_REGNUM
);
2359 /* Save general CPU registers */
2360 PROC_REG_MASK (proc_desc
) = GEN_REG_SAVE_MASK
;
2361 /* PROC_REG_OFFSET is the offset of the first saved register from FP. */
2362 PROC_REG_OFFSET (proc_desc
) = sp
- old_sp
- MIPS_SAVED_REGSIZE
;
2363 for (ireg
= 32; --ireg
>= 0;)
2364 if (PROC_REG_MASK (proc_desc
) & (1 << ireg
))
2365 mips_push_register (&sp
, ireg
);
2367 /* Save floating point registers starting with high order word */
2368 PROC_FREG_MASK (proc_desc
) =
2369 MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? FLOAT_REG_SAVE_MASK
2370 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? FLOAT_SINGLE_REG_SAVE_MASK
: 0;
2371 /* PROC_FREG_OFFSET is the offset of the first saved *double* register
2373 PROC_FREG_OFFSET (proc_desc
) = sp
- old_sp
- 8;
2374 for (ireg
= 32; --ireg
>= 0;)
2375 if (PROC_FREG_MASK (proc_desc
) & (1 << ireg
))
2376 mips_push_register (&sp
, ireg
+ FP0_REGNUM
);
2378 /* Update the frame pointer for the call dummy and the stack pointer.
2379 Set the procedure's starting and ending addresses to point to the
2380 call dummy address at the entry point. */
2381 write_register (PUSH_FP_REGNUM
, old_sp
);
2382 write_register (SP_REGNUM
, sp
);
2383 PROC_LOW_ADDR (proc_desc
) = CALL_DUMMY_ADDRESS ();
2384 PROC_HIGH_ADDR (proc_desc
) = CALL_DUMMY_ADDRESS () + 4;
2385 SET_PROC_DESC_IS_DUMMY (proc_desc
);
2386 PROC_PC_REG (proc_desc
) = RA_REGNUM
;
2392 register int regnum
;
2393 struct frame_info
*frame
= get_current_frame ();
2394 CORE_ADDR new_sp
= FRAME_FP (frame
);
2396 mips_extra_func_info_t proc_desc
= frame
->extra_info
->proc_desc
;
2398 write_register (PC_REGNUM
, FRAME_SAVED_PC (frame
));
2399 if (frame
->saved_regs
== NULL
)
2400 mips_find_saved_regs (frame
);
2401 for (regnum
= 0; regnum
< NUM_REGS
; regnum
++)
2403 if (regnum
!= SP_REGNUM
&& regnum
!= PC_REGNUM
2404 && frame
->saved_regs
[regnum
])
2405 write_register (regnum
,
2406 read_memory_integer (frame
->saved_regs
[regnum
],
2407 MIPS_SAVED_REGSIZE
));
2409 write_register (SP_REGNUM
, new_sp
);
2410 flush_cached_frames ();
2412 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
2414 struct linked_proc_info
*pi_ptr
, *prev_ptr
;
2416 for (pi_ptr
= linked_proc_desc_table
, prev_ptr
= NULL
;
2418 prev_ptr
= pi_ptr
, pi_ptr
= pi_ptr
->next
)
2420 if (&pi_ptr
->info
== proc_desc
)
2425 error ("Can't locate dummy extra frame info\n");
2427 if (prev_ptr
!= NULL
)
2428 prev_ptr
->next
= pi_ptr
->next
;
2430 linked_proc_desc_table
= pi_ptr
->next
;
2434 write_register (HI_REGNUM
,
2435 read_memory_integer (new_sp
- 2 * MIPS_SAVED_REGSIZE
,
2436 MIPS_SAVED_REGSIZE
));
2437 write_register (LO_REGNUM
,
2438 read_memory_integer (new_sp
- 3 * MIPS_SAVED_REGSIZE
,
2439 MIPS_SAVED_REGSIZE
));
2440 if (MIPS_FPU_TYPE
!= MIPS_FPU_NONE
)
2441 write_register (FCRCS_REGNUM
,
2442 read_memory_integer (new_sp
- 4 * MIPS_SAVED_REGSIZE
,
2443 MIPS_SAVED_REGSIZE
));
2448 mips_print_register (regnum
, all
)
2451 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
2453 /* Get the data in raw format. */
2454 if (read_relative_register_raw_bytes (regnum
, raw_buffer
))
2456 printf_filtered ("%s: [Invalid]", REGISTER_NAME (regnum
));
2460 /* If an even floating point register, also print as double. */
2461 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
2462 && !((regnum
- FP0_REGNUM
) & 1))
2463 if (REGISTER_RAW_SIZE (regnum
) == 4) /* this would be silly on MIPS64 or N32 (Irix 6) */
2465 char dbuffer
[2 * MAX_REGISTER_RAW_SIZE
];
2467 read_relative_register_raw_bytes (regnum
, dbuffer
);
2468 read_relative_register_raw_bytes (regnum
+ 1, dbuffer
+ MIPS_REGSIZE
);
2469 REGISTER_CONVERT_TO_TYPE (regnum
, builtin_type_double
, dbuffer
);
2471 printf_filtered ("(d%d: ", regnum
- FP0_REGNUM
);
2472 val_print (builtin_type_double
, dbuffer
, 0, 0,
2473 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2474 printf_filtered ("); ");
2476 fputs_filtered (REGISTER_NAME (regnum
), gdb_stdout
);
2478 /* The problem with printing numeric register names (r26, etc.) is that
2479 the user can't use them on input. Probably the best solution is to
2480 fix it so that either the numeric or the funky (a2, etc.) names
2481 are accepted on input. */
2482 if (regnum
< MIPS_NUMREGS
)
2483 printf_filtered ("(r%d): ", regnum
);
2485 printf_filtered (": ");
2487 /* If virtual format is floating, print it that way. */
2488 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2489 if (FP_REGISTER_DOUBLE
)
2490 { /* show 8-byte floats as float AND double: */
2491 int offset
= 4 * (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
2493 printf_filtered (" (float) ");
2494 val_print (builtin_type_float
, raw_buffer
+ offset
, 0, 0,
2495 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2496 printf_filtered (", (double) ");
2497 val_print (builtin_type_double
, raw_buffer
, 0, 0,
2498 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2501 val_print (REGISTER_VIRTUAL_TYPE (regnum
), raw_buffer
, 0, 0,
2502 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2503 /* Else print as integer in hex. */
2508 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2509 offset
= REGISTER_RAW_SIZE (regnum
) - REGISTER_VIRTUAL_SIZE (regnum
);
2513 print_scalar_formatted (raw_buffer
+ offset
,
2514 REGISTER_VIRTUAL_TYPE (regnum
),
2515 'x', 0, gdb_stdout
);
2519 /* Replacement for generic do_registers_info.
2520 Print regs in pretty columns. */
2523 do_fp_register_row (regnum
)
2525 { /* do values for FP (float) regs */
2526 char *raw_buffer
[2];
2528 /* use HI and LO to control the order of combining two flt regs */
2529 int HI
= (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
2530 int LO
= (TARGET_BYTE_ORDER
!= BIG_ENDIAN
);
2531 double doub
, flt1
, flt2
; /* doubles extracted from raw hex data */
2532 int inv1
, inv2
, inv3
;
2534 raw_buffer
[0] = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM
));
2535 raw_buffer
[1] = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM
));
2536 dbl_buffer
= (char *) alloca (2 * REGISTER_RAW_SIZE (FP0_REGNUM
));
2538 /* Get the data in raw format. */
2539 if (read_relative_register_raw_bytes (regnum
, raw_buffer
[HI
]))
2540 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
2541 if (REGISTER_RAW_SIZE (regnum
) == 4)
2543 /* 4-byte registers: we can fit two registers per row. */
2544 /* Also print every pair of 4-byte regs as an 8-byte double. */
2545 if (read_relative_register_raw_bytes (regnum
+ 1, raw_buffer
[LO
]))
2546 error ("can't read register %d (%s)",
2547 regnum
+ 1, REGISTER_NAME (regnum
+ 1));
2549 /* copy the two floats into one double, and unpack both */
2550 memcpy (dbl_buffer
, raw_buffer
, 2 * REGISTER_RAW_SIZE (FP0_REGNUM
));
2551 flt1
= unpack_double (builtin_type_float
, raw_buffer
[HI
], &inv1
);
2552 flt2
= unpack_double (builtin_type_float
, raw_buffer
[LO
], &inv2
);
2553 doub
= unpack_double (builtin_type_double
, dbl_buffer
, &inv3
);
2555 printf_filtered (inv1
? " %-5s: <invalid float>" :
2556 " %-5s%-17.9g", REGISTER_NAME (regnum
), flt1
);
2557 printf_filtered (inv2
? " %-5s: <invalid float>" :
2558 " %-5s%-17.9g", REGISTER_NAME (regnum
+ 1), flt2
);
2559 printf_filtered (inv3
? " dbl: <invalid double>\n" :
2560 " dbl: %-24.17g\n", doub
);
2561 /* may want to do hex display here (future enhancement) */
2565 { /* eight byte registers: print each one as float AND as double. */
2566 int offset
= 4 * (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
2568 memcpy (dbl_buffer
, raw_buffer
[HI
], 2 * REGISTER_RAW_SIZE (FP0_REGNUM
));
2569 flt1
= unpack_double (builtin_type_float
,
2570 &raw_buffer
[HI
][offset
], &inv1
);
2571 doub
= unpack_double (builtin_type_double
, dbl_buffer
, &inv3
);
2573 printf_filtered (inv1
? " %-5s: <invalid float>" :
2574 " %-5s flt: %-17.9g", REGISTER_NAME (regnum
), flt1
);
2575 printf_filtered (inv3
? " dbl: <invalid double>\n" :
2576 " dbl: %-24.17g\n", doub
);
2577 /* may want to do hex display here (future enhancement) */
2583 /* Print a row's worth of GP (int) registers, with name labels above */
2586 do_gp_register_row (regnum
)
2589 /* do values for GP (int) regs */
2590 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
2591 int ncols
= (MIPS_REGSIZE
== 8 ? 4 : 8); /* display cols per row */
2593 int start_regnum
= regnum
;
2594 int numregs
= NUM_REGS
;
2597 /* For GP registers, we print a separate row of names above the vals */
2598 printf_filtered (" ");
2599 for (col
= 0; col
< ncols
&& regnum
< numregs
; regnum
++)
2601 if (*REGISTER_NAME (regnum
) == '\0')
2602 continue; /* unused register */
2603 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2604 break; /* end the row: reached FP register */
2605 printf_filtered (MIPS_REGSIZE
== 8 ? "%17s" : "%9s",
2606 REGISTER_NAME (regnum
));
2609 printf_filtered (start_regnum
< MIPS_NUMREGS
? "\n R%-4d" : "\n ",
2610 start_regnum
); /* print the R0 to R31 names */
2612 regnum
= start_regnum
; /* go back to start of row */
2613 /* now print the values in hex, 4 or 8 to the row */
2614 for (col
= 0; col
< ncols
&& regnum
< numregs
; regnum
++)
2616 if (*REGISTER_NAME (regnum
) == '\0')
2617 continue; /* unused register */
2618 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2619 break; /* end row: reached FP register */
2620 /* OK: get the data in raw format. */
2621 if (read_relative_register_raw_bytes (regnum
, raw_buffer
))
2622 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
2623 /* pad small registers */
2624 for (byte
= 0; byte
< (MIPS_REGSIZE
- REGISTER_VIRTUAL_SIZE (regnum
)); byte
++)
2625 printf_filtered (" ");
2626 /* Now print the register value in hex, endian order. */
2627 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2628 for (byte
= REGISTER_RAW_SIZE (regnum
) - REGISTER_VIRTUAL_SIZE (regnum
);
2629 byte
< REGISTER_RAW_SIZE (regnum
);
2631 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
2633 for (byte
= REGISTER_VIRTUAL_SIZE (regnum
) - 1;
2636 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
2637 printf_filtered (" ");
2640 if (col
> 0) /* ie. if we actually printed anything... */
2641 printf_filtered ("\n");
2646 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
2649 mips_do_registers_info (regnum
, fpregs
)
2653 if (regnum
!= -1) /* do one specified register */
2655 if (*(REGISTER_NAME (regnum
)) == '\0')
2656 error ("Not a valid register for the current processor type");
2658 mips_print_register (regnum
, 0);
2659 printf_filtered ("\n");
2662 /* do all (or most) registers */
2665 while (regnum
< NUM_REGS
)
2667 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2668 if (fpregs
) /* true for "INFO ALL-REGISTERS" command */
2669 regnum
= do_fp_register_row (regnum
); /* FP regs */
2671 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
2673 regnum
= do_gp_register_row (regnum
); /* GP (int) regs */
2678 /* Return number of args passed to a frame. described by FIP.
2679 Can return -1, meaning no way to tell. */
2682 mips_frame_num_args (frame
)
2683 struct frame_info
*frame
;
2685 #if 0 /* FIXME Use or lose this! */
2686 struct chain_info_t
*p
;
2688 p
= mips_find_cached_frame (FRAME_FP (frame
));
2690 return p
->the_info
.numargs
;
2695 /* Is this a branch with a delay slot? */
2697 static int is_delayed
PARAMS ((unsigned long));
2704 for (i
= 0; i
< NUMOPCODES
; ++i
)
2705 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
2706 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
2708 return (i
< NUMOPCODES
2709 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
2710 | INSN_COND_BRANCH_DELAY
2711 | INSN_COND_BRANCH_LIKELY
)));
2715 mips_step_skips_delay (pc
)
2718 char buf
[MIPS_INSTLEN
];
2720 /* There is no branch delay slot on MIPS16. */
2721 if (pc_is_mips16 (pc
))
2724 if (target_read_memory (pc
, buf
, MIPS_INSTLEN
) != 0)
2725 /* If error reading memory, guess that it is not a delayed branch. */
2727 return is_delayed ((unsigned long) extract_unsigned_integer (buf
, MIPS_INSTLEN
));
2731 /* Skip the PC past function prologue instructions (32-bit version).
2732 This is a helper function for mips_skip_prologue. */
2735 mips32_skip_prologue (pc
, lenient
)
2736 CORE_ADDR pc
; /* starting PC to search from */
2741 int seen_sp_adjust
= 0;
2742 int load_immediate_bytes
= 0;
2744 /* Skip the typical prologue instructions. These are the stack adjustment
2745 instruction and the instructions that save registers on the stack
2746 or in the gcc frame. */
2747 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS_INSTLEN
)
2749 unsigned long high_word
;
2751 inst
= mips_fetch_instruction (pc
);
2752 high_word
= (inst
>> 16) & 0xffff;
2755 if (lenient
&& is_delayed (inst
))
2759 if (high_word
== 0x27bd /* addiu $sp,$sp,offset */
2760 || high_word
== 0x67bd) /* daddiu $sp,$sp,offset */
2762 else if (inst
== 0x03a1e823 || /* subu $sp,$sp,$at */
2763 inst
== 0x03a8e823) /* subu $sp,$sp,$t0 */
2765 else if (((inst
& 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
2766 || (inst
& 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
2767 && (inst
& 0x001F0000)) /* reg != $zero */
2770 else if ((inst
& 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
2772 else if ((inst
& 0xF3E00000) == 0xA3C00000 && (inst
& 0x001F0000))
2774 continue; /* reg != $zero */
2776 /* move $s8,$sp. With different versions of gas this will be either
2777 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
2778 Accept any one of these. */
2779 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2782 else if ((inst
& 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
2784 else if (high_word
== 0x3c1c) /* lui $gp,n */
2786 else if (high_word
== 0x279c) /* addiu $gp,$gp,n */
2788 else if (inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
2789 || inst
== 0x033ce021) /* addu $gp,$t9,$gp */
2791 /* The following instructions load $at or $t0 with an immediate
2792 value in preparation for a stack adjustment via
2793 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
2794 a local variable, so we accept them only before a stack adjustment
2795 instruction was seen. */
2796 else if (!seen_sp_adjust
)
2798 if (high_word
== 0x3c01 || /* lui $at,n */
2799 high_word
== 0x3c08) /* lui $t0,n */
2801 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
2804 else if (high_word
== 0x3421 || /* ori $at,$at,n */
2805 high_word
== 0x3508 || /* ori $t0,$t0,n */
2806 high_word
== 0x3401 || /* ori $at,$zero,n */
2807 high_word
== 0x3408) /* ori $t0,$zero,n */
2809 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
2819 /* In a frameless function, we might have incorrectly
2820 skipped some load immediate instructions. Undo the skipping
2821 if the load immediate was not followed by a stack adjustment. */
2822 if (load_immediate_bytes
&& !seen_sp_adjust
)
2823 pc
-= load_immediate_bytes
;
2827 /* Skip the PC past function prologue instructions (16-bit version).
2828 This is a helper function for mips_skip_prologue. */
2831 mips16_skip_prologue (pc
, lenient
)
2832 CORE_ADDR pc
; /* starting PC to search from */
2836 int extend_bytes
= 0;
2837 int prev_extend_bytes
;
2839 /* Table of instructions likely to be found in a function prologue. */
2842 unsigned short inst
;
2843 unsigned short mask
;
2850 , /* addiu $sp,offset */
2854 , /* daddiu $sp,offset */
2858 , /* sw reg,n($sp) */
2862 , /* sd reg,n($sp) */
2866 , /* sw $ra,n($sp) */
2870 , /* sd $ra,n($sp) */
2878 , /* sw $a0-$a3,n($s1) */
2882 , /* move reg,$a0-$a3 */
2886 , /* entry pseudo-op */
2890 , /* addiu $s1,$sp,n */
2893 } /* end of table marker */
2896 /* Skip the typical prologue instructions. These are the stack adjustment
2897 instruction and the instructions that save registers on the stack
2898 or in the gcc frame. */
2899 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS16_INSTLEN
)
2901 unsigned short inst
;
2904 inst
= mips_fetch_instruction (pc
);
2906 /* Normally we ignore an extend instruction. However, if it is
2907 not followed by a valid prologue instruction, we must adjust
2908 the pc back over the extend so that it won't be considered
2909 part of the prologue. */
2910 if ((inst
& 0xf800) == 0xf000) /* extend */
2912 extend_bytes
= MIPS16_INSTLEN
;
2915 prev_extend_bytes
= extend_bytes
;
2918 /* Check for other valid prologue instructions besides extend. */
2919 for (i
= 0; table
[i
].mask
!= 0; i
++)
2920 if ((inst
& table
[i
].mask
) == table
[i
].inst
) /* found, get out */
2922 if (table
[i
].mask
!= 0) /* it was in table? */
2923 continue; /* ignore it */
2927 /* Return the current pc, adjusted backwards by 2 if
2928 the previous instruction was an extend. */
2929 return pc
- prev_extend_bytes
;
2935 /* To skip prologues, I use this predicate. Returns either PC itself
2936 if the code at PC does not look like a function prologue; otherwise
2937 returns an address that (if we're lucky) follows the prologue. If
2938 LENIENT, then we must skip everything which is involved in setting
2939 up the frame (it's OK to skip more, just so long as we don't skip
2940 anything which might clobber the registers which are being saved.
2941 We must skip more in the case where part of the prologue is in the
2942 delay slot of a non-prologue instruction). */
2945 mips_skip_prologue (pc
, lenient
)
2949 /* See if we can determine the end of the prologue via the symbol table.
2950 If so, then return either PC, or the PC after the prologue, whichever
2953 CORE_ADDR post_prologue_pc
= after_prologue (pc
, NULL
);
2955 if (post_prologue_pc
!= 0)
2956 return max (pc
, post_prologue_pc
);
2958 /* Can't determine prologue from the symbol table, need to examine
2961 if (pc_is_mips16 (pc
))
2962 return mips16_skip_prologue (pc
, lenient
);
2964 return mips32_skip_prologue (pc
, lenient
);
2968 /* The lenient prologue stuff should be superseded by the code in
2969 init_extra_frame_info which looks to see whether the stores mentioned
2970 in the proc_desc have actually taken place. */
2972 /* Is address PC in the prologue (loosely defined) for function at
2976 mips_in_lenient_prologue (startaddr
, pc
)
2977 CORE_ADDR startaddr
;
2980 CORE_ADDR end_prologue
= mips_skip_prologue (startaddr
, 1);
2981 return pc
>= startaddr
&& pc
< end_prologue
;
2985 /* Determine how a return value is stored within the MIPS register
2986 file, given the return type `valtype'. */
2988 struct return_value_word
2996 static void return_value_location
PARAMS ((struct type
*, struct return_value_word
*, struct return_value_word
*));
2999 return_value_location (valtype
, hi
, lo
)
3000 struct type
*valtype
;
3001 struct return_value_word
*hi
;
3002 struct return_value_word
*lo
;
3004 int len
= TYPE_LENGTH (valtype
);
3006 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
3007 && ((MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
&& (len
== 4 || len
== 8))
3008 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
&& len
== 4)))
3010 if (!FP_REGISTER_DOUBLE
&& len
== 8)
3012 /* We need to break a 64bit float in two 32 bit halves and
3013 spread them across a floating-point register pair. */
3014 lo
->buf_offset
= TARGET_BYTE_ORDER
== BIG_ENDIAN
? 4 : 0;
3015 hi
->buf_offset
= TARGET_BYTE_ORDER
== BIG_ENDIAN
? 0 : 4;
3016 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BIG_ENDIAN
3017 && REGISTER_RAW_SIZE (FP0_REGNUM
) == 8)
3019 hi
->reg_offset
= lo
->reg_offset
;
3020 lo
->reg
= FP0_REGNUM
+ 0;
3021 hi
->reg
= FP0_REGNUM
+ 1;
3027 /* The floating point value fits in a single floating-point
3029 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BIG_ENDIAN
3030 && REGISTER_RAW_SIZE (FP0_REGNUM
) == 8
3033 lo
->reg
= FP0_REGNUM
;
3044 /* Locate a result possibly spread across two registers. */
3046 lo
->reg
= regnum
+ 0;
3047 hi
->reg
= regnum
+ 1;
3048 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
3049 && len
< MIPS_SAVED_REGSIZE
)
3051 /* "un-left-justify" the value in the low register */
3052 lo
->reg_offset
= MIPS_SAVED_REGSIZE
- len
;
3057 else if (TARGET_BYTE_ORDER
== BIG_ENDIAN
3058 && len
> MIPS_SAVED_REGSIZE
/* odd-size structs */
3059 && len
< MIPS_SAVED_REGSIZE
* 2
3060 && (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
3061 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
3063 /* "un-left-justify" the value spread across two registers. */
3064 lo
->reg_offset
= 2 * MIPS_SAVED_REGSIZE
- len
;
3065 lo
->len
= MIPS_SAVED_REGSIZE
- lo
->reg_offset
;
3067 hi
->len
= len
- lo
->len
;
3071 /* Only perform a partial copy of the second register. */
3074 if (len
> MIPS_SAVED_REGSIZE
)
3076 lo
->len
= MIPS_SAVED_REGSIZE
;
3077 hi
->len
= len
- MIPS_SAVED_REGSIZE
;
3085 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
3086 && REGISTER_RAW_SIZE (regnum
) == 8
3087 && MIPS_SAVED_REGSIZE
== 4)
3089 /* Account for the fact that only the least-signficant part
3090 of the register is being used */
3091 lo
->reg_offset
+= 4;
3092 hi
->reg_offset
+= 4;
3095 hi
->buf_offset
= lo
->len
;
3099 /* Given a return value in `regbuf' with a type `valtype', extract and
3100 copy its value into `valbuf'. */
3103 mips_extract_return_value (valtype
, regbuf
, valbuf
)
3104 struct type
*valtype
;
3105 char regbuf
[REGISTER_BYTES
];
3108 struct return_value_word lo
;
3109 struct return_value_word hi
;
3110 return_value_location (valtype
, &lo
, &hi
);
3112 memcpy (valbuf
+ lo
.buf_offset
,
3113 regbuf
+ REGISTER_BYTE (lo
.reg
) + lo
.reg_offset
,
3117 memcpy (valbuf
+ hi
.buf_offset
,
3118 regbuf
+ REGISTER_BYTE (hi
.reg
) + hi
.reg_offset
,
3124 int len
= TYPE_LENGTH (valtype
);
3127 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
3128 && (MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
3129 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
3130 && len
<= MIPS_FPU_SINGLE_REGSIZE
)))
3131 regnum
= FP0_REGNUM
;
3133 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
3134 { /* "un-left-justify" the value from the register */
3135 if (len
< REGISTER_RAW_SIZE (regnum
))
3136 offset
= REGISTER_RAW_SIZE (regnum
) - len
;
3137 if (len
> REGISTER_RAW_SIZE (regnum
) && /* odd-size structs */
3138 len
< REGISTER_RAW_SIZE (regnum
) * 2 &&
3139 (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
3140 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
3141 offset
= 2 * REGISTER_RAW_SIZE (regnum
) - len
;
3143 memcpy (valbuf
, regbuf
+ REGISTER_BYTE (regnum
) + offset
, len
);
3144 REGISTER_CONVERT_TO_TYPE (regnum
, valtype
, valbuf
);
3148 /* Given a return value in `valbuf' with a type `valtype', write it's
3149 value into the appropriate register. */
3152 mips_store_return_value (valtype
, valbuf
)
3153 struct type
*valtype
;
3156 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
3157 struct return_value_word lo
;
3158 struct return_value_word hi
;
3159 return_value_location (valtype
, &lo
, &hi
);
3161 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3162 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
3163 write_register_bytes (REGISTER_BYTE (lo
.reg
),
3165 REGISTER_RAW_SIZE (lo
.reg
));
3169 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3170 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
3171 write_register_bytes (REGISTER_BYTE (hi
.reg
),
3173 REGISTER_RAW_SIZE (hi
.reg
));
3179 int len
= TYPE_LENGTH (valtype
);
3180 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
3183 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
3184 && (MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
3185 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
3186 && len
<= MIPS_REGSIZE
)))
3187 regnum
= FP0_REGNUM
;
3189 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
3190 { /* "left-justify" the value in the register */
3191 if (len
< REGISTER_RAW_SIZE (regnum
))
3192 offset
= REGISTER_RAW_SIZE (regnum
) - len
;
3193 if (len
> REGISTER_RAW_SIZE (regnum
) && /* odd-size structs */
3194 len
< REGISTER_RAW_SIZE (regnum
) * 2 &&
3195 (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
3196 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
3197 offset
= 2 * REGISTER_RAW_SIZE (regnum
) - len
;
3199 memcpy (raw_buffer
+ offset
, valbuf
, len
);
3200 REGISTER_CONVERT_FROM_TYPE (regnum
, valtype
, raw_buffer
);
3201 write_register_bytes (REGISTER_BYTE (regnum
), raw_buffer
,
3202 len
> REGISTER_RAW_SIZE (regnum
) ?
3203 len
: REGISTER_RAW_SIZE (regnum
));
3207 /* Exported procedure: Is PC in the signal trampoline code */
3210 in_sigtramp (pc
, ignore
)
3212 char *ignore
; /* function name */
3214 if (sigtramp_address
== 0)
3216 return (pc
>= sigtramp_address
&& pc
< sigtramp_end
);
3219 /* Root of all "set mips "/"show mips " commands. This will eventually be
3220 used for all MIPS-specific commands. */
3222 static void show_mips_command
PARAMS ((char *, int));
3224 show_mips_command (args
, from_tty
)
3228 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
3231 static void set_mips_command
PARAMS ((char *, int));
3233 set_mips_command (args
, from_tty
)
3237 printf_unfiltered ("\"set mips\" must be followed by an appropriate subcommand.\n");
3238 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
3241 /* Commands to show/set the MIPS FPU type. */
3243 static void show_mipsfpu_command
PARAMS ((char *, int));
3245 show_mipsfpu_command (args
, from_tty
)
3251 switch (MIPS_FPU_TYPE
)
3253 case MIPS_FPU_SINGLE
:
3254 fpu
= "single-precision";
3256 case MIPS_FPU_DOUBLE
:
3257 fpu
= "double-precision";
3260 fpu
= "absent (none)";
3263 if (mips_fpu_type_auto
)
3264 printf_unfiltered ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
3267 printf_unfiltered ("The MIPS floating-point coprocessor is assumed to be %s\n",
3272 static void set_mipsfpu_command
PARAMS ((char *, int));
3274 set_mipsfpu_command (args
, from_tty
)
3278 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
3279 show_mipsfpu_command (args
, from_tty
);
3282 static void set_mipsfpu_single_command
PARAMS ((char *, int));
3284 set_mipsfpu_single_command (args
, from_tty
)
3288 mips_fpu_type
= MIPS_FPU_SINGLE
;
3289 mips_fpu_type_auto
= 0;
3292 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_SINGLE
;
3296 static void set_mipsfpu_double_command
PARAMS ((char *, int));
3298 set_mipsfpu_double_command (args
, from_tty
)
3302 mips_fpu_type
= MIPS_FPU_DOUBLE
;
3303 mips_fpu_type_auto
= 0;
3306 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_DOUBLE
;
3310 static void set_mipsfpu_none_command
PARAMS ((char *, int));
3312 set_mipsfpu_none_command (args
, from_tty
)
3316 mips_fpu_type
= MIPS_FPU_NONE
;
3317 mips_fpu_type_auto
= 0;
3320 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_NONE
;
3324 static void set_mipsfpu_auto_command
PARAMS ((char *, int));
3326 set_mipsfpu_auto_command (args
, from_tty
)
3330 mips_fpu_type_auto
= 1;
3333 /* Command to set the processor type. */
3336 mips_set_processor_type_command (args
, from_tty
)
3342 if (tmp_mips_processor_type
== NULL
|| *tmp_mips_processor_type
== '\0')
3344 printf_unfiltered ("The known MIPS processor types are as follows:\n\n");
3345 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
3346 printf_unfiltered ("%s\n", mips_processor_type_table
[i
].name
);
3348 /* Restore the value. */
3349 tmp_mips_processor_type
= strsave (mips_processor_type
);
3354 if (!mips_set_processor_type (tmp_mips_processor_type
))
3356 error ("Unknown processor type `%s'.", tmp_mips_processor_type
);
3357 /* Restore its value. */
3358 tmp_mips_processor_type
= strsave (mips_processor_type
);
3363 mips_show_processor_type_command (args
, from_tty
)
3369 /* Modify the actual processor type. */
3372 mips_set_processor_type (str
)
3380 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
3382 if (strcasecmp (str
, mips_processor_type_table
[i
].name
) == 0)
3384 mips_processor_type
= str
;
3385 mips_processor_reg_names
= mips_processor_type_table
[i
].regnames
;
3387 /* FIXME tweak fpu flag too */
3394 /* Attempt to identify the particular processor model by reading the
3398 mips_read_processor_type ()
3402 prid
= read_register (PRID_REGNUM
);
3404 if ((prid
& ~0xf) == 0x700)
3405 return savestring ("r3041", strlen ("r3041"));
3410 /* Just like reinit_frame_cache, but with the right arguments to be
3411 callable as an sfunc. */
3414 reinit_frame_cache_sfunc (args
, from_tty
, c
)
3417 struct cmd_list_element
*c
;
3419 reinit_frame_cache ();
3423 gdb_print_insn_mips (memaddr
, info
)
3425 disassemble_info
*info
;
3427 mips_extra_func_info_t proc_desc
;
3429 /* Search for the function containing this address. Set the low bit
3430 of the address when searching, in case we were given an even address
3431 that is the start of a 16-bit function. If we didn't do this,
3432 the search would fail because the symbol table says the function
3433 starts at an odd address, i.e. 1 byte past the given address. */
3434 memaddr
= ADDR_BITS_REMOVE (memaddr
);
3435 proc_desc
= non_heuristic_proc_desc (MAKE_MIPS16_ADDR (memaddr
), NULL
);
3437 /* Make an attempt to determine if this is a 16-bit function. If
3438 the procedure descriptor exists and the address therein is odd,
3439 it's definitely a 16-bit function. Otherwise, we have to just
3440 guess that if the address passed in is odd, it's 16-bits. */
3442 info
->mach
= pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)) ? 16 : TM_PRINT_INSN_MACH
;
3444 info
->mach
= pc_is_mips16 (memaddr
) ? 16 : TM_PRINT_INSN_MACH
;
3446 /* Round down the instruction address to the appropriate boundary. */
3447 memaddr
&= (info
->mach
== 16 ? ~1 : ~3);
3449 /* Call the appropriate disassembler based on the target endian-ness. */
3450 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
3451 return print_insn_big_mips (memaddr
, info
);
3453 return print_insn_little_mips (memaddr
, info
);
3456 /* Old-style breakpoint macros.
3457 The IDT board uses an unusual breakpoint value, and sometimes gets
3458 confused when it sees the usual MIPS breakpoint instruction. */
3460 #define BIG_BREAKPOINT {0, 0x5, 0, 0xd}
3461 #define LITTLE_BREAKPOINT {0xd, 0, 0x5, 0}
3462 #define PMON_BIG_BREAKPOINT {0, 0, 0, 0xd}
3463 #define PMON_LITTLE_BREAKPOINT {0xd, 0, 0, 0}
3464 #define IDT_BIG_BREAKPOINT {0, 0, 0x0a, 0xd}
3465 #define IDT_LITTLE_BREAKPOINT {0xd, 0x0a, 0, 0}
3466 #define MIPS16_BIG_BREAKPOINT {0xe8, 0xa5}
3467 #define MIPS16_LITTLE_BREAKPOINT {0xa5, 0xe8}
3469 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
3470 counter value to determine whether a 16- or 32-bit breakpoint should be
3471 used. It returns a pointer to a string of bytes that encode a breakpoint
3472 instruction, stores the length of the string to *lenptr, and adjusts pc
3473 (if necessary) to point to the actual memory location where the
3474 breakpoint should be inserted. */
3477 mips_breakpoint_from_pc (pcptr
, lenptr
)
3481 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
3483 if (pc_is_mips16 (*pcptr
))
3485 static char mips16_big_breakpoint
[] = MIPS16_BIG_BREAKPOINT
;
3486 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
3487 *lenptr
= sizeof (mips16_big_breakpoint
);
3488 return mips16_big_breakpoint
;
3492 static char big_breakpoint
[] = BIG_BREAKPOINT
;
3493 static char pmon_big_breakpoint
[] = PMON_BIG_BREAKPOINT
;
3494 static char idt_big_breakpoint
[] = IDT_BIG_BREAKPOINT
;
3496 *lenptr
= sizeof (big_breakpoint
);
3498 if (strcmp (target_shortname
, "mips") == 0)
3499 return idt_big_breakpoint
;
3500 else if (strcmp (target_shortname
, "ddb") == 0
3501 || strcmp (target_shortname
, "pmon") == 0
3502 || strcmp (target_shortname
, "lsi") == 0)
3503 return pmon_big_breakpoint
;
3505 return big_breakpoint
;
3510 if (pc_is_mips16 (*pcptr
))
3512 static char mips16_little_breakpoint
[] = MIPS16_LITTLE_BREAKPOINT
;
3513 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
3514 *lenptr
= sizeof (mips16_little_breakpoint
);
3515 return mips16_little_breakpoint
;
3519 static char little_breakpoint
[] = LITTLE_BREAKPOINT
;
3520 static char pmon_little_breakpoint
[] = PMON_LITTLE_BREAKPOINT
;
3521 static char idt_little_breakpoint
[] = IDT_LITTLE_BREAKPOINT
;
3523 *lenptr
= sizeof (little_breakpoint
);
3525 if (strcmp (target_shortname
, "mips") == 0)
3526 return idt_little_breakpoint
;
3527 else if (strcmp (target_shortname
, "ddb") == 0
3528 || strcmp (target_shortname
, "pmon") == 0
3529 || strcmp (target_shortname
, "lsi") == 0)
3530 return pmon_little_breakpoint
;
3532 return little_breakpoint
;
3537 /* If PC is in a mips16 call or return stub, return the address of the target
3538 PC, which is either the callee or the caller. There are several
3539 cases which must be handled:
3541 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
3542 target PC is in $31 ($ra).
3543 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
3544 and the target PC is in $2.
3545 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3546 before the jal instruction, this is effectively a call stub
3547 and the the target PC is in $2. Otherwise this is effectively
3548 a return stub and the target PC is in $18.
3550 See the source code for the stubs in gcc/config/mips/mips16.S for
3553 This function implements the SKIP_TRAMPOLINE_CODE macro.
3561 CORE_ADDR start_addr
;
3563 /* Find the starting address and name of the function containing the PC. */
3564 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
3567 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
3568 target PC is in $31 ($ra). */
3569 if (strcmp (name
, "__mips16_ret_sf") == 0
3570 || strcmp (name
, "__mips16_ret_df") == 0)
3571 return read_register (RA_REGNUM
);
3573 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
3575 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
3576 and the target PC is in $2. */
3577 if (name
[19] >= '0' && name
[19] <= '9')
3578 return read_register (2);
3580 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3581 before the jal instruction, this is effectively a call stub
3582 and the the target PC is in $2. Otherwise this is effectively
3583 a return stub and the target PC is in $18. */
3584 else if (name
[19] == 's' || name
[19] == 'd')
3586 if (pc
== start_addr
)
3588 /* Check if the target of the stub is a compiler-generated
3589 stub. Such a stub for a function bar might have a name
3590 like __fn_stub_bar, and might look like this:
3595 la $1,bar (becomes a lui/addiu pair)
3597 So scan down to the lui/addi and extract the target
3598 address from those two instructions. */
3600 CORE_ADDR target_pc
= read_register (2);
3604 /* See if the name of the target function is __fn_stub_*. */
3605 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) == 0)
3607 if (strncmp (name
, "__fn_stub_", 10) != 0
3608 && strcmp (name
, "etext") != 0
3609 && strcmp (name
, "_etext") != 0)
3612 /* Scan through this _fn_stub_ code for the lui/addiu pair.
3613 The limit on the search is arbitrarily set to 20
3614 instructions. FIXME. */
3615 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSTLEN
)
3617 inst
= mips_fetch_instruction (target_pc
);
3618 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
3619 pc
= (inst
<< 16) & 0xffff0000; /* high word */
3620 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
3621 return pc
| (inst
& 0xffff); /* low word */
3624 /* Couldn't find the lui/addui pair, so return stub address. */
3628 /* This is the 'return' part of a call stub. The return
3629 address is in $r18. */
3630 return read_register (18);
3633 return 0; /* not a stub */
3637 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
3638 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
3641 mips_in_call_stub (pc
, name
)
3645 CORE_ADDR start_addr
;
3647 /* Find the starting address of the function containing the PC. If the
3648 caller didn't give us a name, look it up at the same time. */
3649 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) == 0)
3652 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
3654 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
3655 if (name
[19] >= '0' && name
[19] <= '9')
3657 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3658 before the jal instruction, this is effectively a call stub. */
3659 else if (name
[19] == 's' || name
[19] == 'd')
3660 return pc
== start_addr
;
3663 return 0; /* not a stub */
3667 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
3668 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
3671 mips_in_return_stub (pc
, name
)
3675 CORE_ADDR start_addr
;
3677 /* Find the starting address of the function containing the PC. */
3678 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
3681 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
3682 if (strcmp (name
, "__mips16_ret_sf") == 0
3683 || strcmp (name
, "__mips16_ret_df") == 0)
3686 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
3687 i.e. after the jal instruction, this is effectively a return stub. */
3688 if (strncmp (name
, "__mips16_call_stub_", 19) == 0
3689 && (name
[19] == 's' || name
[19] == 'd')
3690 && pc
!= start_addr
)
3693 return 0; /* not a stub */
3697 /* Return non-zero if the PC is in a library helper function that should
3698 be ignored. This implements the IGNORE_HELPER_CALL macro. */
3701 mips_ignore_helper (pc
)
3706 /* Find the starting address and name of the function containing the PC. */
3707 if (find_pc_partial_function (pc
, &name
, NULL
, NULL
) == 0)
3710 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
3711 that we want to ignore. */
3712 return (strcmp (name
, "__mips16_ret_sf") == 0
3713 || strcmp (name
, "__mips16_ret_df") == 0);
3717 /* Return a location where we can set a breakpoint that will be hit
3718 when an inferior function call returns. This is normally the
3719 program's entry point. Executables that don't have an entry
3720 point (e.g. programs in ROM) should define a symbol __CALL_DUMMY_ADDRESS
3721 whose address is the location where the breakpoint should be placed. */
3724 mips_call_dummy_address ()
3726 struct minimal_symbol
*sym
;
3728 sym
= lookup_minimal_symbol ("__CALL_DUMMY_ADDRESS", NULL
, NULL
);
3730 return SYMBOL_VALUE_ADDRESS (sym
);
3732 return entry_point_address ();
3736 /* If the current gcc for for this target does not produce correct debugging
3737 information for float parameters, both prototyped and unprototyped, then
3738 define this macro. This forces gdb to always assume that floats are
3739 passed as doubles and then converted in the callee.
3741 For the mips chip, it appears that the debug info marks the parameters as
3742 floats regardless of whether the function is prototyped, but the actual
3743 values are passed as doubles for the non-prototyped case and floats for
3744 the prototyped case. Thus we choose to make the non-prototyped case work
3745 for C and break the prototyped case, since the non-prototyped case is
3746 probably much more common. (FIXME). */
3749 mips_coerce_float_to_double (struct type
*formal
, struct type
*actual
)
3751 return current_language
->la_language
== language_c
;
3755 static gdbarch_init_ftype mips_gdbarch_init
;
3756 static struct gdbarch
*
3757 mips_gdbarch_init (info
, arches
)
3758 struct gdbarch_info info
;
3759 struct gdbarch_list
*arches
;
3761 static LONGEST mips_call_dummy_words
[] =
3763 struct gdbarch
*gdbarch
;
3764 struct gdbarch_tdep
*tdep
;
3767 int ef_mips_bitptrs
;
3769 enum mips_abi mips_abi
;
3771 /* Extract the elf_flags if available */
3772 if (info
.abfd
!= NULL
3773 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
3774 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
3778 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
3779 switch ((elf_flags
& EF_MIPS_ABI
))
3781 case E_MIPS_ABI_O32
:
3782 mips_abi
= MIPS_ABI_O32
;
3784 case E_MIPS_ABI_O64
:
3785 mips_abi
= MIPS_ABI_O64
;
3787 case E_MIPS_ABI_EABI32
:
3788 mips_abi
= MIPS_ABI_EABI32
;
3790 case E_MIPS_ABI_EABI64
:
3791 mips_abi
= MIPS_ABI_EABI32
;
3794 mips_abi
= MIPS_ABI_UNKNOWN
;
3797 #ifdef MIPS_DEFAULT_ABI
3798 if (mips_abi
== MIPS_ABI_UNKNOWN
)
3799 mips_abi
= MIPS_DEFAULT_ABI
;
3802 /* try to find a pre-existing architecture */
3803 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
3805 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
3807 /* MIPS needs to be pedantic about which ABI the object is
3809 if (gdbarch_tdep (current_gdbarch
)->elf_flags
!= elf_flags
)
3811 if (gdbarch_tdep (current_gdbarch
)->mips_abi
!= mips_abi
)
3813 return arches
->gdbarch
;
3816 /* Need a new architecture. Fill in a target specific vector. */
3817 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
3818 gdbarch
= gdbarch_alloc (&info
, tdep
);
3819 tdep
->elf_flags
= elf_flags
;
3821 /* Initially set everything according to the ABI. */
3822 set_gdbarch_short_bit (gdbarch
, 16);
3823 set_gdbarch_int_bit (gdbarch
, 32);
3824 set_gdbarch_float_bit (gdbarch
, 32);
3825 set_gdbarch_double_bit (gdbarch
, 64);
3826 set_gdbarch_long_double_bit (gdbarch
, 64);
3827 tdep
->mips_abi
= mips_abi
;
3831 ef_mips_abi
= "o32";
3832 tdep
->mips_default_saved_regsize
= 4;
3833 tdep
->mips_default_stack_argsize
= 4;
3834 tdep
->mips_fp_register_double
= 0;
3835 tdep
->mips_last_arg_regnum
= ZERO_REGNUM
+ 7;
3836 tdep
->mips_last_fp_arg_regnum
= FP0_REGNUM
+ 15;
3837 tdep
->mips_regs_have_home_p
= 1;
3838 set_gdbarch_long_bit (gdbarch
, 32);
3839 set_gdbarch_ptr_bit (gdbarch
, 32);
3840 set_gdbarch_long_long_bit (gdbarch
, 64);
3843 ef_mips_abi
= "o64";
3844 tdep
->mips_default_saved_regsize
= 8;
3845 tdep
->mips_default_stack_argsize
= 8;
3846 tdep
->mips_fp_register_double
= 1;
3847 tdep
->mips_last_arg_regnum
= ZERO_REGNUM
+ 7;
3848 tdep
->mips_last_fp_arg_regnum
= FP0_REGNUM
+ 15;
3849 tdep
->mips_regs_have_home_p
= 1;
3850 set_gdbarch_long_bit (gdbarch
, 32);
3851 set_gdbarch_ptr_bit (gdbarch
, 32);
3852 set_gdbarch_long_long_bit (gdbarch
, 64);
3854 case MIPS_ABI_EABI32
:
3855 ef_mips_abi
= "eabi32";
3856 tdep
->mips_default_saved_regsize
= 4;
3857 tdep
->mips_default_stack_argsize
= 4;
3858 tdep
->mips_fp_register_double
= 0;
3859 tdep
->mips_last_arg_regnum
= ZERO_REGNUM
+ 11;
3860 tdep
->mips_last_fp_arg_regnum
= FP0_REGNUM
+ 19;
3861 tdep
->mips_regs_have_home_p
= 0;
3862 set_gdbarch_long_bit (gdbarch
, 32);
3863 set_gdbarch_ptr_bit (gdbarch
, 32);
3864 set_gdbarch_long_long_bit (gdbarch
, 64);
3866 case MIPS_ABI_EABI64
:
3867 ef_mips_abi
= "eabi64";
3868 tdep
->mips_default_saved_regsize
= 8;
3869 tdep
->mips_default_stack_argsize
= 8;
3870 tdep
->mips_fp_register_double
= 1;
3871 tdep
->mips_last_arg_regnum
= ZERO_REGNUM
+ 11;
3872 tdep
->mips_last_fp_arg_regnum
= FP0_REGNUM
+ 19;
3873 tdep
->mips_regs_have_home_p
= 0;
3874 set_gdbarch_long_bit (gdbarch
, 64);
3875 set_gdbarch_ptr_bit (gdbarch
, 64);
3876 set_gdbarch_long_long_bit (gdbarch
, 64);
3879 ef_mips_abi
= "n32";
3880 tdep
->mips_default_saved_regsize
= 4;
3881 tdep
->mips_default_stack_argsize
= 8;
3882 tdep
->mips_fp_register_double
= 1;
3883 tdep
->mips_last_arg_regnum
= ZERO_REGNUM
+ 11;
3884 tdep
->mips_last_fp_arg_regnum
= FP0_REGNUM
+ 19;
3885 tdep
->mips_regs_have_home_p
= 0;
3886 set_gdbarch_long_bit (gdbarch
, 32);
3887 set_gdbarch_ptr_bit (gdbarch
, 32);
3888 set_gdbarch_long_long_bit (gdbarch
, 64);
3891 ef_mips_abi
= "default";
3892 tdep
->mips_default_saved_regsize
= MIPS_REGSIZE
;
3893 tdep
->mips_default_stack_argsize
= MIPS_REGSIZE
;
3894 tdep
->mips_fp_register_double
= (REGISTER_VIRTUAL_SIZE (FP0_REGNUM
) == 8);
3895 tdep
->mips_last_arg_regnum
= ZERO_REGNUM
+ 11;
3896 tdep
->mips_last_fp_arg_regnum
= FP0_REGNUM
+ 19;
3897 tdep
->mips_regs_have_home_p
= 1;
3898 set_gdbarch_long_bit (gdbarch
, 32);
3899 set_gdbarch_ptr_bit (gdbarch
, 32);
3900 set_gdbarch_long_long_bit (gdbarch
, 64);
3904 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
3905 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
3908 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
3909 flag in object files because to do so would make it impossible to
3910 link with libraries compiled without "-gp32". This is
3911 unnecessarily restrictive.
3913 We could solve this problem by adding "-gp32" multilibs to gcc,
3914 but to set this flag before gcc is built with such multilibs will
3915 break too many systems.''
3917 But even more unhelpfully, the default linker output target for
3918 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
3919 for 64-bit programs - you need to change the ABI to change this,
3920 and not all gcc targets support that currently. Therefore using
3921 this flag to detect 32-bit mode would do the wrong thing given
3922 the current gcc - it would make GDB treat these 64-bit programs
3923 as 32-bit programs by default. */
3925 /* determine the ISA */
3926 switch (elf_flags
& EF_MIPS_ARCH
)
3945 /* determine the size of a pointer */
3946 if ((elf_flags
& EF_MIPS_32BITPTRS
))
3948 ef_mips_bitptrs
= 32;
3950 else if ((elf_flags
& EF_MIPS_64BITPTRS
))
3952 ef_mips_bitptrs
= 64;
3956 ef_mips_bitptrs
= 0;
3960 /* enable/disable the MIPS FPU */
3961 if (!mips_fpu_type_auto
)
3962 tdep
->mips_fpu_type
= mips_fpu_type
;
3963 else if (info
.bfd_arch_info
!= NULL
3964 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
3965 switch (info
.bfd_arch_info
->mach
)
3967 case bfd_mach_mips4100
:
3968 case bfd_mach_mips4111
:
3969 tdep
->mips_fpu_type
= MIPS_FPU_NONE
;
3972 tdep
->mips_fpu_type
= MIPS_FPU_DOUBLE
;
3976 tdep
->mips_fpu_type
= MIPS_FPU_DOUBLE
;
3978 /* MIPS version of register names. NOTE: At present the MIPS
3979 register name management is part way between the old -
3980 #undef/#define REGISTER_NAMES and the new REGISTER_NAME(nr).
3981 Further work on it is required. */
3982 set_gdbarch_register_name (gdbarch
, mips_register_name
);
3983 set_gdbarch_read_pc (gdbarch
, generic_target_read_pc
);
3984 set_gdbarch_write_pc (gdbarch
, generic_target_write_pc
);
3985 set_gdbarch_read_fp (gdbarch
, generic_target_read_fp
);
3986 set_gdbarch_write_fp (gdbarch
, generic_target_write_fp
);
3987 set_gdbarch_read_sp (gdbarch
, generic_target_read_sp
);
3988 set_gdbarch_write_sp (gdbarch
, generic_target_write_sp
);
3990 /* Initialize a frame */
3991 set_gdbarch_init_extra_frame_info (gdbarch
, mips_init_extra_frame_info
);
3993 /* MIPS version of CALL_DUMMY */
3995 set_gdbarch_call_dummy_p (gdbarch
, 1);
3996 set_gdbarch_call_dummy_stack_adjust_p (gdbarch
, 0);
3997 set_gdbarch_use_generic_dummy_frames (gdbarch
, 0);
3998 set_gdbarch_call_dummy_location (gdbarch
, AT_ENTRY_POINT
);
3999 set_gdbarch_call_dummy_address (gdbarch
, mips_call_dummy_address
);
4000 set_gdbarch_call_dummy_start_offset (gdbarch
, 0);
4001 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch
, 1);
4002 set_gdbarch_call_dummy_breakpoint_offset (gdbarch
, 0);
4003 set_gdbarch_call_dummy_length (gdbarch
, 0);
4004 set_gdbarch_pc_in_call_dummy (gdbarch
, pc_in_call_dummy_at_entry_point
);
4005 set_gdbarch_call_dummy_words (gdbarch
, mips_call_dummy_words
);
4006 set_gdbarch_sizeof_call_dummy_words (gdbarch
, sizeof (mips_call_dummy_words
));
4007 set_gdbarch_push_return_address (gdbarch
, mips_push_return_address
);
4008 set_gdbarch_push_arguments (gdbarch
, mips_push_arguments
);
4009 set_gdbarch_register_convertible (gdbarch
, generic_register_convertible_not
);
4010 set_gdbarch_coerce_float_to_double (gdbarch
, mips_coerce_float_to_double
);
4012 set_gdbarch_frame_chain_valid (gdbarch
, func_frame_chain_valid
);
4013 set_gdbarch_get_saved_register (gdbarch
, default_get_saved_register
);
4017 fprintf_unfiltered (gdb_stdlog
,
4018 "mips_gdbarch_init: (info)ef_mips_abi = %s\n",
4020 fprintf_unfiltered (gdb_stdlog
,
4021 "mips_gdbarch_init: (info)ef_mips_arch = %d\n",
4023 fprintf_unfiltered (gdb_stdlog
,
4024 "mips_gdbarch_init: (info)ef_mips_bitptrs = %d\n",
4026 fprintf_unfiltered (gdb_stdlog
,
4027 "mips_gdbarch_init: MIPS_REGSIZE = %d\n",
4029 fprintf_unfiltered (gdb_stdlog
,
4030 "mips_gdbarch_init: tdep->elf_flags = 0x%x\n",
4032 fprintf_unfiltered (gdb_stdlog
,
4033 "mips_gdbarch_init: tdep->mips_abi = %d\n",
4035 fprintf_unfiltered (gdb_stdlog
,
4036 "mips_gdbarch_init: tdep->mips_fpu_type = %d (%s)\n",
4037 tdep
->mips_fpu_type
,
4038 (tdep
->mips_fpu_type
== MIPS_FPU_NONE
? "none"
4039 : tdep
->mips_fpu_type
== MIPS_FPU_SINGLE
? "single"
4040 : tdep
->mips_fpu_type
== MIPS_FPU_DOUBLE
? "double"
4042 fprintf_unfiltered (gdb_stdlog
,
4043 "mips_gdbarch_init: tdep->mips_last_arg_regnum = %d\n",
4044 tdep
->mips_last_arg_regnum
);
4045 fprintf_unfiltered (gdb_stdlog
,
4046 "mips_gdbarch_init: tdep->mips_last_fp_arg_regnum = %d (%d)\n",
4047 tdep
->mips_last_fp_arg_regnum
,
4048 tdep
->mips_last_fp_arg_regnum
- FP0_REGNUM
);
4049 fprintf_unfiltered (gdb_stdlog
,
4050 "mips_gdbarch_init: tdep->mips_default_saved_regsize = %d\n",
4051 tdep
->mips_default_saved_regsize
);
4052 fprintf_unfiltered (gdb_stdlog
,
4053 "mips_gdbarch_init: tdep->mips_fp_register_double = %d (%s)\n",
4054 tdep
->mips_fp_register_double
,
4055 (tdep
->mips_fp_register_double
? "true" : "false"));
4056 fprintf_unfiltered (gdb_stdlog
,
4057 "mips_gdbarch_init: tdep->mips_regs_have_home_p = %d\n",
4058 tdep
->mips_regs_have_home_p
);
4059 fprintf_unfiltered (gdb_stdlog
,
4060 "mips_gdbarch_init: tdep->mips_default_stack_argsize = %d\n",
4061 tdep
->mips_default_stack_argsize
);
4069 _initialize_mips_tdep ()
4071 static struct cmd_list_element
*mipsfpulist
= NULL
;
4072 struct cmd_list_element
*c
;
4075 register_gdbarch_init (bfd_arch_mips
, mips_gdbarch_init
);
4076 if (!tm_print_insn
) /* Someone may have already set it */
4077 tm_print_insn
= gdb_print_insn_mips
;
4079 /* Add root prefix command for all "set mips"/"show mips" commands */
4080 add_prefix_cmd ("mips", no_class
, set_mips_command
,
4081 "Various MIPS specific commands.",
4082 &setmipscmdlist
, "set mips ", 0, &setlist
);
4084 add_prefix_cmd ("mips", no_class
, show_mips_command
,
4085 "Various MIPS specific commands.",
4086 &showmipscmdlist
, "show mips ", 0, &showlist
);
4088 /* Allow the user to override the saved register size. */
4089 add_show_from_set (add_set_enum_cmd ("saved-gpreg-size",
4092 (char *) &mips_saved_regsize_string
, "\
4093 Set size of general purpose registers saved on the stack.\n\
4094 This option can be set to one of:\n\
4095 32 - Force GDB to treat saved GP registers as 32-bit\n\
4096 64 - Force GDB to treat saved GP registers as 64-bit\n\
4097 auto - Allow GDB to use the target's default setting or autodetect the\n\
4098 saved GP register size from information contained in the executable.\n\
4103 /* Allow the user to override the argument stack size. */
4104 add_show_from_set (add_set_enum_cmd ("stack-arg-size",
4107 (char *) &mips_stack_argsize_string
, "\
4108 Set the amount of stack space reserved for each argument.\n\
4109 This option can be set to one of:\n\
4110 32 - Force GDB to allocate 32-bit chunks per argument\n\
4111 64 - Force GDB to allocate 64-bit chunks per argument\n\
4112 auto - Allow GDB to determine the correct setting from the current\n\
4113 target and executable (default)",
4117 /* Let the user turn off floating point and set the fence post for
4118 heuristic_proc_start. */
4120 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
4121 "Set use of MIPS floating-point coprocessor.",
4122 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
4123 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
4124 "Select single-precision MIPS floating-point coprocessor.",
4126 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
4127 "Select double-precision MIPS floating-point coprocessor .",
4129 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
4130 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
4131 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
4132 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
4133 "Select no MIPS floating-point coprocessor.",
4135 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
4136 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
4137 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
4138 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
4139 "Select MIPS floating-point coprocessor automatically.",
4141 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
4142 "Show current use of MIPS floating-point coprocessor target.",
4146 c
= add_set_cmd ("processor", class_support
, var_string_noescape
,
4147 (char *) &tmp_mips_processor_type
,
4148 "Set the type of MIPS processor in use.\n\
4149 Set this to be able to access processor-type-specific registers.\n\
4152 c
->function
.cfunc
= mips_set_processor_type_command
;
4153 c
= add_show_from_set (c
, &showlist
);
4154 c
->function
.cfunc
= mips_show_processor_type_command
;
4156 tmp_mips_processor_type
= strsave (DEFAULT_MIPS_TYPE
);
4157 mips_set_processor_type_command (strsave (DEFAULT_MIPS_TYPE
), 0);
4160 /* We really would like to have both "0" and "unlimited" work, but
4161 command.c doesn't deal with that. So make it a var_zinteger
4162 because the user can always use "999999" or some such for unlimited. */
4163 c
= add_set_cmd ("heuristic-fence-post", class_support
, var_zinteger
,
4164 (char *) &heuristic_fence_post
,
4166 Set the distance searched for the start of a function.\n\
4167 If you are debugging a stripped executable, GDB needs to search through the\n\
4168 program for the start of a function. This command sets the distance of the\n\
4169 search. The only need to set it is when debugging a stripped executable.",
4171 /* We need to throw away the frame cache when we set this, since it
4172 might change our ability to get backtraces. */
4173 c
->function
.sfunc
= reinit_frame_cache_sfunc
;
4174 add_show_from_set (c
, &showlist
);
4176 /* Allow the user to control whether the upper bits of 64-bit
4177 addresses should be zeroed. */
4179 (add_set_cmd ("mask-address", no_class
, var_boolean
, (char *) &mask_address_p
,
4180 "Set zeroing of upper 32 bits of 64-bit addresses.\n\
4181 Use \"on\" to enable the masking, and \"off\" to disable it.\n\
4182 Without an argument, zeroing of upper address bits is enabled.", &setlist
),
4185 /* Allow the user to control the size of 32 bit registers within the
4186 raw remote packet. */
4187 add_show_from_set (add_set_cmd ("remote-mips64-transfers-32bit-regs",
4190 (char *)&mips64_transfers_32bit_regs_p
, "\
4191 Set compatibility with MIPS targets that transfers 32 and 64 bit quantities.\n\
4192 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
4193 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
4194 64 bits for others. Use \"off\" to disable compatibility mode",