1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software
7 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
8 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
10 This file is part of GDB.
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the Free Software
24 Foundation, Inc., 59 Temple Place - Suite 330,
25 Boston, MA 02111-1307, USA. */
28 #include "gdb_string.h"
29 #include "gdb_assert.h"
41 #include "arch-utils.h"
44 #include "mips-tdep.h"
46 #include "reggroups.h"
47 #include "opcode/mips.h"
51 #include "sim-regno.h"
53 #include "frame-unwind.h"
54 #include "frame-base.h"
55 #include "trad-frame.h"
57 static const struct objfile_data
*mips_pdr_data
;
59 static void set_reg_offset (CORE_ADDR
*saved_regs
, int regnum
, CORE_ADDR off
);
60 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
62 /* A useful bit in the CP0 status register (PS_REGNUM). */
63 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
64 #define ST0_FR (1 << 26)
66 /* The sizes of floating point registers. */
70 MIPS_FPU_SINGLE_REGSIZE
= 4,
71 MIPS_FPU_DOUBLE_REGSIZE
= 8
75 static const char *mips_abi_string
;
77 static const char *mips_abi_strings
[] = {
88 struct frame_extra_info
90 mips_extra_func_info_t proc_desc
;
94 /* Various MIPS ISA options (related to stack analysis) can be
95 overridden dynamically. Establish an enum/array for managing
98 static const char size_auto
[] = "auto";
99 static const char size_32
[] = "32";
100 static const char size_64
[] = "64";
102 static const char *size_enums
[] = {
109 /* Some MIPS boards don't support floating point while others only
110 support single-precision floating-point operations. See also
111 FP_REGISTER_DOUBLE. */
115 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
116 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
117 MIPS_FPU_NONE
/* No floating point. */
120 #ifndef MIPS_DEFAULT_FPU_TYPE
121 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
123 static int mips_fpu_type_auto
= 1;
124 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
126 static int mips_debug
= 0;
128 /* MIPS specific per-architecture information */
131 /* from the elf header */
135 enum mips_abi mips_abi
;
136 enum mips_abi found_abi
;
137 enum mips_fpu_type mips_fpu_type
;
138 int mips_last_arg_regnum
;
139 int mips_last_fp_arg_regnum
;
140 int mips_default_abi_regsize
;
141 int mips_fp_register_double
;
142 int mips_default_stack_argsize
;
143 int default_mask_address_p
;
144 /* Is the target using 64-bit raw integer registers but only
145 storing a left-aligned 32-bit value in each? */
146 int mips64_transfers_32bit_regs_p
;
147 /* Indexes for various registers. IRIX and embedded have
148 different values. This contains the "public" fields. Don't
149 add any that do not need to be public. */
150 const struct mips_regnum
*regnum
;
151 /* Register names table for the current register set. */
152 const char **mips_processor_reg_names
;
155 const struct mips_regnum
*
156 mips_regnum (struct gdbarch
*gdbarch
)
158 return gdbarch_tdep (gdbarch
)->regnum
;
162 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
164 return mips_regnum (gdbarch
)->fp0
+ 12;
167 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
168 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
170 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
172 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
174 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
176 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
177 functions to test, set, or clear bit 0 of addresses. */
180 is_mips16_addr (CORE_ADDR addr
)
186 make_mips16_addr (CORE_ADDR addr
)
192 unmake_mips16_addr (CORE_ADDR addr
)
194 return ((addr
) & ~1);
197 /* Return the contents of register REGNUM as a signed integer. */
200 read_signed_register (int regnum
)
202 void *buf
= alloca (register_size (current_gdbarch
, regnum
));
203 deprecated_read_register_gen (regnum
, buf
);
204 return (extract_signed_integer
205 (buf
, register_size (current_gdbarch
, regnum
)));
209 read_signed_register_pid (int regnum
, ptid_t ptid
)
214 if (ptid_equal (ptid
, inferior_ptid
))
215 return read_signed_register (regnum
);
217 save_ptid
= inferior_ptid
;
219 inferior_ptid
= ptid
;
221 retval
= read_signed_register (regnum
);
223 inferior_ptid
= save_ptid
;
228 /* Return the MIPS ABI associated with GDBARCH. */
230 mips_abi (struct gdbarch
*gdbarch
)
232 return gdbarch_tdep (gdbarch
)->mips_abi
;
236 mips_isa_regsize (struct gdbarch
*gdbarch
)
238 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
239 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
242 /* Return the currently configured (or set) saved register size. */
244 static const char *mips_abi_regsize_string
= size_auto
;
247 mips_abi_regsize (struct gdbarch_tdep
*tdep
)
249 if (mips_abi_regsize_string
== size_auto
)
250 return tdep
->mips_default_abi_regsize
;
251 else if (mips_abi_regsize_string
== size_64
)
253 else /* if (mips_abi_regsize_string == size_32) */
257 /* Functions for setting and testing a bit in a minimal symbol that
258 marks it as 16-bit function. The MSB of the minimal symbol's
259 "info" field is used for this purpose.
261 ELF_MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special",
262 i.e. refers to a 16-bit function, and sets a "special" bit in a
263 minimal symbol to mark it as a 16-bit function
265 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
268 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
270 if (((elf_symbol_type
*) (sym
))->internal_elf_sym
.st_other
== STO_MIPS16
)
272 MSYMBOL_INFO (msym
) = (char *)
273 (((long) MSYMBOL_INFO (msym
)) | 0x80000000);
274 SYMBOL_VALUE_ADDRESS (msym
) |= 1;
279 msymbol_is_special (struct minimal_symbol
*msym
)
281 return (((long) MSYMBOL_INFO (msym
) & 0x80000000) != 0);
284 /* XFER a value from the big/little/left end of the register.
285 Depending on the size of the value it might occupy the entire
286 register or just part of it. Make an allowance for this, aligning
287 things accordingly. */
290 mips_xfer_register (struct regcache
*regcache
, int reg_num
, int length
,
291 enum bfd_endian endian
, bfd_byte
* in
,
292 const bfd_byte
* out
, int buf_offset
)
295 gdb_assert (reg_num
>= NUM_REGS
);
296 /* Need to transfer the left or right part of the register, based on
297 the targets byte order. */
301 reg_offset
= register_size (current_gdbarch
, reg_num
) - length
;
303 case BFD_ENDIAN_LITTLE
:
306 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
310 internal_error (__FILE__
, __LINE__
, "bad switch");
313 fprintf_unfiltered (gdb_stderr
,
314 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
315 reg_num
, reg_offset
, buf_offset
, length
);
316 if (mips_debug
&& out
!= NULL
)
319 fprintf_unfiltered (gdb_stdlog
, "out ");
320 for (i
= 0; i
< length
; i
++)
321 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
324 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
327 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
329 if (mips_debug
&& in
!= NULL
)
332 fprintf_unfiltered (gdb_stdlog
, "in ");
333 for (i
= 0; i
< length
; i
++)
334 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
337 fprintf_unfiltered (gdb_stdlog
, "\n");
340 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
341 compatiblity mode. A return value of 1 means that we have
342 physical 64-bit registers, but should treat them as 32-bit registers. */
345 mips2_fp_compat (void)
347 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
349 if (register_size (current_gdbarch
, mips_regnum (current_gdbarch
)->fp0
) ==
354 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
355 in all the places we deal with FP registers. PR gdb/413. */
356 /* Otherwise check the FR bit in the status register - it controls
357 the FP compatiblity mode. If it is clear we are in compatibility
359 if ((read_register (PS_REGNUM
) & ST0_FR
) == 0)
366 /* Indicate that the ABI makes use of double-precision registers
367 provided by the FPU (rather than combining pairs of registers to
368 form double-precision values). See also MIPS_FPU_TYPE. */
369 #define FP_REGISTER_DOUBLE (gdbarch_tdep (current_gdbarch)->mips_fp_register_double)
371 /* The amount of space reserved on the stack for registers. This is
372 different to MIPS_ABI_REGSIZE as it determines the alignment of
373 data allocated after the registers have run out. */
375 static const char *mips_stack_argsize_string
= size_auto
;
378 mips_stack_argsize (struct gdbarch_tdep
*tdep
)
380 if (mips_stack_argsize_string
== size_auto
)
381 return tdep
->mips_default_stack_argsize
;
382 else if (mips_stack_argsize_string
== size_64
)
384 else /* if (mips_stack_argsize_string == size_32) */
388 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
390 static mips_extra_func_info_t
heuristic_proc_desc (CORE_ADDR
, CORE_ADDR
,
391 struct frame_info
*, int);
393 static CORE_ADDR
heuristic_proc_start (CORE_ADDR
);
395 static CORE_ADDR
read_next_frame_reg (struct frame_info
*, int);
397 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
399 static mips_extra_func_info_t
find_proc_desc (CORE_ADDR pc
,
400 struct frame_info
*next_frame
,
403 static CORE_ADDR
after_prologue (CORE_ADDR pc
,
404 mips_extra_func_info_t proc_desc
);
406 static struct type
*mips_float_register_type (void);
407 static struct type
*mips_double_register_type (void);
409 /* The list of available "set mips " and "show mips " commands */
411 static struct cmd_list_element
*setmipscmdlist
= NULL
;
412 static struct cmd_list_element
*showmipscmdlist
= NULL
;
414 /* Integer registers 0 thru 31 are handled explicitly by
415 mips_register_name(). Processor specific registers 32 and above
416 are listed in the followign tables. */
419 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
423 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
424 "sr", "lo", "hi", "bad", "cause", "pc",
425 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
426 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
427 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
428 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
429 "fsr", "fir", "" /*"fp" */ , "",
430 "", "", "", "", "", "", "", "",
431 "", "", "", "", "", "", "", "",
434 /* Names of IDT R3041 registers. */
436 static const char *mips_r3041_reg_names
[] = {
437 "sr", "lo", "hi", "bad", "cause", "pc",
438 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
439 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
440 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
441 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
442 "fsr", "fir", "", /*"fp" */ "",
443 "", "", "bus", "ccfg", "", "", "", "",
444 "", "", "port", "cmp", "", "", "epc", "prid",
447 /* Names of tx39 registers. */
449 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
450 "sr", "lo", "hi", "bad", "cause", "pc",
451 "", "", "", "", "", "", "", "",
452 "", "", "", "", "", "", "", "",
453 "", "", "", "", "", "", "", "",
454 "", "", "", "", "", "", "", "",
456 "", "", "", "", "", "", "", "",
457 "", "", "config", "cache", "debug", "depc", "epc", ""
460 /* Names of IRIX registers. */
461 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
462 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
463 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
464 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
465 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
466 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
470 /* Return the name of the register corresponding to REGNO. */
472 mips_register_name (int regno
)
474 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
475 /* GPR names for all ABIs other than n32/n64. */
476 static char *mips_gpr_names
[] = {
477 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
478 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
479 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
480 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
483 /* GPR names for n32 and n64 ABIs. */
484 static char *mips_n32_n64_gpr_names
[] = {
485 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
486 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
487 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
488 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
491 enum mips_abi abi
= mips_abi (current_gdbarch
);
493 /* Map [NUM_REGS .. 2*NUM_REGS) onto the raw registers, but then
494 don't make the raw register names visible. */
495 int rawnum
= regno
% NUM_REGS
;
496 if (regno
< NUM_REGS
)
499 /* The MIPS integer registers are always mapped from 0 to 31. The
500 names of the registers (which reflects the conventions regarding
501 register use) vary depending on the ABI. */
502 if (0 <= rawnum
&& rawnum
< 32)
504 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
505 return mips_n32_n64_gpr_names
[rawnum
];
507 return mips_gpr_names
[rawnum
];
509 else if (32 <= rawnum
&& rawnum
< NUM_REGS
)
511 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
512 return tdep
->mips_processor_reg_names
[rawnum
- 32];
515 internal_error (__FILE__
, __LINE__
,
516 "mips_register_name: bad register number %d", rawnum
);
519 /* Return the groups that a MIPS register can be categorised into. */
522 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
523 struct reggroup
*reggroup
)
528 int rawnum
= regnum
% NUM_REGS
;
529 int pseudo
= regnum
/ NUM_REGS
;
530 if (reggroup
== all_reggroup
)
532 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
533 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
534 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
535 (gdbarch), as not all architectures are multi-arch. */
536 raw_p
= rawnum
< NUM_REGS
;
537 if (REGISTER_NAME (regnum
) == NULL
|| REGISTER_NAME (regnum
)[0] == '\0')
539 if (reggroup
== float_reggroup
)
540 return float_p
&& pseudo
;
541 if (reggroup
== vector_reggroup
)
542 return vector_p
&& pseudo
;
543 if (reggroup
== general_reggroup
)
544 return (!vector_p
&& !float_p
) && pseudo
;
545 /* Save the pseudo registers. Need to make certain that any code
546 extracting register values from a saved register cache also uses
548 if (reggroup
== save_reggroup
)
549 return raw_p
&& pseudo
;
550 /* Restore the same pseudo register. */
551 if (reggroup
== restore_reggroup
)
552 return raw_p
&& pseudo
;
556 /* Map the symbol table registers which live in the range [1 *
557 NUM_REGS .. 2 * NUM_REGS) back onto the corresponding raw
558 registers. Take care of alignment and size problems. */
561 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
562 int cookednum
, void *buf
)
564 int rawnum
= cookednum
% NUM_REGS
;
565 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
566 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
567 regcache_raw_read (regcache
, rawnum
, buf
);
568 else if (register_size (gdbarch
, rawnum
) >
569 register_size (gdbarch
, cookednum
))
571 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
572 || TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
573 regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
575 regcache_raw_read_part (regcache
, rawnum
, 4, 4, buf
);
578 internal_error (__FILE__
, __LINE__
, "bad register size");
582 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
583 struct regcache
*regcache
, int cookednum
,
586 int rawnum
= cookednum
% NUM_REGS
;
587 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
588 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
589 regcache_raw_write (regcache
, rawnum
, buf
);
590 else if (register_size (gdbarch
, rawnum
) >
591 register_size (gdbarch
, cookednum
))
593 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
594 || TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
595 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
597 regcache_raw_write_part (regcache
, rawnum
, 4, 4, buf
);
600 internal_error (__FILE__
, __LINE__
, "bad register size");
603 /* Table to translate MIPS16 register field to actual register number. */
604 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
606 /* Heuristic_proc_start may hunt through the text section for a long
607 time across a 2400 baud serial line. Allows the user to limit this
610 static unsigned int heuristic_fence_post
= 0;
612 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
613 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
614 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
615 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
616 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
617 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
618 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
619 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
620 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
621 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
622 /* FIXME drow/2002-06-10: If a pointer on the host is bigger than a long,
623 this will corrupt pdr.iline. Fortunately we don't use it. */
624 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
625 #define _PROC_MAGIC_ 0x0F0F0F0F
626 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
627 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
629 struct linked_proc_info
631 struct mips_extra_func_info info
;
632 struct linked_proc_info
*next
;
634 *linked_proc_desc_table
= NULL
;
636 /* Number of bytes of storage in the actual machine representation for
637 register N. NOTE: This defines the pseudo register type so need to
638 rebuild the architecture vector. */
640 static int mips64_transfers_32bit_regs_p
= 0;
643 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
644 struct cmd_list_element
*c
)
646 struct gdbarch_info info
;
647 gdbarch_info_init (&info
);
648 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
649 instead of relying on globals. Doing that would let generic code
650 handle the search for this specific architecture. */
651 if (!gdbarch_update_p (info
))
653 mips64_transfers_32bit_regs_p
= 0;
654 error ("32-bit compatibility mode not supported");
658 /* Convert to/from a register and the corresponding memory value. */
661 mips_convert_register_p (int regnum
, struct type
*type
)
663 return (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
664 && register_size (current_gdbarch
, regnum
) == 4
665 && (regnum
% NUM_REGS
) >= mips_regnum (current_gdbarch
)->fp0
666 && (regnum
% NUM_REGS
) < mips_regnum (current_gdbarch
)->fp0
+ 32
667 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
671 mips_register_to_value (struct frame_info
*frame
, int regnum
,
672 struct type
*type
, void *to
)
674 get_frame_register (frame
, regnum
+ 0, (char *) to
+ 4);
675 get_frame_register (frame
, regnum
+ 1, (char *) to
+ 0);
679 mips_value_to_register (struct frame_info
*frame
, int regnum
,
680 struct type
*type
, const void *from
)
682 put_frame_register (frame
, regnum
+ 0, (const char *) from
+ 4);
683 put_frame_register (frame
, regnum
+ 1, (const char *) from
+ 0);
686 /* Return the GDB type object for the "standard" data type of data in
690 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
692 gdb_assert (regnum
>= 0 && regnum
< 2 * NUM_REGS
);
693 if ((regnum
% NUM_REGS
) >= mips_regnum (current_gdbarch
)->fp0
694 && (regnum
% NUM_REGS
) < mips_regnum (current_gdbarch
)->fp0
+ 32)
696 /* The floating-point registers raw, or cooked, always match
697 mips_isa_regsize(), and also map 1:1, byte for byte. */
698 switch (gdbarch_byte_order (gdbarch
))
701 if (mips_isa_regsize (gdbarch
) == 4)
702 return builtin_type_ieee_single_big
;
704 return builtin_type_ieee_double_big
;
705 case BFD_ENDIAN_LITTLE
:
706 if (mips_isa_regsize (gdbarch
) == 4)
707 return builtin_type_ieee_single_little
;
709 return builtin_type_ieee_double_little
;
710 case BFD_ENDIAN_UNKNOWN
:
712 internal_error (__FILE__
, __LINE__
, "bad switch");
716 (NUM_REGS
+ mips_regnum (current_gdbarch
)->fp_control_status
)
717 && regnum
<= NUM_REGS
+ LAST_EMBED_REGNUM
)
718 /* The pseudo/cooked view of the embedded registers is always
719 32-bit. The raw view is handled below. */
720 return builtin_type_int32
;
721 else if (regnum
>= NUM_REGS
&& mips_isa_regsize (gdbarch
)
722 && gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
723 /* The target, while using a 64-bit register buffer, is only
724 transfering 32-bits of each integer register. Reflect this in
725 the cooked/pseudo register value. */
726 return builtin_type_int32
;
727 else if (mips_isa_regsize (gdbarch
) == 8)
729 return builtin_type_int64
;
732 return builtin_type_int32
;
735 /* TARGET_READ_SP -- Remove useless bits from the stack pointer. */
740 return read_signed_register (SP_REGNUM
);
743 /* Should the upper word of 64-bit addresses be zeroed? */
744 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
747 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
749 switch (mask_address_var
)
751 case AUTO_BOOLEAN_TRUE
:
753 case AUTO_BOOLEAN_FALSE
:
756 case AUTO_BOOLEAN_AUTO
:
757 return tdep
->default_mask_address_p
;
759 internal_error (__FILE__
, __LINE__
, "mips_mask_address_p: bad switch");
765 show_mask_address (char *cmd
, int from_tty
, struct cmd_list_element
*c
)
767 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
768 switch (mask_address_var
)
770 case AUTO_BOOLEAN_TRUE
:
771 printf_filtered ("The 32 bit mips address mask is enabled\n");
773 case AUTO_BOOLEAN_FALSE
:
774 printf_filtered ("The 32 bit mips address mask is disabled\n");
776 case AUTO_BOOLEAN_AUTO
:
778 ("The 32 bit address mask is set automatically. Currently %s\n",
779 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
782 internal_error (__FILE__
, __LINE__
, "show_mask_address: bad switch");
787 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
790 pc_is_mips16 (bfd_vma memaddr
)
792 struct minimal_symbol
*sym
;
794 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
795 if (is_mips16_addr (memaddr
))
798 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
799 the high bit of the info field. Use this to decide if the function is
800 MIPS16 or normal MIPS. */
801 sym
= lookup_minimal_symbol_by_pc (memaddr
);
803 return msymbol_is_special (sym
);
808 /* MIPS believes that the PC has a sign extended value. Perhaphs the
809 all registers should be sign extended for simplicity? */
812 mips_read_pc (ptid_t ptid
)
814 return read_signed_register_pid (mips_regnum (current_gdbarch
)->pc
, ptid
);
818 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
820 return frame_unwind_register_signed (next_frame
,
821 NUM_REGS
+ mips_regnum (gdbarch
)->pc
);
824 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
825 dummy frame. The frame ID's base needs to match the TOS value
826 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
829 static struct frame_id
830 mips_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
832 return frame_id_build (frame_unwind_register_signed (next_frame
, NUM_REGS
+ SP_REGNUM
),
833 frame_pc_unwind (next_frame
));
837 mips_write_pc (CORE_ADDR pc
, ptid_t ptid
)
839 write_register_pid (mips_regnum (current_gdbarch
)->pc
, pc
, ptid
);
842 /* This returns the PC of the first inst after the prologue. If we can't
843 find the prologue, then return 0. */
846 after_prologue (CORE_ADDR pc
, mips_extra_func_info_t proc_desc
)
848 struct symtab_and_line sal
;
849 CORE_ADDR func_addr
, func_end
;
851 /* Pass cur_frame == 0 to find_proc_desc. We should not attempt
852 to read the stack pointer from the current machine state, because
853 the current machine state has nothing to do with the information
854 we need from the proc_desc; and the process may or may not exist
857 proc_desc
= find_proc_desc (pc
, NULL
, 0);
861 /* If function is frameless, then we need to do it the hard way. I
862 strongly suspect that frameless always means prologueless... */
863 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
864 && PROC_FRAME_OFFSET (proc_desc
) == 0)
868 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
869 return 0; /* Unknown */
871 sal
= find_pc_line (func_addr
, 0);
873 if (sal
.end
< func_end
)
876 /* The line after the prologue is after the end of the function. In this
877 case, tell the caller to find the prologue the hard way. */
882 /* Decode a MIPS32 instruction that saves a register in the stack, and
883 set the appropriate bit in the general register mask or float register mask
884 to indicate which register is saved. This is a helper function
885 for mips_find_saved_regs. */
888 mips32_decode_reg_save (t_inst inst
, unsigned long *gen_mask
,
889 unsigned long *float_mask
)
893 if ((inst
& 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
894 || (inst
& 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
895 || (inst
& 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
897 /* It might be possible to use the instruction to
898 find the offset, rather than the code below which
899 is based on things being in a certain order in the
900 frame, but figuring out what the instruction's offset
901 is relative to might be a little tricky. */
902 reg
= (inst
& 0x001f0000) >> 16;
903 *gen_mask
|= (1 << reg
);
905 else if ((inst
& 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
906 || (inst
& 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
907 || (inst
& 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */
910 reg
= ((inst
& 0x001f0000) >> 16);
911 *float_mask
|= (1 << reg
);
915 /* Decode a MIPS16 instruction that saves a register in the stack, and
916 set the appropriate bit in the general register or float register mask
917 to indicate which register is saved. This is a helper function
918 for mips_find_saved_regs. */
921 mips16_decode_reg_save (t_inst inst
, unsigned long *gen_mask
)
923 if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
925 int reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
926 *gen_mask
|= (1 << reg
);
928 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
930 int reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
931 *gen_mask
|= (1 << reg
);
933 else if ((inst
& 0xff00) == 0x6200 /* sw $ra,n($sp) */
934 || (inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
935 *gen_mask
|= (1 << RA_REGNUM
);
939 /* Fetch and return instruction from the specified location. If the PC
940 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
943 mips_fetch_instruction (CORE_ADDR addr
)
945 char buf
[MIPS_INSTLEN
];
949 if (pc_is_mips16 (addr
))
951 instlen
= MIPS16_INSTLEN
;
952 addr
= unmake_mips16_addr (addr
);
955 instlen
= MIPS_INSTLEN
;
956 status
= read_memory_nobpt (addr
, buf
, instlen
);
958 memory_error (status
, addr
);
959 return extract_unsigned_integer (buf
, instlen
);
963 mips16_fetch_instruction (CORE_ADDR addr
)
965 char buf
[MIPS_INSTLEN
];
969 instlen
= MIPS16_INSTLEN
;
970 addr
= unmake_mips16_addr (addr
);
971 status
= read_memory_nobpt (addr
, buf
, instlen
);
973 memory_error (status
, addr
);
974 return extract_unsigned_integer (buf
, instlen
);
978 mips32_fetch_instruction (CORE_ADDR addr
)
980 char buf
[MIPS_INSTLEN
];
983 instlen
= MIPS_INSTLEN
;
984 status
= read_memory_nobpt (addr
, buf
, instlen
);
986 memory_error (status
, addr
);
987 return extract_unsigned_integer (buf
, instlen
);
991 /* These the fields of 32 bit mips instructions */
992 #define mips32_op(x) (x >> 26)
993 #define itype_op(x) (x >> 26)
994 #define itype_rs(x) ((x >> 21) & 0x1f)
995 #define itype_rt(x) ((x >> 16) & 0x1f)
996 #define itype_immediate(x) (x & 0xffff)
998 #define jtype_op(x) (x >> 26)
999 #define jtype_target(x) (x & 0x03ffffff)
1001 #define rtype_op(x) (x >> 26)
1002 #define rtype_rs(x) ((x >> 21) & 0x1f)
1003 #define rtype_rt(x) ((x >> 16) & 0x1f)
1004 #define rtype_rd(x) ((x >> 11) & 0x1f)
1005 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1006 #define rtype_funct(x) (x & 0x3f)
1009 mips32_relative_offset (unsigned long inst
)
1012 x
= itype_immediate (inst
);
1013 if (x
& 0x8000) /* sign bit set */
1015 x
|= 0xffff0000; /* sign extension */
1021 /* Determine whate to set a single step breakpoint while considering
1022 branch prediction */
1024 mips32_next_pc (CORE_ADDR pc
)
1028 inst
= mips_fetch_instruction (pc
);
1029 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch instruction */
1031 if (itype_op (inst
) >> 2 == 5)
1032 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1034 op
= (itype_op (inst
) & 0x03);
1044 goto greater_branch
;
1049 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
1050 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1052 int tf
= itype_rt (inst
) & 0x01;
1053 int cnum
= itype_rt (inst
) >> 2;
1055 read_signed_register (mips_regnum (current_gdbarch
)->
1057 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
1059 if (((cond
>> cnum
) & 0x01) == tf
)
1060 pc
+= mips32_relative_offset (inst
) + 4;
1065 pc
+= 4; /* Not a branch, next instruction is easy */
1068 { /* This gets way messy */
1070 /* Further subdivide into SPECIAL, REGIMM and other */
1071 switch (op
= itype_op (inst
) & 0x07) /* extract bits 28,27,26 */
1073 case 0: /* SPECIAL */
1074 op
= rtype_funct (inst
);
1079 /* Set PC to that address */
1080 pc
= read_signed_register (rtype_rs (inst
));
1086 break; /* end SPECIAL */
1087 case 1: /* REGIMM */
1089 op
= itype_rt (inst
); /* branch condition */
1094 case 16: /* BLTZAL */
1095 case 18: /* BLTZALL */
1097 if (read_signed_register (itype_rs (inst
)) < 0)
1098 pc
+= mips32_relative_offset (inst
) + 4;
1100 pc
+= 8; /* after the delay slot */
1104 case 17: /* BGEZAL */
1105 case 19: /* BGEZALL */
1106 if (read_signed_register (itype_rs (inst
)) >= 0)
1107 pc
+= mips32_relative_offset (inst
) + 4;
1109 pc
+= 8; /* after the delay slot */
1111 /* All of the other instructions in the REGIMM category */
1116 break; /* end REGIMM */
1121 reg
= jtype_target (inst
) << 2;
1122 /* Upper four bits get never changed... */
1123 pc
= reg
+ ((pc
+ 4) & 0xf0000000);
1126 /* FIXME case JALX : */
1129 reg
= jtype_target (inst
) << 2;
1130 pc
= reg
+ ((pc
+ 4) & 0xf0000000) + 1; /* yes, +1 */
1131 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1133 break; /* The new PC will be alternate mode */
1134 case 4: /* BEQ, BEQL */
1136 if (read_signed_register (itype_rs (inst
)) ==
1137 read_signed_register (itype_rt (inst
)))
1138 pc
+= mips32_relative_offset (inst
) + 4;
1142 case 5: /* BNE, BNEL */
1144 if (read_signed_register (itype_rs (inst
)) !=
1145 read_signed_register (itype_rt (inst
)))
1146 pc
+= mips32_relative_offset (inst
) + 4;
1150 case 6: /* BLEZ, BLEZL */
1151 if (read_signed_register (itype_rs (inst
) <= 0))
1152 pc
+= mips32_relative_offset (inst
) + 4;
1158 greater_branch
: /* BGTZ, BGTZL */
1159 if (read_signed_register (itype_rs (inst
) > 0))
1160 pc
+= mips32_relative_offset (inst
) + 4;
1167 } /* mips32_next_pc */
1169 /* Decoding the next place to set a breakpoint is irregular for the
1170 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1171 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1172 We dont want to set a single step instruction on the extend instruction
1176 /* Lots of mips16 instruction formats */
1177 /* Predicting jumps requires itype,ritype,i8type
1178 and their extensions extItype,extritype,extI8type
1180 enum mips16_inst_fmts
1182 itype
, /* 0 immediate 5,10 */
1183 ritype
, /* 1 5,3,8 */
1184 rrtype
, /* 2 5,3,3,5 */
1185 rritype
, /* 3 5,3,3,5 */
1186 rrrtype
, /* 4 5,3,3,3,2 */
1187 rriatype
, /* 5 5,3,3,1,4 */
1188 shifttype
, /* 6 5,3,3,3,2 */
1189 i8type
, /* 7 5,3,8 */
1190 i8movtype
, /* 8 5,3,3,5 */
1191 i8mov32rtype
, /* 9 5,3,5,3 */
1192 i64type
, /* 10 5,3,8 */
1193 ri64type
, /* 11 5,3,3,5 */
1194 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1195 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1196 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1197 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1198 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1199 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1200 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1201 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1202 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1203 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1205 /* I am heaping all the fields of the formats into one structure and
1206 then, only the fields which are involved in instruction extension */
1210 unsigned int regx
; /* Function in i8 type */
1215 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1216 for the bits which make up the immediatate extension. */
1219 extended_offset (unsigned int extension
)
1222 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
1224 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
1226 value
|= extension
& 0x01f; /* extract 4:0 */
1230 /* Only call this function if you know that this is an extendable
1231 instruction, It wont malfunction, but why make excess remote memory references?
1232 If the immediate operands get sign extended or somthing, do it after
1233 the extension is performed.
1235 /* FIXME: Every one of these cases needs to worry about sign extension
1236 when the offset is to be used in relative addressing */
1240 fetch_mips_16 (CORE_ADDR pc
)
1243 pc
&= 0xfffffffe; /* clear the low order bit */
1244 target_read_memory (pc
, buf
, 2);
1245 return extract_unsigned_integer (buf
, 2);
1249 unpack_mips16 (CORE_ADDR pc
,
1250 unsigned int extension
,
1252 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
1257 switch (insn_format
)
1264 value
= extended_offset (extension
);
1265 value
= value
<< 11; /* rom for the original value */
1266 value
|= inst
& 0x7ff; /* eleven bits from instruction */
1270 value
= inst
& 0x7ff;
1271 /* FIXME : Consider sign extension */
1280 { /* A register identifier and an offset */
1281 /* Most of the fields are the same as I type but the
1282 immediate value is of a different length */
1286 value
= extended_offset (extension
);
1287 value
= value
<< 8; /* from the original instruction */
1288 value
|= inst
& 0xff; /* eleven bits from instruction */
1289 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
1290 if (value
& 0x4000) /* test the sign bit , bit 26 */
1292 value
&= ~0x3fff; /* remove the sign bit */
1298 value
= inst
& 0xff; /* 8 bits */
1299 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
1300 /* FIXME: Do sign extension , this format needs it */
1301 if (value
& 0x80) /* THIS CONFUSES ME */
1303 value
&= 0xef; /* remove the sign bit */
1313 unsigned long value
;
1314 unsigned int nexthalf
;
1315 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1316 value
= value
<< 16;
1317 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
1325 internal_error (__FILE__
, __LINE__
, "bad switch");
1327 upk
->offset
= offset
;
1334 add_offset_16 (CORE_ADDR pc
, int offset
)
1336 return ((offset
<< 2) | ((pc
+ 2) & (0xf0000000)));
1340 extended_mips16_next_pc (CORE_ADDR pc
,
1341 unsigned int extension
, unsigned int insn
)
1343 int op
= (insn
>> 11);
1346 case 2: /* Branch */
1349 struct upk_mips16 upk
;
1350 unpack_mips16 (pc
, extension
, insn
, itype
, &upk
);
1351 offset
= upk
.offset
;
1357 pc
+= (offset
<< 1) + 2;
1360 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1362 struct upk_mips16 upk
;
1363 unpack_mips16 (pc
, extension
, insn
, jalxtype
, &upk
);
1364 pc
= add_offset_16 (pc
, upk
.offset
);
1365 if ((insn
>> 10) & 0x01) /* Exchange mode */
1366 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1373 struct upk_mips16 upk
;
1375 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1376 reg
= read_signed_register (upk
.regx
);
1378 pc
+= (upk
.offset
<< 1) + 2;
1385 struct upk_mips16 upk
;
1387 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1388 reg
= read_signed_register (upk
.regx
);
1390 pc
+= (upk
.offset
<< 1) + 2;
1395 case 12: /* I8 Formats btez btnez */
1397 struct upk_mips16 upk
;
1399 unpack_mips16 (pc
, extension
, insn
, i8type
, &upk
);
1400 /* upk.regx contains the opcode */
1401 reg
= read_signed_register (24); /* Test register is 24 */
1402 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1403 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1404 /* pc = add_offset_16(pc,upk.offset) ; */
1405 pc
+= (upk
.offset
<< 1) + 2;
1410 case 29: /* RR Formats JR, JALR, JALR-RA */
1412 struct upk_mips16 upk
;
1413 /* upk.fmt = rrtype; */
1418 upk
.regx
= (insn
>> 8) & 0x07;
1419 upk
.regy
= (insn
>> 5) & 0x07;
1427 break; /* Function return instruction */
1433 break; /* BOGUS Guess */
1435 pc
= read_signed_register (reg
);
1442 /* This is an instruction extension. Fetch the real instruction
1443 (which follows the extension) and decode things based on
1447 pc
= extended_mips16_next_pc (pc
, insn
, fetch_mips_16 (pc
));
1460 mips16_next_pc (CORE_ADDR pc
)
1462 unsigned int insn
= fetch_mips_16 (pc
);
1463 return extended_mips16_next_pc (pc
, 0, insn
);
1466 /* The mips_next_pc function supports single_step when the remote
1467 target monitor or stub is not developed enough to do a single_step.
1468 It works by decoding the current instruction and predicting where a
1469 branch will go. This isnt hard because all the data is available.
1470 The MIPS32 and MIPS16 variants are quite different */
1472 mips_next_pc (CORE_ADDR pc
)
1475 return mips16_next_pc (pc
);
1477 return mips32_next_pc (pc
);
1480 struct mips_frame_cache
1483 struct trad_frame_saved_reg
*saved_regs
;
1487 static struct mips_frame_cache
*
1488 mips_mdebug_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1490 mips_extra_func_info_t proc_desc
;
1491 struct mips_frame_cache
*cache
;
1492 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
1493 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1494 /* r0 bit means kernel trap */
1496 /* What registers have been saved? Bitmasks. */
1497 unsigned long gen_mask
, float_mask
;
1499 if ((*this_cache
) != NULL
)
1500 return (*this_cache
);
1501 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1502 (*this_cache
) = cache
;
1503 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1505 /* Get the mdebug proc descriptor. */
1506 proc_desc
= find_proc_desc (frame_pc_unwind (next_frame
), next_frame
, 1);
1507 if (proc_desc
== NULL
)
1508 /* I'm not sure how/whether this can happen. Normally when we
1509 can't find a proc_desc, we "synthesize" one using
1510 heuristic_proc_desc and set the saved_regs right away. */
1513 /* Extract the frame's base. */
1514 cache
->base
= (frame_unwind_register_signed (next_frame
, NUM_REGS
+ PROC_FRAME_REG (proc_desc
))
1515 + PROC_FRAME_OFFSET (proc_desc
) - PROC_FRAME_ADJUST (proc_desc
));
1517 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1518 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
1519 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
1521 /* In any frame other than the innermost or a frame interrupted by a
1522 signal, we assume that all registers have been saved. This
1523 assumes that all register saves in a function happen before the
1524 first function call. */
1525 if (in_prologue (frame_pc_unwind (next_frame
), PROC_LOW_ADDR (proc_desc
))
1526 /* Not sure exactly what kernel_trap means, but if it means the
1527 kernel saves the registers without a prologue doing it, we
1528 better not examine the prologue to see whether registers
1529 have been saved yet. */
1532 /* We need to figure out whether the registers that the
1533 proc_desc claims are saved have been saved yet. */
1537 /* Bitmasks; set if we have found a save for the register. */
1538 unsigned long gen_save_found
= 0;
1539 unsigned long float_save_found
= 0;
1542 /* If the address is odd, assume this is MIPS16 code. */
1543 addr
= PROC_LOW_ADDR (proc_desc
);
1544 mips16
= pc_is_mips16 (addr
);
1546 /* Scan through this function's instructions preceding the
1547 current PC, and look for those that save registers. */
1548 while (addr
< frame_pc_unwind (next_frame
))
1552 mips16_decode_reg_save (mips16_fetch_instruction (addr
),
1554 addr
+= MIPS16_INSTLEN
;
1558 mips32_decode_reg_save (mips32_fetch_instruction (addr
),
1559 &gen_save_found
, &float_save_found
);
1560 addr
+= MIPS_INSTLEN
;
1563 gen_mask
= gen_save_found
;
1564 float_mask
= float_save_found
;
1567 /* Fill in the offsets for the registers which gen_mask says were
1570 CORE_ADDR reg_position
= (cache
->base
1571 + PROC_REG_OFFSET (proc_desc
));
1573 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
1574 if (gen_mask
& 0x80000000)
1576 cache
->saved_regs
[NUM_REGS
+ ireg
].addr
= reg_position
;
1577 reg_position
-= mips_abi_regsize (tdep
);
1581 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse
1582 order of that normally used by gcc. Therefore, we have to fetch
1583 the first instruction of the function, and if it's an entry
1584 instruction that saves $s0 or $s1, correct their saved addresses. */
1585 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
1587 ULONGEST inst
= mips16_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
1588 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700)
1592 int sreg_count
= (inst
>> 6) & 3;
1594 /* Check if the ra register was pushed on the stack. */
1595 CORE_ADDR reg_position
= (cache
->base
1596 + PROC_REG_OFFSET (proc_desc
));
1598 reg_position
-= mips_abi_regsize (tdep
);
1600 /* Check if the s0 and s1 registers were pushed on the
1602 /* NOTE: cagney/2004-02-08: Huh? This is doing no such
1604 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1606 cache
->saved_regs
[NUM_REGS
+ reg
].addr
= reg_position
;
1607 reg_position
-= mips_abi_regsize (tdep
);
1612 /* Fill in the offsets for the registers which float_mask says were
1615 CORE_ADDR reg_position
= (cache
->base
1616 + PROC_FREG_OFFSET (proc_desc
));
1618 /* Fill in the offsets for the float registers which float_mask
1620 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
1621 if (float_mask
& 0x80000000)
1623 if (mips_abi_regsize (tdep
) == 4
1624 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1626 /* On a big endian 32 bit ABI, floating point registers
1627 are paired to form doubles such that the most
1628 significant part is in $f[N+1] and the least
1629 significant in $f[N] vis: $f[N+1] ||| $f[N]. The
1630 registers are also spilled as a pair and stored as a
1633 When little-endian the least significant part is
1634 stored first leading to the memory order $f[N] and
1637 Unfortunately, when big-endian the most significant
1638 part of the double is stored first, and the least
1639 significant is stored second. This leads to the
1640 registers being ordered in memory as firt $f[N+1] and
1643 For the big-endian case make certain that the
1644 addresses point at the correct (swapped) locations
1645 $f[N] and $f[N+1] pair (keep in mind that
1646 reg_position is decremented each time through the
1649 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1650 .addr
= reg_position
- mips_abi_regsize (tdep
);
1652 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1653 .addr
= reg_position
+ mips_abi_regsize (tdep
);
1656 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1657 .addr
= reg_position
;
1658 reg_position
-= mips_abi_regsize (tdep
);
1661 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->pc
]
1662 = cache
->saved_regs
[NUM_REGS
+ RA_REGNUM
];
1665 /* SP_REGNUM, contains the value and not the address. */
1666 trad_frame_set_value (cache
->saved_regs
, NUM_REGS
+ SP_REGNUM
, cache
->base
);
1668 return (*this_cache
);
1672 mips_mdebug_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
1673 struct frame_id
*this_id
)
1675 struct mips_frame_cache
*info
= mips_mdebug_frame_cache (next_frame
,
1677 (*this_id
) = frame_id_build (info
->base
, frame_func_unwind (next_frame
));
1681 mips_mdebug_frame_prev_register (struct frame_info
*next_frame
,
1683 int regnum
, int *optimizedp
,
1684 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1685 int *realnump
, void *valuep
)
1687 struct mips_frame_cache
*info
= mips_mdebug_frame_cache (next_frame
,
1689 trad_frame_prev_register (next_frame
, info
->saved_regs
, regnum
,
1690 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
1693 static const struct frame_unwind mips_mdebug_frame_unwind
=
1696 mips_mdebug_frame_this_id
,
1697 mips_mdebug_frame_prev_register
1700 static const struct frame_unwind
*
1701 mips_mdebug_frame_sniffer (struct frame_info
*next_frame
)
1703 return &mips_mdebug_frame_unwind
;
1707 mips_mdebug_frame_base_address (struct frame_info
*next_frame
,
1710 struct mips_frame_cache
*info
= mips_mdebug_frame_cache (next_frame
,
1715 static const struct frame_base mips_mdebug_frame_base
= {
1716 &mips_mdebug_frame_unwind
,
1717 mips_mdebug_frame_base_address
,
1718 mips_mdebug_frame_base_address
,
1719 mips_mdebug_frame_base_address
1722 static const struct frame_base
*
1723 mips_mdebug_frame_base_sniffer (struct frame_info
*next_frame
)
1725 return &mips_mdebug_frame_base
;
1729 read_next_frame_reg (struct frame_info
*fi
, int regno
)
1731 /* Always a pseudo. */
1732 gdb_assert (regno
>= NUM_REGS
);
1736 regcache_cooked_read_signed (current_regcache
, regno
, &val
);
1739 else if ((regno
% NUM_REGS
) == SP_REGNUM
)
1740 /* The SP_REGNUM is special, its value is stored in saved_regs.
1741 In fact, it is so special that it can even only be fetched
1742 using a raw register number! Once this code as been converted
1743 to frame-unwind the problem goes away. */
1744 return frame_unwind_register_signed (fi
, regno
% NUM_REGS
);
1746 return frame_unwind_register_signed (fi
, regno
);
1750 /* mips_addr_bits_remove - remove useless address bits */
1753 mips_addr_bits_remove (CORE_ADDR addr
)
1755 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1756 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
1757 /* This hack is a work-around for existing boards using PMON, the
1758 simulator, and any other 64-bit targets that doesn't have true
1759 64-bit addressing. On these targets, the upper 32 bits of
1760 addresses are ignored by the hardware. Thus, the PC or SP are
1761 likely to have been sign extended to all 1s by instruction
1762 sequences that load 32-bit addresses. For example, a typical
1763 piece of code that loads an address is this:
1765 lui $r2, <upper 16 bits>
1766 ori $r2, <lower 16 bits>
1768 But the lui sign-extends the value such that the upper 32 bits
1769 may be all 1s. The workaround is simply to mask off these
1770 bits. In the future, gcc may be changed to support true 64-bit
1771 addressing, and this masking will have to be disabled. */
1772 return addr
&= 0xffffffffUL
;
1777 /* mips_software_single_step() is called just before we want to resume
1778 the inferior, if we want to single-step it but there is no hardware
1779 or kernel single-step support (MIPS on GNU/Linux for example). We find
1780 the target of the coming instruction and breakpoint it.
1782 single_step is also called just after the inferior stops. If we had
1783 set up a simulated single-step, we undo our damage. */
1786 mips_software_single_step (enum target_signal sig
, int insert_breakpoints_p
)
1788 static CORE_ADDR next_pc
;
1789 typedef char binsn_quantum
[BREAKPOINT_MAX
];
1790 static binsn_quantum break_mem
;
1793 if (insert_breakpoints_p
)
1795 pc
= read_register (mips_regnum (current_gdbarch
)->pc
);
1796 next_pc
= mips_next_pc (pc
);
1798 target_insert_breakpoint (next_pc
, break_mem
);
1801 target_remove_breakpoint (next_pc
, break_mem
);
1804 static struct mips_extra_func_info temp_proc_desc
;
1806 /* This hack will go away once the get_prev_frame() code has been
1807 modified to set the frame's type first. That is BEFORE init extra
1808 frame info et.al. is called. This is because it will become
1809 possible to skip the init extra info call for sigtramp and dummy
1811 static CORE_ADDR
*temp_saved_regs
;
1813 /* Set a register's saved stack address in temp_saved_regs. If an
1814 address has already been set for this register, do nothing; this
1815 way we will only recognize the first save of a given register in a
1818 For simplicity, save the address in both [0 .. NUM_REGS) and
1819 [NUM_REGS .. 2*NUM_REGS). Strictly speaking, only the second range
1820 is used as it is only second range (the ABI instead of ISA
1821 registers) that comes into play when finding saved registers in a
1825 set_reg_offset (CORE_ADDR
*saved_regs
, int regno
, CORE_ADDR offset
)
1827 if (saved_regs
[regno
] == 0)
1829 saved_regs
[regno
+ 0 * NUM_REGS
] = offset
;
1830 saved_regs
[regno
+ 1 * NUM_REGS
] = offset
;
1835 /* Test whether the PC points to the return instruction at the
1836 end of a function. */
1839 mips_about_to_return (CORE_ADDR pc
)
1841 if (pc_is_mips16 (pc
))
1842 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
1843 generates a "jr $ra"; other times it generates code to load
1844 the return address from the stack to an accessible register (such
1845 as $a3), then a "jr" using that register. This second case
1846 is almost impossible to distinguish from an indirect jump
1847 used for switch statements, so we don't even try. */
1848 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
1850 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
1854 /* This fencepost looks highly suspicious to me. Removing it also
1855 seems suspicious as it could affect remote debugging across serial
1859 heuristic_proc_start (CORE_ADDR pc
)
1866 pc
= ADDR_BITS_REMOVE (pc
);
1868 fence
= start_pc
- heuristic_fence_post
;
1872 if (heuristic_fence_post
== UINT_MAX
|| fence
< VM_MIN_ADDRESS
)
1873 fence
= VM_MIN_ADDRESS
;
1875 instlen
= pc_is_mips16 (pc
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1877 /* search back for previous return */
1878 for (start_pc
-= instlen
;; start_pc
-= instlen
)
1879 if (start_pc
< fence
)
1881 /* It's not clear to me why we reach this point when
1882 stop_soon, but with this test, at least we
1883 don't print out warnings for every child forked (eg, on
1884 decstation). 22apr93 rich@cygnus.com. */
1885 if (stop_soon
== NO_STOP_QUIETLY
)
1887 static int blurb_printed
= 0;
1890 ("GDB can't find the start of the function at 0x%s.",
1895 /* This actually happens frequently in embedded
1896 development, when you first connect to a board
1897 and your stack pointer and pc are nowhere in
1898 particular. This message needs to give people
1899 in that situation enough information to
1900 determine that it's no big deal. */
1901 printf_filtered ("\n\
1902 GDB is unable to find the start of the function at 0x%s\n\
1903 and thus can't determine the size of that function's stack frame.\n\
1904 This means that GDB may be unable to access that stack frame, or\n\
1905 the frames below it.\n\
1906 This problem is most likely caused by an invalid program counter or\n\
1908 However, if you think GDB should simply search farther back\n\
1909 from 0x%s for code which looks like the beginning of a\n\
1910 function, you can increase the range of the search using the `set\n\
1911 heuristic-fence-post' command.\n", paddr_nz (pc
), paddr_nz (pc
));
1918 else if (pc_is_mips16 (start_pc
))
1920 unsigned short inst
;
1922 /* On MIPS16, any one of the following is likely to be the
1923 start of a function:
1927 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
1928 inst
= mips_fetch_instruction (start_pc
);
1929 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1930 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
1931 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
1932 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
1934 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1935 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1940 else if (mips_about_to_return (start_pc
))
1942 start_pc
+= 2 * MIPS_INSTLEN
; /* skip return, and its delay slot */
1949 /* Fetch the immediate value from a MIPS16 instruction.
1950 If the previous instruction was an EXTEND, use it to extend
1951 the upper bits of the immediate value. This is a helper function
1952 for mips16_heuristic_proc_desc. */
1955 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
1956 unsigned short inst
, /* current instruction */
1957 int nbits
, /* number of bits in imm field */
1958 int scale
, /* scale factor to be applied to imm */
1959 int is_signed
) /* is the imm field signed? */
1963 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1965 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1966 if (offset
& 0x8000) /* check for negative extend */
1967 offset
= 0 - (0x10000 - (offset
& 0xffff));
1968 return offset
| (inst
& 0x1f);
1972 int max_imm
= 1 << nbits
;
1973 int mask
= max_imm
- 1;
1974 int sign_bit
= max_imm
>> 1;
1976 offset
= inst
& mask
;
1977 if (is_signed
&& (offset
& sign_bit
))
1978 offset
= 0 - (max_imm
- offset
);
1979 return offset
* scale
;
1984 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
1985 stream from start_pc to limit_pc. */
1988 mips16_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1989 struct frame_info
*next_frame
, CORE_ADDR sp
)
1992 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1993 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1994 unsigned inst
= 0; /* current instruction */
1995 unsigned entry_inst
= 0; /* the entry instruction */
1997 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1999 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0; /* size of stack frame */
2000 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
2002 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS16_INSTLEN
)
2004 /* Save the previous instruction. If it's an EXTEND, we'll extract
2005 the immediate offset extension from it in mips16_get_imm. */
2008 /* Fetch and decode the instruction. */
2009 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
2010 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2011 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2013 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
2014 if (offset
< 0) /* negative stack adjustment? */
2015 PROC_FRAME_OFFSET (&temp_proc_desc
) -= offset
;
2017 /* Exit loop if a positive stack adjustment is found, which
2018 usually means that the stack cleanup code in the function
2019 epilogue is reached. */
2022 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
2024 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2025 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
2026 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
2027 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2029 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
2031 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2032 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2033 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
2034 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2036 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
2038 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2039 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
2040 set_reg_offset (temp_saved_regs
, RA_REGNUM
, sp
+ offset
);
2042 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
2044 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
2045 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
2046 set_reg_offset (temp_saved_regs
, RA_REGNUM
, sp
+ offset
);
2048 else if (inst
== 0x673d) /* move $s1, $sp */
2051 PROC_FRAME_REG (&temp_proc_desc
) = 17;
2053 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
2055 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2056 frame_addr
= sp
+ offset
;
2057 PROC_FRAME_REG (&temp_proc_desc
) = 17;
2058 PROC_FRAME_ADJUST (&temp_proc_desc
) = offset
;
2060 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
2062 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
2063 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2064 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2065 set_reg_offset (temp_saved_regs
, reg
, frame_addr
+ offset
);
2067 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
2069 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2070 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2071 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2072 set_reg_offset (temp_saved_regs
, reg
, frame_addr
+ offset
);
2074 else if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
2075 entry_inst
= inst
; /* save for later processing */
2076 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
2077 cur_pc
+= MIPS16_INSTLEN
; /* 32-bit instruction */
2080 /* The entry instruction is typically the first instruction in a function,
2081 and it stores registers at offsets relative to the value of the old SP
2082 (before the prologue). But the value of the sp parameter to this
2083 function is the new SP (after the prologue has been executed). So we
2084 can't calculate those offsets until we've seen the entire prologue,
2085 and can calculate what the old SP must have been. */
2086 if (entry_inst
!= 0)
2088 int areg_count
= (entry_inst
>> 8) & 7;
2089 int sreg_count
= (entry_inst
>> 6) & 3;
2091 /* The entry instruction always subtracts 32 from the SP. */
2092 PROC_FRAME_OFFSET (&temp_proc_desc
) += 32;
2094 /* Now we can calculate what the SP must have been at the
2095 start of the function prologue. */
2096 sp
+= PROC_FRAME_OFFSET (&temp_proc_desc
);
2098 /* Check if a0-a3 were saved in the caller's argument save area. */
2099 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
2101 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2102 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2103 offset
+= mips_abi_regsize (tdep
);
2106 /* Check if the ra register was pushed on the stack. */
2108 if (entry_inst
& 0x20)
2110 PROC_REG_MASK (&temp_proc_desc
) |= 1 << RA_REGNUM
;
2111 set_reg_offset (temp_saved_regs
, RA_REGNUM
, sp
+ offset
);
2112 offset
-= mips_abi_regsize (tdep
);
2115 /* Check if the s0 and s1 registers were pushed on the stack. */
2116 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
2118 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2119 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2120 offset
-= mips_abi_regsize (tdep
);
2126 mips32_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2127 struct frame_info
*next_frame
, CORE_ADDR sp
)
2130 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
2132 temp_saved_regs
= xrealloc (temp_saved_regs
, SIZEOF_FRAME_SAVED_REGS
);
2133 memset (temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
2134 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0;
2135 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
2136 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSTLEN
)
2138 unsigned long inst
, high_word
, low_word
;
2141 /* Fetch the instruction. */
2142 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
2144 /* Save some code by pre-extracting some useful fields. */
2145 high_word
= (inst
>> 16) & 0xffff;
2146 low_word
= inst
& 0xffff;
2147 reg
= high_word
& 0x1f;
2149 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
2150 || high_word
== 0x23bd /* addi $sp,$sp,-i */
2151 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
2153 if (low_word
& 0x8000) /* negative stack adjustment? */
2154 PROC_FRAME_OFFSET (&temp_proc_desc
) += 0x10000 - low_word
;
2156 /* Exit loop if a positive stack adjustment is found, which
2157 usually means that the stack cleanup code in the function
2158 epilogue is reached. */
2161 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
2163 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2164 set_reg_offset (temp_saved_regs
, reg
, sp
+ low_word
);
2166 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
2168 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra,
2169 but the register size used is only 32 bits. Make the address
2170 for the saved register point to the lower 32 bits. */
2171 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2172 set_reg_offset (temp_saved_regs
, reg
,
2173 sp
+ low_word
+ 8 - mips_isa_regsize (current_gdbarch
));
2175 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
2177 /* Old gcc frame, r30 is virtual frame pointer. */
2178 if ((long) low_word
!= PROC_FRAME_OFFSET (&temp_proc_desc
))
2179 frame_addr
= sp
+ low_word
;
2180 else if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
2182 unsigned alloca_adjust
;
2183 PROC_FRAME_REG (&temp_proc_desc
) = 30;
2184 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
2185 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
2186 if (alloca_adjust
> 0)
2188 /* FP > SP + frame_size. This may be because
2189 * of an alloca or somethings similar.
2190 * Fix sp to "pre-alloca" value, and try again.
2192 sp
+= alloca_adjust
;
2197 /* move $30,$sp. With different versions of gas this will be either
2198 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
2199 Accept any one of these. */
2200 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2202 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
2203 if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
2205 unsigned alloca_adjust
;
2206 PROC_FRAME_REG (&temp_proc_desc
) = 30;
2207 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
2208 alloca_adjust
= (unsigned) (frame_addr
- sp
);
2209 if (alloca_adjust
> 0)
2211 /* FP > SP + frame_size. This may be because
2212 * of an alloca or somethings similar.
2213 * Fix sp to "pre-alloca" value, and try again.
2215 sp
+= alloca_adjust
;
2220 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
2222 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2223 set_reg_offset (temp_saved_regs
, reg
, frame_addr
+ low_word
);
2228 static mips_extra_func_info_t
2229 heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2230 struct frame_info
*next_frame
, int cur_frame
)
2235 sp
= read_next_frame_reg (next_frame
, NUM_REGS
+ SP_REGNUM
);
2241 memset (&temp_proc_desc
, '\0', sizeof (temp_proc_desc
));
2242 temp_saved_regs
= xrealloc (temp_saved_regs
, SIZEOF_FRAME_SAVED_REGS
);
2243 memset (temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
2244 PROC_LOW_ADDR (&temp_proc_desc
) = start_pc
;
2245 PROC_FRAME_REG (&temp_proc_desc
) = SP_REGNUM
;
2246 PROC_PC_REG (&temp_proc_desc
) = RA_REGNUM
;
2248 if (start_pc
+ 200 < limit_pc
)
2249 limit_pc
= start_pc
+ 200;
2250 if (pc_is_mips16 (start_pc
))
2251 mips16_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
2253 mips32_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
2254 return &temp_proc_desc
;
2257 struct mips_objfile_private
2263 /* Global used to communicate between non_heuristic_proc_desc and
2264 compare_pdr_entries within qsort (). */
2265 static bfd
*the_bfd
;
2268 compare_pdr_entries (const void *a
, const void *b
)
2270 CORE_ADDR lhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) a
);
2271 CORE_ADDR rhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) b
);
2275 else if (lhs
== rhs
)
2281 static mips_extra_func_info_t
2282 non_heuristic_proc_desc (CORE_ADDR pc
, CORE_ADDR
*addrptr
)
2284 CORE_ADDR startaddr
;
2285 mips_extra_func_info_t proc_desc
;
2286 struct block
*b
= block_for_pc (pc
);
2288 struct obj_section
*sec
;
2289 struct mips_objfile_private
*priv
;
2291 if (DEPRECATED_PC_IN_CALL_DUMMY (pc
, 0, 0))
2294 find_pc_partial_function (pc
, NULL
, &startaddr
, NULL
);
2296 *addrptr
= startaddr
;
2300 sec
= find_pc_section (pc
);
2303 priv
= (struct mips_objfile_private
*) objfile_data (sec
->objfile
, mips_pdr_data
);
2305 /* Search the ".pdr" section generated by GAS. This includes most of
2306 the information normally found in ECOFF PDRs. */
2308 the_bfd
= sec
->objfile
->obfd
;
2310 && (the_bfd
->format
== bfd_object
2311 && bfd_get_flavour (the_bfd
) == bfd_target_elf_flavour
2312 && elf_elfheader (the_bfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
))
2314 /* Right now GAS only outputs the address as a four-byte sequence.
2315 This means that we should not bother with this method on 64-bit
2316 targets (until that is fixed). */
2318 priv
= obstack_alloc (&sec
->objfile
->objfile_obstack
,
2319 sizeof (struct mips_objfile_private
));
2321 set_objfile_data (sec
->objfile
, mips_pdr_data
, priv
);
2323 else if (priv
== NULL
)
2327 priv
= obstack_alloc (&sec
->objfile
->objfile_obstack
,
2328 sizeof (struct mips_objfile_private
));
2330 bfdsec
= bfd_get_section_by_name (sec
->objfile
->obfd
, ".pdr");
2333 priv
->size
= bfd_section_size (sec
->objfile
->obfd
, bfdsec
);
2334 priv
->contents
= obstack_alloc (&sec
->objfile
->objfile_obstack
,
2336 bfd_get_section_contents (sec
->objfile
->obfd
, bfdsec
,
2337 priv
->contents
, 0, priv
->size
);
2339 /* In general, the .pdr section is sorted. However, in the
2340 presence of multiple code sections (and other corner cases)
2341 it can become unsorted. Sort it so that we can use a faster
2343 qsort (priv
->contents
, priv
->size
/ 32, 32,
2344 compare_pdr_entries
);
2349 set_objfile_data (sec
->objfile
, mips_pdr_data
, priv
);
2353 if (priv
->size
!= 0)
2360 high
= priv
->size
/ 32;
2362 /* We've found a .pdr section describing this objfile. We want to
2363 find the entry which describes this code address. The .pdr
2364 information is not very descriptive; we have only a function
2365 start address. We have to look for the closest entry, because
2366 the local symbol at the beginning of this function may have
2367 been stripped - so if we ask the symbol table for the start
2368 address we may get a preceding global function. */
2370 /* First, find the last .pdr entry starting at or before PC. */
2373 mid
= (low
+ high
) / 2;
2375 ptr
= priv
->contents
+ mid
* 32;
2376 pdr_pc
= bfd_get_signed_32 (sec
->objfile
->obfd
, ptr
);
2377 pdr_pc
+= ANOFFSET (sec
->objfile
->section_offsets
,
2378 SECT_OFF_TEXT (sec
->objfile
));
2385 while (low
!= high
);
2387 /* Both low and high point one past the PDR of interest. If
2388 both are zero, that means this PC is before any region
2389 covered by a PDR, i.e. pdr_pc for the first PDR entry is
2393 ptr
= priv
->contents
+ (low
- 1) * 32;
2394 pdr_pc
= bfd_get_signed_32 (sec
->objfile
->obfd
, ptr
);
2395 pdr_pc
+= ANOFFSET (sec
->objfile
->section_offsets
,
2396 SECT_OFF_TEXT (sec
->objfile
));
2399 /* We don't have a range, so we have no way to know for sure
2400 whether we're in the correct PDR or a PDR for a preceding
2401 function and the current function was a stripped local
2402 symbol. But if the PDR's PC is at least as great as the
2403 best guess from the symbol table, assume that it does cover
2404 the right area; if a .pdr section is present at all then
2405 nearly every function will have an entry. The biggest exception
2406 will be the dynamic linker stubs; conveniently these are
2407 placed before .text instead of after. */
2409 if (pc
>= pdr_pc
&& pdr_pc
>= startaddr
)
2411 struct symbol
*sym
= find_pc_function (pc
);
2416 /* Fill in what we need of the proc_desc. */
2417 proc_desc
= (mips_extra_func_info_t
)
2418 obstack_alloc (&sec
->objfile
->objfile_obstack
,
2419 sizeof (struct mips_extra_func_info
));
2420 PROC_LOW_ADDR (proc_desc
) = pdr_pc
;
2422 /* Only used for dummy frames. */
2423 PROC_HIGH_ADDR (proc_desc
) = 0;
2425 PROC_FRAME_OFFSET (proc_desc
)
2426 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 20);
2427 PROC_FRAME_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2429 PROC_FRAME_ADJUST (proc_desc
) = 0;
2430 PROC_REG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2432 PROC_FREG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2434 PROC_REG_OFFSET (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2436 PROC_FREG_OFFSET (proc_desc
)
2437 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 16);
2438 PROC_PC_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2440 proc_desc
->pdr
.isym
= (long) sym
;
2450 if (startaddr
> BLOCK_START (b
))
2452 /* This is the "pathological" case referred to in a comment in
2453 print_frame_info. It might be better to move this check into
2458 sym
= lookup_symbol (MIPS_EFI_SYMBOL_NAME
, b
, LABEL_DOMAIN
, 0, NULL
);
2460 /* If we never found a PDR for this function in symbol reading, then
2461 examine prologues to find the information. */
2464 proc_desc
= (mips_extra_func_info_t
) SYMBOL_VALUE (sym
);
2465 if (PROC_FRAME_REG (proc_desc
) == -1)
2475 static mips_extra_func_info_t
2476 find_proc_desc (CORE_ADDR pc
, struct frame_info
*next_frame
, int cur_frame
)
2478 mips_extra_func_info_t proc_desc
;
2479 CORE_ADDR startaddr
= 0;
2481 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
2485 /* IF this is the topmost frame AND
2486 * (this proc does not have debugging information OR
2487 * the PC is in the procedure prologue)
2488 * THEN create a "heuristic" proc_desc (by analyzing
2489 * the actual code) to replace the "official" proc_desc.
2491 if (next_frame
== NULL
)
2493 struct symtab_and_line val
;
2494 struct symbol
*proc_symbol
=
2495 PROC_DESC_IS_DUMMY (proc_desc
) ? 0 : PROC_SYMBOL (proc_desc
);
2499 val
= find_pc_line (BLOCK_START
2500 (SYMBOL_BLOCK_VALUE (proc_symbol
)), 0);
2501 val
.pc
= val
.end
? val
.end
: pc
;
2503 if (!proc_symbol
|| pc
< val
.pc
)
2505 mips_extra_func_info_t found_heuristic
=
2506 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc
),
2507 pc
, next_frame
, cur_frame
);
2508 if (found_heuristic
)
2509 proc_desc
= found_heuristic
;
2515 /* Is linked_proc_desc_table really necessary? It only seems to be used
2516 by procedure call dummys. However, the procedures being called ought
2517 to have their own proc_descs, and even if they don't,
2518 heuristic_proc_desc knows how to create them! */
2520 struct linked_proc_info
*link
;
2522 for (link
= linked_proc_desc_table
; link
; link
= link
->next
)
2523 if (PROC_LOW_ADDR (&link
->info
) <= pc
2524 && PROC_HIGH_ADDR (&link
->info
) > pc
)
2528 startaddr
= heuristic_proc_start (pc
);
2530 proc_desc
= heuristic_proc_desc (startaddr
, pc
, next_frame
, cur_frame
);
2535 /* MIPS stack frames are almost impenetrable. When execution stops,
2536 we basically have to look at symbol information for the function
2537 that we stopped in, which tells us *which* register (if any) is
2538 the base of the frame pointer, and what offset from that register
2539 the frame itself is at.
2541 This presents a problem when trying to examine a stack in memory
2542 (that isn't executing at the moment), using the "frame" command. We
2543 don't have a PC, nor do we have any registers except SP.
2545 This routine takes two arguments, SP and PC, and tries to make the
2546 cached frames look as if these two arguments defined a frame on the
2547 cache. This allows the rest of info frame to extract the important
2548 arguments without difficulty. */
2551 setup_arbitrary_frame (int argc
, CORE_ADDR
*argv
)
2554 error ("MIPS frame specifications require two arguments: sp and pc");
2556 return create_new_frame (argv
[0], argv
[1]);
2559 /* According to the current ABI, should the type be passed in a
2560 floating-point register (assuming that there is space)? When there
2561 is no FPU, FP are not even considered as possibile candidates for
2562 FP registers and, consequently this returns false - forces FP
2563 arguments into integer registers. */
2566 fp_register_arg_p (enum type_code typecode
, struct type
*arg_type
)
2568 return ((typecode
== TYPE_CODE_FLT
2570 && (typecode
== TYPE_CODE_STRUCT
2571 || typecode
== TYPE_CODE_UNION
)
2572 && TYPE_NFIELDS (arg_type
) == 1
2573 && TYPE_CODE (TYPE_FIELD_TYPE (arg_type
, 0)) == TYPE_CODE_FLT
))
2574 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
);
2577 /* On o32, argument passing in GPRs depends on the alignment of the type being
2578 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2581 mips_type_needs_double_align (struct type
*type
)
2583 enum type_code typecode
= TYPE_CODE (type
);
2585 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
2587 else if (typecode
== TYPE_CODE_STRUCT
)
2589 if (TYPE_NFIELDS (type
) < 1)
2591 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
2593 else if (typecode
== TYPE_CODE_UNION
)
2597 n
= TYPE_NFIELDS (type
);
2598 for (i
= 0; i
< n
; i
++)
2599 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
2606 /* Adjust the address downward (direction of stack growth) so that it
2607 is correctly aligned for a new stack frame. */
2609 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2611 return align_down (addr
, 16);
2614 /* Determine how a return value is stored within the MIPS register
2615 file, given the return type `valtype'. */
2617 struct return_value_word
2626 return_value_location (struct type
*valtype
,
2627 struct return_value_word
*hi
,
2628 struct return_value_word
*lo
)
2630 int len
= TYPE_LENGTH (valtype
);
2631 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2633 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
2634 && ((MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
&& (len
== 4 || len
== 8))
2635 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
&& len
== 4)))
2637 if (!FP_REGISTER_DOUBLE
&& len
== 8)
2639 /* We need to break a 64bit float in two 32 bit halves and
2640 spread them across a floating-point register pair. */
2641 lo
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
2642 hi
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 0 : 4;
2643 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
2644 && register_size (current_gdbarch
,
2645 mips_regnum (current_gdbarch
)->
2646 fp0
) == 8) ? 4 : 0);
2647 hi
->reg_offset
= lo
->reg_offset
;
2648 lo
->reg
= mips_regnum (current_gdbarch
)->fp0
+ 0;
2649 hi
->reg
= mips_regnum (current_gdbarch
)->fp0
+ 1;
2655 /* The floating point value fits in a single floating-point
2657 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
2658 && register_size (current_gdbarch
,
2659 mips_regnum (current_gdbarch
)->
2661 && len
== 4) ? 4 : 0);
2662 lo
->reg
= mips_regnum (current_gdbarch
)->fp0
;
2673 /* Locate a result possibly spread across two registers. */
2675 lo
->reg
= regnum
+ 0;
2676 hi
->reg
= regnum
+ 1;
2677 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
2678 && len
< mips_abi_regsize (tdep
))
2680 /* "un-left-justify" the value in the low register */
2681 lo
->reg_offset
= mips_abi_regsize (tdep
) - len
;
2686 else if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
&& len
> mips_abi_regsize (tdep
) /* odd-size structs */
2687 && len
< mips_abi_regsize (tdep
) * 2
2688 && (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
2689 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
2691 /* "un-left-justify" the value spread across two registers. */
2692 lo
->reg_offset
= 2 * mips_abi_regsize (tdep
) - len
;
2693 lo
->len
= mips_abi_regsize (tdep
) - lo
->reg_offset
;
2695 hi
->len
= len
- lo
->len
;
2699 /* Only perform a partial copy of the second register. */
2702 if (len
> mips_abi_regsize (tdep
))
2704 lo
->len
= mips_abi_regsize (tdep
);
2705 hi
->len
= len
- mips_abi_regsize (tdep
);
2713 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
2714 && register_size (current_gdbarch
, regnum
) == 8
2715 && mips_abi_regsize (tdep
) == 4)
2717 /* Account for the fact that only the least-signficant part
2718 of the register is being used */
2719 lo
->reg_offset
+= 4;
2720 hi
->reg_offset
+= 4;
2723 hi
->buf_offset
= lo
->len
;
2727 /* Should call_function allocate stack space for a struct return? */
2730 mips_eabi_use_struct_convention (int gcc_p
, struct type
*type
)
2732 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2733 return (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (tdep
));
2736 /* Should call_function pass struct by reference?
2737 For each architecture, structs are passed either by
2738 value or by reference, depending on their size. */
2741 mips_eabi_reg_struct_has_addr (int gcc_p
, struct type
*type
)
2743 enum type_code typecode
= TYPE_CODE (check_typedef (type
));
2744 int len
= TYPE_LENGTH (check_typedef (type
));
2745 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2747 if (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
2748 return (len
> mips_abi_regsize (tdep
));
2754 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
2755 struct regcache
*regcache
, CORE_ADDR bp_addr
,
2756 int nargs
, struct value
**args
, CORE_ADDR sp
,
2757 int struct_return
, CORE_ADDR struct_addr
)
2763 int stack_offset
= 0;
2764 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2766 /* For shared libraries, "t9" needs to point at the function
2768 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
2770 /* Set the return address register to point to the entry point of
2771 the program, where a breakpoint lies in wait. */
2772 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
2774 /* First ensure that the stack and structure return address (if any)
2775 are properly aligned. The stack has to be at least 64-bit
2776 aligned even on 32-bit machines, because doubles must be 64-bit
2777 aligned. For n32 and n64, stack frames need to be 128-bit
2778 aligned, so we round to this widest known alignment. */
2780 sp
= align_down (sp
, 16);
2781 struct_addr
= align_down (struct_addr
, 16);
2783 /* Now make space on the stack for the args. We allocate more
2784 than necessary for EABI, because the first few arguments are
2785 passed in registers, but that's OK. */
2786 for (argnum
= 0; argnum
< nargs
; argnum
++)
2787 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
2788 mips_stack_argsize (tdep
));
2789 sp
-= align_up (len
, 16);
2792 fprintf_unfiltered (gdb_stdlog
,
2793 "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n",
2794 paddr_nz (sp
), (long) align_up (len
, 16));
2796 /* Initialize the integer and float register pointers. */
2798 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
2800 /* The struct_return pointer occupies the first parameter-passing reg. */
2804 fprintf_unfiltered (gdb_stdlog
,
2805 "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n",
2806 argreg
, paddr_nz (struct_addr
));
2807 write_register (argreg
++, struct_addr
);
2810 /* Now load as many as possible of the first arguments into
2811 registers, and push the rest onto the stack. Loop thru args
2812 from first to last. */
2813 for (argnum
= 0; argnum
< nargs
; argnum
++)
2816 char valbuf
[MAX_REGISTER_SIZE
];
2817 struct value
*arg
= args
[argnum
];
2818 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
2819 int len
= TYPE_LENGTH (arg_type
);
2820 enum type_code typecode
= TYPE_CODE (arg_type
);
2823 fprintf_unfiltered (gdb_stdlog
,
2824 "mips_eabi_push_dummy_call: %d len=%d type=%d",
2825 argnum
+ 1, len
, (int) typecode
);
2827 /* The EABI passes structures that do not fit in a register by
2829 if (len
> mips_abi_regsize (tdep
)
2830 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
2832 store_unsigned_integer (valbuf
, mips_abi_regsize (tdep
),
2833 VALUE_ADDRESS (arg
));
2834 typecode
= TYPE_CODE_PTR
;
2835 len
= mips_abi_regsize (tdep
);
2838 fprintf_unfiltered (gdb_stdlog
, " push");
2841 val
= (char *) VALUE_CONTENTS (arg
);
2843 /* 32-bit ABIs always start floating point arguments in an
2844 even-numbered floating point register. Round the FP register
2845 up before the check to see if there are any FP registers
2846 left. Non MIPS_EABI targets also pass the FP in the integer
2847 registers so also round up normal registers. */
2848 if (!FP_REGISTER_DOUBLE
&& fp_register_arg_p (typecode
, arg_type
))
2850 if ((float_argreg
& 1))
2854 /* Floating point arguments passed in registers have to be
2855 treated specially. On 32-bit architectures, doubles
2856 are passed in register pairs; the even register gets
2857 the low word, and the odd register gets the high word.
2858 On non-EABI processors, the first two floating point arguments are
2859 also copied to general registers, because MIPS16 functions
2860 don't use float registers for arguments. This duplication of
2861 arguments in general registers can't hurt non-MIPS16 functions
2862 because those registers are normally skipped. */
2863 /* MIPS_EABI squeezes a struct that contains a single floating
2864 point value into an FP register instead of pushing it onto the
2866 if (fp_register_arg_p (typecode
, arg_type
)
2867 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
2869 if (!FP_REGISTER_DOUBLE
&& len
== 8)
2871 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
2872 unsigned long regval
;
2874 /* Write the low word of the double to the even register(s). */
2875 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
2877 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2878 float_argreg
, phex (regval
, 4));
2879 write_register (float_argreg
++, regval
);
2881 /* Write the high word of the double to the odd register(s). */
2882 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
2884 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2885 float_argreg
, phex (regval
, 4));
2886 write_register (float_argreg
++, regval
);
2890 /* This is a floating point value that fits entirely
2891 in a single register. */
2892 /* On 32 bit ABI's the float_argreg is further adjusted
2893 above to ensure that it is even register aligned. */
2894 LONGEST regval
= extract_unsigned_integer (val
, len
);
2896 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2897 float_argreg
, phex (regval
, len
));
2898 write_register (float_argreg
++, regval
);
2903 /* Copy the argument to general registers or the stack in
2904 register-sized pieces. Large arguments are split between
2905 registers and stack. */
2906 /* Note: structs whose size is not a multiple of
2907 mips_isa_regsize() are treated specially: Irix cc passes them
2908 in registers where gcc sometimes puts them on the stack.
2909 For maximum compatibility, we will put them in both
2911 int odd_sized_struct
= ((len
> mips_abi_regsize (tdep
))
2912 && (len
% mips_abi_regsize (tdep
) != 0));
2914 /* Note: Floating-point values that didn't fit into an FP
2915 register are only written to memory. */
2918 /* Remember if the argument was written to the stack. */
2919 int stack_used_p
= 0;
2920 int partial_len
= (len
< mips_abi_regsize (tdep
)
2921 ? len
: mips_abi_regsize (tdep
));
2924 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
2927 /* Write this portion of the argument to the stack. */
2928 if (argreg
> MIPS_LAST_ARG_REGNUM
2930 || fp_register_arg_p (typecode
, arg_type
))
2932 /* Should shorter than int integer values be
2933 promoted to int before being stored? */
2934 int longword_offset
= 0;
2937 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2939 if (mips_stack_argsize (tdep
) == 8
2940 && (typecode
== TYPE_CODE_INT
2941 || typecode
== TYPE_CODE_PTR
2942 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
2943 longword_offset
= mips_stack_argsize (tdep
) - len
;
2944 else if ((typecode
== TYPE_CODE_STRUCT
2945 || typecode
== TYPE_CODE_UNION
)
2946 && (TYPE_LENGTH (arg_type
)
2947 < mips_stack_argsize (tdep
)))
2948 longword_offset
= mips_stack_argsize (tdep
) - len
;
2953 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
2954 paddr_nz (stack_offset
));
2955 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
2956 paddr_nz (longword_offset
));
2959 addr
= sp
+ stack_offset
+ longword_offset
;
2964 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
2966 for (i
= 0; i
< partial_len
; i
++)
2968 fprintf_unfiltered (gdb_stdlog
, "%02x",
2972 write_memory (addr
, val
, partial_len
);
2975 /* Note!!! This is NOT an else clause. Odd sized
2976 structs may go thru BOTH paths. Floating point
2977 arguments will not. */
2978 /* Write this portion of the argument to a general
2979 purpose register. */
2980 if (argreg
<= MIPS_LAST_ARG_REGNUM
2981 && !fp_register_arg_p (typecode
, arg_type
))
2984 extract_unsigned_integer (val
, partial_len
);
2987 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
2990 mips_abi_regsize (tdep
)));
2991 write_register (argreg
, regval
);
2998 /* Compute the the offset into the stack at which we
2999 will copy the next parameter.
3001 In the new EABI (and the NABI32), the stack_offset
3002 only needs to be adjusted when it has been used. */
3005 stack_offset
+= align_up (partial_len
,
3006 mips_stack_argsize (tdep
));
3010 fprintf_unfiltered (gdb_stdlog
, "\n");
3013 regcache_cooked_write_signed (regcache
, SP_REGNUM
, sp
);
3015 /* Return adjusted stack pointer. */
3019 /* Given a return value in `regbuf' with a type `valtype', extract and
3020 copy its value into `valbuf'. */
3023 mips_eabi_extract_return_value (struct type
*valtype
,
3024 char regbuf
[], char *valbuf
)
3026 struct return_value_word lo
;
3027 struct return_value_word hi
;
3028 return_value_location (valtype
, &hi
, &lo
);
3030 memcpy (valbuf
+ lo
.buf_offset
,
3031 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ lo
.reg
) +
3032 lo
.reg_offset
, lo
.len
);
3035 memcpy (valbuf
+ hi
.buf_offset
,
3036 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ hi
.reg
) +
3037 hi
.reg_offset
, hi
.len
);
3040 /* Given a return value in `valbuf' with a type `valtype', write it's
3041 value into the appropriate register. */
3044 mips_eabi_store_return_value (struct type
*valtype
, char *valbuf
)
3046 char raw_buffer
[MAX_REGISTER_SIZE
];
3047 struct return_value_word lo
;
3048 struct return_value_word hi
;
3049 return_value_location (valtype
, &hi
, &lo
);
3051 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3052 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
3053 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo
.reg
),
3054 raw_buffer
, register_size (current_gdbarch
,
3059 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3060 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
3061 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi
.reg
),
3063 register_size (current_gdbarch
,
3068 /* N32/N64 ABI stuff. */
3071 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
3072 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3073 int nargs
, struct value
**args
, CORE_ADDR sp
,
3074 int struct_return
, CORE_ADDR struct_addr
)
3080 int stack_offset
= 0;
3081 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3083 /* For shared libraries, "t9" needs to point at the function
3085 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3087 /* Set the return address register to point to the entry point of
3088 the program, where a breakpoint lies in wait. */
3089 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3091 /* First ensure that the stack and structure return address (if any)
3092 are properly aligned. The stack has to be at least 64-bit
3093 aligned even on 32-bit machines, because doubles must be 64-bit
3094 aligned. For n32 and n64, stack frames need to be 128-bit
3095 aligned, so we round to this widest known alignment. */
3097 sp
= align_down (sp
, 16);
3098 struct_addr
= align_down (struct_addr
, 16);
3100 /* Now make space on the stack for the args. */
3101 for (argnum
= 0; argnum
< nargs
; argnum
++)
3102 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3103 mips_stack_argsize (tdep
));
3104 sp
-= align_up (len
, 16);
3107 fprintf_unfiltered (gdb_stdlog
,
3108 "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n",
3109 paddr_nz (sp
), (long) align_up (len
, 16));
3111 /* Initialize the integer and float register pointers. */
3113 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3115 /* The struct_return pointer occupies the first parameter-passing reg. */
3119 fprintf_unfiltered (gdb_stdlog
,
3120 "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n",
3121 argreg
, paddr_nz (struct_addr
));
3122 write_register (argreg
++, struct_addr
);
3125 /* Now load as many as possible of the first arguments into
3126 registers, and push the rest onto the stack. Loop thru args
3127 from first to last. */
3128 for (argnum
= 0; argnum
< nargs
; argnum
++)
3131 struct value
*arg
= args
[argnum
];
3132 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3133 int len
= TYPE_LENGTH (arg_type
);
3134 enum type_code typecode
= TYPE_CODE (arg_type
);
3137 fprintf_unfiltered (gdb_stdlog
,
3138 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
3139 argnum
+ 1, len
, (int) typecode
);
3141 val
= (char *) VALUE_CONTENTS (arg
);
3143 if (fp_register_arg_p (typecode
, arg_type
)
3144 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3146 /* This is a floating point value that fits entirely
3147 in a single register. */
3148 /* On 32 bit ABI's the float_argreg is further adjusted
3149 above to ensure that it is even register aligned. */
3150 LONGEST regval
= extract_unsigned_integer (val
, len
);
3152 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3153 float_argreg
, phex (regval
, len
));
3154 write_register (float_argreg
++, regval
);
3157 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3158 argreg
, phex (regval
, len
));
3159 write_register (argreg
, regval
);
3164 /* Copy the argument to general registers or the stack in
3165 register-sized pieces. Large arguments are split between
3166 registers and stack. */
3167 /* Note: structs whose size is not a multiple of
3168 mips_isa_regsize() are treated specially: Irix cc passes them
3169 in registers where gcc sometimes puts them on the stack.
3170 For maximum compatibility, we will put them in both
3172 int odd_sized_struct
= ((len
> mips_abi_regsize (tdep
))
3173 && (len
% mips_abi_regsize (tdep
) != 0));
3174 /* Note: Floating-point values that didn't fit into an FP
3175 register are only written to memory. */
3178 /* Rememer if the argument was written to the stack. */
3179 int stack_used_p
= 0;
3180 int partial_len
= (len
< mips_abi_regsize (tdep
)
3181 ? len
: mips_abi_regsize (tdep
));
3184 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3187 /* Write this portion of the argument to the stack. */
3188 if (argreg
> MIPS_LAST_ARG_REGNUM
3190 || fp_register_arg_p (typecode
, arg_type
))
3192 /* Should shorter than int integer values be
3193 promoted to int before being stored? */
3194 int longword_offset
= 0;
3197 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3199 if (mips_stack_argsize (tdep
) == 8
3200 && (typecode
== TYPE_CODE_INT
3201 || typecode
== TYPE_CODE_PTR
3202 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3203 longword_offset
= mips_stack_argsize (tdep
) - len
;
3208 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3209 paddr_nz (stack_offset
));
3210 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3211 paddr_nz (longword_offset
));
3214 addr
= sp
+ stack_offset
+ longword_offset
;
3219 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3221 for (i
= 0; i
< partial_len
; i
++)
3223 fprintf_unfiltered (gdb_stdlog
, "%02x",
3227 write_memory (addr
, val
, partial_len
);
3230 /* Note!!! This is NOT an else clause. Odd sized
3231 structs may go thru BOTH paths. Floating point
3232 arguments will not. */
3233 /* Write this portion of the argument to a general
3234 purpose register. */
3235 if (argreg
<= MIPS_LAST_ARG_REGNUM
3236 && !fp_register_arg_p (typecode
, arg_type
))
3239 extract_unsigned_integer (val
, partial_len
);
3241 /* A non-floating-point argument being passed in a
3242 general register. If a struct or union, and if
3243 the remaining length is smaller than the register
3244 size, we have to adjust the register value on
3247 It does not seem to be necessary to do the
3248 same for integral types.
3250 cagney/2001-07-23: gdb/179: Also, GCC, when
3251 outputting LE O32 with sizeof (struct) <
3252 mips_abi_regsize(), generates a left shift as
3253 part of storing the argument in a register a
3254 register (the left shift isn't generated when
3255 sizeof (struct) >= mips_abi_regsize()). Since
3256 it is quite possible that this is GCC
3257 contradicting the LE/O32 ABI, GDB has not been
3258 adjusted to accommodate this. Either someone
3259 needs to demonstrate that the LE/O32 ABI
3260 specifies such a left shift OR this new ABI gets
3261 identified as such and GDB gets tweaked
3264 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3265 && partial_len
< mips_abi_regsize (tdep
)
3266 && (typecode
== TYPE_CODE_STRUCT
||
3267 typecode
== TYPE_CODE_UNION
))
3268 regval
<<= ((mips_abi_regsize (tdep
) - partial_len
) *
3272 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3275 mips_abi_regsize (tdep
)));
3276 write_register (argreg
, regval
);
3283 /* Compute the the offset into the stack at which we
3284 will copy the next parameter.
3286 In N32 (N64?), the stack_offset only needs to be
3287 adjusted when it has been used. */
3290 stack_offset
+= align_up (partial_len
,
3291 mips_stack_argsize (tdep
));
3295 fprintf_unfiltered (gdb_stdlog
, "\n");
3298 regcache_cooked_write_signed (regcache
, SP_REGNUM
, sp
);
3300 /* Return adjusted stack pointer. */
3304 static enum return_value_convention
3305 mips_n32n64_return_value (struct gdbarch
*gdbarch
,
3306 struct type
*type
, struct regcache
*regcache
,
3307 void *readbuf
, const void *writebuf
)
3309 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3310 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3311 || TYPE_CODE (type
) == TYPE_CODE_UNION
3312 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
3313 || TYPE_LENGTH (type
) > 2 * mips_abi_regsize (tdep
))
3314 return RETURN_VALUE_STRUCT_CONVENTION
;
3315 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3316 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3318 /* A floating-point value belongs in the least significant part
3321 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3322 mips_xfer_register (regcache
,
3323 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
3325 TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3326 return RETURN_VALUE_REGISTER_CONVENTION
;
3328 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3329 && TYPE_NFIELDS (type
) <= 2
3330 && TYPE_NFIELDS (type
) >= 1
3331 && ((TYPE_NFIELDS (type
) == 1
3332 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3334 || (TYPE_NFIELDS (type
) == 2
3335 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3337 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
3339 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3341 /* A struct that contains one or two floats. Each value is part
3342 in the least significant part of their floating point
3346 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
3347 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3349 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3352 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3354 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
3355 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3356 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3358 return RETURN_VALUE_REGISTER_CONVENTION
;
3360 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3361 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3363 /* A structure or union. Extract the left justified value,
3364 regardless of the byte order. I.e. DO NOT USE
3368 for (offset
= 0, regnum
= V0_REGNUM
;
3369 offset
< TYPE_LENGTH (type
);
3370 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3372 int xfer
= register_size (current_gdbarch
, regnum
);
3373 if (offset
+ xfer
> TYPE_LENGTH (type
))
3374 xfer
= TYPE_LENGTH (type
) - offset
;
3376 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3377 offset
, xfer
, regnum
);
3378 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3379 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
3381 return RETURN_VALUE_REGISTER_CONVENTION
;
3385 /* A scalar extract each part but least-significant-byte
3389 for (offset
= 0, regnum
= V0_REGNUM
;
3390 offset
< TYPE_LENGTH (type
);
3391 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3393 int xfer
= register_size (current_gdbarch
, regnum
);
3394 if (offset
+ xfer
> TYPE_LENGTH (type
))
3395 xfer
= TYPE_LENGTH (type
) - offset
;
3397 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3398 offset
, xfer
, regnum
);
3399 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3400 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3402 return RETURN_VALUE_REGISTER_CONVENTION
;
3406 /* O32 ABI stuff. */
3409 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
3410 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3411 int nargs
, struct value
**args
, CORE_ADDR sp
,
3412 int struct_return
, CORE_ADDR struct_addr
)
3418 int stack_offset
= 0;
3419 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3421 /* For shared libraries, "t9" needs to point at the function
3423 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3425 /* Set the return address register to point to the entry point of
3426 the program, where a breakpoint lies in wait. */
3427 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3429 /* First ensure that the stack and structure return address (if any)
3430 are properly aligned. The stack has to be at least 64-bit
3431 aligned even on 32-bit machines, because doubles must be 64-bit
3432 aligned. For n32 and n64, stack frames need to be 128-bit
3433 aligned, so we round to this widest known alignment. */
3435 sp
= align_down (sp
, 16);
3436 struct_addr
= align_down (struct_addr
, 16);
3438 /* Now make space on the stack for the args. */
3439 for (argnum
= 0; argnum
< nargs
; argnum
++)
3440 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3441 mips_stack_argsize (tdep
));
3442 sp
-= align_up (len
, 16);
3445 fprintf_unfiltered (gdb_stdlog
,
3446 "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n",
3447 paddr_nz (sp
), (long) align_up (len
, 16));
3449 /* Initialize the integer and float register pointers. */
3451 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3453 /* The struct_return pointer occupies the first parameter-passing reg. */
3457 fprintf_unfiltered (gdb_stdlog
,
3458 "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n",
3459 argreg
, paddr_nz (struct_addr
));
3460 write_register (argreg
++, struct_addr
);
3461 stack_offset
+= mips_stack_argsize (tdep
);
3464 /* Now load as many as possible of the first arguments into
3465 registers, and push the rest onto the stack. Loop thru args
3466 from first to last. */
3467 for (argnum
= 0; argnum
< nargs
; argnum
++)
3470 struct value
*arg
= args
[argnum
];
3471 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3472 int len
= TYPE_LENGTH (arg_type
);
3473 enum type_code typecode
= TYPE_CODE (arg_type
);
3476 fprintf_unfiltered (gdb_stdlog
,
3477 "mips_o32_push_dummy_call: %d len=%d type=%d",
3478 argnum
+ 1, len
, (int) typecode
);
3480 val
= (char *) VALUE_CONTENTS (arg
);
3482 /* 32-bit ABIs always start floating point arguments in an
3483 even-numbered floating point register. Round the FP register
3484 up before the check to see if there are any FP registers
3485 left. O32/O64 targets also pass the FP in the integer
3486 registers so also round up normal registers. */
3487 if (!FP_REGISTER_DOUBLE
&& fp_register_arg_p (typecode
, arg_type
))
3489 if ((float_argreg
& 1))
3493 /* Floating point arguments passed in registers have to be
3494 treated specially. On 32-bit architectures, doubles
3495 are passed in register pairs; the even register gets
3496 the low word, and the odd register gets the high word.
3497 On O32/O64, the first two floating point arguments are
3498 also copied to general registers, because MIPS16 functions
3499 don't use float registers for arguments. This duplication of
3500 arguments in general registers can't hurt non-MIPS16 functions
3501 because those registers are normally skipped. */
3503 if (fp_register_arg_p (typecode
, arg_type
)
3504 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3506 if (!FP_REGISTER_DOUBLE
&& len
== 8)
3508 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3509 unsigned long regval
;
3511 /* Write the low word of the double to the even register(s). */
3512 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3514 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3515 float_argreg
, phex (regval
, 4));
3516 write_register (float_argreg
++, regval
);
3518 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3519 argreg
, phex (regval
, 4));
3520 write_register (argreg
++, regval
);
3522 /* Write the high word of the double to the odd register(s). */
3523 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3525 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3526 float_argreg
, phex (regval
, 4));
3527 write_register (float_argreg
++, regval
);
3530 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3531 argreg
, phex (regval
, 4));
3532 write_register (argreg
++, regval
);
3536 /* This is a floating point value that fits entirely
3537 in a single register. */
3538 /* On 32 bit ABI's the float_argreg is further adjusted
3539 above to ensure that it is even register aligned. */
3540 LONGEST regval
= extract_unsigned_integer (val
, len
);
3542 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3543 float_argreg
, phex (regval
, len
));
3544 write_register (float_argreg
++, regval
);
3545 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3546 registers for each argument. The below is (my
3547 guess) to ensure that the corresponding integer
3548 register has reserved the same space. */
3550 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3551 argreg
, phex (regval
, len
));
3552 write_register (argreg
, regval
);
3553 argreg
+= FP_REGISTER_DOUBLE
? 1 : 2;
3555 /* Reserve space for the FP register. */
3556 stack_offset
+= align_up (len
, mips_stack_argsize (tdep
));
3560 /* Copy the argument to general registers or the stack in
3561 register-sized pieces. Large arguments are split between
3562 registers and stack. */
3563 /* Note: structs whose size is not a multiple of
3564 mips_isa_regsize() are treated specially: Irix cc passes them
3565 in registers where gcc sometimes puts them on the stack.
3566 For maximum compatibility, we will put them in both
3568 int odd_sized_struct
= ((len
> mips_abi_regsize (tdep
))
3569 && (len
% mips_abi_regsize (tdep
) != 0));
3570 /* Structures should be aligned to eight bytes (even arg registers)
3571 on MIPS_ABI_O32, if their first member has double precision. */
3572 if (mips_abi_regsize (tdep
) < 8
3573 && mips_type_needs_double_align (arg_type
))
3578 /* Note: Floating-point values that didn't fit into an FP
3579 register are only written to memory. */
3582 /* Remember if the argument was written to the stack. */
3583 int stack_used_p
= 0;
3584 int partial_len
= (len
< mips_abi_regsize (tdep
)
3585 ? len
: mips_abi_regsize (tdep
));
3588 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3591 /* Write this portion of the argument to the stack. */
3592 if (argreg
> MIPS_LAST_ARG_REGNUM
3594 || fp_register_arg_p (typecode
, arg_type
))
3596 /* Should shorter than int integer values be
3597 promoted to int before being stored? */
3598 int longword_offset
= 0;
3601 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3603 if (mips_stack_argsize (tdep
) == 8
3604 && (typecode
== TYPE_CODE_INT
3605 || typecode
== TYPE_CODE_PTR
3606 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3607 longword_offset
= mips_stack_argsize (tdep
) - len
;
3612 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3613 paddr_nz (stack_offset
));
3614 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3615 paddr_nz (longword_offset
));
3618 addr
= sp
+ stack_offset
+ longword_offset
;
3623 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3625 for (i
= 0; i
< partial_len
; i
++)
3627 fprintf_unfiltered (gdb_stdlog
, "%02x",
3631 write_memory (addr
, val
, partial_len
);
3634 /* Note!!! This is NOT an else clause. Odd sized
3635 structs may go thru BOTH paths. Floating point
3636 arguments will not. */
3637 /* Write this portion of the argument to a general
3638 purpose register. */
3639 if (argreg
<= MIPS_LAST_ARG_REGNUM
3640 && !fp_register_arg_p (typecode
, arg_type
))
3642 LONGEST regval
= extract_signed_integer (val
, partial_len
);
3643 /* Value may need to be sign extended, because
3644 mips_isa_regsize() != mips_abi_regsize(). */
3646 /* A non-floating-point argument being passed in a
3647 general register. If a struct or union, and if
3648 the remaining length is smaller than the register
3649 size, we have to adjust the register value on
3652 It does not seem to be necessary to do the
3653 same for integral types.
3655 Also don't do this adjustment on O64 binaries.
3657 cagney/2001-07-23: gdb/179: Also, GCC, when
3658 outputting LE O32 with sizeof (struct) <
3659 mips_abi_regsize(), generates a left shift as
3660 part of storing the argument in a register a
3661 register (the left shift isn't generated when
3662 sizeof (struct) >= mips_abi_regsize()). Since
3663 it is quite possible that this is GCC
3664 contradicting the LE/O32 ABI, GDB has not been
3665 adjusted to accommodate this. Either someone
3666 needs to demonstrate that the LE/O32 ABI
3667 specifies such a left shift OR this new ABI gets
3668 identified as such and GDB gets tweaked
3671 if (mips_abi_regsize (tdep
) < 8
3672 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3673 && partial_len
< mips_abi_regsize (tdep
)
3674 && (typecode
== TYPE_CODE_STRUCT
||
3675 typecode
== TYPE_CODE_UNION
))
3676 regval
<<= ((mips_abi_regsize (tdep
) - partial_len
) *
3680 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3683 mips_abi_regsize (tdep
)));
3684 write_register (argreg
, regval
);
3687 /* Prevent subsequent floating point arguments from
3688 being passed in floating point registers. */
3689 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
3695 /* Compute the the offset into the stack at which we
3696 will copy the next parameter.
3698 In older ABIs, the caller reserved space for
3699 registers that contained arguments. This was loosely
3700 refered to as their "home". Consequently, space is
3701 always allocated. */
3703 stack_offset
+= align_up (partial_len
,
3704 mips_stack_argsize (tdep
));
3708 fprintf_unfiltered (gdb_stdlog
, "\n");
3711 regcache_cooked_write_signed (regcache
, SP_REGNUM
, sp
);
3713 /* Return adjusted stack pointer. */
3717 static enum return_value_convention
3718 mips_o32_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
3719 struct regcache
*regcache
,
3720 void *readbuf
, const void *writebuf
)
3722 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3724 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3725 || TYPE_CODE (type
) == TYPE_CODE_UNION
3726 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
3727 return RETURN_VALUE_STRUCT_CONVENTION
;
3728 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3729 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3731 /* A single-precision floating-point value. It fits in the
3732 least significant part of FP0. */
3734 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3735 mips_xfer_register (regcache
,
3736 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
3738 TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3739 return RETURN_VALUE_REGISTER_CONVENTION
;
3741 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3742 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3744 /* A double-precision floating-point value. The most
3745 significant part goes in FP1, and the least significant in
3748 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
3749 switch (TARGET_BYTE_ORDER
)
3751 case BFD_ENDIAN_LITTLE
:
3752 mips_xfer_register (regcache
,
3753 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
3754 0, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3755 mips_xfer_register (regcache
,
3756 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
3757 1, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 4);
3759 case BFD_ENDIAN_BIG
:
3760 mips_xfer_register (regcache
,
3761 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
3762 1, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3763 mips_xfer_register (regcache
,
3764 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
3765 0, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 4);
3768 internal_error (__FILE__
, __LINE__
, "bad switch");
3770 return RETURN_VALUE_REGISTER_CONVENTION
;
3773 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3774 && TYPE_NFIELDS (type
) <= 2
3775 && TYPE_NFIELDS (type
) >= 1
3776 && ((TYPE_NFIELDS (type
) == 1
3777 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3779 || (TYPE_NFIELDS (type
) == 2
3780 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3782 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
3784 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3786 /* A struct that contains one or two floats. Each value is part
3787 in the least significant part of their floating point
3789 bfd_byte reg
[MAX_REGISTER_SIZE
];
3792 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
3793 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3795 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3798 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3800 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
3801 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3802 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3804 return RETURN_VALUE_REGISTER_CONVENTION
;
3808 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3809 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3811 /* A structure or union. Extract the left justified value,
3812 regardless of the byte order. I.e. DO NOT USE
3816 for (offset
= 0, regnum
= V0_REGNUM
;
3817 offset
< TYPE_LENGTH (type
);
3818 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3820 int xfer
= register_size (current_gdbarch
, regnum
);
3821 if (offset
+ xfer
> TYPE_LENGTH (type
))
3822 xfer
= TYPE_LENGTH (type
) - offset
;
3824 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3825 offset
, xfer
, regnum
);
3826 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3827 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
3829 return RETURN_VALUE_REGISTER_CONVENTION
;
3834 /* A scalar extract each part but least-significant-byte
3835 justified. o32 thinks registers are 4 byte, regardless of
3836 the ISA. mips_stack_argsize controls this. */
3839 for (offset
= 0, regnum
= V0_REGNUM
;
3840 offset
< TYPE_LENGTH (type
);
3841 offset
+= mips_stack_argsize (tdep
), regnum
++)
3843 int xfer
= mips_stack_argsize (tdep
);
3844 if (offset
+ xfer
> TYPE_LENGTH (type
))
3845 xfer
= TYPE_LENGTH (type
) - offset
;
3847 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3848 offset
, xfer
, regnum
);
3849 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3850 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3852 return RETURN_VALUE_REGISTER_CONVENTION
;
3856 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
3860 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
3861 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3863 struct value
**args
, CORE_ADDR sp
,
3864 int struct_return
, CORE_ADDR struct_addr
)
3870 int stack_offset
= 0;
3871 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3873 /* For shared libraries, "t9" needs to point at the function
3875 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3877 /* Set the return address register to point to the entry point of
3878 the program, where a breakpoint lies in wait. */
3879 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3881 /* First ensure that the stack and structure return address (if any)
3882 are properly aligned. The stack has to be at least 64-bit
3883 aligned even on 32-bit machines, because doubles must be 64-bit
3884 aligned. For n32 and n64, stack frames need to be 128-bit
3885 aligned, so we round to this widest known alignment. */
3887 sp
= align_down (sp
, 16);
3888 struct_addr
= align_down (struct_addr
, 16);
3890 /* Now make space on the stack for the args. */
3891 for (argnum
= 0; argnum
< nargs
; argnum
++)
3892 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3893 mips_stack_argsize (tdep
));
3894 sp
-= align_up (len
, 16);
3897 fprintf_unfiltered (gdb_stdlog
,
3898 "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n",
3899 paddr_nz (sp
), (long) align_up (len
, 16));
3901 /* Initialize the integer and float register pointers. */
3903 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3905 /* The struct_return pointer occupies the first parameter-passing reg. */
3909 fprintf_unfiltered (gdb_stdlog
,
3910 "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n",
3911 argreg
, paddr_nz (struct_addr
));
3912 write_register (argreg
++, struct_addr
);
3913 stack_offset
+= mips_stack_argsize (tdep
);
3916 /* Now load as many as possible of the first arguments into
3917 registers, and push the rest onto the stack. Loop thru args
3918 from first to last. */
3919 for (argnum
= 0; argnum
< nargs
; argnum
++)
3922 struct value
*arg
= args
[argnum
];
3923 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3924 int len
= TYPE_LENGTH (arg_type
);
3925 enum type_code typecode
= TYPE_CODE (arg_type
);
3928 fprintf_unfiltered (gdb_stdlog
,
3929 "mips_o64_push_dummy_call: %d len=%d type=%d",
3930 argnum
+ 1, len
, (int) typecode
);
3932 val
= (char *) VALUE_CONTENTS (arg
);
3934 /* 32-bit ABIs always start floating point arguments in an
3935 even-numbered floating point register. Round the FP register
3936 up before the check to see if there are any FP registers
3937 left. O32/O64 targets also pass the FP in the integer
3938 registers so also round up normal registers. */
3939 if (!FP_REGISTER_DOUBLE
&& fp_register_arg_p (typecode
, arg_type
))
3941 if ((float_argreg
& 1))
3945 /* Floating point arguments passed in registers have to be
3946 treated specially. On 32-bit architectures, doubles
3947 are passed in register pairs; the even register gets
3948 the low word, and the odd register gets the high word.
3949 On O32/O64, the first two floating point arguments are
3950 also copied to general registers, because MIPS16 functions
3951 don't use float registers for arguments. This duplication of
3952 arguments in general registers can't hurt non-MIPS16 functions
3953 because those registers are normally skipped. */
3955 if (fp_register_arg_p (typecode
, arg_type
)
3956 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3958 if (!FP_REGISTER_DOUBLE
&& len
== 8)
3960 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3961 unsigned long regval
;
3963 /* Write the low word of the double to the even register(s). */
3964 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3966 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3967 float_argreg
, phex (regval
, 4));
3968 write_register (float_argreg
++, regval
);
3970 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3971 argreg
, phex (regval
, 4));
3972 write_register (argreg
++, regval
);
3974 /* Write the high word of the double to the odd register(s). */
3975 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3977 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3978 float_argreg
, phex (regval
, 4));
3979 write_register (float_argreg
++, regval
);
3982 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3983 argreg
, phex (regval
, 4));
3984 write_register (argreg
++, regval
);
3988 /* This is a floating point value that fits entirely
3989 in a single register. */
3990 /* On 32 bit ABI's the float_argreg is further adjusted
3991 above to ensure that it is even register aligned. */
3992 LONGEST regval
= extract_unsigned_integer (val
, len
);
3994 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3995 float_argreg
, phex (regval
, len
));
3996 write_register (float_argreg
++, regval
);
3997 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3998 registers for each argument. The below is (my
3999 guess) to ensure that the corresponding integer
4000 register has reserved the same space. */
4002 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4003 argreg
, phex (regval
, len
));
4004 write_register (argreg
, regval
);
4005 argreg
+= FP_REGISTER_DOUBLE
? 1 : 2;
4007 /* Reserve space for the FP register. */
4008 stack_offset
+= align_up (len
, mips_stack_argsize (tdep
));
4012 /* Copy the argument to general registers or the stack in
4013 register-sized pieces. Large arguments are split between
4014 registers and stack. */
4015 /* Note: structs whose size is not a multiple of
4016 mips_isa_regsize() are treated specially: Irix cc passes them
4017 in registers where gcc sometimes puts them on the stack.
4018 For maximum compatibility, we will put them in both
4020 int odd_sized_struct
= ((len
> mips_abi_regsize (tdep
))
4021 && (len
% mips_abi_regsize (tdep
) != 0));
4022 /* Structures should be aligned to eight bytes (even arg registers)
4023 on MIPS_ABI_O32, if their first member has double precision. */
4024 if (mips_abi_regsize (tdep
) < 8
4025 && mips_type_needs_double_align (arg_type
))
4030 /* Note: Floating-point values that didn't fit into an FP
4031 register are only written to memory. */
4034 /* Remember if the argument was written to the stack. */
4035 int stack_used_p
= 0;
4036 int partial_len
= (len
< mips_abi_regsize (tdep
)
4037 ? len
: mips_abi_regsize (tdep
));
4040 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4043 /* Write this portion of the argument to the stack. */
4044 if (argreg
> MIPS_LAST_ARG_REGNUM
4046 || fp_register_arg_p (typecode
, arg_type
))
4048 /* Should shorter than int integer values be
4049 promoted to int before being stored? */
4050 int longword_offset
= 0;
4053 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4055 if (mips_stack_argsize (tdep
) == 8
4056 && (typecode
== TYPE_CODE_INT
4057 || typecode
== TYPE_CODE_PTR
4058 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
4059 longword_offset
= mips_stack_argsize (tdep
) - len
;
4064 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
4065 paddr_nz (stack_offset
));
4066 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
4067 paddr_nz (longword_offset
));
4070 addr
= sp
+ stack_offset
+ longword_offset
;
4075 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
4077 for (i
= 0; i
< partial_len
; i
++)
4079 fprintf_unfiltered (gdb_stdlog
, "%02x",
4083 write_memory (addr
, val
, partial_len
);
4086 /* Note!!! This is NOT an else clause. Odd sized
4087 structs may go thru BOTH paths. Floating point
4088 arguments will not. */
4089 /* Write this portion of the argument to a general
4090 purpose register. */
4091 if (argreg
<= MIPS_LAST_ARG_REGNUM
4092 && !fp_register_arg_p (typecode
, arg_type
))
4094 LONGEST regval
= extract_signed_integer (val
, partial_len
);
4095 /* Value may need to be sign extended, because
4096 mips_isa_regsize() != mips_abi_regsize(). */
4098 /* A non-floating-point argument being passed in a
4099 general register. If a struct or union, and if
4100 the remaining length is smaller than the register
4101 size, we have to adjust the register value on
4104 It does not seem to be necessary to do the
4105 same for integral types.
4107 Also don't do this adjustment on O64 binaries.
4109 cagney/2001-07-23: gdb/179: Also, GCC, when
4110 outputting LE O32 with sizeof (struct) <
4111 mips_abi_regsize(), generates a left shift as
4112 part of storing the argument in a register a
4113 register (the left shift isn't generated when
4114 sizeof (struct) >= mips_abi_regsize()). Since
4115 it is quite possible that this is GCC
4116 contradicting the LE/O32 ABI, GDB has not been
4117 adjusted to accommodate this. Either someone
4118 needs to demonstrate that the LE/O32 ABI
4119 specifies such a left shift OR this new ABI gets
4120 identified as such and GDB gets tweaked
4123 if (mips_abi_regsize (tdep
) < 8
4124 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4125 && partial_len
< mips_abi_regsize (tdep
)
4126 && (typecode
== TYPE_CODE_STRUCT
||
4127 typecode
== TYPE_CODE_UNION
))
4128 regval
<<= ((mips_abi_regsize (tdep
) - partial_len
) *
4132 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4135 mips_abi_regsize (tdep
)));
4136 write_register (argreg
, regval
);
4139 /* Prevent subsequent floating point arguments from
4140 being passed in floating point registers. */
4141 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
4147 /* Compute the the offset into the stack at which we
4148 will copy the next parameter.
4150 In older ABIs, the caller reserved space for
4151 registers that contained arguments. This was loosely
4152 refered to as their "home". Consequently, space is
4153 always allocated. */
4155 stack_offset
+= align_up (partial_len
,
4156 mips_stack_argsize (tdep
));
4160 fprintf_unfiltered (gdb_stdlog
, "\n");
4163 regcache_cooked_write_signed (regcache
, SP_REGNUM
, sp
);
4165 /* Return adjusted stack pointer. */
4170 mips_o64_extract_return_value (struct type
*valtype
,
4171 char regbuf
[], char *valbuf
)
4173 struct return_value_word lo
;
4174 struct return_value_word hi
;
4175 return_value_location (valtype
, &hi
, &lo
);
4177 memcpy (valbuf
+ lo
.buf_offset
,
4178 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ lo
.reg
) +
4179 lo
.reg_offset
, lo
.len
);
4182 memcpy (valbuf
+ hi
.buf_offset
,
4183 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ hi
.reg
) +
4184 hi
.reg_offset
, hi
.len
);
4188 mips_o64_store_return_value (struct type
*valtype
, char *valbuf
)
4190 char raw_buffer
[MAX_REGISTER_SIZE
];
4191 struct return_value_word lo
;
4192 struct return_value_word hi
;
4193 return_value_location (valtype
, &hi
, &lo
);
4195 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4196 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
4197 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo
.reg
),
4198 raw_buffer
, register_size (current_gdbarch
,
4203 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4204 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
4205 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi
.reg
),
4207 register_size (current_gdbarch
,
4212 /* Floating point register management.
4214 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
4215 64bit operations, these early MIPS cpus treat fp register pairs
4216 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
4217 registers and offer a compatibility mode that emulates the MIPS2 fp
4218 model. When operating in MIPS2 fp compat mode, later cpu's split
4219 double precision floats into two 32-bit chunks and store them in
4220 consecutive fp regs. To display 64-bit floats stored in this
4221 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
4222 Throw in user-configurable endianness and you have a real mess.
4224 The way this works is:
4225 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
4226 double-precision value will be split across two logical registers.
4227 The lower-numbered logical register will hold the low-order bits,
4228 regardless of the processor's endianness.
4229 - If we are on a 64-bit processor, and we are looking for a
4230 single-precision value, it will be in the low ordered bits
4231 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
4232 save slot in memory.
4233 - If we are in 64-bit mode, everything is straightforward.
4235 Note that this code only deals with "live" registers at the top of the
4236 stack. We will attempt to deal with saved registers later, when
4237 the raw/cooked register interface is in place. (We need a general
4238 interface that can deal with dynamic saved register sizes -- fp
4239 regs could be 32 bits wide in one frame and 64 on the frame above
4242 static struct type
*
4243 mips_float_register_type (void)
4245 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4246 return builtin_type_ieee_single_big
;
4248 return builtin_type_ieee_single_little
;
4251 static struct type
*
4252 mips_double_register_type (void)
4254 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4255 return builtin_type_ieee_double_big
;
4257 return builtin_type_ieee_double_little
;
4260 /* Copy a 32-bit single-precision value from the current frame
4261 into rare_buffer. */
4264 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
4267 int raw_size
= register_size (current_gdbarch
, regno
);
4268 char *raw_buffer
= alloca (raw_size
);
4270 if (!frame_register_read (frame
, regno
, raw_buffer
))
4271 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
4274 /* We have a 64-bit value for this register. Find the low-order
4278 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4283 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
4287 memcpy (rare_buffer
, raw_buffer
, 4);
4291 /* Copy a 64-bit double-precision value from the current frame into
4292 rare_buffer. This may include getting half of it from the next
4296 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
4299 int raw_size
= register_size (current_gdbarch
, regno
);
4301 if (raw_size
== 8 && !mips2_fp_compat ())
4303 /* We have a 64-bit value for this register, and we should use
4305 if (!frame_register_read (frame
, regno
, rare_buffer
))
4306 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
4310 if ((regno
- mips_regnum (current_gdbarch
)->fp0
) & 1)
4311 internal_error (__FILE__
, __LINE__
,
4312 "mips_read_fp_register_double: bad access to "
4313 "odd-numbered FP register");
4315 /* mips_read_fp_register_single will find the correct 32 bits from
4317 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4319 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
4320 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
4324 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
4325 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
4331 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
4333 { /* do values for FP (float) regs */
4335 double doub
, flt1
; /* doubles extracted from raw hex data */
4339 (char *) alloca (2 *
4340 register_size (current_gdbarch
,
4341 mips_regnum (current_gdbarch
)->fp0
));
4343 fprintf_filtered (file
, "%s:", REGISTER_NAME (regnum
));
4344 fprintf_filtered (file
, "%*s", 4 - (int) strlen (REGISTER_NAME (regnum
)),
4347 if (register_size (current_gdbarch
, regnum
) == 4 || mips2_fp_compat ())
4349 /* 4-byte registers: Print hex and floating. Also print even
4350 numbered registers as doubles. */
4351 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4352 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4354 print_scalar_formatted (raw_buffer
, builtin_type_uint32
, 'x', 'w',
4357 fprintf_filtered (file
, " flt: ");
4359 fprintf_filtered (file
, " <invalid float> ");
4361 fprintf_filtered (file
, "%-17.9g", flt1
);
4363 if (regnum
% 2 == 0)
4365 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4366 doub
= unpack_double (mips_double_register_type (), raw_buffer
,
4369 fprintf_filtered (file
, " dbl: ");
4371 fprintf_filtered (file
, "<invalid double>");
4373 fprintf_filtered (file
, "%-24.17g", doub
);
4378 /* Eight byte registers: print each one as hex, float and double. */
4379 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4380 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4382 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4383 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv2
);
4386 print_scalar_formatted (raw_buffer
, builtin_type_uint64
, 'x', 'g',
4389 fprintf_filtered (file
, " flt: ");
4391 fprintf_filtered (file
, "<invalid float>");
4393 fprintf_filtered (file
, "%-17.9g", flt1
);
4395 fprintf_filtered (file
, " dbl: ");
4397 fprintf_filtered (file
, "<invalid double>");
4399 fprintf_filtered (file
, "%-24.17g", doub
);
4404 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
4405 int regnum
, int all
)
4407 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4408 char raw_buffer
[MAX_REGISTER_SIZE
];
4411 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4413 mips_print_fp_register (file
, frame
, regnum
);
4417 /* Get the data in raw format. */
4418 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4420 fprintf_filtered (file
, "%s: [Invalid]", REGISTER_NAME (regnum
));
4424 fputs_filtered (REGISTER_NAME (regnum
), file
);
4426 /* The problem with printing numeric register names (r26, etc.) is that
4427 the user can't use them on input. Probably the best solution is to
4428 fix it so that either the numeric or the funky (a2, etc.) names
4429 are accepted on input. */
4430 if (regnum
< MIPS_NUMREGS
)
4431 fprintf_filtered (file
, "(r%d): ", regnum
);
4433 fprintf_filtered (file
, ": ");
4435 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4437 register_size (current_gdbarch
,
4438 regnum
) - register_size (current_gdbarch
, regnum
);
4442 print_scalar_formatted (raw_buffer
+ offset
,
4443 gdbarch_register_type (gdbarch
, regnum
), 'x', 0,
4447 /* Replacement for generic do_registers_info.
4448 Print regs in pretty columns. */
4451 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4454 fprintf_filtered (file
, " ");
4455 mips_print_fp_register (file
, frame
, regnum
);
4456 fprintf_filtered (file
, "\n");
4461 /* Print a row's worth of GP (int) registers, with name labels above */
4464 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4467 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4468 /* do values for GP (int) regs */
4469 char raw_buffer
[MAX_REGISTER_SIZE
];
4470 int ncols
= (mips_isa_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols per row */
4474 /* For GP registers, we print a separate row of names above the vals */
4475 fprintf_filtered (file
, " ");
4476 for (col
= 0, regnum
= start_regnum
;
4477 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
; regnum
++)
4479 if (*REGISTER_NAME (regnum
) == '\0')
4480 continue; /* unused register */
4481 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
4483 break; /* end the row: reached FP register */
4484 fprintf_filtered (file
,
4485 mips_isa_regsize (current_gdbarch
) == 8 ? "%17s" : "%9s",
4486 REGISTER_NAME (regnum
));
4489 /* print the R0 to R31 names */
4490 if ((start_regnum
% NUM_REGS
) < MIPS_NUMREGS
)
4491 fprintf_filtered (file
, "\n R%-4d", start_regnum
% NUM_REGS
);
4493 fprintf_filtered (file
, "\n ");
4495 /* now print the values in hex, 4 or 8 to the row */
4496 for (col
= 0, regnum
= start_regnum
;
4497 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
; regnum
++)
4499 if (*REGISTER_NAME (regnum
) == '\0')
4500 continue; /* unused register */
4501 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
4503 break; /* end row: reached FP register */
4504 /* OK: get the data in raw format. */
4505 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4506 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
4507 /* pad small registers */
4509 byte
< (mips_isa_regsize (current_gdbarch
)
4510 - register_size (current_gdbarch
, regnum
)); byte
++)
4511 printf_filtered (" ");
4512 /* Now print the register value in hex, endian order. */
4513 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4515 register_size (current_gdbarch
,
4516 regnum
) - register_size (current_gdbarch
, regnum
);
4517 byte
< register_size (current_gdbarch
, regnum
); byte
++)
4518 fprintf_filtered (file
, "%02x", (unsigned char) raw_buffer
[byte
]);
4520 for (byte
= register_size (current_gdbarch
, regnum
) - 1;
4522 fprintf_filtered (file
, "%02x", (unsigned char) raw_buffer
[byte
]);
4523 fprintf_filtered (file
, " ");
4526 if (col
> 0) /* ie. if we actually printed anything... */
4527 fprintf_filtered (file
, "\n");
4532 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
4535 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
4536 struct frame_info
*frame
, int regnum
, int all
)
4538 if (regnum
!= -1) /* do one specified register */
4540 gdb_assert (regnum
>= NUM_REGS
);
4541 if (*(REGISTER_NAME (regnum
)) == '\0')
4542 error ("Not a valid register for the current processor type");
4544 mips_print_register (file
, frame
, regnum
, 0);
4545 fprintf_filtered (file
, "\n");
4548 /* do all (or most) registers */
4551 while (regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
)
4553 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
4556 if (all
) /* true for "INFO ALL-REGISTERS" command */
4557 regnum
= print_fp_register_row (file
, frame
, regnum
);
4559 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
4562 regnum
= print_gp_register_row (file
, frame
, regnum
);
4567 /* Is this a branch with a delay slot? */
4569 static int is_delayed (unsigned long);
4572 is_delayed (unsigned long insn
)
4575 for (i
= 0; i
< NUMOPCODES
; ++i
)
4576 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
4577 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
4579 return (i
< NUMOPCODES
4580 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
4581 | INSN_COND_BRANCH_DELAY
4582 | INSN_COND_BRANCH_LIKELY
)));
4586 mips_step_skips_delay (CORE_ADDR pc
)
4588 char buf
[MIPS_INSTLEN
];
4590 /* There is no branch delay slot on MIPS16. */
4591 if (pc_is_mips16 (pc
))
4594 if (target_read_memory (pc
, buf
, MIPS_INSTLEN
) != 0)
4595 /* If error reading memory, guess that it is not a delayed branch. */
4597 return is_delayed ((unsigned long)
4598 extract_unsigned_integer (buf
, MIPS_INSTLEN
));
4601 /* Skip the PC past function prologue instructions (32-bit version).
4602 This is a helper function for mips_skip_prologue. */
4605 mips32_skip_prologue (CORE_ADDR pc
)
4609 int seen_sp_adjust
= 0;
4610 int load_immediate_bytes
= 0;
4612 /* Find an upper bound on the prologue. */
4613 end_pc
= skip_prologue_using_sal (pc
);
4615 end_pc
= pc
+ 100; /* Magic. */
4617 /* Skip the typical prologue instructions. These are the stack adjustment
4618 instruction and the instructions that save registers on the stack
4619 or in the gcc frame. */
4620 for (; pc
< end_pc
; pc
+= MIPS_INSTLEN
)
4622 unsigned long high_word
;
4624 inst
= mips_fetch_instruction (pc
);
4625 high_word
= (inst
>> 16) & 0xffff;
4627 if (high_word
== 0x27bd /* addiu $sp,$sp,offset */
4628 || high_word
== 0x67bd) /* daddiu $sp,$sp,offset */
4630 else if (inst
== 0x03a1e823 || /* subu $sp,$sp,$at */
4631 inst
== 0x03a8e823) /* subu $sp,$sp,$t0 */
4633 else if (((inst
& 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
4634 || (inst
& 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
4635 && (inst
& 0x001F0000)) /* reg != $zero */
4638 else if ((inst
& 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
4640 else if ((inst
& 0xF3E00000) == 0xA3C00000 && (inst
& 0x001F0000))
4642 continue; /* reg != $zero */
4644 /* move $s8,$sp. With different versions of gas this will be either
4645 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
4646 Accept any one of these. */
4647 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
4650 else if ((inst
& 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
4652 else if (high_word
== 0x3c1c) /* lui $gp,n */
4654 else if (high_word
== 0x279c) /* addiu $gp,$gp,n */
4656 else if (inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
4657 || inst
== 0x033ce021) /* addu $gp,$t9,$gp */
4659 /* The following instructions load $at or $t0 with an immediate
4660 value in preparation for a stack adjustment via
4661 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
4662 a local variable, so we accept them only before a stack adjustment
4663 instruction was seen. */
4664 else if (!seen_sp_adjust
)
4666 if (high_word
== 0x3c01 || /* lui $at,n */
4667 high_word
== 0x3c08) /* lui $t0,n */
4669 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
4672 else if (high_word
== 0x3421 || /* ori $at,$at,n */
4673 high_word
== 0x3508 || /* ori $t0,$t0,n */
4674 high_word
== 0x3401 || /* ori $at,$zero,n */
4675 high_word
== 0x3408) /* ori $t0,$zero,n */
4677 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
4687 /* In a frameless function, we might have incorrectly
4688 skipped some load immediate instructions. Undo the skipping
4689 if the load immediate was not followed by a stack adjustment. */
4690 if (load_immediate_bytes
&& !seen_sp_adjust
)
4691 pc
-= load_immediate_bytes
;
4695 /* Skip the PC past function prologue instructions (16-bit version).
4696 This is a helper function for mips_skip_prologue. */
4699 mips16_skip_prologue (CORE_ADDR pc
)
4702 int extend_bytes
= 0;
4703 int prev_extend_bytes
;
4705 /* Table of instructions likely to be found in a function prologue. */
4708 unsigned short inst
;
4709 unsigned short mask
;
4715 , /* addiu $sp,offset */
4718 , /* daddiu $sp,offset */
4721 , /* sw reg,n($sp) */
4724 , /* sd reg,n($sp) */
4727 , /* sw $ra,n($sp) */
4730 , /* sd $ra,n($sp) */
4736 , /* sw $a0-$a3,n($s1) */
4739 , /* move reg,$a0-$a3 */
4742 , /* entry pseudo-op */
4745 , /* addiu $s1,$sp,n */
4747 0, 0} /* end of table marker */
4750 /* Find an upper bound on the prologue. */
4751 end_pc
= skip_prologue_using_sal (pc
);
4753 end_pc
= pc
+ 100; /* Magic. */
4755 /* Skip the typical prologue instructions. These are the stack adjustment
4756 instruction and the instructions that save registers on the stack
4757 or in the gcc frame. */
4758 for (; pc
< end_pc
; pc
+= MIPS16_INSTLEN
)
4760 unsigned short inst
;
4763 inst
= mips_fetch_instruction (pc
);
4765 /* Normally we ignore an extend instruction. However, if it is
4766 not followed by a valid prologue instruction, we must adjust
4767 the pc back over the extend so that it won't be considered
4768 part of the prologue. */
4769 if ((inst
& 0xf800) == 0xf000) /* extend */
4771 extend_bytes
= MIPS16_INSTLEN
;
4774 prev_extend_bytes
= extend_bytes
;
4777 /* Check for other valid prologue instructions besides extend. */
4778 for (i
= 0; table
[i
].mask
!= 0; i
++)
4779 if ((inst
& table
[i
].mask
) == table
[i
].inst
) /* found, get out */
4781 if (table
[i
].mask
!= 0) /* it was in table? */
4782 continue; /* ignore it */
4786 /* Return the current pc, adjusted backwards by 2 if
4787 the previous instruction was an extend. */
4788 return pc
- prev_extend_bytes
;
4794 /* To skip prologues, I use this predicate. Returns either PC itself
4795 if the code at PC does not look like a function prologue; otherwise
4796 returns an address that (if we're lucky) follows the prologue. If
4797 LENIENT, then we must skip everything which is involved in setting
4798 up the frame (it's OK to skip more, just so long as we don't skip
4799 anything which might clobber the registers which are being saved.
4800 We must skip more in the case where part of the prologue is in the
4801 delay slot of a non-prologue instruction). */
4804 mips_skip_prologue (CORE_ADDR pc
)
4806 /* See if we can determine the end of the prologue via the symbol table.
4807 If so, then return either PC, or the PC after the prologue, whichever
4810 CORE_ADDR post_prologue_pc
= after_prologue (pc
, NULL
);
4812 if (post_prologue_pc
!= 0)
4813 return max (pc
, post_prologue_pc
);
4815 /* Can't determine prologue from the symbol table, need to examine
4818 if (pc_is_mips16 (pc
))
4819 return mips16_skip_prologue (pc
);
4821 return mips32_skip_prologue (pc
);
4824 /* Exported procedure: Is PC in the signal trampoline code */
4827 mips_pc_in_sigtramp (CORE_ADDR pc
, char *ignore
)
4829 if (sigtramp_address
== 0)
4831 return (pc
>= sigtramp_address
&& pc
< sigtramp_end
);
4834 /* Root of all "set mips "/"show mips " commands. This will eventually be
4835 used for all MIPS-specific commands. */
4838 show_mips_command (char *args
, int from_tty
)
4840 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
4844 set_mips_command (char *args
, int from_tty
)
4847 ("\"set mips\" must be followed by an appropriate subcommand.\n");
4848 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
4851 /* Commands to show/set the MIPS FPU type. */
4854 show_mipsfpu_command (char *args
, int from_tty
)
4857 switch (MIPS_FPU_TYPE
)
4859 case MIPS_FPU_SINGLE
:
4860 fpu
= "single-precision";
4862 case MIPS_FPU_DOUBLE
:
4863 fpu
= "double-precision";
4866 fpu
= "absent (none)";
4869 internal_error (__FILE__
, __LINE__
, "bad switch");
4871 if (mips_fpu_type_auto
)
4873 ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
4877 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
4882 set_mipsfpu_command (char *args
, int from_tty
)
4885 ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
4886 show_mipsfpu_command (args
, from_tty
);
4890 set_mipsfpu_single_command (char *args
, int from_tty
)
4892 struct gdbarch_info info
;
4893 gdbarch_info_init (&info
);
4894 mips_fpu_type
= MIPS_FPU_SINGLE
;
4895 mips_fpu_type_auto
= 0;
4896 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4897 instead of relying on globals. Doing that would let generic code
4898 handle the search for this specific architecture. */
4899 if (!gdbarch_update_p (info
))
4900 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
4904 set_mipsfpu_double_command (char *args
, int from_tty
)
4906 struct gdbarch_info info
;
4907 gdbarch_info_init (&info
);
4908 mips_fpu_type
= MIPS_FPU_DOUBLE
;
4909 mips_fpu_type_auto
= 0;
4910 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4911 instead of relying on globals. Doing that would let generic code
4912 handle the search for this specific architecture. */
4913 if (!gdbarch_update_p (info
))
4914 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
4918 set_mipsfpu_none_command (char *args
, int from_tty
)
4920 struct gdbarch_info info
;
4921 gdbarch_info_init (&info
);
4922 mips_fpu_type
= MIPS_FPU_NONE
;
4923 mips_fpu_type_auto
= 0;
4924 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4925 instead of relying on globals. Doing that would let generic code
4926 handle the search for this specific architecture. */
4927 if (!gdbarch_update_p (info
))
4928 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
4932 set_mipsfpu_auto_command (char *args
, int from_tty
)
4934 mips_fpu_type_auto
= 1;
4937 /* Attempt to identify the particular processor model by reading the
4938 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
4939 the relevant processor still exists (it dates back to '94) and
4940 secondly this is not the way to do this. The processor type should
4941 be set by forcing an architecture change. */
4944 deprecated_mips_set_processor_regs_hack (void)
4946 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4949 prid
= read_register (PRID_REGNUM
);
4951 if ((prid
& ~0xf) == 0x700)
4952 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
4955 /* Just like reinit_frame_cache, but with the right arguments to be
4956 callable as an sfunc. */
4959 reinit_frame_cache_sfunc (char *args
, int from_tty
,
4960 struct cmd_list_element
*c
)
4962 reinit_frame_cache ();
4966 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
4968 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4969 mips_extra_func_info_t proc_desc
;
4971 /* Search for the function containing this address. Set the low bit
4972 of the address when searching, in case we were given an even address
4973 that is the start of a 16-bit function. If we didn't do this,
4974 the search would fail because the symbol table says the function
4975 starts at an odd address, i.e. 1 byte past the given address. */
4976 memaddr
= ADDR_BITS_REMOVE (memaddr
);
4977 proc_desc
= non_heuristic_proc_desc (make_mips16_addr (memaddr
), NULL
);
4979 /* Make an attempt to determine if this is a 16-bit function. If
4980 the procedure descriptor exists and the address therein is odd,
4981 it's definitely a 16-bit function. Otherwise, we have to just
4982 guess that if the address passed in is odd, it's 16-bits. */
4983 /* FIXME: cagney/2003-06-26: Is this even necessary? The
4984 disassembler needs to be able to locally determine the ISA, and
4985 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
4989 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
4990 info
->mach
= bfd_mach_mips16
;
4994 if (pc_is_mips16 (memaddr
))
4995 info
->mach
= bfd_mach_mips16
;
4998 /* Round down the instruction address to the appropriate boundary. */
4999 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
5001 /* Set the disassembler options. */
5002 if (tdep
->mips_abi
== MIPS_ABI_N32
|| tdep
->mips_abi
== MIPS_ABI_N64
)
5004 /* Set up the disassembler info, so that we get the right
5005 register names from libopcodes. */
5006 if (tdep
->mips_abi
== MIPS_ABI_N32
)
5007 info
->disassembler_options
= "gpr-names=n32";
5009 info
->disassembler_options
= "gpr-names=64";
5010 info
->flavour
= bfd_target_elf_flavour
;
5013 /* This string is not recognized explicitly by the disassembler,
5014 but it tells the disassembler to not try to guess the ABI from
5015 the bfd elf headers, such that, if the user overrides the ABI
5016 of a program linked as NewABI, the disassembly will follow the
5017 register naming conventions specified by the user. */
5018 info
->disassembler_options
= "gpr-names=32";
5020 /* Call the appropriate disassembler based on the target endian-ness. */
5021 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5022 return print_insn_big_mips (memaddr
, info
);
5024 return print_insn_little_mips (memaddr
, info
);
5027 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
5028 counter value to determine whether a 16- or 32-bit breakpoint should be
5029 used. It returns a pointer to a string of bytes that encode a breakpoint
5030 instruction, stores the length of the string to *lenptr, and adjusts pc
5031 (if necessary) to point to the actual memory location where the
5032 breakpoint should be inserted. */
5034 static const unsigned char *
5035 mips_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
5037 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5039 if (pc_is_mips16 (*pcptr
))
5041 static unsigned char mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
5042 *pcptr
= unmake_mips16_addr (*pcptr
);
5043 *lenptr
= sizeof (mips16_big_breakpoint
);
5044 return mips16_big_breakpoint
;
5048 /* The IDT board uses an unusual breakpoint value, and
5049 sometimes gets confused when it sees the usual MIPS
5050 breakpoint instruction. */
5051 static unsigned char big_breakpoint
[] = { 0, 0x5, 0, 0xd };
5052 static unsigned char pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
5053 static unsigned char idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
5055 *lenptr
= sizeof (big_breakpoint
);
5057 if (strcmp (target_shortname
, "mips") == 0)
5058 return idt_big_breakpoint
;
5059 else if (strcmp (target_shortname
, "ddb") == 0
5060 || strcmp (target_shortname
, "pmon") == 0
5061 || strcmp (target_shortname
, "lsi") == 0)
5062 return pmon_big_breakpoint
;
5064 return big_breakpoint
;
5069 if (pc_is_mips16 (*pcptr
))
5071 static unsigned char mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
5072 *pcptr
= unmake_mips16_addr (*pcptr
);
5073 *lenptr
= sizeof (mips16_little_breakpoint
);
5074 return mips16_little_breakpoint
;
5078 static unsigned char little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
5079 static unsigned char pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
5080 static unsigned char idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
5082 *lenptr
= sizeof (little_breakpoint
);
5084 if (strcmp (target_shortname
, "mips") == 0)
5085 return idt_little_breakpoint
;
5086 else if (strcmp (target_shortname
, "ddb") == 0
5087 || strcmp (target_shortname
, "pmon") == 0
5088 || strcmp (target_shortname
, "lsi") == 0)
5089 return pmon_little_breakpoint
;
5091 return little_breakpoint
;
5096 /* If PC is in a mips16 call or return stub, return the address of the target
5097 PC, which is either the callee or the caller. There are several
5098 cases which must be handled:
5100 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5101 target PC is in $31 ($ra).
5102 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5103 and the target PC is in $2.
5104 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5105 before the jal instruction, this is effectively a call stub
5106 and the the target PC is in $2. Otherwise this is effectively
5107 a return stub and the target PC is in $18.
5109 See the source code for the stubs in gcc/config/mips/mips16.S for
5112 This function implements the SKIP_TRAMPOLINE_CODE macro.
5116 mips_skip_stub (CORE_ADDR pc
)
5119 CORE_ADDR start_addr
;
5121 /* Find the starting address and name of the function containing the PC. */
5122 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
5125 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5126 target PC is in $31 ($ra). */
5127 if (strcmp (name
, "__mips16_ret_sf") == 0
5128 || strcmp (name
, "__mips16_ret_df") == 0)
5129 return read_signed_register (RA_REGNUM
);
5131 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5133 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5134 and the target PC is in $2. */
5135 if (name
[19] >= '0' && name
[19] <= '9')
5136 return read_signed_register (2);
5138 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5139 before the jal instruction, this is effectively a call stub
5140 and the the target PC is in $2. Otherwise this is effectively
5141 a return stub and the target PC is in $18. */
5142 else if (name
[19] == 's' || name
[19] == 'd')
5144 if (pc
== start_addr
)
5146 /* Check if the target of the stub is a compiler-generated
5147 stub. Such a stub for a function bar might have a name
5148 like __fn_stub_bar, and might look like this:
5153 la $1,bar (becomes a lui/addiu pair)
5155 So scan down to the lui/addi and extract the target
5156 address from those two instructions. */
5158 CORE_ADDR target_pc
= read_signed_register (2);
5162 /* See if the name of the target function is __fn_stub_*. */
5163 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) ==
5166 if (strncmp (name
, "__fn_stub_", 10) != 0
5167 && strcmp (name
, "etext") != 0
5168 && strcmp (name
, "_etext") != 0)
5171 /* Scan through this _fn_stub_ code for the lui/addiu pair.
5172 The limit on the search is arbitrarily set to 20
5173 instructions. FIXME. */
5174 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSTLEN
)
5176 inst
= mips_fetch_instruction (target_pc
);
5177 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
5178 pc
= (inst
<< 16) & 0xffff0000; /* high word */
5179 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
5180 return pc
| (inst
& 0xffff); /* low word */
5183 /* Couldn't find the lui/addui pair, so return stub address. */
5187 /* This is the 'return' part of a call stub. The return
5188 address is in $r18. */
5189 return read_signed_register (18);
5192 return 0; /* not a stub */
5196 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
5197 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
5200 mips_in_call_stub (CORE_ADDR pc
, char *name
)
5202 CORE_ADDR start_addr
;
5204 /* Find the starting address of the function containing the PC. If the
5205 caller didn't give us a name, look it up at the same time. */
5206 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) ==
5210 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5212 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
5213 if (name
[19] >= '0' && name
[19] <= '9')
5215 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5216 before the jal instruction, this is effectively a call stub. */
5217 else if (name
[19] == 's' || name
[19] == 'd')
5218 return pc
== start_addr
;
5221 return 0; /* not a stub */
5225 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
5226 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
5229 mips_in_return_stub (CORE_ADDR pc
, char *name
)
5231 CORE_ADDR start_addr
;
5233 /* Find the starting address of the function containing the PC. */
5234 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
5237 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
5238 if (strcmp (name
, "__mips16_ret_sf") == 0
5239 || strcmp (name
, "__mips16_ret_df") == 0)
5242 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
5243 i.e. after the jal instruction, this is effectively a return stub. */
5244 if (strncmp (name
, "__mips16_call_stub_", 19) == 0
5245 && (name
[19] == 's' || name
[19] == 'd') && pc
!= start_addr
)
5248 return 0; /* not a stub */
5252 /* Return non-zero if the PC is in a library helper function that should
5253 be ignored. This implements the IGNORE_HELPER_CALL macro. */
5256 mips_ignore_helper (CORE_ADDR pc
)
5260 /* Find the starting address and name of the function containing the PC. */
5261 if (find_pc_partial_function (pc
, &name
, NULL
, NULL
) == 0)
5264 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
5265 that we want to ignore. */
5266 return (strcmp (name
, "__mips16_ret_sf") == 0
5267 || strcmp (name
, "__mips16_ret_df") == 0);
5271 /* Convert a dbx stab register number (from `r' declaration) to a GDB
5272 [1 * NUM_REGS .. 2 * NUM_REGS) REGNUM. */
5275 mips_stab_reg_to_regnum (int num
)
5278 if (num
>= 0 && num
< 32)
5280 else if (num
>= 38 && num
< 70)
5281 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 38;
5283 regnum
= mips_regnum (current_gdbarch
)->hi
;
5285 regnum
= mips_regnum (current_gdbarch
)->lo
;
5287 /* This will hopefully (eventually) provoke a warning. Should
5288 we be calling complaint() here? */
5289 return NUM_REGS
+ NUM_PSEUDO_REGS
;
5290 return NUM_REGS
+ regnum
;
5294 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
5295 NUM_REGS .. 2 * NUM_REGS) REGNUM. */
5298 mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num
)
5301 if (num
>= 0 && num
< 32)
5303 else if (num
>= 32 && num
< 64)
5304 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 32;
5306 regnum
= mips_regnum (current_gdbarch
)->hi
;
5308 regnum
= mips_regnum (current_gdbarch
)->lo
;
5310 /* This will hopefully (eventually) provoke a warning. Should we
5311 be calling complaint() here? */
5312 return NUM_REGS
+ NUM_PSEUDO_REGS
;
5313 return NUM_REGS
+ regnum
;
5317 mips_register_sim_regno (int regnum
)
5319 /* Only makes sense to supply raw registers. */
5320 gdb_assert (regnum
>= 0 && regnum
< NUM_REGS
);
5321 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
5322 decide if it is valid. Should instead define a standard sim/gdb
5323 register numbering scheme. */
5324 if (REGISTER_NAME (NUM_REGS
+ regnum
) != NULL
5325 && REGISTER_NAME (NUM_REGS
+ regnum
)[0] != '\0')
5328 return LEGACY_SIM_REGNO_IGNORE
;
5332 /* Convert an integer into an address. By first converting the value
5333 into a pointer and then extracting it signed, the address is
5334 guarenteed to be correctly sign extended. */
5337 mips_integer_to_address (struct type
*type
, void *buf
)
5339 char *tmp
= alloca (TYPE_LENGTH (builtin_type_void_data_ptr
));
5340 LONGEST val
= unpack_long (type
, buf
);
5341 store_signed_integer (tmp
, TYPE_LENGTH (builtin_type_void_data_ptr
), val
);
5342 return extract_signed_integer (tmp
,
5343 TYPE_LENGTH (builtin_type_void_data_ptr
));
5347 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
5349 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
5350 const char *name
= bfd_get_section_name (abfd
, sect
);
5352 if (*abip
!= MIPS_ABI_UNKNOWN
)
5355 if (strncmp (name
, ".mdebug.", 8) != 0)
5358 if (strcmp (name
, ".mdebug.abi32") == 0)
5359 *abip
= MIPS_ABI_O32
;
5360 else if (strcmp (name
, ".mdebug.abiN32") == 0)
5361 *abip
= MIPS_ABI_N32
;
5362 else if (strcmp (name
, ".mdebug.abi64") == 0)
5363 *abip
= MIPS_ABI_N64
;
5364 else if (strcmp (name
, ".mdebug.abiO64") == 0)
5365 *abip
= MIPS_ABI_O64
;
5366 else if (strcmp (name
, ".mdebug.eabi32") == 0)
5367 *abip
= MIPS_ABI_EABI32
;
5368 else if (strcmp (name
, ".mdebug.eabi64") == 0)
5369 *abip
= MIPS_ABI_EABI64
;
5371 warning ("unsupported ABI %s.", name
+ 8);
5374 static enum mips_abi
5375 global_mips_abi (void)
5379 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
5380 if (mips_abi_strings
[i
] == mips_abi_string
)
5381 return (enum mips_abi
) i
;
5383 internal_error (__FILE__
, __LINE__
, "unknown ABI string");
5386 static struct gdbarch
*
5387 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
5389 struct gdbarch
*gdbarch
;
5390 struct gdbarch_tdep
*tdep
;
5392 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
5394 enum mips_fpu_type fpu_type
;
5396 /* First of all, extract the elf_flags, if available. */
5397 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
5398 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
5399 else if (arches
!= NULL
)
5400 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
5404 fprintf_unfiltered (gdb_stdlog
,
5405 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
5407 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
5408 switch ((elf_flags
& EF_MIPS_ABI
))
5410 case E_MIPS_ABI_O32
:
5411 found_abi
= MIPS_ABI_O32
;
5413 case E_MIPS_ABI_O64
:
5414 found_abi
= MIPS_ABI_O64
;
5416 case E_MIPS_ABI_EABI32
:
5417 found_abi
= MIPS_ABI_EABI32
;
5419 case E_MIPS_ABI_EABI64
:
5420 found_abi
= MIPS_ABI_EABI64
;
5423 if ((elf_flags
& EF_MIPS_ABI2
))
5424 found_abi
= MIPS_ABI_N32
;
5426 found_abi
= MIPS_ABI_UNKNOWN
;
5430 /* GCC creates a pseudo-section whose name describes the ABI. */
5431 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
5432 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
5434 /* If we have no usefu BFD information, use the ABI from the last
5435 MIPS architecture (if there is one). */
5436 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
5437 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
5439 /* Try the architecture for any hint of the correct ABI. */
5440 if (found_abi
== MIPS_ABI_UNKNOWN
5441 && info
.bfd_arch_info
!= NULL
5442 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5444 switch (info
.bfd_arch_info
->mach
)
5446 case bfd_mach_mips3900
:
5447 found_abi
= MIPS_ABI_EABI32
;
5449 case bfd_mach_mips4100
:
5450 case bfd_mach_mips5000
:
5451 found_abi
= MIPS_ABI_EABI64
;
5453 case bfd_mach_mips8000
:
5454 case bfd_mach_mips10000
:
5455 /* On Irix, ELF64 executables use the N64 ABI. The
5456 pseudo-sections which describe the ABI aren't present
5457 on IRIX. (Even for executables created by gcc.) */
5458 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
5459 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5460 found_abi
= MIPS_ABI_N64
;
5462 found_abi
= MIPS_ABI_N32
;
5468 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
5471 /* What has the user specified from the command line? */
5472 wanted_abi
= global_mips_abi ();
5474 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
5477 /* Now that we have found what the ABI for this binary would be,
5478 check whether the user is overriding it. */
5479 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
5480 mips_abi
= wanted_abi
;
5481 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
5482 mips_abi
= found_abi
;
5484 mips_abi
= MIPS_ABI_O32
;
5486 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
5489 /* Also used when doing an architecture lookup. */
5491 fprintf_unfiltered (gdb_stdlog
,
5492 "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n",
5493 mips64_transfers_32bit_regs_p
);
5495 /* Determine the MIPS FPU type. */
5496 if (!mips_fpu_type_auto
)
5497 fpu_type
= mips_fpu_type
;
5498 else if (info
.bfd_arch_info
!= NULL
5499 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5500 switch (info
.bfd_arch_info
->mach
)
5502 case bfd_mach_mips3900
:
5503 case bfd_mach_mips4100
:
5504 case bfd_mach_mips4111
:
5505 fpu_type
= MIPS_FPU_NONE
;
5507 case bfd_mach_mips4650
:
5508 fpu_type
= MIPS_FPU_SINGLE
;
5511 fpu_type
= MIPS_FPU_DOUBLE
;
5514 else if (arches
!= NULL
)
5515 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
5517 fpu_type
= MIPS_FPU_DOUBLE
;
5519 fprintf_unfiltered (gdb_stdlog
,
5520 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
5522 /* try to find a pre-existing architecture */
5523 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
5525 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
5527 /* MIPS needs to be pedantic about which ABI the object is
5529 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
5531 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
5533 /* Need to be pedantic about which register virtual size is
5535 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
5536 != mips64_transfers_32bit_regs_p
)
5538 /* Be pedantic about which FPU is selected. */
5539 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
5541 return arches
->gdbarch
;
5544 /* Need a new architecture. Fill in a target specific vector. */
5545 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
5546 gdbarch
= gdbarch_alloc (&info
, tdep
);
5547 tdep
->elf_flags
= elf_flags
;
5548 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
5549 tdep
->found_abi
= found_abi
;
5550 tdep
->mips_abi
= mips_abi
;
5551 tdep
->mips_fpu_type
= fpu_type
;
5553 /* Initially set everything according to the default ABI/ISA. */
5554 set_gdbarch_short_bit (gdbarch
, 16);
5555 set_gdbarch_int_bit (gdbarch
, 32);
5556 set_gdbarch_float_bit (gdbarch
, 32);
5557 set_gdbarch_double_bit (gdbarch
, 64);
5558 set_gdbarch_long_double_bit (gdbarch
, 64);
5559 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
5560 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
5561 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
5563 set_gdbarch_elf_make_msymbol_special (gdbarch
,
5564 mips_elf_make_msymbol_special
);
5566 /* Fill in the OS dependant register numbers and names. */
5568 const char **reg_names
;
5569 struct mips_regnum
*regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
,
5570 struct mips_regnum
);
5571 if (info
.osabi
== GDB_OSABI_IRIX
)
5576 regnum
->badvaddr
= 66;
5579 regnum
->fp_control_status
= 69;
5580 regnum
->fp_implementation_revision
= 70;
5582 reg_names
= mips_irix_reg_names
;
5586 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
5587 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
5588 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
5589 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
5590 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
5591 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
5592 regnum
->fp_control_status
= 70;
5593 regnum
->fp_implementation_revision
= 71;
5595 if (info
.bfd_arch_info
!= NULL
5596 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
5597 reg_names
= mips_tx39_reg_names
;
5599 reg_names
= mips_generic_reg_names
;
5601 /* FIXME: cagney/2003-11-15: For MIPS, hasn't PC_REGNUM been
5602 replaced by read_pc? */
5603 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
);
5604 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
5605 set_gdbarch_num_regs (gdbarch
, num_regs
);
5606 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
5607 set_gdbarch_register_name (gdbarch
, mips_register_name
);
5608 tdep
->mips_processor_reg_names
= reg_names
;
5609 tdep
->regnum
= regnum
;
5615 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
5616 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
5617 tdep
->mips_default_abi_regsize
= 4;
5618 tdep
->mips_default_stack_argsize
= 4;
5619 tdep
->mips_fp_register_double
= 0;
5620 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
5621 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5622 tdep
->default_mask_address_p
= 0;
5623 set_gdbarch_long_bit (gdbarch
, 32);
5624 set_gdbarch_ptr_bit (gdbarch
, 32);
5625 set_gdbarch_long_long_bit (gdbarch
, 64);
5628 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
5629 set_gdbarch_deprecated_store_return_value (gdbarch
,
5630 mips_o64_store_return_value
);
5631 set_gdbarch_deprecated_extract_return_value (gdbarch
,
5632 mips_o64_extract_return_value
);
5633 tdep
->mips_default_abi_regsize
= 8;
5634 tdep
->mips_default_stack_argsize
= 8;
5635 tdep
->mips_fp_register_double
= 1;
5636 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
5637 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5638 tdep
->default_mask_address_p
= 0;
5639 set_gdbarch_long_bit (gdbarch
, 32);
5640 set_gdbarch_ptr_bit (gdbarch
, 32);
5641 set_gdbarch_long_long_bit (gdbarch
, 64);
5642 set_gdbarch_use_struct_convention (gdbarch
,
5643 always_use_struct_convention
);
5645 case MIPS_ABI_EABI32
:
5646 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5647 set_gdbarch_deprecated_store_return_value (gdbarch
,
5648 mips_eabi_store_return_value
);
5649 set_gdbarch_deprecated_extract_return_value (gdbarch
,
5650 mips_eabi_extract_return_value
);
5651 tdep
->mips_default_abi_regsize
= 4;
5652 tdep
->mips_default_stack_argsize
= 4;
5653 tdep
->mips_fp_register_double
= 0;
5654 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5655 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5656 tdep
->default_mask_address_p
= 0;
5657 set_gdbarch_long_bit (gdbarch
, 32);
5658 set_gdbarch_ptr_bit (gdbarch
, 32);
5659 set_gdbarch_long_long_bit (gdbarch
, 64);
5660 set_gdbarch_deprecated_reg_struct_has_addr
5661 (gdbarch
, mips_eabi_reg_struct_has_addr
);
5662 set_gdbarch_use_struct_convention (gdbarch
,
5663 mips_eabi_use_struct_convention
);
5665 case MIPS_ABI_EABI64
:
5666 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5667 set_gdbarch_deprecated_store_return_value (gdbarch
,
5668 mips_eabi_store_return_value
);
5669 set_gdbarch_deprecated_extract_return_value (gdbarch
,
5670 mips_eabi_extract_return_value
);
5671 tdep
->mips_default_abi_regsize
= 8;
5672 tdep
->mips_default_stack_argsize
= 8;
5673 tdep
->mips_fp_register_double
= 1;
5674 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5675 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5676 tdep
->default_mask_address_p
= 0;
5677 set_gdbarch_long_bit (gdbarch
, 64);
5678 set_gdbarch_ptr_bit (gdbarch
, 64);
5679 set_gdbarch_long_long_bit (gdbarch
, 64);
5680 set_gdbarch_deprecated_reg_struct_has_addr
5681 (gdbarch
, mips_eabi_reg_struct_has_addr
);
5682 set_gdbarch_use_struct_convention (gdbarch
,
5683 mips_eabi_use_struct_convention
);
5686 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5687 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5688 tdep
->mips_default_abi_regsize
= 8;
5689 tdep
->mips_default_stack_argsize
= 8;
5690 tdep
->mips_fp_register_double
= 1;
5691 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5692 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5693 tdep
->default_mask_address_p
= 0;
5694 set_gdbarch_long_bit (gdbarch
, 32);
5695 set_gdbarch_ptr_bit (gdbarch
, 32);
5696 set_gdbarch_long_long_bit (gdbarch
, 64);
5699 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5700 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5701 tdep
->mips_default_abi_regsize
= 8;
5702 tdep
->mips_default_stack_argsize
= 8;
5703 tdep
->mips_fp_register_double
= 1;
5704 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5705 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5706 tdep
->default_mask_address_p
= 0;
5707 set_gdbarch_long_bit (gdbarch
, 64);
5708 set_gdbarch_ptr_bit (gdbarch
, 64);
5709 set_gdbarch_long_long_bit (gdbarch
, 64);
5712 internal_error (__FILE__
, __LINE__
, "unknown ABI in switch");
5715 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
5716 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
5719 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
5720 flag in object files because to do so would make it impossible to
5721 link with libraries compiled without "-gp32". This is
5722 unnecessarily restrictive.
5724 We could solve this problem by adding "-gp32" multilibs to gcc,
5725 but to set this flag before gcc is built with such multilibs will
5726 break too many systems.''
5728 But even more unhelpfully, the default linker output target for
5729 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
5730 for 64-bit programs - you need to change the ABI to change this,
5731 and not all gcc targets support that currently. Therefore using
5732 this flag to detect 32-bit mode would do the wrong thing given
5733 the current gcc - it would make GDB treat these 64-bit programs
5734 as 32-bit programs by default. */
5736 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
5737 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
5738 set_gdbarch_read_sp (gdbarch
, mips_read_sp
);
5740 /* Add/remove bits from an address. The MIPS needs be careful to
5741 ensure that all 32 bit addresses are sign extended to 64 bits. */
5742 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
5744 /* Unwind the frame. */
5745 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
5746 set_gdbarch_unwind_dummy_id (gdbarch
, mips_unwind_dummy_id
);
5748 /* Map debug register numbers onto internal register numbers. */
5749 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
5750 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
5751 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5752 set_gdbarch_dwarf_reg_to_regnum (gdbarch
,
5753 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5754 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
5755 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5756 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
5758 /* MIPS version of CALL_DUMMY */
5760 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
5761 replaced by a command, and all targets will default to on stack
5762 (regardless of the stack's execute status). */
5763 set_gdbarch_call_dummy_location (gdbarch
, AT_SYMBOL
);
5764 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
5766 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
5767 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
5768 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
5770 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
5771 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
5773 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
5775 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
5776 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
5777 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
5779 set_gdbarch_register_type (gdbarch
, mips_register_type
);
5781 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
5782 set_gdbarch_deprecated_pc_in_sigtramp (gdbarch
, mips_pc_in_sigtramp
);
5784 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
5786 /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT,
5787 HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT
5788 need to all be folded into the target vector. Since they are
5789 being used as guards for STOPPED_BY_WATCHPOINT, why not have
5790 STOPPED_BY_WATCHPOINT return the type of watchpoint that the code
5792 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
5794 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_stub
);
5796 /* NOTE drow/2004-02-11: We overload the core solib trampoline code
5797 to support MIPS16. This is a bad thing. Make sure not to do it
5798 if we have an OS ABI that actually supports shared libraries, since
5799 shared library support is more important. If we have an OS someday
5800 that supports both shared libraries and MIPS16, we'll have to find
5801 a better place for these. */
5802 if (info
.osabi
== GDB_OSABI_UNKNOWN
)
5804 set_gdbarch_in_solib_call_trampoline (gdbarch
, mips_in_call_stub
);
5805 set_gdbarch_in_solib_return_trampoline (gdbarch
, mips_in_return_stub
);
5808 /* Hook in OS ABI-specific overrides, if they have been registered. */
5809 gdbarch_init_osabi (info
, gdbarch
);
5811 /* Unwind the frame. */
5812 frame_unwind_append_sniffer (gdbarch
, mips_mdebug_frame_sniffer
);
5813 frame_base_append_sniffer (gdbarch
, mips_mdebug_frame_base_sniffer
);
5819 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
5821 struct gdbarch_info info
;
5823 /* Force the architecture to update, and (if it's a MIPS architecture)
5824 mips_gdbarch_init will take care of the rest. */
5825 gdbarch_info_init (&info
);
5826 gdbarch_update_p (info
);
5829 /* Print out which MIPS ABI is in use. */
5832 show_mips_abi (char *ignore_args
, int from_tty
)
5834 if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
!= bfd_arch_mips
)
5836 ("The MIPS ABI is unknown because the current architecture is not MIPS.\n");
5839 enum mips_abi global_abi
= global_mips_abi ();
5840 enum mips_abi actual_abi
= mips_abi (current_gdbarch
);
5841 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
5843 if (global_abi
== MIPS_ABI_UNKNOWN
)
5845 ("The MIPS ABI is set automatically (currently \"%s\").\n",
5847 else if (global_abi
== actual_abi
)
5849 ("The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
5853 /* Probably shouldn't happen... */
5855 ("The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n",
5856 actual_abi_str
, mips_abi_strings
[global_abi
]);
5862 mips_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
5864 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
5868 int ef_mips_32bitmode
;
5869 /* determine the ISA */
5870 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
5888 /* determine the size of a pointer */
5889 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
5890 fprintf_unfiltered (file
,
5891 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
5893 fprintf_unfiltered (file
,
5894 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
5896 fprintf_unfiltered (file
,
5897 "mips_dump_tdep: ef_mips_arch = %d\n",
5899 fprintf_unfiltered (file
,
5900 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
5901 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
5902 fprintf_unfiltered (file
,
5903 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
5904 mips_mask_address_p (tdep
),
5905 tdep
->default_mask_address_p
);
5907 fprintf_unfiltered (file
,
5908 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
5909 FP_REGISTER_DOUBLE
);
5910 fprintf_unfiltered (file
,
5911 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
5912 MIPS_DEFAULT_FPU_TYPE
,
5913 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
5914 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
5915 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
5917 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n", MIPS_EABI
);
5918 fprintf_unfiltered (file
,
5919 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
5921 (MIPS_FPU_TYPE
== MIPS_FPU_NONE
? "none"
5922 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
5923 : MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
5925 fprintf_unfiltered (file
,
5926 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
5927 FP_REGISTER_DOUBLE
);
5928 fprintf_unfiltered (file
,
5929 "mips_dump_tdep: mips_stack_argsize() = %d\n",
5930 mips_stack_argsize (tdep
));
5931 fprintf_unfiltered (file
, "mips_dump_tdep: A0_REGNUM = %d\n", A0_REGNUM
);
5932 fprintf_unfiltered (file
,
5933 "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n",
5934 XSTRING (ADDR_BITS_REMOVE (ADDR
)));
5935 fprintf_unfiltered (file
,
5936 "mips_dump_tdep: ATTACH_DETACH # %s\n",
5937 XSTRING (ATTACH_DETACH
));
5938 fprintf_unfiltered (file
,
5939 "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n",
5940 XSTRING (DWARF_REG_TO_REGNUM (REGNUM
)));
5941 fprintf_unfiltered (file
,
5942 "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n",
5943 XSTRING (ECOFF_REG_TO_REGNUM (REGNUM
)));
5944 fprintf_unfiltered (file
,
5945 "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n",
5946 FIRST_EMBED_REGNUM
);
5947 fprintf_unfiltered (file
,
5948 "mips_dump_tdep: IGNORE_HELPER_CALL # %s\n",
5949 XSTRING (IGNORE_HELPER_CALL (PC
)));
5950 fprintf_unfiltered (file
,
5951 "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n",
5952 XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC
, NAME
)));
5953 fprintf_unfiltered (file
,
5954 "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n",
5955 XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC
, NAME
)));
5956 fprintf_unfiltered (file
,
5957 "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n",
5959 #ifdef MACHINE_CPROC_FP_OFFSET
5960 fprintf_unfiltered (file
,
5961 "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n",
5962 MACHINE_CPROC_FP_OFFSET
);
5964 #ifdef MACHINE_CPROC_PC_OFFSET
5965 fprintf_unfiltered (file
,
5966 "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n",
5967 MACHINE_CPROC_PC_OFFSET
);
5969 #ifdef MACHINE_CPROC_SP_OFFSET
5970 fprintf_unfiltered (file
,
5971 "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n",
5972 MACHINE_CPROC_SP_OFFSET
);
5974 fprintf_unfiltered (file
,
5975 "mips_dump_tdep: MIPS16_INSTLEN = %d\n",
5977 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n");
5978 fprintf_unfiltered (file
,
5979 "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n");
5980 fprintf_unfiltered (file
,
5981 "mips_dump_tdep: MIPS_INSTLEN = %d\n", MIPS_INSTLEN
);
5982 fprintf_unfiltered (file
,
5983 "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n",
5984 MIPS_LAST_ARG_REGNUM
,
5985 MIPS_LAST_ARG_REGNUM
- A0_REGNUM
+ 1);
5986 fprintf_unfiltered (file
,
5987 "mips_dump_tdep: MIPS_NUMREGS = %d\n", MIPS_NUMREGS
);
5988 fprintf_unfiltered (file
,
5989 "mips_dump_tdep: mips_abi_regsize() = %d\n",
5990 mips_abi_regsize (tdep
));
5991 fprintf_unfiltered (file
,
5992 "mips_dump_tdep: PRID_REGNUM = %d\n", PRID_REGNUM
);
5993 fprintf_unfiltered (file
,
5994 "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n");
5995 fprintf_unfiltered (file
,
5996 "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n");
5997 fprintf_unfiltered (file
,
5998 "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n");
5999 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_FRAME_REG = function?\n");
6000 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_FREG_MASK = function?\n");
6001 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_FREG_OFFSET = function?\n");
6002 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_HIGH_ADDR = function?\n");
6003 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_LOW_ADDR = function?\n");
6004 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_PC_REG = function?\n");
6005 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_REG_MASK = function?\n");
6006 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_REG_OFFSET = function?\n");
6007 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_SYMBOL = function?\n");
6008 fprintf_unfiltered (file
, "mips_dump_tdep: PS_REGNUM = %d\n", PS_REGNUM
);
6009 fprintf_unfiltered (file
, "mips_dump_tdep: RA_REGNUM = %d\n", RA_REGNUM
);
6011 fprintf_unfiltered (file
,
6012 "mips_dump_tdep: SAVED_BYTES = %d\n", SAVED_BYTES
);
6015 fprintf_unfiltered (file
, "mips_dump_tdep: SAVED_FP = %d\n", SAVED_FP
);
6018 fprintf_unfiltered (file
, "mips_dump_tdep: SAVED_PC = %d\n", SAVED_PC
);
6020 fprintf_unfiltered (file
,
6021 "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n",
6022 XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS
, ARGS
)));
6023 fprintf_unfiltered (file
,
6024 "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n");
6025 fprintf_unfiltered (file
,
6026 "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n",
6027 XSTRING (SKIP_TRAMPOLINE_CODE (PC
)));
6028 fprintf_unfiltered (file
,
6029 "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n",
6030 XSTRING (SOFTWARE_SINGLE_STEP (SIG
, BP_P
)));
6031 fprintf_unfiltered (file
,
6032 "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n",
6033 SOFTWARE_SINGLE_STEP_P ());
6034 fprintf_unfiltered (file
,
6035 "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n",
6036 XSTRING (STAB_REG_TO_REGNUM (REGNUM
)));
6037 #ifdef STACK_END_ADDR
6038 fprintf_unfiltered (file
,
6039 "mips_dump_tdep: STACK_END_ADDR = %d\n",
6042 fprintf_unfiltered (file
,
6043 "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n",
6044 XSTRING (STEP_SKIPS_DELAY (PC
)));
6045 fprintf_unfiltered (file
,
6046 "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n",
6047 STEP_SKIPS_DELAY_P
);
6048 fprintf_unfiltered (file
,
6049 "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n",
6050 XSTRING (STOPPED_BY_WATCHPOINT (WS
)));
6051 fprintf_unfiltered (file
, "mips_dump_tdep: T9_REGNUM = %d\n", T9_REGNUM
);
6052 fprintf_unfiltered (file
,
6053 "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n");
6054 fprintf_unfiltered (file
,
6055 "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n",
6056 XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT
6057 (TYPE
, CNT
, OTHERTYPE
)));
6058 fprintf_unfiltered (file
,
6059 "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n",
6060 XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS
));
6062 fprintf_unfiltered (file
,
6063 "mips_dump_tdep: TRACE_CLEAR # %s\n",
6064 XSTRING (TRACE_CLEAR (THREAD
, STATE
)));
6067 fprintf_unfiltered (file
,
6068 "mips_dump_tdep: TRACE_FLAVOR = %d\n", TRACE_FLAVOR
);
6070 #ifdef TRACE_FLAVOR_SIZE
6071 fprintf_unfiltered (file
,
6072 "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n",
6076 fprintf_unfiltered (file
,
6077 "mips_dump_tdep: TRACE_SET # %s\n",
6078 XSTRING (TRACE_SET (X
, STATE
)));
6080 #ifdef UNUSED_REGNUM
6081 fprintf_unfiltered (file
,
6082 "mips_dump_tdep: UNUSED_REGNUM = %d\n", UNUSED_REGNUM
);
6084 fprintf_unfiltered (file
, "mips_dump_tdep: V0_REGNUM = %d\n", V0_REGNUM
);
6085 fprintf_unfiltered (file
,
6086 "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n",
6087 (long) VM_MIN_ADDRESS
);
6088 fprintf_unfiltered (file
,
6089 "mips_dump_tdep: ZERO_REGNUM = %d\n", ZERO_REGNUM
);
6090 fprintf_unfiltered (file
,
6091 "mips_dump_tdep: _PROC_MAGIC_ = %d\n", _PROC_MAGIC_
);
6094 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
6097 _initialize_mips_tdep (void)
6099 static struct cmd_list_element
*mipsfpulist
= NULL
;
6100 struct cmd_list_element
*c
;
6102 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
6103 if (MIPS_ABI_LAST
+ 1
6104 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
6105 internal_error (__FILE__
, __LINE__
, "mips_abi_strings out of sync");
6107 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
6109 mips_pdr_data
= register_objfile_data ();
6111 /* Add root prefix command for all "set mips"/"show mips" commands */
6112 add_prefix_cmd ("mips", no_class
, set_mips_command
,
6113 "Various MIPS specific commands.",
6114 &setmipscmdlist
, "set mips ", 0, &setlist
);
6116 add_prefix_cmd ("mips", no_class
, show_mips_command
,
6117 "Various MIPS specific commands.",
6118 &showmipscmdlist
, "show mips ", 0, &showlist
);
6120 /* Allow the user to override the saved register size. */
6121 add_show_from_set (add_set_enum_cmd ("saved-gpreg-size",
6124 &mips_abi_regsize_string
, "\
6125 Set size of general purpose registers saved on the stack.\n\
6126 This option can be set to one of:\n\
6127 32 - Force GDB to treat saved GP registers as 32-bit\n\
6128 64 - Force GDB to treat saved GP registers as 64-bit\n\
6129 auto - Allow GDB to use the target's default setting or autodetect the\n\
6130 saved GP register size from information contained in the executable.\n\
6131 (default: auto)", &setmipscmdlist
), &showmipscmdlist
);
6133 /* Allow the user to override the argument stack size. */
6134 add_show_from_set (add_set_enum_cmd ("stack-arg-size",
6137 &mips_stack_argsize_string
, "\
6138 Set the amount of stack space reserved for each argument.\n\
6139 This option can be set to one of:\n\
6140 32 - Force GDB to allocate 32-bit chunks per argument\n\
6141 64 - Force GDB to allocate 64-bit chunks per argument\n\
6142 auto - Allow GDB to determine the correct setting from the current\n\
6143 target and executable (default)", &setmipscmdlist
), &showmipscmdlist
);
6145 /* Allow the user to override the ABI. */
6146 c
= add_set_enum_cmd
6147 ("abi", class_obscure
, mips_abi_strings
, &mips_abi_string
,
6148 "Set the ABI used by this program.\n"
6149 "This option can be set to one of:\n"
6150 " auto - the default ABI associated with the current binary\n"
6152 " o64\n" " n32\n" " n64\n" " eabi32\n" " eabi64", &setmipscmdlist
);
6153 set_cmd_sfunc (c
, mips_abi_update
);
6154 add_cmd ("abi", class_obscure
, show_mips_abi
,
6155 "Show ABI in use by MIPS target", &showmipscmdlist
);
6157 /* Let the user turn off floating point and set the fence post for
6158 heuristic_proc_start. */
6160 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
6161 "Set use of MIPS floating-point coprocessor.",
6162 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
6163 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
6164 "Select single-precision MIPS floating-point coprocessor.",
6166 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
6167 "Select double-precision MIPS floating-point coprocessor.",
6169 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
6170 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
6171 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
6172 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
6173 "Select no MIPS floating-point coprocessor.", &mipsfpulist
);
6174 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
6175 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
6176 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
6177 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
6178 "Select MIPS floating-point coprocessor automatically.",
6180 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
6181 "Show current use of MIPS floating-point coprocessor target.",
6184 /* We really would like to have both "0" and "unlimited" work, but
6185 command.c doesn't deal with that. So make it a var_zinteger
6186 because the user can always use "999999" or some such for unlimited. */
6187 c
= add_set_cmd ("heuristic-fence-post", class_support
, var_zinteger
,
6188 (char *) &heuristic_fence_post
, "\
6189 Set the distance searched for the start of a function.\n\
6190 If you are debugging a stripped executable, GDB needs to search through the\n\
6191 program for the start of a function. This command sets the distance of the\n\
6192 search. The only need to set it is when debugging a stripped executable.", &setlist
);
6193 /* We need to throw away the frame cache when we set this, since it
6194 might change our ability to get backtraces. */
6195 set_cmd_sfunc (c
, reinit_frame_cache_sfunc
);
6196 add_show_from_set (c
, &showlist
);
6198 /* Allow the user to control whether the upper bits of 64-bit
6199 addresses should be zeroed. */
6200 add_setshow_auto_boolean_cmd ("mask-address", no_class
, &mask_address_var
, "\
6201 Set zeroing of upper 32 bits of 64-bit addresses.\n\
6202 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
6203 allow GDB to determine the correct value.\n", "\
6204 Show zeroing of upper 32 bits of 64-bit addresses.",
6205 NULL
, show_mask_address
, &setmipscmdlist
, &showmipscmdlist
);
6207 /* Allow the user to control the size of 32 bit registers within the
6208 raw remote packet. */
6209 add_setshow_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
6210 var_boolean
, &mips64_transfers_32bit_regs_p
, "\
6211 Set compatibility with 64-bit MIPS targets that transfer 32-bit quantities.\n\
6212 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6213 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6214 64 bits for others. Use \"off\" to disable compatibility mode", "\
6215 Show compatibility with 64-bit MIPS targets that transfer 32-bit quantities.\n\
6216 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6217 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6218 64 bits for others. Use \"off\" to disable compatibility mode", set_mips64_transfers_32bit_regs
, NULL
, &setlist
, &showlist
);
6220 /* Debug this files internals. */
6221 add_show_from_set (add_set_cmd ("mips", class_maintenance
, var_zinteger
,
6222 &mips_debug
, "Set mips debugging.\n\
6223 When non-zero, mips specific debugging is enabled.", &setdebuglist
), &showdebuglist
);